Skip to content

Latest commit

 

History

History
17 lines (9 loc) · 442 Bytes

README.md

File metadata and controls

17 lines (9 loc) · 442 Bytes

Project List

Lab 1: Verilog - ADDing and ANDing on De1-SoC

Lab 3: Verilog - Tic-Tac-Toe, Player vs CPU

Lab 5: Verilog - Datapath of Lab 8

Lab 6: Verilog - Finite State Machine Controller for Lab 8

Lab 7: Verilog - Memory and I/O for Lab 8

Lab 8: Verilog - Simple RISC Machine

Lab 9: ARM Assembly - Recursive Binary Search

Lab 10: ARM Assembly - Interrupts and Preemptive Multitasking