Hyper-Acceleration Cards in devices other than ME IO Ports

[NotMyWing]

The current acceleration ratio is 16/128/1024 with ME IO Ports taking up to 3 cards, mixing and matching with the default Acceleration Cards.

If one could put HACs into devices like ME Import/Export Buses, Inscribers or Molecular Assemblers, what would the acceleration rates be?

Looking for some feedback.

[Niels1006]

I don't think we'd need HAC for import/export busses, since interfaces are superior with their 512 cap each slot.

For inscribers it depends on the cost/gating of HACs, if there won't be any custom recipes in greg machines id say one ticking the recipes would be nice, but that needs gating imo.

And molass already oneticks, no? If not, making it onetick seems like a good idea. Or even parallel, but that's probably not really easy to implement.

[yuanju-qwq]

But the fluid interface can only do 24B per tick, which is obviously not very sufficient.

[Niels1006]

But the fluid interface can only do 24B per tick, which is obviously not very sufficient.

Wrong, you can use capacity cards so each slot has 64B capacity.

[CactusCool]

Wrong, you can use capacity cards so each slot has 64B capacity.

yes but its still very lacking a maxed interface does 576,000mb per tick while hyper export fluid in gtnh does close to 10,000,000mb per tick. while 567,000 is a lot its insufficient for things like tj nuclear.

[Niels1006]

Wrong, you can use capacity cards so each slot has 64B capacity.

yes but its still very lacking a maxed interface does 576,000mb per tick while hyper export fluid in gtnh does close to 10,000,000mb per tick. while 567,000 is a lot its insufficient for things like tj nuclear.

Its more than enough for tj nuc, huh?