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How to Describe Bitfields That Span Multiple Registers in CMSIS-SVD #1590
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Hi, does the register have a 32bit representation (means, all three (four) can be read as one 32bit register having the upper 8 bit "reserved")? In this case you can use both descriptions (1x 32bit, 3x 8bit) as alternate specification ("union concept"). |
Please note that CMSIS-SVD spec has moved to https://github.com/Open-CMSIS-Pack/svd-spec. |
Hi @thorstendb-ARM, The register doesn't have a 32 bit representation only the multiple 8 bit representations. I need to know the schema used for naming the LSB register starts with _1 and up to _3. |
Hi @bordeaux15, I suggest to move this discussion to https://github.com/Open-CMSIS-Pack/svd-spec. Cheers, |
Can you please give an example how you would describe this in C with struct and union? Note: SVDConv does currently not support virtual registers that gather information from (several) other registers. The tool is meant to reproduce the physical structure of the peripheral layout, which is then used e.g. for C headerfile generation or displaying tools. |
I'm working on a project where bitfields can span multiple registers (i.e. 8-bit registers, 23-bit bitfields across 3 registers). Example below:
I don't see any where in the CMSIS-SVD 1.3.9 schema that can support this structure. The bitRange identifier is used only to specify a bitfields range within a register. But it cannot specify which bits of the bitfields are included in that bitRange. A couple questions:
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