acs_pcie.c needs reads added to preserve memory ordering

[cdwilde]

acs_pcie.c has many PCIe writes. During testing, we ran into an issue where a disable and enable got out of order. This is because writes in PCIe can go out of order. To ensure that this doesn't happen, we can add a read after each write to ensure ordering.

/* Set SERR# Enable bit in the Command Register to enable reporting

• upstream of Non-fatal and Fatal errors detected by the Function.
  */
  val_pcie_read_cfg(bdf, TYPE01_CR, &reg_value);
  dis_mask = (1 << CR_SERRE_SHIFT);
  val_pcie_write_cfg(bdf, TYPE01_CR, reg_value | dis_mask);
  val_pcie_read_cfg(bdf, TYPE01_CR, &reg_value);