diff --git a/projects.yaml b/projects.yaml index 019b317a7..55195e26c 100644 --- a/projects.yaml +++ b/projects.yaml @@ -494,6 +494,10 @@ projects: - *module_if - *module_hic_m48ssidae - records/board/numaker_iot_m263a.yaml + m48ssidae_numaker_iot_m467_if: + - *module_if + - *module_hic_m48ssidae + - records/board/numaker_iot_m467.yaml m48ssidae_numaker_m2354_if: - *module_if - *module_hic_m48ssidae diff --git a/records/board/numaker_iot_m467.yaml b/records/board/numaker_iot_m467.yaml new file mode 100644 index 000000000..321ae6283 --- /dev/null +++ b/records/board/numaker_iot_m467.yaml @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/numaker_iot_m467.c + family: + - source/family/nuvoton/m467hjhae/target.c diff --git a/records/hic_hal/m48ssidae.yaml b/records/hic_hal/m48ssidae.yaml index 4763d6de7..c651e379c 100644 --- a/records/hic_hal/m48ssidae.yaml +++ b/records/hic_hal/m48ssidae.yaml @@ -22,6 +22,9 @@ common: tool_specific: uvision: misc: + asm_flags: + - -I../../../source/daplink + - -I../../../source/hic_hal/nuvoton/m48ssidae ld_flags: - --predefine="-I..\..\..\source\hic_hal\nuvoton\m48ssidae" sources: @@ -31,12 +34,18 @@ tool_specific: misc: asm_flags: - --no_unaligned_access + - -I../../../source/daplink + - -I../../../source/hic_hal/nuvoton/m48ssidae c_flags: - --no_unaligned_access sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc armclang: + misc: + asm_flags: + - -I../../../source/daplink + - -I../../../source/hic_hal/nuvoton/m48ssidae sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc diff --git a/source/board/numaker_iot_m467.c b/source/board/numaker_iot_m467.c new file mode 100644 index 000000000..0098447bb --- /dev/null +++ b/source/board/numaker_iot_m467.c @@ -0,0 +1,33 @@ +/** + * @file numaker_iot_m467.c + * @brief board ID for the Nuvoton NuMaker-IoT-M467 board + * + * DAPLink Interface Firmware + * Copyright (c) 2022 Nuvoton Technology Corp. All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_family.h" +#include "target_board.h" + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "1313", + .family_id = kStub_SWSysReset_FamilyID, + .flags = kEnablePageErase, + .target_cfg = &target_device, + .board_vendor = "Nuvoton", + .board_name = "NuMaker-IoT-M467", +}; diff --git a/source/daplink/settings/settings.c b/source/daplink/settings/settings.c index 6553e18f6..645da480d 100644 --- a/source/daplink/settings/settings.c +++ b/source/daplink/settings/settings.c @@ -66,7 +66,7 @@ typedef struct __attribute__((__packed__)) cfg_ram { COMPILER_ASSERT((offsetof(cfg_ram_t, hexdump) % sizeof(uint32_t)) == 0); // Configuration RAM -#if defined(__ARMCC) +#if defined(__CC_ARM) static cfg_ram_t config_ram __attribute__((section("cfgram"), zero_init)); #else static cfg_ram_t config_ram __attribute__((section("cfgram"))); diff --git a/source/family/nuvoton/m467hjhae/flash_blob.c b/source/family/nuvoton/m467hjhae/flash_blob.c new file mode 100644 index 000000000..a1c38c224 --- /dev/null +++ b/source/family/nuvoton/m467hjhae/flash_blob.c @@ -0,0 +1,106 @@ +/* Flash OS Routines (Automagically Generated) + * Copyright (c) 2022 Nuvoton Technology Corp + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +static const uint32_t flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x4770ba40, 0x4770bac0, 0x2000b5fe, 0x21009002, 0x680048fc, 0x0d000400, 0x26619002, 0x98020176, + 0xd10a42b0, 0x6bc048f8, 0x42b04ef8, 0x0780d101, 0x2005e001, 0x46010700, 0x4ef5e00e, 0x42b09802, + 0x0701d101, 0x2669e008, 0x98020176, 0xd10142b0, 0xe0010641, 0xbdfe2001, 0x2001460a, 0x180b0700, + 0x34ff1dcc, 0x462034fa, 0x07362601, 0x20031985, 0x18080380, 0x20039001, 0x18080380, 0x90001980, + 0x40304678, 0xd0012800, 0xe0004618, 0x30ff4610, 0x68003001, 0x0fc007c0, 0xd1372800, 0x26014678, + 0x40300736, 0xd0012800, 0xe0004618, 0x26594610, 0x300130ff, 0x46786006, 0x07362601, 0x28004030, + 0x4618d001, 0x4610e000, 0x30ff2616, 0x60063001, 0x26014678, 0x40300736, 0xd0012800, 0xe0004618, + 0x26884610, 0x300130ff, 0x46786006, 0x40300676, 0xd0012800, 0xe0004618, 0x30ff4610, 0x68003001, + 0x0fc007c0, 0xd1012800, 0xe7a42001, 0x2701467e, 0x403e073f, 0xd0012e00, 0xe000462e, 0x46304626, + 0x27046836, 0x6006433e, 0x06bf467e, 0x2e00403e, 0x462ed001, 0x4626e000, 0x68761d30, 0x433e2704, + 0xbf006006, 0x26014678, 0x40300736, 0xd0012800, 0xe0004628, 0x6d004620, 0x40302610, 0xd0f12800, + 0x2701467e, 0x403e073f, 0xd0012e00, 0xe0009e00, 0x46309e01, 0x272d6836, 0x6006433e, 0x26014678, + 0x40300736, 0xd0012800, 0xe0009800, 0x68009801, 0x0fc007c0, 0xd1012800, 0xe75c2001, 0xe75a2000, + 0x4605b578, 0x90002000, 0x48962100, 0x04006800, 0x90000d00, 0x01642461, 0x42a09800, 0x4892d10a, + 0x4c926bc0, 0xd10142a0, 0xe0010780, 0x07002005, 0xe00e4601, 0x98004c8e, 0xd10142a0, 0xe0080701, + 0x01642469, 0x42a09800, 0x0641d101, 0x2001e001, 0x2003bd78, 0x180a0380, 0x24011808, 0x19030724, + 0x2601467c, 0x40340736, 0xd0012c00, 0xe000461c, 0x46204614, 0x08646824, 0x60040064, 0xe7e72000, + 0x4601b5f8, 0x20002300, 0x22009000, 0x68004875, 0x0d000400, 0x26619000, 0x98000176, 0xd10a42b0, + 0x6bc04871, 0x42b04e71, 0x0780d101, 0x2005e001, 0x46020700, 0x4e6ee00e, 0x42b09800, 0x0702d101, + 0x2669e008, 0x98000176, 0xd10142b0, 0xe0010642, 0xbdf82001, 0x03802003, 0x18101814, 0x07362601, + 0x46081985, 0x460143b0, 0x0500200f, 0x11f64008, 0xd10042b0, 0x467e2301, 0x073f2701, 0x2e00403e, + 0x462ed001, 0x4626e000, 0x68364630, 0x433e2740, 0x46786006, 0x403005be, 0xd0012800, 0xe0004628, + 0x26224620, 0x467860c6, 0x403006f6, 0xd0012800, 0xe0004628, 0x60414620, 0xd10c2b00, 0x26014678, + 0x40300736, 0xd0012800, 0xe0004628, 0x26004620, 0x608643f6, 0x4678e00a, 0x07362601, 0x28004030, + 0x4628d001, 0x4620e000, 0x60864e42, 0x26014678, 0x40300736, 0xd0012800, 0xe0004628, 0x26014620, + 0xf3bf6106, 0xbf008f6f, 0x26014678, 0x40300736, 0xd0012800, 0xe0004628, 0x69004620, 0x0fc007c0, + 0xd1f12800, 0x26014678, 0x40300736, 0xd0012800, 0xe0004628, 0x68004620, 0x40302640, 0xd00f2800, + 0x2701467e, 0x403e073f, 0xd0012e00, 0xe000462e, 0x46304626, 0x27406836, 0x6006433e, 0xe7782001, + 0xe7762000, 0x4603b5fc, 0x90012000, 0x481d2400, 0x04006800, 0x90010d00, 0x01762661, 0x42b09801, + 0x4819d10a, 0x4e196bc0, 0xd10142b0, 0xe0010780, 0x07002005, 0xe00e4604, 0x98014e15, 0xd10142b0, + 0xe0080704, 0x01762669, 0x42b09801, 0x0644d101, 0x2001e001, 0x2003bdfc, 0x18250380, 0x26011820, + 0x19800736, 0x1cc89000, 0x00890881, 0x43b04618, 0x467e4603, 0x073f2701, 0x2e00403e, 0x9e00d00c, + 0x0000e00b, 0xe000ed00, 0x40003fc0, 0x20171011, 0x00000c24, 0x0055aa03, 0x4630462e, 0x27406836, + 0x6006433e, 0x05be4678, 0x28004030, 0x9800d001, 0x4628e000, 0x60c62621, 0x4678e051, 0x07362601, + 0x28004030, 0x9800d001, 0x4628e000, 0x46786043, 0x07362601, 0x28004030, 0x9800d001, 0x4628e000, + 0x60866816, 0x26014678, 0x40300736, 0xd0012800, 0xe0009800, 0x26014628, 0xf3bf6106, 0xbf008f6f, + 0x26014678, 0x40300736, 0xd0012800, 0xe0009800, 0x69004628, 0x0fc007c0, 0xd1f12800, 0x26014678, + 0x40300736, 0xd0012800, 0xe0009800, 0x68004628, 0x40302640, 0xd00f2800, 0x2701467e, 0x403e073f, + 0xd0012e00, 0xe0009e00, 0x4630462e, 0x27406836, 0x6006433e, 0xe77d2001, 0x1d121d1b, 0x29001f09, + 0x2000d1ab, 0xb5fce776, 0x20004603, 0x24009001, 0x68004852, 0x0d000400, 0x26619001, 0x98010176, + 0xd10a42b0, 0x6bc0484e, 0x42b04e4e, 0x0780d101, 0x2005e001, 0x46040700, 0x4e4be00e, 0x42b09801, + 0x0704d101, 0x2669e008, 0x98010176, 0xd10142b0, 0xe0010644, 0xbdfc2001, 0x03802003, 0x18201825, + 0x07362601, 0x90001980, 0x08811cc8, 0x46180089, 0x460343b0, 0x2701467e, 0x403e073f, 0xd0012e00, + 0xe0009e00, 0x4630462e, 0x27406836, 0x6006433e, 0x05be4678, 0x28004030, 0x9800d001, 0x4628e000, + 0x60c62600, 0x4678e055, 0x07362601, 0x28004030, 0x9800d001, 0x4628e000, 0x46786043, 0x07362601, + 0x28004030, 0x9800d001, 0x4628e000, 0x61062601, 0x8f6ff3bf, 0x4678bf00, 0x07362601, 0x28004030, + 0x9800d001, 0x4628e000, 0x07c06900, 0x28000fc0, 0x4678d1f1, 0x07362601, 0x28004030, 0x9800d001, + 0x4628e000, 0x26406800, 0x28004030, 0x467ed00f, 0x073f2701, 0x2e00403e, 0x9e00d001, 0x462ee000, + 0x68364630, 0x433e2740, 0x20016006, 0x4678e793, 0x07362601, 0x28004030, 0x9800d001, 0x4628e000, + 0x68166880, 0xd00142b0, 0xe7842001, 0x1d121d1b, 0x29001f09, 0x2000d1a7, 0x0000e77d, 0xe000ed00, + 0x40003fc0, 0x20171011, 0x00000c24, 0x00000000 +}; + +/** +* List of start and size for each size of flash sector - even indexes are start, odd are size +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address flash_start + flash_size. +*/ +static const sector_info_t sectors_info[] = { + { 0x00000000, 0x00001000 }, + { 0x0F100000, 0x00001000 }, +}; + +static const program_target_t flash = { + 0x20000029, // Init + 0x200001c1, // UnInit + 0x0, // EraseChip + 0x20000241, // EraseSector + 0x200003a5, // ProgramPage + 0x20000507, // Verify + + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + { + 0x20000001, + 0x2000066c, + 0x20000900 + }, + + 0x20000000 + 0x00000A00, // mem buffer location + 0x20000000, // location to write prog_blob in target RAM + sizeof(flash_prog_blob), // prog_blob size + flash_prog_blob, // address of prog_blob + 0x00001000 // ram_to_flash_bytes_to_be_written +}; diff --git a/source/family/nuvoton/m467hjhae/target.c b/source/family/nuvoton/m467hjhae/target.c new file mode 100644 index 000000000..4ce9a2ced --- /dev/null +++ b/source/family/nuvoton/m467hjhae/target.c @@ -0,0 +1,43 @@ +/** + * @file target.c + * @brief Target information for the m467hjhae + * + * DAPLink Interface Firmware + * Copyright (c) 2022 Nuvoton Technology Corp. All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" + +// The file flash_blob.c must only be included in target.c +#include "flash_blob.c" + +// target information +target_cfg_t target_device = { + .version = kTargetConfigVersion, + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = 0x00000000, + .flash_regions[0].end = 0x00100000, + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *)&flash, + .flash_regions[1].start = 0x0F100000, + .flash_regions[1].end = 0x0F102000, + .flash_regions[1].flash_algo = (program_target_t *)&flash, + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x20080000, + .target_vendor = "Nuvoton", + .target_part_number = "M467HJHAE", +}; diff --git a/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s b/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s index 4bdd57cc6..aed188ea5 100644 --- a/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s +++ b/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s @@ -31,13 +31,15 @@ ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ;*/ +#include "daplink_addr.h" +#include "daplink_defaults.h" ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; IF :LNOT: :DEF: Stack_Size -Stack_Size EQU 0x00006000 +Stack_Size EQU DAPLINK_STACK_SIZE ENDIF AREA STACK, NOINIT, READWRITE, ALIGN=3 @@ -50,7 +52,7 @@ __initial_sp ; IF :LNOT: :DEF: Heap_Size -Heap_Size EQU 0x00000100 +Heap_Size EQU DAPLINK_HEAP_SIZE ENDIF AREA HEAP, NOINIT, READWRITE, ALIGN=3 diff --git a/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S b/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S index f0de23ea2..13e04addb 100644 --- a/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S +++ b/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S @@ -1,11 +1,9 @@ /** - * @file startup_MK20D5.s + * @file startup_M480.s * @brief * * DAPLink Interface Firmware - * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2017 NXP - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2022 Nuvoton Technology Corp. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -20,149 +18,252 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ + .syntax unified .arch armv7-m .section .isr_vector, "a" - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ - .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ - .long DAPLINK_VERSION /* DAPLINK: Version*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF) */ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility */ + .long DAPLINK_VERSION /* DAPLINK: Version */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long g_board_info /* DAPLINK: Pointer to board/family/target info */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ - /* External Interrupts*/ - .long BOD_IRQHandler /* 0: Brown Out detection */ - .long IRC_IRQHandler /* 1: Internal RC */ - .long PWRWU_IRQHandler /* 2: Power down wake up */ - .long RAMPE_IRQHandler /* 3: RAM parity error */ - .long CKFAIL_IRQHandler /* 4: Clock detection fail */ - .long Reserved0_Handler /* 5: Reserved */ - .long RTC_IRQHandler /* 6: Real Time Clock */ - .long TAMPER_IRQHandler /* 7: Tamper detection */ - .long WDT_IRQHandler /* 8: Watchdog timer */ - .long WWDT_IRQHandler /* 9: Window watchdog timer */ - .long EINT0_IRQHandler /* 10: External Input 0 */ - .long EINT1_IRQHandler /* 11: External Input 1 */ - .long EINT2_IRQHandler /* 12: External Input 2 */ - .long EINT3_IRQHandler /* 13: External Input 3 */ - .long EINT4_IRQHandler /* 14: External Input 4 */ - .long EINT5_IRQHandler /* 15: External Input 5 */ - .long GPA_IRQHandler /* 16: GPIO Port A */ - .long GPB_IRQHandler /* 17: GPIO Port B */ - .long GPC_IRQHandler /* 18: GPIO Port C */ - .long GPD_IRQHandler /* 19: GPIO Port D */ - .long GPE_IRQHandler /* 20: GPIO Port E */ - .long GPF_IRQHandler /* 21: GPIO Port F */ - .long QSPI0_IRQHandler /* 22: QSPI0 */ - .long SPI0_IRQHandler /* 23: SPI0 */ - .long BRAKE0_IRQHandler /* 24: */ - .long EPWM0P0_IRQHandler /* 25: */ - .long EPWM0P1_IRQHandler /* 26: */ - .long EPWM0P2_IRQHandler /* 27: */ - .long BRAKE1_IRQHandler /* 28: */ - .long EPWM1P0_IRQHandler /* 29: */ - .long EPWM1P1_IRQHandler /* 30: */ - .long EPWM1P2_IRQHandler /* 31: */ - .long TMR0_IRQHandler /* 32: Timer 0 */ - .long TMR1_IRQHandler /* 33: Timer 1 */ - .long TMR2_IRQHandler /* 34: Timer 2 */ - .long TMR3_IRQHandler /* 35: Timer 3 */ - .long UART0_IRQHandler /* 36: UART0 */ - .long UART1_IRQHandler /* 37: UART1 */ - .long I2C0_IRQHandler /* 38: I2C0 */ - .long I2C1_IRQHandler /* 39: I2C1 */ - .long PDMA_IRQHandler /* 40: Peripheral DMA */ - .long DAC_IRQHandler /* 41: DAC */ - .long ADC00_IRQHandler /* 42: ADC0 interrupt source 0 */ - .long ADC01_IRQHandler /* 43: ADC0 interrupt source 1 */ - .long ACMP01_IRQHandler /* 44: ACMP0 and ACMP1 */ - .long Reserved1_Handler /* 45: Reserved */ - .long ADC02_IRQHandler /* 46: ADC0 interrupt source 2 */ - .long ADC03_IRQHandler /* 47: ADC0 interrupt source 3 */ - .long UART2_IRQHandler /* 48: UART2 */ - .long UART3_IRQHandler /* 49: UART3 */ - .long Reserved2_Handler /* 50: Reserved */ - .long SPI1_IRQHandler /* 51: SPI1 */ - .long SPI2_IRQHandler /* 52: SPI2 */ - .long USBD_IRQHandler /* 53: USB device */ - .long OHCI_IRQHandler /* 54: OHCI */ - .long USBOTG_IRQHandler /* 55: USB OTG */ - .long CAN0_IRQHandler /* 56: CAN0 */ - .long CAN1_IRQHandler /* 57: CAN1 */ - .long SC0_IRQHandler /* 58: */ - .long SC1_IRQHandler /* 59: */ - .long SC2_IRQHandler /* 60: */ - .long Reserved3_Handler /* 61: */ - .long SPI3_IRQHandler /* 62: SPI3 */ - .long Reserved4_Handler /* 63: */ - .long SDH0_IRQHandler /* 64: SDH0 */ - .long USBD20_IRQHandler /* 65: USBD20 */ - .long EMAC_TX_IRQHandler /* 66: EMAC_TX */ - .long EMAC_RX_IRQHandler /* 67: EMAX_RX */ - .long I2S0_IRQHandler /* 68: I2S0 */ - .long Reserved5_Handler /* 69: ToDo: Add description to this Interrupt */ - .long OPA0_IRQHandler /* 70: OPA0 */ - .long CRYPTO_IRQHandler /* 71: CRYPTO */ - .long GPG_IRQHandler /* 72: */ - .long EINT6_IRQHandler /* 73: */ - .long UART4_IRQHandler /* 74: UART4 */ - .long UART5_IRQHandler /* 75: UART5 */ - .long USCI0_IRQHandler /* 76: USCI0 */ - .long USCI1_IRQHandler /* 77: USCI1 */ - .long BPWM0_IRQHandler /* 78: BPWM0 */ - .long BPWM1_IRQHandler /* 79: BPWM1 */ - .long SPIM_IRQHandler /* 80: SPIM */ - .long Reserved6_Handler /* 81: ToDo: Add description to this Interrupt */ - .long I2C2_IRQHandler /* 82: I2C2 */ - .long Reserved7_Handler /* 83: */ - .long QEI0_IRQHandler /* 84: QEI0 */ - .long QEI1_IRQHandler /* 85: QEI1 */ - .long ECAP0_IRQHandler /* 86: ECAP0 */ - .long ECAP1_IRQHandler /* 87: ECAP1 */ - .long GPH_IRQHandler /* 88: */ - .long EINT7_IRQHandler /* 89: */ - .long SDH1_IRQHandler /* 90: SDH1 */ - .long Reserved8_Handler /* 91: */ - .long EHCI_IRQHandler /* 92: EHCI */ - .long USBOTG20_IRQHandler /* 93: */ + /* External interrupts */ + .long BOD_IRQHandler /* 0: BOD */ + .long IRC_IRQHandler /* 1: IRC */ + .long PWRWU_IRQHandler /* 2: PWRWU */ + .long RAMPE_IRQHandler /* 3: RAMPE */ + .long CKFAIL_IRQHandler /* 4: CKFAIL */ + .long 0 /* 5: Reserved */ + .long RTC_IRQHandler /* 6: RTC */ + .long TAMPER_IRQHandler /* 7: TAMPER */ + .long WDT_IRQHandler /* 8: WDT */ + .long WWDT_IRQHandler /* 9: WWDT */ + .long EINT0_IRQHandler /* 10: EINT0 */ + .long EINT1_IRQHandler /* 11: EINT1 */ + .long EINT2_IRQHandler /* 12: EINT2 */ + .long EINT3_IRQHandler /* 13: EINT3 */ + .long EINT4_IRQHandler /* 14: EINT4 */ + .long EINT5_IRQHandler /* 15: EINT5 */ + .long GPA_IRQHandler /* 16: GPA */ + .long GPB_IRQHandler /* 17: GPB */ + .long GPC_IRQHandler /* 18: GPC */ + .long GPD_IRQHandler /* 19: GPD */ + .long GPE_IRQHandler /* 20: GPE */ + .long GPF_IRQHandler /* 21: GPF */ + .long QSPI0_IRQHandler /* 22: QSPI0 */ + .long SPI0_IRQHandler /* 23: SPI0 */ + .long BRAKE0_IRQHandler /* 24: BRAKE0 */ + .long EPWM0P0_IRQHandler /* 25: EPWM0P0 */ + .long EPWM0P1_IRQHandler /* 26: EPWM0P1 */ + .long EPWM0P2_IRQHandler /* 27: EPWM0P2 */ + .long BRAKE1_IRQHandler /* 28: BRAKE1 */ + .long EPWM1P0_IRQHandler /* 29: EPWM1P0 */ + .long EPWM1P1_IRQHandler /* 30: EPWM1P1 */ + .long EPWM1P2_IRQHandler /* 31: EPWM1P2 */ + .long TMR0_IRQHandler /* 32: TIMER0 */ + .long TMR1_IRQHandler /* 33: TIMER1 */ + .long TMR2_IRQHandler /* 34: TIMER2 */ + .long TMR3_IRQHandler /* 35: TIMER3 */ + .long UART0_IRQHandler /* 36: UART0 */ + .long UART1_IRQHandler /* 37: UART1 */ + .long I2C0_IRQHandler /* 38: I2C0 */ + .long I2C1_IRQHandler /* 39: I2C1 */ + .long PDMA_IRQHandler /* 40: PDMA */ + .long DAC_IRQHandler /* 41: DAC */ + .long ADC00_IRQHandler /* 42: ADC00 */ + .long ADC01_IRQHandler /* 43: ADC01 */ + .long ACMP01_IRQHandler /* 44: ACMP */ + .long 0 /* 45: Reserved */ + .long ADC02_IRQHandler /* 46: ADC02 */ + .long ADC03_IRQHandler /* 47: ADC03 */ + .long UART2_IRQHandler /* 48: UART2 */ + .long UART3_IRQHandler /* 49: UART3 */ + .long 0 /* 50: Reserved */ + .long SPI1_IRQHandler /* 51: SPI1 */ + .long SPI2_IRQHandler /* 52: SPI2 */ + .long USBD_IRQHandler /* 53: USBD */ + .long OHCI_IRQHandler /* 54: OHCI */ + .long USBOTG_IRQHandler /* 55: OTG */ + .long CAN0_IRQHandler /* 56: CAN0 */ + .long CAN1_IRQHandler /* 57: CAN1 */ + .long SC0_IRQHandler /* 58: SC0 */ + .long SC1_IRQHandler /* 59: SC1 */ + .long SC2_IRQHandler /* 60: SC2 */ + .long 0 /* 61: Reserved */ + .long SPI3_IRQHandler /* 62: SPI3 */ + .long 0 /* 63: Reserved */ + .long SDH0_IRQHandler /* 64: SDH0 */ + .long USBD20_IRQHandler /* 65: HSUSBD */ + .long EMAC_TX_IRQHandler /* 66: EMAC_TX */ + .long EMAC_RX_IRQHandler /* 67: EMAC_RX */ + .long I2S0_IRQHandler /* 68: I2S */ + .long 0 /* 69: Reserved */ + .long OPA0_IRQHandler /* 70: OPA */ + .long CRYPTO_IRQHandler /* 71: CRYPTO */ + .long GPG_IRQHandler /* 72: GPG */ + .long EINT6_IRQHandler /* 73: EINT6 */ + .long UART4_IRQHandler /* 74: UART4 */ + .long UART5_IRQHandler /* 75: UART5 */ + .long USCI0_IRQHandler /* 76: USCI0 */ + .long USCI1_IRQHandler /* 77: USCI1 */ + .long BPWM0_IRQHandler /* 78: BPWM0 */ + .long BPWM1_IRQHandler /* 79: BPWM1 */ + .long SPIM_IRQHandler /* 80: SPIM */ + .long 0 /* 81: Reserved */ + .long I2C2_IRQHandler /* 82: I2C2 */ + .long 0 /* 83: Reserved */ + .long QEI0_IRQHandler /* 84: QEI0 */ + .long QEI1_IRQHandler /* 85: QEI1 */ + .long ECAP0_IRQHandler /* 86: ECAP0 */ + .long ECAP1_IRQHandler /* 87: ECAP1 */ + .long GPH_IRQHandler /* 88: GPH */ + .long EINT7_IRQHandler /* 89: EINT7 */ + .long SDH1_IRQHandler /* 90: SDH1 */ + .long 0 /* 91: Reserved */ + .long EHCI_IRQHandler /* 92: EHCI */ + .long USBOTG20_IRQHandler /* 93: HSOTG */ - .size __isr_vector, . - __isr_vector + .size __Vectors, . - __Vectors .text .thumb - -/* Reset Handler */ - .thumb_func - .align 2 + .align 2 .globl Reset_Handler - .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__isr_vector - str r1, [r0] - ldr r2, [r1] - msr msp, r2 +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ /* Unlock Register */ ldr r0, =0x40000100 @@ -173,7 +274,7 @@ Reset_Handler: ldr r1, =0x88 str r1, [r0] -#if !defined(ENABLE_SPIM_CACHE) +#ifndef ENABLE_SPIM_CACHE ldr r0, =0x40000200 /* R0 = Clock Controller Register Base Address */ ldr r1, [r0,#0x4] /* R1 = 0x40000204 (AHBCLK) */ orr r1, r1, #0x4000 @@ -189,273 +290,139 @@ Reset_Handler: #endif #ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 + bl SystemInit #endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: +/* Init POR */ +#if 0 + ldr r0, =0x40000024 + ldr r1, =0x00005AA5 + str r1, [r0] #endif -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - - /* Lock */ +/* Lock register */ ldr r0, =0x40000100 ldr r1, =0 str r1, [r0] - cpsie i /* Unmask interrupts */ #ifndef __START #define __START _start #endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif + bl __START + .pool - .size Reset_Handler, . - Reset_Handler + .size Reset_Handler, . - Reset_Handler .align 1 .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - ldr r0,=MemManage_Handler - bx r0 - .size MemManage_Handler, . - MemManage_Handler - - .align 1 - .thumb_func - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - ldr r0,=BusFault_Handler - bx r0 - .size BusFault_Handler, . - BusFault_Handler - - .align 1 - .thumb_func - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - ldr r0,=UsageFault_Handler - bx r0 - .size UsageFault_Handler, . - UsageFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - ldr r0,=DebugMon_Handler - bx r0 - .size DebugMon_Handler, . - DebugMon_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler /* Macro to define default handlers. Default handler * will be weak symbol and just dead loops. They can be * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler .endm -/* Exception Handlers */ - def_irq_handler BOD_IRQHandler /* 0: Brown Out detection */ - def_irq_handler IRC_IRQHandler /* 1: Internal RC */ - def_irq_handler PWRWU_IRQHandler /* 2: Power down wake up */ - def_irq_handler RAMPE_IRQHandler /* 3: RAM parity error */ - def_irq_handler CKFAIL_IRQHandler /* 4: Clock detection fail */ - def_irq_handler Reserved0_Handler /* 5: Reserved */ - def_irq_handler RTC_IRQHandler /* 6: Real Time Clock */ - def_irq_handler TAMPER_IRQHandler /* 7: Tamper detection */ - def_irq_handler WDT_IRQHandler /* 8: Watchdog timer */ - def_irq_handler WWDT_IRQHandler /* 9: Window watchdog timer */ - def_irq_handler EINT0_IRQHandler /* 10: External Input 0 */ - def_irq_handler EINT1_IRQHandler /* 11: External Input 1 */ - def_irq_handler EINT2_IRQHandler /* 12: External Input 2 */ - def_irq_handler EINT3_IRQHandler /* 13: External Input 3 */ - def_irq_handler EINT4_IRQHandler /* 14: External Input 4 */ - def_irq_handler EINT5_IRQHandler /* 15: External Input 5 */ - def_irq_handler GPA_IRQHandler /* 16: GPIO Port A */ - def_irq_handler GPB_IRQHandler /* 17: GPIO Port B */ - def_irq_handler GPC_IRQHandler /* 18: GPIO Port C */ - def_irq_handler GPD_IRQHandler /* 19: GPIO Port D */ - def_irq_handler GPE_IRQHandler /* 20: GPIO Port E */ - def_irq_handler GPF_IRQHandler /* 21: GPIO Port F */ - def_irq_handler QSPI0_IRQHandler /* 22: QSPI0 */ - def_irq_handler SPI0_IRQHandler /* 23: SPI0 */ - def_irq_handler BRAKE0_IRQHandler /* 24: */ - def_irq_handler EPWM0P0_IRQHandler /* 25: */ - def_irq_handler EPWM0P1_IRQHandler /* 26: */ - def_irq_handler EPWM0P2_IRQHandler /* 27: */ - def_irq_handler BRAKE1_IRQHandler /* 28: */ - def_irq_handler EPWM1P0_IRQHandler /* 29: */ - def_irq_handler EPWM1P1_IRQHandler /* 30: */ - def_irq_handler EPWM1P2_IRQHandler /* 31: */ - def_irq_handler TMR0_IRQHandler /* 32: Timer 0 */ - def_irq_handler TMR1_IRQHandler /* 33: Timer 1 */ - def_irq_handler TMR2_IRQHandler /* 34: Timer 2 */ - def_irq_handler TMR3_IRQHandler /* 35: Timer 3 */ - def_irq_handler UART0_IRQHandler /* 36: UART0 */ - def_irq_handler UART1_IRQHandler /* 37: UART1 */ - def_irq_handler I2C0_IRQHandler /* 38: I2C0 */ - def_irq_handler I2C1_IRQHandler /* 39: I2C1 */ - def_irq_handler PDMA_IRQHandler /* 40: Peripheral DMA */ - def_irq_handler DAC_IRQHandler /* 41: DAC */ - def_irq_handler ADC00_IRQHandler /* 42: ADC0 interrupt source 0 */ - def_irq_handler ADC01_IRQHandler /* 43: ADC0 interrupt source 1 */ - def_irq_handler ACMP01_IRQHandler /* 44: ACMP0 and ACMP1 */ - def_irq_handler Reserved1_Handler /* 45: Reserved */ - def_irq_handler ADC02_IRQHandler /* 46: ADC0 interrupt source 2 */ - def_irq_handler ADC03_IRQHandler /* 47: ADC0 interrupt source 3 */ - def_irq_handler UART2_IRQHandler /* 48: UART2 */ - def_irq_handler UART3_IRQHandler /* 49: UART3 */ - def_irq_handler Reserved2_Handler /* 50: Reserved */ - def_irq_handler SPI1_IRQHandler /* 51: SPI1 */ - def_irq_handler SPI2_IRQHandler /* 52: SPI2 */ - def_irq_handler USBD_IRQHandler /* 53: USB device */ - def_irq_handler OHCI_IRQHandler /* 54: OHCI */ - def_irq_handler USBOTG_IRQHandler /* 55: USB OTG */ - def_irq_handler CAN0_IRQHandler /* 56: CAN0 */ - def_irq_handler CAN1_IRQHandler /* 57: CAN1 */ - def_irq_handler SC0_IRQHandler /* 58: */ - def_irq_handler SC1_IRQHandler /* 59: */ - def_irq_handler SC2_IRQHandler /* 60: */ - def_irq_handler Reserved3_Handler /* 61: */ - def_irq_handler SPI3_IRQHandler /* 62: SPI3 */ - def_irq_handler Reserved4_Handler /* 63: */ - def_irq_handler SDH0_IRQHandler /* 64: SDH0 */ - def_irq_handler USBD20_IRQHandler /* 65: USBD20 */ - def_irq_handler EMAC_TX_IRQHandler /* 66: EMAC_TX */ - def_irq_handler EMAC_RX_IRQHandler /* 67: EMAX_RX */ - def_irq_handler I2S0_IRQHandler /* 68: I2S0 */ - def_irq_handler Reserved5_Handler /* 69: ToDo: Add description to this Interrupt */ - def_irq_handler OPA0_IRQHandler /* 70: OPA0 */ - def_irq_handler CRYPTO_IRQHandler /* 71: CRYPTO */ - def_irq_handler GPG_IRQHandler /* 72: */ - def_irq_handler EINT6_IRQHandler /* 73: */ - def_irq_handler UART4_IRQHandler /* 74: UART4 */ - def_irq_handler UART5_IRQHandler /* 75: UART5 */ - def_irq_handler USCI0_IRQHandler /* 76: USCI0 */ - def_irq_handler USCI1_IRQHandler /* 77: USCI1 */ - def_irq_handler BPWM0_IRQHandler /* 78: BPWM0 */ - def_irq_handler BPWM1_IRQHandler /* 79: BPWM1 */ - def_irq_handler SPIM_IRQHandler /* 80: SPIM */ - def_irq_handler Reserved6_Handler /* 81: ToDo: Add description to this Interrupt */ - def_irq_handler I2C2_IRQHandler /* 82: I2C2 */ - def_irq_handler Reserved7_Handler /* 83: */ - def_irq_handler QEI0_IRQHandler /* 84: QEI0 */ - def_irq_handler QEI1_IRQHandler /* 85: QEI1 */ - def_irq_handler ECAP0_IRQHandler /* 86: ECAP0 */ - def_irq_handler ECAP1_IRQHandler /* 87: ECAP1 */ - def_irq_handler GPH_IRQHandler /* 88: */ - def_irq_handler EINT7_IRQHandler /* 89: */ - def_irq_handler SDH1_IRQHandler /* 90: SDH1 */ - def_irq_handler Reserved8_Handler /* 91: */ - def_irq_handler EHCI_IRQHandler /* 92: EHCI */ - def_irq_handler USBOTG20_IRQHandler /* 93: */ + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler BOD_IRQHandler + def_irq_handler IRC_IRQHandler + def_irq_handler PWRWU_IRQHandler + def_irq_handler RAMPE_IRQHandler + def_irq_handler CKFAIL_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TAMPER_IRQHandler + def_irq_handler WDT_IRQHandler + def_irq_handler WWDT_IRQHandler + def_irq_handler EINT0_IRQHandler + def_irq_handler EINT1_IRQHandler + def_irq_handler EINT2_IRQHandler + def_irq_handler EINT3_IRQHandler + def_irq_handler EINT4_IRQHandler + def_irq_handler EINT5_IRQHandler + def_irq_handler GPA_IRQHandler + def_irq_handler GPB_IRQHandler + def_irq_handler GPC_IRQHandler + def_irq_handler GPD_IRQHandler + def_irq_handler GPE_IRQHandler + def_irq_handler GPF_IRQHandler + def_irq_handler QSPI0_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler BRAKE0_IRQHandler + def_irq_handler EPWM0P0_IRQHandler + def_irq_handler EPWM0P1_IRQHandler + def_irq_handler EPWM0P2_IRQHandler + def_irq_handler BRAKE1_IRQHandler + def_irq_handler EPWM1P0_IRQHandler + def_irq_handler EPWM1P1_IRQHandler + def_irq_handler EPWM1P2_IRQHandler + def_irq_handler TMR0_IRQHandler + def_irq_handler TMR1_IRQHandler + def_irq_handler TMR2_IRQHandler + def_irq_handler TMR3_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler PDMA_IRQHandler + def_irq_handler DAC_IRQHandler + def_irq_handler ADC00_IRQHandler + def_irq_handler ADC01_IRQHandler + def_irq_handler ACMP01_IRQHandler + def_irq_handler ADC02_IRQHandler + def_irq_handler ADC03_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler SPI2_IRQHandler + def_irq_handler USBD_IRQHandler + def_irq_handler OHCI_IRQHandler + def_irq_handler USBOTG_IRQHandler + def_irq_handler CAN0_IRQHandler + def_irq_handler CAN1_IRQHandler + def_irq_handler SC0_IRQHandler + def_irq_handler SC1_IRQHandler + def_irq_handler SC2_IRQHandler + def_irq_handler SPI3_IRQHandler + def_irq_handler SDH0_IRQHandler + def_irq_handler USBD20_IRQHandler + def_irq_handler EMAC_TX_IRQHandler + def_irq_handler EMAC_RX_IRQHandler + def_irq_handler I2S0_IRQHandler + def_irq_handler OPA0_IRQHandler + def_irq_handler CRYPTO_IRQHandler + def_irq_handler GPG_IRQHandler + def_irq_handler EINT6_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler UART5_IRQHandler + def_irq_handler USCI0_IRQHandler + def_irq_handler USCI1_IRQHandler + def_irq_handler BPWM0_IRQHandler + def_irq_handler BPWM1_IRQHandler + def_irq_handler SPIM_IRQHandler + def_irq_handler I2C2_IRQHandler + def_irq_handler QEI0_IRQHandler + def_irq_handler QEI1_IRQHandler + def_irq_handler ECAP0_IRQHandler + def_irq_handler ECAP1_IRQHandler + def_irq_handler GPH_IRQHandler + def_irq_handler EINT7_IRQHandler + def_irq_handler SDH1_IRQHandler + def_irq_handler EHCI_IRQHandler + def_irq_handler USBOTG20_IRQHandler .end diff --git a/test/info.py b/test/info.py index d209e685c..27de0c3e8 100644 --- a/test/info.py +++ b/test/info.py @@ -205,6 +205,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1309, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m252kg_if', 'm48ssidae_bl', None ), ( 0x1310, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_iot_m263a_if', 'm48ssidae_bl', None ), ( 0x1312, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m2354_if', 'm48ssidae_bl', None ), + ( 0x1313, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_iot_m467_if', 'm48ssidae_bl', None ), ( 0x2600, VENDOR_TO_FAMILY('Nordic', 2), 'k20dx_ep_agora_if', None, None ), ( 0x2601, VENDOR_TO_FAMILY('NXP', 0), 'k20dx_ep_kairos_if', None, None ), ( 0x4600, VENDOR_TO_FAMILY('Realtek', 1), 'lpc11u35_rtl8195am_if', None, 'REALTEK-RTL8195AM' ), @@ -310,6 +311,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x1309, # NuMaker-M252KG 0x1310, # NuMaker-IoT-M263A 0x1312, # NuMaker-M2354 + 0x1313, # NuMaker-IoT-M467 0x3103, # dipdap_sdt51822b 0x3104, # dipdap_sdt52832b 0x3105, # dipdap_sdt64b