From d30bdbe08b1223b28e267b286c1f113e8080312f Mon Sep 17 00:00:00 2001 From: "M. Rahimi" Date: Tue, 7 May 2019 19:25:46 +0430 Subject: [PATCH 1/2] Enabled crash reporting for DISCO_F407VG target --- platform/mbed_lib.json | 4 ++++ .../device/TOOLCHAIN_GCC_ARM/STM32F407XG.ld | 14 ++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/platform/mbed_lib.json b/platform/mbed_lib.json index e6746932240..9854de5918e 100644 --- a/platform/mbed_lib.json +++ b/platform/mbed_lib.json @@ -198,6 +198,10 @@ "NUCLEO_F411RE": { "crash-capture-enabled": true, "fatal-error-auto-reboot-enabled": true + }, + "DISCO_F407VG": { + "crash-capture-enabled": true, + "fatal-error-auto-reboot-enabled": true } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/STM32F407XG.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/STM32F407XG.ld index 448b4a679e3..bb1edf9b048 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/STM32F407XG.ld +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/STM32F407XG.ld @@ -6,6 +6,8 @@ STACK_SIZE = MBED_BOOT_STACK_SIZE; +M_CRASH_DATA_RAM_SIZE = 0x100; + MEMORY { FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K @@ -85,6 +87,18 @@ SECTIONS __etext = .; _sidata = .; + .crash_data_ram : + { + . = ALIGN(8); + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > RAM + .data : AT (__etext) { __data_start__ = .; From 06ed3c44c2938ad7631d40ed06ba073c5f4fd6b7 Mon Sep 17 00:00:00 2001 From: "M. Rahimi" Date: Tue, 7 May 2019 21:43:37 +0430 Subject: [PATCH 2/2] Enabled crash reporting for DISCO_F407VG on all other toolchains --- .../TOOLCHAIN_ARM_MICRO/STM32F407xx.sct | 13 ++++++-- .../device/TOOLCHAIN_ARM_STD/STM32F407xx.sct | 32 +++++++++++++++++-- .../device/TOOLCHAIN_IAR/stm32f407xx.icf | 9 +++++- 3 files changed, 48 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct index 49c27b3efd0..9fd75f5b79d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct @@ -29,7 +29,13 @@ #define VECTOR_SIZE 0x188 -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) +#define MBED_CRASH_REPORT_RAM_SIZE 0x100 + +#define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE) +#define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE) + + +#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE+MBED_CRASH_REPORT_RAM_SIZE) LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region @@ -39,7 +45,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region .ANY (+RO) } - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data + RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data + } + + RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data .ANY (+RW +ZI) } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct index c4f0bd2b4d7..899bded7d64 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct @@ -3,24 +3,50 @@ ; *** Scatter-Loading Description File *** ; ***************************************** +; 1 MB FLASH (0x100000) + 192 KB SRAM (0x30000) + 64 KB CCBRAM (0x10000)+ 4 KB BKPSRAM + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + #if !defined(MBED_BOOT_STACK_SIZE) #define MBED_BOOT_STACK_SIZE 0x400 #endif #define Stack_Size MBED_BOOT_STACK_SIZE -LR_IROM1 0x08000000 0x00100000 { ; load region size_region - ER_IROM1 0x08000000 0x00100000 { ; load address = execution address +#define MBED_RAM_START 0x20000000 +#define MBED_RAM_SIZE 0x30000 +#define MBED_VECTTABLE_RAM_START (MBED_RAM_START) +#define MBED_VECTTABLE_RAM_SIZE 0x1B0 +#define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE) +#define MBED_CRASH_REPORT_RAM_SIZE 0x100 +#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE) +#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x20000188 0x0001FE78-Stack_Size { + + ; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM + RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data .ANY (+RW +ZI) } + RW_IRAM2 0x10000000 0x00010000 { ; CCM .ANY (CCMRAM) } + + RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data + } + ARM_LIB_STACK (0x20000188+0x0001FE78) EMPTY -Stack_Size { ; stack } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf index 74a8681bcac..63714e3c658 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf @@ -8,7 +8,9 @@ define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; define symbol __NVIC_start__ = 0x20000000; define symbol __NVIC_end__ = 0x20000187; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000188; +define symbol __region_CRASH_DATA_RAM_start__ = 0x20000188; +define symbol __region_CRASH_DATA_RAM_end__ = 0x20000287; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000288; define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; /*-Sizes-*/ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { @@ -20,8 +22,13 @@ define symbol __ICFEDIT_size_heap__ = 0x8000; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +/* Define Crash Data Symbols */ +define exported symbol __CRASH_DATA_RAM_START__ = __region_CRASH_DATA_RAM_start__; +define exported symbol __CRASH_DATA_RAM_END__ = __region_CRASH_DATA_RAM_end__; + define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };