diff --git a/connectivity/drivers/lora/TARGET_STM32WL/CMakeLists.txt b/connectivity/drivers/lora/TARGET_STM32WL/CMakeLists.txt deleted file mode 100644 index 35280ef154a..00000000000 --- a/connectivity/drivers/lora/TARGET_STM32WL/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -target_include_directories(mbed-lorawan - INTERFACE - . -) - -target_sources(mbed-lorawan - INTERFACE - STM32WL_LoRaRadio.cpp -) diff --git a/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_radio_driver.cpp b/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_radio_driver.cpp index 2640b3a95d3..dbea523fddc 100644 --- a/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_radio_driver.cpp +++ b/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_radio_driver.cpp @@ -60,5 +60,4 @@ MBED_WEAK void set_antenna_switch(RBI_Switch_TypeDef state) default: break; } -} - +} \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt index 1b8e7848726..dd8a9a975ee 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt @@ -16,6 +16,7 @@ target_sources(mbed-stm32wl pwmout_device.c serial_device.c spi_api.c + system_clock.c ) target_include_directories(mbed-stm32wl diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32WL/PeripheralNames.h similarity index 97% rename from targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h rename to targets/TARGET_STM/TARGET_STM32WL/PeripheralNames.h index 3971fb445f0..3a95d6d25d9 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32WL/PeripheralNames.h @@ -35,7 +35,7 @@ typedef enum { typedef enum { UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, + UART_2 = (int)USART2_BASE, LPUART_1 = (int)LPUART1_BASE } UARTName; diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/CMakeLists.txt index 9d95409ac1d..d57d92d8871 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/CMakeLists.txt @@ -6,7 +6,6 @@ add_library(mbed-nucleo-wl55jc INTERFACE) target_sources(mbed-nucleo-wl55jc INTERFACE PeripheralPins.c - system_clock.c ) target_include_directories(mbed-nucleo-wl55jc diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt new file mode 100644 index 00000000000..545b9fc562b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(TARGET_LORA_E5 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_RAK3172 EXCLUDE_FROM_ALL) + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle5xc.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle5xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32wle5xc.sct) +endif() + +add_library(mbed-stm32wle5xc INTERFACE) + +target_sources(mbed-stm32wle5xc + INTERFACE + ${STARTUP_FILE} +) + +target_include_directories(mbed-stm32wle5xc + INTERFACE + . +) + +mbed_set_linker_script(mbed-stm32wle5xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32wle5xc INTERFACE mbed-stm32wl) diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c b/targets/TARGET_STM/TARGET_STM32WL/system_clock.c similarity index 51% rename from targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c rename to targets/TARGET_STM/TARGET_STM32WL/system_clock.c index 70d39202503..ae2309a02a5 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32WL/system_clock.c @@ -39,31 +39,31 @@ MBED_WEAK void SetSysClock(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Configure the main internal regulator output voltage - */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - MBED_ASSERT(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK); - /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3 | RCC_CLOCKTYPE_HCLK - | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 - | RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; - MBED_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK); - /* Peripheral clock enable */ + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + MBED_ASSERT(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK); + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3|RCC_CLOCKTYPE_HCLK + |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 + |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; + MBED_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK); + /* Peripheral clock enable */ } diff --git a/targets/targets.json b/targets/targets.json index 755abe62dc1..87c854b9b9d 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -4381,6 +4381,34 @@ ], "device_name": "STM32WL55JCIx" }, + "MCU_STM32WLe5xC": { + "inherits": [ + "MCU_STM32WL" + ], + "public": false, + "macros_add": [ + "STM32WLE5xx" + ], + "extra_labels_add": [ + "STM32WLE5xC" + ], + "mbed_rom_start": "0x8000000", + "mbed_rom_size": "0x40000", + "mbed_ram_start": "0x20000000", + "mbed_ram_size": "0x10000" + }, + "LORA_E5": { + "inherits": [ + "MCU_STM32WLe5xC" + ], + "device_name": "STM32WLE5JCIx" + }, + "RAK3172": { + "inherits": [ + "MCU_STM32WLe5xC" + ], + "device_name": "STM32WLE5JCIx" + }, "MIMXRT1050_EVK": { "supported_form_factors": [ "ARDUINO_UNO" diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index c0d6f22f9ba..1c6f78d6491 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -480223,6 +480223,74 @@ ], "sub_family": "STM32WL55" }, + "STM32WLE5JCIx": { + "name": "STM32WLE5JCIx:CM4", + "memories": { + "IRAM1": { + "access": { + "read": true, + "write": true, + "execute": false, + "peripheral": false, + "secure": false, + "non_secure": false, + "non_secure_callable": false + }, + "start": 536870912, + "size": 65536, + "startup": false, + "default": true + }, + "IROM1": { + "access": { + "read": true, + "write": false, + "execute": true, + "peripheral": false, + "secure": false, + "non_secure": false, + "non_secure_callable": false + }, + "start": 134217728, + "size": 262144, + "startup": true, + "default": true + } + }, + "algorithms": [ + { + "file_name": "CMSIS/Flash/STM32WLxx_CM4.FLM", + "start": 134217728, + "size": 262144, + "default": true, + "ram_start": null, + "ram_size": null + } + ], + "processor": { + "Symmetric": { + "units": 1, + "core": "CortexM4", + "fpu": "None", + "mpu": "Present" + } + }, + "from_pack": { + "vendor": "Keil", + "pack": "STM32WLxx_DFP", + "version": "1.0.0", + "url": "http://www.keil.com/pack" + }, + "vendor": "STMicroelectronics:13", + "family": "STM32WL Series", + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32WLE5" + }, "STM32WB15CCUx": { "name": "STM32WB15CCUx", "memories": {