From 92bfbccde7ce0f64b98f50bccc4cf79705f5e5f7 Mon Sep 17 00:00:00 2001 From: "Deepak V. Shreshti" Date: Wed, 30 Nov 2022 21:00:33 +0530 Subject: [PATCH 1/2] Added TMPM4GR Platform New Platform for Toshiba Added --- .../Periph_driver/inc/txz_adc.h | 463 ++ .../Periph_driver/inc/txz_adc_ch.h | 132 + .../Periph_driver/inc/txz_adc_include.h | 348 + .../TARGET_TMPM4GR/Periph_driver/inc/txz_cg.h | 111 + .../Periph_driver/inc/txz_driver_def.h | 96 + .../TARGET_TMPM4GR/Periph_driver/inc/txz_fc.h | 136 + .../Periph_driver/inc/txz_flash.h | 122 + .../Periph_driver/inc/txz_fuart.h | 542 ++ .../Periph_driver/inc/txz_fuart_ex.h | 109 + .../Periph_driver/inc/txz_fuart_include.h | 385 + .../Periph_driver/inc/txz_gpio.h | 178 + .../Periph_driver/inc/txz_gpio_M4GR.h | 2731 ++++++ .../Periph_driver/inc/txz_hal.h | 147 + .../Periph_driver/inc/txz_i2c.h | 805 ++ .../Periph_driver/inc/txz_i2c_api.h | 308 + .../Periph_driver/inc/txz_t32a.h | 1000 +++ .../Periph_driver/inc/txz_tspi.h | 1378 ++++ .../Periph_driver/inc/txz_uart.h | 797 ++ .../Periph_driver/inc/txz_uart_include.h | 471 ++ .../Periph_driver/src/txz_adc.c | 1067 +++ .../Periph_driver/src/txz_adc_ch.c | 347 + .../TARGET_TMPM4GR/Periph_driver/src/txz_cg.c | 498 ++ .../TARGET_TMPM4GR/Periph_driver/src/txz_fc.c | 695 ++ .../Periph_driver/src/txz_flash.c | 219 + .../Periph_driver/src/txz_fuart.c | 1384 ++++ .../Periph_driver/src/txz_fuart_ex.c | 218 + .../Periph_driver/src/txz_gpio.c | 1831 ++++ .../Periph_driver/src/txz_hal.c | 297 + .../Periph_driver/src/txz_i2c.c | 414 + .../Periph_driver/src/txz_i2c_api.c | 1721 ++++ .../Periph_driver/src/txz_t32a.c | 1998 +++++ .../Periph_driver/src/txz_tspi.c | 2895 +++++++ .../Periph_driver/src/txz_uart.c | 1805 ++++ .../TARGET_TMPM4GR/PeripheralNames.h | 193 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/PinNames.h | 144 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/PortNames.h | 51 + .../TARGET_TMPM4GR/analogin_api.c | 146 + .../TARGET_TMPM4GR/analogout_api.c | 129 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/device.h | 26 + .../TARGET_TMPM4GR/device/TMPM4GR.h | 7346 +++++++++++++++++ .../TOOLCHAIN_ARM_STD/startup_TMPM4GR.S | 633 ++ .../device/TOOLCHAIN_ARM_STD/tmpm4grf20fg.sct | 84 + .../TOOLCHAIN_GCC_ARM/startup_TMPM4GR.S | 586 ++ .../device/TOOLCHAIN_GCC_ARM/tmpm4grf20fg.ld | 197 + .../TARGET_TMPM4GR/device/cmsis.h | 24 + .../TARGET_TMPM4GR/device/cmsis_nvic.h | 40 + .../TARGET_TMPM4GR/device/system_TMPM4Gx.c | 343 + .../TARGET_TMPM4GR/device/system_TMPM4Gx.h | 67 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/flash_api.c | 130 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_api.c | 127 + .../TARGET_TMPM4GR/gpio_irq_api.c | 297 + .../TARGET_TMPM4GR/gpio_object.h | 70 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/i2c_api.c | 308 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/objects.h | 128 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/pinmap.c | 103 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/port_api.c | 144 + .../TARGET_TMPM4GR/pwmout_api.c | 240 + .../TARGET_TMPM4GR/reset_reason_api.c | 132 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/rtc_api.c | 241 + .../TARGET_TMPM4GR/serial_api.c | 725 ++ targets/TARGET_TOSHIBA/TARGET_TMPM4GR/sleep.c | 126 + .../TARGET_TOSHIBA/TARGET_TMPM4GR/spi_api.c | 678 ++ .../TARGET_TOSHIBA/TARGET_TMPM4GR/us_ticker.c | 108 + targets/TARGET_TOSHIBA/mbed_rtx.h | 10 +- targets/targets.json | 60 +- tools/arm_pack_manager/index.json | 80 + 66 files changed, 39362 insertions(+), 2 deletions(-) create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_ch.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_include.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_cg.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_driver_def.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fc.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_flash.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_ex.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_include.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio_M4GR.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_hal.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c_api.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_t32a.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_tspi.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart_include.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc_ch.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_cg.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fc.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_flash.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart_ex.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_gpio.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_hal.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_t32a.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_tspi.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_uart.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PeripheralNames.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PinNames.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PortNames.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogin_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogout_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TMPM4GR.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/startup_TMPM4GR.S create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/tmpm4grf20fg.sct create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4GR.S create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/tmpm4grf20fg.ld create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis_nvic.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/flash_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_irq_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_object.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/i2c_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/objects.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pinmap.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/port_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pwmout_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/reset_reason_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/rtc_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/serial_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/sleep.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/spi_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM4GR/us_ticker.c diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc.h new file mode 100644 index 00000000000..2e611568153 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc.h @@ -0,0 +1,463 @@ +/** + ******************************************************************************* + * @file txz_adc.h + * @brief This file provides all the functions prototypes for ADC driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __ADC_H +#define __ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +#include "txz_adc_ch.h" +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @defgroup ADC ADC + * @brief ADC Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_define ADC Exported Define + * @{ + */ + +/** + * @defgroup ADC_ChannelMax Channel Num Max + * @brief Max Num of channel. + * @{ + */ + +#define ADC_NUM_MAX ((uint32_t)24) /*!< Max Num of conversion. */ +/** + * @} + */ /* End of group ADC_ChannelMax */ +/** + * @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + @defgroup ADC_Exported_define ADC Exported Define + @{ + */ +/** @enum adc_sampling_period0_t + @brief Outside AIN sampling period. + */ +typedef enum { + ADC_SAMPLING_PERIOD0_XN = 0x00, /*!< SCLK Period (1/SCLK)xN */ + ADC_SAMPLING_PERIOD0_X2N = 0x08, /*!< SCLK Period (1/SCLK)x2N */ + ADC_SAMPLING_PERIOD0_X3N = 0x10, /*!< SCLK Period (1/SCLK)x3N */ + ADC_SAMPLING_PERIOD0_X4N = 0x18, /*!< SCLK Period (1/SCLK)x4N */ +} adc_sampling_period0_t; +/** @enum adc_sampling_period1_t + @brief Outside AIN sampling period. + */ +typedef enum { + ADC_SAMPLING_PERIOD1_XN = 0x000, /*!< SCLK Period (1/SCLK)xN */ + ADC_SAMPLING_PERIOD1_X2N = 0x100, /*!< SCLK Period (1/SCLK)x2N */ + ADC_SAMPLING_PERIOD1_X3N = 0x200, /*!< SCLK Period (1/SCLK)x3N */ + ADC_SAMPLING_PERIOD1_X4N = 0x300, /*!< SCLK Period (1/SCLK)x4N */ +} adc_sampling_period1_t; + +/*! @enum adc_sclk_t + @brief Select AD prescaler output (SCLK). + */ +typedef enum { + ADC_SCLK_2 = (0x00000000U), /*!< ADCLK/2 */ + ADC_SCLK_4 = (0x00000001U), /*!< ADCLK/4 */ + ADC_SCLK_8 = (0x00000002U), /*!< ADCLK/8 */ + ADC_SCLK_16 = (0x00000003U), /*!< ADCLK/16 */ + ADC_SCLK_3 = (0x00000004U), /*!< ADCLK/3 */ + ADC_SCLK_5 = (0x00000005U), /*!< ADCLK/5 */ + ADC_SCLK_6 = (0x00000006U), /*!< ADCLK/6 */ + ADC_SCLK_10 = (0x00000007U), /*!< ADCLK/10 */ +} adc_sclk_t; + +/*! @enum adc_mod1_t + @brief Select SCLK Frequency Band (MOD1). + */ +typedef enum { + ADC_MOD1_SCLK_1 = (0x00001000U), /*!< SCLK =< 20MHz > */ + ADC_MOD1_SCLK_2 = (0x00003000U), /*!< 20MHz < SCLK =< 25MHz > */ + ADC_MOD1_SCLK_3 = (0x00004000U), /*!< 25MHz < SCLK =< 30MHz > */ + ADC_MOD1_SCLK_4 = (0x00006011U), /*!< 30MHz < SCLK =< 40MHz > */ +} adc_mod1_t; + +/*! @enum adc_mod2_t + @brief Select ADC Product Setting Value (MOD2). + */ +typedef enum { + ADC_MOD2_SET = (0x00000000U), /*!< SET Value */ + ADC_MOD2_CLEAR = (0x00000000U), /*!< Reset Value */ +} adc_mod2_t; + +/*! @enum adc_int_t + @brief Select Interrupt Enable/Disable. + */ +typedef enum { + ADC_INT_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_INT_ENABLE = (0x00000080U), /*!< Enable. */ +} adc_int_t; + +/*! @enum adc_conversion_t + @brief Select conversion method. + */ +typedef enum { + ADC_CONVERSION_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_CONVERSION_CNT = (0x00000100U), /*!< Continuation. */ + ADC_CONVERSION_SGL = (0x00000200U), /*!< Single. */ + ADC_CONVERSION_TRG = (0x00000300U), /*!< Universal Trigger. */ + ADC_CONVERSION_HPTG = (0x00000400U), /*!< High Priority Trigger. */ +} adc_conversion_t; + +/*! @enum adc_dma_int_t + @brief Select DMA interrupt method. + */ +typedef enum { + ADC_DMA_INT_SGL_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_DMA_INT_SGL_ENABLE = (0x00000020U), /*!< DMA Single interrupt Enable. */ + ADC_DMA_INT_CNT_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_DMA_INT_CNT_ENABLE = (0x00000040U), /*!< DMA Continuation interrupt Enable. */ + ADC_DMA_INT_TRG_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_DMA_INT_TRG_ENABLE = (0x00000010U), /*!< DMA Universal Trigger interrupt Enable. */ + ADC_TRG_DISABLE = (0x00000000U), /*!< Universal Trigger Disable. */ + ADC_TRG_ENABLE = (0x00000001U), /*!< Universal Trigger Enable. */ + ADC_HPTG_DISABLE = (0x00000000U), /*!< High Priority Trigger Disable. */ + ADC_HPTG_ENABLE = (0x00000002U), /*!< High Priority Trigger Enable. */ +} adc_dma_int_t; + +/*! @enum adc_ain_range_t + @brief Range of AIN Macro Definition. + Range of AIN be set "(ADC_AIN_RANGE_MIN <= Value <= ADC_AIN_RANGE_MAX)". + */ +typedef enum { + ADC_AIN_RANGE_MIN = (0x00000000U), /*!< Minimum Value :AINx00 */ + ADC_AIN_RANGE_MAX = (0x00000017U), /*!< Maximum Value :AINx23 */ +} adc_ain_range_t; + +/*! @enum adc_status_t + @brief AD Running Status. + */ +typedef enum { + ADC_STATUS_MASK = (0x00000080U), /*!< for Mask. */ + ADC_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_STATUS_RUNNING = (0x00000080U), /*!< Running. */ +} adc_status_t; + +/*! @enum adc_cnt_status_t + @brief Continuity Conversion Running Status. + */ +typedef enum { + ADC_CNT_STATUS_MASK = (0x00000008U), /*!< for Mask. */ + ADC_CNT_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_CNT_STATUS_RUNNING = (0x00000008U), /*!< Running. */ +} adc_cnt_status_t; + +/*! @enum adc_sgl_status_t + @brief Single Conversion Running Status. + */ +typedef enum { + ADC_SGL_STATUS_MASK = (0x00000004U), /*!< for Mask. */ + ADC_SGL_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_SGL_STATUS_RUNNING = (0x00000004U), /*!< Running. */ +} adc_sgl_status_t; + +/*! @enum adc_trg_status_t + @brief Trigger Conversion Running Status. + */ +typedef enum { + ADC_TRG_STATUS_MASK = (0x00000002U), /*!< for Mask. */ + ADC_TRG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_TRG_STATUS_RUNNING = (0x00000002U), /*!< Running. */ +} adc_trg_status_t; + +/*! @enum adc_hpri_status_t + @brief Trigger Conversion Running Status. + */ +typedef enum { + ADC_HPTG_STATUS_MASK = (0x00000001U), /*!< for Mask. */ + ADC_HPTG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_HPTG_STATUS_RUNNING = (0x00000001U), /*!< Running. */ +} adc_hpri_status_t; + +/*! @enum adcmpxen_t + @brief Select Enable, Disable setting(ADxCMPEN). + */ +typedef enum { + ADCMP1EN_DISABLE = (0x00000000U), /*!< Disable. */ + ADCMP1EN_ENABLE = (0x00000002U), /*!< Enable. */ + ADCMP0EN_DISABLE = (0x00000000U), /*!< Disable. */ + ADCMP0EN_ENABLE = (0x00000001U), /*!< Enable. */ +} adcmpxen_t; + +/*! @enum adcmpcnt_t + @brief Select Compare count num. + */ +typedef enum { + ADCMPCNT_1 = (0x00000000U), /*!< 1 time */ + ADCMPCNT_2 = (0x00000100U), /*!< 2 times */ + ADCMPCNT_3 = (0x00000200U), /*!< 3 times */ + ADCMPCNT_4 = (0x00000300U), /*!< 4 times */ + ADCMPCNT_5 = (0x00000400U), /*!< 5 times */ + ADCMPCNT_6 = (0x00000500U), /*!< 6 times */ + ADCMPCNT_7 = (0x00000600U), /*!< 7 times */ + ADCMPCNT_8 = (0x00000700U), /*!< 8 times */ + ADCMPCNT_9 = (0x00000800U), /*!< 9 times */ + ADCMPCNT_10 = (0x00000900U), /*!< 10 times */ + ADCMPCNT_11 = (0x00000a00U), /*!< 11 times */ + ADCMPCNT_12 = (0x00000b00U), /*!< 12 times */ + ADCMPCNT_13 = (0x00000c00U), /*!< 13 times */ + ADCMPCNT_14 = (0x00000d00U), /*!< 14 times */ + ADCMPCNT_15 = (0x00000e00U), /*!< 15 times */ + ADCMPCNT_16 = (0x00000f00U), /*!< 16 times */ +} adcmpcnt_t; + +/*! @enum adcmpcond_t + @brief Compare condition + */ +typedef enum { + ADCMPCond_CNT = (0x00000000U), /*!< Continuous */ + ADCMPCond_ACC = (0x00000040U), /*!< Accumulation */ +} adcmpcond_t; + +/*! @enum adcmpbigsml_t + @brief Compare Big, Small condition + */ +typedef enum { + ADCMPBigSml_Big = (0x00000000U), /*!< Big */ + ADCMPBigSml_Sml = (0x00000020U), /*!< Small */ +} adcmpbigsml_t; + +/*! @enum adcmpstr_t + @brief Select Compare Store register + */ +typedef enum { + ADCMPStr_Reg0 = (0x00000000U), /*!< ADxREG0 */ + ADCMPStr_Reg1 = (0x00000001U), /*!< ADxREG1 */ + ADCMPStr_Reg2 = (0x00000002U), /*!< ADxREG2 */ + ADCMPStr_Reg3 = (0x00000003U), /*!< ADxREG3 */ + ADCMPStr_Reg4 = (0x00000004U), /*!< ADxREG4 */ + ADCMPStr_Reg5 = (0x00000005U), /*!< ADxREG5 */ + ADCMPStr_Reg6 = (0x00000006U), /*!< ADxREG6 */ + ADCMPStr_Reg7 = (0x00000007U), /*!< ADxREG7 */ + ADCMPStr_Reg8 = (0x00000008U), /*!< ADxREG8 */ + ADCMPStr_Reg9 = (0x00000009U), /*!< ADxREG9 */ + ADCMPStr_Reg10 = (0x0000000aU), /*!< ADxREG10 */ + ADCMPStr_Reg11 = (0x0000000bU), /*!< ADxREG11 */ + ADCMPStr_Reg12 = (0x0000000cU), /*!< ADxREG12 */ + ADCMPStr_Reg13 = (0x0000000dU), /*!< ADxREG13 */ + ADCMPStr_Reg14 = (0x0000000eU), /*!< ADxREG14 */ + ADCMPStr_Reg15 = (0x0000000fU), /*!< ADxREG15 */ + ADCMPStr_Reg16 = (0x00000010U), /*!< ADxREG16 */ + ADCMPStr_Reg17 = (0x00000011U), /*!< ADxREG17 */ + ADCMPStr_Reg18 = (0x00000012U), /*!< ADxREG18 */ + ADCMPStr_Reg19 = (0x00000013U), /*!< ADxREG19 */ + ADCMPStr_Reg20 = (0x00000014U), /*!< ADxREG20 */ + ADCMPStr_Reg21 = (0x00000015U), /*!< ADxREG21 */ + ADCMPStr_Reg22 = (0x00000016U), /*!< ADxREG22 */ + ADCMPStr_Reg23 = (0x00000017U), /*!< ADxREG23 */ +} adcmpstr_t; +/*! @enum adcexazain_t + @brief Select AIN no. + */ + +typedef enum { + ADCEXAZSEL_AIN0 = 0, /*!< AIN0 */ + ADCEXAZSEL_AIN1, /*!< AIN1 */ + ADCEXAZSEL_AIN2, /*!< AIN2 */ + ADCEXAZSEL_AIN3, /*!< AIN3 */ + ADCEXAZSEL_AIN4, /*!< AIN4 */ + ADCEXAZSEL_AIN5, /*!< AIN5 */ + ADCEXAZSEL_AIN6, /*!< AIN6 */ + ADCEXAZSEL_AIN7, /*!< AIN7 */ + ADCEXAZSEL_AIN8, /*!< AIN8 */ + ADCEXAZSEL_AIN9, /*!< AIN9 */ + ADCEXAZSEL_AIN10, /*!< AIN10 */ + ADCEXAZSEL_AIN11, /*!< AIN11 */ + ADCEXAZSEL_AIN12, /*!< AIN12 */ + ADCEXAZSEL_AIN13, /*!< AIN13 */ + ADCEXAZSEL_AIN14, /*!< AIN14 */ + ADCEXAZSEL_AIN15, /*!< AIN15 */ + ADCEXAZSEL_AIN16, /*!< AIN16 */ + ADCEXAZSEL_AIN17, /*!< AIN17 */ + ADCEXAZSEL_AIN18, /*!< AIN18 */ + ADCEXAZSEL_AIN19, /*!< AIN19 */ + ADCEXAZSEL_AIN20, /*!< AIN20 */ + ADCEXAZSEL_AIN21, /*!< AIN21 */ + ADCEXAZSEL_AIN22, /*!< AIN22 */ + ADCEXAZSEL_AIN23, /*!< AIN23 */ +} adcexazain_t; +/*! @enum adcexazsel_t + @brief Select sampling period, EXAS0 or EXAS1. + */ +typedef enum { + ADCEXAZSEL_EXAZ0 = (0x00000000), /*< EXAZ0 */ + ADCEXAZSEL_EXAZ1 = (0x00000001), /*< EXAZ1 */ +} adcexazsel_t; + +/*! + @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/*! + @defgroup ADC_Exported_typedef ADC Exported Typedef + @{ + */ + +/*----------------------------------*/ +/*! @struct adc_clock_t + @brief Clock information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + adc_sampling_period0_t exaz0; /*!< Outside AIN0 Sampling period. + : Use @ref adc_sampling_period0_t. */ + adc_sampling_period1_t exaz1; /*!< Outside AIN1 Sampling period. + : Use @ref adc_sampling_period1_t. */ + adc_sclk_t vadcld; /*!< Select AD prescaler output (SCLK). + : Use @ref adc_sclk_t. */ + uint32_t sampling_select; /*!< Sampling period select. : bit0-bit23 */ +} adc_clock_t; + +/*----------------------------------*/ +/*! @struct adc_cmpx_t + @brief Clock information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t CMPEN; /*!< Enable Register status */ + uint32_t CMPCNT; /*!< Compare count num. */ + uint32_t CMPCond; /*!< Compare condition */ + uint32_t CMPBigSml; /*!< Compare Big/Small condition */ + uint32_t StrReg; /*!< Compare Store register */ + uint32_t ADComp; /*!< ADxCMP0 register data */ + void (*handle)(uint32_t id, TXZ_Result result); /*!< Notify Compare Done. */ +} adc_cmpx_t; + +/*----------------------------------*/ +/*! @struct adc_initial_setting_t + @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + adc_clock_t clk; /*!< Clock setting. + : Use @ref adc_clock_t. */ + uint32_t mod1; /*!< AVDD3 voltage band setting. + : Use @ref adc_mod1_t. */ + uint32_t mod2; /*!< Product info setting. + : Use @ref adc_mod2_t. */ + adc_cmpx_t CMPxEN[4]; /*!< adc_cmpx_t. */ +} adc_initial_setting_t; + +/*----------------------------------*/ +/*! @struct adc_channel_setting_t + @brief Channel Setting. \n +*/ +/*----------------------------------*/ +typedef struct { + uint32_t interrupt; /*!< Interrupt Enable/Disable. + : Use @ref adc_dma_int_t. */ + uint32_t type; /*!< Conversion Type. + : Use @ref adc_conversion_t. */ + uint32_t ain; /*!< AIN. */ +} adc_channel_setting_t; + +/*----------------------------------*/ +/*! @struct adc_internal_info_t + @brief Driver internal information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + adc_ch_t ch[ADC_NUM_MAX]; /*!< Channel Instance. */ +} adc_internal_info_t; + +/*----------------------------------*/ +/*! @struct adc_t + @brief ADC handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_AD_TypeDef *p_instance; /*!< Registers base address. */ + adc_initial_setting_t init; /*!< Initial setting. */ + adc_internal_info_t info; /*!< Driver internal information. */ + struct { + void (*single)(uint32_t id, TXZ_Result result); /*!< Notify Single Conversion Done. */ + void (*continuity)(uint32_t id, TXZ_Result result); /*!< Notify Continuity Conversion Done. */ + void (*trigger)(uint32_t id, TXZ_Result result); /*!< Notify Trigger Conversion Done. */ + void (*highpriority)(uint32_t id, TXZ_Result result); /*!< Notify HighPriority Conversion Done. */ + } handler; /*!< Handler structure. */ +} adc_t; + +/** + * @} + */ /* End of group ADC_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_functions ADC Exported Functions + * @{ + */ +TXZ_Result adc_init(adc_t *p_obj); +TXZ_Result adc_deinit(adc_t *p_obj); +TXZ_Result adc_mode1_setting(void); +TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting); +TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch); +TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t); +TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t); +TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value); +TXZ_Result adc_start(adc_t *p_obj); +TXZ_Result adc_stop(adc_t *p_obj); +TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status); +TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout); +void adc_compa_irq_handler(void); +void adc_compb_irq_handler(void); +void adc_single_irq_handler(void); +void adc_continuity_irq_handler(void); +void adc_trigger_irq_handler(void); +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_ch.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_ch.h new file mode 100644 index 00000000000..bce9c399438 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_ch.h @@ -0,0 +1,132 @@ +/** + ******************************************************************************* + * @file txz_adc_ch.h + * @brief This file provides all the functions prototypes for ADC driver. \n + * Channel Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __ADC_CH_H +#define __ADC_CH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @defgroup ADC ADC + * @brief ADC Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_define ADC Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_define ADC Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_typedef ADC Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/*! @struct adc_ch_initial_setting_t + * @brief Initialize Setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t interrupt; /*!< Interrupt Enable/Disable. + : Use @ref adc_dma_int_t. */ + uint32_t type; /*!< Conversion Type. + : Use @ref adc_conversion_t. */ + uint32_t ain; /*!< AIN. */ +} adc_ch_initial_setting_t; + +/*----------------------------------*/ +/*! @struct adc_ch_t + * @brief ADC handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + __IO uint32_t *p_tset; /*!< ADxTSETn Address. */ + __I uint32_t *p_reg; /*!< ADxREGx Address. */ + adc_ch_initial_setting_t init; /*!< Initial setting. */ +} adc_ch_t; + +/** + * @} + */ /* End of group ADC_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_functions ADC Exported Functions + * @{ + */ +uint32_t get_conversion_data(uint32_t reg); +TXZ_Result adc_ch_init(adc_ch_t *p_obj); +TXZ_Result adc_ch_deinit(adc_ch_t *p_obj); +TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj); +TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj); +TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value); +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_CH_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_include.h new file mode 100644 index 00000000000..2d99bbdf39e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_include.h @@ -0,0 +1,348 @@ +/** + ******************************************************************************* + * @file txz_adc_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __ADC_INCLUDE_H +#define __ADC_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +#include "txz_hal.h" + +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @defgroup ADC ADC + * @brief ADC Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/** + * @defgroup NULL_Pointer NULL Pointer + * @brief NULL Pointer. + * @{ + */ +#define ADC_NULL ((void *)0) /*!< NULL Pointer. */ +/** + * @} + */ /* End of group NULL_Pointer */ + +/** + * @defgroup Parameter_Result Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define ADC_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define ADC_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group Parameter_Result */ + +/** + * @defgroup ADxCR0 ADxCR0 + * @brief ADxCR0 Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | ADEN | + * | 6-3 | - | + * | 2 | HPSGL | + * | 1 | SGL | + * | 0 | CNT | + * @{ + */ +/* ADEN */ +#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /*!< ADEN :Disable */ +#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /*!< ADEN :Enable */ +/* HPSGL */ +#define ADxCR0_HPSGL_ENABLE ((uint32_t)0x00000004) /*!< HPSGL :Enable */ +/* SGL */ +#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /*!< SGL :Enable */ +/* CNT */ +#define ADxCR0_CNT_MASK ((uint32_t)0x00000001) /*!< CNT :Mask */ +#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /*!< CNT :Disable */ +#define ADxCR0_CNT_ENABLE ((uint32_t)0x00000001) /*!< CNT :Enable */ +/** + * @} + */ /* End of group ADxCR0 */ + +/** + * @defgroup ADxCR1 ADxCR1 + * @brief ADxCR1 Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | HPDMEN | + * | 6 | CNTDMEN | + * | 5 | SGLDMEN | + * | 4 | TRGDMEN | + * | 3:2 | - | + * | 1 | HPTRGEN | + * | 0 | TRGEN | + * @{ + */ +/* HPDMEN */ +#define ADxCR1_HPDMEN_DISABLE ((uint32_t)0x00000000) /*!< HPDMEN :Disable */ +#define ADxCR1_HPDMEN_ENABLE ((uint32_t)0x00000080) /*!< HPDMEN :Enable */ +/* CNTDMEN */ +#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /*!< CNTDMEN :Disable */ +#define ADxCR1_CNTDMEN_ENABLE ((uint32_t)0x00000040) /*!< CNTDMEN :Enable */ +/* SGLDMEN */ +#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /*!< SGLDMEN :Disable */ +#define ADxCR1_SGLDMEN_ENABLE ((uint32_t)0x00000020) /*!< SGLDMEN :Enable */ +/* TRGDMEN */ +#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /*!< TRGDMEN :Disable */ +#define ADxCR1_TRGDMEN_ENABLE ((uint32_t)0x00000010) /*!< TRGDMEN :Enable */ +/* HPTRGEN */ +#define ADxCR1_HPTRGEN_DISABLE ((uint32_t)0x00000000) /*!< HPTRGEN :Disable */ +#define ADxCR1_HPTRGEN_ENABLE ((uint32_t)0x00000002) /*!< HPTRGEN :Enable */ +/* TRGEN */ +#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< TRGEN :Disable */ +#define ADxCR1_TRGEN_ENABLE ((uint32_t)0x00000001) /*!< TRGEN :Enable */ +/** + * @} + */ /* End of group ADxCR1 */ + +/** + * @defgroup ADxST ADxST + * @brief ADxST Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | ADBF | + * | 6-4 | - | + * | 3 | CNTF | + * | 2 | SNGF | + * | 1 | TRGF | + * | 0 | HPF | + * @{ + */ +/* ADBF */ +#define ADxST_ADBF_MASK ((uint32_t)0x00000080) /*!< ADBF :Mask. */ +#define ADxST_ADBF_IDLE ((uint32_t)0x00000000) /*!< ADBF :Idle. Can stop ADCLK. */ +#define ADxST_ADBF_RUN ((uint32_t)0x00000080) /*!< ADBF :Running. Can't stop ADCLK. */ +/* CNTF */ +#define ADxST_CNTF_MASK ((uint32_t)0x00000008) /*!< CNTF :Mask. */ +#define ADxST_CNTF_IDLE ((uint32_t)0x00000000) /*!< CNTF :Idle. */ +#define ADxST_CNTF_RUN ((uint32_t)0x00000008) /*!< CNTF :Running. */ +/* SNGF */ +#define ADxST_SNGF_MASK ((uint32_t)0x00000004) /*!< SNGF :Mask. */ +#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /*!< SNGF :Idle. */ +#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /*!< SNGF :Running. */ +/* TRGF */ +#define ADxST_TRGF_MASK ((uint32_t)0x00000002) /*!< TRGF :Mask. */ +#define ADxST_TRGF_IDLE ((uint32_t)0x00000000) /*!< TRGF :Idle. */ +#define ADxST_TRGF_RUN ((uint32_t)0x00000002) /*!< TRGF :Running. */ +/* PMDF */ +#define ADxST_HPF_MASK ((uint32_t)0x00000001) /*!< HPF :Mask. */ +#define ADxST_HPF_IDLE ((uint32_t)0x00000000) /*!< HPF :Idle. */ +#define ADxST_HPF_RUN ((uint32_t)0x00000001) /*!< HPF :Running. */ +/** + * @} + */ /* End of group ADxST */ + +/** + * @defgroup ADxMOD0 ADxMOD0. + * @brief ADxMOD0 Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-2 | - | + * | 1 | RCUT | + * | 0 | DACON | + * @{ + */ +/* RCUT */ +#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /*!< RCUT :Normal */ +#define ADxMOD0_RCUT_IREF_CUT ((uint32_t)0x00000002) /*!< RCUT :Iref cut */ +/* DACON */ +#define ADxMOD0_DACON_OFF ((uint32_t)0x00000000) /*!< DACON :DAC off */ +#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /*!< DACON :DAC on */ +/** + * @} + */ /* End of group ADxMOD0 */ + +/** + * @name ADxCMPEN Macro Definition. + * @brief ADxCMPEN Register Macro Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-4 | - | + * | 3 | CMP3EN | + * | 2 | CMP2EN | + * | 1 | CMP1EN | + * | 0 | CMP0EN | + * @{ + */ +/* CMP3EN */ +#define ADxCMPEN_CMP3EN_DISABLE ((uint32_t)0x00000000) /*!< CMP3EN :Disable */ +#define ADxCMPEN_CMP3EN_ENABLE ((uint32_t)0x00000008) /*!< CMP3EN :Enable */ +/* CMP2EN */ +#define ADxCMPEN_CMP2EN_DISABLE ((uint32_t)0x00000000) /*!< CMP2EN :Disable */ +#define ADxCMPEN_CMP2EN_ENABLE ((uint32_t)0x00000004) /*!< CMP2EN :Enable */ +/* CMP1EN */ +#define ADxCMPEN_CMP1EN_DISABLE ((uint32_t)0x00000000) /*!< CMP1EN :Disable */ +#define ADxCMPEN_CMP1EN_ENABLE ((uint32_t)0x00000002) /*!< CMP1EN :Enable */ +/* CMP0EN */ +#define ADxCMPEN_CMP0EN_DISABLE ((uint32_t)0x00000000) /*!< CMP0EN :Disable */ +#define ADxCMPEN_CMP0EN_ENABLE ((uint32_t)0x00000001) /*!< CMP0EN :Enable */ +/** + * @} + */ /* End of name ADxCMPEN Macro Definition */ + +/** + * @name ADxTSETn Macro Definition. + * @brief ADxTSETn Register Macro Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | ENINT0 | + * | 6-5 | TRGS0[1:0] | + * | 4-0 | AINST0[4:0]| + * @{ + */ +/* ENINT0 */ +#define ADxTSETn_ENINT_MASK ((uint32_t)0x00000080) /*!< ENINT :Mask */ +#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /*!< ENINT :Disable */ +#define ADxTSETn_ENINT_ENABLE ((uint32_t)0x00000080) /*!< ENINT :Enable */ +/* TRGS0[1:0] */ +#define ADxTSETn_TRGS_DISABLE ((uint32_t)0x00000000) /*!< TRGS :Disable */ +#define ADxTSETn_TRGS_CNT ((uint32_t)0x00000100) /*!< TRGS :Continuation */ +#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000200) /*!< TRGS :Single */ +#define ADxTSETn_TRGS_TRG ((uint32_t)0x00000300) /*!< TRGS :Universal Trigger */ +#define ADxTSETn_TRGS_PRI ((uint32_t)0x00000400) /*!< TRGS :Priority Trigger */ +/** + * @} + */ /* End of name ADxTSETn Macro Definition */ + +/** + * @name ADxREGn Macro Definition. + * @brief ADxREGn Register Macro Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-30 | - | + * | 29 | ADOVRF_Mn | + * | 28 | ADRF_Mn | + * | 27-16 | ADR_Mn[11:0] | + * | 15-4 | ADRn[11:0] | + * | 3-2 | - | + * | 1 | ADOVRFn | + * | 0 | ADRFn | + * @{ + */ +/* ADOVRF_Mn */ +#define ADxREGn_ADOVRF_Mn_MASK ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Mask */ +#define ADxREGn_ADOVRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */ +#define ADxREGn_ADOVRF_Mn_ON ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Flag on */ +/* ADRF_Mn */ +#define ADxREGn_ADRF_Mn_MASK ((uint32_t)0x10000000) /*!< ADRF_Mn :Mask */ +#define ADxREGn_ADRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADRF_Mn :Flag off. */ +#define ADxREGn_ADRF_Mn_ON ((uint32_t)0x10000000) /*!< ADRF_Mn :Flag on */ +/* ADR_Mn */ +#define ADxREGn_ADR_Mn_MASK ((uint32_t)0x0FFF0000) /*!< ADR_Mn :Mask */ +/* ADRn */ +#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /*!< ADRn :Mask */ +/* ADOVRFn */ +#define ADxREGn_ADOVRFn_MASK ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Mask */ +#define ADxREGn_ADOVRFn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */ +#define ADxREGn_ADOVRFn_ON ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Flag on */ +/* ADRFn */ +#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /*!< ADRFn :Mask */ +#define ADxREGn_ADRFn_OFF ((uint32_t)0x00000000) /*!< ADRFn :Flag off. */ +#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /*!< ADRFn :Flag on */ +/** + * @} + */ /* End of name ADxREGn Macro Definition */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_functions ADC Private Functions + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group ADC_Private_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_INCLUDE_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_cg.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_cg.h new file mode 100644 index 00000000000..2abb195ca27 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_cg.h @@ -0,0 +1,111 @@ +/** + ******************************************************************************* + * @file txz_cg.h + * @brief This file provides all the functions prototypes for CG driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __CG_H +#define __CG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup CG CG + * @brief CG Driver. + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_define CG Exported Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_define CG Exported Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_typedef CG Exported Typedef + * @{ + */ +/** + * @brief CG member. +*/ +/*----------------------------------*/ +typedef struct { + TSB_CG_TypeDef *p_instance; /*!< Registers base address. */ +} cg_t; + +/** + * @} + */ /* End of group CG_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_functions CG Exported Functions + * @{ + */ +uint32_t cg_get_fsysm(cg_t *p_obj); +uint32_t cg_get_phyt0(cg_t *p_obj); +uint32_t cg_get_mphyt0(cg_t *p_obj); +TXZ_Result cg_ihosc_enable(cg_t *p_obj); +TXZ_Result cg_ihosc_disable(cg_t *p_obj); +/** + * @} + */ /* End of group CG_Exported_functions */ + +/** + * @} + */ /* End of group CG */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __CG_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_driver_def.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_driver_def.h new file mode 100644 index 00000000000..95428ec9c5b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_driver_def.h @@ -0,0 +1,96 @@ +/** + ******************************************************************************* + * @file txz_driver_def.h + * @brief All common macro and definition for TXZ peripheral drivers + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TXZ_DRIVER_DEF_H +#define __TXZ_DRIVER_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF + * @brief All common macro and definition for TXZ peripheral drivers + * @{ + */ + +/** @defgroup Device_Header_Included Device Header Included + * @brief Include the Device header file of a Target. + * @{ + */ +#include "TMPM4GR.h" /*!< TMPM4GR Header file. */ + +/** + * @} + */ /* End of group Device_Header */ + + +/** @defgroup TXZ_Exported_typedef TXZ Exported typedef + * @{ + */ +typedef enum { + TXZ_SUCCESS = 0U, + TXZ_ERROR = 1U +} TXZ_Result; + +typedef enum { + TXZ_BUSY = 0U, + TXZ_DONE = 1U +} TXZ_WorkState; + +typedef enum { + TXZ_DISABLE = 0U, + TXZ_ENABLE = 1U +} TXZ_FunctionalState; +/** + * @} + */ /* End of group TXZ_Exported_typedef */ + +/** @defgroup TXZ_Exported_macro TXZ Exported macro + * @{ + */ +#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0) + +/** + * @brief To report the name of the source file and source line number where the + * assert_param error has occurred, "__DEBUG__" must be defined. And detailed + * definition of assert_failed() is needed to be implemented, which can be + * done, for example, in the main.c file. + */ +#ifdef __DEBUG__ +void assert_failed(char *file, int32_t line); +#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) +#else +#define assert_param(expr) +#endif /* __DEBUG__ */ +/** + * @} + */ /* End of group TXZ_Exported_macro */ + +/** + * @} + */ /* End of group Periph_Driver */ + +/** + * @} + */ /* End of group TXZ_DRIVER_DEF */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TXZ_DRIVER_DEF_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fc.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fc.h new file mode 100644 index 00000000000..7477f133f31 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fc.h @@ -0,0 +1,136 @@ +/** + ******************************************************************************* + * @file txz_fc.h + * @brief This file provides all the functions prototypes for FLASH. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FC_H +#define __FC_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +#if defined(__FC_H) +/** @addtogroup Periph driver + * @{ + */ + +/** @defgroup fc + * @brief fc + * @{ + */ + + +/** @defgroup FlashApi_Exported_Types + * @{ + */ + +/** + * @enum fc_sr0_t + * @brief Enumerated type definition of the FCSR0 register. + */ +typedef enum { + FC_SR0_RDYBSY = (0x00000001UL) /*!< 0:Busy, 1:Ready all flash */ +} fc_sr0_t; + +/*----------------------------------*/ +/** + * @enum fc_erase_kind_t + * @brief FC Erase Flash Kind structure definenition. +*/ +/*----------------------------------*/ +typedef enum { + FC_ERASE_KIND_PAGE = (0x00000040UL), /*!< Page Erase */ + FC_ERASE_KIND_BLOCK = (0x00000030UL) /*!< Block Erase */ +} fc_erase_kind_t; + +typedef enum { + FC_CODE_FLASH_PAGE0 = 0, /*!< (0x5E000000UL), CODE FLASH Page0 */ + FC_CODE_FLASH_PAGE1, /*!< (0x5E001000UL), CODE FLASH Page1 */ + FC_CODE_FLASH_PAGE2, /*!< (0x5E002000UL), CODE FLASH Page2 */ + FC_CODE_FLASH_PAGE3, /*!< (0x5E003000UL), CODE FLASH Page3 */ + FC_CODE_FLASH_PAGE4, /*!< (0x5E004000UL), CODE FLASH Page4 */ + FC_CODE_FLASH_PAGE5, /*!< (0x5E005000UL), CODE FLASH Page5 */ + FC_CODE_FLASH_PAGE6, /*!< (0x5E006000UL), CODE FLASH Page6 */ + FC_CODE_FLASH_PAGE7, /*!< (0x5E007000UL), CODE FLASH Page7 */ + FC_CODE_FLASH_PAGE8, /*!< (0x5E008000UL), CODE FLASH Page8 */ + FC_CODE_FLASH_PAGE9, /*!< (0x5E009000UL), CODE FLASH Page9 */ + FC_CODE_FLASH_PAGE10, /*!< (0x5E00A000UL), CODE FLASH Page10 */ + FC_CODE_FLASH_PAGE11, /*!< (0x5E00B000UL), CODE FLASH Page11 */ + FC_CODE_FLASH_PAGE12, /*!< (0x5E00C000UL), CODE FLASH Page12 */ + FC_CODE_FLASH_PAGE13, /*!< (0x5E00D000UL), CODE FLASH Page13 */ + FC_CODE_FLASH_PAGE14, /*!< (0x5E00E000UL), CODE FLASH Page14 */ + FC_CODE_FLASH_PAGE15, /*!< (0x5E00F000UL), CODE FLASH Page15 */ + FC_CODE_FLASH_PAGE16, /*!< (0x5E010000UL), CODE FLASH Page16 */ + FC_CODE_FLASH_PAGE17, /*!< (0x5E011000UL), CODE FLASH Page17 */ + FC_CODE_FLASH_PAGE18, /*!< (0x5E012000UL), CODE FLASH Page18 */ + FC_CODE_FLASH_PAGE19, /*!< (0x5E013000UL), CODE FLASH Page19 */ + FC_CODE_FLASH_PAGE20, /*!< (0x5E014000UL), CODE FLASH Page20 */ + FC_CODE_FLASH_PAGE21, /*!< (0x5E015000UL), CODE FLASH Page21 */ + FC_CODE_FLASH_PAGE22, /*!< (0x5E016000UL), CODE FLASH Page22 */ + FC_CODE_FLASH_PAGE23, /*!< (0x5E017000UL), CODE FLASH Page23 */ + FC_CODE_FLASH_PAGE24, /*!< (0x5E018000UL), CODE FLASH Page24 */ + FC_CODE_FLASH_PAGE25, /*!< (0x5E019000UL), CODE FLASH Page25 */ + FC_CODE_FLASH_PAGE26, /*!< (0x5E01A000UL), CODE FLASH Page26 */ + FC_CODE_FLASH_PAGE27, /*!< (0x5E01B000UL), CODE FLASH Page27 */ + FC_CODE_FLASH_PAGE28, /*!< (0x5E01C000UL), CODE FLASH Page28 */ + FC_CODE_FLASH_PAGE29, /*!< (0x5E01D000UL), CODE FLASH Page29 */ + FC_CODE_FLASH_PAGE30, /*!< (0x5E01E000UL), CODE FLASH Page30 */ + FC_CODE_FLASH_PAGE31 /*!< (0x5E01F000UL), CODE FLASH Page31 */ +} fc_code_flash_page_number_t; + +/** @} */ +/* End of group FlashApi_Exported_Types */ + +/** @defgroup FlashApi_Exported_Constants + * @{ + */ + +//#define FC_RAMADDRESSTOP (0x20000000UL) /*!< RAM Address Top */ +//#define FC_RAMADDRESSEND (0x20003fffUL) /*!< RAM Address End */ +#define FC_CODE_FLASH_ADDRESS_TOP (0x5E000000UL) /*!< CODE FLASH Address Top */ +//#define FC_CODEFLASHADDRESSEND (0x5E01FFFFUL) /*!< CODE FLASH Address End */ +#define FC_PAGE_SIZE (0x1000) /*!< The number of bytes in a page. */ +//#define FC_CODEFLASHPAGESIZE (0x1000) /*!< CODE FLASH PAGE SIZE */ +#define FC_CODE_FLASH_WRITE_SIZE (sizeof(uint32_t)*4) /*!< CODE FLASH WRITE SIZE */ + +/** @} */ +/* End of group FlashApi_Exported_Constants */ + + + +/** @weakgroup FlashApi_Exported_FunctionPrototypes + * @{ + */ +TXZ_WorkState fc_get_status(fc_sr0_t status); +TXZ_Result fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages); +TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t lasr_page); +TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr); + +/** @} */ +/* End of group FlashApi_Exported_FunctionPrototypes */ + + +/** @} */ +/* End of group fc */ + +/** @} */ +/* End of group Periph_driver */ + +#endif /* defined(__FC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __FC_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_flash.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_flash.h new file mode 100644 index 00000000000..110a5f1c602 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_flash.h @@ -0,0 +1,122 @@ +/** + ******************************************************************************* + * @file txz_flash.h + * @brief This file provides all the functions prototypes for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FLASH_H +#define __FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup FLASH FLASH + * @brief FLASH Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_macro FLASH Exported Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_define FLASH Exported Define + * @{ + */ +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_define FLASH Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_typedef FLASH Exported Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_functions FLASH Exported Functions + * @{ + */ + +void fc_read_clock_set(uint32_t sysclock); + +/** + * @} + */ /* End of group FLASH_Exported_functions */ + +/** + * @} + */ /* End of group FLASH */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __FLASH_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart.h new file mode 100644 index 00000000000..313c4d02cfc --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart.h @@ -0,0 +1,542 @@ +/** + ******************************************************************************* + * @file txz_fuart.h + * @brief This file provides all the functions prototypes for FUART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FUART_H +#define __FUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup FUART FUART + * @brief FUART Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_define FUART Exported Define + * @{ + */ + +/** + * @defgroup FUART_FifoMax Max Num of FIFO + * @brief Max Num of Tx/Rx Fifo. + * @{ + */ +#define FUART_TX_FIFO_MAX ((uint32_t)0x00000020) /*!< TX FIFO Max. */ +#define FUART_RX_FIFO_MAX ((uint32_t)0x00000020) /*!< RX FIFO Max. */ +/** + * @} + */ /* End of group UART_FifoMax */ + +/** + * @defgroup FUART_CTSHandshake CTS Handshake + * @brief Available CTS Handshake Macro Definition. + * @{ + */ +#define FUART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_CTS_ENABLE ((uint32_t)0x00008000) /*!< Available. */ +/** + * @} + */ /* End of group FUART_CTSHandshake */ + + +/** + * @defgroup FUART_RTSHandshake RTS Handshake + * @brief Available RTS Handshake Macro Definition. + * @{ + */ +#define FUART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_RTS_ENABLE ((uint32_t)0x00004000) /*!< Available. */ +/** + * @} + */ /* End of group FUART_RTSHandshake */ + +/** + * @defgroup FUART_FIFO FIFO Enable + * @brief FIFO Enable Bit Macro Definition. + * @{ + */ +#define FUART_FIFO_DISABLE ((uint32_t)0x00000000) /*!< Disable. */ +#define FUART_FIFO_ENABLE ((uint32_t)0x00000010) /*!< Enable. */ +/** + * @} + */ /* End of group FUART_FIFO */ + + +/** + * @defgroup FUART_StopBit Stop Bit + * @brief Stop Bit Macro Definition. + * @{ + */ +#define FUART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ +#define FUART_STOP_BIT_2 ((uint32_t)0x00000008) /*!< 2 bit */ +/** + * @} + */ /* End of group FUART_StopBit */ + + +/** + * @defgroup FUART_ParityBit Parity Bit + * @brief Parity Bit Macro Definition. + * @{ + */ +#define FUART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define FUART_PARITY_BIT_EVEN ((uint32_t)0x00000004) /*!< Even Parity */ +/** + * @} + */ /* End of group FUART_ParityBit */ + + +/** + * @defgroup FUART_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definition. + * @{ + */ +#define FUART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group FUART_ParityEnable */ + +/** + * @defgroup FUART_StaticParityEnable Static Parity Enable + * @brief Enable/Disable Static Parity Macro Definition. + * @{ + */ +#define FUART_STATIC_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_STATIC_PARITY_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group FUART_ParityEnable */ + +/** + * @defgroup FUART_DataLength Data Length + * @brief Data Length Macro Definition. + * @{ + */ +#define FUART_DATA_LENGTH_5 ((uint32_t)0x00000000) /*!< 5 bit */ +#define FUART_DATA_LENGTH_6 ((uint32_t)0x00000020) /*!< 6 bit */ +#define FUART_DATA_LENGTH_7 ((uint32_t)0x00000040) /*!< 7 bit */ +#define FUART_DATA_LENGTH_8 ((uint32_t)0x00000060) /*!< 8 bit */ +/** + * @} + */ /* End of group FUART_DataLength */ + +/** + * @defgroup FUART_FIFO_Level FIFO Level + * @brief FIFO Level Macro Definition. + * @{ + */ +#define FUART_FIFO_LEVEL_4 ((uint32_t)0x00000000) /*!< 4 level */ +#define FUART_FIFO_LEVEL_8 ((uint32_t)0x00000001) /*!< 8 level */ +#define FUART_FIFO_LEVEL_16 ((uint32_t)0x00000002) /*!< 16 level */ +#define FUART_FIFO_LEVEL_24 ((uint32_t)0x00000003) /*!< 24 level */ +#define FUART_FIFO_LEVEL_28 ((uint32_t)0x00000004) /*!< 28 level */ + +/** + * @} + */ /* End of group FUART_DataLength */ + +/** + * @defgroup FUART_TxInterrupt Tx Interrupt + * @brief Available Transmit Interrupt Macro Definition. + * @{ + */ +#define FUART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_TX_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ +/** + * @} + */ /* End of group FUART_TxInterrupt */ + + +/** + * @defgroup FUART_RxInterrupt Rx Interrupt + * @brief Available Receive Interrupt Macro Definition. + * @{ + */ +#define FUART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ +/** + * @} + */ /* End of group FUART_RxInterrupt */ + + +/** + * @defgroup FUART_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +/** + * @defgroup FUART_OVER_RUN_ErrorInterrupt Over Run Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_OV_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_OV_ERR_INT_ENABLE ((uint32_t)0x00000400) /*!< Enable */ +/** + * @} + */ /* End of group FUART_OVER_RUN_ErrorInterrupt */ + +/** + * @defgroup FUART_BREAK_ErrorInterrupt Break Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_BK_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_BK_ERR_INT_ENABLE ((uint32_t)0x00000200) /*!< Enable */ +/** + * @} + */ /* End of group FUART_BREAK_ErrorInterrupt */ + +/** + * @defgroup FUART_PARITY_ErrorInterrupt Parity Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_PA_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_PA_ERR_INT_ENABLE ((uint32_t)0x00000100) /*!< Enable */ +/** + * @} + */ /* End of group FUART_PARITY_ErrorInterrupt */ + +/** + * @defgroup FUART_FRAMING_ErrorInterrupt Framing Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_FR_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_FR_ERR_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group FUART_FRAMING_ErrorInterrupt */ + +/** + * @defgroup FUART_RX_TIMEOUT_ErrorInterrupt Rx Timeout Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_TO_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_TO_ERR_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group FUART_RX_TIMEOUT_RUN_ErrorInterrupt */ +/** + * @} + */ /* End of group FUART_ErrorInterrupt */ + + +/** + * @defgroup FUART_RangeK Range K + * @brief Range of K Macro Definition. + * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= FUART_RANGE_K_MAX)". + * @{ + */ +#define FUART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ +#define FUART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ +/** + * @} + */ /* End of group FUART_RangeK */ + + +/** + * @defgroup FUART_RangeN Range N + * @brief Range of N Macro Definition. + * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= FUART_RANGE_N_MAX)". + * @{ + */ +#define FUART_RANGE_N_MIN ((uint32_t)0x00000002) /*!< Minimum Value :N=2 */ +#define FUART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ +/** + * @} + */ /* End of group FUART_RangeN */ + + +/** + * @defgroup FUART_OverrunErr Overrun Error + * @brief Overrun Error Macro Definition. + * @{ + */ +#define FUART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ +/** + * @} + */ /* End of group FUART_OverrunErr */ + + +/** + * @defgroup FUART_BreakErr Break Error + * @brief Break Error Macro Definition. + * @{ + */ +#define FUART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_BREAK_ERR ((uint32_t)0x00000004) /*!< Error */ +/** + * @} + */ /* End of group FUART_BreakErr */ + + +/** + * @defgroup FUART_ParityErr Parity Error + * @brief Parity Error Macro Definition. + * @{ + */ +#define FUART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_PARITY_ERR ((uint32_t)0x00000002) /*!< Error */ +/** + * @} + */ /* End of group FUART_ParityErr */ + + +/** + * @defgroup FUART_FramingErr Framing Error + * @brief Framing Error Macro Definition. + * @{ + */ +#define FUART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_FRAMING_ERR ((uint32_t)0x00000001) /*!< Error */ +/** + * @} + */ /* End of group FUART_FramingErr */ + +/** + * @defgroup FUARTxFR FUARTxFR Register + * @brief FUARTxFR Register Definition. + * @{ + */ +/* FR */ +#define FUARTxFR_TXFE_MASK ((uint32_t)0x00000080) /*!< TXFE :Mask */ +#define FUARTxFR_RXFF_MASK ((uint32_t)0x00000040) /*!< RXFF :Mask */ +#define FUARTxFR_TXFF_MASK ((uint32_t)0x00000020) /*!< TXFF :Mask */ +#define FUARTxFR_RXFE_MASK ((uint32_t)0x00000010) /*!< RXFE :Mask */ +#define FUARTxFR_BUSY_MASK ((uint32_t)0x00000008) /*!< BUSY :Mask */ +#define FUARTxFR_CTS_MASK ((uint32_t)0x00000001) /*!< CTS :Mask */ + +#define FUARTxFR_TXFE_FLAG_SET ((uint32_t)0x00000080) /*!< TXFE :Flag Set */ +#define FUARTxFR_RXFF_FLAG_SET ((uint32_t)0x00000040) /*!< RXFF :Flag Set */ +#define FUARTxFR_TXFF_FLAG_SET ((uint32_t)0x00000020) /*!< TXFF :Flag Set */ +#define FUARTxFR_RXFE_FLAG_SET ((uint32_t)0x00000010) /*!< RXFE :Flag Set */ +#define FUARTxFR_BUSY_FLAG_SET ((uint32_t)0x00000008) /*!< BUSY :Flag Set */ +#define FUARTxFR_CTS_FLAG_SET ((uint32_t)0x00000001) /*!< CTS :Flag Set */ + +#define FUARTxFR_TXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFE :Flag Clear */ +#define FUARTxFR_RXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFF :Flag Clear */ +#define FUARTxFR_TXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFF :Flag Clear */ +#define FUARTxFR_RXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFE :Flag Clear */ +#define FUARTxFR_BUSY_FLAG_CLR ((uint32_t)0x00000000) /*!< BUSY :Flag Clear */ +#define FUARTxFR_CTS_FLAG_CLR ((uint32_t)0x00000000) /*!< CTS :Flag Clear */ +/** + * @} + */ /* End of group FUARTxFR */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_define FUART Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_typedef FUART Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} fuart_receive_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} fuart_transmit_t; + +/*----------------------------------*/ +/** + * @brief Boudrate setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t brk; /*!< Division Value K. + : K Range ( FUART_RANGE_K_MIN <= K =< FUART_RANGE_K_MAX ) @ref FUART_RangeK */ + uint32_t brn; /*!< Division Value N. + : N Range ( FUART_RANGE_N_MIN <= N =< FUART_RANGE_N_MAX ) @ref FUART_RangeN */ +} fuart_boudrate_t; + +/*----------------------------------*/ +/** + * @brief Transmit FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inttx; /*!< Available Transmit Interrupt. + : Use @ref FUART_TxInterrupt */ + uint32_t level; /*!< Transmit Fill Level. + : Use @ref FUART_FIFO_Level */ +} fuart_tx_int_t; + +/*----------------------------------*/ +/** + * @brief Receive FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intrx; /*!< Available Receive Interrupt. + : Use @ref FUART_RxInterrupt */ + uint32_t level; /*!< Receive Fill Level. + : Use @ref FUART_FIFO_Level */ +} fuart_rx_int_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + fuart_boudrate_t boudrate; /*!< Boudrate setting. + : Use @ref fuart_boudrate_t */ + uint32_t interr; /*!< Available Error Interrupt. + : Use @ref FUART_ErrorInterrupt */ + fuart_tx_int_t tx_int; /*!< Transmit Interrupt setting. + : Use @ref fuart_tx_int_t */ + fuart_rx_int_t rx_int; /*!< Receive Interrupt setting. + : Use @ref fuart_rx_int_t */ + uint32_t ctse; /*!< Available CTS Handshake. + : Use @ref FUART_CTSHandshake */ + uint32_t rtse; /*!< Available RTS Handshake. + : Use @ref FUART_RTSHandshake */ + uint32_t stpa; /*!< Enable/Disable Static Parity. + : Use @ref FUART_StaticParityEnable */ + uint32_t sm; /*!< Data Length. + : Use @ref FUART_DataLength */ + uint32_t fifo; /*!< Available FIFO. + : Use @ref FUART_FIFO */ + uint32_t sblen; /*!< Stop Bit. + : Use @ref FUART_StopBit */ + uint32_t even; /*!< Odd/Even Parity Bit. + : Use @ref FUART_ParityBit */ + uint32_t pe; /*!< Enable/Disable Parity Bit. + : Use @ref FUART_ParityEnable */ +} fuart_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief FUART handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_FURT_TypeDef *p_instance; /*!< Registers base address. */ + fuart_initial_setting_t init; /*!< Initial setting. */ + /*------------------------------------------*/ + /*! + @brief Transmit Information. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmitted data. */ + fuart_transmit_t info; /*!< Transmit Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Information. + */ + /*------------------------------------------*/ + struct { + uint32_t wp; /*!< Num of received data. */ + fuart_receive_t info; /*!< Receive Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result, fuart_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} fuart_t; + +/** + * @} + */ /* End of group FUART_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_functions FUART Exported Functions + * @{ + */ +TXZ_Result fuart_init(fuart_t *p_obj); +TXZ_Result fuart_deinit(fuart_t *p_obj); +TXZ_Result fuart_discard_transmit(fuart_t *p_obj); +TXZ_Result fuart_discard_receive(fuart_t *p_obj); +TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info); +TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info); +void fuart_transmit_irq_handler(fuart_t *p_obj); +void fuart_receive_irq_handler(fuart_t *p_obj); +void fuart_error_irq_handler(fuart_t *p_obj); +void fuart_irq_handler(fuart_t *p_obj); +TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status); +TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error); +TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_setting); +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_ex.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_ex.h new file mode 100644 index 00000000000..d35c9c36352 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_ex.h @@ -0,0 +1,109 @@ +/** + ******************************************************************************* + * @file txz_fuart_ex.h + * @brief This file provides all the functions prototypes for FUART driver. + * @brief Extended functionality. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FUART_EX_H +#define __FUART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +#include "txz_fuart.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FUART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_functions + * @{ + */ +TXZ_Result fuart_send_break(fuart_t *p_obj); +TXZ_Result fuart_stop_break(fuart_t *p_obj); +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __FUART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_include.h new file mode 100644 index 00000000000..d4e3b95364b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_include.h @@ -0,0 +1,385 @@ +/** + ******************************************************************************* + * @file txz_fuart_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FUART_INCLUDE_H +#define __FUART_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FUART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/** + * @defgroup FUART_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define FUART_NULL ((void *)0) /*!< Null Pointer. */ +/** + * @} + */ /* End of group FUART_NullPointer */ + +/** + * @defgroup FUART_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define FUART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define FUART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group FUART_ParameterResult */ + +/** + * @defgroup FUARTxDR FUARTxDR Register + * @brief FUARTxDR Register Definition. + * @{ + */ +/* DR */ +#define FUARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +/** + * @} + */ /* End of group FUARTxDR */ + +/** + * @defgroup FUARTxCR FUARTxCR Register + * @brief FUARTxCR Register Definition. + * @{ + */ +#define FUARTxCR_CTSEN_MASK ((uint32_t)0x00008000) /*!< CTSEN :MASK. */ +#define FUARTxCR_RTSEN_MASK ((uint32_t)0x00004000) /*!< RTSEN :MASK. */ +#define FUARTxCR_RXE_MASK ((uint32_t)0x00000200) /*!< RXE :MASK. */ +#define FUARTxCR_TXE_MASK ((uint32_t)0x00000100) /*!< TXE :MASK. */ +#define FUARTxCR_UARTEN_MSK ((uint32_t)0x00000001) /*!< UARTEN :MASK. */ + +#define FUARTxCR_CTSEN_DISABLE ((uint32_t)0x00000000) /*!< CTSEN :Not Available. */ +#define FUARTxCR_RTSEN_DISABLE ((uint32_t)0x00000000) /*!< RTSEN :Not Available. */ +#define FUARTxCR_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable. */ +#define FUARTxCR_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable. */ +#define FUARTxCR_UARTEN_DISABLE ((uint32_t)0x00000000) /*!< UARTEN :Disable. */ + +#define FUARTxCR_CTSEN_ENABLE ((uint32_t)0x00008000) /*!< CTSEN :Available. */ +#define FUARTxCR_RTSEN_ENABLE ((uint32_t)0x00004000) /*!< RTSEN :Available. */ +#define FUARTxCR_RXE_ENABLE ((uint32_t)0x00000200) /*!< RXE :Enable. */ +#define FUARTxCR_TXE_ENABLE ((uint32_t)0x00000100) /*!< TXE :Enable. */ +#define FUARTxCR_UARTEN_ENABLE ((uint32_t)0x00000001) /*!< UARTEN :Enable. */ +/** + * @} + */ /* End of group FUARTxRSR */ + +/** + * @defgroup FUARTxRSR FUARTxRSR Register + * @brief FUARTxRSR Register Definition. + * @{ + */ +#define FUARTxRSR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */ +#define FUARTxRSR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */ +#define FUARTxRSR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */ +#define FUARTxRSR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */ + +#define FUARTxRSR_OE_ERR ((uint32_t)0x00000008) /*!< OE :Error */ +#define FUARTxRSR_BE_ERR ((uint32_t)0x00000004) /*!< BE :Error */ +#define FUARTxRSR_PE_ERR ((uint32_t)0x00000002) /*!< PE :Error */ +#define FUARTxRSR_FE_ERR ((uint32_t)0x00000001) /*!< FE :Error */ +/** + * @} + */ /* End of group FUARTxRSR */ + +/** + * @defgroup FUARTxECR FUARTxECR Register + * @brief FUARTxECR Register Definition. + * @{ + */ +/* ECR */ +#define FUARTxECR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */ +#define FUARTxECR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */ +#define FUARTxECR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */ +#define FUARTxECR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */ + +#define FUARTxECR_OE_CLR ((uint32_t)0x00000008) /*!< OE :Clear */ +#define FUARTxECR_BE_CLR ((uint32_t)0x00000004) /*!< BE :Clear */ +#define FUARTxECR_PE_CLR ((uint32_t)0x00000002) /*!< PE :Clear */ +#define FUARTxECR_FE_CLR ((uint32_t)0x00000001) /*!< FE :Clear */ + +/** + * @} + */ /* End of group FUARTxECR */ + +/** + * @defgroup FUARTxLCR_H FUARTxRSR Register + * @brief FUARTxLCR_H Register Definition. + * @{ + */ +#define FUARTxLCR_H_BRK_MASK ((uint32_t)0x00000001) /*!< BRK :Mask */ + +#define FUARTxLCR_H_BRK_SEND ((uint32_t)0x00000001) /*!< BRK :Send */ +#define FUARTxLCR_H_BRK_STOP ((uint32_t)0x00000000) /*!< BRK :Stop */ +/** + * @} + */ /* End of group FUARTxLCR_H */ + +/** + * @defgroup FUARTxRIS FUARTxRIS Register + * @brief FUARTxRIS Register Definition. + * @{ + */ +#define FUARTxRIS_OERIS_MASK ((uint32_t)0x00000400) /*!< OERIS :Mask */ +#define FUARTxRIS_BERIS_MASK ((uint32_t)0x00000200) /*!< BERIS :Mask */ +#define FUARTxRIS_PERIS_MASK ((uint32_t)0x00000100) /*!< PRRIS :Mask */ +#define FUARTxRIS_FERIS_MASK ((uint32_t)0x00000080) /*!< FERIS :Mask */ +#define FUARTxRIS_RTRIS_MASK ((uint32_t)0x00000040) /*!< RTRIS :Mask */ +#define FUARTxRIS_TXRIS_MASK ((uint32_t)0x00000020) /*!< TXRIS :Mask */ +#define FUARTxRIS_RXRIS_MASK ((uint32_t)0x00000010) /*!< RXRIS :Mask */ + +#define FUARTxRIS_OERIS_REQ ((uint32_t)0x00000400) /*!< OERIS :Request */ +#define FUARTxRIS_BERIS_REQ ((uint32_t)0x00000200) /*!< BERIS :Request */ +#define FUARTxRIS_PERIS_REQ ((uint32_t)0x00000100) /*!< PRRIS :Request */ +#define FUARTxRIS_FERIS_REQ ((uint32_t)0x00000080) /*!< FERIS :Request */ +#define FUARTxRIS_RTRIS_REQ ((uint32_t)0x00000040) /*!< RTRIS :Request */ +#define FUARTxRIS_TXRIS_REQ ((uint32_t)0x00000020) /*!< TXRIS :Request */ +#define FUARTxRIS_RXRIS_REQ ((uint32_t)0x00000010) /*!< RXRIS :Request */ + +/** + * @} + */ /* End of group FUARTxRIS */ + +/** + * @defgroup FUARTxMIS FUARTxMIS Register + * @brief FUARTxMIS Register Definition. + * @{ + */ +#define FUARTxMIS_OEMIS_MASK ((uint32_t)0x00000400) /*!< OEMIS :Mask */ +#define FUARTxMIS_BEMIS_MASK ((uint32_t)0x00000200) /*!< BEMIS :Mask */ +#define FUARTxMIS_PEMIS_MASK ((uint32_t)0x00000100) /*!< PRMIS :Mask */ +#define FUARTxMIS_FEMIS_MASK ((uint32_t)0x00000080) /*!< FEMIS :Mask */ +#define FUARTxMIS_RTMIS_MASK ((uint32_t)0x00000040) /*!< RTMIS :Mask */ +#define FUARTxMIS_TXMIS_MASK ((uint32_t)0x00000020) /*!< TXMIS :Mask */ +#define FUARTxMIS_RXMIS_MASK ((uint32_t)0x00000010) /*!< RXMIS :Mask */ + +#define FUARTxMIS_OEMIS_REQ ((uint32_t)0x00000400) /*!< OEMIS :Request */ +#define FUARTxMIS_BEMIS_REQ ((uint32_t)0x00000200) /*!< BEMIS :Request */ +#define FUARTxMIS_PEMIS_REQ ((uint32_t)0x00000100) /*!< PRMIS :Request */ +#define FUARTxMIS_FEMIS_REQ ((uint32_t)0x00000080) /*!< FEMIS :Request */ +#define FUARTxMIS_RTMIS_REQ ((uint32_t)0x00000040) /*!< RTMIS :Request */ +#define FUARTxMIS_TXMIS_REQ ((uint32_t)0x00000020) /*!< TXMIS :Request */ +#define FUARTxMIS_RXMIS_REQ ((uint32_t)0x00000010) /*!< RXMIS :Request */ + +/** + * @} + */ /* End of group FUARTxMIS */ + +/** + * @defgroup FUARTxICR FUARTxICR Register + * @brief FUARTxICR Register Definition. + * @{ + */ +#define FUARTxICR_OEIC_MASK ((uint32_t)0x00000400) /*!< OEIC :Mask */ +#define FUARTxICR_BEIC_MASK ((uint32_t)0x00000200) /*!< BEIC :Mask */ +#define FUARTxICR_PEIC_MASK ((uint32_t)0x00000100) /*!< PRIC :Mask */ +#define FUARTxICR_FEIC_MASK ((uint32_t)0x00000080) /*!< FEIC :Mask */ +#define FUARTxICR_RTIC_MASK ((uint32_t)0x00000040) /*!< RTIC :Mask */ +#define FUARTxICR_TXIC_MASK ((uint32_t)0x00000020) /*!< TXIC :Mask */ +#define FUARTxICR_RXIC_MASK ((uint32_t)0x00000010) /*!< RXIC :Mask */ + +#define FUARTxICR_OEIC_CLR ((uint32_t)0x00000400) /*!< OEIC :Request */ +#define FUARTxICR_BEIC_CLR ((uint32_t)0x00000200) /*!< BEIC :Request */ +#define FUARTxICR_PEIC_CLR ((uint32_t)0x00000100) /*!< PRIC :Request */ +#define FUARTxICR_FEIC_CLR ((uint32_t)0x00000080) /*!< FEIC :Request */ +#define FUARTxICR_RTIC_CLR ((uint32_t)0x00000040) /*!< RTIC :Request */ +#define FUARTxICR_TXIC_CLR ((uint32_t)0x00000020) /*!< TXIC :Request */ +#define FUARTxICR_RXIC_CLR ((uint32_t)0x00000010) /*!< RXIC :Request */ + +/** + * @} + */ /* End of group FUARTxICR */ + +/** + * @defgroup FUARTxDMACR FUARTxDMACR Register + * @brief FUARTxDMACR Register Definition. + * @{ + */ +#define FUARTxDMACR_RXDMAE_MASK ((uint32_t)0x00000001) /*!< RXDMAE :Mask */ +#define FUARTxDMACR_TXDMAE_MASK ((uint32_t)0x00000002) /*!< TXDMAE :Mask */ + +#define FUARTxDMACR_RXDMAE_ENABLE ((uint32_t)0x00000001) /*!< RXDMAE :Enable */ +#define FUARTxDMACR_TXDMAE_ENABLE ((uint32_t)0x00000002) /*!< TXDMAE :Enable */ + +#define FUARTxDMACR_RXDMAE_DISABLE ((uint32_t)0x00000000) /*!< RXDMAE :Disable */ +#define FUARTxDMACR_TXDMAE_DISABLE ((uint32_t)0x00000000) /*!< TXDMAE :Disable */ +/** + * @} + */ /* End of group FUARTxDMACR */ + + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_functions + * @{ + */ +__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance); +__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance); +__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance); +__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance); +/*--------------------------------------------------*/ +/** + * @brief Disable FUARTxCR TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable FUARTxCR TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 1; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable FUARTxCR RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable FUARTxCR RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 1; +#endif +} + + +/** + * @} + */ /* End of group FUART_Private_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio.h new file mode 100644 index 00000000000..ce1926f2898 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio.h @@ -0,0 +1,178 @@ +/** + ******************************************************************************* + * @file txz_gpio.h + * @brief This file provides all the functions prototypes for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __GPIO_H +#define __GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +/** @defgroup Device_Included Device Included + * @{ + */ +#include "txz_gpio_M4GR.h" + +/** + * @} + */ /* End of group Device_Included */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_define GPIO Exported Define + * @{ + */ +#define CHECK_MASK(mode, mask) ((1 << ((mode)/4)) & (mask)) +#define WRITE_PORT(mode, addr, val, mask) \ + do { \ + if(CHECK_MASK(mode, mask)) *((uint32_t*)(addr) + (mode)/4) = (val); \ + }while(0) +#define READ_PORT(mode, addr, val, mask) \ + do { \ + if(CHECK_MASK(mode, mask)) (*(val)) = (*((uint32_t*)(addr) + (mode)/4)); \ + }while(0) + +/** + * @defgroup GPIO_Result Result + * @brief GPIO Result Macro Definition. + * @{ + */ +#define GPIO_RESULT_SUCCESS (0) /*!< Success */ +#define GPIO_RESULT_FAILURE (-1) /*!< Failure */ +#define GPIO_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ +/** + * @} + */ /* End of group GPIO_Result */ + +/** + * @} + */ /* End of group GPIO_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ + +/** + * @enum gpio_pinstate_t + * @brief Pin State Reset/Set Enumerated Type Definition. + */ +typedef enum { + GPIO_PIN_RESET = 0, /*!< 0: Clear */ + GPIO_PIN_SET, /*!< 1: Set */ +} gpio_pinstate_t; + +/** + * @enum gpio_pininout_t + * @brief Pin Input/Output Enumerated Type Definition. + */ +typedef enum { + GPIO_PIN_INPUT = 0, /*!< 0: Input */ + GPIO_PIN_OUTPUT, /*!< 1: Output */ + GPIO_PIN_INOUT, /*!< 2: Input/Output */ + GPIO_PIN_NOTINOUT, /*!< 3: Not Input/Output */ +} gpio_pininout_t; + +/** + * @enum gpio_mode_t + * @brief Port Mode Enumerated Type Definition. + */ +typedef enum { + GPIO_Mode_DATA = 0x0, /*!< 0x0: PxDATA */ + GPIO_Mode_CR = 0x4, /*!< 0x4: PxCR */ + GPIO_Mode_FR1 = 0x8, /*!< 0x8: PxFR1 */ + GPIO_Mode_FR2 = 0xC, /*!< 0xC: PxFR2 */ + GPIO_Mode_FR3 = 0x10, /*!< 0x10: PxFR3 */ + GPIO_Mode_FR4 = 0x14, /*!< 0x14: PxFR4 */ + GPIO_Mode_FR5 = 0x18, /*!< 0x18: PxFR5 */ + GPIO_Mode_FR6 = 0x1C, /*!< 0x1C: PxFR6 */ + GPIO_Mode_FR7 = 0x20, /*!< 0x20: PxFR7 */ + GPIO_Mode_FR8 = 0x24, /*!< 0x24: PxFR8 */ + GPIO_Mode_OD = 0x28, /*!< 0x28: PxOD */ + GPIO_Mode_PUP = 0x2C, /*!< 0x2C: PxPUP */ + GPIO_Mode_PDN = 0x30, /*!< 0x30: PxPDN */ + GPIO_Mode_IE = 0x38 /*!< 0x38: PxIE */ +} gpio_mode_t; + +/** + * @enum gpio_mode_num + * @brief Port Mode Enumerated Num(bit num). + */ +typedef enum { + GPIO_ModeNum_DATA = 0, /*!< 0: PxDATA */ + GPIO_ModeNum_CR, /*!< 1: PxCR */ + GPIO_ModeNum_FR1, /*!< 2: PxFR1 */ + GPIO_ModeNum_FR2, /*!< 3: PxFR2 */ + GPIO_ModeNum_FR3, /*!< 4: PxFR3 */ + GPIO_ModeNum_FR4, /*!< 5: PxFR4 */ + GPIO_ModeNum_FR5, /*!< 6: PxFR5 */ + GPIO_ModeNum_FR6, /*!< 7: PxFR6 */ + GPIO_ModeNum_FR7, /*!< 8: PxFR7 */ + GPIO_ModeNum_FR8, /*!< 9: PxFR8 */ + GPIO_ModeNum_OD, /*!< 10: PxOD */ + GPIO_ModeNum_PUP, /*!< 11: PxPUP */ + GPIO_ModeNum_PDN, /*!< 12: PxPDN */ + GPIO_ModeNum_IE, /*!< 13: PxIE */ + GPIO_ModeNum_Max, /*!< 14: Max */ +} gpio_mode_num; +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_functions GPIO Exported Functions + * @{ + */ +TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group); +TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group); +TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val); +TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val); +TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout); +TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); +TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); +TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); +TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val); +TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate); + +/** + * @} + */ /* End of group GPIO_Exported_functions */ + +/** + * @} + */ /* End of group GPIO */ + +#ifdef __cplusplus +} +#endif +#endif /* __GPIO_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio_M4GR.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio_M4GR.h new file mode 100644 index 00000000000..f42e9b7dfcc --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio_M4GR.h @@ -0,0 +1,2731 @@ +/** + ******************************************************************************* + * @file txz_gpio_M4GR.h + * @brief This file provides all the functions prototypes for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __GPIO_M4GR_H +#define __GPIO_M4GR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup GPIO GPIO + * @brief GPIO Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_define GPIO Exported Define + * @{ + */ +/*PinExist define*/ +/* PortA */ +#define GPIO_PORT_A_0 (0x3DDF) +#define GPIO_PORT_A_1 (0x3D57) +#define GPIO_PORT_A_2 (0x3D17) +#define GPIO_PORT_A_3 (0x3DDF) +#define GPIO_PORT_A_4 (0x3DDF) +#define GPIO_PORT_A_5 (0x3DD7) +#define GPIO_PORT_A_6 (0x3D97) +#define GPIO_PORT_A_7 (0x3DDF) +/* PortB */ +#define GPIO_PORT_B_0 (0x3C7F) +#define GPIO_PORT_B_1 (0x3CDF) +#define GPIO_PORT_B_2 (0x3C57) +#define GPIO_PORT_B_3 (0x3C17) +#define GPIO_PORT_B_4 (0x3C77) +#define GPIO_PORT_B_5 (0x3C37) +#define GPIO_PORT_B_6 (0x3C7F) +#define GPIO_PORT_B_7 (0x3C7F) +/* PortC */ +#define GPIO_PORT_C_0 (0x3C77) +#define GPIO_PORT_C_1 (0x3C77) +#define GPIO_PORT_C_2 (0x3C77) +#define GPIO_PORT_C_3 (0x3C37) +#define GPIO_PORT_C_4 (0x3C57) +#define GPIO_PORT_C_5 (0x3C17) +#define GPIO_PORT_C_6 (0x3C07) +#define GPIO_PORT_C_7 (0x3C07) +/* PortD */ +#define GPIO_PORT_D_0 (0x3DFF) +#define GPIO_PORT_D_1 (0x3D7F) +#define GPIO_PORT_D_2 (0x3F77) +#define GPIO_PORT_D_3 (0x3F37) +#define GPIO_PORT_D_4 (0x3FD7) +#define GPIO_PORT_D_5 (0x3F97) +#define GPIO_PORT_D_6 (0x3FDF) +#define GPIO_PORT_D_7 (0x3FDF) +/* PortE */ +#define GPIO_PORT_E_0 (0x3F7F) +#define GPIO_PORT_E_1 (0x3F77) +#define GPIO_PORT_E_2 (0x3F77) +#define GPIO_PORT_E_3 (0x3F77) +#define GPIO_PORT_E_4 (0x3EF7) +#define GPIO_PORT_E_5 (0x3EF7) +#define GPIO_PORT_E_6 (0x3EF7) +#define GPIO_PORT_E_7 (0x3EFF) +/* PortF */ +#define GPIO_PORT_F_0 (0x3C07) +#define GPIO_PORT_F_1 (0x3C07) +#define GPIO_PORT_F_2 (0x3D83) +#define GPIO_PORT_F_3 (0x3D83) +#define GPIO_PORT_F_4 (0x3C07) +#define GPIO_PORT_F_5 (0x3C07) +#define GPIO_PORT_F_6 (0x3C07) +#define GPIO_PORT_F_7 (0x3C67) +/* PortG */ +#define GPIO_PORT_G_0 (0x3C57) +#define GPIO_PORT_G_1 (0x3C57) +#define GPIO_PORT_G_2 (0x3DF3) +#define GPIO_PORT_G_3 (0x3DF3) +#define GPIO_PORT_G_4 (0x3DEB) +#define GPIO_PORT_G_5 (0x3DFB) +#define GPIO_PORT_G_6 (0x3CE7) +#define GPIO_PORT_G_7 (0x3C67) +/* PortH */ +#define GPIO_PORT_H_0 (0x3C77) +#define GPIO_PORT_H_1 (0x3C77) +#define GPIO_PORT_H_2 (0x3C77) +#define GPIO_PORT_H_3 (0x3C77) +#define GPIO_PORT_H_4 (0x3C57) +#define GPIO_PORT_H_5 (0x3C57) +#define GPIO_PORT_H_6 (0x3C57) +#define GPIO_PORT_H_7 (0x3C57) +/* PortJ */ +#define GPIO_PORT_J_0 (0x3C53) +#define GPIO_PORT_J_1 (0x3C53) +#define GPIO_PORT_J_2 (0x3DD3) +#define GPIO_PORT_J_3 (0x3DD3) +#define GPIO_PORT_J_4 (0x3C5B) +#define GPIO_PORT_J_5 (0x3C5B) +#define GPIO_PORT_J_6 (0x3DC3) +#define GPIO_PORT_J_7 (0x3DC3) +/* PortK */ +#define GPIO_PORT_K_0 (0x3C9F) +#define GPIO_PORT_K_1 (0x3CFF) +#define GPIO_PORT_K_2 (0x3C87) +#define GPIO_PORT_K_3 (0x3C87) +#define GPIO_PORT_K_4 (0x3CA7) +#define GPIO_PORT_K_5 (0x3CA7) +#define GPIO_PORT_K_6 (0x3CBF) +#define GPIO_PORT_K_7 (0x3DBB) +/* PortL */ +#define GPIO_PORT_L_0 (0x3DDB) +#define GPIO_PORT_L_1 (0x3D43) +#define GPIO_PORT_L_2 (0x3D43) +#define GPIO_PORT_L_3 (0x3DDB) +#define GPIO_PORT_L_4 (0x3C1B) +#define GPIO_PORT_L_5 (0x3C0B) +#define GPIO_PORT_L_6 (0x3C1B) +#define GPIO_PORT_L_7 (0x3C0F) +/* PortM */ +#define GPIO_PORT_M_0 (0x3DE7) +#define GPIO_PORT_M_1 (0x3DE7) +#define GPIO_PORT_M_2 (0x3DDB) +#define GPIO_PORT_M_3 (0x3DEB) +#define GPIO_PORT_M_4 (0x3DAB) +#define GPIO_PORT_M_5 (0x3D9B) +#define GPIO_PORT_M_6 (0x3DFF) +#define GPIO_PORT_M_7 (0x3DEF) +/* PortN */ +#define GPIO_PORT_N_0 (0x3C03) +#define GPIO_PORT_N_1 (0x3C03) +#define GPIO_PORT_N_2 (0x3C03) +#define GPIO_PORT_N_3 (0x3C03) +#define GPIO_PORT_N_4 (0x3C03) +#define GPIO_PORT_N_5 (0x3C03) +#define GPIO_PORT_N_6 (0x3C03) +#define GPIO_PORT_N_7 (0x3C03) +/* PortP */ +#define GPIO_PORT_P_0 (0x3C5B) +#define GPIO_PORT_P_1 (0x3C5B) +#define GPIO_PORT_P_2 (0x3C5B) +#define GPIO_PORT_P_3 (0x3C5B) +#define GPIO_PORT_P_4 (0x3C5B) +#define GPIO_PORT_P_5 (0x3C5B) +#define GPIO_PORT_P_6 (0x3C5B) +#define GPIO_PORT_P_7 (0x3C5B) +/* PortR */ +#define GPIO_PORT_R_0 (0x3C1B) +#define GPIO_PORT_R_1 (0x3C1B) +#define GPIO_PORT_R_2 (0x3C1B) +#define GPIO_PORT_R_3 (0x3C1B) +#define GPIO_PORT_R_4 (0x3C1B) +#define GPIO_PORT_R_5 (0x3C1B) +#define GPIO_PORT_R_6 (0x3C1B) +#define GPIO_PORT_R_7 (0x3C1B) +/* PortT */ +#define GPIO_PORT_T_0 (0x3C03) +#define GPIO_PORT_T_1 (0x3C03) +#define GPIO_PORT_T_2 (0x3D03) +#define GPIO_PORT_T_3 (0x3C9F) +#define GPIO_PORT_T_4 (0x3C03) +#define GPIO_PORT_T_5 (0x3C0B) +#define GPIO_PORT_T_6 (0x0000) +#define GPIO_PORT_T_7 (0x0000) +/* PortU */ +#define GPIO_PORT_U_0 (0x3D1B) +#define GPIO_PORT_U_1 (0x3D0B) +#define GPIO_PORT_U_2 (0x3D9B) +#define GPIO_PORT_U_3 (0x3D9B) +#define GPIO_PORT_U_4 (0x3D9B) +#define GPIO_PORT_U_5 (0x3D9B) +#define GPIO_PORT_U_6 (0x3D9B) +#define GPIO_PORT_U_7 (0x3D8B) +/* PortV */ +#define GPIO_PORT_V_0 (0x3DDB) +#define GPIO_PORT_V_1 (0x3DDB) +#define GPIO_PORT_V_2 (0x3DDB) +#define GPIO_PORT_V_3 (0x3DCB) +#define GPIO_PORT_V_4 (0x3DEF) +#define GPIO_PORT_V_5 (0x3DFF) +#define GPIO_PORT_V_6 (0x3D7B) +#define GPIO_PORT_V_7 (0x3DEB) +/* PortW */ +#define GPIO_PORT_W_0 (0x3CE3) +#define GPIO_PORT_W_1 (0x3D63) +#define GPIO_PORT_W_2 (0x3D63) +#define GPIO_PORT_W_3 (0x3C63) +#define GPIO_PORT_W_4 (0x3D53) +#define GPIO_PORT_W_5 (0x3D43) +#define GPIO_PORT_W_6 (0x3D43) +#define GPIO_PORT_W_7 (0x3D53) +/* PortY */ +#define GPIO_PORT_Y_0 (0x3801) +#define GPIO_PORT_Y_1 (0x3801) +#define GPIO_PORT_Y_2 (0x3801) +#define GPIO_PORT_Y_3 (0x3801) +#define GPIO_PORT_Y_4 (0x1C27) +#define GPIO_PORT_Y_5 (0x0000) +#define GPIO_PORT_Y_6 (0x0000) +#define GPIO_PORT_Y_7 (0x0000) + +/* Port Register setting */ +#define PORT_CLOCK_DISABLE_PORTA(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTB(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTC(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTD(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTE(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTF(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTG(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTH(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTJ(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTK(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTL(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTM(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTN(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTP(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTR(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTT(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTU(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTV(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTW(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTY(var) ((var) = 0U) + +#define PORT_CLOCK_ENABLE_PORTA(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTB(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTC(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTD(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTE(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTF(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTG(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTH(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTJ(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTK(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTL(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTM(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTN(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTP(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTR(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTT(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTU(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTV(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTW(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTY(var) ((var) = 1U) + +/* PortA */ +#define INIT_GPIO_PORT_A_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR4(var) +#define INIT_GPIO_PORT_A_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR8(var) +#define INIT_GPIO_PORT_A_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_IE(var) ((var) = 0x00) +/* PortB */ +#define INIT_GPIO_PORT_B_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR7(var) +#define INIT_GPIO_PORT_B_FR8(var) +#define INIT_GPIO_PORT_B_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_IE(var) ((var) = 0x00) +/* PortC */ +#define INIT_GPIO_PORT_C_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR2(var) +#define INIT_GPIO_PORT_C_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR6(var) +#define INIT_GPIO_PORT_C_FR7(var) +#define INIT_GPIO_PORT_C_FR8(var) +#define INIT_GPIO_PORT_C_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_IE(var) ((var) = 0x00) +/* PortD */ +#define INIT_GPIO_PORT_D_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_IE(var) ((var) = 0x00) +/* PortE */ +#define INIT_GPIO_PORT_E_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_IE(var) ((var) = 0x00) +/* PortF */ +#define INIT_GPIO_PORT_F_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR2(var) +#define INIT_GPIO_PORT_F_FR3(var) +#define INIT_GPIO_PORT_F_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR8(var) +#define INIT_GPIO_PORT_F_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_IE(var) ((var) = 0x00) +/* PortG */ +#define INIT_GPIO_PORT_G_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR8(var) +#define INIT_GPIO_PORT_G_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_IE(var) ((var) = 0x00) +/* PortH */ +#define INIT_GPIO_PORT_H_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_CR(var) ((var) = 0x50) +#define INIT_GPIO_PORT_H_FR1(var) ((var) = 0xF8) +#define INIT_GPIO_PORT_H_FR2(var) +#define INIT_GPIO_PORT_H_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_FR6(var) +#define INIT_GPIO_PORT_H_FR7(var) +#define INIT_GPIO_PORT_H_FR8(var) +#define INIT_GPIO_PORT_H_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_PUP(var) ((var) = 0x98) +#define INIT_GPIO_PORT_H_PDN(var) ((var) = 0x20) +#define INIT_GPIO_PORT_H_IE(var) ((var) = 0xB8) +/* PortJ */ +#define INIT_GPIO_PORT_J_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR1(var) +#define INIT_GPIO_PORT_J_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR4(var) +#define INIT_GPIO_PORT_J_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR8(var) +#define INIT_GPIO_PORT_J_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_IE(var) ((var) = 0x00) +/* PortK */ +#define INIT_GPIO_PORT_K_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR8(var) +#define INIT_GPIO_PORT_K_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_IE(var) ((var) = 0x00) +/* PortL */ +#define INIT_GPIO_PORT_L_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR4(var) +#define INIT_GPIO_PORT_L_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR8(var) +#define INIT_GPIO_PORT_L_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_IE(var) ((var) = 0x00) +/* PortM */ +#define INIT_GPIO_PORT_M_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR8(var) +#define INIT_GPIO_PORT_M_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_IE(var) ((var) = 0x00) +/* PortN */ +#define INIT_GPIO_PORT_N_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_FR1(var) +#define INIT_GPIO_PORT_N_FR2(var) +#define INIT_GPIO_PORT_N_FR3(var) +#define INIT_GPIO_PORT_N_FR4(var) +#define INIT_GPIO_PORT_N_FR5(var) +#define INIT_GPIO_PORT_N_FR6(var) +#define INIT_GPIO_PORT_N_FR7(var) +#define INIT_GPIO_PORT_N_FR8(var) +#define INIT_GPIO_PORT_N_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_IE(var) ((var) = 0x00) +/* PortP */ +#define INIT_GPIO_PORT_P_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR1(var) +#define INIT_GPIO_PORT_P_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR4(var) +#define INIT_GPIO_PORT_P_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR6(var) +#define INIT_GPIO_PORT_P_FR7(var) +#define INIT_GPIO_PORT_P_FR8(var) +#define INIT_GPIO_PORT_P_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_IE(var) ((var) = 0x00) +/* PortR */ +#define INIT_GPIO_PORT_R_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_FR1(var) +#define INIT_GPIO_PORT_R_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_FR4(var) +#define INIT_GPIO_PORT_R_FR5(var) +#define INIT_GPIO_PORT_R_FR6(var) +#define INIT_GPIO_PORT_R_FR7(var) +#define INIT_GPIO_PORT_R_FR8(var) +#define INIT_GPIO_PORT_R_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_IE(var) ((var) = 0x00) +/* PortT */ +#define INIT_GPIO_PORT_T_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR4(var) +#define INIT_GPIO_PORT_T_FR5(var) +#define INIT_GPIO_PORT_T_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR8(var) +#define INIT_GPIO_PORT_T_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_IE(var) ((var) = 0x00) +/* PortU */ +#define INIT_GPIO_PORT_U_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR1(var) +#define INIT_GPIO_PORT_U_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR4(var) +#define INIT_GPIO_PORT_U_FR5(var) +#define INIT_GPIO_PORT_U_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR8(var) +#define INIT_GPIO_PORT_U_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_IE(var) ((var) = 0x00) +/* PortV */ +#define INIT_GPIO_PORT_V_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR8(var) +#define INIT_GPIO_PORT_V_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_IE(var) ((var) = 0x00) +/* PortW */ +#define INIT_GPIO_PORT_W_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR1(var) +#define INIT_GPIO_PORT_W_FR2(var) +#define INIT_GPIO_PORT_W_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR8(var) +#define INIT_GPIO_PORT_W_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_IE(var) ((var) = 0x00) +/* PortY */ +#define INIT_GPIO_PORT_Y_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_FR2(var) +#define INIT_GPIO_PORT_Y_FR3(var) +#define INIT_GPIO_PORT_Y_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_FR5(var) +#define INIT_GPIO_PORT_Y_FR6(var) +#define INIT_GPIO_PORT_Y_FR7(var) +#define INIT_GPIO_PORT_Y_FR8(var) +#define INIT_GPIO_PORT_Y_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_IE(var) ((var) = 0x00) +/** + * @} + */ /* End of group GPIO_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ + +/** + * @enum gpio_gr_t + * @brief Port Group Enumerated Type Definition. + */ +typedef enum { + GPIO_PORT_A = 0x0, /*!< 0: PA */ + GPIO_PORT_B, /*!< 1: PB */ + GPIO_PORT_C, /*!< 2: PC */ + GPIO_PORT_D, /*!< 3: PD */ + GPIO_PORT_E, /*!< 4: PE */ + GPIO_PORT_F, /*!< 5: PF */ + GPIO_PORT_G, /*!< 6: PG */ + GPIO_PORT_H, /*!< 7: PH */ + GPIO_PORT_J, /*!< 8: PJ */ + GPIO_PORT_K, /*!< 9: PK */ + GPIO_PORT_L, /*!< 10:PL */ + GPIO_PORT_M, /*!< 11: PM */ + GPIO_PORT_N, /*!< 12: PN */ + GPIO_PORT_P, /*!< 13: PP */ + GPIO_PORT_R, /*!< 14: PR */ + GPIO_PORT_T, /*!< 15: PT */ + GPIO_PORT_U, /*!< 16: PU */ + GPIO_PORT_V, /*!< 17: PV */ + GPIO_PORT_W, /*!< 18: PW */ + GPIO_PORT_Y, /*!< 19: PY */ + GPIO_GROUP_Max /*!< Max Number */ +} gpio_gr_t; + +/** + * @enum gpio_num_t + * @brief Port Number Enumerated Type Definition. + */ +typedef enum { + GPIO_PORT_0 = 0x0, /*!< 0: Port0 */ + GPIO_PORT_1, /*!< 1: Port1 */ + GPIO_PORT_2, /*!< 2: Port2 */ + GPIO_PORT_3, /*!< 3: Port3 */ + GPIO_PORT_4, /*!< 4: Port4 */ + GPIO_PORT_5, /*!< 5: Port5 */ + GPIO_PORT_6, /*!< 6: Port6 */ + GPIO_PORT_7, /*!< 7: Port7 */ + GPIO_PORT_Max /*!< Max Number */ +} gpio_num_t; + +/** + * @enum gpio_fr_t + * @brief Port Function Number Enumerated Type Definition. + */ +typedef enum { + GPIO_FR_1 = 1, /*!< 1: PxFR1 */ + GPIO_FR_2, /*!< 2: PxFR2 */ + GPIO_FR_3, /*!< 3: PxFR3 */ + GPIO_FR_4, /*!< 4: PxFR4 */ + GPIO_FR_5, /*!< 5: PxFR5 */ + GPIO_FR_6, /*!< 6: PxFR6 */ + GPIO_FR_7, /*!< 7: PxFR7 */ + GPIO_FR_8, /*!< 8: PxFR8 */ + GPIO_FR_NA, /*!< 9: N/A */ + GPIO_FR_Max, /*!< Max Number */ +} gpio_fr_t; + +/** + * @enum gpio_pa0_func_t + * @brief PortA0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA0_INT02a = 0, /*!< 0: INT02a */ + GPIO_PA0_EA00 = GPIO_FR_1, /*!< PAFR1: EA00 */ + GPIO_PA0_T32A00INB1 = GPIO_FR_2, /*!< PAFR2: T32A00INB1 */ + GPIO_PA0_T32A00INA0 = GPIO_FR_3, /*!< PAFR3: T32A00INA0 */ + GPIO_PA0_T32A00INC0 = GPIO_FR_5, /*!< PAFR5: T32A00INC0 */ + GPIO_PA0_TSPI0CSIN = GPIO_FR_6, /*!< PAFR6: TSPI0CSIN */ + GPIO_PA0_TSPI0CS0 = GPIO_FR_7, /*!< PAFR7: TSPI0CS0 */ +} gpio_pa0_func_t; + +/** + * @enum gpio_pa1_func_t + * @brief PortA1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA1_EA01 = GPIO_FR_1, /*!< PAFR1: EA01 */ + GPIO_PA1_T32A00OUTA = GPIO_FR_3, /*!< PAFR3: T32A00OUTA */ + GPIO_PA1_T32A00OUTC = GPIO_FR_5, /*!< PAFR5: T32A00OUTC */ + GPIO_PA1_TSPI0SCK = GPIO_FR_7, /*!< PAFR7: TSPI0SCK */ +} gpio_pa1_func_t; + +/** + * @enum gpio_pa2_func_t + * @brief PortA2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA2_EA02 = GPIO_FR_1, /*!< PAFR1: EA02 */ + GPIO_PA2_T32A00OUTB = GPIO_FR_3, /*!< PAFR3: T32A00OUTB */ + GPIO_PA2_TSPI0RXD = GPIO_FR_7, /*!< PAFR7: TSPI0RXD */ +} gpio_pa2_func_t; + +/** +* @enum gpio_pa3_func_t +* @brief PortA3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PA3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA3_EA03 = GPIO_FR_1, /*!< PAFR1: EA03 */ + GPIO_PA3_T32A00INA1 = GPIO_FR_2, /*!< PAFR2: T32A00INA1 */ + GPIO_PA3_T32A00INB0 = GPIO_FR_3, /*!< PAFR3: T32A00INB0 */ + GPIO_PA3_T32A00INC1 = GPIO_FR_5, /*!< PAFR5: T32A00INC1 */ + GPIO_PA3_TSPI2CS1 = GPIO_FR_6, /*!< PAFR6: TSPI2CS1 */ + GPIO_PA3_TSPI0TXD = GPIO_FR_7, /*!< PAFR7: TSPI0TXD */ +} gpio_pa3_func_t; + +/** +* @enum gpio_pa4_func_t +* @brief PortA4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PA4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA4_EA04 = GPIO_FR_1, /*!< PAFR1: EA04 */ + GPIO_PA4_T32A01INB1 = GPIO_FR_2, /*!< PAFR2: T32A01INB1 */ + GPIO_PA4_T32A01INA0 = GPIO_FR_3, /*!< PAFR3: T32A01INA0 */ + GPIO_PA4_T32A01INC0 = GPIO_FR_5, /*!< PAFR5: T32A01INC0 */ + GPIO_PA4_TSPI0CS1 = GPIO_FR_6, /*!< PAFR6: TSPI0CS1 */ + GPIO_PA4_TSPI2TXD = GPIO_FR_7, /*!< PAFR7: TSPI2TXD */ +} gpio_pa4_func_t; + +/** + * @enum gpio_pa5_func_t + * @brief PortA5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA5_EA05 = GPIO_FR_1, /*!< PAFR1: EA05 */ + GPIO_PA5_T32A01OUTA = GPIO_FR_3, /*!< PAFR3: T32A01OUTA */ + GPIO_PA5_T32A01OUTC = GPIO_FR_5, /*!< PAFR5: T32A01OUTC */ + GPIO_PA5_TSPI0CS2 = GPIO_FR_6, /*!< PAFR6: TSPI0CS2 */ + GPIO_PA5_TSPI2RXD = GPIO_FR_7, /*!< PAFR7: TSPI2RXD */ +} gpio_pa5_func_t; + +/** + * @enum gpio_pa6_func_t + * @brief PortA6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA6_EA06 = GPIO_FR_1, /*!< PAFR1: EA06 */ + GPIO_PA6_T32A01OUTB = GPIO_FR_3, /*!< PAFR3: T32A01OUTB */ + GPIO_PA6_TSPI0CS3 = GPIO_FR_6, /*!< PAFR6: TSPI0CS3 */ + GPIO_PA6_TSPI2SCK = GPIO_FR_7, /*!< PAFR7: TSPI2SCK */ +} gpio_pa6_func_t; + + +/** + * @enum gpio_pa7_func_t + * @brief PortA6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA7_INT03a = 0, /*!< 0: INT03a */ + GPIO_PA7_EA07 = GPIO_FR_1, /*!< PAFR1: EA07 */ + GPIO_PA7_T32A01INA1 = GPIO_FR_2, /*!< PAFR2: T32A01INA1 */ + GPIO_PA7_T32A01INB0 = GPIO_FR_3, /*!< PAFR3: T32A01INB0 */ + GPIO_PA7_T32A01INC1 = GPIO_FR_5, /*!< PAFR5: T32A01INC1 */ + GPIO_PA7_TSPI2CSIN = GPIO_FR_6, /*!< PAFR6: TSPI2CSIN */ + GPIO_PA7_TSPI2CS0 = GPIO_FR_7, /*!< PAFR7: TSPI2CS0 */ +} gpio_pa7_func_t; + + + +/** + * @enum gpio_pb0_func_t + * @brief PortB0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB0_INT04a = 0, /*!< 0: INT04a */ + GPIO_PB0_EA08 = GPIO_FR_1, /*!< PBFR1: EA08 */ + GPIO_PB0_T32A02INB1 = GPIO_FR_2, /*!< PBFR2: T32A02INB1 */ + GPIO_PB0_T32A02INA0 = GPIO_FR_3, /*!< PBFR3: T32A02INA0 */ + GPIO_PB0_I2S0MCKIO = GPIO_FR_4, /*!< PBFR4: I2S0MCKI/O */ + GPIO_PB0_T32A02INC0 = GPIO_FR_5, /*!< PBFR5: T32A02INC0 */ +} gpio_pb0_func_t; + +/** + * @enum gpio_pb1_func_t + * @brief PortB1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB1_INT05a = 0, /*!< 0: INT05a */ + GPIO_PB1_EA09 = GPIO_FR_1, /*!< PBFR1: EA09 */ + GPIO_PB1_T32A02INA1 = GPIO_FR_2, /*!< PBFR2: T32A02INA1 */ + GPIO_PB1_T32A02INB0 = GPIO_FR_3, /*!< PBFR3: T32A02INB0 */ + GPIO_PB1_T32A02INC1 = GPIO_FR_5, /*!< PBFR5: T32A02INC1 */ + GPIO_PB1_HDMAREQA = GPIO_FR_6, /*!< PBFR6: HDMAREQA */ +} gpio_pb1_func_t; + +/** + * @enum gpio_pb2_func_t + * @brief PortB2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB2_EA10 = GPIO_FR_1, /*!< PBFR1: EA10 */ + GPIO_PB2_T32A02OUTA = GPIO_FR_3, /*!< PBFR3: T32A02OUTA */ + GPIO_PB2_T32A02OUTC = GPIO_FR_5, /*!< PBFR5: T32A02OUTC */ +} gpio_pb2_func_t; + +/** +* @enum gpio_pb3_func_t +* @brief PortB3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PB3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB3_EA11 = GPIO_FR_1, /*!< PBFR1: EA11 */ + GPIO_PB3_T32A02OUTB = GPIO_FR_3, /*!< PBFR3: T32A02OUTB */ +} gpio_pb3_func_t; + +/** +* @enum gpio_pb4_func_t +* @brief PortB4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PB4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB4_EA12 = GPIO_FR_1, /*!< PBFR1: EA12 */ + GPIO_PB4_T32A03OUTA = GPIO_FR_3, /*!< PBFR3: T32A03OUTA */ + GPIO_PB4_I2S0LRCK = GPIO_FR_4, /*!< PBFR4: I2S0LRCK */ + GPIO_PB4_T32A03OUTC = GPIO_FR_5, /*!< PBFR5: T32A03OUTC */ +} gpio_pb4_func_t; + +/** + * @enum gpio_pb5_func_t + * @brief PortB5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB5_EA13 = GPIO_FR_1, /*!< PBFR1: EA13 */ + GPIO_PB5_T32A03OUTB = GPIO_FR_3, /*!< PBFR3: T32A03OUTB */ + GPIO_PB5_I2S0BCK = GPIO_FR_4, /*!< PBFR4: I2S0BCK */ +} gpio_pb5_func_t; + +/** + * @enum gpio_pb6_func_t + * @brief PortB6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB6_INT06a = 0, /*!< 0: INT06a */ + GPIO_PB6_EA14 = GPIO_FR_1, /*!< PBFR1: EA14 */ + GPIO_PB6_T32A03INB1 = GPIO_FR_2, /*!< PBFR2: T32A03INB1 */ + GPIO_PB6_T32A03INA0 = GPIO_FR_3, /*!< PBFR3: T32A03INA0 */ + GPIO_PB6_I2S0DI = GPIO_FR_4, /*!< PBFR4: I2S0DI */ + GPIO_PB6_T32A03INC0 = GPIO_FR_5, /*!< PBFR5: T32A03INC0 */ +} gpio_pb6_func_t; + +/** + * @enum gpio_pb7_func_t + * @brief PortB7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB7_INT07a = 0, /*!< 0: INT07a */ + GPIO_PB7_EA15 = GPIO_FR_1, /*!< PBFR1: EA15 */ + GPIO_PB7_T32A03INA1 = GPIO_FR_2, /*!< PBFR2: T32A03INA1 */ + GPIO_PB7_T32A03INB0 = GPIO_FR_3, /*!< PBFR3: T32A03INB0 */ + GPIO_PB7_I2S0DO = GPIO_FR_4, /*!< PBFR4: I2S0DO */ + GPIO_PB7_T32A03INC1 = GPIO_FR_5, /*!< PBFR5: T32A03INC1 */ +} gpio_pb7_func_t; + +/** + * @enum gpio_pc0_func_t + * @brief PortC0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC0_INT12a = 0, /*!< 0: INT12a */ + GPIO_PC0_EA16 = GPIO_FR_1, /*!< PCFR1: EA16 */ + GPIO_PC0_T32A08INA0 = GPIO_FR_3, /*!< PCFR3: T32A08INA0 */ + GPIO_PC0_I2S1DO = GPIO_FR_4, /*!< PCFR4: I2S1DO */ + GPIO_PC0_T32A08INC0 = GPIO_FR_5, /*!< PCFR5: T32A08INC0 */ +} gpio_pc0_func_t; + +/** + * @enum gpio_pc1_func_t + * @brief PortC1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC1_INT13a = 0, /*!< 0: INT13a */ + GPIO_PC1_EA17 = GPIO_FR_1, /*!< PCFR1: EA17 */ + GPIO_PC1_T32A08INB0 = GPIO_FR_3, /*!< PCFR3: T32A08INB0 */ + GPIO_PC1_I2S1DI = GPIO_FR_4, /*!< PCFR4: I2S1DI */ + GPIO_PC1_T32A08INC1 = GPIO_FR_5, /*!< PCFR5: T32A08INC1 */ +} gpio_pc1_func_t; + +/** + * @enum gpio_pc2_func_t + * @brief PortC2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC2_EA18 = GPIO_FR_1, /*!< PCFR1: UT4TXDB */ + GPIO_PC2_T32A08OUTA = GPIO_FR_3, /*!< PCFR3: T32A08OUTA */ + GPIO_PC2_I2S1BCK = GPIO_FR_4, /*!< PCFR4: I2S1BCK */ + GPIO_PC2_T32A08OUTC = GPIO_FR_5, /*!< PCFR5: T32A08OUTC */ +} gpio_pc2_func_t; + +/** +* @enum gpio_pc3_func_t +* @brief PortC3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PC3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC3_EA19 = GPIO_FR_1, /*!< PCFR1: EA19 */ + GPIO_PC3_T32A08OUTB = GPIO_FR_3, /*!< PCFR3: T32A08OUTB */ + GPIO_PC3_I2S1LRCK = GPIO_FR_4, /*!< PCFR4: I2S1LRCK */ +} gpio_pc3_func_t; + +/** +* @enum gpio_pc4_func_t +* @brief PortC4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PC4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC4_EA20 = GPIO_FR_1, /*!< PCFR1: EA20 */ + GPIO_PC4_T32A10OUTA = GPIO_FR_3, /*!< PCFR3: T32A10OUTA */ + GPIO_PC4_T32A10OUTC = GPIO_FR_5, /*!< PCFR5: T32A10OUTC */ +} gpio_pc4_func_t; + +/** + * @enum gpio_pc5_func_t + * @brief PortC5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC5_EA21 = GPIO_FR_1, /*!< PCFR1: EA21 */ + GPIO_PC5_T32A10OUTB = GPIO_FR_3, /*!< PCFR3: T32A10OUTB */ +} gpio_pc5_func_t; + +/** + * @enum gpio_pc6_func_t + * @brief PortC6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC6_INT14a = 0, /*!< 0: INT14a */ + GPIO_PC6_EA22 = GPIO_FR_1, /*!< PCFR1: EA22 */ +} gpio_pc6_func_t; + +/** + * @enum gpio_pc7_func_t + * @brief PortC7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC7_INT15a = 0, /*!< 0: INT15a */ + GPIO_PC7_EA23 = GPIO_FR_1, /*!< PCFR1: EA23 */ +} gpio_pc7_func_t; + +/** + * @enum gpio_pd0_func_t + * @brief PortD0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD0_ED00 = GPIO_FR_1, /*!< PCFR1: ED00 */ + GPIO_PD0_T32A04INB1 = GPIO_FR_2, /*!< PCFR2: T32A04INB1 */ + GPIO_PD0_T32A04INA0 = GPIO_FR_3, /*!< PCFR3: T32A04INA0 */ + GPIO_PD0_TSPI4CS0 = GPIO_FR_4, /*!< PCFR4: TSPI4CS0 */ + GPIO_PD0_T32A04INC0 = GPIO_FR_5, /*!< PCFR5: T32A04INC0 */ + GPIO_PD0_TSPI4CSIN = GPIO_FR_6, /*!< PCFR6: TSPI4CSIN */ + GPIO_PD0_UO0 = GPIO_FR_7, /*!< PCFR7: UO0 */ +} gpio_pd0_func_t; + +/** + * @enum gpio_pd1_func_t + * @brief PortD1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD1_ED01 = GPIO_FR_1, /*!< PCFR1: ED01 */ + GPIO_PD1_T32A04INA1 = GPIO_FR_2, /*!< PCFR2: T32A04INA1 */ + GPIO_PD1_T32A04INB0 = GPIO_FR_3, /*!< PCFR3: T32A04INB0 */ + GPIO_PD1_TSPI4SCK = GPIO_FR_4, /*!< PCFR4: TSPI4SCK */ + GPIO_PD1_T32A04INC1 = GPIO_FR_5, /*!< PCFR5: T32A04INC1 */ + GPIO_PD1_XO0 = GPIO_FR_7, /*!< PCFR7: XO0 */ +} gpio_pd1_func_t; + +/** + * @enum gpio_pd2_func_t + * @brief PortD2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD2_ED02 = GPIO_FR_1, /*!< PCFR1: ED02 */ + GPIO_PD2_T32A04OUTA = GPIO_FR_3, /*!< PCFR3: T32A04OUTA */ + GPIO_PD2_TSPI4RXD = GPIO_FR_4, /*!< PCFR4: TSPI4RXD */ + GPIO_PD2_T32A04OUTC = GPIO_FR_5, /*!< PCFR5: T32A04OUTC */ + GPIO_PD2_VO0 = GPIO_FR_7, /*!< PCFR7: VO0 */ + GPIO_PD2_TSSI0TCK = GPIO_FR_8, /*!< PCFR8: TSSI0TCK */ +} gpio_pd2_func_t; + +/** +* @enum gpio_pd3_func_t +* @brief PortD3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PD3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD3_ED03 = GPIO_FR_1, /*!< PCFR1: ED03 */ + GPIO_PD3_T32A04OUTB = GPIO_FR_3, /*!< PCFR3: T32A04OUTB */ + GPIO_PD3_TSPI4TXD = GPIO_FR_4, /*!< PCFR4: TSPI4TXD */ + GPIO_PD3_YO0 = GPIO_FR_7, /*!< PCFR7: YO0 */ + GPIO_PD3_TSSI0TFS = GPIO_FR_8, /*!< PCFR8: TSSI0TFS */ +} gpio_pd3_func_t; + +/** + * @enum gpio_pd4_func_t + * @brief PortD4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD4_ED04 = GPIO_FR_1, /*!< PCFR1: ED04 */ + GPIO_PD4_T32A05OUTA = GPIO_FR_3, /*!< PCFR3: T32A05OUTA */ + GPIO_PD4_T32A05OUTC = GPIO_FR_5, /*!< PCFR5: T32A05OUTC */ + GPIO_PD4_I2S0LRCK = GPIO_FR_6, /*!< PCFR6: I2S0LRCK */ + GPIO_PD4_WO0 = GPIO_FR_7, /*!< PCFR7: WO0 */ + GPIO_PD4_TSSI0TXD = GPIO_FR_8, /*!< PCFR8: TSSI0TXD */ +} gpio_pd4_func_t; + +/** + * @enum gpio_pd5_func_t + * @brief PortD5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD5_ED05 = GPIO_FR_1, /*!< PCFR1: ED05 */ + GPIO_PD5_T32A05OUTB = GPIO_FR_3, /*!< PCFR3: T32A05OUTB */ + GPIO_PD5_I2S0BCK = GPIO_FR_6, /*!< PCFR6: I2S0BCK */ + GPIO_PD5_ZO0 = GPIO_FR_7, /*!< PCFR7: WO0 */ + GPIO_PD5_TSSI0RXD = GPIO_FR_8, /*!< PCFR8: TSSI0RXD */ +} gpio_pd5_func_t; + +/** + * @enum gpio_pd6_func_t + * @brief PortD6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD6_ED06 = GPIO_FR_1, /*!< PCFR1: ED06 */ + GPIO_PD6_T32A05INB1 = GPIO_FR_2, /*!< PCFR2: T32A05INB1 */ + GPIO_PD6_T32A05INA0 = GPIO_FR_3, /*!< PCFR3: T32A05INA0 */ + GPIO_PD6_T32A05INC0 = GPIO_FR_5, /*!< PCFR5: T32A05INC0 */ + GPIO_PD6_I2S0DI = GPIO_FR_6, /*!< PCFR6: I2S0DI */ + GPIO_PD6_EMG0 = GPIO_FR_7, /*!< PCFR7: EMG0 */ + GPIO_PD6_TSSI0RFS = GPIO_FR_8, /*!< PCFR8: TSSI0RFS */ +} gpio_pd6_func_t; + +/** + * @enum gpio_pd7_func_t + * @brief PortD7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD7_ED07 = GPIO_FR_1, /*!< PCFR1: ED07 */ + GPIO_PD7_T32A05INA1 = GPIO_FR_2, /*!< PCFR2: T32A05INA1 */ + GPIO_PD7_T32A05INB0 = GPIO_FR_3, /*!< PCFR3: T32A05INB0 */ + GPIO_PD7_T32A05INC1 = GPIO_FR_5, /*!< PCFR5: T32A05INC1 */ + GPIO_PD7_I2S0DO = GPIO_FR_6, /*!< PCFR6: I2S0DO */ + GPIO_PD7_OVV0 = GPIO_FR_7, /*!< PCFR7: OVV0 */ + GPIO_PD7_TSSI0RCK = GPIO_FR_8, /*!< PCFR8: TSSI0RCK */ +} gpio_pd7_func_t; + +/** + * @enum gpio_pe0_func_t + * @brief PortE0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE0_ED08 = GPIO_FR_1, /*!< PCFR1: ED08 */ + GPIO_PE0_T32A06INB1 = GPIO_FR_2, /*!< PCFR2: T32A06INB1 */ + GPIO_PE0_T32A06OUTB = GPIO_FR_3, /*!< PCFR3: T32A06OUTB */ + GPIO_PE0_EA23 = GPIO_FR_4, /*!< PCFR4: EA23 */ + GPIO_PE0_T32A06INA1 = GPIO_FR_5, /*!< PCFR5: T32A06INA1 */ + GPIO_PE0_UT0RTS_N = GPIO_FR_7, /*!< PCFR7: UT0RTS_N */ + GPIO_PE0_EA15 = GPIO_FR_8, /*!< PCFR8: EA15 */ +} gpio_pe0_func_t; + +/** + * @enum gpio_pe1_func_t + * @brief PortE1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE1_ED09 = GPIO_FR_1, /*!< PCFR1: ED09 */ + GPIO_PE1_T32A06OUTA = GPIO_FR_3, /*!< PCFR3: T32A06OUTA */ + GPIO_PE1_EA22 = GPIO_FR_4, /*!< PCFR4: EA22 */ + GPIO_PE1_T32A06OUTC = GPIO_FR_5, /*!< PCFR5: T32A06OUTC */ + GPIO_PE1_UT0CTS_N = GPIO_FR_7, /*!< PCFR7: UT0CTS_N */ + GPIO_PE1_EA14 = GPIO_FR_8, /*!< PCFR8: EA14 */ +} gpio_pe1_func_t; + +/** + * @enum gpio_pe2_func_t + * @brief PortE2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE2_ED10 = GPIO_FR_1, /*!< PCFR1: ED10 */ + GPIO_PE2_T32A06INA0 = GPIO_FR_3, /*!< PCFR3: T32A06INA0 */ + GPIO_PE2_EA21 = GPIO_FR_4, /*!< PCFR4: EA21 */ + GPIO_PE2_T32A06INC0 = GPIO_FR_5, /*!< PCFR5: T32A06INC0 */ + GPIO_PE2_UT0RXD = GPIO_FR_7, /*!< PCFR7: UT0RXD */ + GPIO_PE2_EA13 = GPIO_FR_8, /*!< PCFR8: EA13 */ +} gpio_pe2_func_t; + +/** +* @enum gpio_pe3_func_t +* @brief PortE3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PE3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE3_ED11 = GPIO_FR_1, /*!< PCFR1: ED11 */ + GPIO_PE3_T32A06INB0 = GPIO_FR_3, /*!< PCFR3: T32A06INB0 */ + GPIO_PE3_EA20 = GPIO_FR_4, /*!< PCFR4: EA20 */ + GPIO_PE3_T32A06INC1 = GPIO_FR_5, /*!< PCFR5: T32A06INC1 */ + GPIO_PE3_UT0TXDA = GPIO_FR_7, /*!< PCFR7: UT0TXDA */ + GPIO_PE3_EA12 = GPIO_FR_8, /*!< PCFR8: EA12 */ +} gpio_pe3_func_t; + +/** +* @enum gpio_pe4_func_t +* @brief PortE4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PE4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE4_ED12 = GPIO_FR_1, /*!< PCFR1: ED12 */ + GPIO_PE4_T32A07INA0 = GPIO_FR_3, /*!< PCFR3: T32A07INA0 */ + GPIO_PE4_EA19 = GPIO_FR_4, /*!< PCFR4: EA19 */ + GPIO_PE4_T32A07INC0 = GPIO_FR_5, /*!< PCFR5: T32A07INC0 */ + GPIO_PE4_I2S1DO = GPIO_FR_6, /*!< PCFR6: I2S1DO */ + GPIO_PE4_ISDAIN0 = 0, /*!< 0: ISDAIN0 */ + GPIO_PE4_EA11 = GPIO_FR_8, /*!< PCFR8: EA11 */ +} gpio_pe4_func_t; + +/** + * @enum gpio_pe5_func_t + * @brief PortE5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE5_ED13 = GPIO_FR_1, /*!< PCFR1: ED13 */ + GPIO_PE5_T32A07INB0 = GPIO_FR_3, /*!< PCFR3: T32A07INB0 */ + GPIO_PE5_EA18 = GPIO_FR_4, /*!< PCFR4: EA18 */ + GPIO_PE5_T32A07INC1 = GPIO_FR_5, /*!< PCFR5: T32A07INC1 */ + GPIO_PE5_I2S1DI = GPIO_FR_6, /*!< PCFR6: I2S1DI */ + GPIO_PE5_ISDAIN1 = 0, /*!< 0: ISDAIN1 */ + GPIO_PE5_EA10 = GPIO_FR_8, /*!< PCFR8: EA10 */ +} gpio_pe5_func_t; + +/** + * @enum gpio_pe6_func_t + * @brief PortE6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE6_ED14 = GPIO_FR_1, /*!< PCFR1: ED14 */ + GPIO_PE6_T32A07OUTA = GPIO_FR_3, /*!< PCFR3: T32A07OUTA */ + GPIO_PE6_EA17 = GPIO_FR_4, /*!< PCFR4: EA17 */ + GPIO_PE6_T32A07OUTC = GPIO_FR_5, /*!< PCFR5: T32A07OUTC */ + GPIO_PE6_I2S1BCK = GPIO_FR_6, /*!< PCFR6: I2S1BCK */ + GPIO_PE6_ISDAIN2 = 0, /*!< 0: ISDAIN2 */ + GPIO_PE6_EA09 = GPIO_FR_8, /*!< PCFR8: EA09 */ +} gpio_pe6_func_t; + +/** + * @enum gpio_pe7_func_t + * @brief PortE7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE7_ED15 = GPIO_FR_1, /*!< PCFR1: ED15 */ + GPIO_PE7_T32A07INB1 = GPIO_FR_2, /*!< PCFR2: T32A07INB1 */ + GPIO_PE7_T32A07OUTB = GPIO_FR_3, /*!< PCFR3: T32A07OUTB */ + GPIO_PE7_EA16 = GPIO_FR_4, /*!< PCFR4: EA16 */ + GPIO_PE7_T32A07INA1 = GPIO_FR_5, /*!< PCFR5: T32A07INA1 */ + GPIO_PE7_I2S1LRCK = GPIO_FR_6, /*!< PCFR6: I2S1LRCK */ + GPIO_PE7_ISDAIN3 = 0, /*!< 0: ISDAIN3 */ + GPIO_PE7_EA08 = GPIO_FR_8, /*!< PCFR8: EA08 */ +} gpio_pe7_func_t; + +/** + * @enum gpio_pf0_func_t + * @brief PortF0 Function Enumerated TyPF Definition. + */ +typedef enum { + GPIO_PF0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF0_INT04b = 0, /*!< 0: INT04b */ + GPIO_PF0_ERD_N = GPIO_FR_1, /*!< PCFR1: ERD_N */ +} gpio_pf0_func_t; + +/** + * @enum gpio_pf1_func_t + * @brief PortF1 Function Enumerated TyPF Definition. + */ +typedef enum { + GPIO_PF1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF1_EWR_N = GPIO_FR_1, /*!< PCFR1: EWR_N */ +} gpio_pf1_func_t; + +/** + * @enum gpio_pf2_func_t + * @brief PortF2 Function Enumerated TyPF Definition. + */ +typedef enum { + GPIO_PF2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF2_EI2C1SDA = GPIO_FR_6, /*!< PCFR6: EI2C1SDA */ + GPIO_PF2_I2C1SDA = GPIO_FR_7, /*!< PCFR7: I2C1SDA */ +} gpio_pf2_func_t; + +/** +* @enum gpio_pf3_func_t +* @brief PortF3 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF3_EI2C1SCL = GPIO_FR_6, /*!< PCFR6: EI2C1SCL */ + GPIO_PF3_I2C1SCL = GPIO_FR_7, /*!< PCFR7: I2C1SCL */ +} gpio_pf3_func_t; + +/** +* @enum gpio_pf4_func_t +* @brief PortF4 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF4_ECS2_N = GPIO_FR_1, /*!< PCFR1: ECS2_N */ +} gpio_pf4_func_t; + +/** +* @enum gpio_pf5_func_t +* @brief PortF5 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF5_ECS3_N = GPIO_FR_1, /*!< PCFR1: ECS3_N */ +} gpio_pf5_func_t; + +/** +* @enum gpio_pf6_func_t +* @brief PortF6 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF6_EBELL_N = GPIO_FR_1, /*!< PCFR1: EBELL_N */ +} gpio_pf6_func_t; + +/** +* @enum gpio_pf7_func_t +* @brief PortF7 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF7_INT05b = 0, /*!< 0: INT05b */ + GPIO_PF7_EBELH_N = GPIO_FR_1, /*!< PCFR1: EBELH_N */ + GPIO_PF7_TSPI2CSIN = GPIO_FR_4, /*!< PCFR4: TSPI2CSIN */ + GPIO_PF7_TSPI2CS0 = GPIO_FR_5, /*!< PCFR5: TSPI2CS0 */ +} gpio_pf7_func_t; + +/** + * @enum gpio_pg0_func_t + * @brief PortG0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG0_INT08a = 0, /*!< 0: INT08a */ + GPIO_PG0_EALE = GPIO_FR_1, /*!< PCFR1: EALE */ + GPIO_PG0_UT2RXD = GPIO_FR_3, /*!< PCFR3: UT2RXD */ + GPIO_PG0_UT2TXDA = GPIO_FR_5, /*!< PCFR5: UT2TXDA */ +} gpio_pg0_func_t; + +/** + * @enum gpio_pg1_func_t + * @brief PortG1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG1_INT09a = 0, /*!< 0: INT09a */ + GPIO_PG1_EWAIT_N = GPIO_FR_1, /*!< PCFR1: EWAIT_N */ + GPIO_PG1_UT2TXDA = GPIO_FR_3, /*!< PCFR3: UT2TXDA */ + GPIO_PG1_UT2RXD = GPIO_FR_5, /*!< PCFR5: UT2RXD */ +} gpio_pg1_func_t; + +/** + * @enum gpio_pg2_func_t + * @brief PortG2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG2_UT2RTS_N = GPIO_FR_3, /*!< PCFR3: UT2RTS_N */ + GPIO_PG2_ALARM_N = GPIO_FR_4, /*!< PCFR4: ALARM_N */ + GPIO_PG2_UT2CTS_N = GPIO_FR_5, /*!< PCFR5: UT2CTS_N */ + GPIO_PG2_EI2C0SDA = GPIO_FR_6, /*!< PCFR6: EI2C0SDA */ + GPIO_PG2_I2C0SDA = GPIO_FR_7, /*!< PCFR7: I2C0SDA */ +} gpio_pg2_func_t; + +/** + * @enum gpio_pg3_func_t + * @brief PortG3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG3_UT2CTS_N = GPIO_FR_3, /*!< PCFR3: UT2CTS_N */ + GPIO_PG3_TRGIN0 = GPIO_FR_4, /*!< PCFR4: TRGIN0 */ + GPIO_PG3_UT2RTS_N = GPIO_FR_5, /*!< PCFR5: UT2RTS_N */ + GPIO_PG3_EI2C0SCL = GPIO_FR_6, /*!< PCFR6: EI2C0SCL */ + GPIO_PG3_I2C0SCL = GPIO_FR_7, /*!< PCFR7: I2C0SCL */ +} gpio_pg3_func_t; + +/** + * @enum gpio_pg4_func_t + * @brief PortG4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG4_T32A02OUTB = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */ + GPIO_PG4_FUT0IROUT = GPIO_FR_4, /*!< PCF41: FUT0IROUT */ + GPIO_PG4_FUT0TXD = GPIO_FR_5, /*!< PCFR5: FUT0TXD */ + GPIO_PG4_EI2C2SDA = GPIO_FR_6, /*!< PCFR6: EI2C2SDA */ + GPIO_PG4_I2C2SDA = GPIO_FR_7, /*!< PCFR7: I2C2SDA */ +} gpio_pg4_func_t; + +/** + * @enum gpio_pg5_func_t + * @brief PortG5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG5_T32A02OUTA = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */ + GPIO_PG5_T32A02OUTC = GPIO_FR_3, /*!< PCFR3: T32A02OUTC */ + GPIO_PG5_FUT0IRIN = GPIO_FR_4, /*!< PCFR4: FUT0IRIN */ + GPIO_PG5_FUT0RXD = GPIO_FR_5, /*!< PCFR5: FUT0RXD */ + GPIO_PG5_EI2C2SCL = GPIO_FR_6, /*!< PCFR6: EI2C2SCL */ + GPIO_PG5_I2C2SCL = GPIO_FR_7, /*!< PCFR7: I2C2SCL */ +} gpio_pg5_func_t; + +/** + * @enum gpio_pg6_func_t + * @brief PortG6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG6_TRACECLK = GPIO_FR_1, /*!< PCFR1: TRACECLK */ + GPIO_PG6_NBDCLK = GPIO_FR_4, /*!< PCFR4: NBDCLK */ + GPIO_PG6_FUT0RTS_N = GPIO_FR_5, /*!< PCFR5: FUT0RTS_N */ + GPIO_PG6_I2S1MCKIO = GPIO_FR_6, /*!< PCFR6: I2S1MCKIO */ +} gpio_pg6_func_t; + +/** + * @enum gpio_pg7_func_t + * @brief PortG7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG7_TRACEDATA0 = GPIO_FR_1, /*!< PCFR1: TRACEDATA0 */ + GPIO_PG7_NBDDATA0 = GPIO_FR_4, /*!< PCFR4: NBDDATA0 */ + GPIO_PG7_FUT0CTS_N = GPIO_FR_5, /*!< PCFR5: FUT0CTS_N */ +} gpio_pg7_func_t; + +/** + * @enum gpio_ph0_func_t + * @brief PortH0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH0_TRACEDATA1 = GPIO_FR_1, /*!< PCFR1: TRACEDATA1 */ + GPIO_PH0_UT1RXD = GPIO_FR_3, /*!< PCFR3: UT1RXD */ + GPIO_PH0_NBDDATA1 = GPIO_FR_4, /*!< PCFR4: NBDDATA1 */ + GPIO_PH0_UT1TXDA = GPIO_FR_5, /*!< PCFR5: UT1TXDA */ +} gpio_ph0_func_t; + +/** + * @enum gpio_ph1_func_t + * @brief PortH1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH1_TRACEDATA2 = GPIO_FR_1, /*!< PCFR1: TRACEDATA2 */ + GPIO_PH1_UT1TXDA = GPIO_FR_3, /*!< PCFR3: UT1TXDA */ + GPIO_PH1_NBDDATA2 = GPIO_FR_4, /*!< PCFR4: NBDDATA2 */ + GPIO_PH1_UT1RXD = GPIO_FR_5, /*!< PCFR5: UT1RXD */ +} gpio_ph1_func_t; + +/** + * @enum gpio_ph2_func_t + * @brief PortH2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH2_TRACEDATA3 = GPIO_FR_1, /*!< PCFR1: TRACEDATA3 */ + GPIO_PH2_UT1RTS_N = GPIO_FR_3, /*!< PCFR3: UT1RTS_N */ + GPIO_PH2_NBDDATA3 = GPIO_FR_4, /*!< PCFR4: NBDDATA3 */ + GPIO_PH2_UT1CTS_N = GPIO_FR_5, /*!< PCFR5: UT1CTS_N */ +} gpio_ph2_func_t; + +/** +* @enum gpio_ph3_func_t +* @brief PortH3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH3_TDI = GPIO_FR_1, /*!< PCFR1: TDI */ + GPIO_PH3_UT1CTS_N = GPIO_FR_3, /*!< PCFR3: UT1CTS_N */ + GPIO_PH3_NBDSYNC = GPIO_FR_4, /*!< PCFR4: NBDSYNC */ + GPIO_PH3_UT1RTS_N = GPIO_FR_5, /*!< PCFR5: UT1RTS_N */ +} gpio_ph3_func_t; + +/** +* @enum gpio_ph4_func_t +* @brief PortH4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH4_SWDIO = GPIO_FR_1, /*!< PCFR1: SWDIO */ + GPIO_PH4_UT0RXD = GPIO_FR_3, /*!< PCFR3: UT0RXD */ + GPIO_PH4_UT0TXDA = GPIO_FR_5, /*!< PCFR5: UT0TXDA */ +} gpio_ph4_func_t; + +/** +* @enum gpio_ph5_func_t +* @brief PortH5 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH5_TCK = GPIO_FR_1, /*!< PCFR1: TCK */ + GPIO_PH5_UT0TXDA = GPIO_FR_3, /*!< PCFR3: UT0TXDA */ + GPIO_PH5_UT0RXD = GPIO_FR_5, /*!< PCFR5: UT0RXD */ +} gpio_ph5_func_t; + +/** +* @enum gpio_ph6_func_t +* @brief PortH6 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH6_TDO = GPIO_FR_1, /*!< PCFR1: TDO */ + GPIO_PH6_UT0RTS_N = GPIO_FR_3, /*!< PCFR3: UT0RTS_N */ + GPIO_PH6_UT0CTS_N = GPIO_FR_5, /*!< PCFR5: UT0CTS_N */ +} gpio_ph6_func_t; + +/** +* @enum gpio_ph7_func_t +* @brief PortH7 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH7_TRST_N = GPIO_FR_1, /*!< PCFR1: TRST_N */ + GPIO_PH7_UT0CTS_N = GPIO_FR_3, /*!< PCFR3: UT0CTS_N */ + GPIO_PH7_UT0RTS_N = GPIO_FR_5, /*!< PCFR5: UT0RTS_N */ +} gpio_ph7_func_t; + +/** + * @enum gpio_pj0_func_t + * @brief PortJ0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ0_UT5RXD = GPIO_FR_3, /*!< PJFR3: UT5RXD */ + GPIO_PJ0_UT5TXDA = GPIO_FR_5, /*!< PJFR5: UT5TXDA */ +} gpio_pj0_func_t; + +/** + * @enum gpio_pj1_func_t + * @brief PortJ1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ1_UT5TXDA = GPIO_FR_3, /*!< PJFR3: UT5TXDA */ + GPIO_PJ1_UT5RXD = GPIO_FR_5, /*!< PJFR5: UT5RXD */ +} gpio_pj1_func_t; + +/** + * @enum gpio_pj2_func_t + * @brief PortJ2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ2_UT5RTS_N = GPIO_FR_3, /*!< PJFR3: UT5RTS_N */ + GPIO_PJ2_UT5CTS_N = GPIO_FR_5, /*!< PJFR5: UT5CTS_N */ + GPIO_PJ2_EI2C4SCL = GPIO_FR_6, /*!< PJFR6: EI2C4SCL */ + GPIO_PJ2_I2C4SCL = GPIO_FR_7, /*!< PJFR7: I2C4SCL */ +} gpio_pj2_func_t; + +/** +* @enum gpio_pj3_func_t +* @brief PortJ3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PJ3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ3_UT5CTS_N = GPIO_FR_3, /*!< PJFR3: UT5CTS_N */ + GPIO_PJ3_UT5RTS_N = GPIO_FR_5, /*!< PJFR5: UT5RTS_N */ + GPIO_PJ3_EI2C4SDA = GPIO_FR_6, /*!< PJFR6: EI2C4SDA */ + GPIO_PJ3_I2C4SDA = GPIO_FR_7, /*!< PJFR7: I2C4SDA */ +} gpio_pj3_func_t; + +/** +* @enum gpio_pj4_func_t +* @brief PortJ4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PJ4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ4_T32A03INA0 = GPIO_FR_2, /*!< PJFR2: T32A03INA0 */ + GPIO_PJ4_T32A03INC0 = GPIO_FR_3, /*!< PJFR3: T32A03INC0 */ + GPIO_PJ4_FUT0TXD = GPIO_FR_5, /*!< PJFR5: FUT0TXD */ +} gpio_pj4_func_t; + +/** + * @enum gpio_pj5_func_t + * @brief PortJ5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ5_T32A03INB0 = GPIO_FR_2, /*!< PJFR2: T32A03INB0 */ + GPIO_PJ5_T32A03INC1 = GPIO_FR_3, /*!< PJFR3: T32A03INC1 */ + GPIO_PJ5_FUT0RXD = GPIO_FR_5, /*!< PJFR5: FUT0RXD */ +} gpio_pj5_func_t; + +/** + * @enum gpio_pj6_func_t + * @brief PortJ6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ6_FUT1TXD = GPIO_FR_5, /*!< PJFR5: FUT1TXD */ + GPIO_PJ6_EI2C3SDA = GPIO_FR_6, /*!< PJFR6: EI2C3SDA */ + GPIO_PJ6_I2C3SDA = GPIO_FR_7, /*!< PJFR7: I2C3SDA */ +} gpio_pj6_func_t; + +/** + * @enum gpio_pj7_func_t + * @brief PortJ7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ7_FUT1RXD = GPIO_FR_5, /*!< PJFR5: FUT1RXD */ + GPIO_PJ7_EI2C3SCL = GPIO_FR_6, /*!< PJFR6: EI2C3SCL */ + GPIO_PJ7_I2C3SCL = GPIO_FR_7, /*!< PJFR7: I2C3SCL */ +} gpio_pj7_func_t; + +/** + * @enum gpio_pk0_func_t + * @brief PortK0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK0_INT10a = 0, /*!< 0: INT10a */ + GPIO_PK0_ISDAOUT = GPIO_FR_1, /*!< PKFR1: ISDAOUT */ + GPIO_PK0_T32A00INA0 = GPIO_FR_2, /*!< PKFR2: T32A00INA0 */ + GPIO_PK0_T32A00INC0 = GPIO_FR_3, /*!< PKFR3: T32A00INC0 */ + GPIO_PK0_SMI0CS1_N = GPIO_FR_6, /*!< PKFR6: ISDAOUT */ +} gpio_pk0_func_t; + +/** + * @enum gpio_pk1_func_t + * @brief PortK1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK1_INT11a = 0, /*!< 0: INT11a */ + GPIO_PK1_ISDBOUT = GPIO_FR_1, /*!< PKFR1: ISDBOUT */ + GPIO_PK1_T32A00INB0 = GPIO_FR_2, /*!< PKFR2: T32A00INB0 */ + GPIO_PK1_T32A00INC1 = GPIO_FR_3, /*!< PKFR3: T32A00INC1 */ + GPIO_PK1_HDMAREQB = GPIO_FR_4, /*!< PKFR4: HDMAREQB */ + GPIO_PK1_TSPI3CS0 = GPIO_FR_5, /*!< PKFR5: TSPI3CS0 */ + GPIO_PK1_TSPI3CSIN = GPIO_FR_6, /*!< PKFR6: TSPI3CSIN */ +} gpio_pk1_func_t; + +/** + * @enum gpio_pk2_func_t + * @brief PortK2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK2_ECS0_N = GPIO_FR_1, /*!< PKFR1: ECS0_N */ + GPIO_PK2_SMI0D0 = GPIO_FR_6, /*!< PKFR6: SMI0D0 */ +} gpio_pk2_func_t; + +/** +* @enum gpio_pk3_func_t +* @brief PortK3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PK3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK3_ECS1_N = GPIO_FR_1, /*!< PKFR1: ECS1_N */ + GPIO_PK3_SMI0D1 = GPIO_FR_6, /*!< PKFR6: SMI0D1 */ +} gpio_pk3_func_t; + +/** +* @enum gpio_pk4_func_t +* @brief PortK4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PK4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK4_TSPI1CS1 = GPIO_FR_1, /*!< PKFR1: TSPI1CS1 */ + GPIO_PK4_TSPI3TXD = GPIO_FR_4, /*!< PKFR4: TSPI3TXD */ + GPIO_PK4_SMI0D2 = GPIO_FR_6, /*!< PKFR6: SMI0D2 */ +} gpio_pk4_func_t; + +/** + * @enum gpio_pk5_func_t + * @brief PortK5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK5_TSPI1CS2 = GPIO_FR_1, /*!< PKFR1: TSPI1CS2 */ + GPIO_PK5_TSPI3RXD = GPIO_FR_4, /*!< PKFR4: TSPI3RXD */ + GPIO_PK5_SMI0D3 = GPIO_FR_6, /*!< PKFR6: SMI0D3 */ +} gpio_pk5_func_t; + +/** + * @enum gpio_pk6_func_t + * @brief PortK6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK6_TSPI1CS3 = GPIO_FR_1, /*!< PKFR1: TSPI1CS3 */ + GPIO_PK6_T32A01INA0 = GPIO_FR_2, /*!< PKFR2: T32A01INA0 */ + GPIO_PK6_T32A01INC0 = GPIO_FR_3, /*!< PKFR3: T32A01INC0 */ + GPIO_PK6_TSPI3SCK = GPIO_FR_4, /*!< PKFR4: TSPI3SCK */ + GPIO_PK6_SMI0CLK = GPIO_FR_6, /*!< PKFR6: SMI0CLK */ +} gpio_pk6_func_t; + +/** + * @enum gpio_pk7_func_t + * @brief PortK7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK7_INT00a = 0, /*!< 0: INT00a */ + GPIO_PK7_T32A01INB0 = GPIO_FR_2, /*!< PKFR2: T32A01INB0 */ + GPIO_PK7_T32A01INC1 = GPIO_FR_3, /*!< PKFR3: T32A01INC1 */ + GPIO_PK7_TSPI3CS0 = GPIO_FR_4, /*!< PKFR4: TSPI3CS0 */ + GPIO_PK7_SMI0CS0_N = GPIO_FR_6, /*!< PKFR6: SMI0CS0_N */ + GPIO_PK7_TSPI3CSIN = GPIO_FR_7, /*!< PKFR7: TSPI3CSIN */ +} gpio_pk7_func_t; + +/** + * @enum gpio_pl0_func_t + * @brief PortL0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL0_INT01a = 0, /*!< 0: INT01a */ + GPIO_PL0_T32A02INA0 = GPIO_FR_2, /*!< PLFR2: T32A02INA0 */ + GPIO_PL0_T32A02INC0 = GPIO_FR_3, /*!< PLFR3: T32A02INC0 */ + GPIO_PL0_SMI0D4 = GPIO_FR_5, /*!< PLFR5: SMI0D4 */ + GPIO_PL0_TSPI1CSIN = GPIO_FR_6, /*!< PLFR6: TSPI1CSIN */ + GPIO_PL0_TSPI1CS0 = GPIO_FR_7, /*!< PLFR7: TSPI1CS0 */ +} gpio_pl0_func_t; + +/** + * @enum gpio_pl1_func_t + * @brief PortL1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL1_SMI0D5 = GPIO_FR_5, /*!< PLFR5: SMI0D5 */ + GPIO_PL1_TSPI1SCK = GPIO_FR_7, /*!< PLFR7: TSPI1SCK */ +} gpio_pl1_func_t; + +/** + * @enum gpio_pl2_func_t + * @brief PortL2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL2_SMI0D6 = GPIO_FR_5, /*!< PLFR5: SMI0D6 */ + GPIO_PL2_TSPI1RXD = GPIO_FR_7, /*!< PLFR7: TSPI1RXD */ +} gpio_pl2_func_t; + +/** +* @enum gpio_pl3_func_t +* @brief PortL3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL3_T32A02INB0 = GPIO_FR_2, /*!< PLFR2: T32A02INB0 */ + GPIO_PL3_T32A02INC1 = GPIO_FR_3, /*!< PLFR3: T32A02INC1 */ + GPIO_PL3_SMI0D7 = GPIO_FR_5, /*!< PLFR5: SMI0D7 */ + GPIO_PL3_TSPI3CS1 = GPIO_FR_6, /*!< PLFR6: TSPI3CS1 */ + GPIO_PL3_TSPI1TXD = GPIO_FR_7, /*!< PLFR7: TSPI1TXD */ +} gpio_pl3_func_t; + +/** +* @enum gpio_pl4_func_t +* @brief PortL4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL4_INT12b = 0, /*!< 0: IN112b */ + GPIO_PL4_T32A08OUTA = GPIO_FR_2, /*!< PLFR2: T32A08OUTA */ + GPIO_PL4_T32A08OUTC = GPIO_FR_3, /*!< PLFR3: T32A08OUTC */ +} gpio_pl4_func_t; + +/** + * @enum gpio_pl5_func_t + * @brief PortL5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL5_INT13b = 0, /*!< 0: INT13b */ + GPIO_PL5_T32A08OUTB = GPIO_FR_2, /*!< PLFR2: T32A08OUTB */ +} gpio_pl5_func_t; + +/** + * @enum gpio_pl6_func_t + * @brief PortL6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL6_INT03b = 0, /*!< 0: INT03b */ + GPIO_PL6_T32A09OUTA = GPIO_FR_2, /*!< PLFR2: T32A09OUTA */ + GPIO_PL6_T32A09OUTC = GPIO_FR_3, /*!< PLFR3: T32A09OUTC */ +} gpio_pl6_func_t; + +/** + * @enum gpio_pl7_func_t + * @brief PortL7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL7_TRGIN1 = GPIO_FR_1, /*!< PLFR1: TRGIN1 */ + GPIO_PL7_T32A09OUTB = GPIO_FR_2, /*!< PLFR2: T32A09OUTB */ +} gpio_pl7_func_t; + +/** + * @enum gpio_pm0_func_t + * @brief PortM0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM0_EI2C3SDA = GPIO_FR_1, /*!< PMFR1: EI2C3SDA */ + GPIO_PM0_I2C3SDA = GPIO_FR_4, /*!< PMFR4: I2C3SDA */ + GPIO_PM0_UT4RXD = GPIO_FR_5, /*!< PMFR5: UT4RXD */ + GPIO_PM0_TSPI6TXD = GPIO_FR_6, /*!< PMFR6: TSPI6TXD */ + GPIO_PM0_UT4TXDA = GPIO_FR_7, /*!< PMFR7: UT4TXDA */ +} gpio_pm0_func_t; + +/** + * @enum gpio_pm1_func_t + * @brief PortM1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM1_EI2C3SCL = GPIO_FR_1, /*!< PMFR1: EI2C3SCL */ + GPIO_PM1_I2C3SCL = GPIO_FR_4, /*!< PMFR4: I2C3SCL */ + GPIO_PM1_UT4TXDA = GPIO_FR_5, /*!< PMFR5: UT4TXDA */ + GPIO_PM1_TSPI6RXD = GPIO_FR_6, /*!< PMFR6: TSPI6RXD */ + GPIO_PM1_UT4RXD = GPIO_FR_7, /*!< PMFR7: UT4RXD */ +} gpio_pm1_func_t; + +/** + * @enum gpio_pm2_func_t + * @brief PortM2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM2_T32A11OUTA = GPIO_FR_2, /*!< PMFR2: T32A11OUTA */ + GPIO_PM2_T32A11OUTC = GPIO_FR_3, /*!< PMFR3: T32A11OUTC */ + GPIO_PM2_UT4RTS_N = GPIO_FR_5, /*!< PMFR5: UT4RTS_N */ + GPIO_PM2_TSPI6SCK = GPIO_FR_6, /*!< PMFR6: TSPI6SCK */ + GPIO_PM2_UT4CTS_N = GPIO_FR_7, /*!< PMFR7: UT4CTS_N */ +} gpio_pm2_func_t; + +/** +* @enum gpio_pm3_func_t +* @brief PortM3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PM3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM3_INT14b = 0, /*!< 0: INT14b */ + GPIO_PM3_T32A11OUTB = GPIO_FR_2, /*!< PMFR2: T32A11OUTB */ + GPIO_PM3_TSPI6CSIN = GPIO_FR_4, /*!< PMFR4: TSPI6CSIN */ + GPIO_PM3_UT4CTS_N = GPIO_FR_5, /*!< PMFR5: UT4CTS_N */ + GPIO_PM3_TSPI6CS0 = GPIO_FR_6, /*!< PMFR6: TSPI6CS0 */ + GPIO_PM3_UT4RTS_N = GPIO_FR_7, /*!< PMFR7: UT4RTS_N */ +} gpio_pm3_func_t; + +/** +* @enum gpio_pm4_func_t +* @brief PortM4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PM4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM4_INT15b = 0, /*!< 0: INT15b */ + GPIO_PM4_T32A06OUTB = GPIO_FR_2, /*!< PMFR2: T32A06OUTB */ + GPIO_PM4_TSPI7CSIN = GPIO_FR_4, /*!< PMFR4: TSPI7CSIN */ + GPIO_PM4_TSPI7CS0 = GPIO_FR_6, /*!< PMFR6: TSPI7CS0 */ + GPIO_PM4_FUT1CTS_N = GPIO_FR_7, /*!< PMFR7: FUT1CTS_N */ +} gpio_pm4_func_t; + +/** + * @enum gpio_pm5_func_t + * @brief PortM5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM5_T32A06OUTA = GPIO_FR_2, /*!< PMFR2: T32A06OUTA */ + GPIO_PM5_T32A06OUTC = GPIO_FR_3, /*!< PMFR3: T32A06OUTC */ + GPIO_PM5_TSPI7SCK = GPIO_FR_6, /*!< PMFR6: TSPI7SCK */ + GPIO_PM5_FUT1RTS_N = GPIO_FR_7, /*!< PMFR7: FUT1RTS_N */ +} gpio_pm5_func_t; + +/** + * @enum gpio_pm6_func_t + * @brief PortM6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM6_EI2C4SDA = GPIO_FR_1, /*!< PMFR1: EI2C4SDA */ + GPIO_PM6_T32A07OUTA = GPIO_FR_2, /*!< PMFR2: T32A07OUTA */ + GPIO_PM6_T32A07OUTC = GPIO_FR_3, /*!< PMFR3: T32A07OUTC */ + GPIO_PM6_I2C4SDA = GPIO_FR_4, /*!< PMFR4: I2C4SDA */ + GPIO_PM6_FUT1IRIN = GPIO_FR_5, /*!< PMFR5: FUT1IRIN */ + GPIO_PM6_TSPI7RXD = GPIO_FR_6, /*!< PMFR6: TSPI7RXD */ + GPIO_PM6_FUT1RXD = GPIO_FR_7, /*!< PMFR7: FUT1RXD */ +} gpio_pm6_func_t; + +/** + * @enum gpio_pm7_func_t + * @brief PortM7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM7_EI2C4SCL = GPIO_FR_1, /*!< PMFR1: EI2C4SCL */ + GPIO_PM7_T32A07OUTB = GPIO_FR_2, /*!< PMFR2: T32A07OUTB */ + GPIO_PM7_I2C4SCL = GPIO_FR_4, /*!< PMFR4: I2C4SCL */ + GPIO_PM7_FUT1IROUT = GPIO_FR_5, /*!< PMFR5: FUT1IROUT */ + GPIO_PM7_TSPI7TXD = GPIO_FR_6, /*!< PMFR6: TSPI7TXD */ + GPIO_PM7_FUT1TXD = GPIO_FR_7, /*!< PMFR7: FUT1TXD */ +} gpio_pm7_func_t; + +/** + * @enum gpio_pn0_func_t + * @brief PortN0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN0_AINA00 = GPIO_FR_NA, /*!< N/A: AINA00 */ +} gpio_pn0_func_t; + +/** + * @enum gpio_pn1_func_t + * @brief PortN1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN1_AINA01 = GPIO_FR_NA, /*!< N/A: AINA01 */ +} gpio_pn1_func_t; + +/** + * @enum gpio_pn2_func_t + * @brief PortN2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN2_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN2_AINA02 = GPIO_FR_NA, /*!< N/A: AINA02 */ +} gpio_pn2_func_t; + +/** + * @enum gpio_pn3_func_t + * @brief PortN3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN3_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN3_AINA03 = GPIO_FR_NA, /*!< N/A: AINA03 */ +} gpio_pn3_func_t; + +/** +* @enum gpio_pn4_func_t +* @brief PortN4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PN4_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN4_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN4_AINA04 = GPIO_FR_NA, /*!< N/A: AINA04 */ +} gpio_pn4_func_t; + +/** + * @enum gpio_pn5_func_t + * @brief PortN5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN5_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN5_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN5_AINA05 = GPIO_FR_NA, /*!< N/A: AINA05 */ +} gpio_pn5_func_t; + +/** + * @enum gpio_pn6_func_t + * @brief PortN6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN6_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN6_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN6_AINA06 = GPIO_FR_NA, /*!< N/A: AINA06 */ +} gpio_pn6_func_t; + +/** + * @enum gpio_pn7_func_t + * @brief PortN7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN7_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN7_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN7_AINA07 = GPIO_FR_NA, /*!< N/A: AINA07 */ +} gpio_pn7_func_t; + +/** + * @enum gpio_pp0_func_t + * @brief PortP0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP0_AINA08 = 0, /*!< 0: AINA08 */ + GPIO_PP0_T32A04INA0 = GPIO_FR_2, /*!< PPFR2: T32A04INA0 */ + GPIO_PP0_T32A04INC0 = GPIO_FR_3, /*!< PPFR3: T32A04INC0 */ + GPIO_PP0_T32A04INB1 = GPIO_FR_5, /*!< PPFR5: T32A04INB1 */ +} gpio_pp0_func_t; + +/** + * @enum gpio_pp1_func_t + * @brief PortP1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP1_AINA09 = 0, /*!< 0: AINA09 */ + GPIO_PP1_T32A04INB0 = GPIO_FR_2, /*!< PPFR2: T32A04INB0 */ + GPIO_PP1_T32A04INC1 = GPIO_FR_3, /*!< PPFR3: T32A04INC1 */ + GPIO_PP1_T32A04INA1 = GPIO_FR_5, /*!< PPFR5: T32A04INA1 */ +} gpio_pp1_func_t; + +/** + * @enum gpio_pp2_func_t + * @brief PortP2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP2_AINA10 = 0, /*!< 0: AINA10 */ + GPIO_PP2_T32A05INA0 = GPIO_FR_2, /*!< PPFR2: T32A05INA0 */ + GPIO_PP2_T32A05INC0 = GPIO_FR_3, /*!< PPFR3: T32A05INC0 */ + GPIO_PP2_T32A05INB1 = GPIO_FR_5, /*!< PPFR5: T32A05INB1 */ +} gpio_pp2_func_t; + +/** +* @enum gpio_pp3_func_t +* @brief PortP3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP3_AINA11 = 0, /*!< 0: AINA11 */ + GPIO_PP3_T32A05INB0 = GPIO_FR_2, /*!< PPFR2: T32A05INB0 */ + GPIO_PP3_T32A05INC1 = GPIO_FR_3, /*!< PPFR3: T32A05INC1 */ + GPIO_PP3_T32A05INA1 = GPIO_FR_5, /*!< PPFR5: T32A05INA1 */ +} gpio_pp3_func_t; + +/** +* @enum gpio_pp4_func_t +* @brief PortP4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP4_AINA12 = 0, /*!< 0: AINA12 */ + GPIO_PP4_T32A06INA0 = GPIO_FR_2, /*!< PPFR2: T32A06INA0 */ + GPIO_PP4_T32A06INC0 = GPIO_FR_3, /*!< PPFR3: T32A06INC0 */ + GPIO_PP4_T32A06INB1 = GPIO_FR_5, /*!< PPFR5: T32A06INB1 */ +} gpio_pp4_func_t; + +/** +* @enum gpio_pp5_func_t +* @brief PortP5 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP5_AINA13 = 0, /*!< 0: AINA13 */ + GPIO_PP5_T32A06INB0 = GPIO_FR_2, /*!< PPFR2: T32A06INB0 */ + GPIO_PP5_T32A06INC1 = GPIO_FR_3, /*!< PPFR3: T32A06INC1 */ + GPIO_PP5_T32A06INA1 = GPIO_FR_5, /*!< PPFR5: T32A06INA1 */ +} gpio_pp5_func_t; + +/** + * @enum gpio_pp6_func_t + * @brief PortP6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP6_AINA14 = 0, /*!< 0: AINA14 */ + GPIO_PP6_INT10b = 0, /*!< 0: INT10b */ + GPIO_PP6_T32A07INA0 = GPIO_FR_2, /*!< PPFR2: T32A07INA0 */ + GPIO_PP6_T32A07INC0 = GPIO_FR_3, /*!< PPFR3: T32A07INC0 */ + GPIO_PP6_T32A07INB1 = GPIO_FR_5, /*!< PPFR5: T32A07INB1 */ +} gpio_pp6_func_t; + +/** +* @enum gpio_pp7_func_t +* @brief PortP7 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP7_AINA15 = 0, /*!< 0: AINA15 */ + GPIO_PP7_INT11b = 0, /*!< 0: INT11b */ + GPIO_PP7_T32A07INB0 = GPIO_FR_2, /*!< PPFR2: T32A07INB0 */ + GPIO_PP7_T32A07INC1 = GPIO_FR_3, /*!< PPFR3: T32A07INC1 */ + GPIO_PP7_T32A07INA1 = GPIO_FR_5, /*!< PPFR5: T32A07INA1 */ +} gpio_pp7_func_t; + +/** + * @enum gpio_pr0_func_t + * @brief PortR0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR0_AINA16 = 0, /*!< 0: AINA16 */ + GPIO_PR0_T32A08INA0 = GPIO_FR_2, /*!< PRFR2: T32A08INA0 */ + GPIO_PR0_T32A08INC0 = GPIO_FR_3, /*!< PRFR3: T32A08INC0 */ +} gpio_pr0_func_t; + +/** + * @enum gpio_pr1_func_t + * @brief PortR1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR1_AINA17 = 0, /*!< 0: AINA17 */ + GPIO_PR1_T32A08INB0 = GPIO_FR_2, /*!< PRFR2: T32A08INB0 */ + GPIO_PR1_T32A08INC1 = GPIO_FR_3, /*!< PRFR3: T32A08INC1 */ +} gpio_pr1_func_t; + +/** + * @enum gpio_pr2_func_t + * @brief PortR2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR2_AINA18 = 0, /*!< 0: AINA18 */ + GPIO_PR2_T32A09INA0 = GPIO_FR_2, /*!< PRFR2: T32A09INA0 */ + GPIO_PR2_T32A09INC0 = GPIO_FR_3, /*!< PRFR3: T32A09INC0 */ +} gpio_pr2_func_t; + +/** + * @enum gpio_pr3_func_t + * @brief PortR3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR3_AINA19 = 0, /*!< 0: AINA19 */ + GPIO_PR3_T32A09INB0 = GPIO_FR_2, /*!< PRFR2: T32A09INB0 */ + GPIO_PR3_T32A09INC1 = GPIO_FR_3, /*!< PRFR3: T32A09INC1 */ +} gpio_pr3_func_t; + +/** + * @enum gpio_pr4_func_t + * @brief PortR4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR4_AINA20 = 0, /*!< 0: AINA20 */ + GPIO_PR4_T32A10INA0 = GPIO_FR_2, /*!< PRFR2: T32A10INA0 */ + GPIO_PR4_T32A10INC0 = GPIO_FR_3, /*!< PRFR3: T32A10INC0 */ +} gpio_pr4_func_t; + +/** + * @enum gpio_pr5_func_t + * @brief PortR5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR5_AINA21 = 0, /*!< 0: AINA21 */ + GPIO_PR5_T32A10INB0 = GPIO_FR_2, /*!< PRFR2: T32A10INB0 */ + GPIO_PR5_T32A10INC1 = GPIO_FR_3, /*!< PRFR3: T32A10INC1 */ +} gpio_pr5_func_t; + +/** + * @enum gpio_pr6_func_t + * @brief PortR6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR6_AINA22 = 0, /*!< 0: AINA22 */ + GPIO_PR6_T32A11INA0 = GPIO_FR_2, /*!< PRFR2: T32A11INA0 */ + GPIO_PR6_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC0 */ +} gpio_pr6_func_t; + +/** + * @enum gpio_pr7_func_t + * @brief PortR7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR7_AINA23 = 0, /*!< 0: AINA23 */ + GPIO_PR7_T32A11INB0 = GPIO_FR_2, /*!< PRFR2: T32A11INB0 */ + GPIO_PR7_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC1 */ +} gpio_pr7_func_t; + + +/** + * @enum gpio_pt0_func_t + * @brief PortT0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PT0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PT0_DAC0 = GPIO_FR_NA, /*!< N/A: DAC0 */ +} gpio_pt0_func_t; + +/** + * @enum gpio_pt1_func_t + * @brief PortT1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PT1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PT1_DAC1 = GPIO_FR_NA, /*!< N/A: DAC1 */ +} gpio_pt1_func_t; + +/** + * @enum gpio_pt2_func_t + * @brief PortT2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT2_CEC0 = GPIO_FR_7, /*!< PTFR1: CEC0 Input/Output */ +} gpio_pt2_func_t; + +/** + * @enum gpio_pt3_func_t + * @brief PortT3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT3_INT00b = 0, /*!< 0: INT00b */ + GPIO_PT3_RTCOUT = GPIO_FR_1, /*!< PTFR1: RTCOUT */ + GPIO_PT3_T32A03OUTA = GPIO_FR_2, /*!< PTFR2: T32A03OUTA */ + GPIO_PT3_T32A03OUTC = GPIO_FR_3, /*!< PTFR3: T32A03OUTC */ + GPIO_PT3_RXIN0 = 0, /*!< 0: RXIN0 */ + GPIO_PT3_TRGIN2 = GPIO_FR_6, /*!< PTFR6: TRGIN2 */ +} gpio_pt3_func_t; + +/** + * @enum gpio_pt4_func_t + * @brief PortT4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT4_INT01b = 0, /*!< 0: INT01b */ + GPIO_PT4_RXIN1 = 0, /*!< 0: RXIN1 */ +} gpio_pt4_func_t; + +/** + * @enum gpio_pt5_func_t + * @brief PortT5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT5_INT02b = 0, /*!< 0: INT02b */ + GPIO_PT5_T32A03OUTB = GPIO_FR_2, /*!< PTFR2: T32A03OUTB */ +} gpio_pt5_func_t; + +/** + * @enum gpio_pu0_func_t + * @brief PortU0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU0_T32A12OUTA = GPIO_FR_2, /*!< PUFR2: T32A12OUTA */ + GPIO_PU0_T32A12OUTC = GPIO_FR_3, /*!< PUFR3: T32A12OUTC */ + GPIO_PU0_UT4TXDA = GPIO_FR_7, /*!< PUFR7: UT4TXDA */ +} gpio_pu0_func_t; + +/** + * @enum gpio_pu1_func_t + * @brief PortU1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU1_T32A12OUTB = GPIO_FR_2, /*!< PUFR2: T32A12OUTB */ + GPIO_PU1_UT4RXD = GPIO_FR_7, /*!< PUFR7: UT4RXD */ +} gpio_pu1_func_t; + +/** + * @enum gpio_pu2_func_t + * @brief PortU2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU2_INT06b = 0, /*!< 0: INT06b */ + GPIO_PU2_T32A12INA0 = GPIO_FR_2, /*!< PUFR2: T32A12INA0 */ + GPIO_PU2_T32A12INC0 = GPIO_FR_3, /*!< PUFR3: T32A12INC0 */ + GPIO_PU2_TSSI1TCK = GPIO_FR_6, /*!< PUFR6: TSSI1TCK */ + GPIO_PU2_UT4CTS_N = GPIO_FR_7, /*!< PUFR7: UT4CTS_N */ +} gpio_pu2_func_t; + +/** + * @enum gpio_pu3_func_t + * @brief PortU3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU3_INT07b = 0, /*!< 0: INT07b */ + GPIO_PU3_T32A12INB0 = GPIO_FR_2, /*!< PUFR2: T32A12INB0 */ + GPIO_PU3_T32A12INC1 = GPIO_FR_3, /*!< PUFR3: T32A12INC1 */ + GPIO_PU3_TSSI1TFS = GPIO_FR_6, /*!< PUFR6: TSSI1TFS */ + GPIO_PU3_UT4RTS_N = GPIO_FR_7, /*!< PUFR7: UT4RTS_N */ +} gpio_pu3_func_t; + +/** + * @enum gpio_pu4_func_t + * @brief PortU4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU4_INT08b = 0, /*!< 0: INT08b */ + GPIO_PU4_T32A13INB0 = GPIO_FR_2, /*!< PUFR2: T32A13INB0 */ + GPIO_PU4_T32A13INC1 = GPIO_FR_3, /*!< PUFR3: T32A13INC1 */ + GPIO_PU4_TSSI1TXD = GPIO_FR_6, /*!< PUFR6: TSSI1TXD */ + GPIO_PU4_UT3RTS_N = GPIO_FR_7, /*!< PUFR7: UT3RTS_N */ +} gpio_pu4_func_t; + +/** + * @enum gpio_pu5_func_t + * @brief PortU5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU5_INT09b = 0, /*!< 0: INT09b */ + GPIO_PU5_T32A13INA0 = GPIO_FR_2, /*!< PUFR2: T32A13INA0 */ + GPIO_PU5_T32A13INC0 = GPIO_FR_3, /*!< PUFR3: T32A13INC0 */ + GPIO_PU5_TSSI1RXD = GPIO_FR_6, /*!< PUFR6: TSSI1RXD */ + GPIO_PU5_UT3CTS_N = GPIO_FR_7, /*!< PUFR7: UT3CTS_N */ +} gpio_pu5_func_t; + +/** + * @enum gpio_pu6_func_t + * @brief PortU6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU6_T32A13OUTA = GPIO_FR_2, /*!< PUFR2: T32A13OUTA */ + GPIO_PU6_T32A13OUTC = GPIO_FR_3, /*!< PUFR3: T32A13OUTC */ + GPIO_PU6_TSSI1RFS = GPIO_FR_6, /*!< PUFR6: TSSI1RFS */ + GPIO_PU6_UT3RXD = GPIO_FR_7, /*!< PUFR7: UT3RXD */ +} gpio_pu6_func_t; + +/** + * @enum gpio_pu7_func_t + * @brief PortU7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU7_T32A13OUTB = GPIO_FR_2, /*!< PUFR2: T32A13OUTB */ + GPIO_PU7_TSSI1RCK = GPIO_FR_6, /*!< PUFR6: TSSI1RCK */ + GPIO_PU7_UT3TXDA = GPIO_FR_7, /*!< PUFR7: UT3TXDA */ +} gpio_pu7_func_t; + +/** + * @enum gpio_pv0_func_t + * @brief PortV0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV0_T32A09INA0 = GPIO_FR_2, /*!< PVFR2: T32A09INA0 */ + GPIO_PV0_T32A09INC0 = GPIO_FR_3, /*!< PVFR3: T32A09INC0 */ + GPIO_PV0_ISDBIN0 = 0, /*!< 0: ISDBIN0 */ + GPIO_PV0_UO0 = GPIO_FR_5, /*!< PVFR5: UO0 */ + GPIO_PV0_UT3RXD = GPIO_FR_6, /*!< PVFR6: UT3RXD */ + GPIO_PV0_UT3TXDA = GPIO_FR_7, /*!< PVFR7: UT3TXDA */ +} gpio_pv0_func_t; + +/** + * @enum gpio_pv1_func_t + * @brief PortV1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV1_T32A09INB0 = GPIO_FR_2, /*!< PVFR2: T32A09INB0 */ + GPIO_PV1_T32A09INC1 = GPIO_FR_3, /*!< PVFR3: T32A09INC1 */ + GPIO_PV1_ISDBIN1 = 0, /*!< 0: ISDBIN1 */ + GPIO_PV1_XO0 = GPIO_FR_5, /*!< PVFR5: XO0 */ + GPIO_PV1_UT3TXDA = GPIO_FR_6, /*!< PVFR6: UT3TXDA */ + GPIO_PV1_UT3RXD = GPIO_FR_7, /*!< PVFR7: UT3RXD */ +} gpio_pv1_func_t; + +/** + * @enum gpio_pv2_func_t + * @brief PortV2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV2_T32A09OUTA = GPIO_FR_2, /*!< PVFR2: T32A09OUTA */ + GPIO_PV2_T32A09OUTC = GPIO_FR_3, /*!< PVFR3: T32A09OUTC */ + GPIO_PV2_ISDBIN2 = 0, /*!< 0: ISDBIN2 */ + GPIO_PV2_VO0 = GPIO_FR_5, /*!< PVFR5: VO0 */ + GPIO_PV2_UT3RTS_N = GPIO_FR_6, /*!< PVFR6: UT3RTS_N */ + GPIO_PV2_UT3CTS_N = GPIO_FR_7, /*!< PVFR7: UT3CTS_N */ +} gpio_pv2_func_t; + +/** + * @enum gpio_pv3_func_t + * @brief PortV3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV3_T32A09OUTB = GPIO_FR_2, /*!< PVFR2: T32A09OUTB */ + GPIO_PV3_ISDBIN3 = 0, /*!< 0: ISDBIN3 */ + GPIO_PV3_YO0 = GPIO_FR_5, /*!< PVFR5: YO0 */ + GPIO_PV3_UT3CTS_N = GPIO_FR_6, /*!< PVFR6: UT3CTS_N */ + GPIO_PV3_UT3RTS_N = GPIO_FR_7, /*!< PVFR7: UT3RTS_N */ +} gpio_pv3_func_t; + +/** + * @enum gpio_pv4_func_t + * @brief PortV4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV4_EI2C2SCL = GPIO_FR_1, /*!< PVFR1: EI2C2SCL */ + GPIO_PV4_T32A04OUTB = GPIO_FR_2, /*!< PVFR2: T32A04OUTB */ + GPIO_PV4_TSPI5RXD = GPIO_FR_4, /*!< PVFR4: TSPI5RXD */ + GPIO_PV4_WO0 = GPIO_FR_5, /*!< PVFR5: WO0 */ + GPIO_PV4_I2C2SCL = GPIO_FR_6, /*!< PVFR6: I2C2SCL */ + GPIO_PV4_UT1RXD = GPIO_FR_7, /*!< PVFR7: UT1RXD */ +} gpio_pv4_func_t; + +/** + * @enum gpio_pv5_func_t + * @brief PortV5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV5_EI2CSDA = GPIO_FR_1, /*!< PVFR1: EI2CSDA */ + GPIO_PV5_T32A04OUTA = GPIO_FR_2, /*!< PVFR2: T32A04OUTA */ + GPIO_PV5_T32A04OUTC = GPIO_FR_3, /*!< PVFR3: T32A04OUTC */ + GPIO_PV5_TSPI5TXD = GPIO_FR_4, /*!< PVFR4: TSPI5TXD */ + GPIO_PV5_ZO0 = GPIO_FR_5, /*!< PVFR5: ZO0 */ + GPIO_PV5_I2C2SDA = GPIO_FR_6, /*!< PVFR6: I2C2SDA */ + GPIO_PV5_UT1TXDA = GPIO_FR_7, /*!< PVFR7: UT1TXDA */ +} gpio_pv5_func_t; + +/** + * @enum gpio_pv6_func_t + * @brief PortV6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV6_T32A05OUTA = GPIO_FR_2, /*!< PVFR2: T32A05OUTA */ + GPIO_PV6_T32A05OUTC = GPIO_FR_3, /*!< PVFR3: T32A05OUTC */ + GPIO_PV6_TSPI5SCK = GPIO_FR_4, /*!< PVFR4: TSPI5SCK */ + GPIO_PV6_EMG0 = GPIO_FR_5, /*!< PVFR5: EMG0 */ + GPIO_PV6_UT1CTS_N = GPIO_FR_7, /*!< PVFR7: UT1CTS_N */ +} gpio_pv6_func_t; + +/** + * @enum gpio_pv7_func_t + * @brief PortV7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV7_T32A05OUTB = GPIO_FR_2, /*!< PVFR2: T32A05OUTB */ + GPIO_PV7_TSPI5CS0 = GPIO_FR_4, /*!< PVFR4: TSPI5CS0 */ + GPIO_PV7_OVV0 = GPIO_FR_5, /*!< PVFR5: OVV0 */ + GPIO_PV7_TSPI5CSIN = GPIO_FR_6, /*!< PVFR6: TSPI5CSIN */ + GPIO_PV7_UT1RTS_N = GPIO_FR_7, /*!< PVFR7: UT1RTS_N */ +} gpio_pv7_func_t; + +/** + * @enum gpio_pw0_func_t + * @brief PortW0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW0_TSPI8CS0 = GPIO_FR_4, /*!< PWFR4: TSPI8CS0 */ + GPIO_PW0_T32A00OUTB = GPIO_FR_5, /*!< PWFR5: T32A00OUTB */ + GPIO_PW0_TSPI8CSIN = GPIO_FR_6, /*!< PWFR6: TSPI8CSIN */ +} gpio_pw0_func_t; + +/** + * @enum gpio_pw1_func_t + * @brief PortW1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW1_TSPI8SCK = GPIO_FR_4, /*!< PWFR4: TSPI8SCK */ + GPIO_PW1_T32A00OUTA = GPIO_FR_5, /*!< PWFR5: T32A00OUTA */ + GPIO_PW1_T32A00OUTC = GPIO_FR_7, /*!< PWFR7: T32A00OUTC */ +} gpio_pw1_func_t; + +/** + * @enum gpio_pw2_func_t + * @brief PortW2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW2_TSPI8RXD = GPIO_FR_4, /*!< PWFR4: TSPI8RXD */ + GPIO_PW2_T32A01OUTA = GPIO_FR_5, /*!< PWFR5: T32A01OUTA */ + GPIO_PW2_T32A01OUTC = GPIO_FR_7, /*!< PWFR7: T32A01OUTC */ +} gpio_pw2_func_t; + +/** + * @enum gpio_pw3_func_t + * @brief PortW3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW3_TSPI8TXD = GPIO_FR_4, /*!< PWFR4: TSPI8TXD */ + GPIO_PW3_T32A01OUTB = GPIO_FR_5, /*!< PWFR5: T32A01OUTB */ +} gpio_pw3_func_t; + +/** + * @enum gpio_pw4_func_t + * @brief PortW4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW4_T32A11INA1 = GPIO_FR_3, /*!< PWFR3: T32A11INA1 */ + GPIO_PW4_T32A10OUTB = GPIO_FR_5, /*!< PWFR5: T32A10OUTB */ + GPIO_PW4_ISDCIN0 = 0, /*!< 0: ISDCIN0 */ + GPIO_PW4_T32A10INA0 = GPIO_FR_7, /*!< PWFR7: T32A10INA0 */ +} gpio_pw4_func_t; + +/** + * @enum gpio_pw5_func_t + * @brief PortW5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW5_T32A10OUTA = GPIO_FR_5, /*!< PWFR5: T32A10OUTA */ + GPIO_PW5_ISDCIN1 = 0, /*!< 0: ISDCIN1 */ + GPIO_PW5_T32A10OUTC = GPIO_FR_7, /*!< PWFR7: T32A10OUTC */ +} gpio_pw5_func_t; + +/** + * @enum gpio_pw6_func_t + * @brief PortW6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW6_T32A11OUTA = GPIO_FR_5, /*!< PWFR5: T32A11OUTA */ + GPIO_PW6_ISDCIN2 = 0, /*!< 0: ISDCIN2 */ + GPIO_PW6_T32A11OUTC = GPIO_FR_7, /*!< PWFR7: T32A11OUTC */ +} gpio_pw6_func_t; + +/** + * @enum gpio_pw7_func_t + * @brief PortW7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW7_T32A10INA1 = GPIO_FR_3, /*!< PWFR3: T32A10INA1 */ + GPIO_PW7_T32A11OUTB = GPIO_FR_5, /*!< PWFR5: T32A11OUTB */ + GPIO_PW7_ISDCIN3 = 0, /*!< 0: ISDCIN3 */ + GPIO_PW7_T32A11INA0 = GPIO_FR_7, /*!< PWFR7: T32A11INA0 */ +} gpio_pw7_func_t; + +/** + * @enum gpio_py0_func_t + * @brief PortY0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY0_X1 = GPIO_FR_NA, /*!< N/A: X1 */ +} gpio_py0_func_t; + +/** + * @enum gpio_py1_func_t + * @brief PortY1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY1_X2 = GPIO_FR_NA, /*!< N/A: X2 */ +} gpio_py1_func_t; + +/** + * @enum gpio_py2_func_t + * @brief PortY2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY2_XT1 = GPIO_FR_NA, /*!< N/A: XT1 */ +} gpio_py2_func_t; + +/** + * @enum gpio_py3_func_t + * @brief PortY3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY3_XT2 = GPIO_FR_NA, /*!< N/A: XT2 */ +} gpio_py3_func_t; + +/** + * @enum gpio_py4_func_t + * @brief PortY4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PY4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PY4_ISDCOUT = GPIO_FR_1, /*!< PYFR1: ISDCOUT */ + GPIO_PY4_EEXBCLK = GPIO_FR_4, /*!< PYFR4: EEXBCLK */ +} gpio_py4_func_t; + +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_typedef GPIO Private Typedef + * @{ + */ +/*! + * @brief Pin Exist Table + * @details Bit0 :GPIO_Mode_DATA + * @details Bit1 :GPIO_Mode_CR + * @details Bit2 :GPIO_Mode_FR1 + * @details Bit3 :GPIO_Mode_FR2 + * @details Bit4 :GPIO_Mode_FR3 + * @details Bit5 :GPIO_Mode_FR4 + * @details Bit6 :GPIO_Mode_FR5 + * @details Bit7 :GPIO_Mode_FR6 + * @details Bit8 :GPIO_Mode_FR7 + * @details Bit9 :GPIO_Mode_FR8 + * @details Bit10 :GPIO_Mode_OD + * @details Bit11 :GPIO_Mode_PUP + * @details Bit12 :GPIO_Mode_PDN + * @details Bit13 :GPIO_Mode_IE + */ +static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = { + /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ + { GPIO_PORT_A_0, GPIO_PORT_A_1, GPIO_PORT_A_2, GPIO_PORT_A_3, GPIO_PORT_A_4, GPIO_PORT_A_5, GPIO_PORT_A_6, GPIO_PORT_A_7 }, /** GPIO_PORT_A */ + { GPIO_PORT_B_0, GPIO_PORT_B_1, GPIO_PORT_B_2, GPIO_PORT_B_3, GPIO_PORT_B_4, GPIO_PORT_B_5, GPIO_PORT_B_6, GPIO_PORT_B_7 }, /** GPIO_PORT_B */ + { GPIO_PORT_C_0, GPIO_PORT_C_1, GPIO_PORT_C_2, GPIO_PORT_C_3, GPIO_PORT_C_4, GPIO_PORT_C_5, GPIO_PORT_C_6, GPIO_PORT_C_7 }, /** GPIO_PORT_C */ + { GPIO_PORT_D_0, GPIO_PORT_D_1, GPIO_PORT_D_2, GPIO_PORT_D_3, GPIO_PORT_D_4, GPIO_PORT_D_5, GPIO_PORT_D_6, GPIO_PORT_D_7 }, /** GPIO_PORT_D */ + { GPIO_PORT_E_0, GPIO_PORT_E_1, GPIO_PORT_E_2, GPIO_PORT_E_3, GPIO_PORT_E_4, GPIO_PORT_E_5, GPIO_PORT_E_6, GPIO_PORT_E_7 }, /** GPIO_PORT_E */ + { GPIO_PORT_F_0, GPIO_PORT_F_1, GPIO_PORT_F_2, GPIO_PORT_F_3, GPIO_PORT_F_4, GPIO_PORT_F_5, GPIO_PORT_F_6, GPIO_PORT_F_7 }, /** GPIO_PORT_F */ + { GPIO_PORT_G_0, GPIO_PORT_G_1, GPIO_PORT_G_2, GPIO_PORT_G_3, GPIO_PORT_G_4, GPIO_PORT_G_5, GPIO_PORT_G_6, GPIO_PORT_G_7 }, /** GPIO_PORT_G */ + { GPIO_PORT_H_0, GPIO_PORT_H_1, GPIO_PORT_H_2, GPIO_PORT_H_3, GPIO_PORT_H_4, GPIO_PORT_H_5, GPIO_PORT_H_6, GPIO_PORT_H_7 }, /** GPIO_PORT_H */ + { GPIO_PORT_J_0, GPIO_PORT_J_1, GPIO_PORT_J_2, GPIO_PORT_J_3, GPIO_PORT_J_4, GPIO_PORT_J_5, GPIO_PORT_J_6, GPIO_PORT_J_7 }, /** GPIO_PORT_J */ + { GPIO_PORT_K_0, GPIO_PORT_K_1, GPIO_PORT_K_2, GPIO_PORT_K_3, GPIO_PORT_K_4, GPIO_PORT_K_5, GPIO_PORT_K_6, GPIO_PORT_K_7 }, /** GPIO_PORT_K */ + { GPIO_PORT_L_0, GPIO_PORT_L_1, GPIO_PORT_L_2, GPIO_PORT_L_3, GPIO_PORT_L_4, GPIO_PORT_L_5, GPIO_PORT_L_6, GPIO_PORT_L_7 }, /** GPIO_PORT_L */ + { GPIO_PORT_M_0, GPIO_PORT_M_1, GPIO_PORT_M_2, GPIO_PORT_M_3, GPIO_PORT_M_4, GPIO_PORT_M_5, GPIO_PORT_M_6, GPIO_PORT_M_7 }, /** GPIO_PORT_M */ + { GPIO_PORT_N_0, GPIO_PORT_N_1, GPIO_PORT_N_2, GPIO_PORT_N_3, GPIO_PORT_N_4, GPIO_PORT_N_5, GPIO_PORT_N_6, GPIO_PORT_N_7 }, /** GPIO_PORT_N */ + { GPIO_PORT_P_0, GPIO_PORT_P_1, GPIO_PORT_P_2, GPIO_PORT_P_3, GPIO_PORT_P_4, GPIO_PORT_P_5, GPIO_PORT_P_6, GPIO_PORT_P_7 }, /** GPIO_PORT_P */ + { GPIO_PORT_R_0, GPIO_PORT_R_1, GPIO_PORT_R_2, GPIO_PORT_R_3, GPIO_PORT_R_4, GPIO_PORT_R_5, GPIO_PORT_R_6, GPIO_PORT_R_7 }, /** GPIO_PORT_R */ + { GPIO_PORT_T_0, GPIO_PORT_T_1, GPIO_PORT_T_2, GPIO_PORT_T_3, GPIO_PORT_T_4, GPIO_PORT_T_5, GPIO_PORT_T_6, GPIO_PORT_T_7 }, /** GPIO_PORT_T */ + { GPIO_PORT_U_0, GPIO_PORT_U_1, GPIO_PORT_U_2, GPIO_PORT_U_3, GPIO_PORT_U_4, GPIO_PORT_U_5, GPIO_PORT_U_6, GPIO_PORT_U_7 }, /** GPIO_PORT_U */ + { GPIO_PORT_V_0, GPIO_PORT_V_1, GPIO_PORT_V_2, GPIO_PORT_V_3, GPIO_PORT_V_4, GPIO_PORT_V_5, GPIO_PORT_V_6, GPIO_PORT_V_7 }, /** GPIO_PORT_V */ + { GPIO_PORT_W_0, GPIO_PORT_W_1, GPIO_PORT_W_2, GPIO_PORT_W_3, GPIO_PORT_W_4, GPIO_PORT_W_5, GPIO_PORT_W_6, GPIO_PORT_W_7 }, /** GPIO_PORT_W */ + { GPIO_PORT_Y_0, GPIO_PORT_Y_1, GPIO_PORT_Y_2, GPIO_PORT_Y_3, GPIO_PORT_Y_4, GPIO_PORT_Y_5, GPIO_PORT_Y_6, GPIO_PORT_Y_7 }, /** GPIO_PORT_Y */ +}; +/** + * @} + */ /* End of group GPIO_Private_typedef */ +/*----------------------------------*/ +/** + * @brief GPIO handle structure definition. +*/ +/*----------------------------------*/ +typedef struct gpio_pa_handle { + TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ + TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ + TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ + TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ + TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ + TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ + TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ + TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ + TSB_PJ_TypeDef *p_pj_instance; /*!< Registers base address. */ + TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ + TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ + TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */ + TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ + TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ + TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */ + TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ + TSB_PU_TypeDef *p_pu_instance; /*!< Registers base address. */ + TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ + TSB_PW_TypeDef *p_pw_instance; /*!< Registers base address. */ + TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ +} _gpio_t; + +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ + +/** + * @} + */ /* End of group GPIO */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __GPIO_M4GR_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_hal.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_hal.h new file mode 100644 index 00000000000..6df6fc1765c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_hal.h @@ -0,0 +1,147 @@ +/** + ******************************************************************************* + * @file txz_hal.h + * @brief This file provides all the functions prototypes for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __HAL_H +#define __HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup HAL HAL + * @brief HAL Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_macro HAL Exported Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_define HAL Exported Define + * @{ + */ +#if defined ( __CC_ARM ) /* RealView Compiler */ +extern uint32_t Load$$FLASH_CODE_RAM$$Base; +extern uint32_t Image$$FLASH_CODE_RAM$$Base; +extern uint32_t Load$$FLASH_CODE_RAM$$Length; + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ +#pragma section = "FLASH_CODE_RAM" +#pragma section = "FLASH_CODE_ROM" +#endif + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#define FLASH_API_ROM (uint32_t *)&Load$$FLASH_CODE_RAM$$Base +#define FLASH_API_RAM (uint32_t *)&Image$$FLASH_CODE_RAM$$Base +#define SIZE_FLASH_API (uint32_t)&Load$$FLASH_CODE_RAM$$Length + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ +#define FLASH_API_ROM ((uint32_t *)__section_begin("FLASH_CODE_ROM")) +#define FLASH_API_RAM ((uint32_t *)__section_begin("FLASH_CODE_RAM")) +#define SIZE_FLASH_API ((uint32_t)__section_size("FLASH_CODE_ROM")) +#endif + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_define HAL Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_typedef HAL Exported Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_functions HAL Exported Functions + * @{ + */ + +void hal_inc_tick(void); +uint32_t hal_get_tick(void); +void wait(uint32_t count); +void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size); +void fc_ram_con_reg_set(uint32_t sysclock); + +/** + * @} + */ /* End of group HAL_Exported_functions */ + +/** + * @} + */ /* End of group HAL */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __HAL_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c.h new file mode 100644 index 00000000000..df0a5e9715c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c.h @@ -0,0 +1,805 @@ +/** + ******************************************************************************* + * @file txz_i2c.h + * @brief This file provides all the functions prototypes for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __I2C_H +#define __I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +#ifdef __DEBUG__ +/** + * @name I2C_NULL Pointer + * @brief NULL Pointer. + * @{ + */ +#define I2C_NULL ((void *)0) +/** + * @} + */ /* End of name I2C_NULL Pointer */ +#endif + +/** + * @name I2CxST Macro Definition. + * @brief I2CxST Register Macro Definition. + * @{ + */ +#define I2CxST_NACK ((uint32_t)0x00000008) /*!< NACK Interrupt Status. */ +#define I2CxST_I2CBF ((uint32_t)0x00000004) /*!< I2CBF Interrupt Status. */ +#define I2CxST_I2CAL ((uint32_t)0x00000002) /*!< I2CAL Interrupt Status. */ +#define I2CxST_I2C ((uint32_t)0x00000001) /*!< I2C Interrupt Status. */ +#define I2CxST_CLEAR ((uint32_t)0x0000000F) /*!< All Bits Clear. */ +/** + * @} + */ /* End of name I2CxST Macro Definition */ + +/** + * @name I2CxCR1 Macro Definition. + * @brief I2CxCR1 Register Macro Definition. + * @{ + */ +#define I2CxCR1_ACK ((uint32_t)0x00000010) /*!< ACK */ +#define I2CxCR1_NOACK ((uint32_t)0x00000008) /*!< NOACK */ +#define I2CxCR1_BC ((uint32_t)0x000000E0) /*!< BC */ + +/** + * @} + */ /* End of name I2CxCR1 Macro Definition */ + +/** + * @name I2CxDBR Macro Definition. + * @brief I2CxDBR Register Macro Definition. + * @{ + */ +#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */ +/** + * @} + */ /* End of name I2CxDBR Macro Definition */ + + +/** + * @name I2CxCR2 Macro Definition. + * @brief I2CxCR2 Register Macro Definition. + * @{ + */ +#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) /*!< PIN=1 */ +#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) /*!< I2CM=0 */ +#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) /*!< I2CM=1 */ +#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) /*!< SWRES=10 */ +#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) /*!< SWRES=01 */ +#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) /*!< MST=1,TRX=1,BB=1,PIN=1,I2CM=1 */ +#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) /*!< MST=1,TRX=1,BB=0,PIN=1,I2CM=1 */ +#define I2CxCR2_INIT ((uint32_t)0x00000008) /*!< MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00 */ + +/** + * @} + */ /* End of name I2CxCR2 Macro Definition */ + +/** + * @name I2CxSR Macro Definition. + * @brief I2CxSR Register Macro Definition. + * @{ + */ +#define I2CxSR_MST ((uint32_t)0x00000080) /*!< MST */ +#define I2CxSR_TRX ((uint32_t)0x00000040) /*!< TRX */ +#define I2CxSR_BB ((uint32_t)0x00000020) /*!< BB */ +#define I2CxSR_PIN ((uint32_t)0x00000010) /*!< PIN */ +#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ +#define I2CxSR_AAS ((uint32_t)0x00000004) /*!< AAS */ +#define I2CxSR_AD0 ((uint32_t)0x00000002) /*!< AD0 */ +#define I2CxSR_LRB ((uint32_t)0x00000001) /*!< LRB */ +/** + * @} + */ /* End of name I2CxSR Macro Definition */ + +/** + * @name I2CxPRS Macro Definition. + * @brief I2CxPRS Register Macro Definition. + * @{ + */ +#define I2CxPRS_PRCK ((uint32_t)0x0000001F) /*!< PRCK */ +/** + * @} + */ /* End of name I2CxPRS Macro Definition */ + +/** + * @name I2CxIE Macro Definition. + * @brief I2CxIE Register Macro Definition. + * @{ + */ +#define I2CxIE_SELPINCD ((uint32_t)0x00000040) /*!< SELPINCD */ +#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) /*!< DMARI2CTX */ +#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) /*!< DMARI2CRX */ +#define I2CxIE_I2C ((uint32_t)0x00000001) /*!< INTI2C */ +#define I2CxIE_CLEAR ((uint32_t)0x00000000) /*!< All Clear Setting */ + +/** + * @} + */ /* End of name I2CxIE Macro Definition */ + + +/** + * @name I2CxOP Macro Definition. + * @brief I2CxOP Register Macro Definition. + * @{ + */ +#define I2CxOP_DISAL ((uint32_t)0x00000080) /*!< DISAL */ +#define I2CxOP_SA2ST ((uint32_t)0x00000040) /*!< SA2ST */ +#define I2CxOP_SAST ((uint32_t)0x00000020) /*!< SAST */ +#define I2CxOP_RSTA ((uint32_t)0x00000008) /*!< RSTA */ +#define I2CxOP_GCDI ((uint32_t)0x00000004) /*!< GDDI */ +#define I2CxOP_SREN ((uint32_t)0x00000002) /*!< SREN */ +#define I2CxOP_MFACK ((uint32_t)0x00000001) /*!< MFACK */ +#ifndef I2C_MULTI_MASTER +#define I2CxOP_INIT ((uint32_t)0x00000084) /*!< Initial Settings. */ +#else +#define I2CxOP_INIT ((uint32_t)0x00000004) /*!< Initial Settings. */ +#endif +#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) /*!< Slave Initial Settings. */ +/** + * @} + */ /* End of name I2CxOP Macro Definition */ + +/** + * @name I2CxAR Macro Definition. + * @brief I2CxAR Register Macro Definition. + * @{ + */ +#define I2CxAR_ALS ((uint32_t)0x00000001) /*!< ALS. */ +#define I2CxAR_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ +#define I2CxAR2_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ + +/** + * @} + */ /* End of name I2CxAR Macro Definition */ + + +/** + * @name I2CxPM Macro Definition. + * @brief I2CxPM Register Macro Definition. + * @{ + */ +#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */ +/** + * @} + */ /* End of name I2CxPM Macro Definition */ + +/** + * @name I2CxWUPCR_INT Macro Definition. + * @brief I2CxWUPCR_INT Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */ +#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */ +/** + * @} + */ /* End of name I2CxWUPCR_INT Macro Definition */ + +/** + * @name I2CxWUPCR_RST Macro Definition. + * @brief I2CxWUPCR_RST Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */ +#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */ +/** + * @} + */ /* End of name I2CxWUPCR_RST Macro Definition */ + + +/** + * @name I2CxWUPCR_ACK Macro Definition. + * @brief I2CxWUPCR_ACK Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */ +#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */ +/** + * @} + */ /* End of name I2CxWUPCR_RST Macro Definition */ +/** + * @} + */ /* End of group UTILITIES_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Clock setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sck; /*!< Select internal SCL output clock frequency. */ + uint32_t prsck; /*!< Prescaler clock frequency for generating the Serial clock. */ +} I2C_clock_setting_t; + +/*----------------------------------*/ +/** + * @brief Wakeup Control setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sgcdi; /*!< Select general call detect ON/OFF. */ + uint32_t ack; /*!< Select ACK output. */ + uint32_t reset; /*!< I2C BUS Rest. */ + uint32_t intend; /*!< Interrupt release. */ +} I2CS_wup_setting_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + I2C_clock_setting_t clock; /*!< Serial clock setting. */ +} I2C_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + I2CS_wup_setting_t wup; /*!< Wakeup Control setting. */ +} I2CS_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief I2C handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_I2C_TypeDef *p_instance; /*!< Registers base address. */ + I2C_initial_setting_t init; /*!< Initial setting. */ +} I2C_t; +#if defined(I2CSxWUP_EN) +/*----------------------------------*/ +/** + * @brief I2CS handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_I2CS_TypeDef *p_instance; /*!< Registers base address. */ + I2CS_initial_setting_t init; /*!< Initial setting. */ +} I2CS_t; +#endif +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +__STATIC_INLINE void I2C_reset(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj); +__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj); +__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj); +__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data); +__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj); +__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack); +__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj); +__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj); +__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj); +__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx); +__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj); +__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr); +__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj); + +/*--------------------------------------------------*/ +/** + * @brief I2C software reset. + * @param p_obj :I2C object. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_reset(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; + p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; + } +#else + p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; + p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief I2C bus port high + * @param p_obj :I2C object. + * @retval true :SDA and SCL Port High. + * @retval false :Bus Error. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); + } + return (0); +#else + return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Generate stop condition. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; + } +#else + p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Read from Data buffer + * @param p_obj :I2C object. + * @retval result :Read data. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); + } + return (0); +#else + return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Write to Data buffer. + * @param p_obj :I2C object. + * @param data :Write data. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); + } +#else + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return restart condition + * @param p_obj :I2C object. + * @retval true :Restart Detected. + * @retval false :Restart Non-Detected. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + __IO uint32_t opreg = p_obj->p_instance->OP; + p_obj->p_instance->OP &= ~I2CxOP_RSTA; + return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); + } + return (0); +#else + __IO uint32_t opreg = p_obj->p_instance->OP; + p_obj->p_instance->OP &= ~I2CxOP_RSTA; + return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Set Ack condition + * @param p_obj :I2C object. + * @param nack :1 NACK, 0 ACK. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + if (nack) { + p_obj->p_instance->OP |= I2CxOP_MFACK; + } else { + p_obj->p_instance->OP &= ~I2CxOP_MFACK; + } + } +#else + if (nack) { + p_obj->p_instance->OP |= I2CxOP_MFACK; + } else { + p_obj->p_instance->OP &= ~I2CxOP_MFACK; + } +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return received Ack condition + * @param p_obj :I2C object. + * @retval true :NACK Received. + * @retval false :ACK Received. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return Busy condition + * @param p_obj :I2C object. + * @retval true :I2C bus busy. + * @retval false :I2C bus free. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return The Master status + * @param p_obj :I2C object. + * @retval true :Master mode. + * @retval false :Slave mode. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return The Transmitter + * @param p_obj :I2C object. + * @retval true :Transmitter. + * @retval false :Receiver. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Interrupt Status + * @param p_obj :I2C object. + * @retval true :Interrupt Occurred. + * @retval false :No Interrupt Occurred. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); + } + return (0); +#else + return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Interrupt Status Clear + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->ST = I2CxST_CLEAR; + } +#else + p_obj->p_instance->ST = I2CxST_CLEAR; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->IE = I2CxIE_I2C; + } +#else + p_obj->p_instance->IE = I2CxIE_I2C; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt setting. + * @param p_obj :I2C object. + * @param tx :Direction of transfer(1=tx 0=rx). + * @retval - + * @note For DMA transfer. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + if (tx) { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); + } else { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); + } + } +#else + if (tx) { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); + } else { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); + } +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable Interrupt setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->IE = I2CxIE_CLEAR; + } +#else + p_obj->p_instance->IE = I2CxIE_CLEAR; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Set slave address. + * @param p_obj :I2C object. + * @param addr :slave address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); + p_obj->p_instance->AR2 = I2CxAR2_INIT; + } +#else + p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); + p_obj->p_instance->AR2 = I2CxAR2_INIT; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Detecting Slave Address + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) + && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); + } + return (0); +#else + return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) + && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); +#endif +} + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +void I2C_init(I2C_t *p_obj); +void I2C_start_condition(I2C_t *p_obj, uint32_t data); +uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting); +void I2C_slave_init(I2C_t *p_obj); +#if defined(I2CSxWUP_EN) +void I2CS_init(I2CS_t *p_obj); +void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); +void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); +#endif +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __I2C_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c_api.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c_api.h new file mode 100644 index 00000000000..e279430d571 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c_api.h @@ -0,0 +1,308 @@ +/** + ******************************************************************************* + * @file i2c_api.h + * @brief This file provides all the functions prototypes for I2C Driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __BSP_I2C_H +#define __BSP_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_i2c.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ +/** + * @defgroup I2C_NullPointer Null Pointer + * @brief I2C NULL Pointer. + * @{ + */ +#define I2C_NULL ((void *)0) +/** + * @} + */ /* End of group I2C_NullPointer */ + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ + +/** + * @defgroup I2C_ACK I2C ACK Macros + * @brief I2C Type of Acknowledge. + * @{ + */ +#define I2C_NACK (0) /*!< NACK Received. */ +#define I2C_ACK (1) /*!< ACK Received. */ +/** + * @} + */ /* End of group I2C_ACK */ + + +/** + * @defgroup I2C_ERROR I2C ERROR Macros + * @brief I2C Error definitions. + * @{ + */ +#define I2C_ERROR_NO_ERROR (0) /*!< No Error. */ +#if 0 +#define I2C_ERROR_NO_SLAVE (-1) /*!< No Slave Error. */ +#define I2C_ERROR_BUS_BUSY (-2) /*!< Bus Busy Error.(now, not support) */ +#endif +#define I2C_ERROR_PARAM (-3) /*!< Parameter Error. */ +#define I2C_ERROR_OTHERS (-4) /*!< Others Error. */ +#define I2C_ERROR_ARBITRATION (-5) /*!< Arbitration Error. */ +/** + * @} + */ /* End of group I2C_ERROR */ + + +/** + * @defgroup I2C_Events I2C Events Macros + * @brief I2C Asynch Events. + * @{ + */ +#define I2C_EVENT_ERROR (1 << 1) /*!< Error. */ +#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) /*!< No Slave. */ +#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) /*!< Transfer Complete. */ +#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) /*!< End of Transfer. */ +#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK) +/** + * @} + */ /* End of group I2C_Events */ + +/** + * @defgroup I2C_SlaveReceive I2C Slave Receive Return Macros + * @brief I2C Received Contents of Slave. + * @{ + */ +#define I2C_NO_DATA (0) /*!< the slave has not been addressed. */ +#define I2C_READ_ADDRESSED (1) /*!< the master has requested a read from this slave. */ +#define I2C_WRITE_GENERAL (2) /*!< the master is writing to all slave.(now, not support) */ +#define I2C_WRITE_ADDRESSED (3) /*!< the master is writing to this slave. */ +/** + * @} + */ /* End of group I2C_SlaveReceive */ + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ + +/*----------------------------------*/ +/** + * @brief i2c Port Enumerated Type Definition. +*/ +/*----------------------------------*/ +typedef enum { + I2C_PORT_PG2 = 0, /*!< 0: PG2 I2C0 */ + I2C_PORT_PG3, /*!< 1: PG3 I2C0 */ + I2C_PORT_PF2, /*!< 2: PF2 I2C1 */ + I2C_PORT_PF3, /*!< 3: PF3 I2C1 */ + I2C_PORT_PG4, /*!< 4: PG4 I2C2 */ + I2C_PORT_PG5, /*!< 5: PG5 I2C2 */ + I2C_PORT_PJ6, /*!< 6: PJ6 I2C3 */ + I2C_PORT_PJ7, /*!< 7: PJ7 I2C3 */ + I2C_PORT_PJ2, /*!< 8: PJ2 I2C4 */ + I2C_PORT_PJ3, /*!< 9: PJ3 I2C4 */ +} +i2c_port_t; + +/*----------------------*/ +/* I2C Setting */ +/*----------------------*/ +/* #define I2C_CHANNEL0 */ +#define I2C_CHANNEL3 +/* #define I2C_CHANNEL2 */ +/* #define I2C_CHANNEL3 */ +/* #define I2C_CHANNEL4 */ +#if defined(I2C_CHANNEL0) +#define I2Cx_TEXT "I2C0" +#define I2C_CFG_PORT_SCL (I2C_PORT_PG3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PG2) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL1) +#define I2Cx_TEXT "I2C1" +#define I2C_CFG_PORT_SCL (I2C_PORT_PF3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PF2) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL2) +#define I2Cx_TEXT "I2C2" +#define I2C_CFG_PORT_SCL (I2C_PORT_PG5) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PG4) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL3) +#define I2Cx_TEXT "I2C3" +#define I2C_CFG_PORT_SCL (I2C_PORT_PJ7) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PJ6) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL4) +#define I2Cx_TEXT "I2C4" +#define I2C_CFG_PORT_SCL (I2C_PORT_PJ3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PJ2) /*!< SDA Port. */ +#else +#error "target channel is non-select." +#endif + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief I2C internal information structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t bus_free; /*!< Bus free information. */ + uint8_t start; /*!< Start condition information. */ + uint32_t irqn; /*!< IRQ number table pointer. */ + struct { + uint32_t address; /*!< Slave address. */ + uint32_t stop; /*!< Stop control */ + uint32_t event; /*!< I2C Event information. */ + uint32_t state; /*!< Transfer State. */ + } asynch; +} i2c_internal_info_t; + +/*----------------------------------*/ +/** + * @brief I2C buffer structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_buffer; /*!< Buffer address. */ + uint32_t length; /*!< Buffer length. */ + uint32_t pos; /*!< Buffer pointer. */ +} i2c_buffer_t; + +/*----------------------------------*/ +/** + * @brief I2C handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + I2C_t i2c; /*!< I2C class structure. */ + i2c_internal_info_t info; /*!< Internal Information. */ + i2c_buffer_t tx_buff; /*!< Tx buffer structure. */ + i2c_buffer_t rx_buff; /*!< Rx buffer structure. */ +} _i2c_t; + +/** + * @} + */ /* End of group UTILITIES_Exported_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_functions + * @{ + */ +TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl); +TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz); +void i2c_reset_t(_i2c_t *p_obj); +TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj); +TXZ_Result i2c_start_t(_i2c_t *p_obj); +TXZ_Result i2c_stop_t(_i2c_t *p_obj); +int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); +int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); +int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last); +int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data); +uint8_t i2c_active_t(_i2c_t *p_obj); +TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop); +uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj); +void i2c_abort_asynch_t(_i2c_t *p_obj); +uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn); + +/* For slave */ +void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave); +int32_t i2c_slave_receive_t(_i2c_t *p_obj); +int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); +int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); +void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address); +TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length); +uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj); +void i2c_slave_abort_asynch_t(_i2c_t *p_obj); + +/** + * @} + */ /* End of group UTILITIES_Exported_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __BSP_I2C_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_t32a.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_t32a.h new file mode 100644 index 00000000000..9d27b6318df --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_t32a.h @@ -0,0 +1,1000 @@ +/** + ******************************************************************************* + * @file txz_t32a.h + * @brief This file provides all the functions prototypes for T32A driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __T32A_H +#define __T32A_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup T32A T32A + * @brief T32A Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Exported_define T32A Exported Define + * @{ + */ + +/** + * @defgroup T32A_Result Result + * @brief T32A Result Macro Definition. + * @{ + */ +#define T32A_RESULT_SUCCESS (0) /*!< Success */ +#define T32A_RESULT_FAILURE (-1) /*!< Failure */ +#define T32A_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ +/** + * @} + */ /* End of group T32A_Result */ + +/** + * @defgroup T32A_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define T32A_NULL ((void *)0) /*!< NULL Pointer For T32A */ +/** + * @} + */ /* End of group T32A_NullPointer */ + +/** +* @defgroup T32A_HALT T32A Debug HALT Control +* @brief Debug HALT Control Run/Stop HALT Macro Definition. +* @{ +*/ +#define T32A_DBG_HALT_RUN ((uint32_t)0x00000000) /*!< Run */ +#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) /*!< Stop */ +/** + * @} + */ /* End of group T32A_HALT */ + +/** +* @defgroup T32A_MODE32 T32A 16bit/32bit MODE +* @brief T32A 16bit/32bit MODE MODE32 Macro Definition. +* @{ +*/ +#define T32A_MODE_16 ((uint32_t)0x00000000) /*!< 16bit Mode */ +#define T32A_MODE_32 ((uint32_t)0x00000001) /*!< 32bit Mode */ +/** + * @} + */ /* End of group T32A_MODE32 */ + +/** +* @defgroup T32A_RUNFLGx T32A RUNFLG Control +* @brief Run/Stop RUNFLGx Macro Definition. +* @{ +*/ +#define T32A_RUNFLG_RUN ((uint32_t)0x00000010) /*!< Run */ +#define T32A_RUNFLG_STOP ((uint32_t)0x00000000) /*!< Stop */ +/** + * @} + */ /* End of group T32A_RUNFLGx */ + +/** + * @defgroup T32A_SFTSTPx T32A SW STOP Control + * @brief T32A SW STOPx SFTSTPx Macro Definition. + * @{ + */ +#define T32A_COUNT_DONT_STOP ((uint32_t)0x0000000) /*!< No effect */ +#define T32A_COUNT_STOP ((uint32_t)0x0000004) /*!< Counter Stop */ +/** + * @} + */ /* End of group T32A_SFTSTPx */ + +/** + * @defgroup T32A_SFTSTAx T32A SW START Control + * @brief T32A SW STARTx SFTSTAx Macro Definition. + * @{ + */ +#define T32A_COUNT_DONT_START ((uint32_t)0x0000000) /*!< No effect */ +#define T32A_COUNT_START ((uint32_t)0x0000002) /*!< Counter Start */ +/** + * @} + */ /* End of group T32A_SFTSTAx */ + +/** + * @defgroup T32A_RUNx T32A RUN Disable/Enable Control + * @brief RUN Disable/Enable RUNx Macro Definition. + * @{ + */ +#define T32A_RUN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define T32A_RUN_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group T32A_RUNx */ + + +/** + * @defgroup T32A_PRSCLx T32A PRESCALER Control + * @brief PRESCALER Control PRSCLx Macro Definition. + * @{ + */ +#define T32A_PRSCLx_1 ((uint32_t)0x00000000) /*!< 1/1 */ +#define T32A_PRSCLx_2 ((uint32_t)0x10000000) /*!< 1/2 */ +#define T32A_PRSCLx_8 ((uint32_t)0x20000000) /*!< 1/8 */ +#define T32A_PRSCLx_32 ((uint32_t)0x30000000) /*!< 1/32 */ +#define T32A_PRSCLx_128 ((uint32_t)0x40000000) /*!< 1/128 */ +#define T32A_PRSCLx_256 ((uint32_t)0x50000000) /*!< 1/256 */ +#define T32A_PRSCLx_512 ((uint32_t)0x60000000) /*!< 1/512 */ +#define T32A_PRSCLx_1024 ((uint32_t)0x70000000) /*!< 1/1024 */ +/** + * @} + */ /* End of group T32A_PRSCLx */ + +/** + * @defgroup T32A_CLKx T32A COLCK Control + * @brief CLOCK Control CLKA Macro Definition. + * @{ + */ +#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /*!< prescaler */ +#define T32A_CLKx_INTRG ((uint32_t)0x01000000) /*!< internal triger */ +#define T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000) /*!< other timer rising edge */ +#define T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000) /*!< other timer trailing edge */ +#define T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000) /*!< external triger rising edge */ +#define T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) /*!< external triger trailing edge */ +/** + * @} + */ /* End of group T32A_CLKx */ + +/** + * @defgroup T32A_WBFx T32A Double Buffer Disable/Enable Control + * @brief Double Buffer Disable/Enable WBFx Macro Definition. + * @{ + */ +#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /*!< Enable */ +/** + * @} + */ /* End of group T32A_WBFx */ + +/** +* @defgroup T32A_UPDNx T32A Counter Up/Down Control +* @brief Counter Up/Down Control UPDNx Macro Definition. +* @{ +*/ +#define T32A_COUNT_UP ((uint32_t)0x00000000) /*!< count up */ +#define T32A_COUNT_DOWN ((uint32_t)0x00010000) /*!< count down */ +#define T32A_COUNT_UPDOWN ((uint32_t)0x00020000) /*!< count updown */ +#define T32A_COUNT_PLS ((uint32_t)0x00030000) /*!< count pulse */ +/** + * @} + */ /* End of group T32A_UPDNx */ + +/** +* @defgroup T32A_RELDx T32A Counter Reload Control +* @brief Counter Reload Control RELDx Macro Definition. +* @{ +*/ +#define T32A_RELOAD_NON ((uint32_t)0x00000000) /*!< Nothing(Free run) */ +#define T32A_RELOAD_INTRG ((uint32_t)0x00000100) /*!< internal trigger */ +#define T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200) /*!< external trigger rising edge */ +#define T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300) /*!< external trigger trailing edge */ +#define T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400) /*!< other timer rising edge */ +#define T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500) /*!< other timer trailing edge */ +#define T32A_RELOAD_SYNC ((uint32_t)0x00000600) /*!< sync(slave channel) */ +#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /*!< match up Timer Register */ +/** + * @} + */ /* End of group T32A_RELDx */ + +/** +* @defgroup T32A_STOPx T32A Counter Stop Control +* @brief Counter Stop Control STOPx Macro Definition. +* @{ +*/ +#define T32A_STOP_NON ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_STOP_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ +#define T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020) /*!< external trigger rising edge */ +#define T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030) /*!< external trigger trailing edge */ +#define T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040) /*!< other timer rising edge */ +#define T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050) /*!< other timer trailing edge */ +#define T32A_STOP_SYNC ((uint32_t)0x00000060) /*!< sync(slave channel) */ +#define T32A_STOP_TREGx ((uint32_t)0x00000070) /*!< match up Timer Register A */ +/** + * @} + */ /* End of group T32A_STOPx */ + + +/** +* @defgroup T32A_STARTx T32A Counter Start Control +* @brief Counter Start Control STARTx Macro Definition. +* @{ +*/ +#define T32A_START_NON ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_START_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ +#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /*!< external trigger rising edge */ +#define T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003) /*!< external trigger trailing edge */ +#define T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004) /*!< other timer rising edge */ +#define T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005) /*!< other timer trailing edge */ +#define T32A_START_SYNC ((uint32_t)0x00000006) /*!< sync(slave channel) */ +#define T32A_START_Rsvd ((uint32_t)0x00000007) /*!< Reserved */ +/** + * @} + */ /* End of group T32A_STARTx */ + +/** + * @defgroup T32A_OCRx T32AxOUTA Control + * @brief T32AxOUTA Control OCRx Macro Definition. + * @{ + */ +#define T32A_OCR_DISABLE ((uint32_t)0x00000000) /*!< Nothing */ +#define T32A_OCR_SET ((uint32_t)0x00000001) /*!< Hi */ +#define T32A_OCR_CLR ((uint32_t)0x00000002) /*!< Low */ +#define T32A_OCR_INVERSION ((uint32_t)0x00000003) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRx */ + +/** + * @defgroup T32A_OCRCAPx1 T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 + * @brief T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 OCRCAPx1 Macro Definition. + * @{ + */ +#define T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCAPx1_SET ((uint32_t)0x00000040) /*!< Hi */ +#define T32A_OCRCAPx1_CLR ((uint32_t)0x00000080) /*!< Low */ +#define T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCAPx1 */ + +/** + * @defgroup T32A_OCRCAPx0 T32AxOUTA Control of T32AxCAPx0 counter value + * @brief T32AxOUTA Control of T32AxCAPx0 T32AxRGx1 OCRCAPx0 Macro Definition. + * @{ + */ +#define T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCAPx0_SET ((uint32_t)0x00000010) /*!< Hi */ +#define T32A_OCRCAPx0_CLR ((uint32_t)0x00000020) /*!< Low */ +#define T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCAPx0 */ + +/** + * @defgroup T32A_OCRCMPx1 T32AxOUTA Control of T32AxRGx1 Counter Value + * @brief T32AxOUTA Control of T32AxRGx1 Counter Value OCRCMPx1 Macro Definition. + * @{ + */ +#define T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /*!< Hi */ +#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) /*!< Low */ +#define T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCMPx1 */ + +/** + * @defgroup T32A_OCRCMPx0 T32AxOUTA Control of T32AxRGx0 Counter Value + * @brief T32AxOUTA Control of T32AxRGx0 Counter Value OCRCMPx0 Macro Definition. + * @{ + */ +#define T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /*!< Hi */ +#define T32A_OCRCMPx0_CLR ((uint32_t)0x00000002) /*!< Low */ +#define T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCMPx0 */ + +/** + * @defgroup T32A_RGx0 T32A Timer Register x0 MASK + * @brief T32A Timer Register A0 MASK RGx0 Macro Definition. + * @{ + */ +#define T32A_RGx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RGx0 */ + +/** + * @defgroup T32A_RGx1 T32A Timer Register x1 MASK + * @brief T32A Timer Register A1 MASK RGx1 Macro Definition. + * @{ + */ +#define T32A_RGx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RGx0 */ + +/** + * @defgroup T32A_TMRx T32A Counter Capture Register x MASK + * @brief T32A Counter Capture Register x MASK TMRx Macro Definition. + * @{ + */ +#define T32A_TMRx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_TMRx */ + +/** + * @defgroup T32A_RELD T32A Counter Reload Register x MASK + * @brief T32A Counter Reload Register x MASK TMRx Macro Definition. + * @{ + */ +#define T32A_RELDx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RELD */ + +/** +* @defgroup T32A_CAPMx1 T32A Capture Control Register x1 +* @brief Capture Control Register A1 CAPMx1 Macro Definition. +* @{ +*/ +#define T32A_CAPMx1_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_CAPMx1_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ +#define T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020) /*!< INx0 rising edge */ +#define T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030) /*!< INx0 trailing edge */ +#define T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040) /*!< INx1 rising edge */ +#define T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050) /*!< INx1 trailing edge */ +#define T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060) /*!< other timer rising edge */ +#define T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) /*!< other timer trailing edge */ +/** + * @} + */ /* End of group T32A_CAPMx1 */ + +/** +* @defgroup T32A_CAPMx0 T32A Capture Control Register x0 +* @brief Capture Control Register x0 CAPMx0 Macro Definition. +* @{ +*/ +#define T32A_CAPMx0_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_CAPMx0_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ +#define T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002) /*!< INx0 rising edge */ +#define T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003) /*!< INx0 trailing edge */ +#define T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004) /*!< INx1 rising edge */ +#define T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005) /*!< INx1 trailing edge */ +#define T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006) /*!< other timer rising edge */ +#define T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) /*!< other timer trailing edge */ +/** + * @} + */ /* End of group T32A_CAPMx0 */ + +/** + * @defgroup T32A_CAPx0 T32A Capture Register x0 MASK + * @brief T32A Capture Register x0 MASK CAPx0 Macro Definition. + * @{ + */ +#define T32A_CAPx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_CAPx0 */ + +/** + * @defgroup T32A_CAPx1 T32A Capture Register x1 MASK + * @brief T32A Capture Register x1 MASK CAPx1 Macro Definition. + * @{ + */ +#define T32A_CAPx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_CAPx1 */ + +/** + * @defgroup T32A_IMSTERR T32A Statuserr Interrupt Request MASK + * @brief T32A Statuserr Interrupt Request MASK IMSTERR Macro Definition. + * @{ + */ +#define T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000) +#define T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010) +/** + * @} + */ /* End of group T32A_IMSTERR */ + +/** + * @defgroup T32A_IMUFx T32A Underflow Interrupt Request MASK + * @brief T32A Underflow Interrupt Request MASK IMUFx Macro Definition. + * @{ + */ +#define T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) /*!< request */ +/** + * @} + */ /* End of group T32A_IMUFx */ + +/** + * @defgroup T32A_IMOFx T32A Overflow Interrupt Request MASK + * @brief T32A Overflow Interrupt Request MASK IMOFx Macro Definition. + * @{ + */ +#define T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) /*!< request */ +/** + * @} + */ /* End of group T32A_IMOFx */ + +/** + * @defgroup T32A_IMx1 T32A Match Up T32AxRGx1 Interrupt Request MASK + * @brief T32A Match Up T32AxRGx1 Interrupt Request MASK IMx1 Macro Definition. + * @{ + */ +#define T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) /*!< request */ +/** + * @} + */ /* End of group T32A_IMx1 */ + +/** + * @defgroup T32A_IMx0 T32A Match Up T32AxRGx0 Interrupt Request MASK + * @brief T32A Match Up T32AxRGx0 Interrupt Request MASK IMx0 Macro Definition. + * @{ + */ +#define T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) /*!< request */ +/** + * @} + */ /* End of group T32A_IMx0 */ + +/** + * @defgroup T32A_INTSTERR T32A_Statuerr Flag Status + * @brief T32A Statuserr Flag Status INTSTERR Macro Definition. + * @{ + */ +#define T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010) +#define T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010) +/** + * @} + */ /* End of group T32A_INTSTERR */ + +/** + * @defgroup T32A_INTUFA T32A Underflow Flag Status + * @brief T32A Underflow Flag Status INTUFA Macro Definition. + * @{ + */ +#define T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008) /*!< Underflow Flag Mask */ +#define T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) /*!< Underflow Flag Clear */ +/** + * @} + */ /* End of group T32A_INTUFA */ + +/** + * @defgroup T32A_INTOFA T32A Overflow Flag Status + * @brief T32A Overflow Flag Status INTOFA Macro Definition. + * @{ + */ +#define T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004) /*!< Overflow Flag Mask */ +#define T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) /*!< Overflow Flag Clear */ +/** + * @} + */ /* End of group T32A_INTOFA */ + +/** + * @defgroup T32A_INTA1 T32A Match Up T32AxRGx1 Flag Status + * @brief T32A Match Up T32AxRGx1 Flag Status INTA1 Macro Definition. + * @{ + */ +#define T32A_INTx1_FLG_MASK ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Mask */ +#define T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Clear */ +/** + * @} + */ /* End of group T32A_INTA1 */ + +/** + * @defgroup T32A_INTA0 T32A Match Up T32AxRGx0 Flag Status + * @brief T32A Match Up T32AxRGx0 Flag Status INTA0 Macro Definition. + * @{ + */ +#define T32A_INTx0_FLG_MASK ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Mask */ +#define T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Clear */ +/** + * @} + */ /* End of group T32A_INTA0 */ + +/** + * @defgroup T32A_DMAENx2 T32A DMA Converter1 Request control + * @brief T32A DMA Converter1 Disable/Enable DMAENx2 Macro Definition. + * @{ + */ +#define T32A_DMAENx2_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx2 */ + +/** + * @defgroup T32A_DMAENx1 T32A DMA InputCapture1 Request control + * @brief T32A DMA InputCapture1 Disable/Enable DMAENx1 Macro Definition. + * @{ + */ +#define T32A_DMAENx1_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx1 */ + +/** + * @defgroup T32A_DMAENx0 T32A DMA InputCapture0 Request control + * @brief T32A DMA InputCapture0 Disable/Enable DMAENx0 Macro Definition. + * @{ + */ +#define T32A_DMAENx0_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx0 */ + +/** +* @defgroup T32A_PDN T32A Pulse Mode Count Down Control +* @brief Pulse Mode Count Down Control PDN Macro Definition. +* @{ +*/ +#define T32A_PDN_NON0 ((uint32_t)0x00000000) /*!< Do not count down */ +#define T32A_PDN_NON1 ((uint32_t)0x00001000) /*!< Do not count down */ +#define T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000) /*!< T32AxINC0 rising edge */ +#define T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000) /*!< T32AxINC0 trailing edge */ +#define T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000) /*!< T32AxINC1 rising edge */ +#define T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000) /*!< T32AxINC1 trailing edge */ +#define T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000) /*!< T32AxINC0 rising edge/trailing edge */ +#define T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) /*!< T32AxINC1 rising edge/trailing edge */ +/** + * @} + */ /* End of group T32A_PDN */ + +/** +* @defgroup T32A_PUP T32A Pulse Mode Count UP Control +* @brief Pulse Mode Count UP Control PUP Macro Definition. +* @{ +*/ +#define T32A_PUP_NON0 ((uint32_t)0x00000000) /*!< Do not count up */ +#define T32A_PUP_NON1 ((uint32_t)0x00000100) /*!< Do not count up */ +#define T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200) /*!< T32AxINC0 rising edge */ +#define T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300) /*!< T32AxINC0 trailing edge */ +#define T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400) /*!< T32AxINC1 rising edge */ +#define T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500) /*!< T32AxINC1 trailing edge */ +#define T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600) /*!< T32AxINC0 rising edge/trailing edge */ +#define T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) /*!< T32AxINC1 rising edge/trailing edge */ +/** + * @} + */ /* End of group T32A_PUP */ + +/** +* @defgroup T32A_NF T32A Noise Filter control +* @brief Noise Filter control NF Macro Definition. +* @{ +*/ +#define T32A_NF_NON ((uint32_t)0x00000000) /*!< Nothing */ +#define T32A_NF_2 ((uint32_t)0x00000010) /*!< Noise Filter less than 2/ PhiT0 */ +#define T32A_NF_4 ((uint32_t)0x00000020) /*!< Noise Filter less than 4/ PhiT0 */ +#define T32A_NF_8 ((uint32_t)0x00000030) /*!< Noise Filter less than 8/ PhiT0 */ +/** + * @} + */ /* End of group T32A_NF */ + +/** + * @defgroup T32A_PDIR T32A Phase 2 Pulse Direction control + * @brief Phase 2 Pulse Direction control PDIR Macro Definition. + * @{ + */ +#define T32A_PDIR_FORWARD ((uint32_t)0x00000000) /*!< forward */ +#define T32A_PDIR_BACKWARD ((uint32_t)0x00000002) /*!< backward */ +/** + * @} + */ /* End of group T32A_PDIR */ + +/** + * @defgroup T32A_PMODE T32A Pulse Count Mode control + * @brief Pulse Count Mode control PDIR Macro Definition. + * @{ + */ +#define T32A_PMODE_PHASE_2 ((uint32_t)0x00000000) /*!< Phase 2 Pulse Counter Mode */ +#define T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) /*!< Phase 1 Pulse Counter Mode */ +/** + * @} + */ /* End of group T32A_PMODE */ + +/** + * @} + */ /* End of group T32A_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup T32A_Exported_Typedef T32A Exported Typedef + * @{ + */ + +/** + * @enum t32_type_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_TIMERA = 0, /*!< 0: Timer A */ + T32A_TIMERB, /*!< 1: Timer B */ + T32A_TIMERC, /*!< 2: Timer C */ + T32A_TIMERMAX, +} t32_type_t; + +/** + * @enum t32_regnum_t + * @brief Use of Timer register number. + */ +typedef enum { + T32A_REG0 = 0, /*!< 0: Register 0 */ + T32A_REG1, /*!< 1: Register 1 */ + T32A_RELOAD, /*!< 2: Reload Register */ +} t32_regnum_t; +/** + * @enum t32_mode_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_MATCH = 0, /*!< 0: compare match detection 0 */ + T32A_OVERFLOW, /*!< 1: Overfloe detection */ + T32A_UNDERFLOW, /*!< 2: Underflow detection */ + T32A_CAPTURE0, /*!< 3: Capture 0 */ + T32A_CAPTURE1, /*!< 4: Capture 0 */ +} t32_mode_t; + +/** + * @enum t32_triger_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_INTRG = 0, /*!< 0: internal triger */ + T32A_TIM_RISING_EDGE, /*!< 1: Same Channel other timer rising edge */ + T32A_TIM_TRAILING_EDGE, /*!< 2: Same Channel other timer trailing edge */ + T32A_EXTTRG_RISING_EDGE, /*!< 3: external triger rising edge */ + T32A_EXTTRG_TRAILING_EDGE, /*!< 4: external triger trailing edge */ +} t32_triger_t; +/** + * @} + */ /* End of group T32A_Exported_Typedef */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Exported_Typedef T32A Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct t32a_mode_t + * @brief TimerA Mode Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t halt; /*!< T32A Debug HALT Control. + : Use @ref T32A_HALT */ + uint32_t mode; /*!< T32A 16bit/32bit MODE . + : Use @ref T32A_MODE32 */ +} t32a_mode_t; + +/*----------------------------------*/ +/** + * @struct t32a_runx_t + * @brief TimerA Run Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t runflg; /*!< TimerA Run Control Flag. + : Use @ref T32A_RUNFLGx */ + uint32_t sftstp; /*!< SW Counter STOP Control. + : Use @ref T32A_SFTSTPx */ + uint32_t sftsta; /*!< SW Counter START Control. + : Use @ref T32A_SFTSTAx */ + uint32_t run; /*!< TimerA Run Control. + : Use @ref T32A_RUNx */ +} t32a_runx_t; + +/*----------------------------------*/ +/** + * @struct t32a_crx_t + * @brief Counter Register Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t prscl; /*!< T32A PRESCALER Control. + : Use @ref T32A_PRSCLx */ + uint32_t clk; /*!< T32A COLCK Control. + : Use @ref T32A_CLKx */ + uint32_t wbf; /*!< T32A Double Buffer Disable/Enable Control. + : Use @ref T32A_WBFx */ + uint32_t updn; /*!< T32A Counter Up/Down Control. + : Use @ref T32A_UPDNx */ + uint32_t reld; /*!< T32A Counter Reload Control. + : Use @ref T32A_RELDx */ + uint32_t stop; /*!< T32A Counter Stop Control. + : Use @ref T32A_STOPx */ + uint32_t start; /*!< T32A Counter Start Controlc. + : Use @ref T32A_STARTx */ +} t32a_crx_t; + +/*----------------------------------*/ +/** + * @struct t32a_outcrx0_t + * @brief TimerA Output Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ocr; /*!< T32AxOUTA Control. + : Use @ref T32A_OCRx */ +} t32a_outcrx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_outcrx1_t + * @brief T32AxOUTA Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ocrcap1; /*!< T32AxOUTA Control of T32AxCAPx1 T32AxRGx1. + : Use @ref T32A_OCRCAPx1 */ + uint32_t ocrcap0; /*!< T32AxOUTA Control of T32AxCAPx0 T32AxRGx1. + : Use @ref T32A_OCRCAPx0 */ + uint32_t ocrcmp1; /*!< T32AxOUTA Control of T32AxRGx1 Counter Value + : Use @ref T32A_OCRCMPx1 */ + uint32_t ocrcmp0; /*!< T32AxOUTA Control of T32AxRGx0 Counter Value + : Use @ref T32A_OCRCMPx0 */ +} t32a_outcrx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_capcrx_t + * @brief Capture Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capmx1; /*!< T32A Capture Control Register x1. + : Use @ref T32A_CAPMx1 */ + uint32_t capmx0; /*!< T32A Capture Control Register A0. + : Use @ref T32A_CAPMx0 */ +} t32a_capcrx_t; + +/*----------------------------------*/ +/** + * @struct t32a_rgx0_t + * @brief T32A Timer Register x0 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t rgx0; /*!< T32A Timer Register x0. + : Use @ref T32A_RGx0 */ +} t32a_rgx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_rgx1_t + * @brief T32A Timer Register x1 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t rgx1; /*!< T32A Timer Register x1. + : Use @ref T32A_RGx1 */ +} t32a_rgx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_tmrx_t + * @brief T32A Counter Capture Register A Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tmrx; /*!< T32A Counter Capture Register x. + : Use @ref T32A_TMRx */ +} t32a_tmrx_t; + +/*----------------------------------*/ +/** + * @struct t32a_reldx_t + * @brief T32A Counter Reload Register Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t reld; /*!< T32A Counter Reload Register. + : Use @ref T32A_RELD */ +} t32a_reldx_t; + +/*----------------------------------*/ +/** + * @struct t32a_capx0_t + * @brief T32A Capture Register x0 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capx0; /*!< T32A Capture Register x0. + : Use @ref T32A_CAPx0 */ +} t32a_capx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_capx1_t + * @brief T32A Capture Register x0 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capx1; /*!< T32A Capture Register x1. + : Use @ref T32A_CAPx1 */ +} t32a_capx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_imx_t + * @brief Interrupt mask register Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t imsterr; /*!< T32A State Transition Err Interrupt Request MASK (Only use Timer C). + : Use @ref T32A_IMSTERR */ + uint32_t imuf; /*!< T32A Underflow Interrupt Request MASK. + : Use @ref T32A_IMUFx */ + uint32_t imof; /*!< T32A Underflow Interrupt Request MASK. + : Use @ref T32A_IMOFx */ + uint32_t imx1; /*!< T32A Match Up T32AxRGx1 Interrupt Request MASK. + : Use @ref T32A_IMx1 */ + uint32_t imx0; /*!< T32A Match Up T32AxRGx0 Interrupt Request MASK. + : Use @ref T32A_IMx0 */ +} t32a_imx_t; + +/*----------------------------------*/ +/** + * @struct t32a_stx_t + * @brief Status register structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intsterr; /*!< T32A State Transition Err Flag Status (Only use Timer C). + : Use @ref T32A_INTSTERR */ + uint32_t intuf; /*!< T32A Underflow Flag Status. + : Use @ref T32A_INTUFA */ + uint32_t intof; /*!< T32A Overflow Flag Status. + : Use @ref T32A_INTOFA */ + uint32_t intx1; /*!< T32A Match Up T32AxRGx1 Flag Status. + : Use @ref T32A_INTA1 */ + uint32_t intx0; /*!< T32A Match Up T32AxRGx0 Flag Status. + : Use @ref T32A_INTA0 */ +} t32a_stx_t; + +/*----------------------------------*/ +/** + * @struct t32a_dma_req_t + * @brief DMA Request register setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t dmaenx2; /*!< T32A DMA Converter1 Request control. + : Use @ref T32A_DMAENx2 */ + uint32_t dmaenx1; /*!< T32A DMA InputCapture1 Request control. + : Use @ref T32A_DMAENx1 */ + uint32_t dmaenx0; /*!< T32A DMA InputCapture0 Request control. + : Use @ref T32A_DMAENx0 */ +} t32a_dma_req_t; + +/*----------------------------------*/ +/** + * @struct t32a_pulse_cr_t + * @brief Pulse Count Control register setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t pdn; /*!< Pulse Mode Count Down Control. + : Use @ref T32A_PDN */ + uint32_t pup; /*!< Pulse Mode Count UP Control. + : Use @ref T32A_PUP */ + uint32_t nf; /*!< Noise Filter control. + : Use @ref T32A_NF */ + uint32_t pdir; /*!< Phase 2 Pulse Direction control. + : Use @ref T32A_PDIR */ + uint32_t pmode; /*!< Pulse Count Mode control. + : Use @ref T32A_PMODE */ +} t32a_pulse_cr_t; + +/** + * @struct t32a_initial_setting_t + * @brief Initial Timer setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + t32a_runx_t runx; /*!< Timer Run Control Setting */ + t32a_crx_t crx; /*!< Counter Register Control Setting */ + t32a_outcrx0_t outcrx0; /*!< Timer Output Control Setting */ + t32a_outcrx1_t outcrx1; /*!< T32AxOUTx Control Setting */ + t32a_capcrx_t capcrx; /*!< Capture Control Setting */ + t32a_rgx0_t rgx0; /*!< T32A Timer Register x0 Setting */ + t32a_rgx1_t rgx1; /*!< T32A Timer Register x1 Setting */ + t32a_tmrx_t tmrx; /*!< T32A Counter Capture Register Setting */ + t32a_reldx_t reldx; /*!< T32A Counter Reload Register Setting */ + t32a_capx0_t capx0; /*!< T32A Capture Register x0 Setting */ + t32a_capx1_t capx1; /*!< T32A Capture Register x1 Setting */ + t32a_imx_t imx; /*!< Interrupt mask register Setting */ + t32a_dma_req_t dma_req; /*!< DMA Request register Setting */ + t32a_pulse_cr_t pls_cr; /*!< Pulse Count Control Register Setting (Only use Timer C) */ + void (*handler_T)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Event handler. */ + void (*handler_TC0)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap0 Event handler. */ + void (*handler_TC1)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap1 Event handler. */ +} t32a_initial_setting_t; + +/** + * @struct t32a_initial_mode_t + * @brief Initial Mode setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + t32a_mode_t mode; /*!< Timer Mode Setting */ +} t32a_initial_mode_t; + + +/*----------------------------------*/ +/** + * @brief T32A handle structure definition. +*/ +/*----------------------------------*/ +typedef struct t32a_handle { + TSB_T32A_TypeDef *p_instance; /*!< Registers base address. */ + t32a_initial_mode_t init_mode; /*!< Timer Mode Initial Setting */ + t32a_initial_setting_t init[T32A_TIMERMAX]; /*!< Initial setting. */ +} t32a_t; + +/** @} */ +/* End of group T32A_Exported_Types */ +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Exported_functions T32A Exported Functions + * @{ + */ +TXZ_Result t32a_mode_init(t32a_t *p_obj); +TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value); +TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val); +TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type); +void t32a_timer_IRQHandler(t32a_t *p_obj); +void t32a_timer_cap0_IRQHandler(t32a_t *p_obj); +void t32a_timer_cap1_IRQHandler(t32a_t *p_obj); +TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl); +/** + * @} + */ /* End of group T32A_Exported_functions */ + +/** + * @} + */ /* End of group T32A */ + +/** + * @} + */ /* End of group Periph_Driver */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __T32A_H */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_tspi.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_tspi.h new file mode 100644 index 00000000000..1f05751fe87 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_tspi.h @@ -0,0 +1,1378 @@ +/** + ******************************************************************************* + * @file txz_tspi.h + * @brief This file provides all the functions prototypes for TSPI driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __TSPI_H +#define __TSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup TSPI TSPI + * @brief TSPI Driver. + * @{ + */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_define TSPI Exported Define + * @{ + */ +/** + * @defgroup TSPI_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define TSPI_NULL ((void *)0) +/** + * @} + */ /* End of group TSPI_NullPointer */ + +/** + * @defgroup TSPI_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group TSPI_ParameterResult */ + + +/** + * @defgroup TSPI_Result Result + * @brief TSPI Result Macro Definition. + * @{ + */ +#define TSPI_RESULT_SUCCESS (0) /*!< Success */ +#define TSPI_RESULT_FAILURE (-1) /*!< Failure */ +/** + * @} + */ /* End of group TSPI_Result */ + +/** + * @defgroup TSPI_SW_Reset SW Reset + * @brief Software Rest Macro Definition. + * @{ + */ +#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattern 10 */ +#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattern 01 */ +/** + * @} + */ /* End of group TSPI_SW_Reset */ + + +/** + * @defgroup TSPI_Enable TSPI Enable/Disable Control + * @brief Enable/Disable TSPIE Macro Definition. + * @{ + */ +#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Enable */ + +/** + * @defgroup TSPI_Infinity_Control Frame infinity Control + * @brief Frame infinity Enable/Disable Macro Definition. + * @{ + */ +#define TSPI_INF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_INF_ENABLE ((uint32_t)0x00010000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Infinity_Control */ + +/** + * @defgroup TSPI_Trigger_Control Trigger Control + * @brief Enable/Disable TRGEN Macro Definition. + * @{ + */ +#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Control Transmission Control + * @brief Enable/Disable TRXE Macro Definition. + * @{ + */ +#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */ +#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Mode Transmission Mode + * @brief TSPIIMS Mode Macro Definition. + * @{ + */ +#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */ +#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */ +/** + * @} + */ /* End of group TSPI_Transmission_Mode */ + + +/** + * @defgroup TSPI_Operation_Select Operation Select + * @brief Master/Slave MSTR Operation Macro Definition. + * @{ + */ +#define TSPI_MASTER_OPERATION ((uint32_t)0x00001000) /*!< MASTER MODE */ +#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */ +/** + * @} + */ /* End of group TSPI_Operation_Select */ + + +/** + * @defgroup TSPI_Transfer_Mode Transfer Mode + * @brief Transfer Mode TMMD Macro Definition. + * @{ + */ +#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */ +#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */ +#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */ +#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */ +/** + * @} + */ /* End of group TSPI_Transfer_Mode */ + + +/** + * @defgroup TSPI_CSSEL_Select CSSEL Select + * @brief TSPIIxCS0/1/2/3 Select Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */ +#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */ +#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */ +#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */ +/** + * @} + */ /* End of group TSPI_CSSEL_Select */ + +/** + * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range + * @brief Transfer Frame Range Macro Definition. + * @{ + */ +#define TSPI_TRANS_RANGE_CONTINUE ((uint32_t)0x00000000) /*!< Continue Transfer Frame :0 */ +#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000001) /*!< Single Transfer Frame :1 */ +#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */ +/** + * @} + */ /* End of group TSPI_Transfer_Frame_Range */ +/** + * @defgroup TSPI_IDLE_Output_value IDLE Output Value + * @brief IDLE time Output Value TIDLE Macro Definition. + * @{ + */ +#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */ +#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */ +#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */ +#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_IDLE_Output_value */ + +/** + * @defgroup TSPI_RXDLY_value RXDLY Value + * @brief IDLE time Output Value TIDLE Macro Definition. + * @{ + */ +#define TSPI_RXDLY_1CLK ((uint32_t)0x00000000) /*!< RXDLY 1CLK */ +#define TSPI_RXDLY_2CLK ((uint32_t)0x00010000) /*!< RXDLY 2CLK */ +#define TSPI_RXDLY_3CLK ((uint32_t)0x00020000) /*!< RXDLY 3CLK */ +#define TSPI_RXDLY_4CLK ((uint32_t)0x00030000) /*!< RXDLY 4CLK */ +#define TSPI_RXDLY_5CLK ((uint32_t)0x00040000) /*!< RXDLY 5CLK */ +#define TSPI_RXDLY_6CLK ((uint32_t)0x00050000) /*!< RXDLY 6CLK */ +#define TSPI_RXDLY_7CLK ((uint32_t)0x00060000) /*!< RXDLY 7CLK */ +#define TSPI_RXDLY_8CLK ((uint32_t)0x00070000) /*!< RXDLY 8CLK */ +/** + * @} + */ /* End of group TSPI_RXDLY_value*/ + + +/** +* @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value +* @brief In case of Under Run Output Value TXDEMP Macro Definition. +* @{ +*/ +#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */ +#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_Underrun_Output_value */ + + +/** + * @defgroup TSPI_TxFillLevel Tx Fill Level + * @brief Transmit Fill Level Macro Definition. + * @{ + */ +#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */ +#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */ +#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */ +#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */ +#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */ +#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */ +#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */ +#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */ +/*! + * @} + */ /* End of group TSPI_TxFillLevel */ + + +/** + * @defgroup TSPI_RxFillLevel Rx Fill Level + * @brief Receive Fill Level Macro Definition. + * @{ + */ +#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */ +#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */ +#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */ +#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */ +#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */ +#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */ +#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */ +#define TSPI_RX_FILL_LEVEL_8 ((uint32_t)0x00000800) /*!< 8 */ +#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000F00) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_RxFillLevel */ + + +/** + * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrupt + * @brief Enable/Disable Transmit FIFO Interrupt Macro Definition. + * @{ + */ +#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterrupt */ + + +/** + * @defgroup TSPI_TxInterrupt Tx Interrupt + * @brief Enable/Disable Transmit Interrupt Macro Definition. + * @{ + */ +#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxInterrupt */ + + +/** + * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrupt + * @brief Enable/Disable Receive FIFO Interrupt Macro Definition. + * @{ + */ +#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterrupt */ + + +/** + * @defgroup TSPI_RxInterrupt Rx Interrupt + * @brief Enable/Disable Receive Interrupt Macro Definition. + * @{ + */ +#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxInterrupt */ + + +/** + * @defgroup TSPI_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ErrorInterrupt */ + + +/** + * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt + * @brief Enable/Disable Transmit DMA Interrupt Macro Definition. + * @{ + */ +#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */ +#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxDMAInterrupt */ + + +/** + * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt + * @brief Enable/Disable Receive DMA Interrupt Macro Definition. + * @{ + */ +#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */ +#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxDMAInterrupt */ + + +/** + * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear + * @brief Tx Buffer Clear Macro Definition. + * @{ + */ +#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Tx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear + * @brief Rx Buffer Clear Macro Definition. + * @{ + */ +#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Rx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock + * @brief Baudrate Input Clock Macro Definition. + * @{ + */ +#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */ +#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */ +#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */ +#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */ +#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */ +#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */ +#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */ +#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */ +#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */ +#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Clock */ + + +/** + * @defgroup TSPI_Baudrate_Divider Baudrate Divider + * @brief Baudrate IDivider Macro Definition. + * @{ + */ +#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */ +#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */ +#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */ +#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */ +#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */ +#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */ +#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */ +#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */ +#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */ +#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */ +#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */ +#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */ +#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */ +#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */ +#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */ +#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Divider */ + + +/** + * @defgroup TSPI_DataDirection Data Direction + * @brief Data Direction Macro Definition. + * @{ + */ +#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */ +/*! + * @} + */ /* End of group TSPI_DataDirection */ + + +/** + * @defgroup TSPI_DataLength Data Length + * @brief Data Length Macro Definition. + * @{ + */ +#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */ +#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */ +#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */ +#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */ +#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */ +#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */ +#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */ +#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */ +#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */ +#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */ +#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */ +#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */ +#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */ +#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */ +#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */ +#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */ +#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */ +#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */ +#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */ +#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */ +#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */ +#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */ +#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */ +#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */ +#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */ +#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */ +/** + * @} + */ /* End of group TSPI_DataLength */ + + +/** + * @defgroup TSPI_Frame_Interval_Time Frame Interval time + * @brief Frame Interval time Macro Definition. + * @{ + */ +#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Frame_Interval_Time */ + + +/** + * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity + * @brief TSPIxCS3 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS3_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity + * @brief TSPIxCS2 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS2_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity + * @brief TSPIxCS1 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS1_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity + * @brief TSPIxCS0 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS0_Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity + * @brief Serial Clock Polarity Macro Definition. + * @{ + */ +#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */ +#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */ +/** + * @} + */ /* End of group Serial Clock Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity + * @brief Serial Clock IDLE Polarity Macro Definition. + * @{ + */ +#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */ +#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */ + + +/** + * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time + * @brief Minimum IDLE Time Macro Definition. + * @{ + */ +#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Minimum_IDLE_Time */ + + +/** + * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay + * @brief Serial Clock Delay Macro Definition. + * @{ + */ +#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_Delay */ + + +/** + * @defgroup TSPI_Negate_Delay Negate Delay + * @brief Negate Delay Macro Definition. + * @{ + */ +#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */ +#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */ +#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */ +#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */ +#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */ +#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */ +#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */ +#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */ +#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */ +#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */ +#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */ +#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */ +#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */ +#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */ +#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Negate_Delay */ + + +/** + * @defgroup TSPI_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definition. + * @{ + */ +#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ParityEnable */ + + +/** + * @defgroup TSPI_ParityBit Parity Bit + * @brief Parity Bit Macro Definition. + * @{ + */ +#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */ +/** + * @} + */ /* End of group TSPI_ParityBit */ + + +/** + * @defgroup TSPI_SECT_MODE Sect mode setting + * @brief Sect mode Macro Definition. + * @{ + */ +#define TSPI_SECT_MODE_FRAME ((uint32_t)0x00000000) /*!< Frame Mode */ +#define TSPI_SECT_MODE_SECT ((uint32_t)0x00000001) /*!< Sect Mode */ +/** + * @} + */ /* End of group TSPI_SECT_MODE */ + + +/** + * @defgroup TSPI_SECT_VALUE Sect bit length setting + * @brief Sect bit length Macro Definition. + * @{ + */ +#define TSPI_SECT_VALUE_0 ((uint32_t)0x00000000) /*!< length:0 */ +#define TSPI_SECT_VALUE_1 ((uint32_t)0x00000001) /*!< length:1 */ +#define TSPI_SECT_VALUE_MAX ((uint32_t)0x00000020) /*!< MAX:32 */ +/** + * @} + */ /* End of group TSPI_SECT_VALUE */ + +/** + * @defgroup TSPI_Status_Setting_flag Status Setting Flag + * @brief Enable/Disable Status Setting Flag Macro Definition. + * @{ + */ +#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group TSPI_Status_Setting_flag */ + + +/** + * @defgroup TSPI_TxState Transmitting State Flag + * @brief Transmitting State Flag Macro Definition. + * @{ + */ +#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */ +#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_TxState */ + + +/** + * @defgroup TSPI_TxDone Transmitting Complete Flag + * @brief Transmitting Complete Flag Macro Definition. + * @{ + */ +#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */ +#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */ +#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxDone */ + + +/** + * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrupt Flag + * @brief Transmitting FIFO Interrupt Flag Macro Definition. + * @{ + */ +#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */ +#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag + * @brief Transmitting FIFO Empty Flag Macro Definition. + * @{ + */ +#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_TxFIFOEmptyFlag */ + +/** + * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level + * @brief Current Transmitting FIFO Level Macro Definition. + * @{ + */ +#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */ +#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */ +#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */ +#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */ +#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */ +#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */ +#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */ +#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_TxReachFillLevel */ + + +/** + * @defgroup TSPI_RxState Receive State Flag + * @brief Receive State Flag Macro Definition. + * @{ + */ +#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */ +#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_RxState */ + + +/** + * @defgroup TSPI_RxDone Receive Complete Flag + * @brief Receive Complete Flag Macro Definition. + * @{ + */ +#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */ +#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */ +#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxDone */ + + +/** + * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrupt Flag + * @brief Rx FIFO Interrupt Flag Macro Definition. + * @{ + */ +#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */ +#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag + * @brief Receiving FIFO Full Flag Macro Definition. + * @{ + */ +#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_RxFIFOFullFlag */ + + +/** + * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level + * @brief Current Receive FIFO Level Macro Definition. + * @{ + */ +#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */ +#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */ +#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */ +#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */ +#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */ +#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */ +#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */ +#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_RxReachFillLevel */ + + +/** + * @defgroup TSPI_TRGErr Trigger Error + * @brief Trigger Error Macro Definition. + * @{ + */ +#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */ +#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_TRGErr */ + +/** + * @defgroup TSPI_UnderrunErr Underrun Error + * @brief Underrun Error Macro Definition. + * @{ + */ +#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */ +#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_UnderrunErr */ + +/** + * @defgroup TSPI_OverrunErr Overrun Error + * @brief Overrun Error Macro Definition. + * @{ + */ +#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */ +#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_OverrunErr */ + + +/** + * @defgroup TSPI_ParityErr Parity Error + * @brief Parity Error Macro Definition. + * @{ + */ +#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */ +#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_ParityErr */ + +/** +* @defgroup TSPI_Data_allign Data allign +* @brief Data allign Macro Definition. +* @{ +*/ +#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */ +#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */ +#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */ +/** + * @} + */ /* End of group TSPI_Data_allign */ + +/** +* @defgroup TSPI_FifoMax FIFO MAX +* @brief FIFO MAX LEVEL +* @{ +*/ +#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */ +/** + * @} + */ /* End of group TSPI_FifoMax */ + +/** +* @defgroup TSPI_ErrCode Error Code +* @brief Error Code Macro Definition. +* @{ +*/ +#define NOERROR ((uint32_t)0x00000000) /*!< no error */ +#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */ +#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */ +#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */ +#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */ +#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */ +#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */ +#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */ +#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */ +#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */ +#define INITERR ((uint32_t)0x000000) /*!< transmit mode error */ +/** +* @} + */ /* End of group TSPI_ErrCode */ + +/** +* @defgroup TSPI_Buffer_Size Receive Buffer size +* @brief Error Code Macro Definition. +* @{ +*/ +#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */ +/** +* @} + */ /* End of group TSPI_Buffer_Size */ +/** + * @} + */ /* End of group TSPI_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/* No define */ +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct tspi_receive8_t + * @brief Receive event information structure definition. + * @brief When data length definition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive8_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive16_t + * @brief Receive event information structure definition. + * @brief When data length definition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive16_t; + +/** + * @struct tspi_receive32_t + * @brief Receive event information structure definition. + * @brief When data length definition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive32_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive_t + * @brief Receive event information structure definition. +*/ +/*----------------------------------*/ +typedef union { + tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */ + tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */ + tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */ +} tspi_receive_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit8_t + * @brief Transmit data information structure definition. + * @brief When data length definition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit8_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit16_t + * @brief Transmit data information structure definition. + * @brief When data length definition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit16_t; +/*----------------------------------*/ +/** + * @struct tspi_transmit32_t + * @brief Transmit data information structure definition. + * @brief When data length definition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit32_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit_t + * @brief Transmit data information structure definition. +*/ +/*----------------------------------*/ +typedef union { + tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */ + tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */ + tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */ +} tspi_transmit_t; + +/*----------------------------------*/ +/** + * @struct tspi_control1_t + * @brief Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inf; /*!< INF Transmission Infinity Control. + : Use @ref TSPI_Infinity_Control */ + uint32_t trgen; /*!< TRGEN Transmission Trigger Control. + : Use @ref TSPI_Trigger_Control */ + uint32_t trxe; /*!< TRXE Transmission Control. + : Use @ref TSPI_Transmission_Control */ + uint32_t tspims; /*!< TSPI/SIO Transmission Mode. + : Use @ref TSPI_Transmission_Mode */ + uint32_t mstr; /*!< Master/Slave Operation Select. + : Use @ref TSPI_Operation_Select */ + uint32_t tmmd; /*!< Transfer Mode Select. + : Use @ref TSPI_Transfer_Mode */ + uint32_t cssel; /*!< CSSEL Select. + : Use @ref TSPI_CSSEL_Select */ + uint32_t fc; /*!< Transfer Frame Value. + : Range ( TSPI_TRANS_RANGE_CONTINUE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */ +} tspi_control1_t; + +/*----------------------------------*/ +/** + * @struct tspi_control2_t + * @brief Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tidle; /*!< IDLE Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t txdemp; /*!< Under Run Occur Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t rxdly; /*!< Fsys Select. + : Use @ref TSPI_RXDLY_value */ + uint32_t til; /*!< Transmit Fill Level. + : Use @ref TSPI_TxFillLevel */ + uint32_t ril; /*!< Receive Fill Level. + : Use @ref TSPI_RxFillLevel */ + uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt. + : Use @ref TSPI_TxFIFOInterrupt */ + uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt. + : Use @ref TSPI_TxInterrupt */ + uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt. + : Use @ref TSPI_RxFIFOInterrupt */ + uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt. + : Use @ref TSPI_RxInterrupt */ + uint32_t interr; /*!< Enable/Disable Error Interrupt. + : Use @ref TSPI_ErrorInterrupt */ + uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt. + : Use @ref TSPI_TxDMAInterrupt */ + uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt. + : Use @ref TSPI_RxDMAInterrupt */ +} tspi_control2_t; + +/*----------------------------------*/ +/** + * @struct tspi_control3_t + * @brief Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tfempclr; /*!< Transmit Buffer Clear. + : Use @ref TSPI_Tx_Buffer_Clear */ + uint32_t rffllclr; /*!< Receive Buffer Clear. + : Use @ref TSPI_Rx_Buffer_Clear */ +} tspi_control3_t; + +/*----------------------------------*/ +/** + * @struct tspi_baudrate_t + * @brief Clock setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t brck; /*!< Baudrate Input Clock. + : Use @ref TSPI_Baudrate_Clock */ + uint32_t brs; /*!< Baudrate Divider. + : Use @ref TSPI_Baudrate_Divider */ +} tspi_baudrate_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr0_t + * @brief Format control0. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t dir; /*!< Data Direction. + : Use @ref TSPI_DataDirection */ + uint32_t fl; /*!< Data Length. + : Use @ref TSPI_DataLength */ + uint32_t fint; /*!< Frame Interval time. + : Use @ref TSPI_Frame_Interval_Time */ + uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS3_Polarity */ + uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS2_Polarity */ + uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS1_Polarity */ + uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS0_Polarity */ + uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge. + : Use @ref TSPI_Serial_Clock_Polarity */ + uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low. + : Use @ref TSPI_Serial_Clock_IDLE_Polarity */ + uint32_t csint; /*!< Minimum IDLE Time. + : Use @ref TSPI_Minimum_IDLE_Time */ + uint32_t cssckdl; /*!< Serial Clock Delay. + : Use @ref TSPI_Serial_Clock_Delay */ + uint32_t sckcsdl; /*!< Negate Delay. + : Use @ref TSPI_Negate_Delay */ +} tspi_fmtr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr1_t + * @brief Format control1. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t reserved; /*!< SIO Slave Mode. + : */ + uint32_t vpe; /*!< Enable/Disable Parity Function. + : Use @ref TSPI_ParityEnable */ + uint32_t vpm; /*!< Odd/Even Parity Bit. + : Use @ref TSPI_ParityBit */ +} tspi_fmtr1_t; + +/*----------------------------------*/ +/** + * @struct tspi_sectcr0_t + * @brief Sect control0. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sect; /*!< Sect mode settings. + : Use @ref TSPI_SECT_MODE */ +} tspi_sectcr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_sectcr1_t + * @brief Sect control1. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sectl3; /*!< SECTL3 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ + uint32_t sectl2; /*!< SECTL2 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ + uint32_t sectl1; /*!< SECTL1 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ + uint32_t sectl0; /*!< SECTL0 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ +} tspi_sectcr1_t; + +/*----------------------------------*/ +/** + * @struct tspi_status_t + * @brief Status register. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tspisue; /*!< Enable/Disable Status Setting Flag. + : Use @ref TSPI_Status_Setting_flag */ + uint32_t txrun; /*!< Stop/Active Tx Active Flag. + : Use @ref TSPI_TxState */ + uint32_t txend; /*!< Tx Data Send Complete Flag. + : Use @ref TSPI_TxDone */ + uint32_t inttxwf; /*!< Tx FIFO Interrupt Flag. + : Use @ref TSPI_TxFIFOInterruptFlag */ + uint32_t tfemp; /*!< Tx FIFO Empty Flag. + : Use @ref TSPI_TxFIFOEmptyFlag */ + uint32_t tlvll; /*!< Tx Reach Fill Level + : Use @ref TSPI_TxReachFillLevel */ + uint32_t rxrun; /*!< Stop/Active Rx Active Flag. + : Use @ref TSPI_RxState */ + uint32_t rxend; /*!< Rx Data Receive Complete Flag. + : Use @ref TSPI_RxDone */ + uint32_t intrxff; /*!< Rx FIFO Interrupt Flag + : Use @ref TSPI_RxFIFOInterruptFlag */ + uint32_t rffll; /*!< Rx FIFO Full Flag + : Use @ref TSPI_RxFIFOFullFlag */ + uint32_t rlvl; /*!< Rx Reach Fill Level + : Use @ref TSPI_RxReachFillLevel */ +} tspi_status_t; + +/*----------------------------------*/ +/** + * @struct tspi_error_t + * @brief Error flag. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t udrerr; /*!< Underrun Error. + : Use @ref TSPI_UnderrunErr */ + uint32_t ovrerr; /*!< Overrun Error. + : Use @ref TSPI_OverrunErr */ + uint32_t perr; /*!< Parity Error. + : Use @ref TSPI_ParityErr */ +} tspi_error_t; + + +/*----------------------------------*/ +/** + * @struct tspi_initial_setting_t + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + tspi_control1_t cnt1; /*!< Control1 setting. + : Use @ref tspi_control1_t */ + tspi_control2_t cnt2; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_control3_t cnt3; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_baudrate_t brd; /*!< Baudrate setting. + : Use @ref tspi_baudrate_t */ + tspi_fmtr0_t fmr0; /*!< Format control0 setting. + : Use @ref tspi_fmtr0_t */ + tspi_fmtr1_t fmr1; /*!< Format control1 setting. + : Use @ref tspi_fmtr1_t */ + tspi_sectcr0_t scr0; /*!< Sect control0 setting. + : Use @ref tspi_sectcr0_t */ + tspi_sectcr1_t scr1; /*!< Sect control1 setting. + : Use @ref tspi_sectcr1_t */ +} tspi_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief TSPI handle structure definition. +*/ +/*----------------------------------*/ +typedef struct tspi_handle { + TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */ + tspi_initial_setting_t init; /*!< Initial setting. */ + uint32_t errcode; /*!< ErrorCode */ + /*------------------------------------------*/ + /*! + @brief Transmit Information. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmitted data. */ + tspi_transmit_t info; /*!< Transmit Data Information. */ + uint8_t tx_allign; /*!< Transmit Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Information. + */ + /*------------------------------------------*/ + struct { + tspi_receive_t info; /*!< Receive Data Information. */ + uint8_t rx_allign; /*!< Receive Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} tspi_t; +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_functions TSPI Exported Functions + * @{ + */ +TXZ_Result tspi_init(tspi_t *p_obj); +TXZ_Result tspi_deinit(tspi_t *p_obj); +TXZ_Result tspi_format(tspi_t *p_obj); +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info); +TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); +TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info); +void tspi_irq_handler_transmit(tspi_t *p_obj); +void tspi_irq_handler_receive(tspi_t *p_obj); +void tspi_error_irq_handler(tspi_t *p_obj); +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status); +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error); +TXZ_Result tspi_error_clear(tspi_t *p_obj); +TXZ_Result tspi_discard_transmit(tspi_t *p_obj); +TXZ_Result tspi_discard_receive(tspi_t *p_obj); +/** + * @} + */ /* End of group TSPI_Exported_functions */ +/** + * @} + */ /* End of group TSPI */ +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TSPI_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart.h new file mode 100644 index 00000000000..2a0663a2f70 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart.h @@ -0,0 +1,797 @@ +/** + ******************************************************************************* + * @file txz_uart.h + * @brief This file provides all the functions prototypes for UART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __UART_H +#define __UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup UART UART + * @brief UART Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_define UART Exported Define + * @{ + */ + +/** + * @defgroup UART_FifoMax Max Num of FIFO + * @brief Max Num of Tx/Rx Fifo. + * @{ + */ +#define UART_TX_FIFO_MAX ((uint32_t)0x00000008) /*!< TX FIFO Max. */ +#define UART_RX_FIFO_MAX ((uint32_t)0x00000008) /*!< RX FIFO Max. */ +/** + * @} + */ /* End of group UART_FifoMax */ + +/** + * @defgroup UART_HalfClockSelect Half Clock Select + * @brief Output Terminal Select + * @{ + */ +#define UART_HALF_CLOCK_UTxTXDA ((uint32_t)0x00000000) /*!< Half Clock output terminal select UTxTXDA. */ +#define UART_HALF_CLOCK_UTxTXDB ((uint32_t)0x00040000) /*!< Half Clock output terminal select UTxTXDB. */ +/** + * @} + */ /* End of group UART_HalfClockSelect */ + +/** + * @defgroup UART_HalfClockMode Half Clock Mode + * @brief Half Clock Mode Setting. + * @{ + */ +#define UART_HALF_CLOCK_MODE_1 ((uint32_t)0x00000000) /*!< Half Clock 1 terminal Mode. */ +#define UART_HALF_CLOCK_MODE_2 ((uint32_t)0x00020000) /*!< Half Clock 2 terminal Mode. */ +/** + * @} + */ /* End of group UART_HalfClockMode */ + +/** + * @defgroup UART_HalfClockCTR Half Clock Mode Control + * @brief Half Clock Control. + * @{ + */ +#define UART_HALF_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< Half Clock Mode Disable. */ +#define UART_HALF_CLOCK_ENABLE ((uint32_t)0x00010000) /*!< Half Clock Mode Enable. */ +/** + * @} + */ /* End of group UART_HalfClockCTR */ + +/** + * @defgroup UART_LoopBack Loop Back Function + * @brief Half Clock Control. + * @{ + */ +#define UART_LOOPBACK_DISABLE ((uint32_t)0x00000000) /*!< Loop Back Function Disable. */ +#define UART_LOOPBACK_ENABLE ((uint32_t)0x00008000) /*!< Loop Back Function Enable. */ +/** + * @} + */ /* End of group UART_LoopBack */ + + +/** + * @defgroup UART_NoiseFilter Noise Filter + * @brief Noise Filter Setting. + * @{ + */ +#define UART_NOISE_FILTER_NON ((uint32_t)0x00000000) /*!< No Filetering. */ +#define UART_NOISE_FILTER_2_T0 ((uint32_t)0x00001000) /*!< A signal below the 2/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_4_T0 ((uint32_t)0x00002000) /*!< A signal below the 4/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_8_T0 ((uint32_t)0x00003000) /*!< A signal below the 8/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_2_CLOCK ((uint32_t)0x00004000) /*!< A signal below the 2/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_3_CLOCK ((uint32_t)0x00005000) /*!< A signal below the 3/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_4_CLOCK ((uint32_t)0x00006000) /*!< A signal below the 4/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_5_CLOCK ((uint32_t)0x00007000) /*!< A signal below the 5/Clock is filtering as noise */ +/** + * @} + */ /* End of group UART_NoiseFilter */ + + +/** + * @defgroup UART_CTSHandshake CTS Handshake + * @brief Available CTS Handshake Macro Definition. + * @{ + */ +#define UART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_CTS_ENABLE ((uint32_t)0x00000400) /*!< Available. */ +/** + * @} + */ /* End of group UART_CTSHandshake */ + + +/** + * @defgroup UART_RTSHandshake RTS Handshake + * @brief Available RTS Handshake Macro Definition. + * @{ + */ +#define UART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RTS_ENABLE ((uint32_t)0x00000200) /*!< Available. */ +/** + * @} + */ /* End of group UART_RTSHandshake */ + + +/** + * @defgroup UART_DataComplementation Data Complementation + * @brief Enable/Disable Data Signal Complementation Macro Definition. + * @{ + */ +#define UART_DATA_COMPLEMENTION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_DATA_COMPLEMENTION_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group UART_DataComplementation */ + + +/** + * @defgroup UART_DataDirection Data Direction + * @brief Data Direction Macro Definition. + * @{ + */ +#define UART_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define UART_DATA_DIRECTION_MSB ((uint32_t)0x00000020) /*!< MSB first */ +/*! + * @} + */ /* End of group UART_DataDirection */ + + +/** + * @defgroup UART_StopBit Stop Bit + * @brief Stop Bit Macro Definition. + * @{ + */ +#define UART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ +#define UART_STOP_BIT_2 ((uint32_t)0x00000010) /*!< 2 bit */ +/** + * @} + */ /* End of group UART_StopBit */ + + +/** + * @defgroup UART_ParityBit Parity Bit + * @brief Parity Bit Macro Definition. + * @{ + */ +#define UART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define UART_PARITY_BIT_EVEN ((uint32_t)0x00000008) /*!< Even Parity */ +/** + * @} + */ /* End of group UART_ParityBit */ + + +/** + * @defgroup UART_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definition. + * @{ + */ +#define UART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_PARITY_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group UART_ParityEnable */ + + +/** + * @defgroup UART_DataLength Data Length + * @brief Data Length Macro Definition. + * @{ + */ +#define UART_DATA_LENGTH_7 ((uint32_t)0x00000000) /*!< 7 bit */ +#define UART_DATA_LENGTH_8 ((uint32_t)0x00000001) /*!< 8 bit */ +#define UART_DATA_LENGTH_9 ((uint32_t)0x00000002) /*!< 9 bit */ +/** + * @} + */ /* End of group UART_DataLength */ + + +/** + * @defgroup UART_TxFillLevelRange Tx Fill Level Range + * @brief Transmit Fill Level Range Macro Definition. + * @brief Range of Value be set "(UART_TX_FILL_LEVEL_MIN <= Value <= UART_TX_FILL_LEVEL_MAX)". + * @{ + */ +#define UART_TX_FILL_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :1 */ +#define UART_TX_FILL_RANGE_MAX ((uint32_t)0x00000007) /*!< Maximum Value :7 */ +/*! + * @} + */ /* End of group UART_TxFillLevelRange */ + + +/** + * @defgroup UART_RxFillLevelRange Rx Fill Level Range + * @brief Receive Fill Level Range Macro Definition. + * @brief Range of Value be set "(UART_RX_FILL_LEVEL_MIN <= Value <= UART_RX_FILL_LEVEL_MAX)". + * @{ + */ +#define UART_RX_FILL_RANGE_MIN ((uint32_t)0x00000001) /*!< Minimum Value :1 */ +#define UART_RX_FILL_RANGE_MAX ((uint32_t)0x00000008) /*!< Maximum Value :8 */ +/** + * @} + */ /* End of group UART_RxFillLevelRange */ + + +/** + * @defgroup UART_TxFIFOInterrupt Tx FIFO Interrupt + * @brief Available Transmit FIFO Interrupt Macro Definition. + * @{ + */ +#define UART_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Available. */ +/** + * @} + */ /* End of group UART_TxFIFOInterrupt */ + + +/** + * @defgroup UART_TxInterrupt Tx Interrupt + * @brief Available Transmit Interrupt Macro Definition. + * @{ + */ +#define UART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Available. */ +/** + * @} + */ /* End of group UART_TxInterrupt */ + + +/** + * @defgroup UART_RxFIFOInterrupt Rx FIFO Interrupt + * @brief Available Receive FIFO Interrupt Macro Definition. + * @{ + */ +#define UART_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ +/** + * @} + */ /* End of group UART_RxFIFOInterrupt */ + + +/** + * @defgroup UART_RxInterrupt Rx Interrupt + * @brief Available Receive Interrupt Macro Definition. + * @{ + */ +#define UART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ +/** + * @} + */ /* End of group UART_RxInterrupt */ + + +/** + * @defgroup UART_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define UART_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group UART_ErrorInterrupt */ + + +/** + * @defgroup UART_Prescaler Prescaler + * @brief Prescaler Macro Definition. + * @{ + */ +#define UART_PLESCALER_1 ((uint32_t)0x00000000) /*!< 1/1 */ +#define UART_PLESCALER_2 ((uint32_t)0x00000010) /*!< 1/2 */ +#define UART_PLESCALER_4 ((uint32_t)0x00000020) /*!< 1/4 */ +#define UART_PLESCALER_8 ((uint32_t)0x00000030) /*!< 1/8 */ +#define UART_PLESCALER_16 ((uint32_t)0x00000040) /*!< 1/16 */ +#define UART_PLESCALER_32 ((uint32_t)0x00000050) /*!< 1/32 */ +#define UART_PLESCALER_64 ((uint32_t)0x00000060) /*!< 1/64 */ +#define UART_PLESCALER_128 ((uint32_t)0x00000070) /*!< 1/128 */ +#define UART_PLESCALER_256 ((uint32_t)0x00000080) /*!< 1/256 */ +#define UART_PLESCALER_512 ((uint32_t)0x00000090) /*!< 1/512 */ +/** + * @} + */ /* End of group UART_Prescaler */ + + +/** + * @defgroup UART_Clock_Mask Clock Mask + * @brief Clock Mask Macro Definition. + * @{ + */ +#define UART_UARTxCLK_MASK ((uint32_t)0x00000000) /*!< [1:0] is always 0 */ +/** + * @} + */ /* End of group UART_Clock_Mask */ + + +/** + * @defgroup UART_Division Division + * @brief Enable/Disable Division Macro Definition. + * @{ + */ +#define UART_DIVISION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /*!< Enable */ +/** + * @} + */ /* End of group UART_Division */ + + +/** + * @defgroup UART_RangeK Range K + * @brief Range of K Macro Definition. + * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= UART_RANGE_K_MAX)". + * @{ + */ +#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ +#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ +/** + * @} + */ /* End of group UART_RangeK */ + + +/** + * @defgroup UART_RangeN Range N + * @brief Range of N Macro Definition. + * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= UART_RANGE_N_MAX)". + * @{ + */ +#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /*!< Minimum Value :N=1 */ +#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ +/** + * @} + */ /* End of group UART_RangeN */ + + +/** + * @defgroup UART_SettingEnable Setting Enable + * @brief Enable/Disable Setting Macro Definition. + * @{ + */ +#define UART_SETTING_MASK ((uint32_t)0x80000000) /*!< for Mask */ +#define UART_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define UART_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group UART_SettingEnable */ + + +/** + * @defgroup UART_TxState Tx State + * @brief Transmitting State Macro Definition. + * @{ + */ +#define UART_TX_STATE_MASK ((uint32_t)0x00008000) /*!< for Mask */ +#define UART_TX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ +#define UART_TX_STATE_RUN ((uint32_t)0x00008000) /*!< Run */ +/** + * @} + */ /* End of group UART_TxState */ + + +/** + * @defgroup UART_TxDone Transmitting Done + * @brief Transmitting Done Macro Definition. + * @{ + */ +#define UART_TX_MASK ((uint32_t)0x00004000) /*!< for Mask */ +#define UART_TX_DONE ((uint32_t)0x00004000) /*!< Transmitting Done */ +/** + * @} + */ /* End of group UART_TxDone */ + + +/** + * @defgroup UART_TxReachFillLevel Tx Reach Fill Level + * @brief Reach Transmitting Fill Level Macro Definition. + * @{ + */ +#define UART_TX_REACH_FILL_MASK ((uint32_t)0x00002000) /*!< for Mask */ +#define UART_TX_REACH_FILL_LEVEL ((uint32_t)0x00002000) /*!< Reach Transmitting Fill Level */ +/** + * @} + */ /* End of group UART_TxReachFillLevel */ + + +/** + * @defgroup UART_TxFifoLevel Tx FIFO Fill Level + * @brief Transmitting FIFO Fill Level Macro Definition. + * @{ + */ +#define UART_TX_FIFO_LEVEL_MASK ((uint32_t)0x00000F00) /*!< for Mask */ +/** + * @} + */ /* End of group UART_TxFifoLevel */ + + +/** + * @defgroup UART_RxState Rx State + * @brief Receive State Macro Definition. + * @{ + */ +#define UART_RX_STATE_MASK ((uint32_t)0x00000080) /*!< for Mask */ +#define UART_RX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ +#define UART_RX_STATE_RUN ((uint32_t)0x00000080) /*!< Run */ +/** + * @} + */ /* End of group UART_RxState */ + + +/** + * @defgroup UART_RxDone Rx Done + * @brief Receive Done Macro Definition. + * @{ + */ +#define UART_RX_MASK ((uint32_t)0x00000040) /*!< for Mask */ +#define UART_RX_DONE ((uint32_t)0x00000040) /*!< Receive Done */ +/** + * @} + */ /* End of group UART_RxDone */ + + +/** + * @defgroup UART_RxReachFillLevel Rx Reach Fill Level + * @brief Reach Receive Fill Level Macro Definition. + * @{ + */ +#define UART_RX_REACH_FILL_MASK ((uint32_t)0x00000020) /*!< for Mask */ +#define UART_RX_REACH_FILL_LEVEL ((uint32_t)0x00000020) /*!< Reach Receive Fill Level */ +/** + * @} + */ /* End of group UART_RxReachFillLevel */ + + +/** + * @defgroup UART_RxFifoLevel Rx FIFO Fill Level + * @brief Receive FIFO Fill Level Macro Definition. + * @{ + */ +#define UART_RX_FIFO_LEVEL_MASK ((uint32_t)0x0000000F) /*!< for Mask */ +/** + * @} + */ /* End of group UART_RxFifoLevel */ + + +/** + * @defgroup UART_TriggerErr Trigger Error + * @brief Trigger Error Macro Definition. + * @{ + */ +#define UART_TRIGGER_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_TRIGGER_ERR ((uint32_t)0x00000010) /*!< Error */ +/** + * @} + */ /* End of group UART_TxTriggerErr */ + + +/** + * @defgroup UART_OverrunErr Overrun Error + * @brief Overrun Error Macro Definition. + * @{ + */ +#define UART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ +/** + * @} + */ /* End of group UART_OverrunErr */ + + +/** + * @defgroup UART_ParityErr Parity Error + * @brief Parity Error Macro Definition. + * @{ + */ +#define UART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_PARITY_ERR ((uint32_t)0x00000004) /*!< Error */ +/** + * @} + */ /* End of group UART_ParityErr */ + + +/** + * @defgroup UART_FramingErr Framing Error + * @brief Framing Error Macro Definition. + * @{ + */ +#define UART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_FRAMING_ERR ((uint32_t)0x00000002) /*!< Error */ +/** + * @} + */ /* End of group UART_FramingErr */ + + +/** + * @defgroup UART_BreakErr Break Error + * @brief Break Error Macro Definition. + * @{ + */ +#define UART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_BREAK_ERR ((uint32_t)0x00000001) /*!< Error */ +/** + * @} + */ /* End of group UART_BreakErr */ + +/** + * @} + */ /* End of group UART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_define UART Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_typedef UART Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. + * @brief When data length definition is "7 or 8bit"( @ref UART_DataLength ), use this. + * @attention "num" must be over FIFO max num. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} uart_receive8_t; + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. + * @brief When data length definition is "9bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} uart_receive16_t; + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. +*/ +/*----------------------------------*/ +typedef union { + uart_receive8_t rx8; /*!< @ref uart_receive8_t */ + uart_receive16_t rx16; /*!< @ref uart_receive16_t */ +} uart_receive_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. + * @brief When data length definition is "7 or 8bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} uart_transmit8_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. + * @brief When data length definition is "9bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to transmit data. + Rransmit data valid range is ( 0x0000 <= range <= 0x01FF ) */ + uint32_t num; /*!< The number of transmit data. */ +} uart_transmit16_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. +*/ +/*----------------------------------*/ +typedef union { + uart_transmit8_t tx8; /*!< @ref uart_transmit8_t */ + uart_transmit16_t tx16; /*!< @ref uart_transmit16_t */ +} uart_transmit_t; + +/*----------------------------------*/ +/** + * @brief Clock setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t prsel; /*!< Prescaler. + : Use @ref UART_Prescaler */ +} uart_clock_t; + +/*----------------------------------*/ +/** + * @brief Boudrate setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ken; /*!< Enable/Disable Division Definition. + : Use @ref UART_Division */ + uint32_t brk; /*!< Division Value K. + : K Range ( UART_RANGE_K_MIN <= K =< UART_RANGE_K_MAX ) @ref UART_RangeK */ + uint32_t brn; /*!< Division Value N. + : N Range ( UART_RANGE_N_MIN <= N =< UART_RANGE_N_MAX ) @ref UART_RangeN */ +} uart_boudrate_t; + +/*----------------------------------*/ +/** + * @brief Transmit FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inttx; /*!< Available Transmit FIFO Interrupt. + : Use @ref UART_TxFIFOInterrupt */ + uint32_t level; /*!< Transmit Fill Level. + : Range ( UART_TX_FILL_RANGE_MIN <= K =< UART_TX_FILL_RANGE_MAX ) @ref UART_TxFillLevelRange */ +} uart_tx_fifo_t; + +/*----------------------------------*/ +/** + * @brief Receive FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intrx; /*!< Available Receive FIFO Interrupt. + : Use @ref UART_RxFIFOInterrupt */ + uint32_t level; /*!< Receive Fill Level. + : Range ( UART_RX_FILL_RANGE_MIN <= K =< UART_RX_FILL_RANGE_MAX ) @ref UART_RxFillLevelRange */ +} uart_rx_fifo_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + uart_clock_t clock; /*!< Clock setting. + : Use @ref uart_clock_t */ + uart_boudrate_t boudrate; /*!< Boudrate setting. + : Use @ref uart_boudrate_t */ + uint32_t inttx; /*!< Available Transmit Interrupt. + : Use @ref UART_TxInterrupt */ + uint32_t intrx; /*!< Available Receive Interrupt. + : Use @ref UART_RxInterrupt */ + uint32_t interr; /*!< Available Error Interrupt. + : Use @ref UART_ErrorInterrupt */ + uart_tx_fifo_t txfifo; /*!< Transmit FIFO setting. + : Use @ref uart_tx_fifo_t */ + uart_rx_fifo_t rxfifo; /*!< Receive FIFO setting. + : Use @ref uart_rx_fifo_t */ + uint32_t hct; /*!< Half Clock Terminal Select. + : Use @ref UART_HalfClockSelect */ + uint32_t hcm; /*!< Half Clock Mode Select. + : Use @ref UART_HalfClockMode */ + uint32_t hcc; /*!< Half Clock Control. + : Use @ref UART_HalfClockCTR */ + uint32_t lbc; /*!< Loop Back Control. + : Use @ref UART_LoopBack */ + uint32_t nf; /*!< UTxRXD Noise Filter. + : Use @ref UART_NoiseFilter */ + uint32_t ctse; /*!< Available CTS Handshake. + : Use @ref UART_CTSHandshake */ + uint32_t rtse; /*!< Available RTS Handshake. + : Use @ref UART_RTSHandshake */ + uint32_t iv; /*!< Data Signal Complementation. + : Use @ref UART_DataComplementation */ + uint32_t dir; /*!< Data Direction. + : Use @ref UART_DataDirection */ + uint32_t sblen; /*!< Stop Bit. + : Use @ref UART_StopBit */ + uint32_t even; /*!< Odd/Even Parity Bit. + : Use @ref UART_ParityBit */ + uint32_t pe; /*!< Enable/Disable Parity Bit. + : Use @ref UART_ParityEnable */ + uint32_t sm; /*!< Data Length. + : Use @ref UART_DataLength */ +} uart_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief UART handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_UART_TypeDef *p_instance; /*!< Registers base address. */ + uart_initial_setting_t init; /*!< Initial setting. */ + /*------------------------------------------*/ + /*! + @brief Transmit Information. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmitted data. */ + uart_transmit_t info; /*!< Transmit Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Information. + */ + /*------------------------------------------*/ + struct { + uart_receive_t info; /*!< Receive Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result, uart_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} uart_t; + +/** + * @} + */ /* End of group UART_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_functions UART Exported Functions + * @{ + */ +TXZ_Result uart_init(uart_t *p_obj); +TXZ_Result uart_deinit(uart_t *p_obj); +TXZ_Result uart_discard_transmit(uart_t *p_obj); +TXZ_Result uart_discard_receive(uart_t *p_obj); +TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info); +TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info); +void uart_transmit_irq_handler(uart_t *p_obj); +void uart_receive_irq_handler(uart_t *p_obj); +void uart_error_irq_handler(uart_t *p_obj); +TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status); +TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error); +TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_setting); +/** + * @} + */ /* End of group UART_Exported_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart_include.h new file mode 100644 index 00000000000..c404645b502 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart_include.h @@ -0,0 +1,471 @@ +/** + ******************************************************************************* + * @file txz_uart_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __UART_INCLUDE_H +#define __UART_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_define + * @{ + */ + +/** + * @defgroup UART_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define UART_NULL ((void *)0) +/** + * @} + */ /* End of group UART_NullPointer */ + +/** + * @defgroup UART_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define UART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define UART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group UART_ParameterResult */ + +/** + * @defgroup UARTxSWRST UARTxSWRST Register + * @brief UARTxSWRST Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | SWRSTF | + * | 6:2 | - | + * | 1:0 | SWRST | + * @{ + */ +/* SWRSTF */ +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /*!< SWRSTF :Mask. */ +#define UARTxSWRST_SWRSTF_IDLE ((uint32_t)0x00000000) /*!< SWRSTF :Not be "Software Reset". */ +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /*!< SWRSTF :During "Software Reset". */ +/* SWRST */ +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /*!< SWRST :"10" */ +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /*!< SWRST :"01" */ +/** + * @} + */ /* End of group UARTxSWRST */ + +/** + * @defgroup UARTxCR0 UARTxCR0 Register + * @brief UARTxCR0 Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-19 | - | + * | 18 | HBSST | + * | 17 | HBSMD | + * | 16 | HBSEN | + * | 15 | LPB | + * | 14-12 | NF[2:0] | + * | 11 | - | + * | 10 | CTSE | + * | 9 | RTSE | + * | 8 | WU | + * | 7 | - | + * | 6 | IV | + * | 5 | DIR | + * | 4 | SBLEN | + * | 3 | EVEN | + * | 2 | PE | + * | 1-0 | SM[1:0] | + * @{ + */ +/* HBSST */ +#define UARTxCR0_HBSST_MASK ((uint32_t)0x00040000) /*!< HBSST :Mask. */ +/* HBSMD */ +#define UARTxCR0_HBSMD_MASK ((uint32_t)0x00020000) /*!< HBSMD :Mask. */ +/* HBSEN */ +#define UARTxCR0_HBSEN_MASK ((uint32_t)0x00010000) /*!< HBSEN :Mask. */ +#define UARTxCR0_HBSEN_DISABLE ((uint32_t)0x00000000) /*!< HBSEN :Disable. */ +#define UARTxCR0_HBSEN_ENABLE ((uint32_t)0x00010000) /*!< HBSEN :Enable. */ +/* LPB */ +#define UARTxCR0_LPB_MASK ((uint32_t)0x00008000) /*!< LPB :Mask. */ +#define UARTxCR0_LPB_DISABLE ((uint32_t)0x00000000) /*!< LPB :Disable. */ +#define UARTxCR0_LPB_ENABLE ((uint32_t)0x00008000) /*!< LPB :Enable. */ +/* WU */ +#define UARTxCR0_WU_MASK ((uint32_t)0x00000100) /*!< WU :Mask. */ +#define UARTxCR0_WU_DISABLE ((uint32_t)0x00000000) /*!< WU :Disable. */ +#define UARTxCR0_WU_ENABLE ((uint32_t)0x00000100) /*!< WU :Enable. */ +/** + * @} + */ /* End of group UARTxCR0 */ + +/** + * @defgroup UARTxCR1 UARTxCR1 Register + * @brief UARTxCR1 Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-15 | - | + * | 14-12 | TIL[2:0] | + * | 11 | - | + * | 10-8 | RIL[2:0] | + * | 7 | INTTXFE | + * | 6 | INTTXWE | + * | 5 | INTRXFE | + * | 4 | INTRXWE | + * | 3 | - | + * | 2 | INTERR | + * | 1 | DMATE | + * | 0 | DMARE | + * @{ + */ +/* RIL */ +#define UARTxCR1_RIL_MASK ((uint32_t)0x00000700) /*!< RIL :Mask. */ +/* DMATE */ +#define UARTxCR1_DMATE_MASK ((uint32_t)0x00000002) /*!< DMATE :Mask. */ +#define UARTxCR1_DMATE_DISABLE ((uint32_t)0x00000000) /*!< DMATE :Disable. */ +#define UARTxCR1_DMATE_ENABLE ((uint32_t)0x00000002) /*!< DMATE :Enable. */ +/* DMARE */ +#define UARTxCR1_DMARE_MASK ((uint32_t)0x00000001) /*!< DMARE :Mask. */ +#define UARTxCR1_DMARE_DISABLE ((uint32_t)0x00000000) /*!< DMARE :Disable. */ +#define UARTxCR1_DMARE_ENABLE ((uint32_t)0x00000001) /*!< DMARE :Enable. */ +/** + * @} + */ /* End of group UARTxCR1 */ + +/** + * @defgroup UARTxTRANS UARTxTRANS Register + * @brief UARTxTRANS Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-4 | - | + * | 3 | BK | + * | 2 | TXTRG | + * | 1 | TXE | + * | 0 | RXE | + * @{ + */ +/* BK */ +#define UARTxTRANS_BK_MASK ((uint32_t)0x00000008) /*!< BK :Mask */ +#define UARTxTRANS_BK_STOP ((uint32_t)0x00000000) /*!< BK :Stop */ +#define UARTxTRANS_BK_SEND ((uint32_t)0x00000008) /*!< BK :Send */ +/* TXTRG */ +#define UARTxTRANS_TXTRG_MASK ((uint32_t)0x00000004) /*!< TXTRG :Mask */ +#define UARTxTRANS_TXTRG_DISABLE ((uint32_t)0x00000000) /*!< TXTRG :Disable */ +#define UARTxTRANS_TXTRG_ENABLE ((uint32_t)0x00000004) /*!< TXTRG :Enable */ +/* TXE */ +#define UARTxTRANS_TXE_MASK ((uint32_t)0x00000002) /*!< TXE :Mask */ +#define UARTxTRANS_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable */ +#define UARTxTRANS_TXE_ENABLE ((uint32_t)0x00000002) /*!< TXE :Enable */ +/* RXE */ +#define UARTxTRANS_RXE_MASK ((uint32_t)0x00000001) /*!< RXE :Mask */ +#define UARTxTRANS_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable */ +#define UARTxTRANS_RXE_ENABLE ((uint32_t)0x00000001) /*!< RXE :Enable */ +/* TXE,RXE */ +#define UARTxTRANS_TXE_RXE_MASK ((uint32_t)0x00000003) /*!< TXE/RXE:Mask */ +/** + * @} + */ /* End of group UARTxTRANS */ + +/** + * @defgroup UARTxDR UARTxDR Register + * @brief UARTxDR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-19 | - | + * | 18 | PERR | + * | 17 | FERR | + * | 16 | BERR | + * | 15:9 | - | + * | 8:0 | DR | + * @{ + */ +/* DR */ +#define UARTxDR_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 9bit */ +#define UARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define UARTxDR_DR_7BIT_MASK ((uint32_t)0x0000007F) /*!< DR :Mask for 7bit */ +/** + * @} + */ /* End of group UARTxDR */ + +/** + * @defgroup UARTxSR UARTxSR Register + * @brief UARTxSR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31 | SUE | + * | 30:16 | - | + * | 15 | TXRUN | + * | 14 | TXEND | + * | 13 | TXFF | + * | 12 | - | + * | 11:8 | TLVL | + * | 7 | RXRUN | + * | 6 | RXEND | + * | 5 | RXFF | + * | 4 | - | + * | 3:0 | RLVL | + * @{ + */ +/* SUE */ +#define UARTxSR_SUE_MASK ((uint32_t)0x80000000) /*!< SUE :Mask. */ +/* TXEND */ +#define UARTxSR_TXEND_MASK ((uint32_t)0x00004000) /*!< TEXND :Mask. */ +#define UARTxSR_TXEND_R_END ((uint32_t)0x00004000) /*!< TXEND :[read] Transfer done. */ +#define UARTxSR_TXEND_W_CLEAR ((uint32_t)0x00004000) /*!< TXEND :[write] Clear Flag. */ +/* TXFF */ +#define UARTxSR_TXFF_MASK ((uint32_t)0x00002000) /*!< TXFF :Mask. */ +#define UARTxSR_TXFF_R_REACHED ((uint32_t)0x00002000) /*!< TXFF :[read] Reached the transfer level. */ +#define UARTxSR_TXFF_W_CLEAR ((uint32_t)0x00002000) /*!< TXFF :[write] Clear Flag. */ +/* TLVL */ +#define UARTxSR_TLVL_MASK ((uint32_t)0x00000F00) /*!< TLVL :Mask. */ +/* RXEND */ +#define UARTxSR_RXEND_MASK ((uint32_t)0x00000040) /*!< RXEND :Mask. */ +#define UARTxSR_RXEND_R_END ((uint32_t)0x00000040) /*!< RXEND :[read] Receive done. */ +#define UARTxSR_RXEND_W_CLEAR ((uint32_t)0x00000040) /*!< RXEND :[write] Clear Flag. */ +/* RXFF */ +#define UARTxSR_RXFF_MASK ((uint32_t)0x00000020) /*!< RXFF :Mask. */ +#define UARTxSR_RXFF_R_REACHED ((uint32_t)0x00000020) /*!< RXFF :[read] Receive done. */ +#define UARTxSR_RXFF_W_CLEAR ((uint32_t)0x00000020) /*!< RXFF :[write] Clear Flag. */ +/* RLVL */ +#define UARTxSR_RLVL_MASK ((uint32_t)0x0000000F) /*!< RLVL :Mask. */ +/** + * @} + */ /* End of group UARTxSR */ + +/** + * @defgroup UARTxFIFOCLR UARTxFIFOCLR Register + * @brief UARTxFIFOCLR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-2 | - | + * | 1 | TFCLR | + * | 0 | RFCLR | + * @{ + */ +/* TFCLR */ +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /*!< TFCLR :Clear the transmit buff. */ +/* RFCLR */ +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /*!< RFCLR :Clear the receive buff. */ +/** + * @} + */ /* End of group UARTxFIFOCLR */ + +/** + * @defgroup UARTxERR UARTxERR Register + * @brief UARTxERR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-5 | - | + * | 4 | TRGERR | + * | 3 | OVRERR | + * | 2 | PERR | + * | 1 | FERR | + * | 0 | BERR | + * @{ + */ +/* TRGERR */ +#define UARTxERR_TRGERR_MASK ((uint32_t)0x00000010) /*!< TRGERR :Mask. */ +#define UARTxERR_TRGERR_R_NO_ERR ((uint32_t)0x00000000) /*!< TRGERR :[read] No Error. */ +#define UARTxERR_TRGERR_R_ERR ((uint32_t)0x00000010) /*!< TRGERR :[read] Error. */ +#define UARTxERR_TRGERR_W_CLEAR ((uint32_t)0x00000010) /*!< TRGERR :[write] Clear Flag. */ +/* OVRERR */ +#define UARTxERR_OVRERR_MASK ((uint32_t)0x00000008) /*!< OVRERR :Mask. */ +#define UARTxERR_OVRERR_R_NO_ERR ((uint32_t)0x00000000) /*!< OVRERR :[read] No Error. */ +#define UARTxERR_OVRERR_R_ERR ((uint32_t)0x00000008) /*!< OVRERR :[read] Error. */ +#define UARTxERR_OVRERR_W_CLEAR ((uint32_t)0x00000008) /*!< OVRERR :[write] Clear Flag. */ +/* PERR */ +#define UARTxERR_PERR_MASK ((uint32_t)0x00000004) /*!< PERR :Mask. */ +#define UARTxERR_PERR_R_NO_ERR ((uint32_t)0x00000000) /*!< PERR :[read] No Error. */ +#define UARTxERR_PERR_R_ERR ((uint32_t)0x00000004) /*!< PERR :[read] Error. */ +#define UARTxERR_PERR_W_CLEAR ((uint32_t)0x00000004) /*!< PERR :[write] Clear Flag. */ +/* FERR */ +#define UARTxERR_FERR_MASK ((uint32_t)0x00000002) /*!< FERR :Mask. */ +#define UARTxERR_FERR_R_NO_ERR ((uint32_t)0x00000000) /*!< FERR :[read] No Error. */ +#define UARTxERR_FERR_R_ERR ((uint32_t)0x00000002) /*!< FERR :[read] Error. */ +#define UARTxERR_FERR_W_CLEAR ((uint32_t)0x00000002) /*!< FERR :[write] Clear Flag. */ +/* BERR */ +#define UARTxERR_BERR_MASK ((uint32_t)0x00000001) /*!< BERR :Mask. */ +#define UARTxERR_BERR_R_NO_ERR ((uint32_t)0x00000000) /*!< BERR :[read] No Error. */ +#define UARTxERR_BERR_R_ERR ((uint32_t)0x00000001) /*!< BERR :[read] Error. */ +#define UARTxERR_BERR_W_CLEAR ((uint32_t)0x00000001) /*!< BERR :[write] Clear Flag. */ +/** + * @} + */ /* End of group UARTxERR */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_functions + * @{ + */ +__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); +/*--------------------------------------------------*/ +/** + * @brief Disable UARTxTRANS TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable UARTxTRANS TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable UARTxTRANS RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable UARTxTRANS RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1; +#endif +} + + +/** + * @} + */ /* End of group UART_Private_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc.c new file mode 100644 index 00000000000..e7f2ca48c9e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc.c @@ -0,0 +1,1067 @@ +/** + ******************************************************************************* + * @file txz_adc.c + * @brief This file provides API functions for ADC driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_adc_include.h" +#include "txz_adc_ch.h" +#include "txz_adc.h" + +#if defined(__ADC_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup ADC + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_macro ADC Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_Enumeration ADC Private Enumeration + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_Enumeration */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Variable Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_variable ADC Private Variable Definition + * @{ + */ +static adc_t *p_AdcObj; +/** + * @} + */ /* End of group ADC_Private_variable */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_fuctions ADC Private Fuctions + * @{ + */ +static int32_t check_param_sampling_period0(adc_sampling_period0_t param); +static int32_t check_param_sampling_period1(adc_sampling_period1_t param); +static int32_t check_param_prescaler_output(adc_sclk_t param); +static int32_t check_param_interrupt(adc_int_t param); +static int32_t check_param_type(adc_conversion_t param); +static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max); +static void clear_ch_instance_info(adc_ch_t *p_ch); + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_sampling_period0(adc_sampling_period0_t param) + * @brief Check the Sampling Period's parameter. + * @param[in] param :Sampling Period's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_sampling_period0(adc_sampling_period0_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_SAMPLING_PERIOD0_XN: + case ADC_SAMPLING_PERIOD0_X2N: + case ADC_SAMPLING_PERIOD0_X3N: + case ADC_SAMPLING_PERIOD0_X4N: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_sampling_period1(adc_sampling_period1_t param) + * @brief Check the Sampling Period's parameter. + * @param[in] param :Sampling Period's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_sampling_period1(adc_sampling_period1_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_SAMPLING_PERIOD1_XN: + case ADC_SAMPLING_PERIOD1_X2N: + case ADC_SAMPLING_PERIOD1_X3N: + case ADC_SAMPLING_PERIOD1_X4N: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_prescaler_output(adc_sclk_t param) + * @brief Check the AD Prescaler Output's parameter. + * @param[in] param :AD Prescaler Output's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_SCLK"ADC_SCLK_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_prescaler_output(adc_sclk_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_SCLK_2: + case ADC_SCLK_4: + case ADC_SCLK_8: + case ADC_SCLK_16: + case ADC_SCLK_3: + case ADC_SCLK_5: + case ADC_SCLK_6: + case ADC_SCLK_10: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_interrupt(adc_int_t param) + * @brief Check the Interrupt's parameter. + * @param[in] param :Interrupt's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_IntEnable"ADC_INT_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_interrupt(adc_int_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_INT_DISABLE: + case ADC_INT_ENABLE: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_type(adc_conversion_t param) + * @brief Check the Conversion Type's parameter. + * @param[in] param :Conversion Type's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_Conversion"ADC_CONVERSION_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_type(adc_conversion_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_CONVERSION_DISABLE: + case ADC_CONVERSION_CNT: + case ADC_CONVERSION_SGL: + case ADC_CONVERSION_TRG: + case ADC_CONVERSION_HPTG: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max) + * @brief Check the AIN Range's parameter. + * @param[in] ain :AIN Range's parameter + * @param[in] min :Range Min. + * @param[in] max :Range Max. + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note - + */ +/*--------------------------------------------------*/ +static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max) +{ + int32_t result = ADC_PARAM_NG; + + if (min == 0) { + if (ain <= max) { + result = ADC_PARAM_OK; + } + } else { + if ((min <= ain) && (ain <= max)) { + result = ADC_PARAM_OK; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static void clear_ch_instance_info(adc_ch_t *p_ch) + * @brief Channel Instance Information Clear. + * @param[in] p_ch :Channel Instance Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +static void clear_ch_instance_info(adc_ch_t *p_ch) +{ + p_ch->p_tset = ADC_NULL; + p_ch->p_reg = ADC_NULL; + p_ch->init.type = ADC_CONVERSION_DISABLE; +} +/*--------------------------------------------------*/ +/*! + * @fn static void adc_compa_irq_handler( void ) + * @brief IRQ Handler for Compare_A done. + * @param - + * @retval - + * @note Call by Compare_A Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_compa_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->init.CMPxEN[0].handle != ADC_NULL)) { + p_AdcObj->init.CMPxEN[0].handle(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_compb_irq_handler( void ) + * @brief IRQ Handler for Compare_B done. + * @param - + * @retval - + * @note Call by Compare_B Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_compb_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->init.CMPxEN[1].handle != ADC_NULL)) { + p_AdcObj->init.CMPxEN[1].handle(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_single_irq_handler( void ) + * @brief IRQ Handler for single conversion done. + * @param - + * @retval - + * @note Call by Single Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_single_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.single != ADC_NULL)) { + p_AdcObj->handler.single(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_continuity_irq_handler( void ) + * @brief IRQ Handler for continuity conversion done. + * @param - + * @retval - + * @note Call by Continuity Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_continuity_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.continuity != ADC_NULL)) { + p_AdcObj->handler.continuity(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_trigger_irq_handler( void ) + * @brief IRQ Handler for trigger conversion done. + * @param - + * @retval - + * @note Call by Trigger Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_trigger_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.trigger != ADC_NULL)) { + p_AdcObj->handler.trigger(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_highpriority_irq_handler( void ) + * @brief IRQ Handler for highpriority conversion done. + * @param - + * @retval - + * @note Call by HigPriority Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_highpriority_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.highpriority != ADC_NULL)) { + p_AdcObj->handler.highpriority(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/** + * @} + */ /* End of group ADC_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup ADC_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_init(adc_t *p_obj) + * @brief Initialize the ADC object. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_init(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + /* Check the parameter. */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if ((void *)(p_obj->p_instance) == (void *)0) { + result = TXZ_ERROR; + } + if (check_param_sampling_period0(p_obj->init.clk.exaz0) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (check_param_sampling_period1(p_obj->init.clk.exaz1) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (p_obj->init.clk.sampling_select > 0x0100000) { + result = TXZ_ERROR; + } + if (check_param_prescaler_output(p_obj->init.clk.vadcld) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (result == TXZ_SUCCESS) { + /*------------------------------*/ + /* Init Variable */ + /*------------------------------*/ + uint32_t i; + + for (i = 0; i < ADC_NUM_MAX; i++) { + clear_ch_instance_info(&p_obj->info.ch[i]); + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCLK ---*/ + p_obj->p_instance->CLK = ((uint32_t)p_obj->init.clk.exaz0 | (uint32_t)p_obj->init.clk.exaz1 | (uint32_t)p_obj->init.clk.vadcld); + /*--- ADxEXAZSEL ---*/ + p_obj->p_instance->EXAZSEL = (uint32_t)p_obj->init.clk.sampling_select; + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); + /* wait 3us after set the MOD0 to 1 */ + wait(3); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->MOD1 = p_obj->init.mod1; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = p_obj->init.mod2; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_deinit(adc_t *p_obj) + * @brief Release the ADC object. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_deinit(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t i; + adc_ch_t *p_ch; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + /*------------------------------*/ + /* Wait Stop */ + /*------------------------------*/ + /*--- ADxST ---*/ + /* When all convetion stop, ADxST is set "0". */ + while (p_obj->p_instance->ST != 0) { + /* no processing */ + } + /*------------------------------*/ + /* Channel Class Destruct */ + /*------------------------------*/ + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type == ADC_CONVERSION_DISABLE) { + if (adc_ch_deinit(p_ch) == TXZ_SUCCESS) { + clear_ch_instance_info(p_ch); + } + } + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCMPEN ---*/ + p_obj->p_instance->CMPEN = (ADxCMPEN_CMP1EN_DISABLE | ADxCMPEN_CMP0EN_DISABLE); + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_IREF_CUT | ADxMOD0_DACON_OFF); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->MOD1 = ADC_MOD1_SCLK_3; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = ADC_MOD2_CLEAR; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) + * @brief ADC Channel Setting + * @param[in] p_obj :ADC object. + * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). + * @param[in] p_setting :Channel Setting Source Address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0) || + ((void *)(p_setting) == (void *)0) || + (ch >= ADC_NUM_MAX)) { + result = TXZ_ERROR; + } + if (check_param_interrupt((adc_int_t)p_setting->interrupt) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (check_param_type((adc_conversion_t)p_setting->type) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (check_param_ain((adc_ain_range_t)p_setting->ain, ADC_AIN_RANGE_MIN, ADC_AIN_RANGE_MAX) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (result == TXZ_SUCCESS) { + /*------------------------------*/ + /* Channel Class Construct */ + /*------------------------------*/ + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + p_ch->p_tset = (__IO uint32_t *)(&p_obj->p_instance->TSET0 + ch); + p_ch->p_reg = (__I uint32_t *)(&p_obj->p_instance->REG0 + ch); + p_ch->init.interrupt = p_setting->interrupt; + p_ch->init.type = p_setting->type; + p_ch->init.ain = p_setting->ain; + result = adc_ch_init(p_ch); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) + * @brief ADC Channel Clear + * @param[in] p_obj :ADC object. + * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + (ch >= ADC_NUM_MAX)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Channel Class Destruct */ + /*------------------------------*/ + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + result = adc_ch_deinit(p_ch); + /* Init Variable */ + clear_ch_instance_info(p_ch); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) + * @brief Initialize the ADC Compare register + * @param[in] p_obj :ADC object. + * @param[in] p_cmpx_t :Clock information structure. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_cmpx_t) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Init Variable */ + /*------------------------------*/ + if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE) { + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE; + } + if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE) { + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE; + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + if (p_cmpx_t->CMPEN == ADCMP0EN_ENABLE) { + p_obj->init.CMPxEN[0].CMPEN = p_cmpx_t->CMPEN; + p_obj->init.CMPxEN[0].CMPCNT = p_cmpx_t->CMPCNT; + p_obj->init.CMPxEN[0].CMPCond = p_cmpx_t->CMPCond; + p_obj->init.CMPxEN[0].CMPBigSml = p_cmpx_t->CMPBigSml; + p_obj->init.CMPxEN[0].StrReg = p_cmpx_t->StrReg; + p_obj->init.CMPxEN[0].ADComp = p_cmpx_t->ADComp; + p_obj->init.CMPxEN[0].handle = p_cmpx_t->handle; + p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; + p_obj->p_instance->CMPCR0 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; + p_obj->p_instance->CMP0 = p_cmpx_t->ADComp; + } else if (p_cmpx_t->CMPEN == ADCMP1EN_ENABLE) { + p_obj->init.CMPxEN[1].CMPEN = p_cmpx_t->CMPEN; + p_obj->init.CMPxEN[1].CMPCNT = p_cmpx_t->CMPCNT; + p_obj->init.CMPxEN[1].CMPCond = p_cmpx_t->CMPCond; + p_obj->init.CMPxEN[1].CMPBigSml = p_cmpx_t->CMPBigSml; + p_obj->init.CMPxEN[1].StrReg = p_cmpx_t->StrReg; + p_obj->init.CMPxEN[1].ADComp = p_cmpx_t->ADComp; + p_obj->init.CMPxEN[1].handle = p_cmpx_t->handle; + p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; + p_obj->p_instance->CMPCR1 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; + p_obj->p_instance->CMP1 = p_cmpx_t->ADComp; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) + * @brief Release the ADC Compare register + * @param[in] p_obj :ADC object. + * @param[in] p_cmpx_t :Clock information structure. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_cmpx_t) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE) { + p_obj->init.CMPxEN[0].CMPEN = 0; + p_obj->init.CMPxEN[0].CMPCNT = 0; + p_obj->init.CMPxEN[0].CMPCond = 0; + p_obj->init.CMPxEN[0].CMPBigSml = 0; + p_obj->init.CMPxEN[0].StrReg = 0; + p_obj->init.CMPxEN[0].ADComp = 0; + p_obj->init.CMPxEN[0].handle = (void *)0; + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE; + p_obj->p_instance->CMPCR0 = 0; + p_obj->p_instance->CMP0 = 0; + } else if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE) { + p_obj->init.CMPxEN[1].CMPEN = 0; + p_obj->init.CMPxEN[1].CMPCNT = 0; + p_obj->init.CMPxEN[1].CMPCond = 0; + p_obj->init.CMPxEN[1].CMPBigSml = 0; + p_obj->init.CMPxEN[1].StrReg = 0; + p_obj->init.CMPxEN[1].ADComp = 0; + p_obj->init.CMPxEN[1].handle = (void *)0; + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE; + p_obj->p_instance->CMPCR1 = 0; + p_obj->p_instance->CMP1 = 0; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) + * @brief Get AD value + * @param[in] p_obj :ADC object. + * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). + * @param p_value :AD value. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0) || + ((void *)(p_value) == (void *)0) || + (ch >= ADC_NUM_MAX)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Get Value */ + /*------------------------------*/ + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + result = adc_ch_get_value(p_ch, p_value); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_start(adc_t *p_obj) + * @brief Start Conversion. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_start(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Enable Conversion */ + /*------------------------------*/ + uint32_t i; + adc_ch_t *p_ch; + uint32_t cr0 = (ADxCR0_ADEN_ENABLE | ADxCR0_CNT_DISABLE); + uint32_t cr1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + switch (p_ch->init.type) { + case ADC_CONVERSION_CNT: + cr0 |= ADxCR0_CNT_ENABLE; + break; + case ADC_CONVERSION_SGL: + cr0 |= ADxCR0_SGL_ENABLE; + break; + case ADC_CONVERSION_TRG: + cr1 |= ADxCR1_TRGEN_ENABLE; + break; + case ADC_CONVERSION_HPTG: + cr1 |= ADxCR1_HPTRGEN_ENABLE; + break; + default: + /* no processing */ + break; + } + } + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = cr1; + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = cr0; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_stop(adc_t *p_obj) + * @brief Stop Conversion. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_stop(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t i; + adc_ch_t *p_ch; + uint32_t value; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Disable Conversion */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + /*------------------------------*/ + /* Wait Stop */ + /*------------------------------*/ + /*--- ADxST ---*/ + /* When all convetion stop, ADxST is set "0". */ + while (p_obj->p_instance->ST != 0) { + /* no processing */ + } + /*------------------------------*/ + /* Dummy Read */ + /*------------------------------*/ + /* Read is needed before the next convertion. */ + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type == ADC_CONVERSION_DISABLE) { + if (adc_ch_get_value(p_ch, &value) != TXZ_SUCCESS) { + /* no processing */ + } + } + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout) + * @brief Wait for single conversion to be completed + * @param[in] p_obj :ADC object. + * @param[in] timeout :Timeout(tick). + * @retval TXZ_DONE :Success. + * @retval TXZ_BUSY :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout) +{ + TXZ_WorkState result = TXZ_BUSY; + TXZ_WorkState loopBreak = TXZ_BUSY; + uint32_t base = hal_get_tick(); + uint32_t current = 0; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_DONE; + } else { + /*------------------------------*/ + /* Check Status */ + /*------------------------------*/ + while (loopBreak == TXZ_BUSY) { + /*--- Check Status ---*/ + /* Read status. */ + status = p_obj->p_instance->ST; + /* Check status. */ + if ((status & ADxST_SNGF_MASK) == ADxST_SNGF_IDLE) { + result = TXZ_DONE; + loopBreak = TXZ_DONE; + } else { + /*--- Check Timeout ---*/ + if (timeout == 0) { + loopBreak = TXZ_DONE; + } else { + current = hal_get_tick(); + if (current > base) { + if ((current - base) >= timeout) { + loopBreak = TXZ_DONE; + } + } else { + base = current; + } + } + } + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @fn TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status) + * @brief Get Conversion Status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-8 | - | - | + * | 7 | ADBF | AD Running Flag. Use @ref adc_status_t. | + * | 6-4 | - | - | + * | 3 | CNTF | Continuity Conversion Running Flag. Use @ref adc_cnt_status_t. | + * | 2 | SNGF | Single Conversion Running Flag. Use @ref adc_sgl_status_t. | + * | 1 | TRGF | Trigger Conversion Running Flag. Use @ref adc_trg_status_t. | + * | 0 | - | - | + * + * @param[in] p_obj :ADC object. + * @param[out] p_status :Conversion Status. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0) || + ((void *)(p_status) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Read Register */ + /*------------------------------*/ + *p_status = p_obj->p_instance->ST; + } + + return (result); +} +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__ADC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc_ch.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc_ch.c new file mode 100644 index 00000000000..0c0241f3b44 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc_ch.c @@ -0,0 +1,347 @@ +/** + ******************************************************************************* + * @file txz_adc_ch.c + * @brief This file provides API functions for ADC driver. \n + * Channel Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_adc_include.h" +#include "txz_adc_ch.h" + +#if defined(__ADC_CH_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup ADC + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_fuctions ADC Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +/* no define */ +#endif + +/** + * @} + */ /* End of group ADC_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup ADC_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/*! + * @fn static uint32_t get_conversion_data(uint32_t reg) + * @brief Get convertion data from ADxREGn. + * @param[in] reg :ADxREGn data. + * @retval Convertion data. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t get_conversion_data(uint32_t reg) +{ + uint32_t result = (uint32_t)((reg & ADxREGn_ADRn_MASK) >> 4); + + return (result); +} +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_init(adc_ch_t *p_obj) + * @brief Initialize the ADC Channel object. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_init(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((volatile void *)(p_obj->p_tset) == (volatile void *)0) || + ((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxREGx ---*/ + /* Read is needed before the next convertion. */ + { + volatile uint32_t reg; + reg = *p_obj->p_reg; + } + /*--- ADxTSET ---*/ + *p_obj->p_tset = (p_obj->init.interrupt | p_obj->init.type | p_obj->init.ain); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) + * @brief Release the ADC Channel object. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + *p_obj->p_tset = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_DISABLE | 0); + /*--- ADxREGx ---*/ + /* Read is needed before the next convertion. */ + { + volatile uint32_t reg; + reg = *p_obj->p_reg; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) + * @brief Enable Interrupt. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((volatile void *)(p_obj->p_tset) == (volatile void *)0) || + ((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + { + uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); + + *p_obj->p_tset = (tset | ADxTSETn_ENINT_ENABLE); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) + * @brief Disable Interrupt. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((volatile void *)(p_obj->p_tset) == (volatile void *)0) || + ((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + { + uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); + + *p_obj->p_tset = (tset | ADxTSETn_ENINT_DISABLE); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) + * @brief Get conversion value. + * @param p_obj :ADC Channel object. + * @param p_value :AD value. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has done. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) +{ + TXZ_Result result = TXZ_ERROR; + uint32_t reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + reg = *p_obj->p_reg; + /*------------------------------*/ + /* Check Result */ + /*------------------------------*/ + if ((reg & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { + *p_value = get_conversion_data(reg); + result = TXZ_SUCCESS; + } + } + + return (result); +} +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__ADC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_cg.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_cg.c new file mode 100644 index 00000000000..440e0123810 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_cg.c @@ -0,0 +1,498 @@ +/** + ******************************************************************************* + * @file txz_cg.c + * @brief This file provides API functions for CG driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_cg.h" + +#if defined(__CG_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup CG + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ +#define CG_FSYS_MASK ((uint32_t)0x00070000) /*!< CG FSYS mask */ + +#define CG_FSYS_1 ((uint32_t)0x00000000) /*!< CG fc register value */ +#define CG_FSYS_2 ((uint32_t)0x00010000) /*!< CG fc/2 register value */ +#define CG_FSYS_4 ((uint32_t)0x00020000) /*!< CG fc/4 register value */ +#define CG_FSYS_8 ((uint32_t)0x00030000) /*!< CG fc/8 register value */ +#define CG_FSYS_16 ((uint32_t)0x00040000) /*!< CG fc/16 register value */ + +#define CG_FSYS_1_MUL ((uint32_t)0x00000001) /*!< CG fc multiplication value */ +#define CG_FSYS_2_MUL ((uint32_t)0x00000002) /*!< CG fc/2 multiplication value */ +#define CG_FSYS_4_MUL ((uint32_t)0x00000004) /*!< CG fc/4 multiplication value */ +#define CG_FSYS_8_MUL ((uint32_t)0x00000008) /*!< CG fc/8 multiplication value */ +#define CG_FSYS_16_MUL ((uint32_t)0x00000010) /*!< CG fc/16 multiplication value */ + +#define CG_PRCK_MASK ((uint32_t)0x00000F00) /*!< CG PRCK mask */ + +#define CG_PRCK_1 ((uint32_t)0x00000000) /*!< CG PhiT0 fc register value */ +#define CG_PRCK_2 ((uint32_t)0x00000100) /*!< CG PhiT0 fc/2 register value */ +#define CG_PRCK_4 ((uint32_t)0x00000200) /*!< CG PhiT0 fc/4 register value */ +#define CG_PRCK_8 ((uint32_t)0x00000300) /*!< CG PhiT0 fc/8 register value */ +#define CG_PRCK_16 ((uint32_t)0x00000400) /*!< CG PhiT0 fc/16 register value */ +#define CG_PRCK_32 ((uint32_t)0x00000500) /*!< CG PhiT0 fc/32 register value */ +#define CG_PRCK_64 ((uint32_t)0x00000600) /*!< CG PhiT0 fc/64 register value */ +#define CG_PRCK_128 ((uint32_t)0x00000700) /*!< CG PhiT0 fc/128 register value */ +#define CG_PRCK_256 ((uint32_t)0x00000800) /*!< CG PhiT0 fc/256 register value */ +#define CG_PRCK_512 ((uint32_t)0x00000900) /*!< CG PhiT0 fc/512 register value */ + +#define CG_PRCKST_MASK ((uint32_t)0x0F000000) /*!< CG PRCKST mask */ + +#define CG_PRCKST_1 ((uint32_t)0x00000000) /*!< CG PhiT0 fc register status */ +#define CG_PRCKST_2 ((uint32_t)0x01000000) /*!< CG PhiT0 fc/2 register status */ +#define CG_PRCKST_4 ((uint32_t)0x02000000) /*!< CG PhiT0 fc/4 register status */ +#define CG_PRCKST_8 ((uint32_t)0x03000000) /*!< CG PhiT0 fc/8 register status */ +#define CG_PRCKST_16 ((uint32_t)0x04000000) /*!< CG PhiT0 fc/16 register status */ +#define CG_PRCKST_32 ((uint32_t)0x05000000) /*!< CG PhiT0 fc/32 register status */ +#define CG_PRCKST_64 ((uint32_t)0x06000000) /*!< CG PhiT0 fc/64 register status */ +#define CG_PRCKST_128 ((uint32_t)0x07000000) /*!< CG PhiT0 fc/128 register status */ +#define CG_PRCKST_256 ((uint32_t)0x08000000) /*!< CG PhiT0 fc/256 register status */ +#define CG_PRCKST_512 ((uint32_t)0x09000000) /*!< CG PhiT0 fc/512 register status */ + +#define CG_PRCK_1_DIV ((uint32_t)0x00000001) /*!< CG PhiT0 fc division value */ +#define CG_PRCK_2_DIV ((uint32_t)0x00000002) /*!< CG PhiT0 fc/2 division value */ +#define CG_PRCK_4_DIV ((uint32_t)0x00000004) /*!< CG PhiT0 fc/4 division value */ +#define CG_PRCK_8_DIV ((uint32_t)0x00000008) /*!< CG PhiT0 fc/8 division value */ +#define CG_PRCK_16_DIV ((uint32_t)0x00000010) /*!< CG PhiT0 fc/16 division value */ +#define CG_PRCK_32_DIV ((uint32_t)0x00000020) /*!< CG PhiT0 fc/32 division value */ +#define CG_PRCK_64_DIV ((uint32_t)0x00000040) /*!< CG PhiT0 fc/64 division value */ +#define CG_PRCK_128_DIV ((uint32_t)0x00000080) /*!< CG PhiT0 fc/128 division value */ +#define CG_PRCK_256_DIV ((uint32_t)0x00000100) /*!< CG PhiT0 fc/256 division value */ +#define CG_PRCK_512_DIV ((uint32_t)0x00000200) /*!< CG PhiT0 fc/512 division value */ + + +#define CG_MCKSELPST_MASK ((uint32_t)0xC0000000) /*!< CG MCKSEL mask */ + +#define CG_MCKSELPST_1 ((uint32_t)0x00000000) /*!< CG PhiT0 fc/PRCK value */ +#define CG_MCKSELPST_2 ((uint32_t)0x40000000) /*!< CG PhiT0 fc/PRCK/2 value */ +#define CG_MCKSELPST_4 ((uint32_t)0x80000000) /*!< CG PhiT0 fc/PRCK/4 value */ + +#define CG_FSYSM_1_DIV ((uint32_t)0x00000001) /*!< CG fsysm PhiT0 division value */ +#define CG_FSYSM_2_DIV ((uint32_t)0x00000002) /*!< CG fsysm PhiT0/2 division value */ +#define CG_FSYSM_4_DIV ((uint32_t)0x00000004) /*!< CG fsysm PhiT0/4 division value */ + +#define CG_IHOSC_DISABLE ((uint32_t)0x00000000) /*!< Internal high-speed oscillator disable */ +#define CG_IHOSC_ENABLE ((uint32_t)0x00000001) /*!< Internal high-speed oscillator enable */ + +#define CG_IHOSC1EN ((uint32_t)0x00000000) /*!< CG OSCCR bit0 */ + +#define CG_MCKSELGST_MASK ((uint32_t)0x00C00000) /*!< CG MCKSELGST mask */ +#define CG_MCKSELGST_1 ((uint32_t)0x00000000) /*!< CG fsysm fc/PRCK value */ +#define CG_MCKSELGST_2 ((uint32_t)0x00400000) /*!< CG fsysm fc/PRCK/2 value */ +#define CG_MCKSELGST_4 ((uint32_t)0x00800000) /*!< CG fsysm fc/PRCK/4 value */ + + +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_typedef CG Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_fuctions CG Private Fuctions + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_functions CG Exported Functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Update Middle PrescalerClock according register values. + * @param p_obj :CG object. + * @retval Middle PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_fsysm(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + switch (p_obj->p_instance->SYSCR & CG_MCKSELGST_MASK) { + case CG_MCKSELGST_1: /* fsysm -> fc/PRCK */ + result = SystemCoreClock / CG_FSYSM_1_DIV; + break; + case CG_MCKSELGST_2: /* fsysm -> fc/PRCK/2 */ + result = SystemCoreClock / CG_FSYSM_2_DIV; + break; + case CG_MCKSELGST_4: /* fsysm -> fc/PRCK/4 */ + result = SystemCoreClock / CG_FSYSM_4_DIV; + break; + default: + result = 0U; + break; + } + return (result); + +} + +/*--------------------------------------------------*/ +/** + * @brief Update PrescalerClock according register values. + * @param p_obj :CG object. + * @retval PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_phyt0(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + /* Get Gear status. */ + switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) { + case CG_FSYS_1: /* Gear -> fc */ + result = SystemCoreClock * CG_FSYS_1_MUL; + break; + case CG_FSYS_2: /* Gear -> fc/2 */ + result = SystemCoreClock * CG_FSYS_2_MUL; + break; + case CG_FSYS_4: /* Gear -> fc/4 */ + result = SystemCoreClock * CG_FSYS_4_MUL; + break; + case CG_FSYS_8: /* Gear -> fc/8 */ + result = SystemCoreClock * CG_FSYS_8_MUL; + break; + case CG_FSYS_16: /* Gear -> fc/16 */ + result = SystemCoreClock * CG_FSYS_16_MUL; + break; + default: + result = 0U; + break; + } + + switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) { + case CG_PRCKST_1: /* PhiT0 -> fc */ + result /= CG_PRCK_1_DIV; + break; + case CG_PRCKST_2: /* PhiT0 -> fc/2 */ + result /= CG_PRCK_2_DIV; + break; + case CG_PRCKST_4: /* PhiT0 -> fc/4 */ + result /= CG_PRCK_4_DIV; + break; + case CG_PRCKST_8: /* PhiT0 -> fc/8 */ + result /= CG_PRCK_8_DIV; + break; + case CG_PRCKST_16: /* PhiT0 -> fc/16 */ + result /= CG_PRCK_16_DIV; + break; + case CG_PRCKST_32: /* PhiT0 -> fc/32 */ + result /= CG_PRCK_32_DIV; + break; + case CG_PRCKST_64: /* PhiT0 -> fc/64 */ + result /= CG_PRCK_64_DIV; + break; + case CG_PRCKST_128: /* PhiT0 -> fc/128 */ + result /= CG_PRCK_128_DIV; + break; + case CG_PRCKST_256: /* PhiT0 -> fc/256 */ + result /= CG_PRCK_256_DIV; + break; + case CG_PRCKST_512: /* PhiT0 -> fc/512 */ + result /= CG_PRCK_512_DIV; + break; + default: + result = 0U; + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Update Middle PrescalerClock according register values. + * @param p_obj :CG object. + * @retval Middle PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_mphyt0(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + /* Get Gear status. */ + switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) { + case CG_FSYS_1: /* Gear -> fc */ + result = SystemCoreClock * CG_FSYS_1_MUL; + break; + case CG_FSYS_2: /* Gear -> fc/2 */ + result = SystemCoreClock * CG_FSYS_2_MUL; + break; + case CG_FSYS_4: /* Gear -> fc/4 */ + result = SystemCoreClock * CG_FSYS_4_MUL; + break; + case CG_FSYS_8: /* Gear -> fc/8 */ + result = SystemCoreClock * CG_FSYS_8_MUL; + break; + case CG_FSYS_16: /* Gear -> fc/16 */ + result = SystemCoreClock * CG_FSYS_16_MUL; + break; + default: + result = 0U; + break; + } + switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) { + case CG_PRCKST_1: /* PhiT0 -> fc */ + result /= CG_PRCK_1_DIV; + break; + case CG_PRCKST_2: /* PhiT0 -> fc/2 */ + result /= CG_PRCK_2_DIV; + break; + case CG_PRCKST_4: /* PhiT0 -> fc/4 */ + result /= CG_PRCK_4_DIV; + break; + case CG_PRCKST_8: /* PhiT0 -> fc/8 */ + result /= CG_PRCK_8_DIV; + break; + case CG_PRCKST_16: /* PhiT0 -> fc/16 */ + result /= CG_PRCK_16_DIV; + break; + case CG_PRCKST_32: /* PhiT0 -> fc/32 */ + result /= CG_PRCK_32_DIV; + break; + case CG_PRCKST_64: /* PhiT0 -> fc/64 */ + result /= CG_PRCK_64_DIV; + break; + case CG_PRCKST_128: /* PhiT0 -> fc/128 */ + result /= CG_PRCK_128_DIV; + break; + case CG_PRCKST_256: /* PhiT0 -> fc/256 */ + result /= CG_PRCK_256_DIV; + break; + case CG_PRCKST_512: /* PhiT0 -> fc/512 */ + result /= CG_PRCK_512_DIV; + break; + default: + result = 0U; + break; + } + + switch (p_obj->p_instance->SYSCR & CG_MCKSELPST_MASK) { + case CG_MCKSELPST_1: /* PhiT0 -> fc/PRCK */ + result /= CG_FSYSM_1_DIV; + break; + case CG_MCKSELPST_2: /* PhiT0 -> fc/PRCK/2 */ + result /= CG_FSYSM_2_DIV; + break; + case CG_MCKSELPST_4: /* PhiT0 -> fc/PRCK/4 */ + result /= CG_FSYSM_4_DIV; + break; + default: + result = 0U; + break; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Set Internal high-speed oscillator enable. + * @param p_obj :CG object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result cg_ihosc_enable(cg_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* Internal high-speed oscillator is enable. */ + (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR, CG_IHOSC1EN))) = CG_IHOSC_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Set Internal high-speed oscillator disable. + * @param p_obj :CG object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result cg_ihosc_disable(cg_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* Internal high-speed oscillator is disable. */ + (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR, CG_IHOSC1EN))) = CG_IHOSC_DISABLE; + + return (result); +} +/** + * @} + */ /* End of group CG_Exported_functions */ + +/** + * @} + */ /* End of group CG */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__CG_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fc.c new file mode 100644 index 00000000000..e849f1c3226 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fc.c @@ -0,0 +1,695 @@ +/** + ******************************************************************************* + * @file flash512ud32_b.c + * @brief This file provides API functions for FLASH. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include +#include "txz_fc.h" +//#include "txz_sample_def.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @defgroup Flash_Userboot Flash_Userboot Sample Appli + * @{ + */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_macro Flash_Userboot Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group Flash_Userboot_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define + * @{ + */ + +/** + * @} + */ /* End of group Flash_Userboot_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define + * @{ + */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */ +#define FC_MAX_PAGES (uint8_t)(0x20) /*!< Maxmum pages */ +#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */ +#define FC_MAX_AREAS (uint8_t)(0x1) /*!< Maxmum areas */ +#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */ +#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */ +#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */ + +/****************** Changed by TSIP *************************************/ +///* Area Selection All */ +#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL) +#define FC_AREASEL_EXPECT_AREA1 (uint32_t)(0x00000000UL) /*!< RW, Selects expect area1 */ +#define FC_AREASEL_AREA0 (uint32_t)(0x00000007UL) //select Area 0 +#define FC_AREASEL_AREA1 (uint32_t)(0x00000070UL) /*!< RW, Selects area1 */ +#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFF8F0FF8UL) //mask Area 0 +#define FC_AREASEL_MASK_AREA1 (uint32_t)(0xFF8F0F8FUL) /*!< RW, Selects area1 */ +#define FC_AREASEL_WRITEA0_MODE (uint32_t)(0x04000000UL) /*!< R, Write Mode(area0) */ +#define FC_AREASEL_WRITEA1_MODE (uint32_t)(0x08000000UL) /*!< R, Write Mode(area1) */ +static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = { + (0x5E000000UL), /*!< CODE FLASH Page0 */ + (0x5E001000UL), /*!< CODE FLASH Page1 */ + (0x5E002000UL), /*!< CODE FLASH Page2 */ + (0x5E003000UL), /*!< CODE FLASH Page3 */ + (0x5E004000UL), /*!< CODE FLASH Page4 */ + (0x5E005000UL), /*!< CODE FLASH Page5 */ + (0x5E006000UL), /*!< CODE FLASH Page6 */ + (0x5E007000UL), /*!< CODE FLASH Page7 */ + (0x5E008000UL), /*!< CODE FLASH Page8 */ + (0x5E009000UL), /*!< CODE FLASH Page9 */ + (0x5E00A000UL), /*!< CODE FLASH Page10 */ + (0x5E00B000UL), /*!< CODE FLASH Page11 */ + (0x5E00C000UL), /*!< CODE FLASH Page12 */ + (0x5E00D000UL), /*!< CODE FLASH Page13 */ + (0x5E00E000UL), /*!< CODE FLASH Page14 */ + (0x5E00F000UL), /*!< CODE FLASH Page15 */ + (0x5E010000UL), /*!< CODE FLASH Page16 */ + (0x5E011000UL), /*!< CODE FLASH Page17 */ + (0x5E012000UL), /*!< CODE FLASH Page18 */ + (0x5E013000UL), /*!< CODE FLASH Page19 */ + (0x5E014000UL), /*!< CODE FLASH Page20 */ + (0x5E015000UL), /*!< CODE FLASH Page21 */ + (0x5E016000UL), /*!< CODE FLASH Page22 */ + (0x5E017000UL), /*!< CODE FLASH Page23 */ + (0x5E018000UL), /*!< CODE FLASH Page24 */ + (0x5E019000UL), /*!< CODE FLASH Page25 */ + (0x5E01A000UL), /*!< CODE FLASH Page26 */ + (0x5E01B000UL), /*!< CODE FLASH Page27 */ + (0x5E01C000UL), /*!< CODE FLASH Page28 */ + (0x5E01D000UL), /*!< CODE FLASH Page29 */ + (0x5E01E000UL), /*!< CODE FLASH Page30 */ + (0x5E01F000UL) /*!< CODE FLASH Page31 */ +}; + +/** + * @} + */ /* End of group Flash_Userboot_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define + * @{ + */ +/** + * @defgroup Flash_Userboot_Private_typedef Flash_Userboot Private Typedef + * @{ + */ + +/** + * @} + */ /* End of group Flash_Userboot_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_variables Flash_Userboot Private Variables + * @{ + */ +/** + * @} + */ /* End of group Flash_Userboot_Private_variables */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_fuctions Flash_Userboot Private Fuctions + * @{ + */ +__STATIC_INLINE TXZ_Result fc_enable_areasel0(void); +__STATIC_INLINE TXZ_Result fc_disable_areasel0(void); +__STATIC_INLINE TXZ_Result fc_enable_areasel1(void); +__STATIC_INLINE TXZ_Result fc_disable_areasel1(void); +static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +static TXZ_Result fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +static TXZ_Result fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind); +static TXZ_Result fc_blank_check(uint32_t *address, uint32_t size); + +/*--------------------------------------------------*/ +/** + * @brief Enables the AREA0. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_enable_areasel0(void) +{ + TXZ_Result retval = TXZ_ERROR; + + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; + reg |= FC_AREASEL_AREA0; + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->AREASEL = reg; + + /* Confirms the FCAREASEL register the SSF0 was set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA0_MODE) == FC_AREASEL_WRITEA0_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Disables the AREA0. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_disable_areasel0(void) +{ + TXZ_Result retval = TXZ_ERROR; + + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; + reg |= FC_AREASEL_EXPECT_AREA0; + + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->AREASEL = reg; + + /* Confirms the SSF0 of the FCAREASEL register is not set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA0_MODE) != FC_AREASEL_WRITEA0_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + return (retval); +} +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_enable_areasel1(void) +{ + TXZ_Result retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA1; + reg |= FC_AREASEL_AREA1; + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->AREASEL = reg; + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA1_MODE) == FC_AREASEL_WRITEA1_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + return (retval); +} +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_disable_areasel1(void) +{ + TXZ_Result retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA1; + reg |= FC_AREASEL_EXPECT_AREA1; + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->AREASEL = reg; + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA1_MODE) != FC_AREASEL_WRITEA1_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Writes data of the Flash ROM. + * @param uint32_t* : src_address + * @param uint32_t* : dst_address + * @param uint32_t : size + * @return - + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + uint32_t retval1; + uint32_t retval0; + volatile uint32_t *addr1; + volatile uint32_t *addr2; + volatile uint32_t *addr3; + uint32_t *source = (uint32_t *) src_address; + + addr1 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); + addr2 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); + addr3 = (uint32_t *)((uint32_t)dst_address + FC_CODE_FLASH_ADDRESS_TOP); + /* Enables the AREA0. Write Mode. */ + retval0 = fc_enable_areasel0(); + retval1 = fc_enable_areasel1(); + + if ((retval0 == TXZ_SUCCESS) + && (retval1 == TXZ_SUCCESS)) { + uint32_t i; + + *addr1 = (0x000000AAUL); /* bus cycle 1 */ + *addr2 = (0x00000055UL); /* bus cycle 2 */ + *addr1 = (0x000000A0UL); /* bus cycle 3 */ + for (i = (0UL); i < size; i += (0x4UL)) { + *addr3 = *source; + source++; + } + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + }; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) { + }; + } + + /* Disables the AREA0. Read Mode. */ + retval0 = fc_disable_areasel0(); + retval1 = fc_disable_areasel1(); +} + +/*--------------------------------------------------*/ +/** + * @brief Verifies data of the Flash ROM. + * @param uint32_t* : src_address + * @param uint32_t* : dst_address + * @param uint32_t : size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static TXZ_Result fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + TXZ_Result retval = TXZ_ERROR; + int res = memcmp(src_address, dst_address, size); + if (res == 0) { + retval = TXZ_SUCCESS; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auro page erase command of the flash ROM. + * @param uint32_t* flash_top_address : flash top address + * @param uint32_t* erase_top_address : erase top address + * @param fc_erase_kind_t kind : Chip, Area, Block, Page, etc. + * @return - + * @note This function erases specified place of the flash ROM. + */ +/*--------------------------------------------------*/ +//TXZ_Result fc_erase_pages_flash(uint32_t* top_address, uint32_t* erase_top_address) +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static TXZ_Result fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind) +{ + TXZ_Result retval0; + + TXZ_Result retval1; + volatile uint32_t *addr1 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC1_ADDR); + volatile uint32_t *addr2 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC2_ADDR); + + volatile uint32_t *addr3 = (uint32_t *) erase_top_address; + + /* Enables the AREA0. Write Mode. */ + retval0 = fc_enable_areasel0(); + retval1 = fc_enable_areasel1(); + + if ((retval0 == TXZ_SUCCESS) + && (retval1 == TXZ_SUCCESS)) { + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr1 = (0x00000080UL); + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr3 = kind; + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + }; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) { + }; + } + + /* Disables the AREA0. Read Mode. */ + retval0 = fc_disable_areasel0(); + retval1 = fc_disable_areasel1(); +} + +/*--------------------------------------------------*/ +/** + * @brief Checks a blank of the Flash ROM every 4bytes. + * @param uint32_t* : addrress + * @param uint32_t : size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static TXZ_Result fc_blank_check(uint32_t *address, uint32_t size) +{ + TXZ_Result retval = TXZ_SUCCESS; + + uint32_t i; + + for (i = 0; i < (size / sizeof(uint32_t)); i++) { + uint32_t *addr = &address[i]; + if (*addr != FC_BRANK_VALUE) { + retval = TXZ_ERROR; + break; + } + } + + return (retval); +} + +/** + * @} + */ /* End of group Flash_Userboot_Private_fuctions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Exported_functions Flash_Userboot Exported Functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Get the status of the flash auto operation. + * @param fc_sr0_t : status + * @return Result. + * @retval TXZ_BUSY : Busy. + * @retval TXZ_DONE : Done. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_WorkState fc_get_status(fc_sr0_t status) +{ + TXZ_WorkState retval = TXZ_BUSY; + uint32_t work32; + + /* Reads the FCSR0. Masks the other specfic status */ + work32 = TSB_FC->SR0 & (uint32_t)status; + + /* Confirms the specific status of the flash ROM */ + if (work32 == (uint32_t)status) { + retval = TXZ_DONE; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto write command of the code flash ROM. + * @param uint32_t* : src_address + * @param uint32_t* : dst_address + * @param uint32_t : size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function writes 16bytes data to the code Flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_Result fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + TXZ_Result retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + + uint32_t i; + /* Checks the code Flash ROM status */ + for (i = 0; i < size; i += (uint32_t)(0x10UL)) { + /* Writes 16bytes data. */ + fc_write_command((uint32_t *)((uint32_t)src_address + i), (uint32_t *)((uint32_t)dst_address + i), (uint32_t)(0x10UL)); + } + + /* Verifies user data and data of the Flash ROM. */ + retval = fc_verify_check(src_address, dst_address, size); + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auro page erase command of the code flash ROM. + * @param first_page : The first page to erase + * @param num_of_pages : The number of pages to erase. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified page of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages) +{ + TXZ_Result retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum pages. */ + if ((first_page + num_of_pages) <= FC_MAX_PAGES) { + uint8_t i; + for (i = 0; i < num_of_pages ; i++) { + /* Erases the specific page. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_code_flash_address[first_page + i], + FC_ERASE_KIND_PAGE); + } + /* Checks a blank of the specific page. */ + if (fc_blank_check((uint32_t *)fc_const_code_flash_address[first_page], FC_PAGE_SIZE * (uint32_t)num_of_pages) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Checks a blank of the code Flash ROM of specified pages. + * @param first_page : The first page which checks a blank. + * @param last_page : The last page which checks a blank.. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t last_page) +{ + TXZ_Result retval; + + uint32_t *address = (uint32_t *)fc_const_code_flash_address[first_page]; + uint32_t size = ((uint32_t)(last_page - first_page + 1) * (uint32_t)FC_PAGE_SIZE); + + retval = fc_blank_check(address, size); + + return (retval); +} + +/*--------------------------------------------------*/ +/*************** written by TSIP ******************/ +/** + * @brief Erases the entire block of code Flash ROM of specified address. + * @param uint32_t *top_addr : top address of Flash ROM. + * @param uint32_t *blk_addr : start address of block to be erased. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr) +{ + TXZ_Result retval = TXZ_SUCCESS; + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Erases the specific block. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, blk_addr, FC_ERASE_KIND_BLOCK); + /* Checks a blank of the specific block. */ + if (fc_blank_check(blk_addr, (uint32_t)0x8000) == TXZ_ERROR) { + retval = TXZ_ERROR; + } else { + // do nothing + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + + +/** + * @} + */ /* End of group Flash_Userboot_Exported_functions */ + +/** + * @} + */ /* End of group Flash_Userboot */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_flash.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_flash.c new file mode 100644 index 00000000000..a35f254d804 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_flash.c @@ -0,0 +1,219 @@ +/** + ******************************************************************************* + * @file txz_flash.c + * @brief This file provides API functions for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_flash.h" + +#if defined(__FLASH_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FLASH + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_macro FLASH Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_define FLASH Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_define FLASH Private Define + * @{ + */ +/** + * @defgroup wait Configuration + * @brief wait Configuration. + * @{ + */ +/* FC ACCR setting configration */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_ACCR_CODE_7CLK (0x00000006UL) /*!< 7clock(less than 200MHZ). */ +#define FC_ACCR_CODE_6CLK (0x00000005UL) /*!< 6clock(less than 160MHZ). */ +#define FC_ACCR_CODE_5CLK (0x00000004UL) /*!< 5clock(less than 120MHZ). */ +#define FC_ACCR_CODE_4CLK (0x00000003UL) /*!< 4clock(less than 100MHZ). */ +#define FC_ACCR_CODE_3CLK (0x00000002UL) /*!< 3clock(less than 80MHZ). */ +#define FC_ACCR_200MHZ (200000000UL) /*!< 200MHZ */ +#define FC_ACCR_160MHZ (160000000UL) /*!< 160MHZ */ +#define FC_ACCR_120MHZ (120000000UL) /*!< 120MHZ */ +#define FC_ACCR_100MHZ (100000000UL) /*!< 100MHZ */ +#define FC_ACCR_80MHZ ( 80000000UL) /*!< 80MHZ */ + +#define FC_ACCR_DATA (FC_ACCR_DATA_7CLK) +#define FC_ACCR_DATA_7CLK (0x00000600UL) /*!< 7clock(Must). */ + +/** + * @} + */ /* End of group waitConfiguration */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_define FLASH Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_typedef FLASH Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_fuctions FLASH Private Fuctions + * @{ + */ + +/** + * @} + */ /* End of group FLASH_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FLASH_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Raed clock set. + * @param none. + * @retval none. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +void fc_read_clock_set(uint32_t sysclock) +{ + uint32_t regval = 0; + + if (sysclock <= FC_ACCR_80MHZ) { /* less than 80MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_3CLK | FC_ACCR_DATA); + } else if (sysclock <= FC_ACCR_100MHZ) { /* less than 100MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_4CLK | FC_ACCR_DATA); + } else if (sysclock <= FC_ACCR_120MHZ) { /* less than 120MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_5CLK | FC_ACCR_DATA); + } else if (sysclock <= FC_ACCR_160MHZ) { /* less than 160MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_6CLK | FC_ACCR_DATA); + } else if (sysclock <= FC_ACCR_200MHZ) { /* less than 200MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_7CLK | FC_ACCR_DATA); + } + + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->ACCR = regval; + while ((TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_3CLK | FC_ACCR_DATA)) + && (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_4CLK | FC_ACCR_DATA)) + && (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_5CLK | FC_ACCR_DATA)) + && (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_6CLK | FC_ACCR_DATA)) + && (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_7CLK | FC_ACCR_DATA))) { + /* no processing */ + } +} + +/** + * @} + */ /* End of group FLASH_Exported_functions */ + +/** + * @} + */ /* End of group FLASH */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__FLASH_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart.c new file mode 100644 index 00000000000..73d10610ce5 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart.c @@ -0,0 +1,1384 @@ +/** + ******************************************************************************* + * @file txz_fuart.c + * @brief This file provides API functions for FUART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_fuart_include.h" +#include "txz_fuart.h" + +#if defined(__FUART_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FUART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_define FUART Private Define + * @{ + */ + +/** + * @defgroup FUART_BourateConfig Bourate Setting Configuration + * @brief Bourate Setting Configuration. + * @{ + */ +#define FUART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ +#define FUART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ +#define FUART_CFG_GET_BOUDRATE FUART_CFG_GET_BOUDRATE_ENABLE /*!< Disable/Enable Get Bourate Setting */ + +#define FUART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ +#define FUART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ +#define FUART_CFG_GET_BOUDRATE_TYPE FUART_CFG_GET_BOUDRATE_TYPE_ALL /*!< Get Bourate Type Setting */ + +#define FUART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)1) /*!< Error Margin(%). */ +#define FUART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ +/** + * @} + */ /* End of group FUART_BourateConfig */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_define FUART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_define FUART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_typedef FUART Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_fuctions FUART Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); +__STATIC_INLINE int32_t check_param_data_length(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_err_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); +#endif /* #ifdef __DEBUG__ */ +#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) +static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); +#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the CTS Handshake's parameter. + * @param param :CTS Handshake's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_CTSHandshake"UART_CTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_CTS_DISABLE: + case FUART_CTS_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the RTS Handshake's parameter. + * @param param :RTS Handshake's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RTSHandshake"UART_RTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_RTS_DISABLE: + case FUART_RTS_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Stop Bit's parameter. + * @param param :Stop Bit's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_StopBit"UART_STOP_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_STOP_BIT_1: + case FUART_STOP_BIT_2: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_ParityBit"UART_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_PARITY_BIT_ODD: + case FUART_PARITY_BIT_EVEN: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_ParityEnable"UART_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_PARITY_DISABLE: + case FUART_PARITY_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_DataLength"UART_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_length(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_DATA_LENGTH_5: + case FUART_DATA_LENGTH_6: + case FUART_DATA_LENGTH_7: + case FUART_DATA_LENGTH_8: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level Range's parameter. + * @param param :Tx Fill Level Range's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_FIFO_LEVEL_4: + case FUART_FIFO_LEVEL_8: + case FUART_FIFO_LEVEL_16: + case FUART_FIFO_LEVEL_24: + case FUART_FIFO_LEVEL_28: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_FIFO_LEVEL_4: + case FUART_FIFO_LEVEL_8: + case FUART_FIFO_LEVEL_16: + case FUART_FIFO_LEVEL_24: + case FUART_FIFO_LEVEL_28: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_TX_INT_DISABLE: + case FUART_TX_INT_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RxInterrupt"UART_RX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_RX_INT_DISABLE: + case FUART_RX_INT_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrpt's parameter. + * @param param :Error Interrpt's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_err_int(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + param &= ~(FUART_OV_ERR_INT_ENABLE | FUART_BK_ERR_INT_ENABLE | FUART_PA_ERR_INT_ENABLE | FUART_FR_ERR_INT_ENABLE | FUART_TO_ERR_INT_ENABLE); + + if (param == 0) { + result = FUART_PARAM_OK; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Range K's parameter. + * @param param :Range K's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RangeK"UART_RANGE_K_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + /*--- Now, FUART_RANGE_K_MIN is 0. ---*/ +#if 0 + if ((FUART_RANGE_K_MIN <= param) && (param <= FUART_RANGE_K_MAX)) +#else + if (param <= FUART_RANGE_K_MAX) +#endif + { + result = FUART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range N's parameter. + * @param param :Range N's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RangeN"UART_RANGE_N_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + if ((FUART_RANGE_N_MIN <= param) && (param <= FUART_RANGE_N_MAX)) { + result = FUART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for transmit. + * @param param :Num of buff. + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + if (param != 0) { + result = FUART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for receive. + * @param param :Num of buff. + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + if (param != 0) { + result = FUART_PARAM_OK; + } + + return (result); +} +#endif /* #ifdef __DEBUG__ */ + +#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) +/*--------------------------------------------------*/ +/** + * @brief Check the within error margin. + * @param boudrate :Boudrate(bps). + * @param clock :Clock(hz). + * @param boudrate :Boudrate(bps). + * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" + * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" + * @param p_range64 :Error range(after fixed point bit shift). + * @retval TXZ_SUCCESS :Within error margin. + * @retval TXZ_ERROR :Without error margin. + * @note For N+(64-K)/64 division. + */ +/*--------------------------------------------------*/ +static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) +{ + TXZ_Result result = TXZ_ERROR; + uint64_t boud64 = 0; + uint64_t tx64 = 0; + uint64_t work64 = 0; + + /* phi T0 */ + tx64 = (uint64_t)((uint64_t)clock << (FUART_CFG_BOUDRATE_FIXED_POINT_BIT + 2)); + + /* Bourate */ + boud64 = (uint64_t)((uint64_t)boudrate << FUART_CFG_BOUDRATE_FIXED_POINT_BIT); + *p_range64 = ((boud64 / 100) * FUART_CFG_BOUDRATE_ERROR_RANGE); + /* BourateX */ + work64 = (uint64_t)((uint64_t)n << 6); + work64 = (uint64_t)(work64 + (uint64_t)k); + work64 = (tx64 / work64); + if (boud64 >= *p_range64) { + if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) { + if (boud64 < work64) { + *p_range64 = (work64 - boud64); + } else { + *p_range64 = (boud64 - work64); + } + result = TXZ_SUCCESS; + } + } + + return (result); +} +#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ + +/** + * @} + */ /* End of group FUART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the FUART object. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_init(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); + assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); + assert_param(check_param_tx_int(p_obj->init.tx_int.inttx)); + assert_param(check_param_rx_int(p_obj->init.rx_int.intrx)); + assert_param(check_param_err_int(p_obj->init.interr)); + assert_param(check_param_tx_fill_level_range(p_obj->init.tx_int.level)); + assert_param(check_param_rx_fill_level_range(p_obj->init.rx_int.level)); + assert_param(check_param_cts_handshake(p_obj->init.ctse)); + assert_param(check_param_rts_handshake(p_obj->init.rtse)); + assert_param(check_param_stop_bit(p_obj->init.sblen)); + assert_param(check_param_parity_bit(p_obj->init.even)); + assert_param(check_param_parity_enable(p_obj->init.pe)); + assert_param(check_param_data_length(p_obj->init.sm)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable FUART */ + /*------------------------------*/ + p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE | + FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE); + /*------------------------------*/ + /* Interrupt Disable */ + /*------------------------------*/ + p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE | + FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE | + FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR | + FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR | + FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR); + + /*------------------------------*/ + /* FIFO Disable */ + /*------------------------------*/ + p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE); + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + p_obj->p_instance->BRD = p_obj->init.boudrate.brn; + p_obj->p_instance->FBRD = p_obj->init.boudrate.brk; + p_obj->p_instance->LCR_H = (p_obj->init.stpa | p_obj->init.sm | + p_obj->init.fifo | p_obj->init.sblen | + p_obj->init.even | p_obj->init.pe); + p_obj->p_instance->IFLS = ((p_obj->init.rx_int.level << 3) | p_obj->init.tx_int.level); + p_obj->p_instance->IMSC = (p_obj->init.interr | p_obj->init.tx_int.inttx | p_obj->init.rx_int.intrx); + p_obj->p_instance->CR = (p_obj->init.ctse | p_obj->init.rtse | FUARTxCR_UARTEN_ENABLE); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the FUART object. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_deinit(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable FUART */ + /*------------------------------*/ + p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE | + FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE); + /*------------------------------*/ + /* Interrupt Disable */ + /*------------------------------*/ + p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE | + FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE | + FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR | + FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR | + FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR); + /*------------------------------*/ + /* FIFO Disable */ + /*------------------------------*/ + p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_discard_transmit(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + disable_FUARTxCR_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = FUARTxICR_TXIC_CLR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_discard_receive(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + disable_FUARTxCR_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = FUARTxICR_RXIC_CLR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :FUART object. + * @param p_info :The information of transmit data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + assert_param(IS_POINTER_NOT_NULL(p_info->p_data)); + assert_param(check_param_tx_buff_num(p_info->num)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_FUARTxCR_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + p_obj->transmit.info.p_data = p_info->p_data; + p_obj->transmit.info.num = p_info->num; + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + volatile uint32_t fr_reg; + + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET) { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- FUARTxDR ---*/ + if (p_obj->transmit.info.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + break; + } + fr_reg = p_obj->p_instance->FR; + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to TXE(=1). */ + /* Bitband Access. */ + enable_FUARTxCR_TXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :FUART object. + * @param p_info :The information of receive buffer. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref FUART_FifoMax) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + volatile uint8_t dummy; + volatile uint32_t fr_reg; + uint32_t rx_count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + assert_param(IS_POINTER_NOT_NULL(p_info->p_data)); + assert_param(check_param_rx_buff_num(p_info->num)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_FUARTxCR_RXE(p_obj->p_instance); + /* FIFO CLR */ + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR) { + dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); + if (p_obj->init.fifo == 1) { + if (++rx_count > FUART_RX_FIFO_MAX) { + break; + } + } else { + if (++rx_count > 1) { + break; + } + } + fr_reg = p_obj->p_instance->FR; + } + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->receive.wp = 0; + p_obj->receive.info.p_data = p_info->p_data; + p_obj->receive.info.num = p_info->num; + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to RXE(=1). */ + /* Bitband Access. */ + enable_FUARTxCR_RXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_transmit_irq_handler(fuart_t *p_obj) +{ + uint32_t cr_reg; + volatile uint32_t fr_reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current FUARTxCR */ + cr_reg = p_obj->p_instance->CR; + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + if ((cr_reg & FUARTxCR_TXE_MASK) == FUARTxCR_TXE_ENABLE) { + if (p_obj->transmit.info.num <= p_obj->transmit.rp) { + /*=== Transmit Done!! ===*/ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + /* disable_FUARTxCR_TXE(p_obj->p_instance); */ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != FUART_NULL) { + /* Call the transmit handler with TXZ_SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET) { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- FUARTxDR ---*/ + if (p_obj->transmit.info.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + break; + } + fr_reg = p_obj->p_instance->FR; + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_receive_irq_handler(fuart_t *p_obj) +{ + uint32_t cr_reg; + volatile uint32_t fr_reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current FUARTxCR */ + cr_reg = p_obj->p_instance->CR; + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE) { + uint32_t rx_count = 0; + + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR) { + *(p_obj->receive.info.p_data + p_obj->receive.wp) = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); + p_obj->receive.wp += 1; + if (p_obj->receive.wp >= p_obj->receive.info.num) { + break; + } + if (p_obj->init.fifo == 1) { + if (++rx_count >= FUART_RX_FIFO_MAX) { + break; + } + } else { + break; + } + fr_reg = p_obj->p_instance->FR; + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.wp >= p_obj->receive.info.num) { + if (p_obj->receive.handler != FUART_NULL) { + fuart_receive_t param; + param.p_data = p_obj->receive.info.p_data; + param.num = p_obj->receive.wp; + p_obj->receive.wp = 0; + /* Call the receive handler with TXZ_SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_error_irq_handler(fuart_t *p_obj) +{ + uint32_t cr_reg; + uint32_t error; + uint32_t ecr_reg = 0x00; + uint32_t icr_reg = 0x00; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current FUARTxCR */ + cr_reg = p_obj->p_instance->CR; + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current FUARTxRSR. */ + error = p_obj->p_instance->RSR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- FUARTxRSR ---*/ + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* OVER RUN */ + if ((error & FUARTxRSR_OE_MASK) == FUARTxRSR_OE_ERR) { + volatile uint8_t dummy; + + icr_reg |= FUARTxICR_OEIC_CLR; + ecr_reg |= FUARTxECR_OE_CLR; + dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); + err = TXZ_ERROR; + } + /* BREAK */ + if ((error & FUARTxRSR_BE_MASK) == FUARTxRSR_BE_ERR) { + icr_reg |= FUARTxICR_BEIC_CLR; + ecr_reg |= FUARTxECR_BE_CLR; + err = TXZ_ERROR; + } + /* PARITY */ + if ((error & FUARTxRSR_PE_MASK) == FUARTxRSR_PE_ERR) { + icr_reg |= FUARTxICR_PEIC_CLR; + ecr_reg |= FUARTxECR_PE_CLR; + err = TXZ_ERROR; + } + /* FRAMING */ + if ((error & FUARTxRSR_FE_MASK) == FUARTxRSR_FE_ERR) { + icr_reg |= FUARTxICR_FEIC_CLR; + ecr_reg |= FUARTxECR_FE_CLR; + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + p_obj->p_instance->ICR = icr_reg; + p_obj->p_instance->ECR = ecr_reg; + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_FUARTxCR_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != FUART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for timeout error. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_timeout_error_irq_handler(fuart_t *p_obj) +{ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != FUART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL); + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler . + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_irq_handler(fuart_t *p_obj) +{ + uint32_t interrupt_status = p_obj->p_instance->MIS; + if ((interrupt_status & FUARTxMIS_RXMIS_MASK) == FUARTxMIS_RXMIS_REQ) { + p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RXMIS_MASK; + fuart_receive_irq_handler(p_obj); + } + if ((interrupt_status & FUARTxMIS_TXMIS_MASK) == FUARTxMIS_TXMIS_REQ) { + p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_TXMIS_MASK; + fuart_transmit_irq_handler(p_obj); + } + if ((interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK)) != 0) { + p_obj->p_instance->ICR = interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK); + fuart_error_irq_handler(p_obj); + } + if ((interrupt_status & FUARTxMIS_RTMIS_MASK) != 0) { + p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RTMIS_MASK; + fuart_timeout_error_irq_handler(p_obj); + } +} + + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | 31-8 | - | - | + * | 7 | TXFE | Transmit FIFO Empty Flag. | + * | 6 | RXFF | Reach Receive Fill Level Flag. | + * | 5 | TXFF | Reach Transmit Fill Level Flag. | | + * | 4 | RXFE | Receive FIFO Empty Flag. | + * | 3 | BUSY | Transmit BUSY Flag. | + * | 2-1 | - | - | + * | 0 | CTS | FUTxCTS Flag. | + * + * @param p_obj :FUART object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + /*--- FUARTxFR ---*/ + /* Read current FUARTxFR. */ + *p_status = p_obj->p_instance->FR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-4 | - | - | + * | 3 | OVRERR | Overrun Error. Use @ref FUART_OverrunErr. | + * | 2 | PERR | Parity Error. Use @ref FUART_ParityErr. | + * | 1 | FERR | Framing Error. Use @ref FUART_FramingErr. | + * | 0 | BERR | Break Error Flag. Use @ref FUART_BreakErr. | + * + * @param p_obj :FUART object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_error)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Error Read */ + /*------------------------------*/ + /*--- FUARTxRSR ---*/ + /* Read current FUARTxRSR. */ + *p_error = p_obj->p_instance->RSR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get the setting of boudrate. + * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". + * @param boudrate :Boudrate(bps). + * @param p_brd :Save area for Division Setting. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Not support setting. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_brd) +{ + TXZ_Result result = TXZ_ERROR; +#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) + uint64_t tx = 0; + uint64_t work = 0; + uint64_t range64 = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_brd)); + /* Check the parameter of FUARTxCLK. */ +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Calculate Division Setting */ + /*------------------------------*/ + if ((clock > 0) && (boudrate > 0)) { + /*--- phi T0 ---*/ + tx = (uint64_t)((uint64_t)clock << FUART_CFG_BOUDRATE_FIXED_POINT_BIT); + + /*--- N+(K/64) division ---*/ + { + uint8_t k = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + + work = ((uint64_t)boudrate); + tx /= work; + tx >>= 4; + for (k = FUART_RANGE_K_MIN; (k <= FUART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) { + work = tx - (uint64_t)k; + work >>= FUART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ + if ((FUART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= FUART_RANGE_N_MAX)) { + uint64_t workRange = 0; + /* Verification */ + if (verification_boudrate64(clock, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) { +#if (FUART_CFG_GET_BOUDRATE_TYPE == FUART_CFG_GET_BOUDRATE_TYPE_ALL) + /* Compare the previous range. */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + } else { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + result = TXZ_SUCCESS; +#else + /* Finish!! */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + } else { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + result = TXZ_SUCCESS; + loopBreak = TXZ_DONE; +#endif + } + } + } + } + } +#endif /* (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ + + return (result); +} + +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart_ex.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart_ex.c new file mode 100644 index 00000000000..22d0cec108d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart_ex.c @@ -0,0 +1,218 @@ +/** + ******************************************************************************* + * @file txz_fuart_ex.c + * @brief This file provides API functions for FUART driver. + * @brief Extended functionality. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_fuart_include.h" +#include "txz_fuart_ex.h" + +#if defined(__FUART_EX_H) + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_fuctions + * @{ + */ + +/** + * @} + */ /* End of group FUART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Send Break. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_send_break(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Set Break */ + /*------------------------------*/ + { + uint32_t trans = p_obj->p_instance->LCR_H; + + trans &= ~FUARTxLCR_H_BRK_MASK; + trans |= FUARTxLCR_H_BRK_SEND; + p_obj->p_instance->LCR_H = trans; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Stop Break. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_stop_break(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Set Break */ + /*------------------------------*/ + { + uint32_t trans = p_obj->p_instance->LCR_H; + + trans &= ~FUARTxLCR_H_BRK_MASK; + trans |= FUARTxLCR_H_BRK_STOP; + p_obj->p_instance->LCR_H = trans; + } + + return (result); +} + + +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_EX_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_gpio.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_gpio.c new file mode 100644 index 00000000000..74907e1c18e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_gpio.c @@ -0,0 +1,1831 @@ +/** + ******************************************************************************* + * @file txz_gpio.c + * @brief This file provides API functions for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_gpio.h" + +#if defined(__GPIO_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup GPIO + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_define GPIO Private Define + * @{ + */ +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name Bit Operation Macro + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PORT_BASE (0x400E0000UL) /*!< Port Register Base Adress */ +#define BITBAND_PORT_OFFSET (0x0000100UL) /*!< Port Register Offset Value */ +#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (uint32_t)(gr)) ) /*!< Operational target Port Adress */ +#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /*!< Operational target Control Register Adress */ +#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) /*!< Target Pin Bit set */ +#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) /*!< Target Pin Bit clear */ +#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) /*!< Target Pin Bit read */ +/** + * @} + */ /* End of Bit Operation Macro */ +/** + * @} + */ /* End of group GPIO_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_define GPIO Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group GPIO_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_typedef GPIO Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group GPIO_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_fuctions GPIO Private Fuctions + * @{ + */ + +static uint8_t change_mode_to_num(uint32_t mode); +static uint8_t change_func_to_num(uint32_t func); +static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); +static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t func); + +static uint8_t change_mode_to_num(uint32_t mode) +{ + uint8_t retVal = 0; + + if (mode == GPIO_Mode_DATA) { + retVal = GPIO_ModeNum_DATA; + } else if (mode == GPIO_Mode_CR) { + retVal = GPIO_ModeNum_CR; + } else if (mode == GPIO_Mode_FR1) { + retVal = GPIO_ModeNum_FR1; + } else if (mode == GPIO_Mode_FR2) { + retVal = GPIO_ModeNum_FR2; + } else if (mode == GPIO_Mode_FR3) { + retVal = GPIO_ModeNum_FR3; + } else if (mode == GPIO_Mode_FR4) { + retVal = GPIO_ModeNum_FR4; + } else if (mode == GPIO_Mode_FR5) { + retVal = GPIO_ModeNum_FR5; + } else if (mode == GPIO_Mode_FR6) { + retVal = GPIO_ModeNum_FR6; + } else if (mode == GPIO_Mode_FR7) { + retVal = GPIO_ModeNum_FR7; + } else if (mode == GPIO_Mode_FR8) { + retVal = GPIO_ModeNum_FR8; + } else if (mode == GPIO_Mode_OD) { + retVal = GPIO_ModeNum_OD; + } else if (mode == GPIO_Mode_PUP) { + retVal = GPIO_ModeNum_PUP; + } else if (mode == GPIO_Mode_PDN) { + retVal = GPIO_ModeNum_PDN; + } else if (mode == GPIO_Mode_IE) { + retVal = GPIO_ModeNum_IE; + } else { + retVal = GPIO_ModeNum_Max; + } + + return retVal; +} + +static uint8_t change_func_to_num(uint32_t func) +{ + uint8_t retVal = 0; + + if (func == GPIO_FR_1) { + retVal = GPIO_ModeNum_FR1; + } else if (func == GPIO_FR_2) { + retVal = GPIO_ModeNum_FR2; + } else if (func == GPIO_FR_3) { + retVal = GPIO_ModeNum_FR3; + } else if (func == GPIO_FR_4) { + retVal = GPIO_ModeNum_FR4; + } else if (func == GPIO_FR_5) { + retVal = GPIO_ModeNum_FR5; + } else if (func == GPIO_FR_6) { + retVal = GPIO_ModeNum_FR6; + } else if (func == GPIO_FR_7) { + retVal = GPIO_ModeNum_FR7; + } else if (func == GPIO_FR_8) { + retVal = GPIO_ModeNum_FR8; + } else if (func == GPIO_FR_NA) { + retVal = GPIO_ModeNum_CR; + } else if (func == 0) { + retVal = GPIO_ModeNum_CR; + } else { + retVal = GPIO_ModeNum_Max; + } + + return retVal; +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) + * @brief Check the Pin Exist. + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + */ +/*--------------------------------------------------*/ +static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) +{ + int32_t result = PARAM_NG; + uint8_t chgmode; + uint16_t tmp; + + chgmode = change_mode_to_num(mode); + if ((chgmode < GPIO_ModeNum_Max) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) { + tmp = (PinExistTbl[group][num] >> chgmode) & 0x01; + result = PARAM_OK; + if (tmp == 0) { + result = PARAM_NG; + } + } else { + result = PARAM_NG; + } + + return (result); +} +static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t func) +{ + int32_t result = PARAM_NG; + uint8_t chgfunc; + uint16_t tmp; + + chgfunc = change_func_to_num(func); + /* param check skip if func is INPUT or OUTPUT */ + if (chgfunc == GPIO_ModeNum_CR) { + return (PARAM_OK); + } + if ((chgfunc < GPIO_ModeNum_Max) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) { + tmp = (PinExistTbl[group][num] >> chgfunc) & 0x01; + result = PARAM_OK; + if (tmp == 0) { + result = PARAM_NG; + } + } else { + result = PARAM_NG; + } + + return (result); +} +/** + * @} + */ /* End of group GPIO_Private_functions */ + + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup GPIO_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) + * @brief Initialize the GPIO object. + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) +{ + TXZ_Result result = TXZ_SUCCESS; + + /* Check the NULL of address. */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + /* PA Clock Enable */ + PORT_CLOCK_ENABLE_PORTA(TSB_CG_FSYSMENB_IPMENB02); + INIT_GPIO_PORT_A_DATA(p_obj->p_pa_instance->DATA); + INIT_GPIO_PORT_A_CR(p_obj->p_pa_instance->CR); + INIT_GPIO_PORT_A_FR1(p_obj->p_pa_instance->FR1); + INIT_GPIO_PORT_A_FR2(p_obj->p_pa_instance->FR2); + INIT_GPIO_PORT_A_FR3(p_obj->p_pa_instance->FR3); + INIT_GPIO_PORT_A_FR4(p_obj->p_pa_instance->FR4); + INIT_GPIO_PORT_A_FR5(p_obj->p_pa_instance->FR5); + INIT_GPIO_PORT_A_FR6(p_obj->p_pa_instance->FR6); + INIT_GPIO_PORT_A_FR7(p_obj->p_pa_instance->FR7); + INIT_GPIO_PORT_A_FR8(p_obj->p_pa_instance->FR8); + INIT_GPIO_PORT_A_OD(p_obj->p_pa_instance->OD); + INIT_GPIO_PORT_A_PUP(p_obj->p_pa_instance->PUP); + INIT_GPIO_PORT_A_PDN(p_obj->p_pa_instance->PDN); + INIT_GPIO_PORT_A_IE(p_obj->p_pa_instance->IE); + break; + case GPIO_PORT_B: + /* PB Clock Enable */ + PORT_CLOCK_ENABLE_PORTB(TSB_CG_FSYSMENB_IPMENB03); + INIT_GPIO_PORT_B_DATA(p_obj->p_pb_instance->DATA); + INIT_GPIO_PORT_B_CR(p_obj->p_pb_instance->CR); + INIT_GPIO_PORT_B_FR1(p_obj->p_pb_instance->FR1); + INIT_GPIO_PORT_B_FR2(p_obj->p_pb_instance->FR2); + INIT_GPIO_PORT_B_FR3(p_obj->p_pb_instance->FR3); + INIT_GPIO_PORT_B_FR4(p_obj->p_pb_instance->FR4); + INIT_GPIO_PORT_B_FR5(p_obj->p_pb_instance->FR5); + INIT_GPIO_PORT_B_FR6(p_obj->p_pb_instance->FR6); + INIT_GPIO_PORT_B_FR7(p_obj->p_pb_instance->FR7); + INIT_GPIO_PORT_B_FR8(p_obj->p_pb_instance->FR8); + INIT_GPIO_PORT_B_OD(p_obj->p_pb_instance->OD); + INIT_GPIO_PORT_B_PUP(p_obj->p_pb_instance->PUP); + INIT_GPIO_PORT_B_PDN(p_obj->p_pb_instance->PDN); + INIT_GPIO_PORT_B_IE(p_obj->p_pb_instance->IE); + break; + case GPIO_PORT_C: + /* PC Clock Enable */ + PORT_CLOCK_ENABLE_PORTC(TSB_CG_FSYSMENB_IPMENB04); + INIT_GPIO_PORT_C_DATA(p_obj->p_pc_instance->DATA); + INIT_GPIO_PORT_C_CR(p_obj->p_pc_instance->CR); + INIT_GPIO_PORT_C_FR1(p_obj->p_pc_instance->FR1); + INIT_GPIO_PORT_C_FR2(p_obj->p_pc_instance->FR2); + INIT_GPIO_PORT_C_FR3(p_obj->p_pc_instance->FR3); + INIT_GPIO_PORT_C_FR4(p_obj->p_pc_instance->FR4); + INIT_GPIO_PORT_C_FR5(p_obj->p_pc_instance->FR5); + INIT_GPIO_PORT_C_FR6(p_obj->p_pc_instance->FR6); + INIT_GPIO_PORT_C_FR7(p_obj->p_pc_instance->FR7); + INIT_GPIO_PORT_C_FR8(p_obj->p_pc_instance->FR8); + INIT_GPIO_PORT_C_OD(p_obj->p_pc_instance->OD); + INIT_GPIO_PORT_C_PUP(p_obj->p_pc_instance->PUP); + INIT_GPIO_PORT_C_PDN(p_obj->p_pc_instance->PDN); + INIT_GPIO_PORT_C_IE(p_obj->p_pc_instance->IE); + break; + case GPIO_PORT_D: + /* PD Clock Enable */ + PORT_CLOCK_ENABLE_PORTD(TSB_CG_FSYSMENB_IPMENB05); + INIT_GPIO_PORT_D_DATA(p_obj->p_pd_instance->DATA); + INIT_GPIO_PORT_D_CR(p_obj->p_pd_instance->CR); + INIT_GPIO_PORT_D_FR1(p_obj->p_pd_instance->FR1); + INIT_GPIO_PORT_D_FR2(p_obj->p_pd_instance->FR2); + INIT_GPIO_PORT_D_FR3(p_obj->p_pd_instance->FR3); + INIT_GPIO_PORT_D_FR4(p_obj->p_pd_instance->FR4); + INIT_GPIO_PORT_D_FR5(p_obj->p_pd_instance->FR5); + INIT_GPIO_PORT_D_FR6(p_obj->p_pd_instance->FR6); + INIT_GPIO_PORT_D_FR7(p_obj->p_pd_instance->FR7); + INIT_GPIO_PORT_D_FR8(p_obj->p_pd_instance->FR8); + INIT_GPIO_PORT_D_OD(p_obj->p_pd_instance->OD); + INIT_GPIO_PORT_D_PUP(p_obj->p_pd_instance->PUP); + INIT_GPIO_PORT_D_PDN(p_obj->p_pd_instance->PDN); + INIT_GPIO_PORT_D_IE(p_obj->p_pd_instance->IE); + break; + case GPIO_PORT_E: + /* PE Clock Enable */ + PORT_CLOCK_ENABLE_PORTE(TSB_CG_FSYSMENB_IPMENB06); + INIT_GPIO_PORT_E_DATA(p_obj->p_pe_instance->DATA); + INIT_GPIO_PORT_E_CR(p_obj->p_pe_instance->CR); + INIT_GPIO_PORT_E_FR1(p_obj->p_pe_instance->FR1); + INIT_GPIO_PORT_E_FR2(p_obj->p_pe_instance->FR2); + INIT_GPIO_PORT_E_FR3(p_obj->p_pe_instance->FR3); + INIT_GPIO_PORT_E_FR4(p_obj->p_pe_instance->FR4); + INIT_GPIO_PORT_E_FR5(p_obj->p_pe_instance->FR5); + INIT_GPIO_PORT_E_FR6(p_obj->p_pe_instance->FR6); + INIT_GPIO_PORT_E_FR7(p_obj->p_pe_instance->FR7); + INIT_GPIO_PORT_E_FR8(p_obj->p_pe_instance->FR8); + INIT_GPIO_PORT_E_OD(p_obj->p_pe_instance->OD); + INIT_GPIO_PORT_E_PUP(p_obj->p_pe_instance->PUP); + INIT_GPIO_PORT_E_PDN(p_obj->p_pe_instance->PDN); + INIT_GPIO_PORT_E_IE(p_obj->p_pe_instance->IE); + break; + case GPIO_PORT_F: + /* PF Clock Enable */ + PORT_CLOCK_ENABLE_PORTF(TSB_CG_FSYSMENB_IPMENB07); + INIT_GPIO_PORT_F_DATA(p_obj->p_pf_instance->DATA); + INIT_GPIO_PORT_F_CR(p_obj->p_pf_instance->CR); + INIT_GPIO_PORT_F_FR1(p_obj->p_pf_instance->FR1); + INIT_GPIO_PORT_F_FR2(p_obj->p_pf_instance->FR2); + INIT_GPIO_PORT_F_FR3(p_obj->p_pf_instance->FR3); + INIT_GPIO_PORT_F_FR4(p_obj->p_pf_instance->FR4); + INIT_GPIO_PORT_F_FR5(p_obj->p_pf_instance->FR5); + INIT_GPIO_PORT_F_FR6(p_obj->p_pf_instance->FR6); + INIT_GPIO_PORT_F_FR7(p_obj->p_pf_instance->FR7); + INIT_GPIO_PORT_F_FR8(p_obj->p_pf_instance->FR8); + INIT_GPIO_PORT_F_OD(p_obj->p_pf_instance->OD); + INIT_GPIO_PORT_F_PUP(p_obj->p_pf_instance->PUP); + INIT_GPIO_PORT_F_PDN(p_obj->p_pf_instance->PDN); + INIT_GPIO_PORT_F_IE(p_obj->p_pf_instance->IE); + break; + case GPIO_PORT_G: + /* PG Clock Enable */ + PORT_CLOCK_ENABLE_PORTG(TSB_CG_FSYSMENB_IPMENB08); + INIT_GPIO_PORT_G_DATA(p_obj->p_pg_instance->DATA); + INIT_GPIO_PORT_G_CR(p_obj->p_pg_instance->CR); + INIT_GPIO_PORT_G_FR1(p_obj->p_pg_instance->FR1); + INIT_GPIO_PORT_G_FR2(p_obj->p_pg_instance->FR2); + INIT_GPIO_PORT_G_FR3(p_obj->p_pg_instance->FR3); + INIT_GPIO_PORT_G_FR4(p_obj->p_pg_instance->FR4); + INIT_GPIO_PORT_G_FR6(p_obj->p_pg_instance->FR6); + INIT_GPIO_PORT_G_FR5(p_obj->p_pg_instance->FR5); + INIT_GPIO_PORT_G_FR7(p_obj->p_pg_instance->FR7); + INIT_GPIO_PORT_G_FR8(p_obj->p_pg_instance->FR8); + INIT_GPIO_PORT_G_OD(p_obj->p_pg_instance->OD); + INIT_GPIO_PORT_G_PUP(p_obj->p_pg_instance->PUP); + INIT_GPIO_PORT_G_PDN(p_obj->p_pg_instance->PDN); + INIT_GPIO_PORT_G_IE(p_obj->p_pg_instance->IE); + break; + case GPIO_PORT_H: + /* PH Clock Enable */ + PORT_CLOCK_ENABLE_PORTH(TSB_CG_FSYSMENB_IPMENB09); + INIT_GPIO_PORT_H_DATA(p_obj->p_ph_instance->DATA); + INIT_GPIO_PORT_H_CR(p_obj->p_ph_instance->CR); + INIT_GPIO_PORT_H_FR1(p_obj->p_ph_instance->FR1); + INIT_GPIO_PORT_H_FR2(p_obj->p_ph_instance->FR2); + INIT_GPIO_PORT_H_FR3(p_obj->p_ph_instance->FR3); + INIT_GPIO_PORT_H_FR4(p_obj->p_ph_instance->FR4); + INIT_GPIO_PORT_H_FR5(p_obj->p_ph_instance->FR5); + INIT_GPIO_PORT_H_FR6(p_obj->p_ph_instance->FR6); + INIT_GPIO_PORT_H_FR7(p_obj->p_ph_instance->FR7); + INIT_GPIO_PORT_H_FR8(p_obj->p_ph_instance->FR8); + INIT_GPIO_PORT_H_OD(p_obj->p_ph_instance->OD); + INIT_GPIO_PORT_H_PUP(p_obj->p_ph_instance->PUP); + INIT_GPIO_PORT_H_PDN(p_obj->p_ph_instance->PDN); + INIT_GPIO_PORT_H_IE(p_obj->p_ph_instance->IE); + break; + case GPIO_PORT_J: + /* PJ Clock Enable */ + PORT_CLOCK_ENABLE_PORTJ(TSB_CG_FSYSMENB_IPMENB10); + INIT_GPIO_PORT_J_DATA(p_obj->p_pj_instance->DATA); + INIT_GPIO_PORT_J_CR(p_obj->p_pj_instance->CR); + INIT_GPIO_PORT_J_FR1(p_obj->p_pj_instance->FR1); + INIT_GPIO_PORT_J_FR2(p_obj->p_pj_instance->FR2); + INIT_GPIO_PORT_J_FR3(p_obj->p_pj_instance->FR3); + INIT_GPIO_PORT_J_FR4(p_obj->p_pj_instance->FR4); + INIT_GPIO_PORT_J_FR5(p_obj->p_pj_instance->FR5); + INIT_GPIO_PORT_J_FR6(p_obj->p_pj_instance->FR6); + INIT_GPIO_PORT_J_FR7(p_obj->p_pj_instance->FR7); + INIT_GPIO_PORT_J_FR8(p_obj->p_pj_instance->FR8); + INIT_GPIO_PORT_J_OD(p_obj->p_pj_instance->OD); + INIT_GPIO_PORT_J_PUP(p_obj->p_pj_instance->PUP); + INIT_GPIO_PORT_J_PDN(p_obj->p_pj_instance->PDN); + INIT_GPIO_PORT_J_IE(p_obj->p_pj_instance->IE); + break; + case GPIO_PORT_K: + /* PK Clock Enable */ + PORT_CLOCK_ENABLE_PORTK(TSB_CG_FSYSMENB_IPMENB11); + INIT_GPIO_PORT_K_DATA(p_obj->p_pk_instance->DATA); + INIT_GPIO_PORT_K_CR(p_obj->p_pk_instance->CR); + INIT_GPIO_PORT_K_FR1(p_obj->p_pk_instance->FR1); + INIT_GPIO_PORT_K_FR2(p_obj->p_pk_instance->FR2); + INIT_GPIO_PORT_K_FR3(p_obj->p_pk_instance->FR3); + INIT_GPIO_PORT_K_FR4(p_obj->p_pk_instance->FR4); + INIT_GPIO_PORT_K_FR5(p_obj->p_pk_instance->FR5); + INIT_GPIO_PORT_K_FR6(p_obj->p_pk_instance->FR6); + INIT_GPIO_PORT_K_FR7(p_obj->p_pk_instance->FR7); + INIT_GPIO_PORT_K_FR8(p_obj->p_pk_instance->FR8); + INIT_GPIO_PORT_K_OD(p_obj->p_pk_instance->OD); + INIT_GPIO_PORT_K_PUP(p_obj->p_pk_instance->PUP); + INIT_GPIO_PORT_K_PDN(p_obj->p_pk_instance->PDN); + INIT_GPIO_PORT_K_IE(p_obj->p_pk_instance->IE); + break; + case GPIO_PORT_L: + /* PL Clock Enable */ + PORT_CLOCK_ENABLE_PORTL(TSB_CG_FSYSMENB_IPMENB12); + INIT_GPIO_PORT_L_DATA(p_obj->p_pl_instance->DATA); + INIT_GPIO_PORT_L_CR(p_obj->p_pl_instance->CR); + INIT_GPIO_PORT_L_FR1(p_obj->p_pl_instance->FR1); + INIT_GPIO_PORT_L_FR2(p_obj->p_pl_instance->FR2); + INIT_GPIO_PORT_L_FR3(p_obj->p_pl_instance->FR3); + INIT_GPIO_PORT_L_FR4(p_obj->p_pl_instance->FR4); + INIT_GPIO_PORT_L_FR5(p_obj->p_pl_instance->FR5); + INIT_GPIO_PORT_L_FR6(p_obj->p_pl_instance->FR6); + INIT_GPIO_PORT_L_FR7(p_obj->p_pl_instance->FR7); + INIT_GPIO_PORT_L_FR8(p_obj->p_pl_instance->FR8); + INIT_GPIO_PORT_L_OD(p_obj->p_pl_instance->OD); + INIT_GPIO_PORT_L_PUP(p_obj->p_pl_instance->PUP); + INIT_GPIO_PORT_L_PDN(p_obj->p_pl_instance->PDN); + INIT_GPIO_PORT_L_IE(p_obj->p_pl_instance->IE); + break; + case GPIO_PORT_M: + /* PM Clock Enable */ + PORT_CLOCK_ENABLE_PORTM(TSB_CG_FSYSMENB_IPMENB13); + INIT_GPIO_PORT_M_DATA(p_obj->p_pm_instance->DATA); + INIT_GPIO_PORT_M_CR(p_obj->p_pm_instance->CR); + INIT_GPIO_PORT_M_FR1(p_obj->p_pm_instance->FR1); + INIT_GPIO_PORT_M_FR2(p_obj->p_pm_instance->FR2); + INIT_GPIO_PORT_M_FR3(p_obj->p_pm_instance->FR3); + INIT_GPIO_PORT_M_FR4(p_obj->p_pm_instance->FR4); + INIT_GPIO_PORT_M_FR5(p_obj->p_pm_instance->FR5); + INIT_GPIO_PORT_M_FR6(p_obj->p_pm_instance->FR6); + INIT_GPIO_PORT_M_FR7(p_obj->p_pm_instance->FR7); + INIT_GPIO_PORT_M_FR8(p_obj->p_pm_instance->FR8); + INIT_GPIO_PORT_M_OD(p_obj->p_pm_instance->OD); + INIT_GPIO_PORT_M_PUP(p_obj->p_pm_instance->PUP); + INIT_GPIO_PORT_M_PDN(p_obj->p_pm_instance->PDN); + INIT_GPIO_PORT_M_IE(p_obj->p_pm_instance->IE); + break; + case GPIO_PORT_N: + /* PN Clock Enable */ + PORT_CLOCK_ENABLE_PORTN(TSB_CG_FSYSMENB_IPMENB14); + INIT_GPIO_PORT_N_DATA(p_obj->p_pn_instance->DATA); + INIT_GPIO_PORT_N_CR(p_obj->p_pn_instance->CR); + INIT_GPIO_PORT_N_FR1(p_obj->p_pn_instance->FR1); + INIT_GPIO_PORT_N_FR2(p_obj->p_pn_instance->FR2); + INIT_GPIO_PORT_N_FR3(p_obj->p_pn_instance->FR3); + INIT_GPIO_PORT_N_FR4(p_obj->p_pn_instance->FR4); + INIT_GPIO_PORT_N_FR5(p_obj->p_pn_instance->FR5); + INIT_GPIO_PORT_N_FR6(p_obj->p_pn_instance->FR6); + INIT_GPIO_PORT_N_FR7(p_obj->p_pn_instance->FR7); + INIT_GPIO_PORT_N_FR8(p_obj->p_pn_instance->FR8); + INIT_GPIO_PORT_N_OD(p_obj->p_pn_instance->OD); + INIT_GPIO_PORT_N_PUP(p_obj->p_pn_instance->PUP); + INIT_GPIO_PORT_N_PDN(p_obj->p_pn_instance->PDN); + INIT_GPIO_PORT_N_IE(p_obj->p_pn_instance->IE); + break; + case GPIO_PORT_P: + /* PP Clock Enable */ + PORT_CLOCK_ENABLE_PORTP(TSB_CG_FSYSMENB_IPMENB15); + INIT_GPIO_PORT_P_DATA(p_obj->p_pp_instance->DATA); + INIT_GPIO_PORT_P_CR(p_obj->p_pp_instance->CR); + INIT_GPIO_PORT_P_FR1(p_obj->p_pp_instance->FR1); + INIT_GPIO_PORT_P_FR2(p_obj->p_pp_instance->FR2); + INIT_GPIO_PORT_P_FR3(p_obj->p_pp_instance->FR3); + INIT_GPIO_PORT_P_FR4(p_obj->p_pp_instance->FR4); + INIT_GPIO_PORT_P_FR5(p_obj->p_pp_instance->FR5); + INIT_GPIO_PORT_P_FR6(p_obj->p_pp_instance->FR6); + INIT_GPIO_PORT_P_FR7(p_obj->p_pp_instance->FR7); + INIT_GPIO_PORT_P_FR8(p_obj->p_pp_instance->FR8); + INIT_GPIO_PORT_P_OD(p_obj->p_pp_instance->OD); + INIT_GPIO_PORT_P_PUP(p_obj->p_pp_instance->PUP); + INIT_GPIO_PORT_P_PDN(p_obj->p_pp_instance->PDN); + INIT_GPIO_PORT_P_IE(p_obj->p_pp_instance->IE); + break; + case GPIO_PORT_R: + /* PR Clock Enable */ + PORT_CLOCK_ENABLE_PORTR(TSB_CG_FSYSMENB_IPMENB16); + INIT_GPIO_PORT_R_DATA(p_obj->p_pr_instance->DATA); + INIT_GPIO_PORT_R_CR(p_obj->p_pr_instance->CR); + INIT_GPIO_PORT_R_FR1(p_obj->p_pr_instance->FR1); + INIT_GPIO_PORT_R_FR2(p_obj->p_pr_instance->FR2); + INIT_GPIO_PORT_R_FR3(p_obj->p_pr_instance->FR3); + INIT_GPIO_PORT_R_FR4(p_obj->p_pr_instance->FR4); + INIT_GPIO_PORT_R_FR5(p_obj->p_pr_instance->FR5); + INIT_GPIO_PORT_R_FR6(p_obj->p_pr_instance->FR6); + INIT_GPIO_PORT_R_FR7(p_obj->p_pr_instance->FR7); + INIT_GPIO_PORT_R_FR8(p_obj->p_pr_instance->FR8); + INIT_GPIO_PORT_R_OD(p_obj->p_pr_instance->OD); + INIT_GPIO_PORT_R_PUP(p_obj->p_pr_instance->PUP); + INIT_GPIO_PORT_R_PDN(p_obj->p_pr_instance->PDN); + INIT_GPIO_PORT_R_IE(p_obj->p_pr_instance->IE); + break; + case GPIO_PORT_T: + /* PT Clock Enable */ + PORT_CLOCK_ENABLE_PORTT(TSB_CG_FSYSMENB_IPMENB17); + INIT_GPIO_PORT_T_DATA(p_obj->p_pt_instance->DATA); + INIT_GPIO_PORT_T_CR(p_obj->p_pt_instance->CR); + INIT_GPIO_PORT_T_FR1(p_obj->p_pt_instance->FR1); + INIT_GPIO_PORT_T_FR2(p_obj->p_pt_instance->FR2); + INIT_GPIO_PORT_T_FR3(p_obj->p_pt_instance->FR3); + INIT_GPIO_PORT_T_FR4(p_obj->p_pt_instance->FR4); + INIT_GPIO_PORT_T_FR5(p_obj->p_pt_instance->FR5); + INIT_GPIO_PORT_T_FR6(p_obj->p_pt_instance->FR6); + INIT_GPIO_PORT_T_FR7(p_obj->p_pt_instance->FR7); + INIT_GPIO_PORT_T_FR8(p_obj->p_pt_instance->FR8); + INIT_GPIO_PORT_T_OD(p_obj->p_pt_instance->OD); + INIT_GPIO_PORT_T_PUP(p_obj->p_pt_instance->PUP); + INIT_GPIO_PORT_T_PDN(p_obj->p_pt_instance->PDN); + INIT_GPIO_PORT_T_IE(p_obj->p_pt_instance->IE); + break; + case GPIO_PORT_U: + /* PU Clock Enable */ + PORT_CLOCK_ENABLE_PORTU(TSB_CG_FSYSMENB_IPMENB18); + INIT_GPIO_PORT_U_DATA(p_obj->p_pu_instance->DATA); + INIT_GPIO_PORT_U_CR(p_obj->p_pu_instance->CR); + INIT_GPIO_PORT_U_FR1(p_obj->p_pu_instance->FR1); + INIT_GPIO_PORT_U_FR2(p_obj->p_pu_instance->FR2); + INIT_GPIO_PORT_U_FR3(p_obj->p_pu_instance->FR3); + INIT_GPIO_PORT_U_FR4(p_obj->p_pu_instance->FR4); + INIT_GPIO_PORT_U_FR5(p_obj->p_pu_instance->FR5); + INIT_GPIO_PORT_U_FR6(p_obj->p_pu_instance->FR6); + INIT_GPIO_PORT_U_FR7(p_obj->p_pu_instance->FR7); + INIT_GPIO_PORT_U_FR8(p_obj->p_pu_instance->FR8); + INIT_GPIO_PORT_U_OD(p_obj->p_pu_instance->OD); + INIT_GPIO_PORT_U_PUP(p_obj->p_pu_instance->PUP); + INIT_GPIO_PORT_U_PDN(p_obj->p_pu_instance->PDN); + INIT_GPIO_PORT_U_IE(p_obj->p_pu_instance->IE); + break; + case GPIO_PORT_V: + /* PV Clock Enable */ + PORT_CLOCK_ENABLE_PORTV(TSB_CG_FSYSMENB_IPMENB19); + INIT_GPIO_PORT_V_DATA(p_obj->p_pv_instance->DATA); + INIT_GPIO_PORT_V_CR(p_obj->p_pv_instance->CR); + INIT_GPIO_PORT_V_FR1(p_obj->p_pv_instance->FR1); + INIT_GPIO_PORT_V_FR2(p_obj->p_pv_instance->FR2); + INIT_GPIO_PORT_V_FR3(p_obj->p_pv_instance->FR3); + INIT_GPIO_PORT_V_FR4(p_obj->p_pv_instance->FR4); + INIT_GPIO_PORT_V_FR5(p_obj->p_pv_instance->FR5); + INIT_GPIO_PORT_V_FR6(p_obj->p_pv_instance->FR6); + INIT_GPIO_PORT_V_FR7(p_obj->p_pv_instance->FR7); + INIT_GPIO_PORT_V_FR8(p_obj->p_pv_instance->FR8); + INIT_GPIO_PORT_V_OD(p_obj->p_pv_instance->OD); + INIT_GPIO_PORT_V_PUP(p_obj->p_pv_instance->PUP); + INIT_GPIO_PORT_V_PDN(p_obj->p_pv_instance->PDN); + INIT_GPIO_PORT_V_IE(p_obj->p_pv_instance->IE); + break; + case GPIO_PORT_W: + /* PW Clock Enable */ + PORT_CLOCK_ENABLE_PORTW(TSB_CG_FSYSMENB_IPMENB20); + INIT_GPIO_PORT_W_DATA(p_obj->p_pw_instance->DATA); + INIT_GPIO_PORT_W_CR(p_obj->p_pw_instance->CR); + INIT_GPIO_PORT_W_FR1(p_obj->p_pw_instance->FR1); + INIT_GPIO_PORT_W_FR2(p_obj->p_pw_instance->FR2); + INIT_GPIO_PORT_W_FR3(p_obj->p_pw_instance->FR3); + INIT_GPIO_PORT_W_FR4(p_obj->p_pw_instance->FR4); + INIT_GPIO_PORT_W_FR5(p_obj->p_pw_instance->FR5); + INIT_GPIO_PORT_W_FR6(p_obj->p_pw_instance->FR6); + INIT_GPIO_PORT_W_FR7(p_obj->p_pw_instance->FR7); + INIT_GPIO_PORT_W_FR8(p_obj->p_pw_instance->FR8); + INIT_GPIO_PORT_W_OD(p_obj->p_pw_instance->OD); + INIT_GPIO_PORT_W_PUP(p_obj->p_pw_instance->PUP); + INIT_GPIO_PORT_W_PDN(p_obj->p_pw_instance->PDN); + INIT_GPIO_PORT_W_IE(p_obj->p_pw_instance->IE); + break; + case GPIO_PORT_Y: + /* PY Clock Enable */ + PORT_CLOCK_ENABLE_PORTY(TSB_CG_FSYSMENB_IPMENB21); + INIT_GPIO_PORT_Y_DATA(p_obj->p_py_instance->DATA); + INIT_GPIO_PORT_Y_CR(p_obj->p_py_instance->CR); + INIT_GPIO_PORT_Y_FR1(p_obj->p_py_instance->FR1); + INIT_GPIO_PORT_Y_FR2(p_obj->p_py_instance->FR2); + INIT_GPIO_PORT_Y_FR3(p_obj->p_py_instance->FR3); + INIT_GPIO_PORT_Y_FR4(p_obj->p_py_instance->FR4); + INIT_GPIO_PORT_Y_FR5(p_obj->p_py_instance->FR5); + INIT_GPIO_PORT_Y_FR6(p_obj->p_py_instance->FR6); + INIT_GPIO_PORT_Y_FR7(p_obj->p_py_instance->FR7); + INIT_GPIO_PORT_Y_FR8(p_obj->p_py_instance->FR8); + INIT_GPIO_PORT_Y_OD(p_obj->p_py_instance->OD); + INIT_GPIO_PORT_Y_PUP(p_obj->p_py_instance->PUP); + INIT_GPIO_PORT_Y_PDN(p_obj->p_py_instance->PDN); + INIT_GPIO_PORT_Y_IE(p_obj->p_py_instance->IE); + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) + * @brief Release the GPIO object. + * @param p_obj :GPIO object. + * @param group :GPIO Port Group.: Use @ref gpio_gr_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) +{ + TXZ_Result result = TXZ_SUCCESS; + + /* Check the NULL of address. */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + /* Disable the selected GPIO peripheral */ + switch (group) { + case GPIO_PORT_A: + INIT_GPIO_PORT_A_DATA(p_obj->p_pa_instance->DATA); + INIT_GPIO_PORT_A_CR(p_obj->p_pa_instance->CR); + INIT_GPIO_PORT_A_FR1(p_obj->p_pa_instance->FR1); + INIT_GPIO_PORT_A_FR2(p_obj->p_pa_instance->FR2); + INIT_GPIO_PORT_A_FR3(p_obj->p_pa_instance->FR3); + INIT_GPIO_PORT_A_FR4(p_obj->p_pa_instance->FR4); + INIT_GPIO_PORT_A_FR5(p_obj->p_pa_instance->FR5); + INIT_GPIO_PORT_A_FR6(p_obj->p_pa_instance->FR6); + INIT_GPIO_PORT_A_FR7(p_obj->p_pa_instance->FR7); + INIT_GPIO_PORT_A_FR8(p_obj->p_pa_instance->FR8); + INIT_GPIO_PORT_A_OD(p_obj->p_pa_instance->OD); + INIT_GPIO_PORT_A_PUP(p_obj->p_pa_instance->PUP); + INIT_GPIO_PORT_A_PDN(p_obj->p_pa_instance->PDN); + INIT_GPIO_PORT_A_IE(p_obj->p_pa_instance->IE); + /* PA Clock Disable */ + PORT_CLOCK_DISABLE_PORTA(TSB_CG_FSYSMENB_IPMENB02); + break; + case GPIO_PORT_B: + INIT_GPIO_PORT_B_DATA(p_obj->p_pb_instance->DATA); + INIT_GPIO_PORT_B_CR(p_obj->p_pb_instance->CR); + INIT_GPIO_PORT_B_FR1(p_obj->p_pb_instance->FR1); + INIT_GPIO_PORT_B_FR2(p_obj->p_pb_instance->FR2); + INIT_GPIO_PORT_B_FR3(p_obj->p_pb_instance->FR3); + INIT_GPIO_PORT_B_FR4(p_obj->p_pb_instance->FR4); + INIT_GPIO_PORT_B_FR5(p_obj->p_pb_instance->FR5); + INIT_GPIO_PORT_B_FR6(p_obj->p_pb_instance->FR6); + INIT_GPIO_PORT_B_FR7(p_obj->p_pb_instance->FR7); + INIT_GPIO_PORT_B_FR8(p_obj->p_pb_instance->FR8); + INIT_GPIO_PORT_B_OD(p_obj->p_pb_instance->OD); + INIT_GPIO_PORT_B_PUP(p_obj->p_pb_instance->PUP); + INIT_GPIO_PORT_B_PDN(p_obj->p_pb_instance->PDN); + INIT_GPIO_PORT_B_IE(p_obj->p_pb_instance->IE); + /* PB Clock Disable */ + PORT_CLOCK_DISABLE_PORTB(TSB_CG_FSYSMENB_IPMENB03); + break; + case GPIO_PORT_C: + INIT_GPIO_PORT_C_DATA(p_obj->p_pc_instance->DATA); + INIT_GPIO_PORT_C_CR(p_obj->p_pc_instance->CR); + INIT_GPIO_PORT_C_FR1(p_obj->p_pc_instance->FR1); + INIT_GPIO_PORT_C_FR2(p_obj->p_pc_instance->FR2); + INIT_GPIO_PORT_C_FR3(p_obj->p_pc_instance->FR3); + INIT_GPIO_PORT_C_FR4(p_obj->p_pc_instance->FR4); + INIT_GPIO_PORT_C_FR5(p_obj->p_pc_instance->FR5); + INIT_GPIO_PORT_C_FR6(p_obj->p_pc_instance->FR6); + INIT_GPIO_PORT_C_FR7(p_obj->p_pc_instance->FR7); + INIT_GPIO_PORT_C_FR8(p_obj->p_pc_instance->FR8); + INIT_GPIO_PORT_C_OD(p_obj->p_pc_instance->OD); + INIT_GPIO_PORT_C_PUP(p_obj->p_pc_instance->PUP); + INIT_GPIO_PORT_C_PDN(p_obj->p_pc_instance->PDN); + INIT_GPIO_PORT_C_IE(p_obj->p_pc_instance->IE); + /* PC Clock Disable */ + PORT_CLOCK_DISABLE_PORTC(TSB_CG_FSYSMENB_IPMENB04); + break; + case GPIO_PORT_D: + INIT_GPIO_PORT_D_DATA(p_obj->p_pd_instance->DATA); + INIT_GPIO_PORT_D_CR(p_obj->p_pd_instance->CR); + INIT_GPIO_PORT_D_FR1(p_obj->p_pd_instance->FR1); + INIT_GPIO_PORT_D_FR2(p_obj->p_pd_instance->FR2); + INIT_GPIO_PORT_D_FR3(p_obj->p_pd_instance->FR3); + INIT_GPIO_PORT_D_FR4(p_obj->p_pd_instance->FR4); + INIT_GPIO_PORT_D_FR5(p_obj->p_pd_instance->FR5); + INIT_GPIO_PORT_D_FR6(p_obj->p_pd_instance->FR6); + INIT_GPIO_PORT_D_FR7(p_obj->p_pd_instance->FR7); + INIT_GPIO_PORT_D_FR8(p_obj->p_pd_instance->FR8); + INIT_GPIO_PORT_D_OD(p_obj->p_pd_instance->OD); + INIT_GPIO_PORT_D_PUP(p_obj->p_pd_instance->PUP); + INIT_GPIO_PORT_D_PDN(p_obj->p_pd_instance->PDN); + INIT_GPIO_PORT_D_IE(p_obj->p_pd_instance->IE); + /* PD Clock Disable */ + PORT_CLOCK_DISABLE_PORTD(TSB_CG_FSYSMENB_IPMENB05); + break; + case GPIO_PORT_E: + INIT_GPIO_PORT_E_DATA(p_obj->p_pe_instance->DATA); + INIT_GPIO_PORT_E_CR(p_obj->p_pe_instance->CR); + INIT_GPIO_PORT_E_FR1(p_obj->p_pe_instance->FR1); + INIT_GPIO_PORT_E_FR2(p_obj->p_pe_instance->FR2); + INIT_GPIO_PORT_E_FR3(p_obj->p_pe_instance->FR3); + INIT_GPIO_PORT_E_FR4(p_obj->p_pe_instance->FR4); + INIT_GPIO_PORT_E_FR5(p_obj->p_pe_instance->FR5); + INIT_GPIO_PORT_E_FR6(p_obj->p_pe_instance->FR6); + INIT_GPIO_PORT_E_FR7(p_obj->p_pe_instance->FR7); + INIT_GPIO_PORT_E_FR8(p_obj->p_pe_instance->FR8); + INIT_GPIO_PORT_E_OD(p_obj->p_pe_instance->OD); + INIT_GPIO_PORT_E_PUP(p_obj->p_pe_instance->PUP); + INIT_GPIO_PORT_E_PDN(p_obj->p_pe_instance->PDN); + INIT_GPIO_PORT_E_IE(p_obj->p_pe_instance->IE); + /* PE Clock Disable */ + PORT_CLOCK_DISABLE_PORTE(TSB_CG_FSYSMENB_IPMENB06); + break; + case GPIO_PORT_F: + INIT_GPIO_PORT_F_DATA(p_obj->p_pf_instance->DATA); + INIT_GPIO_PORT_F_CR(p_obj->p_pf_instance->CR); + INIT_GPIO_PORT_F_FR1(p_obj->p_pf_instance->FR1); + INIT_GPIO_PORT_F_FR2(p_obj->p_pf_instance->FR2); + INIT_GPIO_PORT_F_FR3(p_obj->p_pf_instance->FR3); + INIT_GPIO_PORT_F_FR4(p_obj->p_pf_instance->FR4); + INIT_GPIO_PORT_F_FR5(p_obj->p_pf_instance->FR5); + INIT_GPIO_PORT_F_FR6(p_obj->p_pf_instance->FR6); + INIT_GPIO_PORT_F_FR7(p_obj->p_pf_instance->FR7); + INIT_GPIO_PORT_F_FR8(p_obj->p_pf_instance->FR8); + INIT_GPIO_PORT_F_OD(p_obj->p_pf_instance->OD); + INIT_GPIO_PORT_F_PUP(p_obj->p_pf_instance->PUP); + INIT_GPIO_PORT_F_PDN(p_obj->p_pf_instance->PDN); + INIT_GPIO_PORT_F_IE(p_obj->p_pf_instance->IE); + /* PF Clock Disable */ + PORT_CLOCK_DISABLE_PORTF(TSB_CG_FSYSMENB_IPMENB07); + break; + case GPIO_PORT_G: + INIT_GPIO_PORT_G_DATA(p_obj->p_pg_instance->DATA); + INIT_GPIO_PORT_G_CR(p_obj->p_pg_instance->CR); + INIT_GPIO_PORT_G_FR1(p_obj->p_pg_instance->FR1); + INIT_GPIO_PORT_G_FR2(p_obj->p_pg_instance->FR2); + INIT_GPIO_PORT_G_FR3(p_obj->p_pg_instance->FR3); + INIT_GPIO_PORT_G_FR4(p_obj->p_pg_instance->FR4); + INIT_GPIO_PORT_G_FR5(p_obj->p_pg_instance->FR5); + INIT_GPIO_PORT_G_FR6(p_obj->p_pg_instance->FR6); + INIT_GPIO_PORT_G_FR7(p_obj->p_pg_instance->FR7); + INIT_GPIO_PORT_G_FR8(p_obj->p_pg_instance->FR8); + INIT_GPIO_PORT_G_OD(p_obj->p_pg_instance->OD); + INIT_GPIO_PORT_G_PUP(p_obj->p_pg_instance->PUP); + INIT_GPIO_PORT_G_PDN(p_obj->p_pg_instance->PDN); + INIT_GPIO_PORT_G_IE(p_obj->p_pg_instance->IE); + /* PG Clock Disable */ + PORT_CLOCK_DISABLE_PORTG(TSB_CG_FSYSMENB_IPMENB08); + break; + case GPIO_PORT_H: + INIT_GPIO_PORT_H_DATA(p_obj->p_ph_instance->DATA); + INIT_GPIO_PORT_H_CR(p_obj->p_ph_instance->CR); + INIT_GPIO_PORT_H_FR1(p_obj->p_ph_instance->FR1); + INIT_GPIO_PORT_H_FR2(p_obj->p_ph_instance->FR2); + INIT_GPIO_PORT_H_FR3(p_obj->p_ph_instance->FR3); + INIT_GPIO_PORT_H_FR4(p_obj->p_ph_instance->FR4); + INIT_GPIO_PORT_H_FR5(p_obj->p_ph_instance->FR5); + INIT_GPIO_PORT_H_FR6(p_obj->p_ph_instance->FR6); + INIT_GPIO_PORT_H_FR7(p_obj->p_ph_instance->FR7); + INIT_GPIO_PORT_H_FR8(p_obj->p_ph_instance->FR8); + INIT_GPIO_PORT_H_OD(p_obj->p_ph_instance->OD); + INIT_GPIO_PORT_H_PUP(p_obj->p_ph_instance->PUP); + INIT_GPIO_PORT_H_PDN(p_obj->p_ph_instance->PDN); + INIT_GPIO_PORT_H_IE(p_obj->p_ph_instance->IE); + /* PH Clock Disable */ + PORT_CLOCK_DISABLE_PORTH(TSB_CG_FSYSMENB_IPMENB09); + break; + case GPIO_PORT_J: + INIT_GPIO_PORT_J_DATA(p_obj->p_pj_instance->DATA); + INIT_GPIO_PORT_J_CR(p_obj->p_pj_instance->CR); + INIT_GPIO_PORT_J_FR1(p_obj->p_pj_instance->FR1); + INIT_GPIO_PORT_J_FR2(p_obj->p_pj_instance->FR2); + INIT_GPIO_PORT_J_FR3(p_obj->p_pj_instance->FR3); + INIT_GPIO_PORT_J_FR4(p_obj->p_pj_instance->FR4); + INIT_GPIO_PORT_J_FR5(p_obj->p_pj_instance->FR5); + INIT_GPIO_PORT_J_FR6(p_obj->p_pj_instance->FR6); + INIT_GPIO_PORT_J_FR7(p_obj->p_pj_instance->FR7); + INIT_GPIO_PORT_J_FR8(p_obj->p_pj_instance->FR8); + INIT_GPIO_PORT_J_OD(p_obj->p_pj_instance->OD); + INIT_GPIO_PORT_J_PUP(p_obj->p_pj_instance->PUP); + INIT_GPIO_PORT_J_PDN(p_obj->p_pj_instance->PDN); + INIT_GPIO_PORT_J_IE(p_obj->p_pj_instance->IE); + /* PJ Clock Disable */ + PORT_CLOCK_DISABLE_PORTJ(TSB_CG_FSYSMENB_IPMENB10); + break; + case GPIO_PORT_K: + INIT_GPIO_PORT_K_DATA(p_obj->p_pk_instance->DATA); + INIT_GPIO_PORT_K_CR(p_obj->p_pk_instance->CR); + INIT_GPIO_PORT_K_FR1(p_obj->p_pk_instance->FR1); + INIT_GPIO_PORT_K_FR2(p_obj->p_pk_instance->FR2); + INIT_GPIO_PORT_K_FR3(p_obj->p_pk_instance->FR3); + INIT_GPIO_PORT_K_FR4(p_obj->p_pk_instance->FR4); + INIT_GPIO_PORT_K_FR5(p_obj->p_pk_instance->FR5); + INIT_GPIO_PORT_K_FR6(p_obj->p_pk_instance->FR6); + INIT_GPIO_PORT_K_FR7(p_obj->p_pk_instance->FR7); + INIT_GPIO_PORT_K_FR8(p_obj->p_pk_instance->FR8); + INIT_GPIO_PORT_K_OD(p_obj->p_pk_instance->OD); + INIT_GPIO_PORT_K_PUP(p_obj->p_pk_instance->PUP); + INIT_GPIO_PORT_K_PDN(p_obj->p_pk_instance->PDN); + INIT_GPIO_PORT_K_IE(p_obj->p_pk_instance->IE); + /* PK Clock Disable */ + PORT_CLOCK_DISABLE_PORTK(TSB_CG_FSYSMENB_IPMENB11); + break; + case GPIO_PORT_L: + INIT_GPIO_PORT_L_DATA(p_obj->p_pl_instance->DATA); + INIT_GPIO_PORT_L_CR(p_obj->p_pl_instance->CR); + INIT_GPIO_PORT_L_FR1(p_obj->p_pl_instance->FR1); + INIT_GPIO_PORT_L_FR2(p_obj->p_pl_instance->FR2); + INIT_GPIO_PORT_L_FR3(p_obj->p_pl_instance->FR3); + INIT_GPIO_PORT_L_FR4(p_obj->p_pl_instance->FR4); + INIT_GPIO_PORT_L_FR5(p_obj->p_pl_instance->FR5); + INIT_GPIO_PORT_L_FR6(p_obj->p_pl_instance->FR6); + INIT_GPIO_PORT_L_FR7(p_obj->p_pl_instance->FR7); + INIT_GPIO_PORT_L_FR8(p_obj->p_pl_instance->FR8); + INIT_GPIO_PORT_L_OD(p_obj->p_pl_instance->OD); + INIT_GPIO_PORT_L_PUP(p_obj->p_pl_instance->PUP); + INIT_GPIO_PORT_L_PDN(p_obj->p_pl_instance->PDN); + INIT_GPIO_PORT_L_IE(p_obj->p_pl_instance->IE); + /* PL Clock Disable */ + PORT_CLOCK_DISABLE_PORTL(TSB_CG_FSYSMENB_IPMENB12); + break; + case GPIO_PORT_M: + INIT_GPIO_PORT_M_DATA(p_obj->p_pm_instance->DATA); + INIT_GPIO_PORT_M_CR(p_obj->p_pm_instance->CR); + INIT_GPIO_PORT_M_FR1(p_obj->p_pm_instance->FR1); + INIT_GPIO_PORT_M_FR2(p_obj->p_pm_instance->FR2); + INIT_GPIO_PORT_M_FR3(p_obj->p_pm_instance->FR3); + INIT_GPIO_PORT_M_FR4(p_obj->p_pm_instance->FR4); + INIT_GPIO_PORT_M_FR5(p_obj->p_pm_instance->FR5); + INIT_GPIO_PORT_M_FR6(p_obj->p_pm_instance->FR6); + INIT_GPIO_PORT_M_FR7(p_obj->p_pm_instance->FR7); + INIT_GPIO_PORT_M_FR8(p_obj->p_pm_instance->FR8); + INIT_GPIO_PORT_M_OD(p_obj->p_pm_instance->OD); + INIT_GPIO_PORT_M_PUP(p_obj->p_pm_instance->PUP); + INIT_GPIO_PORT_M_PDN(p_obj->p_pm_instance->PDN); + INIT_GPIO_PORT_M_IE(p_obj->p_pm_instance->IE); + /* PM Clock Disable */ + PORT_CLOCK_DISABLE_PORTM(TSB_CG_FSYSMENB_IPMENB13); + break; + case GPIO_PORT_N: + INIT_GPIO_PORT_N_DATA(p_obj->p_pn_instance->DATA); + INIT_GPIO_PORT_N_CR(p_obj->p_pn_instance->CR); + INIT_GPIO_PORT_N_FR1(p_obj->p_pn_instance->FR1); + INIT_GPIO_PORT_N_FR2(p_obj->p_pn_instance->FR2); + INIT_GPIO_PORT_N_FR3(p_obj->p_pn_instance->FR3); + INIT_GPIO_PORT_N_FR4(p_obj->p_pn_instance->FR4); + INIT_GPIO_PORT_N_FR5(p_obj->p_pn_instance->FR5); + INIT_GPIO_PORT_N_FR6(p_obj->p_pn_instance->FR6); + INIT_GPIO_PORT_N_FR7(p_obj->p_pn_instance->FR7); + INIT_GPIO_PORT_N_FR8(p_obj->p_pn_instance->FR8); + INIT_GPIO_PORT_N_OD(p_obj->p_pn_instance->OD); + INIT_GPIO_PORT_N_PUP(p_obj->p_pn_instance->PUP); + INIT_GPIO_PORT_N_PDN(p_obj->p_pn_instance->PDN); + INIT_GPIO_PORT_N_IE(p_obj->p_pn_instance->IE); + /* PN Clock Disable */ + PORT_CLOCK_DISABLE_PORTN(TSB_CG_FSYSMENB_IPMENB14); + break; + case GPIO_PORT_P: + INIT_GPIO_PORT_P_DATA(p_obj->p_pp_instance->DATA); + INIT_GPIO_PORT_P_CR(p_obj->p_pp_instance->CR); + INIT_GPIO_PORT_P_FR1(p_obj->p_pp_instance->FR1); + INIT_GPIO_PORT_P_FR2(p_obj->p_pp_instance->FR2); + INIT_GPIO_PORT_P_FR3(p_obj->p_pp_instance->FR3); + INIT_GPIO_PORT_P_FR4(p_obj->p_pp_instance->FR4); + INIT_GPIO_PORT_P_FR5(p_obj->p_pp_instance->FR5); + INIT_GPIO_PORT_P_FR6(p_obj->p_pp_instance->FR6); + INIT_GPIO_PORT_P_FR7(p_obj->p_pp_instance->FR7); + INIT_GPIO_PORT_P_FR8(p_obj->p_pp_instance->FR8); + INIT_GPIO_PORT_P_OD(p_obj->p_pp_instance->OD); + INIT_GPIO_PORT_P_PUP(p_obj->p_pp_instance->PUP); + INIT_GPIO_PORT_P_PDN(p_obj->p_pp_instance->PDN); + INIT_GPIO_PORT_P_IE(p_obj->p_pp_instance->IE); + /* PP Clock Disable */ + PORT_CLOCK_DISABLE_PORTP(TSB_CG_FSYSMENB_IPMENB15); + break; + case GPIO_PORT_R: + INIT_GPIO_PORT_R_DATA(p_obj->p_pr_instance->DATA); + INIT_GPIO_PORT_R_CR(p_obj->p_pr_instance->CR); + INIT_GPIO_PORT_R_FR1(p_obj->p_pr_instance->FR1); + INIT_GPIO_PORT_R_FR2(p_obj->p_pr_instance->FR2); + INIT_GPIO_PORT_R_FR3(p_obj->p_pr_instance->FR3); + INIT_GPIO_PORT_R_FR4(p_obj->p_pr_instance->FR4); + INIT_GPIO_PORT_R_FR5(p_obj->p_pr_instance->FR5); + INIT_GPIO_PORT_R_FR6(p_obj->p_pr_instance->FR6); + INIT_GPIO_PORT_R_FR7(p_obj->p_pr_instance->FR7); + INIT_GPIO_PORT_R_FR8(p_obj->p_pr_instance->FR8); + INIT_GPIO_PORT_R_OD(p_obj->p_pr_instance->OD); + INIT_GPIO_PORT_R_PUP(p_obj->p_pr_instance->PUP); + INIT_GPIO_PORT_R_PDN(p_obj->p_pr_instance->PDN); + INIT_GPIO_PORT_R_IE(p_obj->p_pr_instance->IE); + /* PR Clock Disable */ + PORT_CLOCK_DISABLE_PORTR(TSB_CG_FSYSMENB_IPMENB16); + break; + case GPIO_PORT_T: + INIT_GPIO_PORT_T_DATA(p_obj->p_pt_instance->DATA); + INIT_GPIO_PORT_T_CR(p_obj->p_pt_instance->CR); + INIT_GPIO_PORT_T_FR1(p_obj->p_pt_instance->FR1); + INIT_GPIO_PORT_T_FR2(p_obj->p_pt_instance->FR2); + INIT_GPIO_PORT_T_FR3(p_obj->p_pt_instance->FR3); + INIT_GPIO_PORT_T_FR4(p_obj->p_pt_instance->FR4); + INIT_GPIO_PORT_T_FR5(p_obj->p_pt_instance->FR5); + INIT_GPIO_PORT_T_FR6(p_obj->p_pt_instance->FR6); + INIT_GPIO_PORT_T_FR7(p_obj->p_pt_instance->FR7); + INIT_GPIO_PORT_T_FR8(p_obj->p_pt_instance->FR8); + INIT_GPIO_PORT_T_OD(p_obj->p_pt_instance->OD); + INIT_GPIO_PORT_T_PUP(p_obj->p_pt_instance->PUP); + INIT_GPIO_PORT_T_PDN(p_obj->p_pt_instance->PDN); + INIT_GPIO_PORT_T_IE(p_obj->p_pt_instance->IE); + /* PT Clock Disable */ + PORT_CLOCK_DISABLE_PORTT(TSB_CG_FSYSMENB_IPMENB17); + break; + case GPIO_PORT_U: + INIT_GPIO_PORT_U_DATA(p_obj->p_pu_instance->DATA); + INIT_GPIO_PORT_U_CR(p_obj->p_pu_instance->CR); + INIT_GPIO_PORT_U_FR1(p_obj->p_pu_instance->FR1); + INIT_GPIO_PORT_U_FR2(p_obj->p_pu_instance->FR2); + INIT_GPIO_PORT_U_FR3(p_obj->p_pu_instance->FR3); + INIT_GPIO_PORT_U_FR4(p_obj->p_pu_instance->FR4); + INIT_GPIO_PORT_U_FR5(p_obj->p_pu_instance->FR5); + INIT_GPIO_PORT_U_FR6(p_obj->p_pu_instance->FR6); + INIT_GPIO_PORT_U_FR7(p_obj->p_pu_instance->FR7); + INIT_GPIO_PORT_U_FR8(p_obj->p_pu_instance->FR8); + INIT_GPIO_PORT_U_OD(p_obj->p_pu_instance->OD); + INIT_GPIO_PORT_U_PUP(p_obj->p_pu_instance->PUP); + INIT_GPIO_PORT_U_PDN(p_obj->p_pu_instance->PDN); + INIT_GPIO_PORT_U_IE(p_obj->p_pu_instance->IE); + /* PU Clock Disable */ + PORT_CLOCK_DISABLE_PORTU(TSB_CG_FSYSMENB_IPMENB18); + break; + case GPIO_PORT_V: + INIT_GPIO_PORT_V_DATA(p_obj->p_pv_instance->DATA); + INIT_GPIO_PORT_V_CR(p_obj->p_pv_instance->CR); + INIT_GPIO_PORT_V_FR1(p_obj->p_pv_instance->FR1); + INIT_GPIO_PORT_V_FR2(p_obj->p_pv_instance->FR2); + INIT_GPIO_PORT_V_FR3(p_obj->p_pv_instance->FR3); + INIT_GPIO_PORT_V_FR4(p_obj->p_pv_instance->FR4); + INIT_GPIO_PORT_V_FR5(p_obj->p_pv_instance->FR5); + INIT_GPIO_PORT_V_FR6(p_obj->p_pv_instance->FR6); + INIT_GPIO_PORT_V_FR7(p_obj->p_pv_instance->FR7); + INIT_GPIO_PORT_V_FR8(p_obj->p_pv_instance->FR8); + INIT_GPIO_PORT_V_OD(p_obj->p_pv_instance->OD); + INIT_GPIO_PORT_V_PUP(p_obj->p_pv_instance->PUP); + INIT_GPIO_PORT_V_PDN(p_obj->p_pv_instance->PDN); + INIT_GPIO_PORT_V_IE(p_obj->p_pv_instance->IE); + /* PV Clock Disable */ + PORT_CLOCK_DISABLE_PORTV(TSB_CG_FSYSMENB_IPMENB19); + break; + case GPIO_PORT_W: + INIT_GPIO_PORT_W_DATA(p_obj->p_pw_instance->DATA); + INIT_GPIO_PORT_W_CR(p_obj->p_pw_instance->CR); + INIT_GPIO_PORT_W_FR1(p_obj->p_pw_instance->FR1); + INIT_GPIO_PORT_W_FR2(p_obj->p_pw_instance->FR2); + INIT_GPIO_PORT_W_FR3(p_obj->p_pw_instance->FR3); + INIT_GPIO_PORT_W_FR4(p_obj->p_pw_instance->FR4); + INIT_GPIO_PORT_W_FR5(p_obj->p_pw_instance->FR5); + INIT_GPIO_PORT_W_FR6(p_obj->p_pw_instance->FR6); + INIT_GPIO_PORT_W_FR7(p_obj->p_pw_instance->FR7); + INIT_GPIO_PORT_W_FR8(p_obj->p_pw_instance->FR8); + INIT_GPIO_PORT_W_OD(p_obj->p_pw_instance->OD); + INIT_GPIO_PORT_W_PUP(p_obj->p_pw_instance->PUP); + INIT_GPIO_PORT_W_PDN(p_obj->p_pw_instance->PDN); + INIT_GPIO_PORT_W_IE(p_obj->p_pw_instance->IE); + /* PW Clock Disable */ + PORT_CLOCK_DISABLE_PORTW(TSB_CG_FSYSMENB_IPMENB20); + break; + case GPIO_PORT_Y: + INIT_GPIO_PORT_Y_DATA(p_obj->p_py_instance->DATA); + INIT_GPIO_PORT_Y_CR(p_obj->p_py_instance->CR); + INIT_GPIO_PORT_Y_FR1(p_obj->p_py_instance->FR1); + INIT_GPIO_PORT_Y_FR2(p_obj->p_py_instance->FR2); + INIT_GPIO_PORT_Y_FR3(p_obj->p_py_instance->FR3); + INIT_GPIO_PORT_Y_FR4(p_obj->p_py_instance->FR4); + INIT_GPIO_PORT_Y_FR5(p_obj->p_py_instance->FR5); + INIT_GPIO_PORT_Y_FR6(p_obj->p_py_instance->FR6); + INIT_GPIO_PORT_Y_FR7(p_obj->p_py_instance->FR7); + INIT_GPIO_PORT_Y_FR8(p_obj->p_py_instance->FR8); + INIT_GPIO_PORT_Y_OD(p_obj->p_py_instance->OD); + INIT_GPIO_PORT_Y_PUP(p_obj->p_py_instance->PUP); + INIT_GPIO_PORT_Y_PDN(p_obj->p_py_instance->PDN); + INIT_GPIO_PORT_Y_IE(p_obj->p_py_instance->IE); + /* PY Clock Disable */ + PORT_CLOCK_DISABLE_PORTY(TSB_CG_FSYSMENB_IPMENB21); + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) + * @brief Port Mode Write + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t + * @param[in] val :value + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t i; + int32_t param_result = PARAM_NG; + + /* Check the parameters, the NULL of address */ + for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) { + param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); + if (param_result == PARAM_OK) { + break; + } else { + result = TXZ_ERROR; + } + } + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + WRITE_PORT(mode, p_obj->p_pa_instance, val, PinExistTbl[GPIO_PORT_A][i]); + break; + case GPIO_PORT_B: + WRITE_PORT(mode, p_obj->p_pb_instance, val, PinExistTbl[GPIO_PORT_B][i]); + break; + case GPIO_PORT_C: + WRITE_PORT(mode, p_obj->p_pc_instance, val, PinExistTbl[GPIO_PORT_C][i]); + break; + case GPIO_PORT_D: + WRITE_PORT(mode, p_obj->p_pd_instance, val, PinExistTbl[GPIO_PORT_D][i]); + break; + case GPIO_PORT_E: + WRITE_PORT(mode, p_obj->p_pe_instance, val, PinExistTbl[GPIO_PORT_E][i]); + break; + case GPIO_PORT_F: + WRITE_PORT(mode, p_obj->p_pf_instance, val, PinExistTbl[GPIO_PORT_F][i]); + break; + case GPIO_PORT_G: + WRITE_PORT(mode, p_obj->p_pg_instance, val, PinExistTbl[GPIO_PORT_G][i]); + break; + case GPIO_PORT_H: + WRITE_PORT(mode, p_obj->p_ph_instance, val, PinExistTbl[GPIO_PORT_H][i]); + break; + case GPIO_PORT_J: + WRITE_PORT(mode, p_obj->p_pj_instance, val, PinExistTbl[GPIO_PORT_J][i]); + break; + case GPIO_PORT_K: + WRITE_PORT(mode, p_obj->p_pk_instance, val, PinExistTbl[GPIO_PORT_K][i]); + break; + case GPIO_PORT_L: + WRITE_PORT(mode, p_obj->p_pl_instance, val, PinExistTbl[GPIO_PORT_L][i]); + break; + case GPIO_PORT_M: + WRITE_PORT(mode, p_obj->p_pm_instance, val, PinExistTbl[GPIO_PORT_M][i]); + break; + case GPIO_PORT_N: + WRITE_PORT(mode, p_obj->p_pn_instance, val, PinExistTbl[GPIO_PORT_N][i]); + break; + case GPIO_PORT_P: + WRITE_PORT(mode, p_obj->p_pp_instance, val, PinExistTbl[GPIO_PORT_P][i]); + break; + case GPIO_PORT_R: + WRITE_PORT(mode, p_obj->p_pr_instance, val, PinExistTbl[GPIO_PORT_R][i]); + break; + case GPIO_PORT_T: + WRITE_PORT(mode, p_obj->p_pt_instance, val, PinExistTbl[GPIO_PORT_T][i]); + break; + case GPIO_PORT_U: + WRITE_PORT(mode, p_obj->p_pu_instance, val, PinExistTbl[GPIO_PORT_U][i]); + break; + case GPIO_PORT_V: + WRITE_PORT(mode, p_obj->p_pv_instance, val, PinExistTbl[GPIO_PORT_V][i]); + break; + case GPIO_PORT_W: + WRITE_PORT(mode, p_obj->p_pw_instance, val, PinExistTbl[GPIO_PORT_W][i]); + break; + case GPIO_PORT_Y: + WRITE_PORT(mode, p_obj->p_py_instance, val, PinExistTbl[GPIO_PORT_Y][i]); + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) + * @brief Port Mode Read + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t + * @param[out] val :Store of value + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t param_result = PARAM_NG; + int32_t i; + + /* Check the parameters, the NULL of address */ + for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) { + param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); + if (param_result == PARAM_OK) { + break; + } else { + result = TXZ_ERROR; + } + } + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + READ_PORT(mode, p_obj->p_pa_instance, val, PinExistTbl[GPIO_PORT_A][i]); + break; + case GPIO_PORT_B: + READ_PORT(mode, p_obj->p_pb_instance, val, PinExistTbl[GPIO_PORT_B][i]); + break; + case GPIO_PORT_C: + READ_PORT(mode, p_obj->p_pc_instance, val, PinExistTbl[GPIO_PORT_C][i]); + break; + case GPIO_PORT_D: + READ_PORT(mode, p_obj->p_pd_instance, val, PinExistTbl[GPIO_PORT_D][i]); + break; + case GPIO_PORT_E: + READ_PORT(mode, p_obj->p_pe_instance, val, PinExistTbl[GPIO_PORT_E][i]); + break; + case GPIO_PORT_F: + READ_PORT(mode, p_obj->p_pf_instance, val, PinExistTbl[GPIO_PORT_F][i]); + break; + case GPIO_PORT_G: + READ_PORT(mode, p_obj->p_pg_instance, val, PinExistTbl[GPIO_PORT_G][i]); + break; + case GPIO_PORT_H: + READ_PORT(mode, p_obj->p_ph_instance, val, PinExistTbl[GPIO_PORT_H][i]); + break; + case GPIO_PORT_J: + READ_PORT(mode, p_obj->p_pj_instance, val, PinExistTbl[GPIO_PORT_J][i]); + break; + case GPIO_PORT_K: + READ_PORT(mode, p_obj->p_pk_instance, val, PinExistTbl[GPIO_PORT_K][i]); + break; + case GPIO_PORT_L: + READ_PORT(mode, p_obj->p_pl_instance, val, PinExistTbl[GPIO_PORT_L][i]); + break; + case GPIO_PORT_M: + READ_PORT(mode, p_obj->p_pm_instance, val, PinExistTbl[GPIO_PORT_M][i]); + break; + case GPIO_PORT_N: + READ_PORT(mode, p_obj->p_pn_instance, val, PinExistTbl[GPIO_PORT_N][i]); + break; + case GPIO_PORT_P: + READ_PORT(mode, p_obj->p_pp_instance, val, PinExistTbl[GPIO_PORT_P][i]); + break; + case GPIO_PORT_R: + READ_PORT(mode, p_obj->p_pr_instance, val, PinExistTbl[GPIO_PORT_R][i]); + break; + case GPIO_PORT_T: + READ_PORT(mode, p_obj->p_pt_instance, val, PinExistTbl[GPIO_PORT_T][i]); + break; + case GPIO_PORT_U: + READ_PORT(mode, p_obj->p_pu_instance, val, PinExistTbl[GPIO_PORT_U][i]); + break; + case GPIO_PORT_V: + READ_PORT(mode, p_obj->p_pv_instance, val, PinExistTbl[GPIO_PORT_V][i]); + break; + case GPIO_PORT_W: + READ_PORT(mode, p_obj->p_pw_instance, val, PinExistTbl[GPIO_PORT_W][i]); + break; + case GPIO_PORT_Y: + READ_PORT(mode, p_obj->p_py_instance, val, PinExistTbl[GPIO_PORT_Y][i]); + break; + default: + result = TXZ_ERROR; + break; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/** + * @brief Port Function switching + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param func :GPIO Portxx Func. : Use @ref gpio_pa0_func_t - @ref gpio_pl4_func_t + * @param inout :GPIO Input/Output.: Use @ref gpio_pininout_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + int32_t param_result = PARAM_NG; + + /* Check the parameters, the NULL of address */ + param_result = check_param_func_pin_exist(p_obj, group, num, func); + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + port_base = (uint32_t)p_obj->p_pa_instance; + break; + case GPIO_PORT_B: + port_base = (uint32_t)p_obj->p_pb_instance; + break; + case GPIO_PORT_C: + port_base = (uint32_t)p_obj->p_pc_instance; + break; + case GPIO_PORT_D: + port_base = (uint32_t)p_obj->p_pd_instance; + break; + case GPIO_PORT_E: + port_base = (uint32_t)p_obj->p_pe_instance; + break; + case GPIO_PORT_F: + port_base = (uint32_t)p_obj->p_pf_instance; + break; + case GPIO_PORT_G: + port_base = (uint32_t)p_obj->p_pg_instance; + break; + case GPIO_PORT_H: + port_base = (uint32_t)p_obj->p_ph_instance; + break; + case GPIO_PORT_J: + port_base = (uint32_t)p_obj->p_pj_instance; + break; + case GPIO_PORT_K: + port_base = (uint32_t)p_obj->p_pk_instance; + break; + case GPIO_PORT_L: + port_base = (uint32_t)p_obj->p_pl_instance; + break; + case GPIO_PORT_M: + port_base = (uint32_t)p_obj->p_pm_instance; + break; + case GPIO_PORT_N: + port_base = (uint32_t)p_obj->p_pn_instance; + break; + case GPIO_PORT_P: + port_base = (uint32_t)p_obj->p_pp_instance; + break; + case GPIO_PORT_R: + port_base = (uint32_t)p_obj->p_pr_instance; + break; + case GPIO_PORT_T: + port_base = (uint32_t)p_obj->p_pt_instance; + break; + case GPIO_PORT_U: + port_base = (uint32_t)p_obj->p_pu_instance; + break; + case GPIO_PORT_V: + port_base = (uint32_t)p_obj->p_pv_instance; + break; + case GPIO_PORT_W: + port_base = (uint32_t)p_obj->p_pw_instance; + break; + case GPIO_PORT_Y: + port_base = (uint32_t)p_obj->p_py_instance; + break; + default: + result = TXZ_ERROR; + break; + } + if (result == TXZ_ERROR) { + return (result); + } + + /* Initialization PxFR OFF */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_CLR(mode_base, num); + + /* Initialize Input/Output */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + + switch (func) { + case 0: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_1: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_2: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_3: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_4: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_5: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case GPIO_FR_6: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_7: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_8: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_NA: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Set Pull up mode + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PUP) == PARAM_NG) { + result = TXZ_ERROR; + } else { + port_base = BITBAND_PORT_BASE(group); + + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PUP); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(mode_base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(mode_base, num); + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/** + * @brief Set Pull down mode + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PDN) == PARAM_NG) { + result = TXZ_ERROR; + } else { + port_base = BITBAND_PORT_BASE(group); + + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PDN); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(mode_base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(mode_base, num); + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/** + * @brief Set Open drain mode + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_OD) == PARAM_NG) { + result = TXZ_ERROR; + } else { + port_base = BITBAND_PORT_BASE(group); + + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_OD); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(mode_base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(mode_base, num); + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) + * @brief Port Bit Write + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @param val :GPIO Pin Reset/Set. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t base; + + /* Check the parameters */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) { + result = TXZ_ERROR; + } else { + base = BITBAND_PORT_BASE(group); + base = BITBAND_PORT_MODE_BASE(base, mode); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(base, num); + } else { + result = TXZ_ERROR; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) + * @brief Port Bit Read + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @param[out] *pinstate : store Value of GPIO BitPin. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing.: Use @ref gpio_pinstate_t + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t base; + uint32_t val; + + /* Check the parameters */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) { + result = TXZ_ERROR; + } else { + base = BITBAND_PORT_BASE(group); + base = BITBAND_PORT_MODE_BASE(base, mode); + BITBAND_PORT_READ(val, base, num); + if (val == GPIO_PIN_RESET) { + *pinstate = GPIO_PIN_RESET; + } else if (val == GPIO_PIN_SET) { + *pinstate = GPIO_PIN_SET; + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/** + * @} + */ /* End of group GPIO_Exported_functions */ + +/** + * @} + */ /* End of group GPIO */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__GPIO_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_hal.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_hal.c new file mode 100644 index 00000000000..fda615a9ade --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_hal.c @@ -0,0 +1,297 @@ +/** + ******************************************************************************* + * @file txz_hal.c + * @brief This file provides API functions for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_hal.h" + +#if defined(__HAL_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup HAL + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_macro HAL Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_define HAL Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_define HAL Private Define + * @{ + */ +/** + * @defgroup wait Configuration + * @brief wait Configuration. + * @{ + */ +#define WAIT_UNIT_1US ((uint32_t)(1000000)) /*!< 1S-1us transfor unit. */ +#define WAIT_FORLOOP_STEPS ((uint32_t)(5)) /*!< for loop steps. */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_ACCR_200MHZ (200000000UL) /*!< 200MHZ */ +#define FC_ACCR_160MHZ (160000000UL) /*!< 160MHZ */ +#define FC_ACCR_120MHZ (120000000UL) /*!< 120MHZ */ +#define FC_ACCR_100MHZ (100000000UL) /*!< 100MHZ */ +#define FC_ACCR_80MHZ ( 80000000UL) /*!< 80MHZ */ +/* FC RACCR setting configration */ +#define FC_RACCR_RAMLC_1CLK (0x00000000UL) /*!< 1clock(less than 160MHZ). */ +#define FC_RACCR_RAMLC_2CLK (0x00000010UL) /*!< 2clock(more than 160MHZ). */ + +/** + * @} + */ /* End of group waitConfiguration */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_define HAL Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_typedef HAL Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_fuctions HAL Private Fuctions + * @{ + */ + +static uint32_t tick; + +/** + * @} + */ /* End of group HAL_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup HAL_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Increment a tick value. + * @param - + * @retval - + * @note Please call by user. + * @note In the sample, this variable is incremented each 1ms timer interrupt. + */ +/*--------------------------------------------------*/ +void hal_inc_tick(void) +{ + tick++; +} + +/*--------------------------------------------------*/ +/** + * @brief Provides a tick value. + * @param - + * @return Tick value. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +uint32_t hal_get_tick(void) +{ + return (tick); +} + +/*--------------------------------------------------*/ +/** + * @brief wait Function(us) + * @param uint32_t :count(unit:us). + * @return void + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void wait(uint32_t count) +{ + uint32_t i, steps; + + /*-----------------------------------------*/ + /* step : 1000000us = fsys :1 */ + /* step = EOSC_SYS_CLOCK/1000000 */ + /*-----------------------------------------*/ + /* system core clock update */ + SystemCoreClockUpdate(); + steps = count * (SystemCoreClock / WAIT_UNIT_1US) / WAIT_FORLOOP_STEPS; + + for (i = 0; i < steps; ++i) { + __NOP(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief copy 32-bit data from source to dest + * @param the address of source and dast, the data size + * @retval None. + * @note - + */ +/*--------------------------------------------------*/ +void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size) +{ + uint32_t *dest_addr, *source_addr, tmpsize; + uint32_t i, tmps, tmpd, mask; + + dest_addr = dest; + source_addr = source; + + tmpsize = size >> 2U; + for (i = 0U; i < tmpsize; i++) { /* 32bits copy */ + *dest_addr = *source_addr; + dest_addr++; + source_addr++; + } + if (size & 0x00000003U) { /* if the last data size is not 0(maybe 1,2 or 3), copy the last data */ + mask = 0xFFFFFF00U; + i = size & 0x00000003U; + tmps = *source_addr; + tmpd = *dest_addr; + while (i - 1U) { + mask = mask << 8U; + i--; + } + tmps = tmps & (~mask); + tmpd = tmpd & (mask); + *dest_addr = tmps + tmpd; /* 32bits copy, but only change the bytes need to be changed */ + } else { + /* Do nothing */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief RAM register set. + * @param none. + * @retval none. + * @note - + */ +/*--------------------------------------------------*/ +void fc_ram_con_reg_set(uint32_t sysclock) +{ + uint32_t regval = 0; + + if (sysclock <= FC_ACCR_160MHZ) { /* less than 160MHZ */ + regval = (uint32_t)FC_RACCR_RAMLC_1CLK; + } else { /* more than 160MHZ */ + regval = (uint32_t)FC_RACCR_RAMLC_2CLK; + } + + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->RACCR = regval; + while ((TSB_FC->RACCR != FC_RACCR_RAMLC_1CLK) && (TSB_FC->RACCR != FC_RACCR_RAMLC_2CLK)) { + /* no processing */ + } +} + +/** + * @} + */ /* End of group HAL_Exported_functions */ + +/** + * @} + */ /* End of group HAL */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__HAL_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c.c new file mode 100644 index 00000000000..c48c4f93921 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c.c @@ -0,0 +1,414 @@ +/** + ******************************************************************************* + * @file txz_i2c.c + * @brief This file provides API functions for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_i2c.h" + +#if defined(__I2C_H) + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_variables + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_variables */ + +/*------------------------------------------------------------------------------*/ +/* Const Table */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_const + * @{ + */ +/*----------------------------------*/ +/** + * @brief SCK Divider value table. + * @details SCK = b000 - b111. + * @note NFSEL=0 (Digital Setting) Divider value. +*/ +/*----------------------------------*/ +static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20, 24, 32, 48, 80, 144, 272, 528 }; +static const uint32_t I2C_SCK_LOW_MUL_TBL[8] = { 12, 14, 18, 26, 42, 74, 138, 266 }; + +/** + * @} + */ /* End of group UTILITIES_Private_const */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Initializing I2C Regester + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_init(I2C_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + p_obj->p_instance->CR2 = I2CxCR2_I2CM_ENABLE; + p_obj->p_instance->OP = I2CxOP_INIT; + p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); + p_obj->p_instance->AR = I2CxAR_INIT; + p_obj->p_instance->AR2 = I2CxAR2_INIT; + p_obj->p_instance->CR2 = I2CxCR2_INIT; + p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); + p_obj->p_instance->IE = I2CxIE_CLEAR; +} + +/*--------------------------------------------------*/ +/** + * @brief Generate start condition + * @param p_obj :I2C object. + * @param data :Slave address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_start_condition(I2C_t *p_obj, uint32_t data) +{ + __IO uint32_t opreg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + opreg = p_obj->p_instance->OP; + opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); + if (I2C_master(p_obj)) { + if ((p_obj->p_instance->SR & I2CxSR_BB)) { + opreg |= I2CxOP_SREN; + } + } + p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); + p_obj->p_instance->OP = opreg; + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); + p_obj->p_instance->CR2 = I2CxCR2_START_CONDITION; +} + +/*--------------------------------------------------*/ +/** + * @brief Return the I2c clock setting + * @param p_obj :I2C object. + * @param frequency :Maximum frequency. + * @param fsys :SystemCoreClock. + * @param p_setting :Clock data pointer. + * @retval Non-zero :Scl frequency. + * @retval 0 :Error. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting) +{ + uint32_t result = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_setting)); +#endif /* #ifdef __DEBUG__ */ + + if (frequency <= 1000000) { + uint64_t sck, tmp_sck; + uint64_t prsck, tmp_prsck; + uint64_t fscl, tmp_fscl; + uint64_t fx; + uint64_t max_fx, min_fx; + uint64_t low_width, low_width_min; + + sck = tmp_sck = 0; + prsck = tmp_prsck = 1; + fscl = tmp_fscl = 0; + + if (frequency <= 400000) { + max_fx = 11428572U; /* Tpresck: 87.5ns 1/87.5 = 0.0114285714 */ + min_fx = 6666666U; /* Tpresck:150.0ns 1/150 = 0.0066666667 */ + low_width_min = 1600; + } else { + max_fx = 26666667U; /* Tpresck:37.5ns 1/37.5 = 0.0266666667 */ + min_fx = 15384615U; /* Tpresck:65.0ns 1/65 = 0.0153846154 */ + low_width_min = 675; + } + for (prsck = 1; prsck <= 32; prsck++) { + fx = ((uint64_t)fsys / prsck); + + if ((fx < max_fx) && (fx >= min_fx)) { + for (sck = 0; sck <= 7; sck++) { + low_width = (uint64_t)(1000000000 * prsck * I2C_SCK_LOW_MUL_TBL[sck]) / fsys; + if (low_width < low_width_min) { + continue; + } + fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); + + if ((fscl <= frequency) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + tmp_sck = sck; + tmp_prsck = (prsck < 32) ? prsck : 0; + } + } + } + } + result = (uint32_t)tmp_fscl; + p_setting->sck = (uint32_t)tmp_sck; + p_setting->prsck = (tmp_prsck < 32) ? (uint32_t)tmp_prsck : 0; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Slave mode setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_slave_init(I2C_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->OP = I2CxOP_SLAVE_INIT; + p_obj->p_instance->CR1 = (I2CxCR1_ACK | p_obj->init.clock.sck); + p_obj->p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + p_obj->p_instance->CR2 = I2CxCR2_INIT; + p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); +} +#if defined(I2CSxWUP_EN) +/*--------------------------------------------------*/ +/** + * @brief I2C Wakeup Control setting. + * @param p_obj :I2CS object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_init(I2CS_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->WUPCR1 = (p_obj->init.wup.sgcdi | p_obj->init.wup.ack | p_obj->init.wup.reset | p_obj->init.wup.intend); +} + +/*--------------------------------------------------*/ +/** + * @brief Primary Slave Address setting. + * @param p_obj :I2CS object. + * @param addr :Primary Slave Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->WUPCR2 = (0x0000000E & adr); +} + +/*--------------------------------------------------*/ +/** + * @brief Secondary Slave Address setting. + * @param p_obj :I2CS object. + * @param addr :Secondary Slave Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->WUPCR3 = (0x0000000E & adr); + p_obj->p_instance->WUPCR3 |= 0x00000001; /* WUPSA2EN: Secondary Slave Address Use Setting */ +} +#endif +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#endif /* defined(__I2C_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c_api.c new file mode 100644 index 00000000000..a30079d2b95 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c_api.c @@ -0,0 +1,1721 @@ +/** + ******************************************************************************* + * @file i2c_b.c + * @brief This file provides API functions for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_i2c_api.h" + +#if defined(__BSP_I2C_H) + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define I2C_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define I2C_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name timeout + * @brief This timeouts are not based on accurate values, this just guarantee that + the application will not remain stuck if the I2C communication is corrupted. + * @{ + */ +#define I2C_TIMEOUT (100000) /*>! fail safe. */ + +/** + * @} + */ /* End of name timeout */ + +#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ +#define I2C_CH0 (0) /*!< I2C Channel 0. */ +#define I2C_CH1 (1) /*!< I2C Channel 1. */ +#define I2C_CH2 (2) /*!< I2C Channel 2. */ +#define I2C_CH3 (3) /*!< I2C Channel 3. */ +#define I2C_CH4 (4) /*!< I2C Channel 3. */ +#define I2C_CH_NUM (5) /*!< Number of I2C Channel. */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ +/*----------------------------------*/ +/** + * @brief Transfer State. +*/ +/*----------------------------------*/ +enum { + I2C_TRANSFER_STATE_IDLE = 0U, /*!< Idle. */ + I2C_TRANSFER_STATE_BUSY /*!< Busy. */ +} TransferState; + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief For IRQn_Type number definition. +*/ +/*----------------------------------*/ +typedef struct { + IRQn_Type i2c; + IRQn_Type al; + IRQn_Type bf; + IRQn_Type na; +} i2c_irq_t; + +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_variables + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_variables */ + +/*------------------------------------------------------------------------------*/ +/* Const Table */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_const + * @{ + */ +/*----------------------------------*/ +/** + * @brief Channel 0 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = { + { INTI2C0NST_IRQn, INTI2C0ATX_IRQn, INTI2C0BRX_IRQn, INTI2C0NA_IRQn} +}; + +/*----------------------------------*/ +/** + * @brief Channel 1 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH1_IRQN_TBL[1] = { + { INTI2C1NST_IRQn, INTI2C1ATX_IRQn, INTI2C1BRX_IRQn, INTI2C1NA_IRQn } +}; + +/*----------------------------------*/ +/** + * @brief Channel 2 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH2_IRQN_TBL[1] = { + { INTI2C2NST_IRQn, INTI2C2ATX_IRQn, INTI2C2BRX_IRQn, INTI2C2NA_IRQn} +}; + +/*----------------------------------*/ +/** + * @brief Channel 3 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH3_IRQN_TBL[1] = { + {INTI2C3NST_IRQn, INTI2C3ATX_IRQn, INTI2C3BRX_IRQn, INTI2C3NA_IRQn} +}; + +/*----------------------------------*/ +/** + * @brief Channel 4 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH4_IRQN_TBL[1] = { + { INTI2C4NST_IRQn, INTI2C4ATX_IRQn, INTI2C4BRX_IRQn, INTI2C4NA_IRQn} +}; +/** + * @} + */ /* End of group UTILITIES_Private_const */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +#ifdef DEBUG +__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn); +__STATIC_INLINE int32_t check_param_address(int32_t address); +#endif +__STATIC_INLINE void enable_irq(uint32_t irqn); +__STATIC_INLINE void disable_irq(uint32_t irqn); +__STATIC_INLINE void clear_irq(uint32_t irqn); +__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void reset_asynch(_i2c_t *p_obj); +__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj); +static void i2c_irq_handler(_i2c_t *p_obj); +static void i2c_slave_irq_handler(_i2c_t *p_obj); + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Compare the IRQn's parameter. + * @param irqn :I2C IRQn List. + * @retval I2C_PARAM_OK :Available. + * @retval I2C_PARAM_NG :Not Available. + * @note -. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn) +{ + int32_t result = I2C_PARAM_NG; + + if (irqn == (uint32_t)&I2C_CH0_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH1_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH2_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH3_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH4_IRQN_TBL) { + result = I2C_PARAM_OK; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Compare the Slave address's parameter. + * @param address :Address. + * @retval I2C_PARAM_OK :Available. + * @retval I2C_PARAM_NG :Not Available. + * @note Here, 10bit address has not supported. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_address(int32_t address) +{ + int32_t result = I2C_PARAM_NG; + + if ((address >= 0) && (address <= 255)) { + result = I2C_PARAM_OK; + } + return (result); +} +#endif + +/*--------------------------------------------------*/ +/** + * @brief Enable I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_EnableIRQ(p_irqn->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_DisableIRQ(p_irqn->i2c); + NVIC_DisableIRQ(p_irqn->al); + NVIC_DisableIRQ(p_irqn->bf); + NVIC_DisableIRQ(p_irqn->na); +} + +/*--------------------------------------------------*/ +/** + * @brief ClearPending I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void clear_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_ClearPendingIRQ(p_irqn->i2c); + NVIC_ClearPendingIRQ(p_irqn->al); + NVIC_ClearPendingIRQ(p_irqn->bf); + NVIC_ClearPendingIRQ(p_irqn->na); +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PG2, PG3) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3)) { + /* Port G */ + + /* SCL */ + TSB_PG_IE_PG3IE = 0; /* Input :Disable */ + TSB_PG_CR_PG3C = 0; /* Output :Disable */ + TSB_PG_OD_PG3OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG3UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG3DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG3 = 0; /* Data :0 */ + TSB_PG_FR7_PG3F7 = 1; /* Function :I2C0SCL */ + TSB_PG_IE_PG3IE = 1; /* Input :Enable */ + TSB_PG_CR_PG3C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PG_IE_PG2IE = 0; /* Input :Disable */ + TSB_PG_CR_PG2C = 0; /* Output :Disable */ + TSB_PG_OD_PG2OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG2UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG2DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG2 = 0; /* Data :0 */ + TSB_PG_FR7_PG2F7 = 1; /* Function :I2C0SDA */ + TSB_PG_IE_PG2IE = 1; /* Input :Enable */ + TSB_PG_CR_PG2C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PF2, PF3) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3)) { + /* Port F */ + + /* SCL */ + TSB_PF_IE_PF3IE = 0; /* Input :Disable */ + TSB_PF_CR_PF3C = 0; /* Output :Disable */ + TSB_PF_OD_PF3OD = 1; /* OD Control :Open Drain */ + TSB_PF_PUP_PF3UP = 0; /* Pull-up :Disable */ + TSB_PF_PDN_PF3DN = 0; /* Pull-down :Disable */ + TSB_PF_DATA_PF3 = 0; /* Data :0 */ + TSB_PF_FR7_PF3F7 = 1; /* Function :I2C0SCL */ + TSB_PF_IE_PF3IE = 1; /* Input :Enable */ + TSB_PF_CR_PF3C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PF_IE_PF2IE = 0; /* Input :Disable */ + TSB_PF_CR_PF2C = 0; /* Output :Disable */ + TSB_PF_OD_PF2OD = 1; /* OD Control :Open Drain */ + TSB_PF_PUP_PF2UP = 0; /* Pull-up :Disable */ + TSB_PF_PDN_PF2DN = 0; /* Pull-down :Disable */ + TSB_PF_DATA_PF2 = 0; /* Data :0 */ + TSB_PF_FR7_PF2F7 = 1; /* Function :I2C0SDA */ + TSB_PF_IE_PF2IE = 1; /* Input :Enable */ + TSB_PF_CR_PF2C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PG4, PG5) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5)) { + /* Port G */ + + /* SCL */ + TSB_PG_IE_PG5IE = 0; /* Input :Disable */ + TSB_PG_CR_PG5C = 0; /* Output :Disable */ + TSB_PG_OD_PG5OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG5UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG5DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG5 = 0; /* Data :0 */ + TSB_PG_FR7_PG5F7 = 1; /* Function :I2C0SCL */ + TSB_PG_IE_PG5IE = 1; /* Input :Enable */ + TSB_PG_CR_PG5C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PG_IE_PG4IE = 0; /* Input :Disable */ + TSB_PG_CR_PG4C = 0; /* Output :Disable */ + TSB_PG_OD_PG4OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG4UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG4DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG4 = 0; /* Data :0 */ + TSB_PG_FR7_PG4F7 = 1; /* Function :I2C0SDA */ + TSB_PG_IE_PG4IE = 1; /* Input :Enable */ + TSB_PG_CR_PG4C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PM0, PM1) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7)) { + /* Port M */ + + /* SCL */ + TSB_PJ_IE_PJ6IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ6C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ6OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ6UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ6DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ6 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ6F7 = 1; /* Function :I2C3SCL */ + TSB_PJ_IE_PJ6IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ6C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PJ_IE_PJ7IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ7C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ7OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ7UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ7DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ7 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ7F7 = 1; /* Function :I2C3SDA */ + TSB_PJ_IE_PJ7IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ7C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PM6, PM7) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3)) { + /* Port M */ + + /* SCL */ + TSB_PJ_IE_PJ2IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ2C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ2OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ2UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ2DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ2 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ2F7 = 1; /* Function :I2C3SCL */ + TSB_PJ_IE_PJ2IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ2C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PJ_IE_PJ3IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ3C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ3OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ3UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ3DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ3 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ3F7 = 1; /* Function :I2C3SDA */ + TSB_PJ_IE_PJ3IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ3C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Setting + * @param ch :I2C Channel. + * @param p_irqn :Destination Address of a I2C IRQn List. + * @retval non-zero :Instance Address. + * @retval zero :Channel not supported. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn) +{ + uint32_t instance = 0; + + switch (ch) { + case I2C_CH0: + instance = (uint32_t)TSB_I2C0; + *p_irqn = (uint32_t)&I2C_CH0_IRQN_TBL; + break; + + case I2C_CH1: + instance = (uint32_t)TSB_I2C1; + *p_irqn = (uint32_t)&I2C_CH1_IRQN_TBL; + break; + + case I2C_CH2: + instance = (uint32_t)TSB_I2C2; + *p_irqn = (uint32_t)&I2C_CH2_IRQN_TBL; + break; + + case I2C_CH3: + instance = (uint32_t)TSB_I2C3; + *p_irqn = (uint32_t)&I2C_CH3_IRQN_TBL; + break; + + case I2C_CH4: + instance = (uint32_t)TSB_I2C4; + *p_irqn = (uint32_t)&I2C_CH4_IRQN_TBL; + break; + + default: + break; + } + return (instance); +} + +/*--------------------------------------------------*/ +/** + * @brief Reset Asynch Transfer + * @param p_obj :i2c object + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void reset_asynch(_i2c_t *p_obj) +{ + disable_irq(p_obj->info.irqn); + I2C_disable_interrupt(&p_obj->i2c); +} + +__STATIC_INLINE int32_t I2C_status_arbitration(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); +#endif +} +/*--------------------------------------------------*/ +/** + * @brief Waiting i2c status + * @param p_obj :i2c object + * @retval 0 :Success. + * @retval -1 :Failure. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj) +{ + int32_t timeout; + + timeout = I2C_TIMEOUT; + while (!I2C_int_status(&p_obj->i2c)) { + if (I2C_status_arbitration(&p_obj->i2c)) { + volatile uint32_t dummy = 0; + dummy = I2C_read_data(&p_obj->i2c); + (void)dummy; + return (-5); + } + if ((timeout--) == 0) { + return (-1); + } + } + if (I2C_status_arbitration(&p_obj->i2c)) { + volatile uint32_t dummy = 0; + dummy = I2C_read_data(&p_obj->i2c); + (void)dummy; + return (-5); + } + return (0); +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Transfer handler + * @param p_obj :i2c object. + * @retval - + * @note Called by i2c_irq_handler_asynch_t. + */ +/*--------------------------------------------------*/ +static void i2c_irq_handler(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + + if ((!I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) { + p_obj->info.asynch.event = I2C_EVENT_ERROR; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + if (I2C_transmitter(&p_obj->i2c)) { + int32_t start = I2C_restart(&p_obj->i2c); + (void)start; + + if (!I2C_get_ack(&p_obj->i2c)) { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); + } else if (p_obj->rx_buff.length != 0) { + I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U)); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if ((p_obj->tx_buff.pos < p_obj->tx_buff.length) || (p_obj->tx_buff.length == 0)) { + if (p_obj->tx_buff.pos == 0) { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else if (p_obj->rx_buff.length != 0) { + I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U)); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } else { + int32_t start = I2C_restart(&p_obj->i2c); + + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + if (!start) { + p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + } + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1) ? 0 : 1))); + I2C_write_data(&p_obj->i2c, 0); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Transfer handler + * @param p_obj :i2c object. + * @retval - + * @note Called by i2c_slave_irq_handler_asynch_t. + */ +/*--------------------------------------------------*/ +static void i2c_slave_irq_handler(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + + if ((I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) { + p_obj->info.asynch.event = I2C_EVENT_ERROR; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + int32_t start = I2C_slave_detected(&p_obj->i2c); + if (start) { + uint8_t sa = (uint8_t)I2C_read_data(&p_obj->i2c); + (void)sa; + } + if (I2C_transmitter(&p_obj->i2c)) { + if (!I2C_get_ack(&p_obj->i2c)) { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); + } else { + /* dummy, wait nack */ + I2C_write_data(&p_obj->i2c, 0); + } + } else { + /* error event not be set */ + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + if (!start) { + p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + } + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1) ? 0 : 1))); + I2C_write_data(&p_obj->i2c, 0); + } else { + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + I2C_slave_init(&p_obj->i2c); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Enable I2C IRQ + * @param p_obj :i2c object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void i2c_enable_irq(_i2c_t *p_obj) +{ + enable_irq(p_obj->info.irqn); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable I2C IRQ + * @param p_obj :i2c object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void i2c_disable_irq(_i2c_t *p_obj) +{ + disable_irq(p_obj->info.irqn); +} + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Initialize the I2C Driver + * @param p_obj :i2c object. + * @param sda :SDA port. + * @param scl :SCL port. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl) +{ + TXZ_Result result = TXZ_ERROR; + uint32_t instance = 0; + uint32_t irqn = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + /* ch0 */ + if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3)) { + set_port_ch0(sda, scl); + instance = set_i2c(I2C_CH0, &irqn); + } + /* ch1 */ + if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3)) { + set_port_ch1(sda, scl); + instance = set_i2c(I2C_CH1, &irqn); + } + /* ch2 */ + if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5)) { + set_port_ch2(sda, scl); + instance = set_i2c(I2C_CH2, &irqn); + } + /* ch3 */ + if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7)) { + set_port_ch3(sda, scl); + instance = set_i2c(I2C_CH3, &irqn); + } + /* ch4 */ + if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3)) { + set_port_ch4(sda, scl); + instance = set_i2c(I2C_CH3, &irqn); + } + + if ((instance != 0) && (irqn != 0)) { + disable_irq(irqn); + clear_irq(irqn); + + /* Set irqn table */ + p_obj->info.irqn = irqn; + + /* Set instance */ + p_obj->i2c.p_instance = (TSB_I2C_TypeDef *)instance; + + /* I2C Reset */ + i2c_reset_t(p_obj); + + /* Set Frequency Default at 100KHz */ + if (i2c_frequency_t(p_obj, 100000) == TXZ_SUCCESS) { + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Reset I2C peripheral + * @param p_obj :i2c object. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_reset_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + /* Software reset */ + I2C_reset(&p_obj->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure the I2C frequency + * @param p_obj :i2c object. + * @param hz :frequency in Hz. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_port_high(&p_obj->i2c)) { + uint32_t fval; + + SystemCoreClockUpdate(); + + fval = I2C_get_clock_setting(&p_obj->i2c, (uint32_t)hz, SystemCoreClock, &p_obj->i2c.init.clock); + if (fval != 0) { + //I2C_init(&p_obj->i2c); + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + p_obj->info.asynch.address = 0; + p_obj->info.asynch.stop = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + p_obj->info.asynch.event = 0; + p_obj->tx_buff.p_buffer = I2C_NULL; + p_obj->tx_buff.length = 0; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = I2C_NULL; + p_obj->rx_buff.length = 0; + p_obj->rx_buff.pos = 0; + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check bus free on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + p_obj->info.bus_free = 1; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Creates a start condition on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure.(now, not use) + * @note Start condition is not generate yet, after this function returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_start_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + p_obj->info.start = 1; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Creates a stop condition on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_stop_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t timeout; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_stop_condition(&p_obj->i2c); + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + + timeout = I2C_TIMEOUT; + while (i2c_active_t(p_obj)) { + if ((timeout--) == 0) { + result = TXZ_ERROR; + break; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking reading data + * @param p_obj :i2c object. + * @param address :Slave address(7-bit) and last bit is 0. + * @param p_data :Address of Read data. + * @param length :Number of the bytes to read. + * @param stop :Stop to be generated after the transfer is done. + * @retval Number of read bytes. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) +{ + int32_t result = 0; + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + if (length > 0) { + /* Start Condition */ + if (i2c_start_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + result = i2c_byte_write_t(p_obj, (int32_t)((uint32_t)address | 1U)); + if (result == I2C_ACK) { + /* Read all bytes */ + while (count < length) { + int32_t data = i2c_byte_read_t(p_obj, ((count < (length - 1)) ? 0 : 1)); + if (data < 0) { + result = data; + break; + } + p_data[count++] = (uint8_t)data; + } + result = count; + } else if (result == I2C_ERROR_ARBITRATION) { + } else if (result == (-2)) { //I2C_ERROR_BUS_BUSY + } else { + stop = 1; + result = (-1) ;//I2C_ERROR_NO_SLAVE; + } + /* Stop Condition */ + if (stop) { + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking sending data + * @param p_obj :i2c object. + * @param address :Slave address(7-bit) and last bit is 0. + * @param p_data :Destination address of Write data. + * @param length :Number of the bytes to write. + * @param stop :Stop to be generated after the transfer is done. + * @retval Number of write bytes. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) +{ + int32_t result = 0; + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + /* Start Condition */ + if (i2c_start_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + result = i2c_byte_write_t(p_obj, address); + if (result == I2C_ACK) { + /* Write all bytes */ + while (count < length) { + int32_t data = i2c_byte_write_t(p_obj, (int32_t)p_data[count++]); + if (data < I2C_ACK) { + result = data; + break; + } + } + if (result >= 0) { + result = count; + } + } else if (result == I2C_ERROR_ARBITRATION) { + } else if (result == (-2)) { //I2C_ERROR_BUS_BUSY + } else { + stop = 1; + result = (-1); //I2C_ERROR_NO_SLAVE; + } + /* Stop Condition */ + if (stop) { + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Read one byte + * @param p_obj :i2c object. + * @param last :last acknowledge. + * @retval The read byte (but -1 is timout error). + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last) +{ + int32_t result; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + I2C_set_ack(&p_obj->i2c, last); + I2C_write_data(&p_obj->i2c, 0); + result = wait_status(p_obj); + if (result < 0) { + // result = -1; + } else { + result = (int32_t)I2C_read_data(&p_obj->i2c); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Write one byte + * @param p_obj :i2c object. + * @param data :Write data. + * @retval 0 :NACK was received. + * @retval 1 :ACK was received. + * @retval -1 :Timout error. + * @note Macro definition of return values is @ref I2C_ACK. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data) +{ + int32_t result; + int32_t timeout; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + if (p_obj->info.start == 1) { + p_obj->info.start = 0; + if (p_obj->info.bus_free == 1) { + timeout = I2C_TIMEOUT; + while (i2c_active_t(p_obj)) { + if ((timeout--) == 0) { + p_obj->info.bus_free = 0; + return (-1); + } + } + } + /* Start Condition */ + I2C_start_condition(&p_obj->i2c, (uint32_t)data); + if ((p_obj->info.bus_free == 1) && (!I2C_master(&p_obj->i2c))) { + p_obj->i2c.p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + p_obj->info.bus_free = 0; + if (I2C_status_arbitration(&p_obj->i2c)) { + return (-5); + } + return (-2); + } + } else { + I2C_write_data(&p_obj->i2c, (uint32_t)data); + } + p_obj->info.bus_free = 0; + result = wait_status(p_obj); + if (result < 0) { + return (result); + } + if (!I2C_get_ack(&p_obj->i2c)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Attempts to determine if the I2C bus is already in use + * @param p_obj :i2c object. + * @retval 0 :Non-active. + * @retval 1 :Active. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint8_t i2c_active_t(_i2c_t *p_obj) +{ + uint8_t result; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_status_busy(&p_obj->i2c)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Start I2C asynchronous transfer + * @param p_obj :i2c object. + * @param p_tx :Buffer of write data. + * @param tx_length :Length of write data. + * @param p_rx :Buffer of read data. + * @param rx_length :Length of read data. + * @param address :Slave address(7-bit) and last bit is 0. + * @param stop :Stop to be generated after the transfer is done. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Master and non-blocking function. + * @note Events of this function will be notified on i2c_irq_handler_asynch_t. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); + p_obj->info.asynch.address = (uint32_t)address; + p_obj->info.asynch.event = 0; + p_obj->info.asynch.stop = (uint32_t)stop; + p_obj->tx_buff.p_buffer = p_tx; + p_obj->tx_buff.length = (uint32_t)tx_length; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = p_rx; + p_obj->rx_buff.length = (uint32_t)rx_length; + p_obj->rx_buff.pos = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; + I2C_enable_interrupt(&p_obj->i2c); + if ((tx_length == 0) && (rx_length != 0)) { + I2C_start_condition(&p_obj->i2c, (uint32_t)((uint32_t)address | 1U)); + } else { + I2C_start_condition(&p_obj->i2c, (uint32_t)address); + } + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + enable_irq(p_obj->info.irqn); + result = TXZ_SUCCESS; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief The asynchronous IRQ handler + * @param p_obj :i2c object. + * @retval zero :Transfer in progress. + * @retval non-zero :Event information. + * @note Macro definition of return values is @ref I2C_Events. + * @attention This function should be implement as INTI2Cx_IRQHandler. + */ +/*--------------------------------------------------*/ +uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + i2c_irq_handler(p_obj); + + return (p_obj->info.asynch.event & I2C_EVENT_ALL); +} + +/*--------------------------------------------------*/ +/** + * @brief Abort asynchronous transfer + * @param p_obj :i2c object. + * @retval - + * @note After error event occurred on i2c_irq_handler_asynch_t, + * @note call this function and clear error status. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_abort_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + reset_asynch(p_obj); + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + i2c_reset_t(p_obj); + I2C_init(&p_obj->i2c); + clear_irq(p_obj->info.irqn); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure I2C as slave or master. + * @param p_obj :i2c object. + * @param enable_slave :Enable slave mode. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + disable_irq(p_obj->info.irqn); + + if (enable_slave) { + I2C_slave_init(&p_obj->i2c); + } else { + /* Slave Disable Settings. */ + i2c_reset_t(p_obj); + I2C_init(&p_obj->i2c); + } + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + I2C_clear_int_status(&p_obj->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Check to see if the I2C slave has been addressed. + * @param p_obj :i2c object. + * @retval I2C_NO_DATA :The slave has not been addressed. + * @retval I2C_READ_ADDRESSED :Read addresses. + * @retval I2C_WRITE_GENERAL :Write to all slaves(now, not support). + * @retval I2C_WRITE_ADDRESSED :Write addressed. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_receive_t(_i2c_t *p_obj) +{ + int32_t result = I2C_NO_DATA; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_slave_detected(&p_obj->i2c)) { + uint32_t sa = I2C_read_data(&p_obj->i2c); + (void)sa; + + if (!I2C_transmitter(&p_obj->i2c)) { + result = I2C_WRITE_ADDRESSED; + } else { + result = I2C_READ_ADDRESSED; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking reading data. + * @param p_obj :i2c object. + * @param p_data :Destination address of read data. + * @param length :Number of bytes to read. + * @retval Number of read bytes. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) +{ + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); +#endif /* #ifdef DEBUG */ + + /* Read all bytes */ + while (count < length) { + I2C_clear_int_status(&p_obj->i2c); + I2C_set_ack(&p_obj->i2c, ((count < (length - 1)) ? 0 : 1)); + I2C_write_data(&p_obj->i2c, 0); + if (wait_status(p_obj) < 0) { + break; + } + if (I2C_slave_detected(&p_obj->i2c)) { + return (count); + } + p_data[count++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + I2C_slave_init(&p_obj->i2c); + return (count); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking sending data. + * @param p_obj :i2c object. + * @param p_data :Source address of write data. + * @param length :Number of bytes to write. + * @retval Number of written bytes. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) +{ + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); +#endif /* #ifdef DEBUG */ + + /* Write all bytes */ + while (count < length) { + I2C_clear_int_status(&p_obj->i2c); + I2C_write_data(&p_obj->i2c, (uint32_t)p_data[count++]); + if (wait_status(p_obj) < 0) { + break; + } + if (!I2C_get_ack(&p_obj->i2c)) { + /* continue */ + } else { + break; + } + } + I2C_slave_init(&p_obj->i2c); + return (count); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure I2C slave address. + * @param p_obj :i2c object. + * @param address :Address to be set. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(check_param_address((int32_t)address)); +#endif /* #ifdef DEBUG */ + + I2C_set_address(&p_obj->i2c, address); +} + + +/*--------------------------------------------------*/ +/** + * @brief Start I2C asynchronous transfer + * @param p_obj :i2c object. + * @param p_tx :Buffer of write data. + * @param tx_length :Length of write data. + * @param p_rx :Buffer of read data. + * @param rx_length :Length of read data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Slave and non-blocking function. + * @note Events of this function will be notified on i2c_slave_irq_handler_asynch_t. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) { + reset_asynch(p_obj); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); + p_obj->info.asynch.address = 0; + p_obj->info.asynch.event = 0; + p_obj->info.asynch.stop = 0; + p_obj->tx_buff.p_buffer = p_tx; + p_obj->tx_buff.length = (uint32_t)tx_length; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = p_rx; + p_obj->rx_buff.length = (uint32_t)rx_length; + p_obj->rx_buff.pos = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; + I2C_enable_interrupt(&p_obj->i2c); + enable_irq(p_obj->info.irqn); + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief The asynchronous IRQ handler + * @param p_obj :i2c object. + * @retval zero :Transfer in progress. + * @retval non-zero :Event information. + * @note Macro definition of return values is @ref I2C_Events. + * @attention This function should be implement as INTI2Cx_IRQHandler. + */ +/*--------------------------------------------------*/ +uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + i2c_slave_irq_handler(p_obj); + + return (p_obj->info.asynch.event & I2C_EVENT_ALL); +} + +/*--------------------------------------------------*/ +/** + * @brief Abort asynchronous transfer + * @param p_obj :i2c object. + * @retval - + * @note For a non-blocking function. + * @note After error event occurred on i2c_slave_irq_handler_asynch_t, + * @note call this function and clear error status. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_abort_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + reset_asynch(p_obj); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + I2C_slave_init(&p_obj->i2c); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); +} + +/** + * @} + */ /* End of group UTILITIES_Exported_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#endif /* defined(__BSP_I2C_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_t32a.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_t32a.c new file mode 100644 index 00000000000..58225fadf32 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_t32a.c @@ -0,0 +1,1998 @@ +/** +******************************************************************************* +* @file txz_t32a.c +* @brief This file provides API functions for T32A driver. +* @version V1.0.0 +* +* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +* +* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +******************************************************************************* +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_t32a.h" + +#if defined(__T32A_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup T32A + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_define T32A Private Define + * @{ + */ +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ +/** + * @} + */ /* End of group T32A_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_define T32A Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_typedef T32A Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Private_member T32A Private Member + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_member */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_fuctions TSPI Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +__INLINE static int32_t check_param_mode_halt(uint32_t param); +__INLINE static int32_t check_param_mode_mode32(uint32_t param); +__INLINE static int32_t check_param_runx_sftstpx(uint32_t param); +__INLINE static int32_t check_param_runx_sftstax(uint32_t param); +__INLINE static int32_t check_param_runx_runx(uint32_t param); +__INLINE static int32_t check_param_crx_prsclx(uint32_t param); +__INLINE static int32_t check_param_crx_clkx(uint32_t param); +__INLINE static int32_t check_param_crx_wbfx(uint32_t param); +__INLINE static int32_t check_param_crx_updnx(uint32_t param); +__INLINE static int32_t check_param_crx_reldx(uint32_t param); +__INLINE static int32_t check_param_crx_stopx(uint32_t param); +__INLINE static int32_t check_param_crx_startx(uint32_t param); +__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param); +__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param); +__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param); +__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param); +__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param); +__INLINE static int32_t check_param_reldx_reld(uint32_t param); +__INLINE static int32_t check_param_imx_imsterr(uint32_t param); +__INLINE static int32_t check_param_imx_imufx(uint32_t param); +__INLINE static int32_t check_param_imx_imofx(uint32_t param); +__INLINE static int32_t check_param_imx_imx1(uint32_t param); +__INLINE static int32_t check_param_imx_imx0(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pup(uint32_t param); +__INLINE static int32_t check_param_pls_cr_nf(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param); +#endif + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the Mode HALT's parameter. + * @param param :Mode HALT's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_HALT + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_mode_halt(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DBG_HALT_RUN: + case T32A_DBG_HALT_STOP: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Mode mode32's parameter. + * @param param :Mode mode32's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_MODE32 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_mode_mode32(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_MODE_16: + case T32A_MODE_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the SW Counter STOP Control's parameter. + * @param param :SW Counter STOP Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_SFTSTPx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_sftstpx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_DONT_STOP: + case T32A_COUNT_STOP: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the SW START Control's parameter. + * @param param :SW START Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_SFTSTAx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_sftstax(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_DONT_START: + case T32A_COUNT_START: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A RUN Disable/Enable Control's parameter. + * @param param :T32A RUN Disable/Enable Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PRSCLx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_runx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_RUN_DISABLE: + case T32A_RUN_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A PRESCALER Control's parameter. + * @param param :T32A PRESCALER Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PRSCLx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_prsclx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PRSCLx_1: + case T32A_PRSCLx_2: + case T32A_PRSCLx_8: + case T32A_PRSCLx_32: + case T32A_PRSCLx_128: + case T32A_PRSCLx_256: + case T32A_PRSCLx_512: + case T32A_PRSCLx_1024: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A PRESCALER Control's parameter. + * @param param :T32A PRESCALER Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CLKx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_clkx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CLKx_PRSCLx: + case T32A_CLKx_INTRG: + case T32A_CLKx_TIM_RISING_EDGE: + case T32A_CLKx_TIM_TRAILING_EDGE: + case T32A_CLKx_EXTTRG_RISING_EDGE: + case T32A_CLKx_EXTTRG_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Double Buffer Disable/Enable Control's parameter. + * @param param :Double Buffer Disable/Enable Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_WBFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_wbfx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_WBF_DISABLE: + case T32A_WBF_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Up/Down Control's parameter. + * @param param :T32A Counter Up/Down Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_UPDNx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_updnx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_UP: + case T32A_COUNT_DOWN: + case T32A_COUNT_UPDOWN: + case T32A_COUNT_PLS: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Reload Control's parameter. + * @param param :T32A Counter Reload Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RELDx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_reldx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_RELOAD_NON: + case T32A_RELOAD_INTRG: + case T32A_RELOAD_EXTTRG_RISING_EDGE: + case T32A_RELOAD_EXTTRG_TRAILING_EDGE: + case T32A_RELOAD_TIM_RISING_EDGE: + case T32A_RELOAD_TIM_TRAILING_EDGE: + case T32A_RELOAD_SYNC: + case T32A_RELOAD_TREGx: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Stop Control's parameter. + * @param param :T32A Counter Stop Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_STOPx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_stopx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_STOP_NON: + case T32A_STOP_INTRG: + case T32A_STOP_EXTTRG_RISING_EDGE: + case T32A_STOP_EXTTRG_TRAILING_EDGE: + case T32A_STOP_TIM_RISING_EDGE: + case T32A_STOP_TIM_TRAILING_EDGE: + case T32A_STOP_SYNC: + case T32A_STOP_TREGx: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Start Control's parameter. + * @param param :T32A Counter Start Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_STARTx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_startx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_START_NON: + case T32A_START_INTRG: + case T32A_START_EXTTRG_RISING_EDGE: + case T32A_START_EXTTRG_TRAILING_EDGE: + case T32A_START_TIM_RISING_EDGE: + case T32A_START_TIM_TRAILING_EDGE: + case T32A_START_SYNC: + result = PARAM_OK; + break; + case T32A_START_Rsvd: + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control's parameter. + * @param param :T32AxOUTA Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCR_DISABLE: + case T32A_OCR_SET: + case T32A_OCR_CLR: + case T32A_OCR_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter. + * @param param :T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCAPx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCAPx1_DISABLE: + case T32A_OCRCAPx1_SET: + case T32A_OCRCAPx1_CLR: + case T32A_OCRCAPx1_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter. + * @param param :T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCAPx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCAPx0_DISABLE: + case T32A_OCRCAPx0_SET: + case T32A_OCRCAPx0_CLR: + case T32A_OCRCAPx0_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. + * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCMPx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCMPx1_DISABLE: + case T32A_OCRCMPx1_SET: + case T32A_OCRCMPx1_CLR: + case T32A_OCRCMPx1_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. + * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCMPx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCMPx0_DISABLE: + case T32A_OCRCMPx0_SET: + case T32A_OCRCMPx0_CLR: + case T32A_OCRCMPx0_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Capture Control Register A1's parameter. + * @param param :T32A Capture Control Register A1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CAPMx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CAPMx1_DISABLE: + case T32A_CAPMx1_INTRG: + case T32A_CAPMx1_INx0_RISING_EDGE: + case T32A_CAPMx1_INx0_TRAILING_EDGE: + case T32A_CAPMx1_INx1_RISING_EDGE: + case T32A_CAPMx1_INx1_TRAILING_EDGE: + case T32A_CAPMx1_TIM_RISING_EDGE: + case T32A_CAPMx1_TIM_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Capture Control Register A0's parameter. + * @param param :T32A Capture Control Register A0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CAPMx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CAPMx0_DISABLE: + case T32A_CAPMx0_INTRG: + case T32A_CAPMx0_INx0_RISING_EDGE: + case T32A_CAPMx0_INx0_TRAILING_EDGE: + case T32A_CAPMx0_INx1_RISING_EDGE: + case T32A_CAPMx0_INx1_TRAILING_EDGE: + case T32A_CAPMx0_TIM_RISING_EDGE: + case T32A_CAPMx0_TIM_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Timer Register A0's parameter. + * @param param :T32A Timer Register A0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RGx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RGx0_MASK) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Timer Register A1's parameter. + * @param param :T32A Timer Register A1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RGx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RGx1_MASK) { + result = PARAM_OK; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Reload Register A's parameter. + * @param param :T32A Counter Reload Register A's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RELD + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_reldx_reld(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RELDx_MASK) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Statuserr Interrupt Request MASK's parameter. + * @param param :T32A Statuserr Interrupt Request MASK's parameter. + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMSTEER + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imsterr(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMSTERR_MASK_NOREQ: + case T32A_IMSTERR_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Overflow Interrupt Request MASK's parameter. + * @param param :T32A Overflow Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMUFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imufx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMOFx_MASK_NOREQ: + case T32A_IMOFx_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Overflow Interrupt Request MASK's parameter. + * @param param :T32A Overflow Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMOFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imofx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMOFx_MASK_NOREQ: + case T32A_IMOFx_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter. + * @param param :T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMx1_MASK_NOREQ: + case T32A_IMx1_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter. + * @param param :T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMx0_MASK_NOREQ: + case T32A_IMx0_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA Converter1 Request control's parameter. + * @param param :T32A DMA Converter1 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx2 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx2_DISABLE: + case T32A_DMAENx2_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA InputCapture1 Request control's parameter. + * @param param :T32A DMA InputCapture1 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx1_DISABLE: + case T32A_DMAENx1_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA InputCapture0 Request control's parameter. + * @param param :T32A DMA InputCapture0 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx0_DISABLE: + case T32A_DMAENx0_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Mode Count Down Control's parameter. + * @param param :T32A Pulse Mode Count Down Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PDN + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PDN_NON0: + case T32A_PDN_NON1: + case T32A_PDN_INC0_RISING_EDGE: + case T32A_PDN_INC0_TRAILING_EDGE: + case T32A_PDN_INC1_RISING_EDGE: + case T32A_PDN_INC1_TRAILING_EDGE: + case T32A_PDN_INC0_BOTH_EDGE: + case T32A_PDN_INC1_BOTH_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Mode Count UP Control's parameter. + * @param param :T32A Pulse Mode Count UP Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PUP + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pup(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PUP_NON0: + case T32A_PUP_NON1: + case T32A_PUP_INC0_RISING_EDGE: + case T32A_PUP_INC0_TRAILING_EDGE: + case T32A_PUP_INC1_RISING_EDGE: + case T32A_PUP_INC1_TRAILING_EDGE: + case T32A_PUP_INC0_BOTH_EDGE: + case T32A_PUP_INC1_BOTH_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Noise Filter control's parameter. + * @param param :T32A Noise Filter control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_NF + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_nf(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_NF_NON: + case T32A_NF_2: + case T32A_NF_4: + case T32A_NF_8: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Phase 2 Pulse Direction control's parameter. + * @param param :T32A Phase 2 Pulse Direction control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PDIR + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PDIR_FORWARD: + case T32A_PDIR_BACKWARD: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Count Mode control's parameter. + * @param param :T32A Pulse Count Mode control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PMODE + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PMODE_PHASE_2: + case T32A_PMODE_PHASE_1: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + + + +#endif +/** + * @} + */ /* End of group T32A_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Exported_functions + + */ +/*--------------------------------------------------*/ +/** + * @brief Mode Initialize the T32A object. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_mode_init(t32a_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + check_param_mode_halt(p_obj->init_mode.mode.halt); + check_param_mode_mode32(p_obj->init_mode.mode.mode); +#endif /* __DEBUG__ */ + /* Timer Mode Set */ + p_obj->p_instance->MOD = 0; + p_obj->p_instance->MOD = (p_obj->init_mode.mode.halt | p_obj->init_mode.mode.mode); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Initialize the T32A object. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + /* Check the parameter of TimerA Mode Set */ + check_param_mode_halt(p_obj->init_mode.mode.halt); + check_param_mode_mode32(p_obj->init_mode.mode.mode); + /* Check the parameter of TimerA Run Control Set */ + check_param_runx_sftstpx(p_obj->init[type].runx.sftstp); + check_param_runx_sftstax(p_obj->init[type].runx.sftsta); + check_param_runx_runx(p_obj->init[type].runx.run); + /* Check the parameter of Counter Register Control Set */ + check_param_crx_prsclx(p_obj->init[type].crx.prscl); + check_param_crx_clkx(p_obj->init[type].crx.clk); + check_param_crx_wbfx(p_obj->init[type].crx.wbf); + check_param_crx_updnx(p_obj->init[type].crx.updn); + check_param_crx_reldx(p_obj->init[type].crx.reld); + check_param_crx_stopx(p_obj->init[type].crx.stop); + check_param_crx_startx(p_obj->init[type].crx.start); + /* Check the parameter of TimerA Output Control Set */ + check_param_outcrx0_ocrx(p_obj->init[type].outcrx0.ocr); + /* Check the parameter of T32AxOUTA Control Set */ + check_param_outcrx1_ocrcapx1(p_obj->init[type].outcrx1.ocrcap1); + check_param_outcrx1_ocrcapx0(p_obj->init[type].outcrx1.ocrcap0); + check_param_outcrx1_ocrcmpx1(p_obj->init[type].outcrx1.ocrcmp1); + check_param_outcrx1_ocrcmpx0(p_obj->init[type].outcrx1.ocrcmp0); + /* Check the parameter of Capture Control Set */ + check_param_capcrx_capmx1(p_obj->init[type].capcrx.capmx1); + check_param_capcrx_capmx0(p_obj->init[type].capcrx.capmx0); + /* Check the parameter of T32A Timer Register 0 Set */ + check_param_rgx0_rgx0(p_obj->init[type].rgx0.rgx0); + /* Check the parameter of T32A Timer Register 1 Set */ + check_param_rgx1_rgx1(p_obj->init[type].rgx1.rgx1); + /* Check the parameter of T32A Counter Reload Register Set */ + check_param_reldx_reld(p_obj->init[type].reldx.reld); + /* Check the parameter of Interrupt mask register Set */ + check_param_imx_imsterr(p_obj->init[type].imx.imsterr); + check_param_imx_imufx(p_obj->init[type].imx.imuf); + check_param_imx_imofx(p_obj->init[type].imx.imof); + check_param_imx_imx1(p_obj->init[type].imx.imx1); + check_param_imx_imx0(p_obj->init[type].imx.imx0); + /* Check the parameter of DMA Request register Set */ + check_param_dma_req_dmaenx2(p_obj->init[type].dma_req.dmaenx2); + check_param_dma_req_dmaenx1(p_obj->init[type].dma_req.dmaenx1); + check_param_dma_req_dmaenx0(p_obj->init[type].dma_req.dmaenx0); +#endif + + switch (type) { + case T32A_TIMERA: + /* Timer A */ + if (p_obj->init_mode.mode.mode != T32A_MODE_16) { + result = TXZ_ERROR; + return (result); + } + /* TimerA Run Control Disable */ + p_obj->p_instance->RUNA = 0; + /* Counter Register Control Set */ + p_obj->p_instance->CRA = 0; + p_obj->p_instance->CRA = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerA Output Control Set */ + p_obj->p_instance->OUTCRA0 = 0; + p_obj->p_instance->OUTCRA0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTA Control Set */ + p_obj->p_instance->OUTCRA1 = 0; + p_obj->p_instance->OUTCRA1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register A0 Set */ + p_obj->p_instance->RGA0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register A1 Set */ + p_obj->p_instance->RGA1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDA = 0; + p_obj->p_instance->RELDA = p_obj->init[type].reldx.reld; + /* TimerB Capture Control Set */ + p_obj->p_instance->CAPCRA = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMA = 0; + p_obj->p_instance->IMA = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAA = 0; + p_obj->p_instance->DMAA = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* TimerA Run Control Set */ + p_obj->p_instance->RUNA = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + case T32A_TIMERB: + /* Timer B */ + if (p_obj->init_mode.mode.mode != T32A_MODE_16) { + result = TXZ_ERROR; + return (result); + } + /* TimerB Run Control Disable */ + p_obj->p_instance->RUNB = 0; + /* Counter Register Control Set */ + p_obj->p_instance->CRB = 0; + p_obj->p_instance->CRB = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerB Output Control Set */ + p_obj->p_instance->OUTCRB0 = 0; + p_obj->p_instance->OUTCRB0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTB Control Set */ + p_obj->p_instance->OUTCRB1 = 0; + p_obj->p_instance->OUTCRB1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register B0 Set */ + p_obj->p_instance->RGB0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register B1 Set */ + p_obj->p_instance->RGB1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDB = 0; + p_obj->p_instance->RELDB = p_obj->init[type].reldx.reld; + /* TimerB Capture Control Set */ + p_obj->p_instance->CAPCRB = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMB = 0; + p_obj->p_instance->IMB = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAB = 0; + p_obj->p_instance->DMAB = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* TimerB Run Control Set */ + p_obj->p_instance->RUNB = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + case T32A_TIMERC: + /* Timer C */ + if (p_obj->init_mode.mode.mode != T32A_MODE_32) { + result = TXZ_ERROR; + return (result); + } + /* TimerC Run Control Disable */ + p_obj->p_instance->RUNC = 0; +#ifdef __DEBUG__ + /* Pulse Count Control register Set */ + check_param_pls_cr_pdn(p_obj->init[type].pls_cr.pdn); + check_param_pls_cr_pup(p_obj->init[type].pls_cr.pup); + check_param_pls_cr_nf(p_obj->init[type].pls_cr.nf); + check_param_pls_cr_pdir(p_obj->init[type].pls_cr.pdir); + check_param_pls_cr_pmode(p_obj->init[type].pls_cr.pmode); +#endif + /* Counter Register Control Set */ + p_obj->p_instance->CRC = 0; + p_obj->p_instance->CRC = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerC Output Control Set */ + p_obj->p_instance->OUTCRC0 = 0; + p_obj->p_instance->OUTCRC0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTC Control Set */ + p_obj->p_instance->OUTCRC1 = 0; + p_obj->p_instance->OUTCRC1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register C0 Set */ + p_obj->p_instance->RGC0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register C1 Set */ + p_obj->p_instance->RGC1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDC = 0; + p_obj->p_instance->RELDC = p_obj->init[type].reldx.reld; + /* TimerC Capture Control Set */ + p_obj->p_instance->CAPCRC = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMC = 0; + p_obj->p_instance->IMC = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAC = 0; + p_obj->p_instance->DMAC = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* Pulse Count Control register Set */ + p_obj->p_instance->PLSCR = 0; + p_obj->p_instance->PLSCR = (p_obj->init[type].pls_cr.pdn | p_obj->init[type].pls_cr.pup | p_obj->init[type].pls_cr.nf | \ + p_obj->init[type].pls_cr.pdir | p_obj->init[type].pls_cr.pmode); + /* TimerC Run Control Set */ + p_obj->p_instance->RUNC = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the T32A object. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNA = T32A_RUN_DISABLE; + break; + case T32A_TIMERB: + /* Timer B */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNB = T32A_RUN_DISABLE; + break; + case T32A_TIMERC: + /* Timer C */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNC = T32A_RUN_DISABLE; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Timer Start in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + if (((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0) { + /* Timer A RUN */ + p_obj->p_instance->RUNA |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERB: + if (((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0) { + /* Timer B RUN */ + p_obj->p_instance->RUNB |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERC: + if (((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0) { + /* Timer C RUN */ + p_obj->p_instance->RUNC |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Stop in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A Stop */ + p_obj->p_instance->RUNA = T32A_RUN_DISABLE; + break; + case T32A_TIMERB: + /* Timer B Stop */ + p_obj->p_instance->RUNB = T32A_RUN_DISABLE; + break; + case T32A_TIMERC: + /* SW Counter Stop & Timer C Stop */ + p_obj->p_instance->RUNC = T32A_RUN_DISABLE; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Start in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + if (((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0) { + /* Timer A SW Counter start */ + p_obj->p_instance->RUNA |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERB: + if (((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0) { + /* Timer SW Counter start */ + p_obj->p_instance->RUNB |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERC: + if (((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0) { + /* Timer C SW Counter start */ + p_obj->p_instance->RUNC |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Stop in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* TimerA SW Counter Stop */ + p_obj->p_instance->RUNA = T32A_COUNT_STOP; + break; + case T32A_TIMERB: + /* Timer B SW Counter Stop */ + p_obj->p_instance->RUNB = T32A_COUNT_STOP; + break; + case T32A_TIMERC: + /* Timer C SW Counter Stop */ + p_obj->p_instance->RUNC = T32A_COUNT_STOP; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Register Value Setting + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @param num :T32A Register Number. : Use @ref t32_regnum_t + * @param value :Setting Value. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A */ + if (num == T32A_REG0) { + p_obj->p_instance->RGA0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGA1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDA = value; + } + break; + case T32A_TIMERB: + /* Timer B */ + if (num == T32A_REG0) { + p_obj->p_instance->RGB0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGB1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDB = value; + } + break; + case T32A_TIMERC: + /* Timer C */ + if (num == T32A_REG0) { + p_obj->p_instance->RGC0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGC1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDC = value; + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Timer Register Value Read + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @param p_val :Save area for register value. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val) +{ + TXZ_Result result = TXZ_SUCCESS; + switch (type) { + case T32A_TIMERA: + /* Timer A */ + *p_val = p_obj->p_instance->TMRA; + break; + case T32A_TIMERB: + /* Timer B */ + *p_val = p_obj->p_instance->TMRB; + break; + case T32A_TIMERC: + /* Timer C */ + *p_val = p_obj->p_instance->TMRC; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-4 | - | - | + * | 3 | INTUFA | Under Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | + * | 2 | INTOFA | Over Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | + * | 1 | INTx1 | Match up TimerRegister x1 Intterrupt. Use @ref T32A_INTx1_FLG_MASK. | + * | 0 | INTx0 | Match up TimerRegister x0 Intterrupt. Use @ref T32A_INTx0_FLG_MASK. | + * + * @param p_obj :T32A object. + * @param p_status :Save area for status. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + switch (type) { + case T32A_TIMERA: + /* Timer A */ + *p_status = p_obj->p_instance->STA; + break; + case T32A_TIMERB: + /* Timer B */ + *p_status = p_obj->p_instance->STB; + break; + case T32A_TIMERC: + /* Timer C */ + *p_status = p_obj->p_instance->STC; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for Timer interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_T(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_T(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_T(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Timer Capture0 Handler for Timer Capture0 interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_cap0_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_TC0(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_TC0(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_TC0(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Timer Capture1 Handler for Timer Capture1 interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_cap1_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_TC1(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_TC1(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_TC1(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Calculate timer value to set timer register. + * @param p_value: time value store pointer. + * @param time: The require period which the uint is us. + * @param prescaler: System Clock Freq + * @param prscl: Select the division for source clock @ref T32A_PRSCLx. + * @retval the value set to Tmrb timer register. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl) +{ + TXZ_Result result = TXZ_SUCCESS; + uint64_t denominator; + uint64_t numerator; + uint32_t div; + + /* div */ + switch (prscl) { + case T32A_PRSCLx_1: + div = 1; + break; + case T32A_PRSCLx_2: + div = 2; + break; + case T32A_PRSCLx_8: + div = 8; + break; + case T32A_PRSCLx_32: + div = 32; + break; + case T32A_PRSCLx_128: + div = 128; + break; + case T32A_PRSCLx_256: + div = 256; + break; + case T32A_PRSCLx_512: + div = 512; + break; + case T32A_PRSCLx_1024: + div = 1024; + break; + default: + div = 1; + break; + } + /*-----------------------------------------------*/ + /* "1"counter (s) = 1 / fs */ + /* "1"counter (s) = 1 / (prescaler / div) */ + /* "1"counter (us) = (10^6) / (prescaler / div) */ + /* "1"counter (us) = ((10^6) * div)/prescaler */ + /* "x"counter (us) = time */ + /*-----------------------------------------------*/ + /* x : time = 1 : ((10^6) * div)/prescaler */ + /*-----------------------------------------------*/ + /* x = time / (((10^6) * div)/prescaler) */ + /* = (prescaler * time) / ((10^6) * div) */ + /*-----------------------------------------------*/ + denominator = (uint64_t)((uint64_t)(prescaler) * (uint64_t)(time)); + numerator = (uint64_t)((uint64_t)(1000000) * (uint64_t)div); + denominator = (uint64_t)(denominator / numerator); + /* result */ + if ((denominator == (uint64_t)(0)) || (denominator > (uint64_t)(0xFFFF))) { + result = TXZ_ERROR; + } else { + *p_value = (uint32_t)denominator; + } + + return (result); +} + +/** + * @} + */ /* End of group T32A_Exported_functions */ + +/** + * @} + */ /* End of group T32A */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__T32A_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_tspi.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_tspi.c new file mode 100644 index 00000000000..b84b9266fa4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_tspi.c @@ -0,0 +1,2895 @@ +/** + ******************************************************************************* + * @file txz_tspi.c + * @brief This file provides API functions for TSPI driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_tspi.h" + +#if defined(__TSPI_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup TSPI + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ +/** + * @name TSPI NULL Pointer + * @brief Null Pointer for TSPI + * @{ + */ +#define TSPI_NULL ((void *)0) /*!< NULL pointer. */ +/** + * @} + */ /* End of name TSPI NULL Pointer */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name FIFO Max Num. + * @brief Transfer's/Receive's FIFO Max Num. + * @{ + */ +#define TRANSFER_FIFO_MAX_NUM ((uint32_t)8) /*!< Transfer's FIFO Max Num. */ +#define RECEIVE_FIFO_MAX_NUM ((uint32_t)8) /*!< Receive's FIFO Max Num. */ +/** + * @} + */ /* End of name FIFO Max Num */ + +/** + * @name TSPIxDR_MASK Macro Definition. + * @brief TSPIxDR_MASK Macro Definition. + * @{ + */ +/* DR */ +#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_31BIT_MASK ((uint32_t)0x7FFFFFFF) /*!< DR :Mask for 8bit */ +/** + * @} + */ /* End of name TSPIxDR_MASK Macro Definition */ + +/** + * @name TSPI _DATA_LENGTH Macro Definition. + * @brief TSPI DATA LENGTH Macro Definition. + * @{ + */ +#define DATA_LENGTH_8 ((uint32_t)0x08) /*!< 8 bit */ +#define DATA_LENGTH_9 ((uint32_t)0x09) /*!< 9 bit */ +#define DATA_LENGTH_10 ((uint32_t)0x0a) /*!< 10 bit */ +#define DATA_LENGTH_11 ((uint32_t)0x0b) /*!< 11 bit */ +#define DATA_LENGTH_12 ((uint32_t)0x0c) /*!< 12 bit */ +#define DATA_LENGTH_13 ((uint32_t)0x0d) /*!< 13 bit */ +#define DATA_LENGTH_14 ((uint32_t)0x0e) /*!< 14 bit */ +#define DATA_LENGTH_15 ((uint32_t)0x0f) /*!< 15 bit */ +#define DATA_LENGTH_16 ((uint32_t)0x10) /*!< 16 bit */ +#define DATA_LENGTH_17 ((uint32_t)0x11) /*!< 17 bit */ +#define DATA_LENGTH_18 ((uint32_t)0x12) /*!< 18 bit */ +#define DATA_LENGTH_19 ((uint32_t)0x13) /*!< 19 bit */ +#define DATA_LENGTH_20 ((uint32_t)0x14) /*!< 20 bit */ +#define DATA_LENGTH_21 ((uint32_t)0x15) /*!< 21 bit */ +#define DATA_LENGTH_22 ((uint32_t)0x16) /*!< 22 bit */ +#define DATA_LENGTH_23 ((uint32_t)0x17) /*!< 23 bit */ +#define DATA_LENGTH_24 ((uint32_t)0x18) /*!< 24 bit */ +#define DATA_LENGTH_25 ((uint32_t)0x19) /*!< 25 bit */ +#define DATA_LENGTH_26 ((uint32_t)0x1a) /*!< 26 bit */ +#define DATA_LENGTH_27 ((uint32_t)0x1b) /*!< 27 bit */ +#define DATA_LENGTH_28 ((uint32_t)0x1c) /*!< 28 bit */ +#define DATA_LENGTH_29 ((uint32_t)0x1d) /*!< 29 bit */ +#define DATA_LENGTH_30 ((uint32_t)0x1e) /*!< 30 bit */ +#define DATA_LENGTH_31 ((uint32_t)0x1f) /*!< 31 bit */ +#define DATA_LENGTH_32 ((uint32_t)0x20) /*!< 32 bit */ +/** + * @} + */ /* End of name TSPI _DATA_LENGTH Macro Definition */ +/** + * @} + */ /* End of group TSPI_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group TSPI_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_typedef TSPI Private Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief TSPI mask array. +*/ +/*----------------------------------*/ +static uint32_t mask[32] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TSPI_DR_8BIT_MASK, + TSPI_DR_9BIT_MASK, + TSPI_DR_10BIT_MASK, + TSPI_DR_11BIT_MASK, + TSPI_DR_12BIT_MASK, + TSPI_DR_13BIT_MASK, + TSPI_DR_14BIT_MASK, + TSPI_DR_15BIT_MASK, + TSPI_DR_16BIT_MASK, + TSPI_DR_17BIT_MASK, + TSPI_DR_18BIT_MASK, + TSPI_DR_19BIT_MASK, + TSPI_DR_20BIT_MASK, + TSPI_DR_21BIT_MASK, + TSPI_DR_22BIT_MASK, + TSPI_DR_23BIT_MASK, + TSPI_DR_24BIT_MASK, + TSPI_DR_25BIT_MASK, + TSPI_DR_26BIT_MASK, + TSPI_DR_27BIT_MASK, + TSPI_DR_28BIT_MASK, + TSPI_DR_29BIT_MASK, + TSPI_DR_30BIT_MASK, + TSPI_DR_31BIT_MASK +}; + +/** + * @} + */ /* End of group TSPI_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_fuctions TSPI Private Fuctions + * @{ + */ + +#ifdef __DEBUG__ +__INLINE static int32_t check_param_frameinf_enable(uint32_t param); +__INLINE static int32_t check_param_trgen_enable(uint32_t param); +__INLINE static int32_t check_param_transmit_enable(uint32_t param); +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param); +__INLINE static int32_t check_param_transmit_master(uint32_t param); +__INLINE static int32_t check_param_transmit_mode(uint32_t param); +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param); +__INLINE static int32_t check_param_frame_range(uint32_t param); +__INLINE static int32_t check_param_idle_imp(uint32_t param); +__INLINE static int32_t check_param_underrun_imp(uint32_t param); +__INLINE static int32_t check_param_rxdly_value(uint32_t param); +__INLINE static int32_t check_param_tx_fill_level(uint32_t param); +__INLINE static int32_t check_param_rx_fill_level(uint32_t param); +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param); +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param); +__INLINE static int32_t check_param_err_int(uint32_t param); +__INLINE static int32_t check_param_tx_dma_int(uint32_t param); +__INLINE static int32_t check_param_rx_dma_int(uint32_t param); +__INLINE static int32_t check_param_input_clock(uint32_t param); +__INLINE static int32_t check_param_input_divider(uint32_t param); +__INLINE static int32_t check_param_data_direction(uint32_t param); +__INLINE static int32_t check_param_frame_length(uint32_t param); +__INLINE static int32_t check_param_frame_interval(uint32_t param); +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param); +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param); +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param); +__INLINE static int32_t check_param_min_idle_time(uint32_t param); +__INLINE static int32_t check_param_clock_delay(uint32_t param); +__INLINE static int32_t check_param_negate_delay(uint32_t param); +__INLINE static int32_t check_param_parity_enable(uint32_t param); +__INLINE static int32_t check_param_parity_bit(uint32_t param); +__INLINE static int32_t check_param_sect_mode(uint32_t param); +__INLINE static int32_t check_param_sectl0_value(uint32_t param); +__INLINE static int32_t check_param_sectl1_value(uint32_t param); +__INLINE static int32_t check_param_sectl2_value(uint32_t param); +__INLINE static int32_t check_param_sectl3_value(uint32_t param); +#endif + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit frame infinity Enable's parameter. + * @param param :Transmit frame infinity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Infinity_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frameinf_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_INF_DISABLE: + case TSPI_INF_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Trgen Enable's parameter. + * @param param :Trgen Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Trigger_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_trgen_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TRGEN_DISABLE: + case TSPI_TRGEN_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Enable's parameter. + * @param param :Transmit Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TRXE_DISABLE: + case TSPI_TRXE_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Mode's parameter. + * @param param :Transmit Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SPI_MODE: + case TSPI_SIO_MODE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Master/Slave parameter. + * @param param :Transmit Master/Slave parameter (Only support Master mode) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Operation_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_master(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_MASTER_OPERATION: + case TSPI_SLAVE_OPERATION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transfer Mode's parameter. + * @param param :Transfer Mode's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TWO_WAY: + case TSPI_TX_ONLY: + case TSPI_RX_ONLY: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Sel Select's parameter. + * @param param :Transmit Sel Select's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_CSSEL_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS0_ENABLE: + case TSPI_TSPIxCS1_ENABLE: + case TSPI_TSPIxCS2_ENABLE: + case TSPI_TSPIxCS3_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Frame Range's parameter. + * @param param :TransmitFrame Range's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Frame_Range + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_range(uint32_t param) + +{ + int32_t result = PARAM_NG; + + if ((TSPI_TRANS_RANGE_CONTINUE == param) || (TSPI_TRANS_RANGE_SINGLE == param) || (param <= TSPI_TRANS_RANGE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the IDLE Output Value's parameter. + * @param param :IDLE Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_IDLE_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TIDLE_Hiz: + case TSPI_TIDLE_LAST_DATA: + case TSPI_TIDLE_LOW: + case TSPI_TIDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_underrun_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TXDEMP_LOW: + case TSPI_TXDEMP_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rxdly_value(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RXDLY_1CLK: + case TSPI_RXDLY_2CLK: + case TSPI_RXDLY_3CLK: + case TSPI_RXDLY_4CLK: + case TSPI_RXDLY_5CLK: + case TSPI_RXDLY_6CLK: + case TSPI_RXDLY_7CLK: + case TSPI_RXDLY_8CLK: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level's parameter. + * @param param :Tx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_FILL_LEVEL_0: + case TSPI_TX_FILL_LEVEL_1: + case TSPI_TX_FILL_LEVEL_2: + case TSPI_TX_FILL_LEVEL_3: + case TSPI_TX_FILL_LEVEL_4: + case TSPI_TX_FILL_LEVEL_5: + case TSPI_TX_FILL_LEVEL_6: + case TSPI_TX_FILL_LEVEL_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_FILL_LEVEL_1: + case TSPI_RX_FILL_LEVEL_2: + case TSPI_RX_FILL_LEVEL_3: + case TSPI_RX_FILL_LEVEL_4: + case TSPI_RX_FILL_LEVEL_5: + case TSPI_RX_FILL_LEVEL_6: + case TSPI_RX_FILL_LEVEL_7: + case TSPI_RX_FILL_LEVEL_8: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_FIFO_INT_DISABLE: + case TSPI_TX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_INT_DISABLE: + case TSPI_TX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFIFOInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_FIFO_INT_DISABLE: + case TSPI_RX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_INT_DISABLE: + case TSPI_RX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ErrorInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_err_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_ERR_INT_DISABLE: + case TSPI_ERR_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx DMA Interrupt's parameter. + * @param param :Tx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_DMA_INT_DISABLE: + case TSPI_TX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx DMA Interrupt's parameter. + * @param param :Rx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_DMA_INT_DISABLE: + case TSPI_RX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Input Clock's parameter. + * @param param :Input Clock's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_clock(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_BR_CLOCK_0: + case TSPI_BR_CLOCK_1: + case TSPI_BR_CLOCK_2: + case TSPI_BR_CLOCK_4: + case TSPI_BR_CLOCK_8: + case TSPI_BR_CLOCK_16: + case TSPI_BR_CLOCK_32: + case TSPI_BR_CLOCK_64: + case TSPI_BR_CLOCK_128: + case TSPI_BR_CLOCK_256: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Baudrate Divider's parameter. + * @param param :Baudrate Divider's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_divider(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_BR_DIVIDER_16: + case TSPI_BR_DIVIDER_1: + case TSPI_BR_DIVIDER_2: + case TSPI_BR_DIVIDER_3: + case TSPI_BR_DIVIDER_4: + case TSPI_BR_DIVIDER_5: + case TSPI_BR_DIVIDER_6: + case TSPI_BR_DIVIDER_7: + case TSPI_BR_DIVIDER_8: + case TSPI_BR_DIVIDER_9: + case TSPI_BR_DIVIDER_10: + case TSPI_BR_DIVIDER_11: + case TSPI_BR_DIVIDER_12: + case TSPI_BR_DIVIDER_13: + case TSPI_BR_DIVIDER_14: + case TSPI_BR_DIVIDER_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataDirection"TSPI_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_DATA_DIRECTION_LSB: + case TSPI_DATA_DIRECTION_MSB: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter (Only support 8bit DATA) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataLength"TSPI_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_length(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_DATA_LENGTH_8: + case TSPI_DATA_LENGTH_9: + case TSPI_DATA_LENGTH_10: + case TSPI_DATA_LENGTH_11: + case TSPI_DATA_LENGTH_12: + case TSPI_DATA_LENGTH_13: + case TSPI_DATA_LENGTH_14: + case TSPI_DATA_LENGTH_15: + case TSPI_DATA_LENGTH_16: + case TSPI_DATA_LENGTH_17: + case TSPI_DATA_LENGTH_18: + case TSPI_DATA_LENGTH_19: + case TSPI_DATA_LENGTH_20: + case TSPI_DATA_LENGTH_21: + case TSPI_DATA_LENGTH_22: + case TSPI_DATA_LENGTH_23: + case TSPI_DATA_LENGTH_24: + case TSPI_DATA_LENGTH_25: + case TSPI_DATA_LENGTH_26: + case TSPI_DATA_LENGTH_27: + case TSPI_DATA_LENGTH_28: + case TSPI_DATA_LENGTH_29: + case TSPI_DATA_LENGTH_30: + case TSPI_DATA_LENGTH_31: + case TSPI_DATA_LENGTH_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Frame Interval's parameter. + * @param param :Frame Interval's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Frame_Interval_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_interval(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_INTERVAL_TIME_0: + case TSPI_INTERVAL_TIME_1: + case TSPI_INTERVAL_TIME_2: + case TSPI_INTERVAL_TIME_3: + case TSPI_INTERVAL_TIME_4: + case TSPI_INTERVAL_TIME_5: + case TSPI_INTERVAL_TIME_6: + case TSPI_INTERVAL_TIME_7: + case TSPI_INTERVAL_TIME_8: + case TSPI_INTERVAL_TIME_9: + case TSPI_INTERVAL_TIME_10: + case TSPI_INTERVAL_TIME_11: + case TSPI_INTERVAL_TIME_12: + case TSPI_INTERVAL_TIME_13: + case TSPI_INTERVAL_TIME_14: + case TSPI_INTERVAL_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS3 Polarity's parameter. + * @param param :TTSPIxCS3 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS3_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS3_NEGATIVE: + case TSPI_TSPIxCS3_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS2 Polarity's parameter. + * @param param :TTSPIxCS2 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS2_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS2_NEGATIVE: + case TSPI_TSPIxCS2_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS1 Polarity's parameter. + * @param param :TTSPIxCS1 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS1_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS1_NEGATIVE: + case TSPI_TSPIxCS1_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS0 Polarity's parameter. + * @param param :TTSPIxCS0 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS0_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS0_NEGATIVE: + case TSPI_TSPIxCS0_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Polarity's parameter. + * @param param :Serial Clock Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_1ST_EDGE: + case TSPI_SERIAL_CK_2ND_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock IDLE Polarity's parameter. + * @param param :Serial Clock IDLE Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_IDLE_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_IDLE_LOW: + case TSPI_SERIAL_CK_IDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Minimum IDLE Time's parameter. + * @param param :Minimum IDLE Time's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Minimum_IDLE_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_min_idle_time(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_MIN_IDLE_TIME_1: + case TSPI_MIN_IDLE_TIME_2: + case TSPI_MIN_IDLE_TIME_3: + case TSPI_MIN_IDLE_TIME_4: + case TSPI_MIN_IDLE_TIME_5: + case TSPI_MIN_IDLE_TIME_6: + case TSPI_MIN_IDLE_TIME_7: + case TSPI_MIN_IDLE_TIME_8: + case TSPI_MIN_IDLE_TIME_9: + case TSPI_MIN_IDLE_TIME_10: + case TSPI_MIN_IDLE_TIME_11: + case TSPI_MIN_IDLE_TIME_12: + case TSPI_MIN_IDLE_TIME_13: + case TSPI_MIN_IDLE_TIME_14: + case TSPI_MIN_IDLE_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Delay's parameter. + * @param param :Serial Clock Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_DELAY_1: + case TSPI_SERIAL_CK_DELAY_2: + case TSPI_SERIAL_CK_DELAY_3: + case TSPI_SERIAL_CK_DELAY_4: + case TSPI_SERIAL_CK_DELAY_5: + case TSPI_SERIAL_CK_DELAY_6: + case TSPI_SERIAL_CK_DELAY_7: + case TSPI_SERIAL_CK_DELAY_8: + case TSPI_SERIAL_CK_DELAY_9: + case TSPI_SERIAL_CK_DELAY_10: + case TSPI_SERIAL_CK_DELAY_11: + case TSPI_SERIAL_CK_DELAY_12: + case TSPI_SERIAL_CK_DELAY_13: + case TSPI_SERIAL_CK_DELAY_14: + case TSPI_SERIAL_CK_DELAY_15: + case TSPI_SERIAL_CK_DELAY_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Negate Delay's parameter. + * @param param :Negate Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Negate_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_negate_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_NEGATE_1: + case TSPI_NEGATE_2: + case TSPI_NEGATE_3: + case TSPI_NEGATE_4: + case TSPI_NEGATE_5: + case TSPI_NEGATE_6: + case TSPI_NEGATE_7: + case TSPI_NEGATE_8: + case TSPI_NEGATE_9: + case TSPI_NEGATE_10: + case TSPI_NEGATE_11: + case TSPI_NEGATE_12: + case TSPI_NEGATE_13: + case TSPI_NEGATE_14: + case TSPI_NEGATE_15: + case TSPI_NEGATE_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityEnable"TSPI_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_PARITY_DISABLE: + case TSPI_PARITY_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityBit"TSPI_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_PARITY_BIT_ODD: + case TSPI_PARITY_BIT_EVEN: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sect Mode's parameter. + * @param param :Sect Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_MODE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sect_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SECT_MODE_FRAME: + case TSPI_SECT_MODE_SECT: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl0 bit length's parameter. + * @param param :Sectl0 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl0_value(uint32_t param) +{ + int32_t result = PARAM_NG; + + /* 1~32:setting enable */ + if ((param >= TSPI_SECT_VALUE_1) && (param <= TSPI_SECT_VALUE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl1 bit length's parameter. + * @param param :Sectl1 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl1_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl1_value = (param >> 8); + + /* 1~32:setting enable */ + if ((sectl1_value >= TSPI_SECT_VALUE_1) && (sectl1_value <= TSPI_SECT_VALUE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl2 bit length's parameter. + * @param param :Sectl2 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl2_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl2_value = (param >> 16); + + /* 0~32:setting enable */ + if (sectl2_value <= TSPI_SECT_VALUE_MAX) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl3 bit length's parameter. + * @param param :Sectl3 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl3_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl3_value = (param >> 24); + + /* 0~32:setting enable */ + if (sectl3_value <= TSPI_SECT_VALUE_MAX) { + result = PARAM_OK; + } + + return (result); +} +#endif +/** + * @} + */ /* End of group TSPI_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_init(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxCR1. */ + assert_param(check_param_frameinf_enable(p_obj->init.cnt1.inf)); + assert_param(check_param_trgen_enable(p_obj->init.cnt1.trgen)); + assert_param(check_param_transmit_enable(p_obj->init.cnt1.trxe)); + assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims)); + assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr)); + assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd)); + assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel)); + assert_param(check_param_frame_range(p_obj->init.cnt1.fc)); + /* Check the parameter of TTSPIxCR2 */ + assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle)); + assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp)); + assert_param(check_param_rxdly_value(p_obj->init.cnt2.rxdly)); + assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til)); + assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril)); + assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe)); + assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe)); + assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe)); + assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe)); + assert_param(check_param_err_int(p_obj->init.cnt2.interr)); + assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate)); + assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare)); + /* Check the parameter of TTSPIxBR */ + assert_param(check_param_input_clock(p_obj->init.brd.brck)); + assert_param(check_param_input_divider(p_obj->init.brd.brs)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); + /* Check the parameter of TSPISECTCR0 */ + assert_param(check_param_sect_mode(p_obj->init.scr0.sect)); + /* Check the parameter of TSPISECTCR1 */ + assert_param(check_param_sectl0_value(p_obj->init.scr1.sectl0)); + assert_param(check_param_sectl1_value(p_obj->init.scr1.sectl1)); + assert_param(check_param_sectl2_value(p_obj->init.scr1.sectl2)); + assert_param(check_param_sectl3_value(p_obj->init.scr1.sectl3)); +#endif + + + /* TSPI Software Reset */ + p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE); + p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE);; + + /* Wait for 2 clocks of reset completion */ + __NOP(); + __NOP(); + + /* Enable the selected TSPI peripheral (TSPIE)*/ + p_obj->p_instance->CR0 = TSPI_ENABLE; + + /* Control1 Register1 Set*/ + p_obj->p_instance->CR1 = 0x00001C01U; + p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \ + p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims | p_obj->init.cnt1.trgen | p_obj->init.cnt1.inf); + /* Control2 Register Set */ + p_obj->p_instance->CR2 = 0x00E10100U; + p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \ + p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe | p_obj->init.cnt2.inttxwe | \ + p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare); + + /* Control3 Register is FIFO clear, do nothing */ + + /* Baudrate Register Set */ + p_obj->p_instance->BR = 0U; + p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs); + + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = 0x8800C400U; + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl); + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = 0U; + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + + /* Sect control0 Register Set*/ + p_obj->p_instance->SECTCR0 = 0U; + p_obj->p_instance->SECTCR0 = p_obj->init.scr0.sect; + + /* Sect control1 Register Set*/ + p_obj->p_instance->SECTCR1 = 0x00000101U; + p_obj->p_instance->SECTCR1 = (p_obj->init.scr1.sectl3 | p_obj->init.scr1.sectl2 | p_obj->init.scr1.sectl1 | p_obj->init.scr1.sectl0); + + /* not created */ + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_deinit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Disable the selected TSPI peripheral */ + p_obj->p_instance->CR0 = TSPI_DISABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data.. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err = 0; + uint32_t length = 0; + + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + + /* Transmit data check*/ + if ((p_info->tx8.p_data == TSPI_NULL) || (p_info->tx8.num == 0)) { + p_obj->errcode = DATABUFEMPERR; + result = TXZ_ERROR; + return (result); + } + + /* FIFO Cear */ + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8; + } else { + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + /* Transmit Data write to D ata Register */ + while (p_info->tx8.num > 0) { + /* Check the current fill level */ + if (((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) { + *((__IO uint8_t *)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK); + p_info->tx8.num--; + /* check complete transmit */ + if ((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) { + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } else { + /* Enable TSPI Transmission Control */ + if (p_info->tx8.num == 0) { + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + return (result); + } else { + /* Next transmit data sending */ + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + } + } else { + p_obj->errcode = FIFOFULLERR; + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + + } + /* check complete transmit */ + while ((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) { + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + /* Check Error Flag */ + if ((tspi_get_error(p_obj, &err)) != TXZ_ERROR) { + if (((err) & TSPI_UNDERRUN_ERR) == TSPI_UNDERRUN_ERR) { + p_obj->errcode = UNDERRUNERR; + } else if (((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) { + p_obj->errcode = OVERRUNERR; + } else if (((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) { + p_obj->errcode = PARITYERR; + } + } else { + result = TXZ_ERROR; + return (result); + } + if (p_obj->errcode == NOERROR) { + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err = 0; + uint32_t length = 0; + uint32_t count = 0; + uint32_t index = 0; + + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + /* Transmit data check*/ + if ((p_info->rx8.p_data == TSPI_NULL) || (p_info->rx8.num == 0)) { + result = TXZ_ERROR; + return (result); + } + count = p_info->rx8.num; + + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8; + } else { + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + while (timeout > 0) { + /* Wait until Receive Complete Flag is set to receive data */ + if ((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) { + while (count > 0) { + /* Check the remain data exist */ + if ((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0) { + p_info->rx8.p_data[index] = (*((__IO uint8_t *)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK); + count--; + index++; + } else { + p_obj->errcode = FIFOFULLERR; + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + } + /* Receive Complete Flag is clear */ + p_obj->p_instance->SR |= TSPI_RX_DONE_CLR; + /* FIFO Cear */ + p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } else { + timeout--; + } + } + /* Timeout management */ + p_obj->errcode = TIMEOUTERR; + + /* Check Error Flag set */ + if ((tspi_get_error(p_obj, &err)) != TXZ_ERROR) { + if (((err) & TSPI_UNDERRUN_ERR) == TSPI_UNDERRUN_ERR) { + p_obj->errcode = UNDERRUNERR; + } else if (((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) { + p_obj->errcode = OVERRUNERR; + } else if (((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) { + p_obj->errcode = PARITYERR; + } + } else { + result = TXZ_ERROR; + return (result); + } + + result = TXZ_ERROR; + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + p_obj->transmit.tx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + p_obj->transmit.tx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; + p_obj->transmit.info.tx32.num = p_info->tx32.num; + p_obj->transmit.tx_allign = 32; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /* transmit data length set */ + + /*--- TSPIxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Empty FIFO Num */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + /*--- TSPIxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + return (result); +} + + + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + p_obj->receive.rx_allign = 8; + + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; + p_obj->receive.info.rx32.num = p_info->rx32.num; + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data DMA. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + p_obj->transmit.tx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + p_obj->transmit.tx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; + p_obj->transmit.info.tx32.num = p_info->tx32.num; + p_obj->transmit.tx_allign = 32; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /* transmit data length set */ + + /*--- TSPIxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Empty FIFO Num */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + /*--- TSPIxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /* Write to DMATE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR2 & TSPI_TX_DMA_INT_ENABLE) != TSPI_TX_DMA_INT_ENABLE) { + p_obj->p_instance->CR2 |= TSPI_TX_DMA_INT_ENABLE; + } + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data DMA. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + p_obj->receive.rx_allign = 8; + + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; + p_obj->receive.info.rx32.num = p_info->rx32.num; + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /* Write to DMARE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR2 & TSPI_RX_DMA_INT_ENABLE) != TSPI_RX_DMA_INT_ENABLE) { + p_obj->p_instance->CR2 |= TSPI_RX_DMA_INT_ENABLE; + } + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_transmit(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + /* Check the transmit's end flag. */ + if (((status & TSPI_TX_DONE_FLAG) == TSPI_TX_DONE) || + ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til)) { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Get the empty num in FIFO. */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + if (tlvl == TRANSFER_FIFO_MAX_NUM) { + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.tx_allign = 8; + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.tx_allign = 16; + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } else { + /* 17 - 32 bit */ + p_obj->transmit.tx_allign = 32; + if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } + } + if (txDone == TXZ_DONE) { + /*=== Transmit Done!! ===*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) { + /* Call the transmit handler with SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } +#if 0 + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; +#endif + } + } +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_receive(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.rx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + /* Check the receive's end flag. */ + if (((status & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) || + ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril)) { + /* Read FIFO fill level. */ + __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK); + /* FIFO Max = RECEIVE_FIFO_MAX_NUM */ + if (rlvl > RECEIVE_FIFO_MAX_NUM) { + rlvl = RECEIVE_FIFO_MAX_NUM; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) { + uint32_t i; + for (i = 0; i < rlvl; i++) { + switch (p_obj->receive.rx_allign) { + case 8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK); + break; + case 16: + *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + case 32: + *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) { + tspi_receive_t param; + + switch (p_obj->receive.rx_allign) { + case 8: + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + break; + case 16: + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + break; + case 32: + param.rx32.p_data = p_obj->receive.info.rx32.p_data; + param.rx32.num = rlvl; + break; + default: + /* no process */ + break; + } + /* Call the receive handler with SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_error_irq_handler(tspi_t *p_obj) +{ + __IO uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current TSPIxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- TSPIxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) { + /* Call the transmit handler with FAILURE. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* UNDERERR */ + if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR) { + err = TXZ_ERROR; + } + /* OVRERR */ + if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR) { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR) { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) { + /* Call the receive handler with FAILURE. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL); + } + } + } +} + + +/*--------------------------------------------------*/ +/** + * @brief Data Format setting + * @param p_obj :TSPI object. + * @retval - + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_format(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); +#endif + + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. | + * | 30-24 | - | - | + * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. | + * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. | + * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. | + * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. | + * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. | + * | 15-8 | - | - | + * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. | + * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. | + * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag | + * + * @param p_obj :TSPI object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_status is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI state */ + *p_status = p_obj->p_instance->SR; + if (p_status != TSPI_NULL) { + return (result); + } else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI ERROR */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Error information clear. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_error_clear(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + p_obj->p_instance->ERR = (TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_transmit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_receive(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + + +/** + * @} + */ /* End of group TSPI_Exported_functions */ + +/** + * @} + */ /* End of group TSPI */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__TSPI_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_uart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_uart.c new file mode 100644 index 00000000000..95f315ac404 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_uart.c @@ -0,0 +1,1805 @@ +/** + ******************************************************************************* + * @file txz_uart.c + * @brief This file provides API functions for UART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_uart_include.h" +#include "txz_uart.h" + +#if defined(__UART_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/** + * @defgroup UART_BourateConfig Bourate Setting Configuration + * @brief Bourate Setting Configuration. + * @{ + */ +#define UART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ +#define UART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ +#define UART_CFG_GET_BOUDRATE UART_CFG_GET_BOUDRATE_ENABLE /* Disable/Enable Get Bourate Setting */ + +#define UART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ +#define UART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ +#define UART_CFG_GET_BOUDRATE_TYPE UART_CFG_GET_BOUDRATE_TYPE_ALL + +#define UART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)3) /*!< Error Margin(%). */ +#define UART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ +/** + * @} + */ /* End of group UART_BourateConfig */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_typedef UART Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_fuctions UART Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param); +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param); +__STATIC_INLINE int32_t check_param_data_direction(uint32_t param); +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); +__STATIC_INLINE int32_t check_param_data_length(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_err_int(uint32_t param); +__STATIC_INLINE int32_t check_param_prescaler(uint32_t param); +__STATIC_INLINE int32_t check_param_division(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); +#endif /* #ifdef __DEBUG__ */ +__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level); +__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level); +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) +static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); +#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the Noize Fileter's parameter. + * @param param :Noize fileter's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_NoiseFilter"UART_NOISE_FILTER_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_NOISE_FILTER_NON: + case UART_NOISE_FILTER_2_T0: + case UART_NOISE_FILTER_4_T0: + case UART_NOISE_FILTER_8_T0: + case UART_NOISE_FILTER_2_CLOCK: + case UART_NOISE_FILTER_3_CLOCK: + case UART_NOISE_FILTER_4_CLOCK: + case UART_NOISE_FILTER_5_CLOCK: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the CTS Handshake's parameter. + * @param param :CTS Handshake's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_CTSHandshake"UART_CTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_CTS_DISABLE: + case UART_CTS_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the RTS Handshake's parameter. + * @param param :RTS Handshake's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RTSHandshake"UART_RTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RTS_DISABLE: + case UART_RTS_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Complementation's parameter. + * @param param :Data Complementation's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataComplementation"UART_DATA_COMPLEMENTION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_COMPLEMENTION_DISABLE: + case UART_DATA_COMPLEMENTION_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataDirection"UART_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_DIRECTION_LSB: + case UART_DATA_DIRECTION_MSB: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Stop Bit's parameter. + * @param param :Stop Bit's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_StopBit"UART_STOP_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_STOP_BIT_1: + case UART_STOP_BIT_2: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ParityBit"UART_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PARITY_BIT_ODD: + case UART_PARITY_BIT_EVEN: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ParityEnable"UART_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PARITY_DISABLE: + case UART_PARITY_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataLength"UART_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_length(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_LENGTH_7: + case UART_DATA_LENGTH_8: + case UART_DATA_LENGTH_9: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level Range's parameter. + * @param param :Tx Fill Level Range's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + /*--- Now, UART_TX_FILL_RANGE_MIN is 0. ---*/ +#if 0 + if ((UART_TX_FILL_RANGE_MIN <= param) && (param <= UART_TX_FILL_RANGE_MAX)) +#else + if (param <= UART_TX_FILL_RANGE_MAX) +#endif + { + result = UART_PARAM_OK; + } + + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if ((UART_RX_FILL_RANGE_MIN <= param) && (param <= UART_RX_FILL_RANGE_MAX)) { + result = UART_PARAM_OK; + } + + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxFIFOInterrupt"UART_TX_FIFO_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_TX_FIFO_INT_DISABLE: + case UART_TX_FIFO_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_TX_INT_DISABLE: + case UART_TX_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxFIFOInterrupt"UART_RX_FIFO_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RX_FIFO_INT_DISABLE: + case UART_RX_FIFO_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxInterrupt"UART_RX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RX_INT_DISABLE: + case UART_RX_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ErrorInterrupt"UART_ERR_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_err_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_ERR_INT_DISABLE: + case UART_ERR_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Prescaler's parameter. + * @param param :Prescaler's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_Prescaler"UART_PLESCALER_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_prescaler(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PLESCALER_1: + case UART_PLESCALER_2: + case UART_PLESCALER_4: + case UART_PLESCALER_8: + case UART_PLESCALER_16: + case UART_PLESCALER_32: + case UART_PLESCALER_64: + case UART_PLESCALER_128: + case UART_PLESCALER_256: + case UART_PLESCALER_512: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Division's parameter. + * @param param :Division's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_Division"UART_DIVISION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_division(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DIVISION_DISABLE: + case UART_DIVISION_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range K's parameter. + * @param param :Range K's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RangeK"UART_RANGE_K_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + /*--- Now, UART_RANGE_K_MIN is 0. ---*/ +#if 0 + if ((UART_RANGE_K_MIN <= param) && (param <= UART_RANGE_K_MAX)) +#else + if (param <= UART_RANGE_K_MAX) +#endif + { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range N's parameter. + * @param param :Range N's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RangeN"UART_RANGE_N_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if ((UART_RANGE_N_MIN <= param) && (param <= UART_RANGE_N_MAX)) { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for transmit. + * @param param :Num of buff. + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if (param != 0) { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for receive. + * @param param :Num of buff. + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if (param >= 8) { + result = UART_PARAM_OK; + } + + return (result); +} +#endif /* #ifdef __DEBUG__ */ + +/*--------------------------------------------------*/ +/** + * @brief Convert Tx FIFO fill level to register. + * @param level :Fill Level. + * @retval Register value. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level) +{ + uint32_t result = (level << 12); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Convert Rx FIFO fill level to register. + * @param level :Fill Level. + * @retval Register value. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level) +{ + uint32_t result; + + if (level < 8) { + result = (level << 8); + } else { + result = 0; + } + + return (result); +} + +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) +/*--------------------------------------------------*/ +/** + * @brief Check the within error margin. + * @param boudrate :Boudrate(bps). + * @param clock :Clock(hz). + * @param p_clk :Select Clock Setting. + * @param boudrate :Boudrate(bps). + * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" + * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" + * @param p_range64 :Error range(after fixed point bit shift). + * @retval TXZ_SUCCESS :Within error margin. + * @retval TXZ_ERROR :Without error margin. + * @note For N+(64-K)/64 division. + */ +/*--------------------------------------------------*/ +static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) +{ + TXZ_Result result = TXZ_ERROR; + uint64_t boud64 = 0; + uint64_t tx64 = 0; + uint64_t work64 = 0; + + /* phi Tx */ + uint32_t prescaler = (p_clk->prsel >> 4); + + work64 = (uint64_t)((uint64_t)1 << prescaler); + tx64 = (uint64_t)((uint64_t)clock << (UART_CFG_BOUDRATE_FIXED_POINT_BIT + 2)); + tx64 /= work64; + + /* Bourate */ + boud64 = (uint64_t)((uint64_t)boudrate << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + *p_range64 = ((boud64 / 100) * UART_CFG_BOUDRATE_ERROR_RANGE); + /* BourateX */ + work64 = (uint64_t)((uint64_t)n << 6); + work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); + work64 = (tx64 / work64); + if (boud64 >= *p_range64) { + if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) { + if (boud64 < work64) { + *p_range64 = (work64 - boud64); + } else { + *p_range64 = (boud64 - work64); + } + result = TXZ_SUCCESS; + } + } + + return (result); +} +#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + +/** + * @} + */ /* End of group UART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the UART object. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_init(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(check_param_prescaler(p_obj->init.clock.prsel)); + assert_param(check_param_division(p_obj->init.boudrate.ken)); + assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); + assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); + assert_param(check_param_tx_int(p_obj->init.inttx)); + assert_param(check_param_rx_int(p_obj->init.intrx)); + assert_param(check_param_err_int(p_obj->init.interr)); + assert_param(check_param_tx_fifo_int(p_obj->init.txfifo.inttx)); + assert_param(check_param_tx_fill_level_range(p_obj->init.txfifo.level)); + assert_param(check_param_rx_fifo_int(p_obj->init.rxfifo.intrx)); + assert_param(check_param_rx_fill_level_range(p_obj->init.rxfifo.level)); + assert_param(check_param_noize_filter(p_obj->init.nf)); + assert_param(check_param_cts_handshake(p_obj->init.ctse)); + assert_param(check_param_rts_handshake(p_obj->init.rtse)); + assert_param(check_param_data_complemention(p_obj->init.iv)); + assert_param(check_param_data_direction(p_obj->init.dir)); + assert_param(check_param_stop_bit(p_obj->init.sblen)); + assert_param(check_param_parity_bit(p_obj->init.even)); + assert_param(check_param_parity_enable(p_obj->init.pe)); + assert_param(check_param_data_length(p_obj->init.sm)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* SW Reset */ + /*------------------------------*/ + /*--- UARTxSWRST ---*/ + /* SW Reset initializes UARTxTRANS, UARTxDR, UARTxSR, UARTxERR. */ + /* Wait to "SWRSTF = 0". */ + while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + /* no process */ + } + /* Write to SWRST(=10). */ + p_obj->p_instance->SWRST = UARTxSWRST_SWRST_10; + /* Write to SWRST(=01). */ + p_obj->p_instance->SWRST = UARTxSWRST_SWRST_01; + /* Wait to "SWRSTF = 0". */ + while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + /* no process */ + } + /*------------------------------*/ + /* FIFO Clear */ + /*------------------------------*/ + /*--- UARTxFIFOCLR ---*/ + /* Write to TFCLR(=1), and RFCLR(=1) */ + p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- UARTxCLK ---*/ + /* Reflecting "p_obj->init.clk" */ + p_obj->p_instance->CLK = (p_obj->init.clock.prsel & UART_UARTxCLK_MASK); + /*--- UARTxBRD ---*/ + /* Reflecting "p_obj->init.brd" */ + /* Be careful, BRK needs to bit shit. */ + { + uint32_t brk = (p_obj->init.boudrate.brk << 16); + p_obj->p_instance->BRD = (p_obj->init.boudrate.ken | brk | p_obj->init.boudrate.brn); + } + /*--- UARTxCR0 ---*/ + /* Reflecting "p_obj->init.cnt0" */ + p_obj->p_instance->CR0 = (p_obj->init.hct | p_obj->init.hcm | + p_obj->init.hcc | p_obj->init.lbc | + p_obj->init.nf | p_obj->init.ctse | + p_obj->init.rtse | p_obj->init.iv | + p_obj->init.dir | p_obj->init.sblen | + p_obj->init.even | p_obj->init.pe | + p_obj->init.sm); + /*--- UARTxCR1 ---*/ + /* Reflecting "p_obj->init.cnt1" */ + /* Fixed: "DMATE=0", "DMARE=0". */ + /* Be careful, "TIL", "RIL" need to bit shit. */ + p_obj->p_instance->CR1 = (convert_tx_fifo_fill_level_to_reg(p_obj->init.txfifo.level) | + convert_rx_fifo_fill_level_to_reg(p_obj->init.rxfifo.level) | + p_obj->init.txfifo.inttx | p_obj->init.inttx | + p_obj->init.rxfifo.intrx | p_obj->init.intrx | + p_obj->init.interr); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the UART object. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_deinit(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*--- UARTxCR1 ---*/ + p_obj->p_instance->CR1 = 0; + /*--- UARTxCR0 ---*/ + p_obj->p_instance->CR0 = 0; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_discard_transmit(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t trans = 0; + uint32_t count = 10000000; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Read current UARTxTRANS value. */ + trans = p_obj->p_instance->TRANS; + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); + while ((p_obj->p_instance->SR & UART_TX_STATE_MASK) == UART_TX_STATE_RUN) { + if (--count == 0) { + break; + } + } + /*--- UARTxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR); + /*--- UARTxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (UARTxERR_TRGERR_W_CLEAR); + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /* Return RXE setting to UARTxTRANS */ + p_obj->p_instance->TRANS = (trans & UARTxTRANS_RXE_MASK); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_discard_receive(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t trans = 0; + uint32_t count = 10000000; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Read current UARTxTRANS value. */ + trans = p_obj->p_instance->TRANS; + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Clear the receive's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); + while ((p_obj->p_instance->SR & UART_RX_STATE_MASK) == UART_RX_STATE_RUN) { + if (--count == 0) { + break; + } + } + /*--- UARTxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to OVRERR(=1), PERR(=1), and FERR(=1), BERR(=1) */ + p_obj->p_instance->ERR = (UARTxERR_OVRERR_W_CLEAR | UARTxERR_PERR_W_CLEAR | + UARTxERR_FERR_W_CLEAR | UARTxERR_BERR_W_CLEAR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /* Return TXE setting to UARTxTRANS */ + p_obj->p_instance->TRANS = (trans & (UARTxTRANS_BK_MASK | UARTxTRANS_TXTRG_MASK | UARTxTRANS_TXE_MASK)); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :UART object. + * @param p_info :The information of transmit data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + assert_param(check_param_tx_buff_num(p_info->tx16.num)); + } else { + /* 7/8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + assert_param(check_param_tx_buff_num(p_info->tx8.num)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + } else { + /* 7/8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /*--- UARTxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + uint32_t tlvl = (p_obj->p_instance->SR & UARTxSR_TLVL_MASK); + tlvl >>= 8; + /* FIFO Max = UART_TX_FIFO_MAX */ + if (tlvl > UART_TX_FIFO_MAX) { + tlvl = UART_TX_FIFO_MAX; + } + /* Empty FIFO Num */ + { + uint32_t work = tlvl; + tlvl = (UART_TX_FIFO_MAX - work); + } + /*--- UARTxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_7: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=1). */ + /* Bitband Access. */ + enable_UARTxTRANS_TXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :UART object. + * @param p_info :The information of receive buffer. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref UART_FifoMax) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + assert_param(check_param_rx_buff_num(p_info->rx16.num)); + } else { + /* 7/8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + assert_param(check_param_rx_buff_num(p_info->rx8.num)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + } else { + /* 7/8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to RXE(=1). */ + /* Bitband Access. */ + enable_UARTxTRANS_RXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_transmit_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current UARTxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) { + /*---- UARTxSR ---*/ + /* Check the transmit's end flag. */ + if (((status & UARTxSR_TXEND_MASK) == UARTxSR_TXEND_R_END) || + ((status & UARTxSR_TXFF_MASK) == UARTxSR_TXFF_R_REACHED)) { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + uint32_t tlvl = (status & UARTxSR_TLVL_MASK); + tlvl >>= 8; + /* FIFO Max = UART_TX_FIFO_MAX */ + if (tlvl > UART_TX_FIFO_MAX) { + tlvl = UART_TX_FIFO_MAX; + } + /* Get the empty num in FIFO. */ + { + uint32_t work = tlvl; + tlvl = (UART_TX_FIFO_MAX - work); + } + if (tlvl == UART_TX_FIFO_MAX) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + break; + default: + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + break; + } + } + if (txDone == TXZ_DONE) { + /*=== Transmit Done!! ===*/ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != UART_NULL) { + /* Call the transmit handler with TXZ_SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- UARTxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_7: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_receive_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current UARTxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) { + /* Check the receive's end flag. */ + if (((status & UARTxSR_RXEND_MASK) == UARTxSR_RXEND_R_END) || + ((status & UARTxSR_RXFF_MASK) == UARTxSR_RXFF_R_REACHED)) { + /* Read FIFO fill level. */ + uint32_t rlvl = (status & UARTxSR_RLVL_MASK); + /* FIFO Max = UART_RX_FIFO_MAX */ + if (rlvl > UART_RX_FIFO_MAX) { + rlvl = UART_RX_FIFO_MAX; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) { + uint32_t i; + for (i = 0; i < rlvl; i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + *(p_obj->receive.info.rx16.p_data + i) = (uint16_t)(p_obj->p_instance->DR & UARTxDR_DR_9BIT_MASK); + break; + case UART_DATA_LENGTH_8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_8BIT_MASK); + break; + case UART_DATA_LENGTH_7: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_7BIT_MASK); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != UART_NULL) { + uart_receive_t param; + + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + } else { + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + } + /* Call the receive handler with TXZ_SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_error_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current UARTxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- UARTxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & UARTxERR_TRGERR_MASK) == UARTxERR_TRGERR_R_ERR) { + /*------------------------------*/ + /* Transmit Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) { + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != UART_NULL) { + /* Call the transmit handler with TXZ_ERROR. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* OVRERR */ + if ((error & UARTxERR_OVRERR_MASK) == UARTxERR_OVRERR_R_ERR) { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & UARTxERR_PERR_MASK) == UARTxERR_PERR_R_ERR) { + err = TXZ_ERROR; + } + /* FERR */ + if ((error & UARTxERR_FERR_MASK) == UARTxERR_FERR_R_ERR) { + err = TXZ_ERROR; + } + /* BERR */ + if ((error & UARTxERR_BERR_MASK) == UARTxERR_BERR_R_ERR) { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != UART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, UART_NULL); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref UART_SettingEnable. | + * | 30-16 | - | - | + * | 15 | TXRUN | Transmitting State Flag. Use @ref UART_TxState. | + * | 14 | TXEND | Transmitting Done Flag. Use @ref UART_TxDone. | + * | 13 | TXFF | Reach Transmitting Fill Level Flag. Use @ref UART_TxReachFillLevel. | + * | 12 | - | - | + * | 11-8 | TLVL | Current Transmitting FIFO Level. Use @ref UART_TxFifoLevel | + * | 7 | RXRUN | Receive State Flag. Use @ref UART_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref UART_RxDone. | + * | 5 | RXFF | Reach Receive Fill Level Flag. Use @ref UART_RxReachFillLevel | + * | 4 | - | - | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref UART_RxFifoLevel | + * + * @param p_obj :UART object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Read current UARTxSR. */ + *p_status = p_obj->p_instance->SR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-5 | - | - | + * | 4 | TRGERR | Transmitting Trigger Error. Use @ref UART_TriggerErr. | + * | 3 | OVRERR | Overrun Error. Use @ref UART_OverrunErr. | + * | 2 | PERR | Parity Error. Use @ref UART_ParityErr. | + * | 1 | FERR | Framing Error. Use @ref UART_FramingErr. | + * | 0 | BERR | Break Error Flag. Use @ref UART_BreakErr. | + * + * @param p_obj :UART object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_error)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Error Read */ + /*------------------------------*/ + /*--- UARTxERR ---*/ + /* Read current UARTxERR. */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get the setting of boudrate. + * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". + * @param p_clk :Select Clock Setting. + * @param boudrate :Boudrate(bps). + * @param p_brd :Save area for Division Setting. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Not support setting. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_brd) +{ + TXZ_Result result = TXZ_ERROR; +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) + uint64_t tx = 0; + uint64_t work = 0; + uint64_t range64 = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_clk)); + assert_param(IS_POINTER_NOT_NULL(p_brd)); + /* Check the parameter of UARTxCLK. */ +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Calculate Division Setting */ + /*------------------------------*/ + if ((clock > 0) && (boudrate > 0)) { + /*--- phi Tx ---*/ + uint32_t prescaler = (p_clk->prsel >> 4); + + work = (uint64_t)((uint64_t)1 << prescaler); + tx = (uint64_t)((uint64_t)clock << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + tx /= work; + + /*--- N+(64-K)/64 division ---*/ + { + uint8_t k = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + + work = ((uint64_t)boudrate); + tx /= work; + tx >>= 4; + for (k = UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) { + work = tx + (uint64_t)k; + if (work >= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT)) { + work -= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + work >>= UART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ + if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { + uint64_t workRange = 0; + + /* Verification */ + if (verification_boudrate64(clock, p_clk, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) { +#if (UART_CFG_GET_BOUDRATE_TYPE == UART_CFG_GET_BOUDRATE_TYPE_ALL) + /* Compare the previous range. */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + } else { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + result = TXZ_SUCCESS; +#else + /* Finish!! */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + } else { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + result = TXZ_SUCCESS; + loopBreak = TXZ_DONE; +#endif + } + } + } + } + } + } +#endif /* (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + + return (result); +} + +/** + * @} + */ /* End of group UART_Exported_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PeripheralNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PeripheralNames.h new file mode 100644 index 00000000000..532e9d62299 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PeripheralNames.h @@ -0,0 +1,193 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SERIAL_0 = 0, + SERIAL_1, + SERIAL_2, + SERIAL_3, + SERIAL_4, + SERIAL_5, + SERIAL_6, + SERIAL_7, + INVALID_SERIAL = (int)NC +} UARTName; + +typedef enum { + DAC_0 = 0, + DAC_1, + INVALID_DAC = (int)NC +} DACName; + +typedef enum { + PWM_0 = 0, + PWM_1, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11, + PWM_12, + INVALID_PWM = (int)NC +} PWMName; + +typedef enum { + ADC_A0 = 0, + ADC_A1, + ADC_A2, + ADC_A3, + ADC_A4, + ADC_A5, + ADC_A6, + ADC_A7, + ADC_A8, + ADC_A9, + ADC_A10, + ADC_A11, + ADC_A12, + ADC_A13, + ADC_A14, + ADC_A15, + ADC_A16, + ADC_A17, + ADC_A18, + ADC_A19, + ADC_A20, + ADC_A21, + ADC_A22, + ADC_A23, + INVALID_ADC = (int)NC +} ADCName; + +typedef enum { + I2C_0 = 0, + I2C_1, + I2C_2, + I2C_3, + I2C_4, + INVALID_I2C = (int)NC +} I2CName; + +typedef enum { + SPI_0 = 0, + SPI_1, + SPI_2, + SPI_3, + SPI_4, + SPI_5, + SPI_6, + SPI_7, + SPI_8, + INVALID_SPI = (int)NC +} SPIName; + +typedef enum { + GPIO_IRQ_0 = 0, + GPIO_IRQ_1, + GPIO_IRQ_2, + GPIO_IRQ_3, + GPIO_IRQ_4, + GPIO_IRQ_5, + GPIO_IRQ_6, + GPIO_IRQ_7, + GPIO_IRQ_8, + GPIO_IRQ_9, + GPIO_IRQ_A, + GPIO_IRQ_B, + GPIO_IRQ_C, + GPIO_IRQ_D, + GPIO_IRQ_E, + GPIO_IRQ_F, + INVALID_GPIO_IRQ = (int)NC +} GPIO_IRQName; + +// DAP UART +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#define SERIAL_TX PU0 +#define SERIAL_RX PU1 + +#define STDIO_UART SERIAL_4 + +// TxD RxD +#define MBED_UART0 PE3, PE2 +#define MBED_UART1 PH1, PH0 +#define MBED_UART2 PG1, PG0 +#define MBED_UART3 PU7, PU6 +#define MBED_UART4 PM1, PM0 +#define MBED_UART5 PJ1, PJ0 +#define MBED_UART6 PG4, PG5 +#define MBED_UART7 PJ6, PJ7 +#define MBED_UARTUSB USBTX, USBRX + +// SDA SCK +#define MBED_I2C0 PG2, PG3 +#define MBED_I2C1 PF2, PF3 +#define MBED_I2C2 PG4, PG5 +#define MBED_I2C3 PJ6, PJ7 +#define MBED_I2C4 PJ3, PJ2 + +// MOSI, MISO, SCLK SS +#define MBED_SPI0 PA3, PA2, PA1, PA0 +#define MBED_SPI1 PL3, PL2, PL1, PL0 +#define MBED_SPI2 PA4, PA5, PA6, PA7 +#define MBED_SPI3 PK4, PK5, PK6, PK7 +#define MBED_SPI4 PD3, PD2, PD1, PD0 +#define MBED_SPI5 PV5, PV4, PV6, PV7 +#define MBED_SPI6 PM0, PM1, PM2, PM3 +#define MBED_SPI7 PM7, PM6, PM5, PM4 +#define MBED_SPI8 PW3, PW2, PW1, PW0 + +#define MBED_ANALOGIN0 A0 +#define MBED_ANALOGIN1 A1 +#define MBED_ANALOGIN2 A2 +#define MBED_ANALOGIN3 A3 +#define MBED_ANALOGIN4 A4 +#define MBED_ANALOGIN5 A5 + +#define MBED_PWMOUT0 PA5 +#define MBED_PWMOUT1 PB2 +#define MBED_PWMOUT2 PB4 +#define MBED_PWMOUT3 PD2 +#define MBED_PWMOUT4 PD4 +#define MBED_PWMOUT5 PE1 +#define MBED_PWMOUT6 PE6 +#define MBED_PWMOUT7 PC2 +#define MBED_PWMOUT8 PL6 +#define MBED_PWMOUT9 PC4 +#define MBED_PWMOUT10 PM2 +#define MBED_PWMOUT11 PU0 +#define MBED_PWMOUT12 PU6 + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PinNames.h new file mode 100644 index 00000000000..5257e5cc967 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PinNames.h @@ -0,0 +1,144 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xFF) +#define PIN_POS(X) ((uint32_t)(X) & 0x7) + +// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction +#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0)) +#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) +#define PIN_DIR(X) ((X) & 0xffff) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INOUT +} PinDirection; + +typedef enum { + // TMPM4G9 Pin Names + PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, + PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, PD6, PD7, + PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, + PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, + PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7, + PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, PN6, PN7, + PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7, + PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7, + PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, + PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5, PU6, PU7, + PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7, + PW0 = 18 << 3, PW1, PW2, PW3, PW4, PW5, PW6, PW7, + PY0 = 19 << 3, PY1, PY2, PY3, PY4, + + // External data bus Pin Names + D0 = PJ1, + D1 = PJ0, + D2 = PF4, + D3 = PB2, + D4 = PF5, + D5 = PB4, + D6 = PC2, + D7 = PF6, + D8 = PA4, + D9 = PC4, + D10 = PA0, + D11 = PA3, + D12 = PA2, + D13 = PA1, + D14 = PG2, + D15 = PG3, + + // Analogue in pins + A0 = PN0, + A1 = PN1, + A2 = PN2, + A3 = PN3, + A4 = PN4, + A5 = PN5, + + // USB2_UART + CONSOLE_TX = PU0, + CONSOLE_RX = PU1, + MBEDIF_TXD = CONSOLE_TX, + MBEDIF_RXD = CONSOLE_RX, + + MBED_CONF_APP_UART0_TX = PE3, + MBED_CONF_APP_UART0_RX = PE2, + + // Switches + SW1 = PL4, + SW2 = PL5, + SW3 = PV0, + SW4 = PV1, + + // I2C pins + SDA = PG2, + SCL = PG3, + + // Analogue out + DAC0 = PT0, + DAC1 = PT1, + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + +// LED definitions +#define LED1 PE4 +#define LED2 PE5 +#define LED3 PE6 +#define LED4 PE7 + +// Standardized button names +#define BUTTON1 SW1 +#define BUTTON2 SW2 +#define BUTTON3 SW3 +#define BUTTON4 SW4 + +//I2C +#define I2C_SDA SDA +#define I2C_SCL SCL + +typedef enum { + PullUp = 0, + PullDown, + PullNone, + OpenDrain, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PortNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PortNames.h new file mode 100644 index 00000000000..3ccc362131f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PortNames.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB, + PortC, + PortD, + PortE, + PortF, + PortG, + PortH, + PortJ, + PortK, + PortL, + PortM, + PortN, + PortP, + PortR, + PortT, + PortU, + PortV, + PortW, + PortY +} PortName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogin_api.c new file mode 100644 index 00000000000..1341823f781 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogin_api.c @@ -0,0 +1,146 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogin_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_wait_api.h" +#include "mbed_error.h" +#include "txz_adc_include.h" + +#define ADC_12BIT_RANGE 0xFFF +#define CONVERSION_FLAG 0x4 + +static const PinMap PinMap_ADC[] = { + {PN0, ADC_A0, PIN_DATA(0, 0)}, + {PN1, ADC_A1, PIN_DATA(0, 0)}, + {PN2, ADC_A2, PIN_DATA(0, 0)}, + {PN3, ADC_A3, PIN_DATA(0, 0)}, + {PN4, ADC_A4, PIN_DATA(0, 0)}, + {PN5, ADC_A5, PIN_DATA(0, 0)}, + {PN6, ADC_A6, PIN_DATA(0, 0)}, + {PN7, ADC_A7, PIN_DATA(0, 0)}, + {PP0, ADC_A8, PIN_DATA(0, 0)}, + {PP1, ADC_A9, PIN_DATA(0, 0)}, + {PP2, ADC_A10, PIN_DATA(0, 0)}, + {PP3, ADC_A11, PIN_DATA(0, 0)}, + {PP4, ADC_A12, PIN_DATA(0, 0)}, + {PP5, ADC_A13, PIN_DATA(0, 0)}, + {PP6, ADC_A14, PIN_DATA(0, 0)}, + {PP7, ADC_A15, PIN_DATA(0, 0)}, + {PR0, ADC_A16, PIN_DATA(0, 0)}, + {PR1, ADC_A17, PIN_DATA(0, 0)}, + {PR2, ADC_A18, PIN_DATA(0, 0)}, + {PR3, ADC_A19, PIN_DATA(0, 0)}, + {PR4, ADC_A20, PIN_DATA(0, 0)}, + {PR5, ADC_A21, PIN_DATA(0, 0)}, + {PR6, ADC_A22, PIN_DATA(0, 0)}, + {PR7, ADC_A23, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +void analogin_init(analogin_t *obj, PinName pin) +{ + // Check that pin belong to ADC module + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + + MBED_ASSERT(obj->adc != (ADCName)NC); + + // Enable ADC clock supply + TSB_CG_FSYSMENA_IPMENA03 = TXZ_ENABLE; + TSB_CG_SPCLKEN_ADCKEN = TXZ_ENABLE; + TSB_CG_SPCLKEN_TRCKEN = TXZ_ENABLE; + + // Enable clock for GPIO + if (obj->adc <= ADC_A7) { + TSB_CG_FSYSMENB_IPMENB14 = TXZ_ENABLE; + } else if (obj->adc <= ADC_A15) { + TSB_CG_FSYSMENB_IPMENB15 = TXZ_ENABLE; + } else { + TSB_CG_FSYSMENB_IPMENB16 = TXZ_ENABLE; + } + + // Set pin function as ADC + pinmap_pinout(pin, PinMap_ADC); + + // Initialize + obj->p_adc.p_instance = TSB_ADA; + obj->p_adc.init.clk.exaz0 = ADC_SAMPLING_PERIOD0_XN; + obj->p_adc.init.clk.exaz1 = ADC_SAMPLING_PERIOD1_XN; + obj->p_adc.init.clk.vadcld = ADC_SCLK_5; /*less than 40MHz*/ + obj->p_adc.init.clk.sampling_select = 0; + obj->p_adc.init.mod1 = ADC_MOD1_SCLK_4; + obj->p_adc.init.mod2 = ADC_MOD2_SET; + obj->p_adc.handler.single = NULL; + obj->p_adc.handler.continuity = NULL; + obj->p_adc.handler.trigger = NULL; + obj->p_adc.handler.highpriority = NULL; + + if (adc_init(&obj->p_adc) != TXZ_SUCCESS) { + error("Failed : ADC Initialization"); + } + + // ADC channel setting + obj->param.interrupt = ADC_INT_DISABLE; + obj->param.type = ADC_CONVERSION_SGL; + obj->param.ain = obj->adc; + + if (adc_channel_setting(&obj->p_adc, obj->param.ain, &obj->param) != TXZ_SUCCESS) { + error("Failed : ADC channel setting"); + } +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint32_t adc_result = 0; + + wait_us(700); // Wait at least 700us to ensure the voltage is stable + // Assert that ADC channel is valid + MBED_ASSERT(obj->adc != (ADCName)NC); + + if (adc_start(&obj->p_adc) == TXZ_SUCCESS) { + // adc started + } + + // Wait for Continuous conversion program flag clear. + while ((obj->p_adc.p_instance->ST & CONVERSION_FLAG)) { + // Do nothing + } + + if (adc_channel_get_value(&obj->p_adc, obj->param.ain, &adc_result) != TXZ_SUCCESS) { + error("Failed : To read ADC converted result"); + } + + if (adc_stop(&obj->p_adc) != TXZ_SUCCESS) { + error("Failed : To Stop ADC Conversion"); + } + + return (uint16_t)adc_result; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = 0; + + value = analogin_read_u16(obj); + + return (float)(value * (1.0f / (float)ADC_12BIT_RANGE)); +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogout_api.c new file mode 100644 index 00000000000..d40de120233 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogout_api.c @@ -0,0 +1,129 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "cmsis.h" +#include "analogout_api.h" +#include "pinmap.h" + +#define REG_DAC_DAxCR_REN_DISABLE ((uint32_t)0x00000000) // DAC Control Disable. +#define REG_DAC_DAxCR_REN_ENABLE ((uint32_t)0x00000001) // DAC Control Enable. +#define DAC0_CLR_IN_CLR_OUT (1) // As per TRM DAC pin inout mode should be neither in nor out +#define DAC1_CLR_IN_CLR_OUT (2) +#define MAX_ANALOG_VAL (1.0f) +#define MIN_ANALOG_VAL (0.0f) + + +static const PinMap PinMap_DAC[] = { + {PT0, DAC_0, PIN_DATA(0, 1)}, + {PT1, DAC_1, PIN_DATA(0, 1)}, + {NC, NC, 0} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + DACName dac_name = (DACName)pinmap_peripheral(pin, PinMap_DAC); + + MBED_ASSERT(dac_name != (DACName)NC); + + obj->dac = dac_name; + + switch (dac_name) { + case DAC_0: + obj->DACx = TSB_DA0; + // Enable clock for DAC0 and Port T + TSB_CG_FSYSMENA_IPMENA04 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE; + break; + case DAC_1: + obj->DACx = TSB_DA1; + // Enable clock for DAC1 and Port T + TSB_CG_FSYSMENA_IPMENA05 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE; + break; + default: + break; + } + + + pinmap_pinout(pin, PinMap_DAC); + + // DAC pins as neither input and nor output + if (dac_name == DAC_0) { + TSB_PT->CR &= ~(DAC0_CLR_IN_CLR_OUT); + TSB_PT->IE &= ~(DAC0_CLR_IN_CLR_OUT); + } else if (dac_name == DAC_1) { + TSB_PT->CR &= ~(DAC1_CLR_IN_CLR_OUT); + TSB_PT->IE &= ~(DAC1_CLR_IN_CLR_OUT); + } else { + return; + } + + obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE; +} + +void analogout_free(dac_t *obj) +{ + obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE; + obj->dac = (DACName)NC; +} + +void analogout_write(dac_t *obj, float value) +{ + uint8_t outputcode = 0; + obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE; + if (value < 0.0f) { + value = 0.0f; + } else { + if (value >= 1.0f) { + value = 1.0f; + } + } + outputcode = (uint8_t)(value * 255.0f); + obj->DACx->REG = outputcode; +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + // Writing higher 8-bits to Data Register + obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE; + obj->DACx->REG = (uint8_t)(value & 0xFF); +} + +float analogout_read(dac_t *obj) +{ + float result = 0.0; + uint32_t value = 0; + + value = ((obj->DACx->REG) & (0xFF)); + result = ((float)value / 255.0f); + + return result; +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + uint16_t value = 0; + + value = (uint16_t)((obj->DACx->REG) & (0xFF)); + return value; + // Upper and lower byte stored with read value +} + +const PinMap *analogout_pinmap() +{ + return PinMap_DAC; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device.h new file mode 100644 index 00000000000..3390d2b9ec2 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device.h @@ -0,0 +1,26 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define TRANSACTION_QUEUE_SIZE_SPI 4 +#define DEVICE_ID_LENGTH 32 + +#include +#include "objects.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TMPM4GR.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TMPM4GR.h new file mode 100644 index 00000000000..f8dae225aa4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TMPM4GR.h @@ -0,0 +1,7346 @@ +/** + ******************************************************************************* + * @file TMPM4GR.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4GR' Device Series + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER + * @{ + */ + +/** @addtogroup TMPM4GR + * @{ + */ + +#ifndef __TMPM4GR_H__ +#define __TMPM4GR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** TMPM4GR Specific Interrupt Numbers *******************************************************************/ + INT00_IRQn = 0, /*!< Interrupt pin 00a/00b */ + INT01_IRQn = 1, /*!< Interrupt pin 01a/00b */ + INT02_IRQn = 2, /*!< Interrupt pin 02a/00b */ + INT03_IRQn = 3, /*!< Interrupt pin 03a/03b */ + INT04_IRQn = 4, /*!< Interrupt pin 04a/04b */ + INT05_IRQn = 5, /*!< Interrupt pin 05a/05b */ + INT06_IRQn = 6, /*!< Interrupt pin 06a/06b */ + INT07_IRQn = 7, /*!< Interrupt pin 07a/07b */ + INT08_IRQn = 8, /*!< Interrupt pin 08a/08b */ + INT09_IRQn = 9, /*!< Interrupt pin 09a/09b */ + INT10_IRQn = 10, /*!< Interrupt pin 10a/10b */ + INT11_IRQn = 11, /*!< Interrupt pin 11a/11b */ + INT12_IRQn = 12, /*!< Interrupt pin 12a/12b */ + INT13_IRQn = 13, /*!< Interrupt pin 13a/13b */ + INT14_IRQn = 14, /*!< Interrupt pin 14a/14b */ + INT15_IRQn = 15, /*!< Interrupt pin 15a/15b */ + INTRTC_IRQn = 16, /*!< Real time clock(XHz) interrupt */ + INTCEC0RX_IRQn = 17, /*!< CEC reception interrupt (channel 0) */ + INTCEC0TX_IRQn = 18, /*!< CEC transmission interrupt (channel 0) */ + INTISDA_IRQn = 19, /*!< Interval Sensing Detector interrupt (Unit A) */ + INTISDB_IRQn = 20, /*!< Interval Sensing Detector interrupt (Unit B) */ + INTISDC_IRQn = 21, /*!< Interval Sensing Detector interrupt (Unit C) */ + INTRMC0_IRQn = 22, /*!< Remote control reception interrupt 0 */ + INTRMC1_IRQn = 23, /*!< Remote control reception interrupt 1 */ + INTLTTMR0_IRQn = 24, /*!< Long Term Timer Interrupt(channel 0) */ + INTHDMAATC_IRQn = 25, /*!< HDMA complete of transfer(Unit A) */ + INTHDMAAERR_IRQn = 26, /*!< HDMA transfer error(Unit A) */ + INTHDMABTC_IRQn = 27, /*!< HDMA end of transfer(Unit B) */ + INTHDMABERR_IRQn = 28, /*!< HDMA transfer error(Unit B) */ + INTMDMAATC_IRQn = 29, /*!< MDMA complete of transfer(Unit A) */ + INTT32A00_A_CT_IRQn = 30, /*!< T32A00 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A00_B_C01_CPC_IRQn = 31, /*!< T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A01_A_CT_IRQn = 32, /*!< T32A01 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A01_B_C01_CPC_IRQn = 33, /*!< T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A02_A_CT_IRQn = 34, /*!< T32A02 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A02_B_C01_CPC_IRQn = 35, /*!< T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A03_A_CT_IRQn = 36, /*!< T32A03 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A03_B_C01_CPC_IRQn = 37, /*!< T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A04_A_CT_IRQn = 38, /*!< T32A04 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A04_B_C01_CPC_IRQn = 39, /*!< T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A05_A_CT_IRQn = 40, /*!< T32A05 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A05_B_C01_CPC_IRQn = 41, /*!< T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A06_A_CT_IRQn = 42, /*!< T32A06 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A06_B_C01_CPC_IRQn = 43, /*!< T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A07_A_CT_IRQn = 44, /*!< T32A07 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A07_B_C01_CPC_IRQn = 45, /*!< T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A08_A_CT_IRQn = 46, /*!< T32A08 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A08_B_C01_CPC_IRQn = 47, /*!< T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A09_A_CT_IRQn = 48, /*!< T32A09 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A09_B_C01_CPC_IRQn = 49, /*!< T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A10_A_CT_IRQn = 50, /*!< T32A10 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A10_B_C01_CPC_IRQn = 51, /*!< T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A11_A_CT_IRQn = 52, /*!< T32A11 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A11_B_C01_CPC_IRQn = 53, /*!< T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A12_A_CT_IRQn = 54, /*!< T32A12 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A12_B_C01_CPC_IRQn = 55, /*!< T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A13_A_CT_IRQn = 56, /*!< T32A13 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A13_B_C01_CPC_IRQn = 57, /*!< T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTEMG0_IRQn = 58, /*!< PMD0 EMG interrupt */ + INTOVV0_IRQn = 59, /*!< PMD0 OVV interrupt */ + INTPWM0_IRQn = 60, /*!< PMD0 interrupt */ + INTT0RX_IRQn = 61, /*!< TSPI/SIO reception (channel 0) interrupt */ + INTT0TX_IRQn = 62, /*!< TSPI/SIO transmit (channel 0) interrupt */ + INTT0ERR_IRQn = 63, /*!< TSPI/SIO error (channel 0) interrupt */ + INTT1RX_IRQn = 64, /*!< TSPI/SIO reception (channel 1) interrupt */ + INTT1TX_IRQn = 65, /*!< TSPI/SIO transmit (channel 1) interrupt */ + INTT1ERR_IRQn = 66, /*!< TSPI/SIO error (channel 1) interrupt */ + INTT2RX_IRQn = 67, /*!< TSPI/SIO reception (channel 2) interrupt */ + INTT2TX_IRQn = 68, /*!< TSPI/SIO transmit (channel 2) interrupt */ + INTT2ERR_IRQn = 69, /*!< TSPI/SIO error (channel 2) interrupt */ + INTT3RX_IRQn = 70, /*!< TSPI/SIO reception (channel 3) interrupt */ + INTT3TX_IRQn = 71, /*!< TSPI/SIO transmit (channel 3) interrupt */ + INTT3ERR_IRQn = 72, /*!< TSPI/SIO error (channel 3) interrupt */ + INTT4RX_IRQn = 73, /*!< TSPI/SIO reception (channel 4) interrupt */ + INTT4TX_IRQn = 74, /*!< TSPI/SIO transmit (channel 4) interrupt */ + INTT4ERR_IRQn = 75, /*!< TSPI/SIO error (channel 4) interrupt */ + INTT5RX_IRQn = 76, /*!< TSPI/SIO reception (channel 5) interrupt */ + INTT5TX_IRQn = 77, /*!< TSPI/SIO transmit (channel 5) interrupt */ + INTT5ERR_IRQn = 78, /*!< TSPI/SIO error (channel 5) interrupt */ + INTT6RX_IRQn = 79, /*!< TSPI/SIO reception (channel 6) interrupt */ + INTT6TX_IRQn = 80, /*!< TSPI/SIO transmit (channel 6) interrupt */ + INTT6ERR_IRQn = 81, /*!< TSPI/SIO error (channel 6) interrupt */ + INTT7RX_IRQn = 82, /*!< TSPI/SIO reception (channel 7) interrupt */ + INTT7TX_IRQn = 83, /*!< TSPI/SIO transmit (channel 7) interrupt */ + INTT7ERR_IRQn = 84, /*!< TSPI/SIO error (channel 7) interrupt */ + INTT8RX_IRQn = 85, /*!< TSPI/SIO reception (channel 8) interrupt */ + INTT8TX_IRQn = 86, /*!< TSPI/SIO transmit (channel 8) interrupt */ + INTT8ERR_IRQn = 87, /*!< TSPI/SIO error (channel 8) interrupt */ + INTSMI0_IRQn = 88, /*!< Serial Memory Interface interrupt */ + INTUART0RX_IRQn = 89, /*!< UART reception (channel 0) interrupt */ + INTUART0TX_IRQn = 90, /*!< UART transmit (channel 0) interrupt */ + INTUART0ERR_IRQn = 91, /*!< UART error (channel 0) interrupt */ + INTUART1RX_IRQn = 92, /*!< UART reception (channel 1) interrupt */ + INTUART1TX_IRQn = 93, /*!< UART transmit (channel 1) interrupt */ + INTUART1ERR_IRQn = 94, /*!< UART error (channel 1) interrupt */ + INTUART2RX_IRQn = 95, /*!< UART reception (channel 2) interrupt */ + INTUART2TX_IRQn = 96, /*!< UART transmit (channel 2) interrupt */ + INTUART2ERR_IRQn = 97, /*!< UART error (channel 2) interrupt */ + INTUART3RX_IRQn = 98, /*!< UART reception (channel 3) interrupt */ + INTUART3TX_IRQn = 99, /*!< UART transmit (channel 3) interrupt */ + INTUART3ERR_IRQn = 100, /*!< UART error (channel 3) interrupt */ + INTUART4RX_IRQn = 101, /*!< UART reception (channel 4) interrupt */ + INTUART4TX_IRQn = 102, /*!< UART transmit (channel 4) interrupt */ + INTUART4ERR_IRQn = 103, /*!< UART error (channel 4) interrupt */ + INTUART5RX_IRQn = 104, /*!< UART reception (channel 5) interrupt */ + INTUART5TX_IRQn = 105, /*!< UART transmit (channel 5) interrupt */ + INTUART5ERR_IRQn = 106, /*!< UART error (channel 5) interrupt */ + INTFUART0_IRQn = 107, /*!< FUART interrupt(channel 0) */ + INTFUART1_IRQn = 108, /*!< FUART interrupt(channel 1) */ + INTI2C0NST_IRQn = 109, /*!< I2C0 interrupt / EI2C0 status interrupt */ + INTI2C0ATX_IRQn = 110, /*!< I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C0BRX_IRQn = 111, /*!< I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C0NA_IRQn = 112, /*!< I2C0 NACK detection interrupt */ + INTI2C1NST_IRQn = 113, /*!< I2C1 interrupt / EI2C0 status interrupt */ + INTI2C1ATX_IRQn = 114, /*!< I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C1BRX_IRQn = 115, /*!< I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C1NA_IRQn = 116, /*!< I2C1 NACK detection interrupt */ + INTI2C2NST_IRQn = 117, /*!< I2C2 interrupt / EI2C0 status interrupt */ + INTI2C2ATX_IRQn = 118, /*!< I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C2BRX_IRQn = 119, /*!< I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C2NA_IRQn = 120, /*!< I2C2 NACK detection interrupt */ + INTI2C3NST_IRQn = 121, /*!< I2C3 interrupt / EI2C0 status interrupt */ + INTI2C3ATX_IRQn = 122, /*!< I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C3BRX_IRQn = 123, /*!< I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C3NA_IRQn = 124, /*!< I2C3 NACK detection interrupt */ + INTI2C4NST_IRQn = 125, /*!< I2C4 interrupt / EI2C0 status interrupt */ + INTI2C4ATX_IRQn = 126, /*!< I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C4BRX_IRQn = 127, /*!< I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C4NA_IRQn = 128, /*!< I2C4 NACK detection interrupt */ + INTADACP0_IRQn = 129, /*!< ADC conversion monitoring function interrupt 0 */ + INTADACP1_IRQn = 130, /*!< ADC conversion monitoring function interrupt 1 */ + INTADATRG_IRQn = 131, /*!< ADC conversion triggered by General purpose is finished */ + INTADASGL_IRQn = 132, /*!< ADC conversion triggered by Single program is finished */ + INTADACNT_IRQn = 133, /*!< ADC conversion triggered by Continuity program is finished */ + INTADAHP_IRQn = 134, /*!< ADC high priority AD conversion interrupt */ + INTFLDRDY_IRQn = 135, /*!< Data FLASH Ready interrupt */ + INTFLCRDY_IRQn = 136, /*!< Code FLASH Area0/1 Ready interrupt */ + INTMDMAABERR_IRQn = 139, /*!< MDMA bus error(Unit A) interrupt */ + INTMDMAADERR_IRQn = 140, /*!< MDMA descriptor error(Unit A) interrupt */ + INTI2S0SI_IRQn = 141, /*!< I2S ch0 SI transfer end interrupt */ + INTI2S0SIERR_IRQn = 142, /*!< I2S ch0 SI error interrupt */ + INTI2S0SO_IRQn = 143, /*!< I2S ch0 SO transfer end interrupt */ + INTI2S0SOERR_IRQn = 144, /*!< I2S ch0 SO error interrupt */ + INTI2S1SI_IRQn = 145, /*!< I2S ch1 SI transfer end interrupt */ + INTI2S1SIERR_IRQn = 146, /*!< I2S ch1 SI error interrupt */ + INTI2S1SO_IRQn = 147, /*!< I2S ch1 SO transfer end interrupt */ + INTI2S1SOERR_IRQn = 148, /*!< I2S ch1 SO error interrupt */ + INTFIR0_IRQn = 149, /*!< FIR ch0 interrupt */ + INTTSSI0RX_IRQn = 150, /*!< TSSI ch0 receive interrupt */ + INTTSSI0TX_IRQn = 151, /*!< TSSI ch0 transmission interrupt */ + INTTSSI0ERR_IRQn = 152, /*!< TSSI ch0 error interrupt */ + INTTSSI1RX_IRQn = 153, /*!< TSSI ch1 receive interrupt */ + INTTSSI1TX_IRQn = 154, /*!< TSSI ch1 transmission interrupt */ + INTTSSI1ERR_IRQn = 155, /*!< TSSI ch1 error interrupt */ + INTT32A14_A_IRQn = 168, /*!< T32A14 TimerA all interrupt */ + INTT32A14_B_IRQn = 169, /*!< T32A14 TimerB all interrupt */ + INTT32A14_CT_IRQn = 170, /*!< T32A14 TimerC match, overflow, and underflow Interrupt */ + INTT32A15_A_IRQn = 171, /*!< T32A15 TimerA all interrupt */ + INTT32A15_B_IRQn = 172, /*!< T32A15 TimerB all interrupt */ + INTT32A15_C_IRQn = 173, /*!< T32A15 TimerC all interrupt */ + INTMDMAADISR_IRQn = 174 /*!< MDMAC unit A Descriptor interrupt */ +} IRQn_Type; + +/** Processor and Core Peripheral Section */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_TMPM4Gx.h" /* TMPM4Gx System */ + +/** @addtogroup Device_Peripheral_registers + * @{ + */ + +/** Device Specific Peripheral registers structures */ + +/** + * @brief DMA Controller + */ +typedef struct { + __I uint32_t INTSTATUS; /*!< DMAC Interrupt Status Register */ + __I uint32_t INTTCSTATUS; /*!< DMAC Transfer Completion Interrupt Status Register*/ + __O uint32_t INTTCCLEAR; /*!< DMAC Transfer Completion Interrupt Clear Register*/ + __I uint32_t INTERRORSTATUS; /*!< DMAC Error Interrupt Status Register */ + __O uint32_t INTERRCLR; /*!< DMAC Error Interrupt Clear Register */ + __I uint32_t RAWINTTCSTATUS; /*!< DMAC Raw Transfer Completion Interrupt Status Register*/ + __I uint32_t RAWINTERRORSTATUS; /*!< DMAC Raw Error Interrupt Status Register */ + __I uint32_t ENBLDCHNS; /*!< DMAC Channel Enable Register */ + __IO uint32_t SOFTBREQ; /*!< DMAC Software Burst Transfer Request Register*/ + __IO uint32_t SOFTSREQ; /*!< DMAC Software Single Transfer Request Register*/ + uint32_t RESERVED0[2]; + __IO uint32_t CONFIGURATION; /*!< DMAC Configuration Register */ + uint32_t RESERVED1[51]; + __IO uint32_t C0SRCADDR; /*!< DMAC Channel 0 Transfer Source Address Register*/ + __IO uint32_t C0DESTADDR; /*!< DMAC Channel 0 Transfer Destination Address Register*/ + __IO uint32_t C0LLI; /*!< DMAC Channel 0 Linked List Item Register */ + __IO uint32_t C0CONTROL; /*!< DMAC Channel 0 Control Register */ + __IO uint32_t C0CONFIGURATION; /*!< DMAC Channel 0 Configuration Register */ + uint32_t RESERVED2[3]; + __IO uint32_t C1SRCADDR; /*!< DMAC Channel 1 Transfer Source Address Register*/ + __IO uint32_t C1DESTADDR; /*!< DMAC Channel 1 Transfer Destination Address Register*/ + __IO uint32_t C1LLI; /*!< DMAC Channel 1 Linked List Item Register */ + __IO uint32_t C1CONTROL; /*!< DMAC Channel 1 Control Register */ + __IO uint32_t C1CONFIGURATION; /*!< DMAC Channel 1 Configuration Register */ +} TSB_DMAC_TypeDef; + +/** + * @brief SMIF + */ +typedef struct { + __IO uint32_t MAP0; /*!< SMIF Address Map Control Register 0 */ + __IO uint32_t MAP1; /*!< SMIF Address Map Control Register 1 */ + __IO uint32_t DACR0; /*!< SMIF Direct Access Control Register 0 */ + __IO uint32_t DACR1; /*!< SMIF Direct Access Control Register 1 */ + __IO uint32_t DRCR0; /*!< SMIF Direct Read Control Register 0 */ + __IO uint32_t DRCR1; /*!< SMIF Direct Read Control Register 1 */ + __IO uint32_t DWCR0; /*!< SMIF Direct Write Control Register 0 */ + __IO uint32_t DWCR1; /*!< SMIF Direct Write Control Register 1 */ + uint32_t RESERVED0[248]; + __IO uint32_t RACR0; /*!< SMIF Indirect Access Control Register 0 */ + __IO uint32_t RACR1; /*!< SMIF Indirect Access Control Register 1 */ + __IO uint32_t IOCR; /*!< SMIF Indirect Access I/O Control Register */ + __IO uint32_t OECR; /*!< SMIF Indirect Access Output Enable Register */ + uint32_t RESERVED1[12]; + __IO uint32_t INT; /*!< SMIF Interrupt Control Register */ + __IO uint32_t STAT; /*!< SMIF Status Register */ + uint32_t RESERVED2[14]; + __IO uint32_t SWR; /*!< SMIF Software Reset Register */ + __IO uint32_t ACKR; /*!< SMIF Additional Clock Control Register */ + __IO uint32_t CCOR; /*!< SMIF Serial Clock, CS pin Direction Control Register*/ + __IO uint32_t STPR; /*!< SMIF Forced Stop Control Register */ + uint32_t RESERVED3[28]; + __IO uint32_t PBUF0; /*!< SMIF Indirect Access Primary Buffer Register 0*/ + __IO uint32_t PBUF1; /*!< SMIF Indirect Access Primary Buffer Register 1*/ + __IO uint32_t PBUF2; /*!< SMIF Indirect Access Primary Buffer Register 2*/ + __IO uint32_t PBUF3; /*!< SMIF Indirect Access Primary Buffer Register 3*/ + __IO uint32_t PBUF4; /*!< SMIF Indirect Access Primary Buffer Register 4*/ + __IO uint32_t PBUF5; /*!< SMIF Indirect Access Primary Buffer Register 5*/ + __IO uint32_t PBUF6; /*!< SMIF Indirect Access Primary Buffer Register 6*/ + __IO uint32_t PBUF7; /*!< SMIF Indirect Access Primary Buffer Register 7*/ + uint32_t RESERVED4[56]; + __IO uint32_t SBUF00; /*!< SMIF Indirect Access Secondary Buffer Register 00*/ + __IO uint32_t SBUF01; /*!< SMIF Indirect Access Secondary Buffer Register 01*/ + __IO uint32_t SBUF02; /*!< SMIF Indirect Access Secondary Buffer Register 02*/ + __IO uint32_t SBUF03; /*!< SMIF Indirect Access Secondary Buffer Register 03*/ + __IO uint32_t SBUF04; /*!< SMIF Indirect Access Secondary Buffer Register 04*/ + __IO uint32_t SBUF05; /*!< SMIF Indirect Access Secondary Buffer Register 05*/ + __IO uint32_t SBUF06; /*!< SMIF Indirect Access Secondary Buffer Register 06*/ + __IO uint32_t SBUF07; /*!< SMIF Indirect Access Secondary Buffer Register 07*/ + __IO uint32_t SBUF08; /*!< SMIF Indirect Access Secondary Buffer Register 08*/ + __IO uint32_t SBUF09; /*!< SMIF Indirect Access Secondary Buffer Register 09*/ + __IO uint32_t SBUF10; /*!< SMIF Indirect Access Secondary Buffer Register 10*/ + __IO uint32_t SBUF11; /*!< SMIF Indirect Access Secondary Buffer Register 11*/ + __IO uint32_t SBUF12; /*!< SMIF Indirect Access Secondary Buffer Register 12*/ + __IO uint32_t SBUF13; /*!< SMIF Indirect Access Secondary Buffer Register 13*/ + __IO uint32_t SBUF14; /*!< SMIF Indirect Access Secondary Buffer Register 14*/ + __IO uint32_t SBUF15; /*!< SMIF Indirect Access Secondary Buffer Register 15*/ + __IO uint32_t SBUF16; /*!< SMIF Indirect Access Secondary Buffer Register 16*/ + __IO uint32_t SBUF17; /*!< SMIF Indirect Access Secondary Buffer Register 17*/ + __IO uint32_t SBUF18; /*!< SMIF Indirect Access Secondary Buffer Register 18*/ + __IO uint32_t SBUF19; /*!< SMIF Indirect Access Secondary Buffer Register 19*/ + __IO uint32_t SBUF20; /*!< SMIF Indirect Access Secondary Buffer Register 20*/ + __IO uint32_t SBUF21; /*!< SMIF Indirect Access Secondary Buffer Register 21*/ + __IO uint32_t SBUF22; /*!< SMIF Indirect Access Secondary Buffer Register 22*/ + __IO uint32_t SBUF23; /*!< SMIF Indirect Access Secondary Buffer Register 23*/ + __IO uint32_t SBUF24; /*!< SMIF Indirect Access Secondary Buffer Register 24*/ + __IO uint32_t SBUF25; /*!< SMIF Indirect Access Secondary Buffer Register 25*/ + __IO uint32_t SBUF26; /*!< SMIF Indirect Access Secondary Buffer Register 26*/ + __IO uint32_t SBUF27; /*!< SMIF Indirect Access Secondary Buffer Register 27*/ + __IO uint32_t SBUF28; /*!< SMIF Indirect Access Secondary Buffer Register 28*/ + __IO uint32_t SBUF29; /*!< SMIF Indirect Access Secondary Buffer Register 29*/ + __IO uint32_t SBUF30; /*!< SMIF Indirect Access Secondary Buffer Register 30*/ + __IO uint32_t SBUF31; /*!< SMIF Indirect Access Secondary Buffer Register 31*/ + __IO uint32_t SBUF32; /*!< SMIF Indirect Access Secondary Buffer Register 32*/ + __IO uint32_t SBUF33; /*!< SMIF Indirect Access Secondary Buffer Register 33*/ + __IO uint32_t SBUF34; /*!< SMIF Indirect Access Secondary Buffer Register 34*/ + __IO uint32_t SBUF35; /*!< SMIF Indirect Access Secondary Buffer Register 35*/ + __IO uint32_t SBUF36; /*!< SMIF Indirect Access Secondary Buffer Register 36*/ + __IO uint32_t SBUF37; /*!< SMIF Indirect Access Secondary Buffer Register 37*/ + __IO uint32_t SBUF38; /*!< SMIF Indirect Access Secondary Buffer Register 38*/ + __IO uint32_t SBUF39; /*!< SMIF Indirect Access Secondary Buffer Register 39*/ + __IO uint32_t SBUF40; /*!< SMIF Indirect Access Secondary Buffer Register 40*/ + __IO uint32_t SBUF41; /*!< SMIF Indirect Access Secondary Buffer Register 41*/ + __IO uint32_t SBUF42; /*!< SMIF Indirect Access Secondary Buffer Register 42*/ + __IO uint32_t SBUF43; /*!< SMIF Indirect Access Secondary Buffer Register 43*/ + __IO uint32_t SBUF44; /*!< SMIF Indirect Access Secondary Buffer Register 44*/ + __IO uint32_t SBUF45; /*!< SMIF Indirect Access Secondary Buffer Register 45*/ + __IO uint32_t SBUF46; /*!< SMIF Indirect Access Secondary Buffer Register 46*/ + __IO uint32_t SBUF47; /*!< SMIF Indirect Access Secondary Buffer Register 47*/ + __IO uint32_t SBUF48; /*!< SMIF Indirect Access Secondary Buffer Register 48*/ + __IO uint32_t SBUF49; /*!< SMIF Indirect Access Secondary Buffer Register 49*/ + __IO uint32_t SBUF50; /*!< SMIF Indirect Access Secondary Buffer Register 50*/ + __IO uint32_t SBUF51; /*!< SMIF Indirect Access Secondary Buffer Register 51*/ + __IO uint32_t SBUF52; /*!< SMIF Indirect Access Secondary Buffer Register 52*/ + __IO uint32_t SBUF53; /*!< SMIF Indirect Access Secondary Buffer Register 53*/ + __IO uint32_t SBUF54; /*!< SMIF Indirect Access Secondary Buffer Register 54*/ + __IO uint32_t SBUF55; /*!< SMIF Indirect Access Secondary Buffer Register 55*/ + __IO uint32_t SBUF56; /*!< SMIF Indirect Access Secondary Buffer Register 56*/ + __IO uint32_t SBUF57; /*!< SMIF Indirect Access Secondary Buffer Register 57*/ + __IO uint32_t SBUF58; /*!< SMIF Indirect Access Secondary Buffer Register 58*/ + __IO uint32_t SBUF59; /*!< SMIF Indirect Access Secondary Buffer Register 59*/ + __IO uint32_t SBUF60; /*!< SMIF Indirect Access Secondary Buffer Register 60*/ + __IO uint32_t SBUF61; /*!< SMIF Indirect Access Secondary Buffer Register 61*/ + __IO uint32_t SBUF62; /*!< SMIF Indirect Access Secondary Buffer Register 62*/ + __IO uint32_t SBUF63; /*!< SMIF Indirect Access Secondary Buffer Register 63*/ +} TSB_SMI_TypeDef; + +/** + * @brief Interrupt Control Registers A + */ +typedef struct { + __IO uint8_t NIC00; /*!< Non-maskable Interrupt A Control Register 00 */ + uint8_t RESERVED0[31]; + __IO uint8_t IMC00; /*!< Interrupt A Mode Control Register 00 */ + __IO uint8_t IMC01; /*!< Interrupt A Mode Control Register 01 */ + __IO uint8_t IMC02; /*!< Interrupt A Mode Control Register 02 */ + __IO uint8_t IMC03; /*!< Interrupt A Mode Control Register 03 */ + __IO uint8_t IMC04; /*!< Interrupt A Mode Control Register 04 */ + __IO uint8_t IMC05; /*!< Interrupt A Mode Control Register 05 */ + __IO uint8_t IMC06; /*!< Interrupt A Mode Control Register 06 */ + __IO uint8_t IMC07; /*!< Interrupt A Mode Control Register 07 */ + __IO uint8_t IMC08; /*!< Interrupt A Mode Control Register 08 */ + __IO uint8_t IMC09; /*!< Interrupt A Mode Control Register 09 */ + __IO uint8_t IMC10; /*!< Interrupt A Mode Control Register 10 */ + __IO uint8_t IMC11; /*!< Interrupt A Mode Control Register 11 */ + __IO uint8_t IMC12; /*!< Interrupt A Mode Control Register 12 */ + __IO uint8_t IMC13; /*!< Interrupt A Mode Control Register 13 */ + __IO uint8_t IMC14; /*!< Interrupt A Mode Control Register 14 */ + __IO uint8_t IMC15; /*!< Interrupt A Mode Control Register 15 */ + __IO uint8_t IMC16; /*!< Interrupt A Mode Control Register 16 */ + __IO uint8_t IMC17; /*!< Interrupt A Mode Control Register 17 */ + __IO uint8_t IMC18; /*!< Interrupt A Mode Control Register 18 */ + __IO uint8_t IMC19; /*!< Interrupt A Mode Control Register 19 */ + __IO uint8_t IMC20; /*!< Interrupt A Mode Control Register 20 */ + __IO uint8_t IMC21; /*!< Interrupt A Mode Control Register 21 */ + __IO uint8_t IMC22; /*!< Interrupt A Mode Control Register 22 */ + __IO uint8_t IMC23; /*!< Interrupt A Mode Control Register 23 */ + __IO uint8_t IMC24; /*!< Interrupt A Mode Control Register 24 */ + __IO uint8_t IMC25; /*!< Interrupt A Mode Control Register 25 */ + __IO uint8_t IMC26; /*!< Interrupt A Mode Control Register 26 */ + __IO uint8_t IMC27; /*!< Interrupt A Mode Control Register 27 */ + __IO uint8_t IMC28; /*!< Interrupt A Mode Control Register 28 */ + __IO uint8_t IMC29; /*!< Interrupt A Mode Control Register 29 */ + __IO uint8_t IMC30; /*!< Interrupt A Mode Control Register 30 */ + __IO uint8_t IMC31; /*!< Interrupt A Mode Control Register 31 */ + uint8_t RESERVED1[17]; + __IO uint8_t IMC49; /*!< Interrupt A Mode Control Register 49 */ + __IO uint8_t IMC50; /*!< Interrupt A Mode Control Register 50 */ + __IO uint8_t IMC51; /*!< Interrupt A Mode Control Register 51 */ + __IO uint8_t IMC52; /*!< Interrupt A Mode Control Register 52 */ + __IO uint8_t IMC53; /*!< Interrupt A Mode Control Register 53 */ + __IO uint8_t IMC54; /*!< Interrupt A Mode Control Register 54 */ + __IO uint8_t IMC55; /*!< Interrupt A Mode Control Register 55 */ + __IO uint8_t IMC56; /*!< Interrupt A Mode Control Register 56 */ + __IO uint8_t IMC57; /*!< Interrupt A Mode Control Register 57 */ +} TSB_IA_TypeDef; + +/** + * @brief Low speed oscillation/power control/reset + */ +typedef struct { + __IO uint8_t LOSCCR; /*!< Low speed oscillation and Internal High speed oscillation 2 clock control register*/ + __IO uint8_t SHTDNOP; /*!< Power supply cut off control register */ + __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ + __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ + uint8_t RESERVED0[11]; + __IO uint8_t PROTECT; /*!< RLM write protection register */ +} TSB_RLM_TypeDef; + +/** + * @brief LVD0 + */ +typedef struct { + __IO uint8_t CR1; /*!< LVD Control Register1 */ + __IO uint8_t CR2; /*!< LVD Control Register2 */ + __IO uint8_t LVL1; /*!< LVD Detection Voltage Select Register 1 */ + uint8_t RESERVED0; + __I uint8_t SR; /*!< LVD Status Register */ +} TSB_LVD_TypeDef; + +/** + * @brief TRGSEL + */ +typedef struct { + __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ + __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ + __IO uint32_t CR2; /*!< TSEL Control register 2 */ + __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ + __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ + __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ + __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ + __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ + __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ + __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ + __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ + __IO uint32_t CR11; /*!< TRGSEL Control register 11 */ + __IO uint32_t CR12; /*!< TRGSEL Control register 12 */ + __IO uint32_t CR13; /*!< TRGSEL Control register 13 */ + __IO uint32_t CR14; /*!< TRGSEL Control register 14 */ +} TSB_TSEL_TypeDef; + +/** + * @brief Long Term Timer(LTTMR) + */ +typedef struct { + __IO uint8_t CR0; /*!< LTTMR Control Register */ + __IO uint8_t VALL; /*!< LTTMR Data Register (Lower) */ + __IO uint8_t VALH; /*!< LTTMR Data Register (Upper) */ +} TSB_LTT_TypeDef; + +/** + * @brief Serial Interface (TSPI) + */ +typedef struct { + __IO uint32_t CR0; /*!< TSPI Control Register 0 */ + __IO uint32_t CR1; /*!< TSPI Control Register 1 */ + __IO uint32_t CR2; /*!< TSPI Control Register 2 */ + __IO uint32_t CR3; /*!< TSPI Control Register 3 */ + __IO uint32_t BR; /*!< TSPI Baud Rate Register */ + __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ + __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ + __IO uint32_t SECTCR0; /*!< TSPI Sector mode Control Register 0 */ + __IO uint32_t SECTCR1; /*!< TSPI Sector mode Control Register 1 */ + uint32_t RESERVED0[55]; + __IO uint32_t DR; /*!< TSPI Data Register */ + uint32_t RESERVED1[63]; + __IO uint32_t SR; /*!< TSPI Status Register */ + __IO uint32_t ERR; /*!< TSPI Error Flag Register */ +} TSB_TSPI_TypeDef; + +/** + * @brief External Bus Interface(EXB) + */ +typedef struct { + __IO uint32_t MOD; /*!< EBIF Mode Control Register */ + uint32_t RESERVED0[3]; + __IO uint32_t AS0; /*!< EBIF Area and Start Address Configuration Register 0*/ + __IO uint32_t AS1; /*!< EBIF Area and Start Address Configuration Register 1*/ + __IO uint32_t AS2; /*!< EBIF Area and Start Address Configuration Register 2*/ + __IO uint32_t AS3; /*!< EBIF Area and Start Address Configuration Register 3*/ + uint32_t RESERVED1[8]; + __IO uint32_t CS0; /*!< EBIF Chip Select Control Register 0 */ + __IO uint32_t CS1; /*!< EBIF Chip Select Control Register 1 */ + __IO uint32_t CS2; /*!< EBIF Chip Select Control Register 2 */ + __IO uint32_t CS3; /*!< EBIF Chip Select Control Register 3 */ + uint32_t RESERVED2[4]; + __IO uint32_t CLKCTL; /*!< EBIF Clock Output Control Register */ +} TSB_EXB_TypeDef; + +/** + * @brief Clock Generator (CG) + */ +typedef struct { + __IO uint32_t PROTECT; /*!< CG write protection register */ + __IO uint32_t OSCCR; /*!< CG Oscillation control register */ + __IO uint32_t SYSCR; /*!< CG System clock control register */ + __IO uint32_t STBYCR; /*!< CG Standby control register */ + uint32_t RESERVED0[4]; + __IO uint32_t PLL0SEL; /*!< CG PLL selection register for fsys */ + uint32_t RESERVED1[3]; + __IO uint32_t WUPHCR; /*!< CG High speed oscillation warming up register*/ + __IO uint32_t WUPLCR; /*!< CG Low speed oscillation warming up register */ + uint32_t RESERVED2[3]; + __IO uint32_t FSYSMENC; /*!< CG Middle speed clock supply and stop register C for fsys*/ + __IO uint32_t FSYSMENA; /*!< CG Middle speed clock supply and stop register A for fsys*/ + __IO uint32_t FSYSMENB; /*!< CG Middle speed clock supply and stop register B for fsys*/ + __IO uint32_t FSYSENA; /*!< CG High speed clock supply and stop register A for fsys*/ + uint32_t RESERVED3; + __IO uint32_t FCEN; /*!< CG Clock supply and stop register for fc */ + __IO uint32_t SPCLKEN; /*!< CG Clock supply for ADC and Trace Register */ + uint32_t RESERVED4[2]; + __IO uint32_t EXTEND2; /*!< CG Function extension register 2 */ +} TSB_CG_TypeDef; + +/** + * @brief Interrupt Control Register B + */ +typedef struct { + uint8_t RESERVED0[16]; + __IO uint8_t NIC00; /*!< Non-maskable Interrupt B Control Register 00 */ + uint8_t RESERVED1[79]; + __IO uint8_t IMC000; /*!< Interrupt B Mode Control Register 000 */ + __IO uint8_t IMC001; /*!< Interrupt B Mode Control Register 001 */ + __IO uint8_t IMC002; /*!< Interrupt B Mode Control Register 002 */ + __IO uint8_t IMC003; /*!< Interrupt B Mode Control Register 003 */ + __IO uint8_t IMC004; /*!< Interrupt B Mode Control Register 004 */ + __IO uint8_t IMC005; /*!< Interrupt B Mode Control Register 005 */ + __IO uint8_t IMC006; /*!< Interrupt B Mode Control Register 006 */ + __IO uint8_t IMC007; /*!< Interrupt B Mode Control Register 007 */ + __IO uint8_t IMC008; /*!< Interrupt B Mode Control Register 008 */ + __IO uint8_t IMC009; /*!< Interrupt B Mode Control Register 009 */ + __IO uint8_t IMC010; /*!< Interrupt B Mode Control Register 010 */ + __IO uint8_t IMC011; /*!< Interrupt B Mode Control Register 011 */ + __IO uint8_t IMC012; /*!< Interrupt B Mode Control Register 012 */ + __IO uint8_t IMC013; /*!< Interrupt B Mode Control Register 013 */ + __IO uint8_t IMC014; /*!< Interrupt B Mode Control Register 014 */ + __IO uint8_t IMC015; /*!< Interrupt B Mode Control Register 015 */ + __IO uint8_t IMC016; /*!< Interrupt B Mode Control Register 016 */ + __IO uint8_t IMC017; /*!< Interrupt B Mode Control Register 017 */ + __IO uint8_t IMC018; /*!< Interrupt B Mode Control Register 018 */ + __IO uint8_t IMC019; /*!< Interrupt B Mode Control Register 019 */ + __IO uint8_t IMC020; /*!< Interrupt B Mode Control Register 020 */ + __IO uint8_t IMC021; /*!< Interrupt B Mode Control Register 021 */ + __IO uint8_t IMC022; /*!< Interrupt B Mode Control Register 022 */ + __IO uint8_t IMC023; /*!< Interrupt B Mode Control Register 023 */ + __IO uint8_t IMC024; /*!< Interrupt B Mode Control Register 024 */ + __IO uint8_t IMC025; /*!< Interrupt B Mode Control Register 025 */ + __IO uint8_t IMC026; /*!< Interrupt B Mode Control Register 026 */ + __IO uint8_t IMC027; /*!< Interrupt B Mode Control Register 027 */ + __IO uint8_t IMC028; /*!< Interrupt B Mode Control Register 028 */ + __IO uint8_t IMC029; /*!< Interrupt B Mode Control Register 029 */ + __IO uint8_t IMC030; /*!< Interrupt B Mode Control Register 030 */ + __IO uint8_t IMC031; /*!< Interrupt B Mode Control Register 031 */ + __IO uint8_t IMC032; /*!< Interrupt B Mode Control Register 032 */ + __IO uint8_t IMC033; /*!< Interrupt B Mode Control Register 033 */ + __IO uint8_t IMC034; /*!< Interrupt B Mode Control Register 034 */ + __IO uint8_t IMC035; /*!< Interrupt B Mode Control Register 035 */ + __IO uint8_t IMC036; /*!< Interrupt B Mode Control Register 036 */ + __IO uint8_t IMC037; /*!< Interrupt B Mode Control Register 037 */ + __IO uint8_t IMC038; /*!< Interrupt B Mode Control Register 038 */ + __IO uint8_t IMC039; /*!< Interrupt B Mode Control Register 039 */ + __IO uint8_t IMC040; /*!< Interrupt B Mode Control Register 040 */ + __IO uint8_t IMC041; /*!< Interrupt B Mode Control Register 041 */ + __IO uint8_t IMC042; /*!< Interrupt B Mode Control Register 042 */ + __IO uint8_t IMC043; /*!< Interrupt B Mode Control Register 043 */ + __IO uint8_t IMC044; /*!< Interrupt B Mode Control Register 044 */ + __IO uint8_t IMC045; /*!< Interrupt B Mode Control Register 045 */ + __IO uint8_t IMC046; /*!< Interrupt B Mode Control Register 046 */ + __IO uint8_t IMC047; /*!< Interrupt B Mode Control Register 047 */ + __IO uint8_t IMC048; /*!< Interrupt B Mode Control Register 048 */ + __IO uint8_t IMC049; /*!< Interrupt B Mode Control Register 049 */ + __IO uint8_t IMC050; /*!< Interrupt B Mode Control Register 050 */ + __IO uint8_t IMC051; /*!< Interrupt B Mode Control Register 051 */ + __IO uint8_t IMC052; /*!< Interrupt B Mode Control Register 052 */ + __IO uint8_t IMC053; /*!< Interrupt B Mode Control Register 053 */ + __IO uint8_t IMC054; /*!< Interrupt B Mode Control Register 054 */ + __IO uint8_t IMC055; /*!< Interrupt B Mode Control Register 055 */ + __IO uint8_t IMC056; /*!< Interrupt B Mode Control Register 056 */ + __IO uint8_t IMC057; /*!< Interrupt B Mode Control Register 057 */ + __IO uint8_t IMC058; /*!< Interrupt B Mode Control Register 058 */ + __IO uint8_t IMC059; /*!< Interrupt B Mode Control Register 059 */ + __IO uint8_t IMC060; /*!< Interrupt B Mode Control Register 060 */ + __IO uint8_t IMC061; /*!< Interrupt B Mode Control Register 061 */ + __IO uint8_t IMC062; /*!< Interrupt B Mode Control Register 062 */ + __IO uint8_t IMC063; /*!< Interrupt B Mode Control Register 063 */ + __IO uint8_t IMC064; /*!< Interrupt B Mode Control Register 064 */ + __IO uint8_t IMC065; /*!< Interrupt B Mode Control Register 065 */ + __IO uint8_t IMC066; /*!< Interrupt B Mode Control Register 066 */ + __IO uint8_t IMC067; /*!< Interrupt B Mode Control Register 067 */ + __IO uint8_t IMC068; /*!< Interrupt B Mode Control Register 068 */ + __IO uint8_t IMC069; /*!< Interrupt B Mode Control Register 069 */ + __IO uint8_t IMC070; /*!< Interrupt B Mode Control Register 070 */ + __IO uint8_t IMC071; /*!< Interrupt B Mode Control Register 071 */ + __IO uint8_t IMC072; /*!< Interrupt B Mode Control Register 072 */ + __IO uint8_t IMC073; /*!< Interrupt B Mode Control Register 073 */ + __IO uint8_t IMC074; /*!< Interrupt B Mode Control Register 074 */ + __IO uint8_t IMC075; /*!< Interrupt B Mode Control Register 075 */ + __IO uint8_t IMC076; /*!< Interrupt B Mode Control Register 076 */ + __IO uint8_t IMC077; /*!< Interrupt B Mode Control Register 077 */ + __IO uint8_t IMC078; /*!< Interrupt B Mode Control Register 078 */ + __IO uint8_t IMC079; /*!< Interrupt B Mode Control Register 079 */ + __IO uint8_t IMC080; /*!< Interrupt B Mode Control Register 080 */ + __IO uint8_t IMC081; /*!< Interrupt B Mode Control Register 081 */ + __IO uint8_t IMC082; /*!< Interrupt B Mode Control Register 082 */ + __IO uint8_t IMC083; /*!< Interrupt B Mode Control Register 083 */ + __IO uint8_t IMC084; /*!< Interrupt B Mode Control Register 084 */ + __IO uint8_t IMC085; /*!< Interrupt B Mode Control Register 085 */ + __IO uint8_t IMC086; /*!< Interrupt B Mode Control Register 086 */ + __IO uint8_t IMC087; /*!< Interrupt B Mode Control Register 087 */ + __IO uint8_t IMC088; /*!< Interrupt B Mode Control Register 088 */ + __IO uint8_t IMC089; /*!< Interrupt B Mode Control Register 089 */ + __IO uint8_t IMC090; /*!< Interrupt B Mode Control Register 090 */ + __IO uint8_t IMC091; /*!< Interrupt B Mode Control Register 091 */ + __IO uint8_t IMC092; /*!< Interrupt B Mode Control Register 092 */ + __IO uint8_t IMC093; /*!< Interrupt B Mode Control Register 093 */ + __IO uint8_t IMC094; /*!< Interrupt B Mode Control Register 094 */ + __IO uint8_t IMC095; /*!< Interrupt B Mode Control Register 095 */ + __IO uint8_t IMC096; /*!< Interrupt B Mode Control Register 096 */ + __IO uint8_t IMC097; /*!< Interrupt B Mode Control Register 097 */ + __IO uint8_t IMC098; /*!< Interrupt B Mode Control Register 098 */ + __IO uint8_t IMC099; /*!< Interrupt B Mode Control Register 099 */ + __IO uint8_t IMC100; /*!< Interrupt B Mode Control Register 100 */ + __IO uint8_t IMC101; /*!< Interrupt B Mode Control Register 101 */ + __IO uint8_t IMC102; /*!< Interrupt B Mode Control Register 102 */ + __IO uint8_t IMC103; /*!< Interrupt B Mode Control Register 103 */ + __IO uint8_t IMC104; /*!< Interrupt B Mode Control Register 104 */ + __IO uint8_t IMC105; /*!< Interrupt B Mode Control Register 105 */ + __IO uint8_t IMC106; /*!< Interrupt B Mode Control Register 106 */ + __IO uint8_t IMC107; /*!< Interrupt B Mode Control Register 107 */ + __IO uint8_t IMC108; /*!< Interrupt B Mode Control Register 108 */ + __IO uint8_t IMC109; /*!< Interrupt B Mode Control Register 109 */ + __IO uint8_t IMC110; /*!< Interrupt B Mode Control Register 110 */ + __IO uint8_t IMC111; /*!< Interrupt B Mode Control Register 111 */ + __IO uint8_t IMC112; /*!< Interrupt B Mode Control Register 112 */ + __IO uint8_t IMC113; /*!< Interrupt B Mode Control Register 113 */ + __IO uint8_t IMC114; /*!< Interrupt B Mode Control Register 114 */ + __IO uint8_t IMC115; /*!< Interrupt B Mode Control Register 115 */ + __IO uint8_t IMC116; /*!< Interrupt B Mode Control Register 116 */ + __IO uint8_t IMC117; /*!< Interrupt B Mode Control Register 117 */ + __IO uint8_t IMC118; /*!< Interrupt B Mode Control Register 118 */ + __IO uint8_t IMC119; /*!< Interrupt B Mode Control Register 119 */ + __IO uint8_t IMC120; /*!< Interrupt B Mode Control Register 120 */ + __IO uint8_t IMC121; /*!< Interrupt B Mode Control Register 121 */ + __IO uint8_t IMC122; /*!< Interrupt B Mode Control Register 122 */ + __IO uint8_t IMC123; /*!< Interrupt B Mode Control Register 123 */ + __IO uint8_t IMC124; /*!< Interrupt B Mode Control Register 124 */ + __IO uint8_t IMC125; /*!< Interrupt B Mode Control Register 125 */ + __IO uint8_t IMC126; /*!< Interrupt B Mode Control Register 126 */ + __IO uint8_t IMC127; /*!< Interrupt B Mode Control Register 127 */ + __IO uint8_t IMC128; /*!< Interrupt B Mode Control Register 128 */ + __IO uint8_t IMC129; /*!< Interrupt B Mode Control Register 129 */ + __IO uint8_t IMC130; /*!< Interrupt B Mode Control Register 130 */ + __IO uint8_t IMC131; /*!< Interrupt B Mode Control Register 131 */ + __IO uint8_t IMC132; /*!< Interrupt B Mode Control Register 132 */ + __IO uint8_t IMC133; /*!< Interrupt B Mode Control Register 133 */ + __IO uint8_t IMC134; /*!< Interrupt B Mode Control Register 134 */ + __IO uint8_t IMC135; /*!< Interrupt B Mode Control Register 135 */ + __IO uint8_t IMC136; /*!< Interrupt B Mode Control Register 136 */ + __IO uint8_t IMC137; /*!< Interrupt B Mode Control Register 137 */ + __IO uint8_t IMC138; /*!< Interrupt B Mode Control Register 138 */ + __IO uint8_t IMC139; /*!< Interrupt B Mode Control Register 139 */ + __IO uint8_t IMC140; /*!< Interrupt B Mode Control Register 140 */ + __IO uint8_t IMC141; /*!< Interrupt B Mode Control Register 141 */ + uint8_t RESERVED2[3]; + __IO uint8_t IMC145; /*!< Interrupt B Mode Control Register 145 */ + __IO uint8_t IMC146; /*!< Interrupt B Mode Control Register 146 */ + __IO uint8_t IMC147; /*!< Interrupt B Mode Control Register 147 */ + __IO uint8_t IMC148; /*!< Interrupt B Mode Control Register 148 */ + __IO uint8_t IMC149; /*!< Interrupt B Mode Control Register 149 */ + __IO uint8_t IMC150; /*!< Interrupt B Mode Control Register 150 */ + __IO uint8_t IMC151; /*!< Interrupt B Mode Control Register 151 */ + __IO uint8_t IMC152; /*!< Interrupt B Mode Control Register 152 */ + __IO uint8_t IMC153; /*!< Interrupt B Mode Control Register 153 */ + __IO uint8_t IMC154; /*!< Interrupt B Mode Control Register 154 */ + __IO uint8_t IMC155; /*!< Interrupt B Mode Control Register 155 */ + __IO uint8_t IMC156; /*!< Interrupt B Mode Control Register 156 */ + __IO uint8_t IMC157; /*!< Interrupt B Mode Control Register 157 */ + __IO uint8_t IMC158; /*!< Interrupt B Mode Control Register 158 */ + __IO uint8_t IMC159; /*!< Interrupt B Mode Control Register 159 */ +} TSB_IB_TypeDef; + +/** + * @brief Interrupt Monitor Register + */ +typedef struct { + __I uint32_t FLGNMI; /*!< Non-maskable Interrupt Monitor Flag Register Register*/ + __I uint32_t FLG1; /*!< Interrupt Monitor Flag Register 1 (032 - 063)*/ + __I uint32_t FLG2; /*!< Interrupt Monitor Flag Register 2 (064 - 095)*/ + __I uint32_t FLG3; /*!< Interrupt Monitor Flag Register 3 (096 - 127)*/ + __I uint32_t FLG4; /*!< Interrupt Monitor Flag Register 4 (128 - 159)*/ + __I uint32_t FLG5; /*!< Interrupt Monitor Flag Register 5 (160 - 191)*/ + __I uint32_t FLG6; /*!< Interrupt Monitor Flag Register 6 (192 - 223)*/ + __I uint32_t FLG7; /*!< Interrupt Monitor Flag Register 7 (224 - 255)*/ +} TSB_IMN_TypeDef; + +/** + * @brief DNF + */ +typedef struct { + __IO uint32_t CKCR; /*!< DNF Unit A Noise Filter Control Register */ + __IO uint32_t ENCR; /*!< DNF Unit A Noise Filter Enable Register */ +} TSB_DNF_TypeDef; + +/** + * @brief Watchdog Timer (SIWDT) + */ +typedef struct { + __IO uint32_t PRO; /*!< SIWDT Protect Register */ + __IO uint32_t EN; /*!< SIWDT Enable Register */ + __O uint32_t CR; /*!< SIWDT Control Register */ + __IO uint32_t MOD; /*!< SIWDT Mode Register */ + __I uint32_t MONI; /*!< SIWDT Count Monitor Register */ +} TSB_SIWD_TypeDef; + +/** + * @brief NBDIF + */ +typedef struct { + __IO uint32_t CR0; /*!< NBDIF control register 0 */ + __IO uint32_t CR1; /*!< NBDIF control register 1 */ +} TSB_NBD_TypeDef; + +/** + * @brief Malti Porpose Direct Memory Accsess(MDMA) + */ +typedef struct { + uint32_t RESERVED0; + __IO uint32_t CEN; /*!< MDMA Transfer Channel Enable Register */ + __IO uint32_t REQ; /*!< MDMA Transfer Request Register */ + __IO uint32_t SUS; /*!< MDMA Transfer Suspension Register */ + __IO uint32_t ACT; /*!< MDMA Transfer Active Register */ + __IO uint32_t END; /*!< MDMA Transfer End Register */ + __IO uint32_t PRI; /*!< MDMA Transfer Priority Setting Register */ + __IO uint32_t ENE; /*!< MDMA Transfer Completion Interrupt Enable Register*/ + __IO uint32_t DTAB; /*!< MDMA Transfer Descriptor Table Start Address Register*/ + uint32_t RESERVED1; + __I uint32_t CHN; /*!< MDMA Transfer Execution Channel Number Register*/ + __I uint32_t XFTYP; /*!< MDMA Transfer Type Register */ + __I uint32_t XFSAD; /*!< MDMA Transfer Source Address Register */ + __I uint32_t XFDAD; /*!< MDMA Transfer Destination Address Register */ + __I uint32_t XFSIZ; /*!< MDMA Transfer Size Register */ + __I uint32_t DSADS; /*!< MDMA Transfer Descriptor Storage Address Register*/ + __I uint32_t DSNUM; /*!< MDMA Transfer Descriptor Count Register */ + uint32_t RESERVED2; + __IO uint32_t DEND; /*!< MDMA Descriptor End Register */ + __IO uint32_t DENE; /*!< MDMA Descriptor Completion Interrupt Enable Register*/ + __I uint32_t C00XFTYP; /*!< MDMA ch 00 Transfer Type Saving Register */ + __I uint32_t C00XFSAD; /*!< MDMA ch 00 Transfer Source Address Saving Register*/ + __I uint32_t C00XFDAD; /*!< MDMA ch 00 Transfer Destination Address Saving Register*/ + __I uint32_t C00XFSIZ; /*!< MDMA ch 00 Transfer Size Saving Register */ + __I uint32_t C00DSADS; /*!< MDMA ch 00 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C00DSNUM; /*!< MDMA ch 00 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED3[2]; + __I uint32_t C01XFTYP; /*!< MDMA ch 01 Transfer Type Saving Register */ + __I uint32_t C01XFSAD; /*!< MDMA ch 01 Transfer Source Address Saving Register*/ + __I uint32_t C01XFDAD; /*!< MDMA ch 01 Transfer Destination Address Saving Register*/ + __I uint32_t C01XFSIZ; /*!< MDMA ch 01 Transfer Size Saving Register */ + __I uint32_t C01DSADS; /*!< MDMA ch 01 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C01DSNUM; /*!< MDMA ch 01 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED4[2]; + __I uint32_t C02XFTYP; /*!< MDMA ch 02 Transfer Type Saving Register */ + __I uint32_t C02XFSAD; /*!< MDMA ch 02 Transfer Source Address Saving Register*/ + __I uint32_t C02XFDAD; /*!< MDMA ch 02 Transfer Destination Address Saving Register*/ + __I uint32_t C02XFSIZ; /*!< MDMA ch 02 Transfer Size Saving Register */ + __I uint32_t C02DSADS; /*!< MDMA ch 02 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C02DSNUM; /*!< MDMA ch 02 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED5[2]; + __I uint32_t C03XFTYP; /*!< MDMA ch 03 Transfer Type Saving Register */ + __I uint32_t C03XFSAD; /*!< MDMA ch 03 Transfer Source Address Saving Register*/ + __I uint32_t C03XFDAD; /*!< MDMA ch 03 Transfer Destination Address Saving Register*/ + __I uint32_t C03XFSIZ; /*!< MDMA ch 03 Transfer Size Saving Register */ + __I uint32_t C03DSADS; /*!< MDMA ch 03 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C03DSNUM; /*!< MDMA ch 03 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED6[2]; + __I uint32_t C04XFTYP; /*!< MDMA ch 04 Transfer Type Saving Register */ + __I uint32_t C04XFSAD; /*!< MDMA ch 04 Transfer Source Address Saving Register*/ + __I uint32_t C04XFDAD; /*!< MDMA ch 04 Transfer Destination Address Saving Register*/ + __I uint32_t C04XFSIZ; /*!< MDMA ch 04 Transfer Size Saving Register */ + __I uint32_t C04DSADS; /*!< MDMA ch 04 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C04DSNUM; /*!< MDMA ch 04 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED7[2]; + __I uint32_t C05XFTYP; /*!< MDMA ch 05 Transfer Type Saving Register */ + __I uint32_t C05XFSAD; /*!< MDMA ch 05 Transfer Source Address Saving Register*/ + __I uint32_t C05XFDAD; /*!< MDMA ch 05 Transfer Destination Address Saving Register*/ + __I uint32_t C05XFSIZ; /*!< MDMA ch 05 Transfer Size Saving Register */ + __I uint32_t C05DSADS; /*!< MDMA ch 05 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C05DSNUM; /*!< MDMA ch 05 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED8[2]; + __I uint32_t C06XFTYP; /*!< MDMA ch 06 Transfer Type Saving Register */ + __I uint32_t C06XFSAD; /*!< MDMA ch 06 Transfer Source Address Saving Register*/ + __I uint32_t C06XFDAD; /*!< MDMA ch 06 Transfer Destination Address Saving Register*/ + __I uint32_t C06XFSIZ; /*!< MDMA ch 06 Transfer Size Saving Register */ + __I uint32_t C06DSADS; /*!< MDMA ch 06 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C06DSNUM; /*!< MDMA ch 06 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED9[2]; + __I uint32_t C07XFTYP; /*!< MDMA ch 07 Transfer Type Saving Register */ + __I uint32_t C07XFSAD; /*!< MDMA ch 07 Transfer Source Address Saving Register*/ + __I uint32_t C07XFDAD; /*!< MDMA ch 07 Transfer Destination Address Saving Register*/ + __I uint32_t C07XFSIZ; /*!< MDMA ch 07 Transfer Size Saving Register */ + __I uint32_t C07DSADS; /*!< MDMA ch 07 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C07DSNUM; /*!< MDMA ch 07 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED10[2]; + __I uint32_t C08XFTYP; /*!< MDMA ch 08 Transfer Type Saving Register */ + __I uint32_t C08XFSAD; /*!< MDMA ch 08 Transfer Source Address Saving Register*/ + __I uint32_t C08XFDAD; /*!< MDMA ch 08 Transfer Destination Address Saving Register*/ + __I uint32_t C08XFSIZ; /*!< MDMA ch 08 Transfer Size Saving Register */ + __I uint32_t C08DSADS; /*!< MDMA ch 08 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C08DSNUM; /*!< MDMA ch 08 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED11[2]; + __I uint32_t C09XFTYP; /*!< MDMA ch n Transfer Type Saving Register */ + __I uint32_t C09XFSAD; /*!< MDMA ch n Transfer Source Address Saving Register*/ + __I uint32_t C09XFDAD; /*!< MDMA ch n Transfer Destination Address Saving Register*/ + __I uint32_t C09XFSIZ; /*!< MDMA ch n Transfer Size Saving Register */ + __I uint32_t C09DSADS; /*!< MDMA ch n Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C09DSNUM; /*!< MDMA ch n Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED12[2]; + __I uint32_t C10XFTYP; /*!< MDMA ch 10 Transfer Type Saving Register */ + __I uint32_t C10XFSAD; /*!< MDMA ch 10 Transfer Source Address Saving Register*/ + __I uint32_t C10XFDAD; /*!< MDMA ch 10 Transfer Destination Address Saving Register*/ + __I uint32_t C10XFSIZ; /*!< MDMA ch 10 Transfer Size Saving Register */ + __I uint32_t C10DSADS; /*!< MDMA ch 10 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C10DSNUM; /*!< MDMA ch 10 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED13[2]; + __I uint32_t C11XFTYP; /*!< MDMA ch 11 Transfer Type Saving Register */ + __I uint32_t C11XFSAD; /*!< MDMA ch 11 Transfer Source Address Saving Register*/ + __I uint32_t C11XFDAD; /*!< MDMA ch 11 Transfer Destination Address Saving Register*/ + __I uint32_t C11XFSIZ; /*!< MDMA ch 11 Transfer Size Saving Register */ + __I uint32_t C11DSADS; /*!< MDMA ch 11 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C11DSNUM; /*!< MDMA ch 11 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED14[2]; + __I uint32_t C12XFTYP; /*!< MDMA ch 12 Transfer Type Saving Register */ + __I uint32_t C12XFSAD; /*!< MDMA ch 12 Transfer Source Address Saving Register*/ + __I uint32_t C12XFDAD; /*!< MDMA ch 12 Transfer Destination Address Saving Register*/ + __I uint32_t C12XFSIZ; /*!< MDMA ch 12 Transfer Size Saving Register */ + __I uint32_t C12DSADS; /*!< MDMA ch 12 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C12DSNUM; /*!< MDMA ch 12 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED15[2]; + __I uint32_t C13XFTYP; /*!< MDMA ch 13 Transfer Type Saving Register */ + __I uint32_t C13XFSAD; /*!< MDMA ch 13 Transfer Source Address Saving Register*/ + __I uint32_t C13XFDAD; /*!< MDMA ch 13 Transfer Destination Address Saving Register*/ + __I uint32_t C13XFSIZ; /*!< MDMA ch 13 Transfer Size Saving Register */ + __I uint32_t C13DSADS; /*!< MDMA ch 13 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C13DSNUM; /*!< MDMA ch 13 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED16[2]; + __I uint32_t C14XFTYP; /*!< MDMA ch 14 Transfer Type Saving Register */ + __I uint32_t C14XFSAD; /*!< MDMA ch 14 Transfer Source Address Saving Register*/ + __I uint32_t C14XFDAD; /*!< MDMA ch 14 Transfer Destination Address Saving Register*/ + __I uint32_t C14XFSIZ; /*!< MDMA ch 14 Transfer Size Saving Register */ + __I uint32_t C14DSADS; /*!< MDMA ch 14 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C14DSNUM; /*!< MDMA ch 14 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED17[2]; + __I uint32_t C15XFTYP; /*!< MDMA ch 15 Transfer Type Saving Register */ + __I uint32_t C15XFSAD; /*!< MDMA ch 15 Transfer Source Address Saving Register*/ + __I uint32_t C15XFDAD; /*!< MDMA ch 15 Transfer Destination Address Saving Register*/ + __I uint32_t C15XFSIZ; /*!< MDMA ch 15 Transfer Size Saving Register */ + __I uint32_t C15DSADS; /*!< MDMA ch 15 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C15DSNUM; /*!< MDMA ch 15 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED18[2]; + __I uint32_t C16XFTYP; /*!< MDMA ch 16 Transfer Type Saving Register */ + __I uint32_t C16XFSAD; /*!< MDMA ch 16 Transfer Source Address Saving Register*/ + __I uint32_t C16XFDAD; /*!< MDMA ch 16 Transfer Destination Address Saving Register*/ + __I uint32_t C16XFSIZ; /*!< MDMA ch 16 Transfer Size Saving Register */ + __I uint32_t C16DSADS; /*!< MDMA ch 16 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C16DSNUM; /*!< MDMA ch 16 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED19[2]; + __I uint32_t C17XFTYP; /*!< MDMA ch 17 Transfer Type Saving Register */ + __I uint32_t C17XFSAD; /*!< MDMA ch 17 Transfer Source Address Saving Register*/ + __I uint32_t C17XFDAD; /*!< MDMA ch 17 Transfer Destination Address Saving Register*/ + __I uint32_t C17XFSIZ; /*!< MDMA ch 17 Transfer Size Saving Register */ + __I uint32_t C17DSADS; /*!< MDMA ch 17 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C17DSNUM; /*!< MDMA ch 17 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED20[2]; + __I uint32_t C18XFTYP; /*!< MDMA ch 18 Transfer Type Saving Register */ + __I uint32_t C18XFSAD; /*!< MDMA ch 18 Transfer Source Address Saving Register*/ + __I uint32_t C18XFDAD; /*!< MDMA ch 18 Transfer Destination Address Saving Register*/ + __I uint32_t C18XFSIZ; /*!< MDMA ch 18 Transfer Size Saving Register */ + __I uint32_t C18DSADS; /*!< MDMA ch 18 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C18DSNUM; /*!< MDMA ch 18 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED21[2]; + __I uint32_t C19XFTYP; /*!< MDMA ch 19 Transfer Type Saving Register */ + __I uint32_t C19XFSAD; /*!< MDMA ch 19 Transfer Source Address Saving Register*/ + __I uint32_t C19XFDAD; /*!< MDMA ch 19 Transfer Destination Address Saving Register*/ + __I uint32_t C19XFSIZ; /*!< MDMA ch 19 Transfer Size Saving Register */ + __I uint32_t C19DSADS; /*!< MDMA ch 19 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C19DSNUM; /*!< MDMA ch 19 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED22[2]; + __I uint32_t C20XFTYP; /*!< MDMA ch 20 Transfer Type Saving Register */ + __I uint32_t C20XFSAD; /*!< MDMA ch 20 Transfer Source Address Saving Register*/ + __I uint32_t C20XFDAD; /*!< MDMA ch 20 Transfer Destination Address Saving Register*/ + __I uint32_t C20XFSIZ; /*!< MDMA ch 20 Transfer Size Saving Register */ + __I uint32_t C20DSADS; /*!< MDMA ch 20 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C20DSNUM; /*!< MDMA ch 20 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED23[2]; + __I uint32_t C21XFTYP; /*!< MDMA ch 21 Transfer Type Saving Register */ + __I uint32_t C21XFSAD; /*!< MDMA ch 21 Transfer Source Address Saving Register*/ + __I uint32_t C21XFDAD; /*!< MDMA ch 21 Transfer Destination Address Saving Register*/ + __I uint32_t C21XFSIZ; /*!< MDMA ch 21 Transfer Size Saving Register */ + __I uint32_t C21DSADS; /*!< MDMA ch 21 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C21DSNUM; /*!< MDMA ch 21 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED24[2]; + __I uint32_t C22XFTYP; /*!< MDMA ch 22 Transfer Type Saving Register */ + __I uint32_t C22XFSAD; /*!< MDMA ch 22 Transfer Source Address Saving Register*/ + __I uint32_t C22XFDAD; /*!< MDMA ch 22 Transfer Destination Address Saving Register*/ + __I uint32_t C22XFSIZ; /*!< MDMA ch 22 Transfer Size Saving Register */ + __I uint32_t C22DSADS; /*!< MDMA ch 22 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C22DSNUM; /*!< MDMA ch 22 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED25[2]; + __I uint32_t C23XFTYP; /*!< MDMA ch 23 Transfer Type Saving Register */ + __I uint32_t C23XFSAD; /*!< MDMA ch 23 Transfer Source Address Saving Register*/ + __I uint32_t C23XFDAD; /*!< MDMA ch 23 Transfer Destination Address Saving Register*/ + __I uint32_t C23XFSIZ; /*!< MDMA ch 23 Transfer Size Saving Register */ + __I uint32_t C23DSADS; /*!< MDMA ch 23 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C23DSNUM; /*!< MDMA ch 23 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED26[2]; + __I uint32_t C24XFTYP; /*!< MDMA ch 24 Transfer Type Saving Register */ + __I uint32_t C24XFSAD; /*!< MDMA ch 24 Transfer Source Address Saving Register*/ + __I uint32_t C24XFDAD; /*!< MDMA ch 24 Transfer Destination Address Saving Register*/ + __I uint32_t C24XFSIZ; /*!< MDMA ch 24 Transfer Size Saving Register */ + __I uint32_t C24DSADS; /*!< MDMA ch 24 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C24DSNUM; /*!< MDMA ch 24 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED27[2]; + __I uint32_t C25XFTYP; /*!< MDMA ch 25 Transfer Type Saving Register */ + __I uint32_t C25XFSAD; /*!< MDMA ch 25 Transfer Source Address Saving Register*/ + __I uint32_t C25XFDAD; /*!< MDMA ch 25 Transfer Destination Address Saving Register*/ + __I uint32_t C25XFSIZ; /*!< MDMA ch 25 Transfer Size Saving Register */ + __I uint32_t C25DSADS; /*!< MDMA ch 25 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C25DSNUM; /*!< MDMA ch 25 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED28[2]; + __I uint32_t C26XFTYP; /*!< MDMA ch 26 Transfer Type Saving Register */ + __I uint32_t C26XFSAD; /*!< MDMA ch 26 Transfer Source Address Saving Register*/ + __I uint32_t C26XFDAD; /*!< MDMA ch 26 Transfer Destination Address Saving Register*/ + __I uint32_t C26XFSIZ; /*!< MDMA ch 26 Transfer Size Saving Register */ + __I uint32_t C26DSADS; /*!< MDMA ch 26 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C26DSNUM; /*!< MDMA ch 26 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED29[2]; + __I uint32_t C27XFTYP; /*!< MDMA ch 27 Transfer Type Saving Register */ + __I uint32_t C27XFSAD; /*!< MDMA ch 27 Transfer Source Address Saving Register*/ + __I uint32_t C27XFDAD; /*!< MDMA ch 27 Transfer Destination Address Saving Register*/ + __I uint32_t C27XFSIZ; /*!< MDMA ch 27 Transfer Size Saving Register */ + __I uint32_t C27DSADS; /*!< MDMA ch 27 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C27DSNUM; /*!< MDMA ch 27 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED30[2]; + __I uint32_t C28XFTYP; /*!< MDMA ch 28 Transfer Type Saving Register */ + __I uint32_t C28XFSAD; /*!< MDMA ch 28 Transfer Source Address Saving Register*/ + __I uint32_t C28XFDAD; /*!< MDMA ch 28 Transfer Destination Address Saving Register*/ + __I uint32_t C28XFSIZ; /*!< MDMA ch 28 Transfer Size Saving Register */ + __I uint32_t C28DSADS; /*!< MDMA ch 28 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C28DSNUM; /*!< MDMA ch 28 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED31[2]; + __I uint32_t C29XFTYP; /*!< MDMA ch 29 Transfer Type Saving Register */ + __I uint32_t C29XFSAD; /*!< MDMA ch 29 Transfer Source Address Saving Register*/ + __I uint32_t C29XFDAD; /*!< MDMA ch 29 Transfer Destination Address Saving Register*/ + __I uint32_t C29XFSIZ; /*!< MDMA ch 29 Transfer Size Saving Register */ + __I uint32_t C29DSADS; /*!< MDMA ch 29 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C29DSNUM; /*!< MDMA ch 29 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED32[2]; + __I uint32_t C30XFTYP; /*!< MDMA ch 30 Transfer Type Saving Register */ + __I uint32_t C30XFSAD; /*!< MDMA ch 30 Transfer Source Address Saving Register*/ + __I uint32_t C30XFDAD; /*!< MDMA ch 30 Transfer Destination Address Saving Register*/ + __I uint32_t C30XFSIZ; /*!< MDMA ch 30 Transfer Size Saving Register */ + __I uint32_t C30DSADS; /*!< MDMA ch 30 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C30DSNUM; /*!< MDMA ch 30 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED33[2]; + __I uint32_t C31XFTYP; /*!< MDMA ch 31 Transfer Type Saving Register */ + __I uint32_t C31XFSAD; /*!< MDMA ch 31 Transfer Source Address Saving Register*/ + __I uint32_t C31XFDAD; /*!< MDMA ch 31 Transfer Destination Address Saving Register*/ + __I uint32_t C31XFSIZ; /*!< MDMA ch 31 Transfer Size Saving Register */ + __I uint32_t C31DSADS; /*!< MDMA ch 31 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C31DSNUM; /*!< MDMA ch 31 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED34[238]; + __IO uint32_t MSK; /*!< MDMA Transfer Request Mask Register */ +} TSB_MDMA_TypeDef; + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#pragma anon_unions +#elif (defined (__ICCARM__)) /* ICC Compiler */ +#pragma language=extended +#endif + +/** + * @brief ARM Prime Cell PL011 + */ +typedef struct { + __IO uint32_t DR; /*!< FUART Data Register */ + union { + __I uint32_t RSR; /*!< FUART Receive Status Register */ + __O uint32_t ECR; /*!< FUART Error Clear Register */ + }; + uint32_t RESERVED0[4]; + __I uint32_t FR; /*!< FUART Flag Register */ + uint32_t RESERVED1; + __IO uint32_t ILPR; /*!< FUART IrDA Low-power Counter register */ + __IO uint32_t BRD; /*!< FUART Integer Baud Rate Register */ + __IO uint32_t FBRD; /*!< FUART Fractional Baud Rate Register */ + __IO uint32_t LCR_H; /*!< FUART Line Control Register */ + __IO uint32_t CR; /*!< FUART Cntrol Register */ + __IO uint32_t IFLS; /*!< FUART Interrupt FIFO Level Select Register */ + __IO uint32_t IMSC; /*!< FUART Interrupt Mask Set/Clear Register */ + __I uint32_t RIS; /*!< FUART Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< FUART Masked Interrupt Status Register */ + __O uint32_t ICR; /*!< FUART Interrupt Clear Register */ + __IO uint32_t DMACR; /*!< FUART DMA Control Register */ +} TSB_FURT_TypeDef; + +/** + * @brief ADC + */ +typedef struct { + __IO uint32_t CR0; /*!< AD Control Register 0 */ + __IO uint32_t CR1; /*!< AD Control Register 1 */ + __I uint32_t ST; /*!< AD Status Register */ + __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ + __IO uint32_t MOD0; /*!< AD Mode Setting Register 0 */ + __IO uint32_t MOD1; /*!< AD Mode Setting Register 1 */ + __IO uint32_t MOD2; /*!< AD Mode Setting Register 2 */ + uint32_t RESERVED0; + __IO uint32_t CMPEN; /*!< Monitor function Enable Register */ + __IO uint32_t CMPCR0; /*!< AD Monitor function Setting Register 0 */ + __IO uint32_t CMPCR1; /*!< AD Monitor function Setting Register 1 */ + __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ + __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ + uint32_t RESERVED1[34]; + __IO uint32_t EXAZSEL; /*!< AD External AIN sampling period selection Register*/ + __IO uint32_t TSET0; /*!< AD Start-up Factor Program Register 0 */ + __IO uint32_t TSET1; /*!< AD Start-up Factor Program Register 1 */ + __IO uint32_t TSET2; /*!< AD Start-up Factor Program Register 2 */ + __IO uint32_t TSET3; /*!< AD Start-up Factor Program Register 3 */ + __IO uint32_t TSET4; /*!< AD Start-up Factor Program Register 4 */ + __IO uint32_t TSET5; /*!< AD Start-up Factor Program Register 5 */ + __IO uint32_t TSET6; /*!< AD Start-up Factor Program Register 6 */ + __IO uint32_t TSET7; /*!< AD Start-up Factor Program Register 7 */ + __IO uint32_t TSET8; /*!< AD Start-up Factor Program Register 8 */ + __IO uint32_t TSET9; /*!< AD Start-up Factor Program Register 9 */ + __IO uint32_t TSET10; /*!< AD Start-up Factor Program Register 10 */ + __IO uint32_t TSET11; /*!< AD Start-up Factor Program Register 11 */ + __IO uint32_t TSET12; /*!< AD Start-up Factor Program Register 12 */ + __IO uint32_t TSET13; /*!< AD Start-up Factor Program Register 13 */ + __IO uint32_t TSET14; /*!< AD Start-up Factor Program Register 14 */ + __IO uint32_t TSET15; /*!< AD Start-up Factor Program Register 15 */ + __IO uint32_t TSET16; /*!< AD Start-up Factor Program Register 16 */ + __IO uint32_t TSET17; /*!< AD Start-up Factor Program Register 17 */ + __IO uint32_t TSET18; /*!< AD Start-up Factor Program Register 18 */ + __IO uint32_t TSET19; /*!< AD Start-up Factor Program Register 19 */ + __IO uint32_t TSET20; /*!< AD Start-up Factor Program Register 20 */ + __IO uint32_t TSET21; /*!< AD Start-up Factor Program Register 21 */ + __IO uint32_t TSET22; /*!< AD Start-up Factor Program Register 22 */ + __IO uint32_t TSET23; /*!< AD Start-up Factor Program Register 23 */ + uint32_t RESERVED2[8]; + __I uint32_t REG0; /*!< AD Conversion Result Storage Register 0 */ + __I uint32_t REG1; /*!< AD Conversion Result Storage Register 1 */ + __I uint32_t REG2; /*!< AD Conversion Result Storage Register 2 */ + __I uint32_t REG3; /*!< AD Conversion Result Storage Register 3 */ + __I uint32_t REG4; /*!< AD Conversion Result Storage Register 4 */ + __I uint32_t REG5; /*!< AD Conversion Result Storage Register 5 */ + __I uint32_t REG6; /*!< AD Conversion Result Storage Register 6 */ + __I uint32_t REG7; /*!< AD Conversion Result Storage Register 7 */ + __I uint32_t REG8; /*!< AD Conversion Result Storage Register 8 */ + __I uint32_t REG9; /*!< AD Conversion Result Storage Register 9 */ + __I uint32_t REG10; /*!< AD Conversion Result Storage Register 10 */ + __I uint32_t REG11; /*!< AD Conversion Result Storage Register 11 */ + __I uint32_t REG12; /*!< AD Conversion Result Storage Register 12 */ + __I uint32_t REG13; /*!< AD Conversion Result Storage Register 13 */ + __I uint32_t REG14; /*!< AD Conversion Result Storage Register 14 */ + __I uint32_t REG15; /*!< AD Conversion Result Storage Register 15 */ + __I uint32_t REG16; /*!< AD Conversion Result Storage Register 16 */ + __I uint32_t REG17; /*!< AD Conversion Result Storage Register 17 */ + __I uint32_t REG18; /*!< AD Conversion Result Storage Register 18 */ + __I uint32_t REG19; /*!< AD Conversion Result Storage Register 19 */ + __I uint32_t REG20; /*!< AD Conversion Result Storage Register 20 */ + __I uint32_t REG21; /*!< AD Conversion Result Storage Register 21 */ + __I uint32_t REG22; /*!< AD Conversion Result Storage Register 22 */ + __I uint32_t REG23; /*!< AD Conversion Result Storage Register 23 */ +} TSB_AD_TypeDef; + +/** + * @brief Digital analog converter (DAC) + */ +typedef struct { + __IO uint32_t CR; /*!< DAC Control Register */ + __IO uint32_t REG; /*!< DAC Converted Value Setting Register */ +} TSB_DA_TypeDef; + +/** + * @brief 16-bit Timer/Event Counter (TB) + */ +typedef struct { + __IO uint32_t MOD; /*!< T32A Mode Register */ + uint32_t RESERVED0[15]; + __IO uint32_t RUNA; /*!< T32A Run Register A */ + __IO uint32_t CRA; /*!< T32A Counter Control Register A */ + __IO uint32_t CAPCRA; /*!< T32A Capture Control Register A */ + __O uint32_t OUTCRA0; /*!< T32A Output Control Register A0 */ + __IO uint32_t OUTCRA1; /*!< T32A Output Control Register A1 */ + __IO uint32_t STA; /*!< T32A Status Register A */ + __IO uint32_t IMA; /*!< T32A Interrupt Mask Register A */ + __I uint32_t TMRA; /*!< T32A Counter Capture Register A */ + __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ + __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ + __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ + __I uint32_t CAPA0; /*!< T32A Timer Capture A0 Register */ + __I uint32_t CAPA1; /*!< T32A Timer Cupture A1 Register */ + __IO uint32_t DMAA; /*!< T32A DMA Request Enable Register A */ + uint32_t RESERVED1[2]; + __IO uint32_t RUNB; /*!< T32A Run Register B */ + __IO uint32_t CRB; /*!< T32A Counter Control Register B */ + __IO uint32_t CAPCRB; /*!< T32A Capture Control Register B */ + __O uint32_t OUTCRB0; /*!< T32A Output Control Register B0 */ + __IO uint32_t OUTCRB1; /*!< T32A Output Control Register B1 */ + __IO uint32_t STB; /*!< T32A Status Register B */ + __IO uint32_t IMB; /*!< T32A Interrupt Mask Register B */ + __I uint32_t TMRB; /*!< T32A Counter Capture Register B */ + __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ + __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ + __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ + __I uint32_t CAPB0; /*!< T32A Timer Capture B0 Register */ + __I uint32_t CAPB1; /*!< T32A Timer Capture B1 Register */ + __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ + uint32_t RESERVED2[2]; + __IO uint32_t RUNC; /*!< T32A Run Register C */ + __IO uint32_t CRC; /*!< T32A Counter Control Register C */ + __IO uint32_t CAPCRC; /*!< T32A Capture Control Register C */ + __O uint32_t OUTCRC0; /*!< T32A Output Control Register C0 */ + __IO uint32_t OUTCRC1; /*!< T32A Output Control Register C1 */ + __IO uint32_t STC; /*!< T32A Status Register C */ + __IO uint32_t IMC; /*!< T32A Interrupt Mask Register C */ + __I uint32_t TMRC; /*!< T32A Counter Capture Register C */ + __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ + __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ + __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ + __I uint32_t CAPC0; /*!< T32A Timer Capture C0 Register */ + __I uint32_t CAPC1; /*!< T32A Capture Register C1 */ + __IO uint32_t DMAC; /*!< T32A DMA Request Enable Register C */ + __IO uint32_t PLSCR; /*!< T32A Pulse Count Control Register */ +} TSB_T32A_TypeDef; + +/** + * @brief TSSI + */ +typedef struct { + __IO uint32_t CR0; /*!< TSSI Control Register 0 */ + __IO uint32_t CR1; /*!< TSSI Control Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t CPR; /*!< TSSI Clock Divider Register */ + uint32_t RESERVED1[11]; + __IO uint32_t RCMR; /*!< TSSI Receive Clock / Mode Control Register */ + __IO uint32_t RFMR; /*!< TSSI Receive Data Frame Control Register */ + __IO uint32_t RCR; /*!< TSSI Receive Data Comparison Register */ + __IO uint32_t RDMACR; /*!< TSSI Receive DMA Control Register */ + uint32_t RESERVED2[4]; + __IO uint32_t RSR; /*!< TSSI Reception Status Register */ + __IO uint32_t RIER; /*!< TSSI Receive Interrupt Enable Register */ + uint32_t RESERVED3[2]; + __IO uint32_t RFTLR; /*!< TSSI Receive FIFO Threshold Register */ + __I uint32_t RFLR; /*!< TSSI Receive FIFO Entry Register */ + uint32_t RESERVED4[2]; + __I uint32_t RDR0; /*!< TSSI Receive Data Register 0 */ + __I uint32_t RDR1; /*!< TSSI Receive Data Register 1 */ + __I uint32_t RDR2; /*!< TSSI Receive Data Register 2 */ + __I uint32_t RDR3; /*!< TSSI Receive Data Register 3 */ + uint32_t RESERVED5[4]; + __IO uint32_t TCMR; /*!< TSSI Transmit Clock / Mode Control Register */ + __IO uint32_t TFMR; /*!< TSSI Transmit Data Frame Control Register */ + uint32_t RESERVED6; + __IO uint32_t TDMACR; /*!< TSSI Transmit DMA Control Register */ + uint32_t RESERVED7[4]; + __IO uint32_t TSR; /*!< TSSI Transmission Status Register */ + __IO uint32_t TIER; /*!< TSSI Transmission Interrupt Enable Register */ + uint32_t RESERVED8[2]; + __IO uint32_t TFTLR; /*!< TSSI Transmit FIFO Threshold Register */ + __I uint32_t TFLR; /*!< TSSI Transmit FIFO Entry Register */ + uint32_t RESERVED9[2]; + __O uint32_t TDR0; /*!< TSSI Transmission Data Register 0 */ + __O uint32_t TDR1; /*!< TSSI Transmission Data Register 1 */ + __O uint32_t TDR2; /*!< TSSI Transmission Data Register 2 */ + __O uint32_t TDR3; /*!< TSSI Transmission Data Register 3 */ +} TSB_TSSI_TypeDef; + +/** + * @brief UART + */ +typedef struct { + __IO uint32_t SWRST; /*!< UART Software Reset Register */ + __IO uint32_t CR0; /*!< UART Control Register 0 */ + __IO uint32_t CR1; /*!< UART Control Register 1 */ + __IO uint32_t CLK; /*!< UART Clock Control Register */ + __IO uint32_t BRD; /*!< UART Baud Rate Register */ + __IO uint32_t TRANS; /*!< UART Transfer Enable Register */ + __IO uint32_t DR; /*!< UART Data Register */ + __IO uint32_t SR; /*!< UART Status Register */ + __O uint32_t FIFOCLR; /*!< UART FIFO Clear Register */ + __IO uint32_t ERR; /*!< UART Error Register */ +} TSB_UART_TypeDef; + +/** + * @brief I2S interface + */ +typedef struct { + uint32_t RESERVED0; + __IO uint32_t CSTART; /*!< I2S Clock LRCK Generation Start Register */ + __I uint32_t CBUSY; /*!< I2S Clock LRCK Generation Status Register */ + __IO uint32_t CSTOP; /*!< I2S Clock LRCK Generation Stop Register */ + __IO uint32_t CAUDIOSET; /*!< I2S Clock AUDIOSET Register */ + uint32_t RESERVED1[11]; + __I uint32_t CREGBUSY; /*!< I2S Clock REGBUSY Register */ + uint32_t RESERVED2[45]; + __IO uint32_t CMODESET; /*!< I2S Clock Audio Data Format Setting Register */ + uint32_t RESERVED3[65]; + __IO uint32_t CMS_SEL; /*!< I2S Clock Master/Slave Select Register */ + __IO uint32_t CMCLK_IO_SEL; /*!< I2S Clock MCLK pin input/output Selection Register*/ + uint32_t RESERVED4[3]; + __IO uint32_t CPHT_DIV; /*!< I2S Clock Phi T0 Frequency Division Setting Register*/ + __IO uint32_t CPHT_DIVOUT_EN; /*!< I2S Clock Phi T0 Divided Clock Output Enable Register*/ + uint32_t RESERVED5; + __IO uint32_t CBCK_SRC_SEL; /*!< I2S Clock BCK Source Clock Select Register */ + __IO uint32_t CBCK_DIV; /*!< I2S Clock BCK Frequency Division Setting Register*/ + __IO uint32_t CBCK_DIVOUT_EN; /*!< I2S Clock BCK Output Enable Register */ + uint32_t RESERVED6[118]; + __IO uint32_t ISTART; /*!< I2S Receive Control Start Register */ + __I uint32_t IBUSY; /*!< I2S Receive Operation Status Register */ + __IO uint32_t ISTOP; /*!< I2S Data Receive Stop Register */ + __IO uint32_t IAUDIOSET; /*!< I2S Receive AUDIOSET Register */ + __I uint32_t IINTSTAT; /*!< I2S Receive Control Interrupt Status Register*/ + __IO uint32_t IINTMASK; /*!< I2S Receive Control Interrupt Mask Register */ + __IO uint32_t IINTCLR; /*!< I2S Receive Control Interrupt Clear Register */ + uint32_t RESERVED7; + __IO uint32_t IMUTE; /*!< I2S Receive Mute Setting Register */ + __I uint32_t IEPTR; /*!< I2S Receive Control Error Occurrence Address Storage Register*/ + uint32_t RESERVED8[5]; + __I uint32_t IREGBUSY; /*!< I2S Receive REGBUSY register */ + uint32_t RESERVED9[3]; + __IO uint32_t ITHRESHOLD; /*!< I2S Receive Threshold Setting Register */ + __I uint32_t IFIFO_STS; /*!< I2S Receive FIFO Status Register */ + uint32_t RESERVED10[40]; + __IO uint32_t IMODESET; /*!< I2S Receive Audio Data Format Setting Register*/ + uint32_t RESERVED11; + __I uint32_t ILMEM00; /*!< I2S Receive Data Storage Register 00 */ + __I uint32_t ILMEM01; /*!< I2S Receive Data Storage Register 01 */ + __I uint32_t ILMEM02; /*!< I2S Receive Data Storage Register 02 */ + __I uint32_t ILMEM03; /*!< I2S Receive Data Storage Register 03 */ + __I uint32_t ILMEM04; /*!< I2S Receive Data Storage Register 04 */ + __I uint32_t ILMEM05; /*!< I2S Receive Data Storage Register 05 */ + __I uint32_t ILMEM06; /*!< I2S Receive Data Storage Register 06 */ + __I uint32_t ILMEM07; /*!< I2S Receive Data Storage Register 07 */ + __I uint32_t ILMEM08; /*!< I2S Receive Data Storage Register 08 */ + __I uint32_t ILMEM09; /*!< I2S Receive Data Storage Register 09 */ + __I uint32_t ILMEM10; /*!< I2S Receive Data Storage Register 10 */ + __I uint32_t ILMEM11; /*!< I2S Receive Data Storage Register 11 */ + __I uint32_t ILMEM12; /*!< I2S Receive Data Storage Register 12 */ + __I uint32_t ILMEM13; /*!< I2S Receive Data Storage Register 13 */ + __I uint32_t ILMEM14; /*!< I2S Receive Data Storage Register 14 */ + __I uint32_t ILMEM15; /*!< I2S Receive Data Storage Register 15 */ + __I uint32_t ILMEM16; /*!< I2S Receive Data Storage Register 16 */ + __I uint32_t ILMEM17; /*!< I2S Receive Data Storage Register 17 */ + __I uint32_t ILMEM18; /*!< I2S Receive Data Storage Register 18 */ + __I uint32_t ILMEM19; /*!< I2S Receive Data Storage Register 19 */ + __I uint32_t ILMEM20; /*!< I2S Receive Data Storage Register 20 */ + __I uint32_t ILMEM21; /*!< I2S Receive Data Storage Register 21 */ + __I uint32_t ILMEM22; /*!< I2S Receive Data Storage Register 22 */ + __I uint32_t ILMEM23; /*!< I2S Receive Data Storage Register 23 */ + __I uint32_t ILMEM24; /*!< I2S Receive Data Storage Register 24 */ + __I uint32_t ILMEM25; /*!< I2S Receive Data Storage Register 25 */ + __I uint32_t ILMEM26; /*!< I2S Receive Data Storage Register 26 */ + __I uint32_t ILMEM27; /*!< I2S Receive Data Storage Register 27 */ + __I uint32_t ILMEM28; /*!< I2S Receive Data Storage Register 28 */ + __I uint32_t ILMEM29; /*!< I2S Receive Data Storage Register 29 */ + __I uint32_t ILMEM30; /*!< I2S Receive Data Storage Register 30 */ + __I uint32_t ILMEM31; /*!< I2S Receive Data Storage Register 31 */ + __I uint32_t ILMEM32; /*!< I2S Receive Data Storage Register 32 */ + __I uint32_t ILMEM33; /*!< I2S Receive Data Storage Register 33 */ + __I uint32_t ILMEM34; /*!< I2S Receive Data Storage Register 34 */ + __I uint32_t ILMEM35; /*!< I2S Receive Data Storage Register 35 */ + __I uint32_t ILMEM36; /*!< I2S Receive Data Storage Register 36 */ + __I uint32_t ILMEM37; /*!< I2S Receive Data Storage Register 37 */ + __I uint32_t ILMEM38; /*!< I2S Receive Data Storage Register 38 */ + __I uint32_t ILMEM39; /*!< I2S Receive Data Storage Register 39 */ + __I uint32_t ILMEM40; /*!< I2S Receive Data Storage Register 40 */ + __I uint32_t ILMEM41; /*!< I2S Receive Data Storage Register 41 */ + __I uint32_t ILMEM42; /*!< I2S Receive Data Storage Register 42 */ + __I uint32_t ILMEM43; /*!< I2S Receive Data Storage Register 43 */ + __I uint32_t ILMEM44; /*!< I2S Receive Data Storage Register 44 */ + __I uint32_t ILMEM45; /*!< I2S Receive Data Storage Register 45 */ + __I uint32_t ILMEM46; /*!< I2S Receive Data Storage Register 46 */ + __I uint32_t ILMEM47; /*!< I2S Receive Data Storage Register 47 */ + __I uint32_t ILMEM48; /*!< I2S Receive Data Storage Register 48 */ + __I uint32_t ILMEM49; /*!< I2S Receive Data Storage Register 49 */ + __I uint32_t ILMEM50; /*!< I2S Receive Data Storage Register 50 */ + __I uint32_t ILMEM51; /*!< I2S Receive Data Storage Register 51 */ + __I uint32_t ILMEM52; /*!< I2S Receive Data Storage Register 52 */ + __I uint32_t ILMEM53; /*!< I2S Receive Data Storage Register 53 */ + __I uint32_t ILMEM54; /*!< I2S Receive Data Storage Register 54 */ + __I uint32_t ILMEM55; /*!< I2S Receive Data Storage Register 55 */ + __I uint32_t ILMEM56; /*!< I2S Receive Data Storage Register 56 */ + __I uint32_t ILMEM57; /*!< I2S Receive Data Storage Register 57 */ + __I uint32_t ILMEM58; /*!< I2S Receive Data Storage Register 58 */ + __I uint32_t ILMEM59; /*!< I2S Receive Data Storage Register 59 */ + __I uint32_t ILMEM60; /*!< I2S Receive Data Storage Register 60 */ + __I uint32_t ILMEM61; /*!< I2S Receive Data Storage Register 61 */ + __I uint32_t ILMEM62; /*!< I2S Receive Data Storage Register 62 */ + __I uint32_t ILMEM63; /*!< I2S Receive Data Storage Register 63 */ + uint32_t RESERVED12; + __IO uint32_t OSTART; /*!< I2S Transmit Control Start Register */ + __I uint32_t OBUSY; /*!< I2S Transmit Operation Status Register */ + __IO uint32_t OSTOP; /*!< I2S Data Transmit Stop Register */ + __IO uint32_t OAUDIOSET; /*!< I2S Transmit AUDIOSET Register */ + __I uint32_t OINTSTAT; /*!< I2S Transmit Control Interrupt Status Register*/ + __IO uint32_t OINTMASK; /*!< I2S Transmit Control Interrupt Mask Register */ + __IO uint32_t OINTCLR; /*!< I2S Transmit Control Interrupt Clear Register*/ + uint32_t RESERVED13; + __IO uint32_t OMUTE; /*!< I2S Transmit Mute Setting Register */ + __I uint32_t OEPTR; /*!< I2S Transmit Control Error Occurrence Address Storage Register*/ + uint32_t RESERVED14; + __IO uint32_t OTX_SSIZE; /*!< I2S TX_SSIZE Register */ + uint32_t RESERVED15[3]; + __I uint32_t OREGBUSY; /*!< I2S Transmit REGBUSY Register */ + uint32_t RESERVED16[3]; + __IO uint32_t OTHRESHOLD; /*!< I2S Transmit Threshold Setting Register */ + __I uint32_t OFIFO_STS; /*!< I2S Transmit FIFO Status Register */ + uint32_t RESERVED17[40]; + __IO uint32_t OMODESET; /*!< I2S Transmit Audio Data Format Setting Register*/ + uint32_t RESERVED18; + __O uint32_t OLMEM00; /*!< I2S Transmit Data Storage Register 00 */ + __O uint32_t OLMEM01; /*!< I2S Transmit Data Storage Register 01 */ + __O uint32_t OLMEM02; /*!< I2S Transmit Data Storage Register 02 */ + __O uint32_t OLMEM03; /*!< I2S Transmit Data Storage Register 03 */ + __O uint32_t OLMEM04; /*!< I2S Transmit Data Storage Register 04 */ + __O uint32_t OLMEM05; /*!< I2S Transmit Data Storage Register 05 */ + __O uint32_t OLMEM06; /*!< I2S Transmit Data Storage Register 06 */ + __O uint32_t OLMEM07; /*!< I2S Transmit Data Storage Register 07 */ + __O uint32_t OLMEM08; /*!< I2S Transmit Data Storage Register 08 */ + __O uint32_t OLMEM09; /*!< I2S Transmit Data Storage Register 09 */ + __O uint32_t OLMEM10; /*!< I2S Transmit Data Storage Register 10 */ + __O uint32_t OLMEM11; /*!< I2S Transmit Data Storage Register 11 */ + __O uint32_t OLMEM12; /*!< I2S Transmit Data Storage Register 12 */ + __O uint32_t OLMEM13; /*!< I2S Transmit Data Storage Register 13 */ + __O uint32_t OLMEM14; /*!< I2S Transmit Data Storage Register 14 */ + __O uint32_t OLMEM15; /*!< I2S Transmit Data Storage Register 15 */ + __O uint32_t OLMEM16; /*!< I2S Transmit Data Storage Register 16 */ + __O uint32_t OLMEM17; /*!< I2S Transmit Data Storage Register 17 */ + __O uint32_t OLMEM18; /*!< I2S Transmit Data Storage Register 18 */ + __O uint32_t OLMEM19; /*!< I2S Transmit Data Storage Register 19 */ + __O uint32_t OLMEM20; /*!< I2S Transmit Data Storage Register 20 */ + __O uint32_t OLMEM21; /*!< I2S Transmit Data Storage Register 21 */ + __O uint32_t OLMEM22; /*!< I2S Transmit Data Storage Register 22 */ + __O uint32_t OLMEM23; /*!< I2S Transmit Data Storage Register 23 */ + __O uint32_t OLMEM24; /*!< I2S Transmit Data Storage Register 24 */ + __O uint32_t OLMEM25; /*!< I2S Transmit Data Storage Register 25 */ + __O uint32_t OLMEM26; /*!< I2S Transmit Data Storage Register 26 */ + __O uint32_t OLMEM27; /*!< I2S Transmit Data Storage Register 27 */ + __O uint32_t OLMEM28; /*!< I2S Transmit Data Storage Register 28 */ + __O uint32_t OLMEM29; /*!< I2S Transmit Data Storage Register 29 */ + __O uint32_t OLMEM30; /*!< I2S Transmit Data Storage Register 30 */ + __O uint32_t OLMEM31; /*!< I2S Transmit Data Storage Register 31 */ + __O uint32_t OLMEM32; /*!< I2S Transmit Data Storage Register 32 */ + __O uint32_t OLMEM33; /*!< I2S Transmit Data Storage Register 33 */ + __O uint32_t OLMEM34; /*!< I2S Transmit Data Storage Register 34 */ + __O uint32_t OLMEM35; /*!< I2S Transmit Data Storage Register 35 */ + __O uint32_t OLMEM36; /*!< I2S Transmit Data Storage Register 36 */ + __O uint32_t OLMEM37; /*!< I2S Transmit Data Storage Register 37 */ + __O uint32_t OLMEM38; /*!< I2S Transmit Data Storage Register 38 */ + __O uint32_t OLMEM39; /*!< I2S Transmit Data Storage Register 39 */ + __O uint32_t OLMEM40; /*!< I2S Transmit Data Storage Register 40 */ + __O uint32_t OLMEM41; /*!< I2S Transmit Data Storage Register 41 */ + __O uint32_t OLMEM42; /*!< I2S Transmit Data Storage Register 42 */ + __O uint32_t OLMEM43; /*!< I2S Transmit Data Storage Register 43 */ + __O uint32_t OLMEM44; /*!< I2S Transmit Data Storage Register 44 */ + __O uint32_t OLMEM45; /*!< I2S Transmit Data Storage Register 45 */ + __O uint32_t OLMEM46; /*!< I2S Transmit Data Storage Register 46 */ + __O uint32_t OLMEM47; /*!< I2S Transmit Data Storage Register 47 */ + __O uint32_t OLMEM48; /*!< I2S Transmit Data Storage Register 48 */ + __O uint32_t OLMEM49; /*!< I2S Transmit Data Storage Register 49 */ + __O uint32_t OLMEM50; /*!< I2S Transmit Data Storage Register 50 */ + __O uint32_t OLMEM51; /*!< I2S Transmit Data Storage Register 51 */ + __O uint32_t OLMEM52; /*!< I2S Transmit Data Storage Register 52 */ + __O uint32_t OLMEM53; /*!< I2S Transmit Data Storage Register 53 */ + __O uint32_t OLMEM54; /*!< I2S Transmit Data Storage Register 54 */ + __O uint32_t OLMEM55; /*!< I2S Transmit Data Storage Register 55 */ + __O uint32_t OLMEM56; /*!< I2S Transmit Data Storage Register 56 */ + __O uint32_t OLMEM57; /*!< I2S Transmit Data Storage Register 57 */ + __O uint32_t OLMEM58; /*!< I2S Transmit Data Storage Register 58 */ + __O uint32_t OLMEM59; /*!< I2S Transmit Data Storage Register 59 */ + __O uint32_t OLMEM60; /*!< I2S Transmit Data Storage Register 60 */ + __O uint32_t OLMEM61; /*!< I2S Transmit Data Storage Register 61 */ + __O uint32_t OLMEM62; /*!< I2S Transmit Data Storage Register 62 */ + __O uint32_t OLMEM63; /*!< I2S Transmit Data Storage Register 63 */ +} TSB_I2S_TypeDef; + +/** + * @brief I2C + */ +typedef struct { + __IO uint32_t CR1; /*!< I2C Control Register 1 */ + __IO uint32_t DBR; /*!< I2C Data Buffer Register */ + __IO uint32_t AR; /*!< I2C Bus address Register */ + union { + __O uint32_t CR2; /*!< I2C Control Register 2 */ + __I uint32_t SR; /*!< I2C Status Register */ + }; + __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ + __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ + __IO uint32_t ST; /*!< I2C Interruption Status Register */ + __IO uint32_t OP; /*!< I2C Expanded function setting Register */ + __I uint32_t PM; /*!< I2C Bus pin Monitor Register */ + __IO uint32_t AR2; /*!< I2C 2nd address Register */ +} TSB_I2C_TypeDef; + +/** + * @brief EI2C + */ +typedef struct { + __IO uint32_t ARST; /*!< I2C Reset Register */ + __IO uint32_t AEN; /*!< I2C Bus Enable Register */ + __IO uint32_t ACR0; /*!< I2C Control Register 0 */ + __IO uint32_t ACR1; /*!< I2C Control Register 1 */ + __IO uint32_t ADBRT; /*!< I2C Transmit Data Buffer Register */ + __I uint32_t ADBRR; /*!< I2C Receive Data Buffer Register */ + __I uint32_t ASR0; /*!< I2C Status Register 0 */ + __IO uint32_t ASR1; /*!< I2C Status Register 1 */ + __IO uint32_t APRS; /*!< I2C Prescaler Clock Setting Register */ + __IO uint32_t ASCL; /*!< I2C SCL Wdth Setting Register */ + __IO uint32_t AAR1; /*!< I2C 1st Slave Address Register */ + __IO uint32_t AAR2; /*!< I2C 2nd Slave Address Register */ + __IO uint32_t AIE; /*!< I2C Interrupt DMA Setting Register */ + __I uint32_t APM; /*!< I2C Bus Terminal Monitor Setting Register */ +} TSB_EI2C_TypeDef; + +/** + * @brief Finite Impulse Response + */ +typedef struct { + __IO uint32_t START; /*!< FIR Start Register */ + __IO uint32_t CTRL; /*!< FIR Control Register */ + __IO uint32_t INITIALIZE; /*!< FIR Initialize Register */ + __IO uint32_t INITDATA; /*!< FIR Init data Register */ + __IO uint32_t INTEN; /*!< FIR Interrupt Enable Register */ + __IO uint32_t DMAEN; /*!< FIR DMA Enable Register */ + __IO uint32_t RAWINTSTAT; /*!< FIR Raw Interrupt Status Register */ + __I uint32_t SEQSTAT; /*!< FIR Sequencer Status Register */ + __IO uint32_t DBUFWPTR; /*!< FIR Data Buffer Write Pointer Register */ + __IO uint32_t DBUFRPTR; /*!< FIR Data Buffer Read Pointer Register */ + uint32_t RESERVED0[2]; + __IO uint32_t IDATA; /*!< FIR Input Data Register */ + __I uint32_t ODATA; /*!< FIR Output Data Register */ + uint32_t RESERVED1[2]; + __IO uint32_t COEF0; /*!< FIR Coefficient Register0 */ + __IO uint32_t COEF1; /*!< FIR Coefficient Register1 */ + __IO uint32_t COEF2; /*!< FIR Coefficient Register2 */ + __IO uint32_t COEF3; /*!< FIR Coefficient Register3 */ + __IO uint32_t COEF4; /*!< FIR Coefficient Register4 */ + __IO uint32_t COEF5; /*!< FIR Coefficient Register5 */ + __IO uint32_t COEF6; /*!< FIR Coefficient Register6 */ + __IO uint32_t COEF7; /*!< FIR Coefficient Register7 */ + __IO uint32_t COEF8; /*!< FIR Coefficient Register8 */ + __IO uint32_t COEF9; /*!< FIR Coefficient Register9 */ + __IO uint32_t COEF10; /*!< FIR Coefficient Register10 */ + __IO uint32_t COEF11; /*!< FIR Coefficient Register11 */ + __IO uint32_t COEF12; /*!< FIR Coefficient Register12 */ + __IO uint32_t COEF13; /*!< FIR Coefficient Register13 */ + __IO uint32_t COEF14; /*!< FIR Coefficient Register14 */ + __IO uint32_t COEF15; /*!< FIR Coefficient Register15 */ + __IO uint32_t COEF16; /*!< FIR Coefficient Register16 */ + __IO uint32_t COEF17; /*!< FIR Coefficient Register17 */ + __IO uint32_t COEF18; /*!< FIR Coefficient Register18 */ + __IO uint32_t COEF19; /*!< FIR Coefficient Register19 */ + __IO uint32_t COEF20; /*!< FIR Coefficient Register20 */ + __IO uint32_t COEF21; /*!< FIR Coefficient Register21 */ + __IO uint32_t COEF22; /*!< FIR Coefficient Register22 */ + __IO uint32_t COEF23; /*!< FIR Coefficient Register23 */ + __IO uint32_t COEF24; /*!< FIR Coefficient Register24 */ + __IO uint32_t COEF25; /*!< FIR Coefficient Register25 */ + __IO uint32_t COEF26; /*!< FIR Coefficient Register26 */ + __IO uint32_t COEF27; /*!< FIR Coefficient Register27 */ + __IO uint32_t COEF28; /*!< FIR Coefficient Register28 */ + __IO uint32_t COEF29; /*!< FIR Coefficient Register29 */ + __IO uint32_t COEF30; /*!< FIR Coefficient Register30 */ + __IO uint32_t COEF31; /*!< FIR Coefficient Register31 */ + __IO uint32_t COEF32; /*!< FIR Coefficient Register32 */ + __IO uint32_t COEF33; /*!< FIR Coefficient Register33 */ + __IO uint32_t COEF34; /*!< FIR Coefficient Register34 */ + __IO uint32_t COEF35; /*!< FIR Coefficient Register35 */ + __IO uint32_t COEF36; /*!< FIR Coefficient Register36 */ + __IO uint32_t COEF37; /*!< FIR Coefficient Register37 */ + __IO uint32_t COEF38; /*!< FIR Coefficient Register38 */ + __IO uint32_t COEF39; /*!< FIR Coefficient Register39 */ + __IO uint32_t COEF40; /*!< FIR Coefficient Register40 */ + __IO uint32_t COEF41; /*!< FIR Coefficient Register41 */ + __IO uint32_t COEF42; /*!< FIR Coefficient Register42 */ + __IO uint32_t COEF43; /*!< FIR Coefficient Register43 */ + __IO uint32_t COEF44; /*!< FIR Coefficient Register44 */ + __IO uint32_t COEF45; /*!< FIR Coefficient Register45 */ + __IO uint32_t COEF46; /*!< FIR Coefficient Register46 */ + __IO uint32_t COEF47; /*!< FIR Coefficient Register47 */ + __IO uint32_t COEF48; /*!< FIR Coefficient Register48 */ + __IO uint32_t COEF49; /*!< FIR Coefficient Register49 */ + __IO uint32_t COEF50; /*!< FIR Coefficient Register50 */ + __IO uint32_t COEF51; /*!< FIR Coefficient Register51 */ + __IO uint32_t COEF52; /*!< FIR Coefficient Register52 */ + __IO uint32_t COEF53; /*!< FIR Coefficient Register53 */ + __IO uint32_t COEF54; /*!< FIR Coefficient Register54 */ + __IO uint32_t COEF55; /*!< FIR Coefficient Register55 */ + __IO uint32_t COEF56; /*!< FIR Coefficient Register56 */ + __IO uint32_t COEF57; /*!< FIR Coefficient Register57 */ + __IO uint32_t COEF58; /*!< FIR Coefficient Register58 */ + __IO uint32_t COEF59; /*!< FIR Coefficient Register59 */ + __IO uint32_t COEF60; /*!< FIR Coefficient Register60 */ + __IO uint32_t COEF61; /*!< FIR Coefficient Register61 */ + __IO uint32_t COEF62; /*!< FIR Coefficient Register62 */ + __IO uint32_t COEF63; /*!< FIR Coefficient Register63 */ + __IO uint32_t COEF64; /*!< FIR Coefficient Register64 */ + __IO uint32_t COEF65; /*!< FIR Coefficient Register65 */ + __IO uint32_t COEF66; /*!< FIR Coefficient Register66 */ + __IO uint32_t COEF67; /*!< FIR Coefficient Register67 */ + __IO uint32_t COEF68; /*!< FIR Coefficient Register68 */ + __IO uint32_t COEF69; /*!< FIR Coefficient Register69 */ + __IO uint32_t COEF70; /*!< FIR Coefficient Register70 */ + __IO uint32_t COEF71; /*!< FIR Coefficient Register71 */ + __IO uint32_t COEF72; /*!< FIR Coefficient Register72 */ + __IO uint32_t COEF73; /*!< FIR Coefficient Register73 */ + __IO uint32_t COEF74; /*!< FIR Coefficient Register74 */ + __IO uint32_t COEF75; /*!< FIR Coefficient Register75 */ + __IO uint32_t COEF76; /*!< FIR Coefficient Register76 */ + __IO uint32_t COEF77; /*!< FIR Coefficient Register77 */ + __IO uint32_t COEF78; /*!< FIR Coefficient Register78 */ + __IO uint32_t COEF79; /*!< FIR Coefficient Register79 */ + __IO uint32_t COEF80; /*!< FIR Coefficient Register80 */ + __IO uint32_t COEF81; /*!< FIR Coefficient Register81 */ + __IO uint32_t COEF82; /*!< FIR Coefficient Register82 */ + __IO uint32_t COEF83; /*!< FIR Coefficient Register83 */ + __IO uint32_t COEF84; /*!< FIR Coefficient Register84 */ + __IO uint32_t COEF85; /*!< FIR Coefficient Register85 */ + __IO uint32_t COEF86; /*!< FIR Coefficient Register86 */ + __IO uint32_t COEF87; /*!< FIR Coefficient Register87 */ + __IO uint32_t COEF88; /*!< FIR Coefficient Register88 */ + __IO uint32_t COEF89; /*!< FIR Coefficient Register89 */ + __IO uint32_t COEF90; /*!< FIR Coefficient Register90 */ + __IO uint32_t COEF91; /*!< FIR Coefficient Register91 */ + __IO uint32_t COEF92; /*!< FIR Coefficient Register92 */ + __IO uint32_t COEF93; /*!< FIR Coefficient Register93 */ + __IO uint32_t COEF94; /*!< FIR Coefficient Register94 */ + __IO uint32_t COEF95; /*!< FIR Coefficient Register95 */ + __IO uint32_t COEF96; /*!< FIR Coefficient Register96 */ + __IO uint32_t COEF97; /*!< FIR Coefficient Register97 */ + __IO uint32_t COEF98; /*!< FIR Coefficient Register98 */ + __IO uint32_t COEF99; /*!< FIR Coefficient Register99 */ + __IO uint32_t COEF100; /*!< FIR Coefficient Register100 */ + __IO uint32_t COEF101; /*!< FIR Coefficient Register101 */ + __IO uint32_t COEF102; /*!< FIR Coefficient Register102 */ + __IO uint32_t COEF103; /*!< FIR Coefficient Register103 */ + __IO uint32_t COEF104; /*!< FIR Coefficient Register104 */ + __IO uint32_t COEF105; /*!< FIR Coefficient Register105 */ + __IO uint32_t COEF106; /*!< FIR Coefficient Register106 */ + __IO uint32_t COEF107; /*!< FIR Coefficient Register107 */ + __IO uint32_t COEF108; /*!< FIR Coefficient Register108 */ + __IO uint32_t COEF109; /*!< FIR Coefficient Register109 */ + __IO uint32_t COEF110; /*!< FIR Coefficient Register110 */ + __IO uint32_t COEF111; /*!< FIR Coefficient Register111 */ + __IO uint32_t COEF112; /*!< FIR Coefficient Register112 */ + __IO uint32_t COEF113; /*!< FIR Coefficient Register113 */ + __IO uint32_t COEF114; /*!< FIR Coefficient Register114 */ + __IO uint32_t COEF115; /*!< FIR Coefficient Register115 */ + __IO uint32_t COEF116; /*!< FIR Coefficient Register116 */ + __IO uint32_t COEF117; /*!< FIR Coefficient Register117 */ + __IO uint32_t COEF118; /*!< FIR Coefficient Register118 */ + __IO uint32_t COEF119; /*!< FIR Coefficient Register119 */ + __IO uint32_t COEF120; /*!< FIR Coefficient Register120 */ + __IO uint32_t COEF121; /*!< FIR Coefficient Register121 */ + __IO uint32_t COEF122; /*!< FIR Coefficient Register122 */ + __IO uint32_t COEF123; /*!< FIR Coefficient Register123 */ + __IO uint32_t COEF124; /*!< FIR Coefficient Register124 */ + __IO uint32_t COEF125; /*!< FIR Coefficient Register125 */ + __IO uint32_t COEF126; /*!< FIR Coefficient Register126 */ + __IO uint32_t COEF127; /*!< FIR Coefficient Register127 */ +} TSB_FIR_TypeDef; + +/** + * @brief Port A + */ +typedef struct { + __IO uint32_t DATA; /*!< Port A Data Register */ + __IO uint32_t CR; /*!< Port A Output Control Register */ + __IO uint32_t FR1; /*!< Port A Function Register 1 */ + __IO uint32_t FR2; /*!< Port A Function Register 2 */ + __IO uint32_t FR3; /*!< Port A Function Register 3 */ + uint32_t RESERVED0; + __IO uint32_t FR5; /*!< Port A Function Register 5 */ + __IO uint32_t FR6; /*!< Port A Function Register 6 */ + __IO uint32_t FR7; /*!< Port A Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port A Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port A Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port A Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port A Input Control Register */ +} TSB_PA_TypeDef; + +/** + * @brief Port B + */ +typedef struct { + __IO uint32_t DATA; /*!< Port B Data Register */ + __IO uint32_t CR; /*!< Port B Output Control Register */ + __IO uint32_t FR1; /*!< Port B Function Register 1 */ + __IO uint32_t FR2; /*!< Port B Function Register 2 */ + __IO uint32_t FR3; /*!< Port B Function Register 3 */ + __IO uint32_t FR4; /*!< Port B Function Register 4 */ + __IO uint32_t FR5; /*!< Port B Function Register 5 */ + __IO uint32_t FR6; /*!< Port B Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< Port B Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port B Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port B Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port B Input Control Register */ +} TSB_PB_TypeDef; + +/** + * @brief Port C + */ +typedef struct { + __IO uint32_t DATA; /*!< Port C Data Register */ + __IO uint32_t CR; /*!< Port C Output Control Register */ + __IO uint32_t FR1; /*!< Port C Function Register 1 */ + uint32_t RESERVED0; + __IO uint32_t FR3; /*!< Port C Function Register 3 */ + __IO uint32_t FR4; /*!< Port C Function Register 4 */ + __IO uint32_t FR5; /*!< Port C Function Register 5 */ + uint32_t RESERVED1[3]; + __IO uint32_t OD; /*!< Port C Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port C Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port C Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port C Input Control Register */ +} TSB_PC_TypeDef; + +/** + * @brief Port D + */ +typedef struct { + __IO uint32_t DATA; /*!< Port D Data Register */ + __IO uint32_t CR; /*!< Port D Output Control Register */ + __IO uint32_t FR1; /*!< Port D Function Register 1 */ + __IO uint32_t FR2; /*!< Port D Function Register 2 */ + __IO uint32_t FR3; /*!< Port D Function Register 3 */ + __IO uint32_t FR4; /*!< Port D Function Register 4 */ + __IO uint32_t FR5; /*!< Port D Function Register 5 */ + __IO uint32_t FR6; /*!< Port D Function Register 6 */ + __IO uint32_t FR7; /*!< Port D Function Register 7 */ + __IO uint32_t FR8; /*!< Port D Function Register 8 */ + __IO uint32_t OD; /*!< Port D Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port D Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port D Pull-down Control Register */ + uint32_t RESERVED0; + __IO uint32_t IE; /*!< Port D Input Control Register */ +} TSB_PD_TypeDef; + +/** + * @brief Port E + */ +typedef struct { + __IO uint32_t DATA; /*!< Port E Data Register */ + __IO uint32_t CR; /*!< Port E Output Control Register */ + __IO uint32_t FR1; /*!< Port E Function Register 1 */ + __IO uint32_t FR2; /*!< Port E Function Register 2 */ + __IO uint32_t FR3; /*!< Port E Function Register 3 */ + __IO uint32_t FR4; /*!< Port E Function Register 4 */ + __IO uint32_t FR5; /*!< Port E Function Register 5 */ + __IO uint32_t FR6; /*!< Port E Function Register 6 */ + __IO uint32_t FR7; /*!< Port E Function Register 7 */ + __IO uint32_t FR8; /*!< Port E Function Register 8 */ + __IO uint32_t OD; /*!< Port E Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port E Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port E Pull-down Control Register */ + uint32_t RESERVED0; + __IO uint32_t IE; /*!< Port E Input Control Register */ +} TSB_PE_TypeDef; + +/** + * @brief Port F + */ +typedef struct { + __IO uint32_t DATA; /*!< Port F Data Register */ + __IO uint32_t CR; /*!< Port F Output Control Register */ + __IO uint32_t FR1; /*!< Port F Function Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR4; /*!< Port F Function Register 4 */ + __IO uint32_t FR5; /*!< Port F Function Register 5 */ + __IO uint32_t FR6; /*!< Port F Function Register 6 */ + __IO uint32_t FR7; /*!< Port F Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port F Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port F Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port F Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port F Input Control Register */ +} TSB_PF_TypeDef; + +/** + * @brief Port G + */ +typedef struct { + __IO uint32_t DATA; /*!< Port G Data Register */ + __IO uint32_t CR; /*!< Port G Output Control Register */ + __IO uint32_t FR1; /*!< Port G Function Register 1 */ + __IO uint32_t FR2; /*!< Port G Function Register 2 */ + __IO uint32_t FR3; /*!< Port G Function Register 3 */ + __IO uint32_t FR4; /*!< Port G Function Register 4 */ + __IO uint32_t FR5; /*!< Port G Function Register 5 */ + __IO uint32_t FR6; /*!< Port G Function Register 6 */ + __IO uint32_t FR7; /*!< Port G Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port G Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port G Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port G Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port G Input Control Register */ +} TSB_PG_TypeDef; + +/** + * @brief Port H + */ +typedef struct { + __IO uint32_t DATA; /*!< Port H Data Register */ + __IO uint32_t CR; /*!< Port H Output Control Register */ + __IO uint32_t FR1; /*!< Port H Function Register 1 */ + uint32_t RESERVED0; + __IO uint32_t FR3; /*!< Port H Function Register 3 */ + __IO uint32_t FR4; /*!< Port H Function Register 4 */ + __IO uint32_t FR5; /*!< Port H Function Register 5 */ + uint32_t RESERVED1[3]; + __IO uint32_t OD; /*!< Port H Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port H Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port H Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port H Input Control Register */ +} TSB_PH_TypeDef; + +/** + * @brief Port J + */ +typedef struct { + __IO uint32_t DATA; /*!< Port J Data Register */ + __IO uint32_t CR; /*!< Port J Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port J Function Register 2 */ + __IO uint32_t FR3; /*!< Port J Function Register 3 */ + uint32_t RESERVED1; + __IO uint32_t FR5; /*!< Port J Function Register 5 */ + __IO uint32_t FR6; /*!< Port J Function Register 6 */ + __IO uint32_t FR7; /*!< Port J Function Register 7 */ + uint32_t RESERVED2; + __IO uint32_t OD; /*!< Port J Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port J Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port J Pull-down Control Register */ + uint32_t RESERVED3; + __IO uint32_t IE; /*!< Port J Input Control Register */ +} TSB_PJ_TypeDef; + +/** + * @brief Port K + */ +typedef struct { + __IO uint32_t DATA; /*!< Port K Data Register */ + __IO uint32_t CR; /*!< Port K Output Control Register */ + __IO uint32_t FR1; /*!< Port K Function Register 1 */ + __IO uint32_t FR2; /*!< Port K Function Register 2 */ + __IO uint32_t FR3; /*!< Port K Function Register 3 */ + __IO uint32_t FR4; /*!< Port K Function Register 4 */ + __IO uint32_t FR5; /*!< Port K Function Register 5 */ + __IO uint32_t FR6; /*!< Port K Function Register 6 */ + __IO uint32_t FR7; /*!< Port K Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port K Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port K Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port K Pull-up Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port K Input Control Register */ +} TSB_PK_TypeDef; + +/** + * @brief Port L + */ +typedef struct { + __IO uint32_t DATA; /*!< Port L Data Register */ + __IO uint32_t CR; /*!< Port L Output Control Register */ + __IO uint32_t FR1; /*!< Port L Function Register 1 */ + __IO uint32_t FR2; /*!< Port L Function Register 2 */ + __IO uint32_t FR3; /*!< Port L Function Register 3 */ + uint32_t RESERVED0; + __IO uint32_t FR5; /*!< Port L Function Register 5 */ + __IO uint32_t FR6; /*!< Port L Function Register 6 */ + __IO uint32_t FR7; /*!< Port L Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port L Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port L Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port L Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port L Input Control Register */ +} TSB_PL_TypeDef; + +/** + * @brief Port M + */ +typedef struct { + __IO uint32_t DATA; /*!< Port M Data Register */ + __IO uint32_t CR; /*!< Port M Output Control Register */ + __IO uint32_t FR1; /*!< Port M Function Register 1 */ + __IO uint32_t FR2; /*!< Port M Function Register 2 */ + __IO uint32_t FR3; /*!< Port M Function Register 3 */ + __IO uint32_t FR4; /*!< Port M Function Register 4 */ + __IO uint32_t FR5; /*!< Port M Function Register 5 */ + __IO uint32_t FR6; /*!< Port M Function Register 6 */ + __IO uint32_t FR7; /*!< Port M Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port M Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port M Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port M Pull-up Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port M Input Control Register */ +} TSB_PM_TypeDef; + +/** + * @brief Port N + */ +typedef struct { + __IO uint32_t DATA; /*!< Port N Data Register */ + __IO uint32_t CR; /*!< Port N Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port N Opend Drain Control Register */ + __IO uint32_t PUP; /*!< Port N Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port N Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port N Input Control Register */ +} TSB_PN_TypeDef; + +/** + * @brief Port P + */ +typedef struct { + __IO uint32_t DATA; /*!< Port P Data Register */ + __IO uint32_t CR; /*!< Port P Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port P Function Register 2 */ + __IO uint32_t FR3; /*!< Port P Function Register 3 */ + uint32_t RESERVED1; + __IO uint32_t FR5; /*!< Port P Function Register 5 */ + uint32_t RESERVED2[3]; + __IO uint32_t OD; /*!< Port P Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port P Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port P Pull-down Control Register */ + uint32_t RESERVED3; + __IO uint32_t IE; /*!< Port P Input Control Register */ +} TSB_PP_TypeDef; + +/** + * @brief Port R + */ +typedef struct { + __IO uint32_t DATA; /*!< Port R Data Register */ + __IO uint32_t CR; /*!< Port R Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port R Function Register 2 */ + __IO uint32_t FR3; /*!< Port R Function Register 3 */ + uint32_t RESERVED1[5]; + __IO uint32_t OD; /*!< Port R Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port R Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port R Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port R Input Control Register */ +} TSB_PR_TypeDef; + +/** + * @brief Port T + */ +typedef struct { + __IO uint32_t DATA; /*!< Port T Data Register */ + __IO uint32_t CR; /*!< Port T Output Control Register */ + __IO uint32_t FR1; /*!< Port T Function Register 1 */ + __IO uint32_t FR2; /*!< Port T Function Register 2 */ + __IO uint32_t FR3; /*!< Port T Function Register 3 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR6; /*!< Port T Function Register 6 */ + __IO uint32_t FR7; /*!< Port T Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port T Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port T Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port T Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port T Input Control Register */ +} TSB_PT_TypeDef; + +/** + * @brief Port U + */ +typedef struct { + __IO uint32_t DATA; /*!< Port U Data Register */ + __IO uint32_t CR; /*!< Port U Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port U Function Register 2 */ + __IO uint32_t FR3; /*!< Port U Function Register 3 */ + uint32_t RESERVED1[2]; + __IO uint32_t FR6; /*!< Port U Function Register 6 */ + __IO uint32_t FR7; /*!< Port U Function Register 7 */ + uint32_t RESERVED2; + __IO uint32_t OD; /*!< Port U Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port U Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port U Pull-down Control Register */ + uint32_t RESERVED3; + __IO uint32_t IE; /*!< Port U Input Control Register */ +} TSB_PU_TypeDef; + +/** + * @brief Port V + */ +typedef struct { + __IO uint32_t DATA; /*!< Port V Data Register */ + __IO uint32_t CR; /*!< Port V OutPut Control Register */ + __IO uint32_t FR1; /*!< Port V Function Register 1 */ + __IO uint32_t FR2; /*!< Port V Function Register 2 */ + __IO uint32_t FR3; /*!< Port V Function Register 3 */ + __IO uint32_t FR4; /*!< Port V Function Register 4 */ + __IO uint32_t FR5; /*!< Port V Function Register 5 */ + __IO uint32_t FR6; /*!< Port V Function Register 6 */ + __IO uint32_t FR7; /*!< Port V Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port V Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port V Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port V Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port V InPut Control Register */ +} TSB_PV_TypeDef; + +/** + * @brief Port W + */ +typedef struct { + __IO uint32_t DATA; /*!< Port W Data Register */ + __IO uint32_t CR; /*!< Port W OutPut Control Register */ + uint32_t RESERVED0[2]; + __IO uint32_t FR3; /*!< Port W Function Register 3 */ + __IO uint32_t FR4; /*!< Port W Function Register 4 */ + __IO uint32_t FR5; /*!< Port W Function Register 5 */ + __IO uint32_t FR6; /*!< Port W Function Register 6 */ + __IO uint32_t FR7; /*!< Port W Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port W Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port W Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port W Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port W InPut Control Register */ +} TSB_PW_TypeDef; + +/** + * @brief Port Y + */ +typedef struct { + __IO uint32_t DATA; /*!< Port Y Data Register */ + __IO uint32_t CR; /*!< Port Y OutPut Control Register */ + __IO uint32_t FR1; /*!< Port Y Function Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR4; /*!< Port Y Function Register 4 */ + uint32_t RESERVED1[4]; + __IO uint32_t OD; /*!< Port Y Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port Y Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port Y Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port Y InPut Control Register */ +} TSB_PY_TypeDef; + +/** + * @brief Internal High-speed Oscillation Adjustment + */ +typedef struct { + __IO uint32_t OSCPRO; /*!< TRM Protection Register */ + __IO uint32_t OSCEN; /*!< TRM User Trimming Value Enable Register */ + uint32_t RESERVED0[2]; + __I uint32_t OSCINIT0; /*!< TRM Initial trimming level monitor register0 */ + __I uint32_t OSCINIT1; /*!< TRM Initial trimming level monitor register1 */ + __I uint32_t OSCINIT2; /*!< TRM Initial trimming level monitor register2 */ + uint32_t RESERVED1; + __IO uint32_t OSCSET0; /*!< TRM Trimming level setting register0 for User*/ + __IO uint32_t OSCSET1; /*!< TRM Trimming level setting register1 for User*/ + __IO uint32_t OSCSET2; /*!< TRM Trimming level setting register2 for User*/ +} TSB_TRM_TypeDef; + +/** + * @brief Oscillation Frequency Detector (OFD) + */ +typedef struct { + __IO uint32_t CR1; /*!< OFD Frequency Detection Control Register 1 */ + __IO uint32_t CR2; /*!< OFD Frequency Detection Control Register 2 */ + __IO uint32_t MN0; /*!< OFD Minimum Detection Frequency Setting Register 0 (EHOSC)*/ + __IO uint32_t MN1; /*!< OFD Minimum Detection Frequency Setting Register 1 (fc)*/ + __IO uint32_t MX0; /*!< OFD Maximum Detection Frequency Setting Register 0 (EHOSC)*/ + __IO uint32_t MX1; /*!< OFD Maximum Detection Frequency Setting Register 1 (fc)*/ + __IO uint32_t RST; /*!< OFD Reset Control Register */ + __I uint32_t STAT; /*!< OFD Status Register */ + __IO uint32_t MON; /*!< OFD Detection Target Clock 1 Monitor Setting Register*/ +} TSB_OFD_TypeDef; + +/** + * @brief Real Time Clock (RTC) + */ +typedef struct { + __IO uint8_t SECR; /*!< RTC Second column register (PAGE0) */ + __IO uint8_t MINR; /*!< RTC Minute column register (PAGE0/1) */ + __IO uint8_t HOURR; /*!< RTC Hour column register (PAGE0/1) */ + uint8_t RESERVED0; + __IO uint8_t DAYR; /*!< RTC Day of the week column register (PAGE0/1)*/ + __IO uint8_t DATER; /*!< RTC Day column register (PAGE0/1) */ + __IO uint8_t MONTHR; /*!< RTC Month column register (PAGE0) */ + __IO uint8_t YEARR; /*!< RTC Year column register (PAGE0) */ + __IO uint8_t PAGER; /*!< RTC PAGE register (PAGE0/1) */ + uint8_t RESERVED1[3]; + __IO uint8_t RESTR; /*!< RTC Reset register (PAGE0/1) */ + uint8_t RESERVED2; + __IO uint8_t PROTECT; /*!< RTC Protect register */ + __IO uint8_t ADJCTL; /*!< RTC Correction Function Control Register */ + __IO uint8_t ADJDAT; /*!< RTC Correction Value Register */ + __IO uint8_t ADJSIGN; /*!< RTC Correction Value sign Register */ +} TSB_RTC_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct { + __IO uint32_t EN; /*!< CEC Enable Register */ + __IO uint32_t ADD; /*!< CEC Logical Address Register */ + __O uint32_t RESET; /*!< CEC Software Reset Register */ + __IO uint32_t REN; /*!< CEC Receive Enable Register */ + __I uint32_t RBUF; /*!< CEC Receive Buffer Register */ + __IO uint32_t RCR1; /*!< CEC Receive Control Register 1 */ + __IO uint32_t RCR2; /*!< CEC Receive Control Register 2 */ + __IO uint32_t RCR3; /*!< CEC Receive Control Register 3 */ + __IO uint32_t TEN; /*!< CEC Transmit Enable Register */ + __IO uint32_t TBUF; /*!< CEC Transmit Buffer Register */ + __IO uint32_t TCR; /*!< CEC Transmit Control Register */ + __I uint32_t RSTAT; /*!< CEC Receive Interrupt Status Register */ + __I uint32_t TSTAT; /*!< CEC Transmit Interrupt Status Register */ + __IO uint32_t FSSEL; /*!< CEC sampling clock select Register */ +} TSB_CEC_TypeDef; + +/** + * @brief Remote Control Signal Preprocessor (RMC) + */ +typedef struct { + __IO uint32_t EN; /*!< RMC Enable Register */ + __IO uint32_t REN; /*!< RMC Receive Enable Register */ + __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ + __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ + __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ + __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ + __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ + __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ + __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ + __I uint32_t RSTAT; /*!< RMC Receive Status Register */ + __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ + __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ + __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ + __IO uint32_t FSSEL; /*!< RMC Sampling Clock Selection Register */ +} TSB_RMC_TypeDef; + +/** + * @brief + */ +typedef struct { + __IO uint32_t MDEN; /*!< PMD Enable Register */ + __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ + __IO uint32_t MDCR; /*!< PMD Control Register */ + __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ + __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ + __IO uint32_t RATE; /*!< PWM Frequency Register */ + __IO uint32_t CMPU; /*!< PMD PWM duty comparison U Register */ + __IO uint32_t CMPV; /*!< PMD PWM duty comparison V Register */ + __IO uint32_t CMPW; /*!< PMD PWM duty comparison W Register */ + __IO uint32_t MODESEL; /*!< PMD Mode Select Register */ + __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ + __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ + __O uint32_t EMGREL; /*!< PMD EMG Release Register */ + __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ + __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ + __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ + __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ + __IO uint32_t DTR; /*!< PMD Dead Time Register */ + __IO uint32_t TRGCMP0; /*!< PMD Trigger comparison Register 0 */ + __IO uint32_t TRGCMP1; /*!< PMD Trigger comparison Register 1 */ + __IO uint32_t TRGCMP2; /*!< PMD Trigger comparison Register 2 */ + __IO uint32_t TRGCMP3; /*!< PMD Trigger comparison Register 3 */ + __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ + __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ + __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ + __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ + __IO uint32_t VPWMPH; /*!< PMD V-phase phase difference register */ + __IO uint32_t WPWMPH; /*!< PMD W-phase phase difference register */ + __IO uint32_t MBUFCR; /*!< PMD Intermediate buffer control register */ + __IO uint32_t SYNCCR; /*!< Synchronization control between the PMD channel*/ +} TSB_PMD_TypeDef; + +/** + * @brief + */ +typedef struct { + __IO uint32_t EN; /*!< Interval Sencing Detector(ISD) */ + __IO uint32_t CLKCR; /*!< ISD Clock Control Register */ + __IO uint32_t OCR0; /*!< ISD Output Control Register 0 */ + __IO uint32_t OCR1; /*!< ISD Output Control Register 1 */ + __IO uint32_t ICR; /*!< ISD Input Control Register */ + __IO uint32_t CR; /*!< ISD Control Register */ + __I uint32_t BR; /*!< ISD Buffer Register */ + __I uint32_t SR; /*!< ISD Status Register */ + __IO uint32_t INTCR; /*!< ISD Interrupt Control Register */ +} TSB_ISD_TypeDef; + +/** + * @brief + */ +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ + __IO uint32_t SSR; /*!< Flash Security Status Register */ + __O uint32_t KCR; /*!< Flash Key Code Register */ + uint32_t RESERVED1; + __IO uint32_t SR0; /*!< Flash Status Register 0 */ + uint32_t RESERVED2[3]; + __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ + __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ + __I uint32_t PSR2; /*!< Flash Protect Status Register 2 */ + uint32_t RESERVED3[3]; + __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ + uint32_t RESERVED4; + __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ + __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ + __IO uint32_t PMR2; /*!< Flash Protect Mask Register 2 */ + uint32_t RESERVED5[3]; + __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ + uint32_t RESERVED6[37]; + __I uint32_t SR1; /*!< Flash Status Register 1 */ + __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ + uint32_t RESERVED7[14]; + __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ + uint32_t RESERVED8; + __IO uint32_t CR; /*!< Flash Control Register */ + __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ + __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ + __IO uint32_t ACCR; /*!< Flash Access Control Register */ + __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ + uint32_t RESERVED9[1071]; + __IO uint32_t RACCR; /*!< RAM Access Control Register */ +} TSB_FC_TypeDef; + + +/* Memory map */ +#define FLASH_BASE (0x00000000UL) +#define RAM_BASE (0x20000000UL) +#define PERI_BASE (0x40000000UL) + + +#define TSB_DMACA_BASE (PERI_BASE + 0x0000000UL) +#define TSB_DMACB_BASE (PERI_BASE + 0x0001000UL) +#define TSB_SMI0_BASE (PERI_BASE + 0x000C000UL) +#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) +#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) +#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) +#define TSB_TSEL0_BASE (PERI_BASE + 0x00A0400UL) +#define TSB_LTT0_BASE (PERI_BASE + 0x003FF00UL) +#define TSB_TSPI0_BASE (PERI_BASE + 0x006A000UL) +#define TSB_TSPI1_BASE (PERI_BASE + 0x006A400UL) +#define TSB_TSPI2_BASE (PERI_BASE + 0x006A800UL) +#define TSB_TSPI3_BASE (PERI_BASE + 0x006AC00UL) +#define TSB_TSPI4_BASE (PERI_BASE + 0x006B000UL) +#define TSB_TSPI5_BASE (PERI_BASE + 0x006B400UL) +#define TSB_TSPI6_BASE (PERI_BASE + 0x00CB800UL) +#define TSB_TSPI7_BASE (PERI_BASE + 0x00CBC00UL) +#define TSB_TSPI8_BASE (PERI_BASE + 0x00CC000UL) +#define TSB_EXB_BASE (PERI_BASE + 0x0076000UL) +#define TSB_CG_BASE (PERI_BASE + 0x0083000UL) +#define TSB_IB_BASE (PERI_BASE + 0x0083200UL) +#define TSB_IMN_BASE (PERI_BASE + 0x0083300UL) +#define TSB_DNFA_BASE (PERI_BASE + 0x00A0200UL) +#define TSB_DNFB_BASE (PERI_BASE + 0x00A0300UL) +#define TSB_SIWD0_BASE (PERI_BASE + 0x00A0600UL) +#define TSB_NBD_BASE (PERI_BASE + 0x00A2000UL) +#define TSB_MDMAA_BASE (PERI_BASE + 0x00A4000UL) +#define TSB_FURT0_BASE (PERI_BASE + 0x00A8000UL) +#define TSB_FURT1_BASE (PERI_BASE + 0x00A9000UL) +#define TSB_ADA_BASE (PERI_BASE + 0x00BA000UL) +#define TSB_DA0_BASE (PERI_BASE + 0x00BC800UL) +#define TSB_DA1_BASE (PERI_BASE + 0x00BC900UL) +#define TSB_T32A0_BASE (PERI_BASE + 0x00C1000UL) +#define TSB_T32A1_BASE (PERI_BASE + 0x00C1400UL) +#define TSB_T32A2_BASE (PERI_BASE + 0x00C1800UL) +#define TSB_T32A3_BASE (PERI_BASE + 0x00C1C00UL) +#define TSB_T32A4_BASE (PERI_BASE + 0x00C2000UL) +#define TSB_T32A5_BASE (PERI_BASE + 0x00C2400UL) +#define TSB_T32A6_BASE (PERI_BASE + 0x00C2800UL) +#define TSB_T32A7_BASE (PERI_BASE + 0x00C2C00UL) +#define TSB_T32A8_BASE (PERI_BASE + 0x00C3000UL) +#define TSB_T32A9_BASE (PERI_BASE + 0x00C3400UL) +#define TSB_T32A10_BASE (PERI_BASE + 0x00C3800UL) +#define TSB_T32A11_BASE (PERI_BASE + 0x00C3C00UL) +#define TSB_T32A12_BASE (PERI_BASE + 0x00C4000UL) +#define TSB_T32A13_BASE (PERI_BASE + 0x00C4400UL) +#define TSB_T32A14_BASE (PERI_BASE + 0x00C4800UL) +#define TSB_T32A15_BASE (PERI_BASE + 0x00C4C00UL) +#define TSB_TSSI0_BASE (PERI_BASE + 0x00CD000UL) +#define TSB_TSSI1_BASE (PERI_BASE + 0x00CD400UL) +#define TSB_UART0_BASE (PERI_BASE + 0x00CE000UL) +#define TSB_UART1_BASE (PERI_BASE + 0x00CE400UL) +#define TSB_UART2_BASE (PERI_BASE + 0x00CE800UL) +#define TSB_UART3_BASE (PERI_BASE + 0x00CEC00UL) +#define TSB_UART4_BASE (PERI_BASE + 0x00CF000UL) +#define TSB_UART5_BASE (PERI_BASE + 0x00CF400UL) +#define TSB_I2S0_BASE (PERI_BASE + 0x00D0000UL) +#define TSB_I2S1_BASE (PERI_BASE + 0x00D0800UL) +#define TSB_I2C0_BASE (PERI_BASE + 0x00D1000UL) +#define TSB_I2C1_BASE (PERI_BASE + 0x00D2000UL) +#define TSB_I2C2_BASE (PERI_BASE + 0x00D3000UL) +#define TSB_I2C3_BASE (PERI_BASE + 0x00D4000UL) +#define TSB_I2C4_BASE (PERI_BASE + 0x00D5000UL) +#define TSB_EI2C0_BASE (PERI_BASE + 0x00D8000UL) +#define TSB_EI2C1_BASE (PERI_BASE + 0x00D9000UL) +#define TSB_EI2C2_BASE (PERI_BASE + 0x00DA000UL) +#define TSB_EI2C3_BASE (PERI_BASE + 0x00DB000UL) +#define TSB_EI2C4_BASE (PERI_BASE + 0x00DC000UL) +#define TSB_FIRnore_BASE (PERI_BASE + 0x00DD000UL) +#define TSB_PA_BASE (PERI_BASE + 0x00E0000UL) +#define TSB_PB_BASE (PERI_BASE + 0x00E0100UL) +#define TSB_PC_BASE (PERI_BASE + 0x00E0200UL) +#define TSB_PD_BASE (PERI_BASE + 0x00E0300UL) +#define TSB_PE_BASE (PERI_BASE + 0x00E0400UL) +#define TSB_PF_BASE (PERI_BASE + 0x00E0500UL) +#define TSB_PG_BASE (PERI_BASE + 0x00E0600UL) +#define TSB_PH_BASE (PERI_BASE + 0x00E0700UL) +#define TSB_PJ_BASE (PERI_BASE + 0x00E0800UL) +#define TSB_PK_BASE (PERI_BASE + 0x00E0900UL) +#define TSB_PL_BASE (PERI_BASE + 0x00E0A00UL) +#define TSB_PM_BASE (PERI_BASE + 0x00E0B00UL) +#define TSB_PN_BASE (PERI_BASE + 0x00E0C00UL) +#define TSB_PP_BASE (PERI_BASE + 0x00E0D00UL) +#define TSB_PR_BASE (PERI_BASE + 0x00E0E00UL) +#define TSB_PT_BASE (PERI_BASE + 0x00E0F00UL) +#define TSB_PU_BASE (PERI_BASE + 0x00E1000UL) +#define TSB_PV_BASE (PERI_BASE + 0x00E1100UL) +#define TSB_PW_BASE (PERI_BASE + 0x00E1200UL) +#define TSB_PY_BASE (PERI_BASE + 0x00E1300UL) +#define TSB_TRM_BASE (PERI_BASE + 0x00E3100UL) +#define TSB_OFD_BASE (PERI_BASE + 0x00E4000UL) +#define TSB_RTC_BASE (PERI_BASE + 0x00E4800UL) +#define TSB_CEC0_BASE (PERI_BASE + 0x00E8000UL) +#define TSB_RMC0_BASE (PERI_BASE + 0x00E8100UL) +#define TSB_RMC1_BASE (PERI_BASE + 0x00E8200UL) +#define TSB_PMD0_BASE (PERI_BASE + 0x00E9000UL) +#define TSB_ISDA_BASE (PERI_BASE + 0x00F0000UL) +#define TSB_ISDB_BASE (PERI_BASE + 0x00F0100UL) +#define TSB_ISDC_BASE (PERI_BASE + 0x00F0200UL) +#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) + + +/* Peripheral declaration */ +#define TSB_DMACA (( TSB_DMAC_TypeDef *) TSB_DMACA_BASE) +#define TSB_DMACB (( TSB_DMAC_TypeDef *) TSB_DMACB_BASE) +#define TSB_SMI0 (( TSB_SMI_TypeDef *) TSB_SMI0_BASE) +#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) +#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) +#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) +#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) +#define TSB_LTT0 (( TSB_LTT_TypeDef *) TSB_LTT0_BASE) +#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) +#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) +#define TSB_TSPI2 (( TSB_TSPI_TypeDef *) TSB_TSPI2_BASE) +#define TSB_TSPI3 (( TSB_TSPI_TypeDef *) TSB_TSPI3_BASE) +#define TSB_TSPI4 (( TSB_TSPI_TypeDef *) TSB_TSPI4_BASE) +#define TSB_TSPI5 (( TSB_TSPI_TypeDef *) TSB_TSPI5_BASE) +#define TSB_TSPI6 (( TSB_TSPI_TypeDef *) TSB_TSPI6_BASE) +#define TSB_TSPI7 (( TSB_TSPI_TypeDef *) TSB_TSPI7_BASE) +#define TSB_TSPI8 (( TSB_TSPI_TypeDef *) TSB_TSPI8_BASE) +#define TSB_EXB (( TSB_EXB_TypeDef *) TSB_EXB_BASE) +#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) +#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) +#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) +#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) +#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) +#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) +#define TSB_NBD (( TSB_NBD_TypeDef *) TSB_NBD_BASE) +#define TSB_MDMAA (( TSB_MDMA_TypeDef *) TSB_MDMAA_BASE) +#define TSB_FURT0 (( TSB_FURT_TypeDef *) TSB_FURT0_BASE) +#define TSB_FURT1 (( TSB_FURT_TypeDef *) TSB_FURT1_BASE) +#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) +#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) +#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) +#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) +#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) +#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) +#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) +#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) +#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) +#define TSB_T32A6 (( TSB_T32A_TypeDef *) TSB_T32A6_BASE) +#define TSB_T32A7 (( TSB_T32A_TypeDef *) TSB_T32A7_BASE) +#define TSB_T32A8 (( TSB_T32A_TypeDef *) TSB_T32A8_BASE) +#define TSB_T32A9 (( TSB_T32A_TypeDef *) TSB_T32A9_BASE) +#define TSB_T32A10 (( TSB_T32A_TypeDef *)TSB_T32A10_BASE) +#define TSB_T32A11 (( TSB_T32A_TypeDef *)TSB_T32A11_BASE) +#define TSB_T32A12 (( TSB_T32A_TypeDef *)TSB_T32A12_BASE) +#define TSB_T32A13 (( TSB_T32A_TypeDef *)TSB_T32A13_BASE) +#define TSB_T32A14 (( TSB_T32A_TypeDef *)TSB_T32A14_BASE) +#define TSB_T32A15 (( TSB_T32A_TypeDef *)TSB_T32A15_BASE) +#define TSB_TSSI0 (( TSB_TSSI_TypeDef *) TSB_TSSI0_BASE) +#define TSB_TSSI1 (( TSB_TSSI_TypeDef *) TSB_TSSI1_BASE) +#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) +#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) +#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) +#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) +#define TSB_UART4 (( TSB_UART_TypeDef *) TSB_UART4_BASE) +#define TSB_UART5 (( TSB_UART_TypeDef *) TSB_UART5_BASE) +#define TSB_I2S0 (( TSB_I2S_TypeDef *) TSB_I2S0_BASE) +#define TSB_I2S1 (( TSB_I2S_TypeDef *) TSB_I2S1_BASE) +#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) +#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) +#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) +#define TSB_I2C3 (( TSB_I2C_TypeDef *) TSB_I2C3_BASE) +#define TSB_I2C4 (( TSB_I2C_TypeDef *) TSB_I2C4_BASE) +#define TSB_EI2C0 (( TSB_EI2C_TypeDef *) TSB_EI2C0_BASE) +#define TSB_EI2C1 (( TSB_EI2C_TypeDef *) TSB_EI2C1_BASE) +#define TSB_EI2C2 (( TSB_EI2C_TypeDef *) TSB_EI2C2_BASE) +#define TSB_EI2C3 (( TSB_EI2C_TypeDef *) TSB_EI2C3_BASE) +#define TSB_EI2C4 (( TSB_EI2C_TypeDef *) TSB_EI2C4_BASE) +#define TSB_FIRnore (( TSB_FIR_TypeDef *)TSB_FIRnore_BASE) +#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) +#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) +#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) +#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) +#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) +#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) +#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) +#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) +#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) +#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) +#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) +#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) +#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) +#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) +#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) +#define TSB_PT (( TSB_PT_TypeDef *) TSB_PT_BASE) +#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) +#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) +#define TSB_PW (( TSB_PW_TypeDef *) TSB_PW_BASE) +#define TSB_PY (( TSB_PY_TypeDef *) TSB_PY_BASE) +#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) +#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) +#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) +#define TSB_CEC0 (( TSB_CEC_TypeDef *) TSB_CEC0_BASE) +#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) +#define TSB_RMC1 (( TSB_RMC_TypeDef *) TSB_RMC1_BASE) +#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) +#define TSB_ISDA (( TSB_ISD_TypeDef *) TSB_ISDA_BASE) +#define TSB_ISDB (( TSB_ISD_TypeDef *) TSB_ISDB_BASE) +#define TSB_ISDC (( TSB_ISD_TypeDef *) TSB_ISDC_BASE) +#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) + + +/* Bit-Band for Device Specific Peripheral Registers */ +#define BITBAND_OFFSET (0x02000000UL) +#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) +#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) + + + +/* DMA Controller */ +#define TSB_DMACA_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,0))) +#define TSB_DMACA_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,1))) +#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,0))) +#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,1))) +#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,0))) +#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,1))) +#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,0))) +#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,1))) +#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,0))) +#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,1))) +#define TSB_DMACA_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,0))) +#define TSB_DMACA_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,1))) +#define TSB_DMACA_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->CONFIGURATION,0))) +#define TSB_DMACA_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,26))) +#define TSB_DMACA_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,27))) +#define TSB_DMACA_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,31))) +#define TSB_DMACA_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,0))) +#define TSB_DMACA_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,14))) +#define TSB_DMACA_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,15))) +#define TSB_DMACA_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,16))) +#define TSB_DMACA_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,17))) +#define TSB_DMACA_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,18))) +#define TSB_DMACA_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,26))) +#define TSB_DMACA_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,27))) +#define TSB_DMACA_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,31))) +#define TSB_DMACA_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,0))) +#define TSB_DMACA_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,14))) +#define TSB_DMACA_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,15))) +#define TSB_DMACA_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,16))) +#define TSB_DMACA_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,17))) +#define TSB_DMACA_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,18))) + +#define TSB_DMACB_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,0))) +#define TSB_DMACB_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,1))) +#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,0))) +#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,1))) +#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,0))) +#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,1))) +#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,0))) +#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,1))) +#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,0))) +#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,1))) +#define TSB_DMACB_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,0))) +#define TSB_DMACB_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,1))) +#define TSB_DMACB_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->CONFIGURATION,0))) +#define TSB_DMACB_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,26))) +#define TSB_DMACB_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,27))) +#define TSB_DMACB_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,31))) +#define TSB_DMACB_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,0))) +#define TSB_DMACB_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,14))) +#define TSB_DMACB_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,15))) +#define TSB_DMACB_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,16))) +#define TSB_DMACB_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,17))) +#define TSB_DMACB_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,18))) +#define TSB_DMACB_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,26))) +#define TSB_DMACB_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,27))) +#define TSB_DMACB_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,31))) +#define TSB_DMACB_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,0))) +#define TSB_DMACB_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,14))) +#define TSB_DMACB_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,15))) +#define TSB_DMACB_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,16))) +#define TSB_DMACB_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,17))) +#define TSB_DMACB_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,18))) + + +/* SMIF */ +#define TSB_SMI0_MAP0_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP0,0))) +#define TSB_SMI0_MAP0_WE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP0,1))) +#define TSB_SMI0_MAP1_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP1,0))) +#define TSB_SMI0_DACR0_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR0,6))) +#define TSB_SMI0_DACR1_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR1,6))) +#define TSB_SMI0_DRCR0_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DRCR0,8))) +#define TSB_SMI0_DRCR1_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DRCR1,8))) +#define TSB_SMI0_DWCR0_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DWCR0,8))) +#define TSB_SMI0_DWCR1_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DWCR1,8))) +#define TSB_SMI0_RACR1_CYCGO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,0))) +#define TSB_SMI0_RACR1_CSNUM (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,1))) +#define TSB_SMI0_RACR1_PBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,4))) +#define TSB_SMI0_RACR1_SBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,5))) +#define TSB_SMI0_OECR_PBUFOCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->OECR,0))) +#define TSB_SMI0_INT_SCDINTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->INT,0))) +#define TSB_SMI0_INT_SDINTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->INT,4))) +#define TSB_SMI0_STAT_CYCDONE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,0))) +#define TSB_SMI0_STAT_CYCPROG (*((__I uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,1))) +#define TSB_SMI0_STAT_STPPROGDONE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,4))) +#define TSB_SMI0_STAT_DIACCINPROG (*((__I uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,6))) +#define TSB_SMI0_SWR_RSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->SWR,0))) +#define TSB_SMI0_ACKR_FRCCLKOUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->ACKR,0))) +#define TSB_SMI0_ACKR_ADDCLKTGLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->ACKR,8))) +#define TSB_SMI0_CCOR_CLKOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->CCOR,0))) +#define TSB_SMI0_CCOR_CS0OE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->CCOR,4))) +#define TSB_SMI0_CCOR_CS1OE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->CCOR,5))) +#define TSB_SMI0_STPR_STOPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STPR,0))) + + + +/* Low speed oscillation/power control/reset */ +#define TSB_RLM_LOSCCR_DRCOSCL (*((__IO uint32_t *)BITBAND_PERI(&TSB_RLM->LOSCCR,2))) + + +/* LVD0 */ +#define TSB_LVD_CR1_LVDNEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,0))) +#define TSB_LVD_CR1_LVDSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,4))) +#define TSB_LVD_CR2_LVDOEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR2,0))) +#define TSB_LVD_SR_LVDNS (*((__I uint32_t *)BITBAND_PERI(&TSB_LVD->SR,0))) + + +/* TRGSEL */ +#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) +#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) +#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) +#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) +#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) +#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) +#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) +#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) +#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) +#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) +#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) +#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) +#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) +#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) +#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) +#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) +#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) +#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) +#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) +#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) +#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) +#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) +#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) +#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) +#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) +#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) +#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) +#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) +#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) +#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) +#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) +#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) +#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) +#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) +#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) +#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) +#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) +#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) +#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) +#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) +#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) +#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) +#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) +#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) +#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) +#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) +#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) +#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) +#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) +#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) +#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) +#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) +#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) +#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) +#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) +#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) +#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) +#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) +#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) +#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) +#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) +#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) +#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) +#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) +#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) +#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) +#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) +#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) +#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) +#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) +#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) +#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) +#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) +#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) +#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) +#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) +#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) +#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) +#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) +#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) +#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) +#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) +#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) +#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) +#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) +#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) +#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) +#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) +#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) +#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) +#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) +#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) +#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) +#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) +#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) +#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) +#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) +#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) +#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) +#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) +#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) +#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) +#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) +#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) +#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) +#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) +#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) +#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) +#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) +#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) +#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) +#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) +#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) +#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) +#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) +#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) +#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) +#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) +#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) +#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) +#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) +#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) +#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) +#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) +#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) +#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) +#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) +#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) +#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) +#define TSB_TSEL0_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,24))) +#define TSB_TSEL0_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,25))) +#define TSB_TSEL0_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,26))) +#define TSB_TSEL0_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,0))) +#define TSB_TSEL0_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,1))) +#define TSB_TSEL0_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,2))) +#define TSB_TSEL0_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,8))) +#define TSB_TSEL0_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,9))) +#define TSB_TSEL0_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,10))) +#define TSB_TSEL0_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,16))) +#define TSB_TSEL0_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,17))) +#define TSB_TSEL0_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,18))) +#define TSB_TSEL0_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,24))) +#define TSB_TSEL0_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,25))) +#define TSB_TSEL0_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,26))) +#define TSB_TSEL0_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,0))) +#define TSB_TSEL0_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,1))) +#define TSB_TSEL0_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,2))) +#define TSB_TSEL0_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,8))) +#define TSB_TSEL0_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,9))) +#define TSB_TSEL0_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,10))) +#define TSB_TSEL0_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,16))) +#define TSB_TSEL0_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,17))) +#define TSB_TSEL0_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,18))) +#define TSB_TSEL0_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,24))) +#define TSB_TSEL0_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,25))) +#define TSB_TSEL0_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,26))) +#define TSB_TSEL0_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,0))) +#define TSB_TSEL0_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,1))) +#define TSB_TSEL0_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,2))) +#define TSB_TSEL0_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,8))) +#define TSB_TSEL0_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,9))) +#define TSB_TSEL0_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,10))) +#define TSB_TSEL0_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,16))) +#define TSB_TSEL0_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,17))) +#define TSB_TSEL0_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,18))) +#define TSB_TSEL0_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,24))) +#define TSB_TSEL0_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,25))) +#define TSB_TSEL0_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,26))) +#define TSB_TSEL0_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,0))) +#define TSB_TSEL0_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,1))) +#define TSB_TSEL0_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,2))) + + + +/* Serial Interface (TSPI) */ +#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) +#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) +#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) +#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) +#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) +#define TSB_TSPI0_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,16))) +#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) +#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) +#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) +#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) +#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) +#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) +#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) +#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) +#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) +#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) +#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) +#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) +#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) +#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) +#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) +#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) +#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) +#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) +#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) +#define TSB_TSPI0_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SECTCR0,0))) +#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) +#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) +#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) +#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) +#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) +#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) +#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) +#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) +#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) +#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) +#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) +#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) +#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) + +#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) +#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) +#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) +#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) +#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) +#define TSB_TSPI1_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,16))) +#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) +#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) +#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) +#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) +#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) +#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) +#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) +#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) +#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) +#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) +#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) +#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) +#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) +#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) +#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) +#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) +#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) +#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) +#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) +#define TSB_TSPI1_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SECTCR0,0))) +#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) +#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) +#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) +#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) +#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) +#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) +#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) +#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) +#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) +#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) +#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) +#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) +#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) + +#define TSB_TSPI2_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR0,0))) +#define TSB_TSPI2_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,12))) +#define TSB_TSPI2_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,13))) +#define TSB_TSPI2_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,14))) +#define TSB_TSPI2_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,15))) +#define TSB_TSPI2_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,16))) +#define TSB_TSPI2_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,0))) +#define TSB_TSPI2_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,1))) +#define TSB_TSPI2_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,2))) +#define TSB_TSPI2_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,4))) +#define TSB_TSPI2_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,5))) +#define TSB_TSPI2_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,6))) +#define TSB_TSPI2_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,7))) +#define TSB_TSPI2_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,21))) +#define TSB_TSPI2_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,0))) +#define TSB_TSPI2_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,1))) +#define TSB_TSPI2_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,14))) +#define TSB_TSPI2_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,15))) +#define TSB_TSPI2_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,16))) +#define TSB_TSPI2_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,17))) +#define TSB_TSPI2_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,18))) +#define TSB_TSPI2_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,19))) +#define TSB_TSPI2_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,31))) +#define TSB_TSPI2_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,0))) +#define TSB_TSPI2_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,1))) +#define TSB_TSPI2_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SECTCR0,0))) +#define TSB_TSPI2_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,4))) +#define TSB_TSPI2_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,5))) +#define TSB_TSPI2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,6))) +#define TSB_TSPI2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,7))) +#define TSB_TSPI2_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,20))) +#define TSB_TSPI2_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,21))) +#define TSB_TSPI2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,22))) +#define TSB_TSPI2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,23))) +#define TSB_TSPI2_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,31))) +#define TSB_TSPI2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,0))) +#define TSB_TSPI2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,1))) +#define TSB_TSPI2_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,2))) +#define TSB_TSPI2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,3))) + +#define TSB_TSPI3_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR0,0))) +#define TSB_TSPI3_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,12))) +#define TSB_TSPI3_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,13))) +#define TSB_TSPI3_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,14))) +#define TSB_TSPI3_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,15))) +#define TSB_TSPI3_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,16))) +#define TSB_TSPI3_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,0))) +#define TSB_TSPI3_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,1))) +#define TSB_TSPI3_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,2))) +#define TSB_TSPI3_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,4))) +#define TSB_TSPI3_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,5))) +#define TSB_TSPI3_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,6))) +#define TSB_TSPI3_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,7))) +#define TSB_TSPI3_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,21))) +#define TSB_TSPI3_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,0))) +#define TSB_TSPI3_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,1))) +#define TSB_TSPI3_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,14))) +#define TSB_TSPI3_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,15))) +#define TSB_TSPI3_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,16))) +#define TSB_TSPI3_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,17))) +#define TSB_TSPI3_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,18))) +#define TSB_TSPI3_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,19))) +#define TSB_TSPI3_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,31))) +#define TSB_TSPI3_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,0))) +#define TSB_TSPI3_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,1))) +#define TSB_TSPI3_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SECTCR0,0))) +#define TSB_TSPI3_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,4))) +#define TSB_TSPI3_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,5))) +#define TSB_TSPI3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,6))) +#define TSB_TSPI3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,7))) +#define TSB_TSPI3_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,20))) +#define TSB_TSPI3_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,21))) +#define TSB_TSPI3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,22))) +#define TSB_TSPI3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,23))) +#define TSB_TSPI3_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,31))) +#define TSB_TSPI3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,0))) +#define TSB_TSPI3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,1))) +#define TSB_TSPI3_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,2))) +#define TSB_TSPI3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,3))) + +#define TSB_TSPI4_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR0,0))) +#define TSB_TSPI4_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,12))) +#define TSB_TSPI4_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,13))) +#define TSB_TSPI4_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,14))) +#define TSB_TSPI4_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,15))) +#define TSB_TSPI4_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,16))) +#define TSB_TSPI4_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,0))) +#define TSB_TSPI4_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,1))) +#define TSB_TSPI4_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,2))) +#define TSB_TSPI4_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,4))) +#define TSB_TSPI4_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,5))) +#define TSB_TSPI4_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,6))) +#define TSB_TSPI4_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,7))) +#define TSB_TSPI4_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,21))) +#define TSB_TSPI4_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,0))) +#define TSB_TSPI4_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,1))) +#define TSB_TSPI4_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,14))) +#define TSB_TSPI4_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,15))) +#define TSB_TSPI4_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,16))) +#define TSB_TSPI4_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,17))) +#define TSB_TSPI4_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,18))) +#define TSB_TSPI4_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,19))) +#define TSB_TSPI4_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,31))) +#define TSB_TSPI4_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,0))) +#define TSB_TSPI4_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,1))) +#define TSB_TSPI4_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SECTCR0,0))) +#define TSB_TSPI4_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,4))) +#define TSB_TSPI4_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,5))) +#define TSB_TSPI4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,6))) +#define TSB_TSPI4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,7))) +#define TSB_TSPI4_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,20))) +#define TSB_TSPI4_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,21))) +#define TSB_TSPI4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,22))) +#define TSB_TSPI4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,23))) +#define TSB_TSPI4_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,31))) +#define TSB_TSPI4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,0))) +#define TSB_TSPI4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,1))) +#define TSB_TSPI4_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,2))) +#define TSB_TSPI4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,3))) + +#define TSB_TSPI5_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR0,0))) +#define TSB_TSPI5_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,12))) +#define TSB_TSPI5_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,13))) +#define TSB_TSPI5_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,14))) +#define TSB_TSPI5_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,15))) +#define TSB_TSPI5_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,16))) +#define TSB_TSPI5_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,0))) +#define TSB_TSPI5_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,1))) +#define TSB_TSPI5_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,2))) +#define TSB_TSPI5_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,4))) +#define TSB_TSPI5_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,5))) +#define TSB_TSPI5_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,6))) +#define TSB_TSPI5_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,7))) +#define TSB_TSPI5_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,21))) +#define TSB_TSPI5_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,0))) +#define TSB_TSPI5_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,1))) +#define TSB_TSPI5_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,14))) +#define TSB_TSPI5_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,15))) +#define TSB_TSPI5_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,16))) +#define TSB_TSPI5_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,17))) +#define TSB_TSPI5_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,18))) +#define TSB_TSPI5_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,19))) +#define TSB_TSPI5_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,31))) +#define TSB_TSPI5_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,0))) +#define TSB_TSPI5_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,1))) +#define TSB_TSPI5_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SECTCR0,0))) +#define TSB_TSPI5_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,4))) +#define TSB_TSPI5_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,5))) +#define TSB_TSPI5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,6))) +#define TSB_TSPI5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,7))) +#define TSB_TSPI5_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,20))) +#define TSB_TSPI5_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,21))) +#define TSB_TSPI5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,22))) +#define TSB_TSPI5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,23))) +#define TSB_TSPI5_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,31))) +#define TSB_TSPI5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,0))) +#define TSB_TSPI5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,1))) +#define TSB_TSPI5_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,2))) +#define TSB_TSPI5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,3))) + +#define TSB_TSPI6_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR0,0))) +#define TSB_TSPI6_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,12))) +#define TSB_TSPI6_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,13))) +#define TSB_TSPI6_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,14))) +#define TSB_TSPI6_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,15))) +#define TSB_TSPI6_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,16))) +#define TSB_TSPI6_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,0))) +#define TSB_TSPI6_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,1))) +#define TSB_TSPI6_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,2))) +#define TSB_TSPI6_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,4))) +#define TSB_TSPI6_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,5))) +#define TSB_TSPI6_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,6))) +#define TSB_TSPI6_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,7))) +#define TSB_TSPI6_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,21))) +#define TSB_TSPI6_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,0))) +#define TSB_TSPI6_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,1))) +#define TSB_TSPI6_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,14))) +#define TSB_TSPI6_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,15))) +#define TSB_TSPI6_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,16))) +#define TSB_TSPI6_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,17))) +#define TSB_TSPI6_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,18))) +#define TSB_TSPI6_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,19))) +#define TSB_TSPI6_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,31))) +#define TSB_TSPI6_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,0))) +#define TSB_TSPI6_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,1))) +#define TSB_TSPI6_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SECTCR0,0))) +#define TSB_TSPI6_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,4))) +#define TSB_TSPI6_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,5))) +#define TSB_TSPI6_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,6))) +#define TSB_TSPI6_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,7))) +#define TSB_TSPI6_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,20))) +#define TSB_TSPI6_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,21))) +#define TSB_TSPI6_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,22))) +#define TSB_TSPI6_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,23))) +#define TSB_TSPI6_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,31))) +#define TSB_TSPI6_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,0))) +#define TSB_TSPI6_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,1))) +#define TSB_TSPI6_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,2))) +#define TSB_TSPI6_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,3))) + +#define TSB_TSPI7_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR0,0))) +#define TSB_TSPI7_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,12))) +#define TSB_TSPI7_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,13))) +#define TSB_TSPI7_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,14))) +#define TSB_TSPI7_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,15))) +#define TSB_TSPI7_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,16))) +#define TSB_TSPI7_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,0))) +#define TSB_TSPI7_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,1))) +#define TSB_TSPI7_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,2))) +#define TSB_TSPI7_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,4))) +#define TSB_TSPI7_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,5))) +#define TSB_TSPI7_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,6))) +#define TSB_TSPI7_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,7))) +#define TSB_TSPI7_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,21))) +#define TSB_TSPI7_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,0))) +#define TSB_TSPI7_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,1))) +#define TSB_TSPI7_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,14))) +#define TSB_TSPI7_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,15))) +#define TSB_TSPI7_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,16))) +#define TSB_TSPI7_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,17))) +#define TSB_TSPI7_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,18))) +#define TSB_TSPI7_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,19))) +#define TSB_TSPI7_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,31))) +#define TSB_TSPI7_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,0))) +#define TSB_TSPI7_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,1))) +#define TSB_TSPI7_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SECTCR0,0))) +#define TSB_TSPI7_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,4))) +#define TSB_TSPI7_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,5))) +#define TSB_TSPI7_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,6))) +#define TSB_TSPI7_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,7))) +#define TSB_TSPI7_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,20))) +#define TSB_TSPI7_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,21))) +#define TSB_TSPI7_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,22))) +#define TSB_TSPI7_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,23))) +#define TSB_TSPI7_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,31))) +#define TSB_TSPI7_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,0))) +#define TSB_TSPI7_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,1))) +#define TSB_TSPI7_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,2))) +#define TSB_TSPI7_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,3))) + +#define TSB_TSPI8_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR0,0))) +#define TSB_TSPI8_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,12))) +#define TSB_TSPI8_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,13))) +#define TSB_TSPI8_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,14))) +#define TSB_TSPI8_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,15))) +#define TSB_TSPI8_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,16))) +#define TSB_TSPI8_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,0))) +#define TSB_TSPI8_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,1))) +#define TSB_TSPI8_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,2))) +#define TSB_TSPI8_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,4))) +#define TSB_TSPI8_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,5))) +#define TSB_TSPI8_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,6))) +#define TSB_TSPI8_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,7))) +#define TSB_TSPI8_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,21))) +#define TSB_TSPI8_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,0))) +#define TSB_TSPI8_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,1))) +#define TSB_TSPI8_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,14))) +#define TSB_TSPI8_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,15))) +#define TSB_TSPI8_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,16))) +#define TSB_TSPI8_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,17))) +#define TSB_TSPI8_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,18))) +#define TSB_TSPI8_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,19))) +#define TSB_TSPI8_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,31))) +#define TSB_TSPI8_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,0))) +#define TSB_TSPI8_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,1))) +#define TSB_TSPI8_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SECTCR0,0))) +#define TSB_TSPI8_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,4))) +#define TSB_TSPI8_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,5))) +#define TSB_TSPI8_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,6))) +#define TSB_TSPI8_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,7))) +#define TSB_TSPI8_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,20))) +#define TSB_TSPI8_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,21))) +#define TSB_TSPI8_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,22))) +#define TSB_TSPI8_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,23))) +#define TSB_TSPI8_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,31))) +#define TSB_TSPI8_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,0))) +#define TSB_TSPI8_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,1))) +#define TSB_TSPI8_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,2))) +#define TSB_TSPI8_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,3))) + + +/* External Bus Interface(EXB) */ +#define TSB_EXB_MOD_EXBSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->MOD,0))) +#define TSB_EXB_CS0_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,0))) +#define TSB_EXB_CS0_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,12))) +#define TSB_EXB_CS0_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,13))) +#define TSB_EXB_CS1_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,0))) +#define TSB_EXB_CS1_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,12))) +#define TSB_EXB_CS1_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,13))) +#define TSB_EXB_CS2_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,0))) +#define TSB_EXB_CS2_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,12))) +#define TSB_EXB_CS2_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,13))) +#define TSB_EXB_CS3_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,0))) +#define TSB_EXB_CS3_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,12))) +#define TSB_EXB_CS3_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,13))) +#define TSB_EXB_CLKCTL_CLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CLKCTL,0))) + + +/* Clock Generator (CG) */ +#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) +#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) +#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) +#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) +#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) +#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) +#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) +#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) +#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) +#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) +#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) +#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) +#define TSB_CG_FSYSMENC_IPMENC00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,0))) +#define TSB_CG_FSYSMENC_IPMENC01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,1))) +#define TSB_CG_FSYSMENC_IPMENC02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,2))) +#define TSB_CG_FSYSMENC_IPMENC03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,3))) +#define TSB_CG_FSYSMENC_IPMENC04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,4))) +#define TSB_CG_FSYSMENC_IPMENC05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,5))) +#define TSB_CG_FSYSMENC_IPMENC06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,6))) +#define TSB_CG_FSYSMENC_IPMENC07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,7))) +#define TSB_CG_FSYSMENC_IPMENC08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,8))) +#define TSB_CG_FSYSMENC_IPMENC09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,9))) +#define TSB_CG_FSYSMENC_IPMENC15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,15))) +#define TSB_CG_FSYSMENC_IPMENC16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,16))) +#define TSB_CG_FSYSMENA_IPMENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,0))) +#define TSB_CG_FSYSMENA_IPMENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,1))) +#define TSB_CG_FSYSMENA_IPMENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,2))) +#define TSB_CG_FSYSMENA_IPMENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,3))) +#define TSB_CG_FSYSMENA_IPMENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,4))) +#define TSB_CG_FSYSMENA_IPMENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,5))) +#define TSB_CG_FSYSMENA_IPMENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,6))) +#define TSB_CG_FSYSMENA_IPMENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,7))) +#define TSB_CG_FSYSMENA_IPMENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,8))) +#define TSB_CG_FSYSMENA_IPMENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,9))) +#define TSB_CG_FSYSMENA_IPMENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,10))) +#define TSB_CG_FSYSMENA_IPMENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,11))) +#define TSB_CG_FSYSMENA_IPMENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,12))) +#define TSB_CG_FSYSMENA_IPMENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,13))) +#define TSB_CG_FSYSMENA_IPMENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,14))) +#define TSB_CG_FSYSMENA_IPMENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,15))) +#define TSB_CG_FSYSMENA_IPMENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,16))) +#define TSB_CG_FSYSMENA_IPMENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,17))) +#define TSB_CG_FSYSMENA_IPMENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,18))) +#define TSB_CG_FSYSMENA_IPMENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,19))) +#define TSB_CG_FSYSMENA_IPMENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,20))) +#define TSB_CG_FSYSMENA_IPMENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,21))) +#define TSB_CG_FSYSMENA_IPMENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,22))) +#define TSB_CG_FSYSMENA_IPMENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,23))) +#define TSB_CG_FSYSMENA_IPMENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,24))) +#define TSB_CG_FSYSMENA_IPMENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,25))) +#define TSB_CG_FSYSMENA_IPMENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,26))) +#define TSB_CG_FSYSMENA_IPMENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,27))) +#define TSB_CG_FSYSMENA_IPMENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,28))) +#define TSB_CG_FSYSMENA_IPMENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,29))) +#define TSB_CG_FSYSMENA_IPMENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,30))) +#define TSB_CG_FSYSMENA_IPMENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,31))) +#define TSB_CG_FSYSMENB_IPMENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,0))) +#define TSB_CG_FSYSMENB_IPMENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,1))) +#define TSB_CG_FSYSMENB_IPMENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,2))) +#define TSB_CG_FSYSMENB_IPMENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,3))) +#define TSB_CG_FSYSMENB_IPMENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,4))) +#define TSB_CG_FSYSMENB_IPMENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,5))) +#define TSB_CG_FSYSMENB_IPMENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,6))) +#define TSB_CG_FSYSMENB_IPMENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,7))) +#define TSB_CG_FSYSMENB_IPMENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,8))) +#define TSB_CG_FSYSMENB_IPMENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,9))) +#define TSB_CG_FSYSMENB_IPMENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,10))) +#define TSB_CG_FSYSMENB_IPMENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,11))) +#define TSB_CG_FSYSMENB_IPMENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,12))) +#define TSB_CG_FSYSMENB_IPMENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,13))) +#define TSB_CG_FSYSMENB_IPMENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,14))) +#define TSB_CG_FSYSMENB_IPMENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,15))) +#define TSB_CG_FSYSMENB_IPMENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,16))) +#define TSB_CG_FSYSMENB_IPMENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,17))) +#define TSB_CG_FSYSMENB_IPMENB18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,18))) +#define TSB_CG_FSYSMENB_IPMENB19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,19))) +#define TSB_CG_FSYSMENB_IPMENB20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,20))) +#define TSB_CG_FSYSMENB_IPMENB21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,21))) +#define TSB_CG_FSYSMENB_IPMENB22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,22))) +#define TSB_CG_FSYSMENB_IPMENB23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,23))) +#define TSB_CG_FSYSMENB_IPMENB24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,24))) +#define TSB_CG_FSYSMENB_IPMENB28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,28))) +#define TSB_CG_FSYSMENB_IPMENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,29))) +#define TSB_CG_FSYSMENB_IPMENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,30))) +#define TSB_CG_FSYSMENB_IPMENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,31))) +#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) +#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) +#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) +#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) +#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) +#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) +#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) +#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) +#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) +#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) +#define TSB_CG_FCEN_FCIPEN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,23))) +#define TSB_CG_FCEN_FCIPEN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,26))) +#define TSB_CG_FCEN_FCIPEN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,27))) +#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) +#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) +#define TSB_CG_EXTEND2_RSV20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,0))) +#define TSB_CG_EXTEND2_RSV21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,1))) +#define TSB_CG_EXTEND2_RSV22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,2))) + + + +/* Interrupt Monitor Register */ +#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) +#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) +#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) +#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) +#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) +#define TSB_IMN_FLG1_INT035FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,3))) +#define TSB_IMN_FLG1_INT036FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,4))) +#define TSB_IMN_FLG1_INT037FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,5))) +#define TSB_IMN_FLG1_INT038FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,6))) +#define TSB_IMN_FLG1_INT039FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,7))) +#define TSB_IMN_FLG1_INT040FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,8))) +#define TSB_IMN_FLG1_INT041FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,9))) +#define TSB_IMN_FLG1_INT042FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,10))) +#define TSB_IMN_FLG1_INT043FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,11))) +#define TSB_IMN_FLG1_INT044FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,12))) +#define TSB_IMN_FLG1_INT045FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,13))) +#define TSB_IMN_FLG1_INT046FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,14))) +#define TSB_IMN_FLG1_INT047FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,15))) +#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) +#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) +#define TSB_IMN_FLG1_INT050FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,18))) +#define TSB_IMN_FLG1_INT051FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,19))) +#define TSB_IMN_FLG1_INT052FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,20))) +#define TSB_IMN_FLG1_INT053FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,21))) +#define TSB_IMN_FLG1_INT054FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,22))) +#define TSB_IMN_FLG1_INT055FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,23))) +#define TSB_IMN_FLG1_INT056FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,24))) +#define TSB_IMN_FLG1_INT057FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,25))) +#define TSB_IMN_FLG1_INT058FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,26))) +#define TSB_IMN_FLG1_INT059FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,27))) +#define TSB_IMN_FLG1_INT060FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,28))) +#define TSB_IMN_FLG1_INT061FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,29))) +#define TSB_IMN_FLG1_INT062FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,30))) +#define TSB_IMN_FLG1_INT063FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,31))) +#define TSB_IMN_FLG2_INT081FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,17))) +#define TSB_IMN_FLG2_INT082FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,18))) +#define TSB_IMN_FLG2_INT083FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,19))) +#define TSB_IMN_FLG2_INT084FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,20))) +#define TSB_IMN_FLG2_INT085FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,21))) +#define TSB_IMN_FLG2_INT086FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,22))) +#define TSB_IMN_FLG2_INT087FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,23))) +#define TSB_IMN_FLG2_INT088FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,24))) +#define TSB_IMN_FLG2_INT089FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,25))) +#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) +#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) +#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) +#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) +#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) +#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) +#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) +#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) +#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) +#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) +#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) +#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) +#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) +#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) +#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) +#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) +#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) +#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) +#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) +#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) +#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) +#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) +#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) +#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) +#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) +#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) +#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) +#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) +#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) +#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) +#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) +#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) +#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) +#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) +#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) +#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) +#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) +#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) +#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) +#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) +#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) +#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) +#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) +#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) +#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) +#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) +#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) +#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) +#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) +#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) +#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) +#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) +#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) +#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) +#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) +#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) +#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) +#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) +#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) +#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) +#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) +#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) +#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) +#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) +#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) +#define TSB_IMN_FLG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,1))) +#define TSB_IMN_FLG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,2))) +#define TSB_IMN_FLG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,3))) +#define TSB_IMN_FLG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,4))) +#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) +#define TSB_IMN_FLG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,6))) +#define TSB_IMN_FLG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,7))) +#define TSB_IMN_FLG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,8))) +#define TSB_IMN_FLG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,9))) +#define TSB_IMN_FLG5_INT170FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,10))) +#define TSB_IMN_FLG5_INT171FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,11))) +#define TSB_IMN_FLG5_INT172FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,12))) +#define TSB_IMN_FLG5_INT173FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,13))) +#define TSB_IMN_FLG5_INT174FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,14))) +#define TSB_IMN_FLG5_INT175FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,15))) +#define TSB_IMN_FLG5_INT176FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,16))) +#define TSB_IMN_FLG5_INT177FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,17))) +#define TSB_IMN_FLG5_INT178FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,18))) +#define TSB_IMN_FLG5_INT179FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,19))) +#define TSB_IMN_FLG5_INT180FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,20))) +#define TSB_IMN_FLG5_INT181FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,21))) +#define TSB_IMN_FLG5_INT182FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,22))) +#define TSB_IMN_FLG5_INT183FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,23))) +#define TSB_IMN_FLG5_INT184FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,24))) +#define TSB_IMN_FLG5_INT185FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,25))) +#define TSB_IMN_FLG5_INT186FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,26))) +#define TSB_IMN_FLG5_INT187FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,27))) +#define TSB_IMN_FLG5_INT188FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,28))) +#define TSB_IMN_FLG5_INT189FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,29))) +#define TSB_IMN_FLG5_INT190FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,30))) +#define TSB_IMN_FLG5_INT191FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,31))) +#define TSB_IMN_FLG6_INT192FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,0))) +#define TSB_IMN_FLG6_INT193FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,1))) +#define TSB_IMN_FLG6_INT194FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,2))) +#define TSB_IMN_FLG6_INT195FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,3))) +#define TSB_IMN_FLG6_INT196FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,4))) +#define TSB_IMN_FLG6_INT197FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,5))) +#define TSB_IMN_FLG6_INT198FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,6))) +#define TSB_IMN_FLG6_INT199FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,7))) +#define TSB_IMN_FLG6_INT200FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,8))) +#define TSB_IMN_FLG6_INT201FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,9))) +#define TSB_IMN_FLG6_INT202FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,10))) +#define TSB_IMN_FLG6_INT203FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,11))) +#define TSB_IMN_FLG6_INT204FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,12))) +#define TSB_IMN_FLG6_INT205FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,13))) +#define TSB_IMN_FLG6_INT206FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,14))) +#define TSB_IMN_FLG6_INT207FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,15))) +#define TSB_IMN_FLG6_INT208FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,16))) +#define TSB_IMN_FLG6_INT209FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,17))) +#define TSB_IMN_FLG6_INT210FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,18))) +#define TSB_IMN_FLG6_INT211FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,19))) +#define TSB_IMN_FLG6_INT212FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,20))) +#define TSB_IMN_FLG6_INT213FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,21))) +#define TSB_IMN_FLG6_INT214FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,22))) +#define TSB_IMN_FLG6_INT215FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,23))) +#define TSB_IMN_FLG6_INT216FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,24))) +#define TSB_IMN_FLG6_INT217FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,25))) +#define TSB_IMN_FLG6_INT218FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,26))) +#define TSB_IMN_FLG6_INT219FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,27))) +#define TSB_IMN_FLG6_INT220FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,28))) +#define TSB_IMN_FLG6_INT221FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,29))) +#define TSB_IMN_FLG6_INT222FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,30))) +#define TSB_IMN_FLG6_INT223FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,31))) +#define TSB_IMN_FLG7_INT224FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,0))) +#define TSB_IMN_FLG7_INT225FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,1))) +#define TSB_IMN_FLG7_INT226FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,2))) +#define TSB_IMN_FLG7_INT227FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,3))) +#define TSB_IMN_FLG7_INT228FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,4))) +#define TSB_IMN_FLG7_INT229FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,5))) +#define TSB_IMN_FLG7_INT230FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,6))) +#define TSB_IMN_FLG7_INT231FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,7))) +#define TSB_IMN_FLG7_INT232FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,8))) +#define TSB_IMN_FLG7_INT233FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,9))) +#define TSB_IMN_FLG7_INT234FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,10))) +#define TSB_IMN_FLG7_INT235FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,11))) +#define TSB_IMN_FLG7_INT236FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,12))) +#define TSB_IMN_FLG7_INT237FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,13))) +#define TSB_IMN_FLG7_INT241FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,17))) +#define TSB_IMN_FLG7_INT242FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,18))) +#define TSB_IMN_FLG7_INT243FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,19))) +#define TSB_IMN_FLG7_INT244FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,20))) +#define TSB_IMN_FLG7_INT245FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,21))) +#define TSB_IMN_FLG7_INT246FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,22))) +#define TSB_IMN_FLG7_INT247FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,23))) +#define TSB_IMN_FLG7_INT248FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,24))) +#define TSB_IMN_FLG7_INT249FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,25))) +#define TSB_IMN_FLG7_INT250FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,26))) +#define TSB_IMN_FLG7_INT251FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,27))) +#define TSB_IMN_FLG7_INT252FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,28))) +#define TSB_IMN_FLG7_INT253FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,29))) +#define TSB_IMN_FLG7_INT254FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,30))) +#define TSB_IMN_FLG7_INT255FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,31))) + + +/* DNF */ +#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) +#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) +#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) +#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) +#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) +#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) +#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) +#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) +#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) +#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) +#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) +#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) +#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) +#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) +#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) +#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) + +#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) +#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) +#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) +#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) +#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) +#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) +#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) +#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) +#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) +#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) +#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) +#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) +#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) +#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) +#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) +#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) + + +/* Watchdog Timer (SIWDT) */ +#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) +#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) +#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) +#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) + + +/* NBDIF */ +#define TSB_NBD_CR0_NBDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_NBD->CR0,0))) + + +/* Malti Porpose Direct Memory Accsess(MDMA) */ +#define TSB_MDMAA_XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,16))) +#define TSB_MDMAA_XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,24))) +#define TSB_MDMAA_DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->DSNUM,8))) +#define TSB_MDMAA_C00XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,16))) +#define TSB_MDMAA_C00XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,24))) +#define TSB_MDMAA_C00DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00DSNUM,8))) +#define TSB_MDMAA_C01XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,16))) +#define TSB_MDMAA_C01XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,24))) +#define TSB_MDMAA_C01DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01DSNUM,8))) +#define TSB_MDMAA_C02XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,16))) +#define TSB_MDMAA_C02XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,24))) +#define TSB_MDMAA_C02DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02DSNUM,8))) +#define TSB_MDMAA_C03XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,16))) +#define TSB_MDMAA_C03XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,24))) +#define TSB_MDMAA_C03DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03DSNUM,8))) +#define TSB_MDMAA_C04XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,16))) +#define TSB_MDMAA_C04XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,24))) +#define TSB_MDMAA_C04DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04DSNUM,8))) +#define TSB_MDMAA_C05XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,16))) +#define TSB_MDMAA_C05XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,24))) +#define TSB_MDMAA_C05DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05DSNUM,8))) +#define TSB_MDMAA_C06XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,16))) +#define TSB_MDMAA_C06XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,24))) +#define TSB_MDMAA_C06DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06DSNUM,8))) +#define TSB_MDMAA_C07XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,16))) +#define TSB_MDMAA_C07XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,24))) +#define TSB_MDMAA_C07DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07DSNUM,8))) +#define TSB_MDMAA_C08XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,16))) +#define TSB_MDMAA_C08XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,24))) +#define TSB_MDMAA_C08DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08DSNUM,8))) +#define TSB_MDMAA_C09XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,16))) +#define TSB_MDMAA_C09XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,24))) +#define TSB_MDMAA_C09DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09DSNUM,8))) +#define TSB_MDMAA_C10XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,16))) +#define TSB_MDMAA_C10XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,24))) +#define TSB_MDMAA_C10DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10DSNUM,8))) +#define TSB_MDMAA_C11XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,16))) +#define TSB_MDMAA_C11XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,24))) +#define TSB_MDMAA_C11DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11DSNUM,8))) +#define TSB_MDMAA_C12XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,16))) +#define TSB_MDMAA_C12XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,24))) +#define TSB_MDMAA_C12DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12DSNUM,8))) +#define TSB_MDMAA_C13XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,16))) +#define TSB_MDMAA_C13XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,24))) +#define TSB_MDMAA_C13DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13DSNUM,8))) +#define TSB_MDMAA_C14XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,16))) +#define TSB_MDMAA_C14XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,24))) +#define TSB_MDMAA_C14DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14DSNUM,8))) +#define TSB_MDMAA_C15XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,16))) +#define TSB_MDMAA_C15XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,24))) +#define TSB_MDMAA_C15DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15DSNUM,8))) +#define TSB_MDMAA_C16XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,16))) +#define TSB_MDMAA_C16XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,24))) +#define TSB_MDMAA_C16DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16DSNUM,8))) +#define TSB_MDMAA_C17XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,16))) +#define TSB_MDMAA_C17XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,24))) +#define TSB_MDMAA_C17DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17DSNUM,8))) +#define TSB_MDMAA_C18XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,16))) +#define TSB_MDMAA_C18XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,24))) +#define TSB_MDMAA_C18DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18DSNUM,8))) +#define TSB_MDMAA_C19XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,16))) +#define TSB_MDMAA_C19XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,24))) +#define TSB_MDMAA_C19DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19DSNUM,8))) +#define TSB_MDMAA_C20XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,16))) +#define TSB_MDMAA_C20XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,24))) +#define TSB_MDMAA_C20DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20DSNUM,8))) +#define TSB_MDMAA_C21XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,16))) +#define TSB_MDMAA_C21XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,24))) +#define TSB_MDMAA_C21DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21DSNUM,8))) +#define TSB_MDMAA_C22XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,16))) +#define TSB_MDMAA_C22XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,24))) +#define TSB_MDMAA_C22DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22DSNUM,8))) +#define TSB_MDMAA_C23XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,16))) +#define TSB_MDMAA_C23XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,24))) +#define TSB_MDMAA_C23DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23DSNUM,8))) +#define TSB_MDMAA_C24XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,16))) +#define TSB_MDMAA_C24XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,24))) +#define TSB_MDMAA_C24DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24DSNUM,8))) +#define TSB_MDMAA_C25XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,16))) +#define TSB_MDMAA_C25XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,24))) +#define TSB_MDMAA_C25DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25DSNUM,8))) +#define TSB_MDMAA_C26XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,16))) +#define TSB_MDMAA_C26XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,24))) +#define TSB_MDMAA_C26DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26DSNUM,8))) +#define TSB_MDMAA_C27XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,16))) +#define TSB_MDMAA_C27XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,24))) +#define TSB_MDMAA_C27DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27DSNUM,8))) +#define TSB_MDMAA_C28XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,16))) +#define TSB_MDMAA_C28XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,24))) +#define TSB_MDMAA_C28DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28DSNUM,8))) +#define TSB_MDMAA_C29XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,16))) +#define TSB_MDMAA_C29XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,24))) +#define TSB_MDMAA_C29DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29DSNUM,8))) +#define TSB_MDMAA_C30XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,16))) +#define TSB_MDMAA_C30XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,24))) +#define TSB_MDMAA_C30DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30DSNUM,8))) +#define TSB_MDMAA_C31XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,16))) +#define TSB_MDMAA_C31XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,24))) +#define TSB_MDMAA_C31DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31DSNUM,8))) +#define TSB_MDMAA_MSK_MSK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,0))) +#define TSB_MDMAA_MSK_MSK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,1))) +#define TSB_MDMAA_MSK_MSK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,2))) +#define TSB_MDMAA_MSK_MSK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,3))) +#define TSB_MDMAA_MSK_MSK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,4))) +#define TSB_MDMAA_MSK_MSK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,5))) +#define TSB_MDMAA_MSK_MSK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,6))) +#define TSB_MDMAA_MSK_MSK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,7))) +#define TSB_MDMAA_MSK_MSK8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,8))) +#define TSB_MDMAA_MSK_MSK9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,9))) +#define TSB_MDMAA_MSK_MSK10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,10))) +#define TSB_MDMAA_MSK_MSK11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,11))) +#define TSB_MDMAA_MSK_MSK12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,12))) +#define TSB_MDMAA_MSK_MSK13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,13))) +#define TSB_MDMAA_MSK_MSK14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,14))) +#define TSB_MDMAA_MSK_MSK15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,15))) +#define TSB_MDMAA_MSK_MSK16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,16))) +#define TSB_MDMAA_MSK_MSK17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,17))) +#define TSB_MDMAA_MSK_MSK18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,18))) +#define TSB_MDMAA_MSK_MSK19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,19))) +#define TSB_MDMAA_MSK_MSK20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,20))) +#define TSB_MDMAA_MSK_MSK21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,21))) +#define TSB_MDMAA_MSK_MSK22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,22))) +#define TSB_MDMAA_MSK_MSK23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,23))) +#define TSB_MDMAA_MSK_MSK24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,24))) +#define TSB_MDMAA_MSK_MSK25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,25))) +#define TSB_MDMAA_MSK_MSK26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,26))) +#define TSB_MDMAA_MSK_MSK27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,27))) +#define TSB_MDMAA_MSK_MSK28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,28))) +#define TSB_MDMAA_MSK_MSK29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,29))) +#define TSB_MDMAA_MSK_MSK30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,30))) +#define TSB_MDMAA_MSK_MSK31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,31))) + + +/* ARM Prime Cell PL011 */ +#define TSB_FURT0_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,8))) +#define TSB_FURT0_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,9))) +#define TSB_FURT0_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,10))) +#define TSB_FURT0_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,11))) +#define TSB_FURT0_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,0))) +#define TSB_FURT0_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,1))) +#define TSB_FURT0_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,2))) +#define TSB_FURT0_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,3))) +#define TSB_FURT0_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,0))) +#define TSB_FURT0_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,3))) +#define TSB_FURT0_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,4))) +#define TSB_FURT0_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,5))) +#define TSB_FURT0_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,6))) +#define TSB_FURT0_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,7))) +#define TSB_FURT0_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,0))) +#define TSB_FURT0_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,1))) +#define TSB_FURT0_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,2))) +#define TSB_FURT0_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,3))) +#define TSB_FURT0_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,4))) +#define TSB_FURT0_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,7))) +#define TSB_FURT0_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,0))) +#define TSB_FURT0_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,1))) +#define TSB_FURT0_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,2))) +#define TSB_FURT0_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,8))) +#define TSB_FURT0_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,9))) +#define TSB_FURT0_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,14))) +#define TSB_FURT0_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,15))) +#define TSB_FURT0_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,4))) +#define TSB_FURT0_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,5))) +#define TSB_FURT0_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,6))) +#define TSB_FURT0_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,7))) +#define TSB_FURT0_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,8))) +#define TSB_FURT0_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,9))) +#define TSB_FURT0_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,10))) +#define TSB_FURT0_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,4))) +#define TSB_FURT0_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,5))) +#define TSB_FURT0_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,6))) +#define TSB_FURT0_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,7))) +#define TSB_FURT0_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,8))) +#define TSB_FURT0_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,9))) +#define TSB_FURT0_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,10))) +#define TSB_FURT0_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,4))) +#define TSB_FURT0_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,5))) +#define TSB_FURT0_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,6))) +#define TSB_FURT0_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,7))) +#define TSB_FURT0_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,8))) +#define TSB_FURT0_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,9))) +#define TSB_FURT0_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,10))) +#define TSB_FURT0_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,4))) +#define TSB_FURT0_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,5))) +#define TSB_FURT0_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,6))) +#define TSB_FURT0_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,7))) +#define TSB_FURT0_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,8))) +#define TSB_FURT0_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,9))) +#define TSB_FURT0_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,10))) +#define TSB_FURT0_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,0))) +#define TSB_FURT0_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,1))) +#define TSB_FURT0_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,2))) + +#define TSB_FURT1_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,8))) +#define TSB_FURT1_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,9))) +#define TSB_FURT1_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,10))) +#define TSB_FURT1_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,11))) +#define TSB_FURT1_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,0))) +#define TSB_FURT1_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,1))) +#define TSB_FURT1_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,2))) +#define TSB_FURT1_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,3))) +#define TSB_FURT1_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,0))) +#define TSB_FURT1_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,3))) +#define TSB_FURT1_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,4))) +#define TSB_FURT1_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,5))) +#define TSB_FURT1_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,6))) +#define TSB_FURT1_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,7))) +#define TSB_FURT1_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,0))) +#define TSB_FURT1_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,1))) +#define TSB_FURT1_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,2))) +#define TSB_FURT1_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,3))) +#define TSB_FURT1_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,4))) +#define TSB_FURT1_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,7))) +#define TSB_FURT1_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,0))) +#define TSB_FURT1_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,1))) +#define TSB_FURT1_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,2))) +#define TSB_FURT1_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,8))) +#define TSB_FURT1_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,9))) +#define TSB_FURT1_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,14))) +#define TSB_FURT1_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,15))) +#define TSB_FURT1_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,4))) +#define TSB_FURT1_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,5))) +#define TSB_FURT1_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,6))) +#define TSB_FURT1_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,7))) +#define TSB_FURT1_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,8))) +#define TSB_FURT1_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,9))) +#define TSB_FURT1_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,10))) +#define TSB_FURT1_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,4))) +#define TSB_FURT1_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,5))) +#define TSB_FURT1_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,6))) +#define TSB_FURT1_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,7))) +#define TSB_FURT1_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,8))) +#define TSB_FURT1_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,9))) +#define TSB_FURT1_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,10))) +#define TSB_FURT1_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,4))) +#define TSB_FURT1_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,5))) +#define TSB_FURT1_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,6))) +#define TSB_FURT1_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,7))) +#define TSB_FURT1_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,8))) +#define TSB_FURT1_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,9))) +#define TSB_FURT1_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,10))) +#define TSB_FURT1_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,4))) +#define TSB_FURT1_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,5))) +#define TSB_FURT1_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,6))) +#define TSB_FURT1_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,7))) +#define TSB_FURT1_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,8))) +#define TSB_FURT1_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,9))) +#define TSB_FURT1_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,10))) +#define TSB_FURT1_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,0))) +#define TSB_FURT1_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,1))) +#define TSB_FURT1_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,2))) + + +/* ADC */ +#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) +#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) +#define TSB_ADA_CR0_HPSGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,2))) +#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) +#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) +#define TSB_ADA_CR1_HPTRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,1))) +#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) +#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) +#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) +#define TSB_ADA_CR1_HPDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,7))) +#define TSB_ADA_ST_HPF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) +#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) +#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) +#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) +#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) +#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) +#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) +#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) +#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) +#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) +#define TSB_ADA_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) +#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) +#define TSB_ADA_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) +#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) +#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) +#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) +#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) +#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) +#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) +#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) +#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) +#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) +#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) +#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) +#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) +#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) +#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) +#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) +#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) +#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) +#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) +#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) +#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) +#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) +#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) +#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) +#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) +#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) +#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) +#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) +#define TSB_ADA_REG0_ADOVRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) +#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) +#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) +#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) +#define TSB_ADA_REG1_ADOVRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) +#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) +#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) +#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) +#define TSB_ADA_REG2_ADOVRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) +#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) +#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) +#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) +#define TSB_ADA_REG3_ADOVRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) +#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) +#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) +#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) +#define TSB_ADA_REG4_ADOVRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) +#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) +#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) +#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) +#define TSB_ADA_REG5_ADOVRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) +#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) +#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) +#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) +#define TSB_ADA_REG6_ADOVRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) +#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) +#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) +#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) +#define TSB_ADA_REG7_ADOVRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) +#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) +#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) +#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) +#define TSB_ADA_REG8_ADOVRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) +#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) +#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) +#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) +#define TSB_ADA_REG9_ADOVRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) +#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) +#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) +#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) +#define TSB_ADA_REG10_ADOVRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) +#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) +#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) +#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) +#define TSB_ADA_REG11_ADOVRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) +#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) +#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) +#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) +#define TSB_ADA_REG12_ADOVRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) +#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) +#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) +#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) +#define TSB_ADA_REG13_ADOVRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) +#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) +#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) +#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) +#define TSB_ADA_REG14_ADOVRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) +#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) +#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) +#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) +#define TSB_ADA_REG15_ADOVRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) +#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) +#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) +#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) +#define TSB_ADA_REG16_ADOVRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) +#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) +#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) +#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) +#define TSB_ADA_REG17_ADOVRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) +#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) +#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) +#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) +#define TSB_ADA_REG18_ADOVRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) +#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) +#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) +#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) +#define TSB_ADA_REG19_ADOVRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) +#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) +#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) +#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) +#define TSB_ADA_REG20_ADOVRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) +#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) +#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) +#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) +#define TSB_ADA_REG21_ADOVRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) +#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) +#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) +#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) +#define TSB_ADA_REG22_ADOVRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) +#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) +#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) +#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) +#define TSB_ADA_REG23_ADOVRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) + + +/* Digital analog converter (DAC) */ +#define TSB_DA0_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CR,0))) + +#define TSB_DA1_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CR,0))) + + +/* 16-bit Timer/Event Counter (TB) */ +#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) +#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) +#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) +#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) +#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) +#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) +#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) +#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) +#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) +#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) +#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) +#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) +#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) +#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) +#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) +#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) +#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) +#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) +#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) +#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) +#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) +#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) +#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) +#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) +#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) +#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) +#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) +#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) +#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) +#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) +#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) +#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) +#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) +#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) +#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) +#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) +#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) +#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) +#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) +#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) +#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) +#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) +#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) +#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) +#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) +#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) +#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) +#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) +#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) +#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) +#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) +#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) +#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) +#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) + +#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) +#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) +#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) +#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) +#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) +#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) +#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) +#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) +#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) +#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) +#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) +#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) +#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) +#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) +#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) +#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) +#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) +#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) +#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) +#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) +#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) +#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) +#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) +#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) +#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) +#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) +#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) +#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) +#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) +#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) +#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) +#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) +#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) +#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) +#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) +#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) +#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) +#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) +#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) +#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) +#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) +#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) +#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) +#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) +#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) +#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) +#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) +#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) +#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) +#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) +#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) +#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) +#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) +#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) + +#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) +#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) +#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) +#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) +#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) +#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) +#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) +#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) +#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) +#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) +#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) +#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) +#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) +#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) +#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) +#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) +#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) +#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) +#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) +#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) +#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) +#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) +#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) +#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) +#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) +#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) +#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) +#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) +#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) +#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) +#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) +#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) +#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) +#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) +#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) +#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) +#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) +#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) +#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) +#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) +#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) +#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) +#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) +#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) +#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) +#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) +#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) +#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) +#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) +#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) +#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) +#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) +#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) +#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) + +#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) +#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) +#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) +#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) +#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) +#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) +#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) +#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) +#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) +#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) +#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) +#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) +#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) +#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) +#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) +#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) +#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) +#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) +#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) +#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) +#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) +#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) +#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) +#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) +#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) +#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) +#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) +#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) +#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) +#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) +#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) +#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) +#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) +#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) +#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) +#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) +#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) +#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) +#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) +#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) +#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) +#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) +#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) +#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) +#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) +#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) +#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) +#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) +#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) +#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) +#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) +#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) +#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) +#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) + +#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) +#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) +#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) +#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) +#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) +#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) +#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) +#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) +#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) +#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) +#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) +#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) +#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) +#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) +#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) +#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) +#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) +#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) +#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) +#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) +#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) +#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) +#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) +#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) +#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) +#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) +#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) +#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) +#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) +#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) +#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) +#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) +#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) +#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) +#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) +#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) +#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) +#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) +#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) +#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) +#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) +#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) +#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) +#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) +#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) +#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) +#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) +#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) +#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) +#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) +#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) +#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) +#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) +#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) + +#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) +#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) +#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) +#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) +#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) +#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) +#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) +#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) +#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) +#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) +#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) +#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) +#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) +#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) +#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) +#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) +#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) +#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) +#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) +#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) +#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) +#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) +#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) +#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) +#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) +#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) +#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) +#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) +#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) +#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) +#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) +#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) +#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) +#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) +#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) +#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) +#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) +#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) +#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) +#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) +#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) +#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) +#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) +#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) +#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) +#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) +#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) +#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) +#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) +#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) +#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) +#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) +#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) +#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) + +#define TSB_T32A6_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,0))) +#define TSB_T32A6_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,1))) +#define TSB_T32A6_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,0))) +#define TSB_T32A6_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,1))) +#define TSB_T32A6_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,2))) +#define TSB_T32A6_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,4))) +#define TSB_T32A6_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRA,20))) +#define TSB_T32A6_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,0))) +#define TSB_T32A6_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,1))) +#define TSB_T32A6_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,2))) +#define TSB_T32A6_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,3))) +#define TSB_T32A6_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,0))) +#define TSB_T32A6_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,1))) +#define TSB_T32A6_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,2))) +#define TSB_T32A6_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,3))) +#define TSB_T32A6_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,0))) +#define TSB_T32A6_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,1))) +#define TSB_T32A6_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,2))) +#define TSB_T32A6_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,0))) +#define TSB_T32A6_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,1))) +#define TSB_T32A6_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,2))) +#define TSB_T32A6_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,4))) +#define TSB_T32A6_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRB,20))) +#define TSB_T32A6_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,0))) +#define TSB_T32A6_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,1))) +#define TSB_T32A6_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,2))) +#define TSB_T32A6_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,3))) +#define TSB_T32A6_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,0))) +#define TSB_T32A6_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,1))) +#define TSB_T32A6_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,2))) +#define TSB_T32A6_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,3))) +#define TSB_T32A6_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,0))) +#define TSB_T32A6_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,1))) +#define TSB_T32A6_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,2))) +#define TSB_T32A6_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,0))) +#define TSB_T32A6_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,1))) +#define TSB_T32A6_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,2))) +#define TSB_T32A6_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,4))) +#define TSB_T32A6_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRC,20))) +#define TSB_T32A6_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,0))) +#define TSB_T32A6_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,1))) +#define TSB_T32A6_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,2))) +#define TSB_T32A6_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,3))) +#define TSB_T32A6_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,4))) +#define TSB_T32A6_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,0))) +#define TSB_T32A6_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,1))) +#define TSB_T32A6_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,2))) +#define TSB_T32A6_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,3))) +#define TSB_T32A6_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,4))) +#define TSB_T32A6_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,0))) +#define TSB_T32A6_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,1))) +#define TSB_T32A6_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,2))) +#define TSB_T32A6_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,0))) +#define TSB_T32A6_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,1))) + +#define TSB_T32A7_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,0))) +#define TSB_T32A7_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,1))) +#define TSB_T32A7_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,0))) +#define TSB_T32A7_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,1))) +#define TSB_T32A7_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,2))) +#define TSB_T32A7_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,4))) +#define TSB_T32A7_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRA,20))) +#define TSB_T32A7_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,0))) +#define TSB_T32A7_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,1))) +#define TSB_T32A7_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,2))) +#define TSB_T32A7_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,3))) +#define TSB_T32A7_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,0))) +#define TSB_T32A7_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,1))) +#define TSB_T32A7_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,2))) +#define TSB_T32A7_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,3))) +#define TSB_T32A7_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,0))) +#define TSB_T32A7_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,1))) +#define TSB_T32A7_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,2))) +#define TSB_T32A7_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,0))) +#define TSB_T32A7_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,1))) +#define TSB_T32A7_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,2))) +#define TSB_T32A7_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,4))) +#define TSB_T32A7_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRB,20))) +#define TSB_T32A7_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,0))) +#define TSB_T32A7_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,1))) +#define TSB_T32A7_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,2))) +#define TSB_T32A7_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,3))) +#define TSB_T32A7_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,0))) +#define TSB_T32A7_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,1))) +#define TSB_T32A7_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,2))) +#define TSB_T32A7_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,3))) +#define TSB_T32A7_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,0))) +#define TSB_T32A7_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,1))) +#define TSB_T32A7_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,2))) +#define TSB_T32A7_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,0))) +#define TSB_T32A7_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,1))) +#define TSB_T32A7_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,2))) +#define TSB_T32A7_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,4))) +#define TSB_T32A7_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRC,20))) +#define TSB_T32A7_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,0))) +#define TSB_T32A7_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,1))) +#define TSB_T32A7_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,2))) +#define TSB_T32A7_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,3))) +#define TSB_T32A7_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,4))) +#define TSB_T32A7_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,0))) +#define TSB_T32A7_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,1))) +#define TSB_T32A7_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,2))) +#define TSB_T32A7_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,3))) +#define TSB_T32A7_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,4))) +#define TSB_T32A7_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,0))) +#define TSB_T32A7_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,1))) +#define TSB_T32A7_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,2))) +#define TSB_T32A7_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,0))) +#define TSB_T32A7_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,1))) + +#define TSB_T32A8_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,0))) +#define TSB_T32A8_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,1))) +#define TSB_T32A8_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,0))) +#define TSB_T32A8_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,1))) +#define TSB_T32A8_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,2))) +#define TSB_T32A8_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,4))) +#define TSB_T32A8_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRA,20))) +#define TSB_T32A8_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,0))) +#define TSB_T32A8_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,1))) +#define TSB_T32A8_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,2))) +#define TSB_T32A8_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,3))) +#define TSB_T32A8_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,0))) +#define TSB_T32A8_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,1))) +#define TSB_T32A8_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,2))) +#define TSB_T32A8_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,3))) +#define TSB_T32A8_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,0))) +#define TSB_T32A8_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,1))) +#define TSB_T32A8_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,2))) +#define TSB_T32A8_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,0))) +#define TSB_T32A8_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,1))) +#define TSB_T32A8_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,2))) +#define TSB_T32A8_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,4))) +#define TSB_T32A8_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRB,20))) +#define TSB_T32A8_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,0))) +#define TSB_T32A8_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,1))) +#define TSB_T32A8_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,2))) +#define TSB_T32A8_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,3))) +#define TSB_T32A8_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,0))) +#define TSB_T32A8_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,1))) +#define TSB_T32A8_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,2))) +#define TSB_T32A8_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,3))) +#define TSB_T32A8_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,0))) +#define TSB_T32A8_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,1))) +#define TSB_T32A8_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,2))) +#define TSB_T32A8_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,0))) +#define TSB_T32A8_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,1))) +#define TSB_T32A8_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,2))) +#define TSB_T32A8_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,4))) +#define TSB_T32A8_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRC,20))) +#define TSB_T32A8_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,0))) +#define TSB_T32A8_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,1))) +#define TSB_T32A8_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,2))) +#define TSB_T32A8_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,3))) +#define TSB_T32A8_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,4))) +#define TSB_T32A8_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,0))) +#define TSB_T32A8_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,1))) +#define TSB_T32A8_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,2))) +#define TSB_T32A8_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,3))) +#define TSB_T32A8_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,4))) +#define TSB_T32A8_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,0))) +#define TSB_T32A8_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,1))) +#define TSB_T32A8_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,2))) +#define TSB_T32A8_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,0))) +#define TSB_T32A8_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,1))) + +#define TSB_T32A9_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,0))) +#define TSB_T32A9_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,1))) +#define TSB_T32A9_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,0))) +#define TSB_T32A9_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,1))) +#define TSB_T32A9_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,2))) +#define TSB_T32A9_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,4))) +#define TSB_T32A9_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRA,20))) +#define TSB_T32A9_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,0))) +#define TSB_T32A9_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,1))) +#define TSB_T32A9_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,2))) +#define TSB_T32A9_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,3))) +#define TSB_T32A9_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,0))) +#define TSB_T32A9_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,1))) +#define TSB_T32A9_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,2))) +#define TSB_T32A9_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,3))) +#define TSB_T32A9_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,0))) +#define TSB_T32A9_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,1))) +#define TSB_T32A9_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,2))) +#define TSB_T32A9_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,0))) +#define TSB_T32A9_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,1))) +#define TSB_T32A9_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,2))) +#define TSB_T32A9_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,4))) +#define TSB_T32A9_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRB,20))) +#define TSB_T32A9_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,0))) +#define TSB_T32A9_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,1))) +#define TSB_T32A9_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,2))) +#define TSB_T32A9_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,3))) +#define TSB_T32A9_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,0))) +#define TSB_T32A9_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,1))) +#define TSB_T32A9_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,2))) +#define TSB_T32A9_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,3))) +#define TSB_T32A9_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,0))) +#define TSB_T32A9_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,1))) +#define TSB_T32A9_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,2))) +#define TSB_T32A9_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,0))) +#define TSB_T32A9_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,1))) +#define TSB_T32A9_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,2))) +#define TSB_T32A9_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,4))) +#define TSB_T32A9_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRC,20))) +#define TSB_T32A9_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,0))) +#define TSB_T32A9_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,1))) +#define TSB_T32A9_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,2))) +#define TSB_T32A9_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,3))) +#define TSB_T32A9_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,4))) +#define TSB_T32A9_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,0))) +#define TSB_T32A9_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,1))) +#define TSB_T32A9_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,2))) +#define TSB_T32A9_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,3))) +#define TSB_T32A9_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,4))) +#define TSB_T32A9_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,0))) +#define TSB_T32A9_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,1))) +#define TSB_T32A9_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,2))) +#define TSB_T32A9_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,0))) +#define TSB_T32A9_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,1))) + +#define TSB_T32A10_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,0))) +#define TSB_T32A10_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,1))) +#define TSB_T32A10_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,0))) +#define TSB_T32A10_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,1))) +#define TSB_T32A10_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,2))) +#define TSB_T32A10_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,4))) +#define TSB_T32A10_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRA,20))) +#define TSB_T32A10_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,0))) +#define TSB_T32A10_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,1))) +#define TSB_T32A10_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,2))) +#define TSB_T32A10_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,3))) +#define TSB_T32A10_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,0))) +#define TSB_T32A10_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,1))) +#define TSB_T32A10_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,2))) +#define TSB_T32A10_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,3))) +#define TSB_T32A10_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,0))) +#define TSB_T32A10_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,1))) +#define TSB_T32A10_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,2))) +#define TSB_T32A10_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,0))) +#define TSB_T32A10_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,1))) +#define TSB_T32A10_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,2))) +#define TSB_T32A10_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,4))) +#define TSB_T32A10_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRB,20))) +#define TSB_T32A10_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,0))) +#define TSB_T32A10_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,1))) +#define TSB_T32A10_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,2))) +#define TSB_T32A10_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,3))) +#define TSB_T32A10_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,0))) +#define TSB_T32A10_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,1))) +#define TSB_T32A10_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,2))) +#define TSB_T32A10_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,3))) +#define TSB_T32A10_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,0))) +#define TSB_T32A10_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,1))) +#define TSB_T32A10_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,2))) +#define TSB_T32A10_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,0))) +#define TSB_T32A10_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,1))) +#define TSB_T32A10_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,2))) +#define TSB_T32A10_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,4))) +#define TSB_T32A10_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRC,20))) +#define TSB_T32A10_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,0))) +#define TSB_T32A10_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,1))) +#define TSB_T32A10_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,2))) +#define TSB_T32A10_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,3))) +#define TSB_T32A10_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,4))) +#define TSB_T32A10_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,0))) +#define TSB_T32A10_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,1))) +#define TSB_T32A10_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,2))) +#define TSB_T32A10_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,3))) +#define TSB_T32A10_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,4))) +#define TSB_T32A10_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,0))) +#define TSB_T32A10_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,1))) +#define TSB_T32A10_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,2))) +#define TSB_T32A10_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,0))) +#define TSB_T32A10_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,1))) + +#define TSB_T32A11_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,0))) +#define TSB_T32A11_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,1))) +#define TSB_T32A11_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,0))) +#define TSB_T32A11_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,1))) +#define TSB_T32A11_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,2))) +#define TSB_T32A11_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,4))) +#define TSB_T32A11_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRA,20))) +#define TSB_T32A11_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,0))) +#define TSB_T32A11_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,1))) +#define TSB_T32A11_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,2))) +#define TSB_T32A11_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,3))) +#define TSB_T32A11_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,0))) +#define TSB_T32A11_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,1))) +#define TSB_T32A11_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,2))) +#define TSB_T32A11_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,3))) +#define TSB_T32A11_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,0))) +#define TSB_T32A11_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,1))) +#define TSB_T32A11_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,2))) +#define TSB_T32A11_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,0))) +#define TSB_T32A11_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,1))) +#define TSB_T32A11_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,2))) +#define TSB_T32A11_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,4))) +#define TSB_T32A11_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRB,20))) +#define TSB_T32A11_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,0))) +#define TSB_T32A11_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,1))) +#define TSB_T32A11_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,2))) +#define TSB_T32A11_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,3))) +#define TSB_T32A11_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,0))) +#define TSB_T32A11_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,1))) +#define TSB_T32A11_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,2))) +#define TSB_T32A11_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,3))) +#define TSB_T32A11_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,0))) +#define TSB_T32A11_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,1))) +#define TSB_T32A11_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,2))) +#define TSB_T32A11_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,0))) +#define TSB_T32A11_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,1))) +#define TSB_T32A11_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,2))) +#define TSB_T32A11_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,4))) +#define TSB_T32A11_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRC,20))) +#define TSB_T32A11_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,0))) +#define TSB_T32A11_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,1))) +#define TSB_T32A11_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,2))) +#define TSB_T32A11_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,3))) +#define TSB_T32A11_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,4))) +#define TSB_T32A11_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,0))) +#define TSB_T32A11_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,1))) +#define TSB_T32A11_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,2))) +#define TSB_T32A11_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,3))) +#define TSB_T32A11_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,4))) +#define TSB_T32A11_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,0))) +#define TSB_T32A11_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,1))) +#define TSB_T32A11_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,2))) +#define TSB_T32A11_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,0))) +#define TSB_T32A11_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,1))) + +#define TSB_T32A12_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,0))) +#define TSB_T32A12_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,1))) +#define TSB_T32A12_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,0))) +#define TSB_T32A12_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,1))) +#define TSB_T32A12_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,2))) +#define TSB_T32A12_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,4))) +#define TSB_T32A12_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRA,20))) +#define TSB_T32A12_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,0))) +#define TSB_T32A12_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,1))) +#define TSB_T32A12_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,2))) +#define TSB_T32A12_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,3))) +#define TSB_T32A12_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,0))) +#define TSB_T32A12_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,1))) +#define TSB_T32A12_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,2))) +#define TSB_T32A12_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,3))) +#define TSB_T32A12_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,0))) +#define TSB_T32A12_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,1))) +#define TSB_T32A12_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,2))) +#define TSB_T32A12_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,0))) +#define TSB_T32A12_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,1))) +#define TSB_T32A12_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,2))) +#define TSB_T32A12_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,4))) +#define TSB_T32A12_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRB,20))) +#define TSB_T32A12_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,0))) +#define TSB_T32A12_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,1))) +#define TSB_T32A12_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,2))) +#define TSB_T32A12_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,3))) +#define TSB_T32A12_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,0))) +#define TSB_T32A12_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,1))) +#define TSB_T32A12_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,2))) +#define TSB_T32A12_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,3))) +#define TSB_T32A12_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,0))) +#define TSB_T32A12_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,1))) +#define TSB_T32A12_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,2))) +#define TSB_T32A12_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,0))) +#define TSB_T32A12_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,1))) +#define TSB_T32A12_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,2))) +#define TSB_T32A12_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,4))) +#define TSB_T32A12_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRC,20))) +#define TSB_T32A12_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,0))) +#define TSB_T32A12_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,1))) +#define TSB_T32A12_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,2))) +#define TSB_T32A12_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,3))) +#define TSB_T32A12_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,4))) +#define TSB_T32A12_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,0))) +#define TSB_T32A12_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,1))) +#define TSB_T32A12_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,2))) +#define TSB_T32A12_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,3))) +#define TSB_T32A12_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,4))) +#define TSB_T32A12_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,0))) +#define TSB_T32A12_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,1))) +#define TSB_T32A12_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,2))) +#define TSB_T32A12_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,0))) +#define TSB_T32A12_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,1))) + +#define TSB_T32A13_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,0))) +#define TSB_T32A13_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,1))) +#define TSB_T32A13_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,0))) +#define TSB_T32A13_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,1))) +#define TSB_T32A13_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,2))) +#define TSB_T32A13_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,4))) +#define TSB_T32A13_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRA,20))) +#define TSB_T32A13_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,0))) +#define TSB_T32A13_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,1))) +#define TSB_T32A13_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,2))) +#define TSB_T32A13_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,3))) +#define TSB_T32A13_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,0))) +#define TSB_T32A13_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,1))) +#define TSB_T32A13_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,2))) +#define TSB_T32A13_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,3))) +#define TSB_T32A13_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,0))) +#define TSB_T32A13_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,1))) +#define TSB_T32A13_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,2))) +#define TSB_T32A13_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,0))) +#define TSB_T32A13_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,1))) +#define TSB_T32A13_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,2))) +#define TSB_T32A13_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,4))) +#define TSB_T32A13_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRB,20))) +#define TSB_T32A13_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,0))) +#define TSB_T32A13_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,1))) +#define TSB_T32A13_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,2))) +#define TSB_T32A13_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,3))) +#define TSB_T32A13_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,0))) +#define TSB_T32A13_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,1))) +#define TSB_T32A13_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,2))) +#define TSB_T32A13_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,3))) +#define TSB_T32A13_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,0))) +#define TSB_T32A13_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,1))) +#define TSB_T32A13_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,2))) +#define TSB_T32A13_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,0))) +#define TSB_T32A13_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,1))) +#define TSB_T32A13_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,2))) +#define TSB_T32A13_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,4))) +#define TSB_T32A13_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRC,20))) +#define TSB_T32A13_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,0))) +#define TSB_T32A13_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,1))) +#define TSB_T32A13_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,2))) +#define TSB_T32A13_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,3))) +#define TSB_T32A13_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,4))) +#define TSB_T32A13_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,0))) +#define TSB_T32A13_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,1))) +#define TSB_T32A13_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,2))) +#define TSB_T32A13_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,3))) +#define TSB_T32A13_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,4))) +#define TSB_T32A13_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,0))) +#define TSB_T32A13_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,1))) +#define TSB_T32A13_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,2))) +#define TSB_T32A13_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,0))) +#define TSB_T32A13_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,1))) + +#define TSB_T32A14_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->MOD,0))) +#define TSB_T32A14_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->MOD,1))) +#define TSB_T32A14_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,0))) +#define TSB_T32A14_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,1))) +#define TSB_T32A14_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,2))) +#define TSB_T32A14_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,4))) +#define TSB_T32A14_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->CRA,20))) +#define TSB_T32A14_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,0))) +#define TSB_T32A14_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,1))) +#define TSB_T32A14_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,2))) +#define TSB_T32A14_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,3))) +#define TSB_T32A14_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,0))) +#define TSB_T32A14_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,1))) +#define TSB_T32A14_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,2))) +#define TSB_T32A14_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,3))) +#define TSB_T32A14_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAA,0))) +#define TSB_T32A14_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAA,1))) +#define TSB_T32A14_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAA,2))) +#define TSB_T32A14_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,0))) +#define TSB_T32A14_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,1))) +#define TSB_T32A14_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,2))) +#define TSB_T32A14_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,4))) +#define TSB_T32A14_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->CRB,20))) +#define TSB_T32A14_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,0))) +#define TSB_T32A14_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,1))) +#define TSB_T32A14_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,2))) +#define TSB_T32A14_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,3))) +#define TSB_T32A14_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,0))) +#define TSB_T32A14_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,1))) +#define TSB_T32A14_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,2))) +#define TSB_T32A14_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,3))) +#define TSB_T32A14_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAB,0))) +#define TSB_T32A14_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAB,1))) +#define TSB_T32A14_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAB,2))) +#define TSB_T32A14_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,0))) +#define TSB_T32A14_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,1))) +#define TSB_T32A14_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,2))) +#define TSB_T32A14_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,4))) +#define TSB_T32A14_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->CRC,20))) +#define TSB_T32A14_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,0))) +#define TSB_T32A14_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,1))) +#define TSB_T32A14_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,2))) +#define TSB_T32A14_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,3))) +#define TSB_T32A14_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,4))) +#define TSB_T32A14_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,0))) +#define TSB_T32A14_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,1))) +#define TSB_T32A14_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,2))) +#define TSB_T32A14_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,3))) +#define TSB_T32A14_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,4))) +#define TSB_T32A14_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAC,0))) +#define TSB_T32A14_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAC,1))) +#define TSB_T32A14_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAC,2))) +#define TSB_T32A14_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->PLSCR,0))) +#define TSB_T32A14_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->PLSCR,1))) + +#define TSB_T32A15_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->MOD,0))) +#define TSB_T32A15_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->MOD,1))) +#define TSB_T32A15_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,0))) +#define TSB_T32A15_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,1))) +#define TSB_T32A15_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,2))) +#define TSB_T32A15_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,4))) +#define TSB_T32A15_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->CRA,20))) +#define TSB_T32A15_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,0))) +#define TSB_T32A15_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,1))) +#define TSB_T32A15_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,2))) +#define TSB_T32A15_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,3))) +#define TSB_T32A15_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,0))) +#define TSB_T32A15_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,1))) +#define TSB_T32A15_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,2))) +#define TSB_T32A15_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,3))) +#define TSB_T32A15_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAA,0))) +#define TSB_T32A15_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAA,1))) +#define TSB_T32A15_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAA,2))) +#define TSB_T32A15_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,0))) +#define TSB_T32A15_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,1))) +#define TSB_T32A15_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,2))) +#define TSB_T32A15_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,4))) +#define TSB_T32A15_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->CRB,20))) +#define TSB_T32A15_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,0))) +#define TSB_T32A15_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,1))) +#define TSB_T32A15_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,2))) +#define TSB_T32A15_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,3))) +#define TSB_T32A15_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,0))) +#define TSB_T32A15_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,1))) +#define TSB_T32A15_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,2))) +#define TSB_T32A15_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,3))) +#define TSB_T32A15_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAB,0))) +#define TSB_T32A15_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAB,1))) +#define TSB_T32A15_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAB,2))) +#define TSB_T32A15_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,0))) +#define TSB_T32A15_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,1))) +#define TSB_T32A15_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,2))) +#define TSB_T32A15_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,4))) +#define TSB_T32A15_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->CRC,20))) +#define TSB_T32A15_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,0))) +#define TSB_T32A15_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,1))) +#define TSB_T32A15_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,2))) +#define TSB_T32A15_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,3))) +#define TSB_T32A15_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,4))) +#define TSB_T32A15_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,0))) +#define TSB_T32A15_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,1))) +#define TSB_T32A15_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,2))) +#define TSB_T32A15_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,3))) +#define TSB_T32A15_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,4))) +#define TSB_T32A15_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAC,0))) +#define TSB_T32A15_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAC,1))) +#define TSB_T32A15_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAC,2))) +#define TSB_T32A15_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->PLSCR,0))) +#define TSB_T32A15_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->PLSCR,1))) + + +/* TSSI */ +#define TSB_TSSI0_CR0_RXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,6))) +#define TSB_TSSI0_CR0_RXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,7))) +#define TSB_TSSI0_CR0_TXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,14))) +#define TSB_TSSI0_CR0_TXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,15))) +#define TSB_TSSI0_CR0_SWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,31))) +#define TSB_TSSI0_CR1_RXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR1,2))) +#define TSB_TSSI0_CR1_TXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR1,10))) +#define TSB_TSSI0_RDMACR_RDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RDMACR,0))) +#define TSB_TSSI0_RSR_RBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,0))) +#define TSB_TSSI0_RSR_RFNE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,1))) +#define TSB_TSSI0_RSR_RFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,2))) +#define TSB_TSSI0_RSR_RFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,4))) +#define TSB_TSSI0_RSR_RFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,5))) +#define TSB_TSSI0_RIER_RFNEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,1))) +#define TSB_TSSI0_RIER_RFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,2))) +#define TSB_TSSI0_RIER_RCMIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,3))) +#define TSB_TSSI0_RIER_RFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,4))) +#define TSB_TSSI0_RIER_RFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,5))) +#define TSB_TSSI0_RIER_RFTEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,7))) +#define TSB_TSSI0_TDMACR_TDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TDMACR,0))) +#define TSB_TSSI0_TSR_TBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,0))) +#define TSB_TSSI0_TSR_TFNF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,1))) +#define TSB_TSSI0_TSR_TFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,2))) +#define TSB_TSSI0_TSR_TFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,4))) +#define TSB_TSSI0_TSR_TFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,5))) +#define TSB_TSSI0_TIER_TFNFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,1))) +#define TSB_TSSI0_TIER_TFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,2))) +#define TSB_TSSI0_TIER_TFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,4))) +#define TSB_TSSI0_TIER_TFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,5))) + +#define TSB_TSSI1_CR0_RXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,6))) +#define TSB_TSSI1_CR0_RXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,7))) +#define TSB_TSSI1_CR0_TXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,14))) +#define TSB_TSSI1_CR0_TXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,15))) +#define TSB_TSSI1_CR0_SWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,31))) +#define TSB_TSSI1_CR1_RXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR1,2))) +#define TSB_TSSI1_CR1_TXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR1,10))) +#define TSB_TSSI1_RDMACR_RDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RDMACR,0))) +#define TSB_TSSI1_RSR_RBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,0))) +#define TSB_TSSI1_RSR_RFNE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,1))) +#define TSB_TSSI1_RSR_RFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,2))) +#define TSB_TSSI1_RSR_RFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,4))) +#define TSB_TSSI1_RSR_RFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,5))) +#define TSB_TSSI1_RIER_RFNEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,1))) +#define TSB_TSSI1_RIER_RFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,2))) +#define TSB_TSSI1_RIER_RCMIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,3))) +#define TSB_TSSI1_RIER_RFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,4))) +#define TSB_TSSI1_RIER_RFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,5))) +#define TSB_TSSI1_RIER_RFTEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,7))) +#define TSB_TSSI1_TDMACR_TDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TDMACR,0))) +#define TSB_TSSI1_TSR_TBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,0))) +#define TSB_TSSI1_TSR_TFNF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,1))) +#define TSB_TSSI1_TSR_TFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,2))) +#define TSB_TSSI1_TSR_TFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,4))) +#define TSB_TSSI1_TSR_TFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,5))) +#define TSB_TSSI1_TIER_TFNFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,1))) +#define TSB_TSSI1_TIER_TFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,2))) +#define TSB_TSSI1_TIER_TFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,4))) +#define TSB_TSSI1_TIER_TFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,5))) + + +/* UART */ +#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) +#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) +#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) +#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) +#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) +#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) +#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) +#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) +#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) +#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) +#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) +#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) +#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) +#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) +#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) +#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) +#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) +#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) +#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) +#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) +#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) +#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) +#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) +#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) +#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) +#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) +#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) +#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) +#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) +#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) +#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) +#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) +#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) +#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) +#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) +#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) +#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) +#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) +#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) +#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) +#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) +#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) + +#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) +#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) +#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) +#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) +#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) +#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) +#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) +#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) +#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) +#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) +#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) +#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) +#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) +#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) +#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) +#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) +#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) +#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) +#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) +#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) +#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) +#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) +#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) +#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) +#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) +#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) +#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) +#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) +#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) +#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) +#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) +#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) +#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) +#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) +#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) +#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) +#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) +#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) +#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) +#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) +#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) +#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) + +#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) +#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) +#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) +#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) +#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) +#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) +#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) +#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) +#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) +#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) +#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) +#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) +#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) +#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) +#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) +#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) +#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) +#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) +#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) +#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) +#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) +#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) +#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) +#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) +#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) +#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) +#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) +#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) +#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) +#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) +#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) +#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) +#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) +#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) +#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) +#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) +#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) +#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) +#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) +#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) +#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) +#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) + +#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) +#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) +#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) +#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) +#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) +#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) +#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) +#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) +#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) +#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) +#define TSB_UART3_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,16))) +#define TSB_UART3_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,17))) +#define TSB_UART3_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,18))) +#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) +#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) +#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) +#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) +#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) +#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) +#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) +#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) +#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) +#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) +#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) +#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) +#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) +#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) +#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) +#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) +#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) +#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) +#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) +#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) +#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) +#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) +#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) +#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) +#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) +#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) +#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) +#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) +#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) + +#define TSB_UART4_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SWRST,7))) +#define TSB_UART4_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,2))) +#define TSB_UART4_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,3))) +#define TSB_UART4_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,4))) +#define TSB_UART4_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,5))) +#define TSB_UART4_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,6))) +#define TSB_UART4_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,8))) +#define TSB_UART4_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,9))) +#define TSB_UART4_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,10))) +#define TSB_UART4_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,15))) +#define TSB_UART4_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,16))) +#define TSB_UART4_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,17))) +#define TSB_UART4_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,18))) +#define TSB_UART4_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,0))) +#define TSB_UART4_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,1))) +#define TSB_UART4_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,2))) +#define TSB_UART4_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,4))) +#define TSB_UART4_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,5))) +#define TSB_UART4_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,6))) +#define TSB_UART4_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,7))) +#define TSB_UART4_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->BRD,23))) +#define TSB_UART4_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,0))) +#define TSB_UART4_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,1))) +#define TSB_UART4_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,2))) +#define TSB_UART4_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,3))) +#define TSB_UART4_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,16))) +#define TSB_UART4_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,17))) +#define TSB_UART4_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,18))) +#define TSB_UART4_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,5))) +#define TSB_UART4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,6))) +#define TSB_UART4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,7))) +#define TSB_UART4_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,13))) +#define TSB_UART4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,14))) +#define TSB_UART4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,15))) +#define TSB_UART4_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,31))) +#define TSB_UART4_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,0))) +#define TSB_UART4_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,1))) +#define TSB_UART4_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,0))) +#define TSB_UART4_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,1))) +#define TSB_UART4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,2))) +#define TSB_UART4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,3))) +#define TSB_UART4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,4))) + +#define TSB_UART5_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SWRST,7))) +#define TSB_UART5_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,2))) +#define TSB_UART5_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,3))) +#define TSB_UART5_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,4))) +#define TSB_UART5_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,5))) +#define TSB_UART5_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,6))) +#define TSB_UART5_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,8))) +#define TSB_UART5_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,9))) +#define TSB_UART5_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,10))) +#define TSB_UART5_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,15))) +#define TSB_UART5_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,16))) +#define TSB_UART5_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,17))) +#define TSB_UART5_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,18))) +#define TSB_UART5_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,0))) +#define TSB_UART5_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,1))) +#define TSB_UART5_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,2))) +#define TSB_UART5_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,4))) +#define TSB_UART5_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,5))) +#define TSB_UART5_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,6))) +#define TSB_UART5_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,7))) +#define TSB_UART5_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->BRD,23))) +#define TSB_UART5_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,0))) +#define TSB_UART5_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,1))) +#define TSB_UART5_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,2))) +#define TSB_UART5_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,3))) +#define TSB_UART5_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,16))) +#define TSB_UART5_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,17))) +#define TSB_UART5_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,18))) +#define TSB_UART5_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,5))) +#define TSB_UART5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,6))) +#define TSB_UART5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,7))) +#define TSB_UART5_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,13))) +#define TSB_UART5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,14))) +#define TSB_UART5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,15))) +#define TSB_UART5_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,31))) +#define TSB_UART5_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,0))) +#define TSB_UART5_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,1))) +#define TSB_UART5_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,0))) +#define TSB_UART5_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,1))) +#define TSB_UART5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,2))) +#define TSB_UART5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,3))) +#define TSB_UART5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,4))) + + +/* I2S interface */ +#define TSB_I2S0_CSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CSTART,8))) +#define TSB_I2S0_CBUSY_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CBUSY,8))) +#define TSB_I2S0_CSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CSTOP,0))) +#define TSB_I2S0_CAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CAUDIOSET,8))) +#define TSB_I2S0_CAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CAUDIOSET,11))) +#define TSB_I2S0_CREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,0))) +#define TSB_I2S0_CREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,3))) +#define TSB_I2S0_CREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,16))) +#define TSB_I2S0_CREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,19))) +#define TSB_I2S0_CMS_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CMS_SEL,0))) +#define TSB_I2S0_CMCLK_IO_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CMCLK_IO_SEL,0))) +#define TSB_I2S0_CPHT_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CPHT_DIVOUT_EN,0))) +#define TSB_I2S0_CBCK_SRC_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CBCK_SRC_SEL,0))) +#define TSB_I2S0_CBCK_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CBCK_DIVOUT_EN,0))) +#define TSB_I2S0_ISTART_MICSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->ISTART,0))) +#define TSB_I2S0_ISTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->ISTART,8))) +#define TSB_I2S0_IBUSY_MICBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,0))) +#define TSB_I2S0_IBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,1))) +#define TSB_I2S0_IBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,16))) +#define TSB_I2S0_IBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,17))) +#define TSB_I2S0_ISTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->ISTOP,0))) +#define TSB_I2S0_IAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,8))) +#define TSB_I2S0_IAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,11))) +#define TSB_I2S0_IAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,12))) +#define TSB_I2S0_IAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,16))) +#define TSB_I2S0_IINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,0))) +#define TSB_I2S0_IINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,1))) +#define TSB_I2S0_IINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,2))) +#define TSB_I2S0_IINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,3))) +#define TSB_I2S0_IINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,0))) +#define TSB_I2S0_IINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,1))) +#define TSB_I2S0_IINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,2))) +#define TSB_I2S0_IINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,3))) +#define TSB_I2S0_IINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,16))) +#define TSB_I2S0_IINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,0))) +#define TSB_I2S0_IINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,1))) +#define TSB_I2S0_IINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,2))) +#define TSB_I2S0_IINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,3))) +#define TSB_I2S0_IMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IMUTE,0))) +#define TSB_I2S0_IREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,0))) +#define TSB_I2S0_IREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,1))) +#define TSB_I2S0_IREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,3))) +#define TSB_I2S0_IREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,16))) +#define TSB_I2S0_IREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,17))) +#define TSB_I2S0_IREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,19))) +#define TSB_I2S0_OSTART_SPKSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OSTART,0))) +#define TSB_I2S0_OSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OSTART,8))) +#define TSB_I2S0_OBUSY_SPKBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,0))) +#define TSB_I2S0_OBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,1))) +#define TSB_I2S0_OBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,16))) +#define TSB_I2S0_OBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,17))) +#define TSB_I2S0_OSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OSTOP,0))) +#define TSB_I2S0_OAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,8))) +#define TSB_I2S0_OAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,11))) +#define TSB_I2S0_OAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,12))) +#define TSB_I2S0_OAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,16))) +#define TSB_I2S0_OINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,0))) +#define TSB_I2S0_OINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,1))) +#define TSB_I2S0_OINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,2))) +#define TSB_I2S0_OINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,3))) +#define TSB_I2S0_OINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,0))) +#define TSB_I2S0_OINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,1))) +#define TSB_I2S0_OINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,2))) +#define TSB_I2S0_OINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,3))) +#define TSB_I2S0_OINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,16))) +#define TSB_I2S0_OINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,0))) +#define TSB_I2S0_OINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,1))) +#define TSB_I2S0_OINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,2))) +#define TSB_I2S0_OINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,3))) +#define TSB_I2S0_OMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OMUTE,0))) +#define TSB_I2S0_OREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,0))) +#define TSB_I2S0_OREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,1))) +#define TSB_I2S0_OREGBUSY_TXSSIZEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,2))) +#define TSB_I2S0_OREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,3))) +#define TSB_I2S0_OREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,16))) +#define TSB_I2S0_OREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,17))) +#define TSB_I2S0_OREGBUSY_TXSSIZEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,18))) +#define TSB_I2S0_OREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,19))) + +#define TSB_I2S1_CSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CSTART,8))) +#define TSB_I2S1_CBUSY_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CBUSY,8))) +#define TSB_I2S1_CSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CSTOP,0))) +#define TSB_I2S1_CAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CAUDIOSET,8))) +#define TSB_I2S1_CAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CAUDIOSET,11))) +#define TSB_I2S1_CREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,0))) +#define TSB_I2S1_CREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,3))) +#define TSB_I2S1_CREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,16))) +#define TSB_I2S1_CREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,19))) +#define TSB_I2S1_CMS_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CMS_SEL,0))) +#define TSB_I2S1_CMCLK_IO_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CMCLK_IO_SEL,0))) +#define TSB_I2S1_CPHT_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CPHT_DIVOUT_EN,0))) +#define TSB_I2S1_CBCK_SRC_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CBCK_SRC_SEL,0))) +#define TSB_I2S1_CBCK_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CBCK_DIVOUT_EN,0))) +#define TSB_I2S1_ISTART_MICSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->ISTART,0))) +#define TSB_I2S1_ISTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->ISTART,8))) +#define TSB_I2S1_IBUSY_MICBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,0))) +#define TSB_I2S1_IBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,1))) +#define TSB_I2S1_IBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,16))) +#define TSB_I2S1_IBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,17))) +#define TSB_I2S1_ISTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->ISTOP,0))) +#define TSB_I2S1_IAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,8))) +#define TSB_I2S1_IAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,11))) +#define TSB_I2S1_IAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,12))) +#define TSB_I2S1_IAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,16))) +#define TSB_I2S1_IINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,0))) +#define TSB_I2S1_IINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,1))) +#define TSB_I2S1_IINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,2))) +#define TSB_I2S1_IINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,3))) +#define TSB_I2S1_IINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,0))) +#define TSB_I2S1_IINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,1))) +#define TSB_I2S1_IINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,2))) +#define TSB_I2S1_IINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,3))) +#define TSB_I2S1_IINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,16))) +#define TSB_I2S1_IINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,0))) +#define TSB_I2S1_IINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,1))) +#define TSB_I2S1_IINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,2))) +#define TSB_I2S1_IINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,3))) +#define TSB_I2S1_IMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IMUTE,0))) +#define TSB_I2S1_IREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,0))) +#define TSB_I2S1_IREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,1))) +#define TSB_I2S1_IREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,3))) +#define TSB_I2S1_IREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,16))) +#define TSB_I2S1_IREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,17))) +#define TSB_I2S1_IREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,19))) +#define TSB_I2S1_OSTART_SPKSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OSTART,0))) +#define TSB_I2S1_OSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OSTART,8))) +#define TSB_I2S1_OBUSY_SPKBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,0))) +#define TSB_I2S1_OBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,1))) +#define TSB_I2S1_OBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,16))) +#define TSB_I2S1_OBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,17))) +#define TSB_I2S1_OSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OSTOP,0))) +#define TSB_I2S1_OAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,8))) +#define TSB_I2S1_OAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,11))) +#define TSB_I2S1_OAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,12))) +#define TSB_I2S1_OAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,16))) +#define TSB_I2S1_OINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,0))) +#define TSB_I2S1_OINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,1))) +#define TSB_I2S1_OINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,2))) +#define TSB_I2S1_OINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,3))) +#define TSB_I2S1_OINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,0))) +#define TSB_I2S1_OINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,1))) +#define TSB_I2S1_OINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,2))) +#define TSB_I2S1_OINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,3))) +#define TSB_I2S1_OINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,16))) +#define TSB_I2S1_OINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,0))) +#define TSB_I2S1_OINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,1))) +#define TSB_I2S1_OINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,2))) +#define TSB_I2S1_OINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,3))) +#define TSB_I2S1_OMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OMUTE,0))) +#define TSB_I2S1_OREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,0))) +#define TSB_I2S1_OREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,1))) +#define TSB_I2S1_OREGBUSY_TXSSIZEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,2))) +#define TSB_I2S1_OREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,3))) +#define TSB_I2S1_OREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,16))) +#define TSB_I2S1_OREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,17))) +#define TSB_I2S1_OREGBUSY_TXSSIZEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,18))) +#define TSB_I2S1_OREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,19))) + + +/* I2C */ +#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) +#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) +#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) +#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) +#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) +#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) +#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) +#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) +#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) +#define TSB_I2C0_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) +#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) +#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) +#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) +#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) +#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) +#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) +#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) +#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) +#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) +#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) +#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) +#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) +#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) +#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) +#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) +#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) +#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) +#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) +#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) +#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) +#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) +#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) +#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) +#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) +#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) +#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) +#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) +#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) + +#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) +#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) +#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) +#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) +#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) +#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) +#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) +#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) +#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) +#define TSB_I2C1_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) +#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) +#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) +#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) +#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) +#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) +#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) +#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) +#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) +#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) +#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) +#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) +#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) +#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) +#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) +#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) +#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) +#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) +#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) +#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) +#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) +#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) +#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) +#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) +#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) +#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) +#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) +#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) +#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) + +#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) +#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) +#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) +#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) +#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) +#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) +#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) +#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) +#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) +#define TSB_I2C2_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) +#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) +#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) +#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) +#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) +#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) +#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) +#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) +#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) +#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) +#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) +#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) +#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) +#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) +#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) +#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) +#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) +#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) +#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) +#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) +#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) +#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) +#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) +#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) +#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) +#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) +#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) +#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) +#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) + +#define TSB_I2C3_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,3))) +#define TSB_I2C3_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,4))) +#define TSB_I2C3_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR,0))) +#define TSB_I2C3_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,3))) +#define TSB_I2C3_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,4))) +#define TSB_I2C3_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,5))) +#define TSB_I2C3_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,6))) +#define TSB_I2C3_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,7))) +#define TSB_I2C3_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,0))) +#define TSB_I2C3_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,1))) +#define TSB_I2C3_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,2))) +#define TSB_I2C3_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,3))) +#define TSB_I2C3_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,4))) +#define TSB_I2C3_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,5))) +#define TSB_I2C3_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,6))) +#define TSB_I2C3_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,7))) +#define TSB_I2C3_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,0))) +#define TSB_I2C3_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,1))) +#define TSB_I2C3_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,2))) +#define TSB_I2C3_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,3))) +#define TSB_I2C3_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,4))) +#define TSB_I2C3_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,5))) +#define TSB_I2C3_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,6))) +#define TSB_I2C3_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,0))) +#define TSB_I2C3_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,1))) +#define TSB_I2C3_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,2))) +#define TSB_I2C3_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,3))) +#define TSB_I2C3_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,0))) +#define TSB_I2C3_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,1))) +#define TSB_I2C3_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,2))) +#define TSB_I2C3_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,3))) +#define TSB_I2C3_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,4))) +#define TSB_I2C3_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,5))) +#define TSB_I2C3_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,6))) +#define TSB_I2C3_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,7))) +#define TSB_I2C3_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,0))) +#define TSB_I2C3_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,1))) +#define TSB_I2C3_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR2,0))) + +#define TSB_I2C4_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,3))) +#define TSB_I2C4_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,4))) +#define TSB_I2C4_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR,0))) +#define TSB_I2C4_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,3))) +#define TSB_I2C4_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,4))) +#define TSB_I2C4_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,5))) +#define TSB_I2C4_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,6))) +#define TSB_I2C4_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,7))) +#define TSB_I2C4_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,0))) +#define TSB_I2C4_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,1))) +#define TSB_I2C4_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,2))) +#define TSB_I2C4_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,3))) +#define TSB_I2C4_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,4))) +#define TSB_I2C4_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,5))) +#define TSB_I2C4_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,6))) +#define TSB_I2C4_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,7))) +#define TSB_I2C4_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,0))) +#define TSB_I2C4_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,1))) +#define TSB_I2C4_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,2))) +#define TSB_I2C4_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,3))) +#define TSB_I2C4_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,4))) +#define TSB_I2C4_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,5))) +#define TSB_I2C4_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,6))) +#define TSB_I2C4_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,0))) +#define TSB_I2C4_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,1))) +#define TSB_I2C4_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,2))) +#define TSB_I2C4_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,3))) +#define TSB_I2C4_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,0))) +#define TSB_I2C4_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,1))) +#define TSB_I2C4_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,2))) +#define TSB_I2C4_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,3))) +#define TSB_I2C4_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,4))) +#define TSB_I2C4_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,5))) +#define TSB_I2C4_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,6))) +#define TSB_I2C4_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,7))) +#define TSB_I2C4_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,0))) +#define TSB_I2C4_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,1))) +#define TSB_I2C4_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR2,0))) + + +/* EI2C */ +#define TSB_EI2C0_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AEN,0))) +#define TSB_EI2C0_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,0))) +#define TSB_EI2C0_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,1))) +#define TSB_EI2C0_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,2))) +#define TSB_EI2C0_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,3))) +#define TSB_EI2C0_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,4))) +#define TSB_EI2C0_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,8))) +#define TSB_EI2C0_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,11))) +#define TSB_EI2C0_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,0))) +#define TSB_EI2C0_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,1))) +#define TSB_EI2C0_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,2))) +#define TSB_EI2C0_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,3))) +#define TSB_EI2C0_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,4))) +#define TSB_EI2C0_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,10))) +#define TSB_EI2C0_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,0))) +#define TSB_EI2C0_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,1))) +#define TSB_EI2C0_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,2))) +#define TSB_EI2C0_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,3))) +#define TSB_EI2C0_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,0))) +#define TSB_EI2C0_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,1))) +#define TSB_EI2C0_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,2))) +#define TSB_EI2C0_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,3))) +#define TSB_EI2C0_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,4))) +#define TSB_EI2C0_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,5))) +#define TSB_EI2C0_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,6))) +#define TSB_EI2C0_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,7))) +#define TSB_EI2C0_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,8))) +#define TSB_EI2C0_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,9))) +#define TSB_EI2C0_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,10))) +#define TSB_EI2C0_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,11))) +#define TSB_EI2C0_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,12))) +#define TSB_EI2C0_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,13))) +#define TSB_EI2C0_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR1,0))) +#define TSB_EI2C0_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR1,15))) +#define TSB_EI2C0_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR2,0))) +#define TSB_EI2C0_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR2,15))) +#define TSB_EI2C0_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,0))) +#define TSB_EI2C0_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,1))) +#define TSB_EI2C0_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,2))) +#define TSB_EI2C0_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,6))) +#define TSB_EI2C0_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,7))) +#define TSB_EI2C0_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,8))) +#define TSB_EI2C0_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,9))) +#define TSB_EI2C0_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,11))) +#define TSB_EI2C0_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,12))) +#define TSB_EI2C0_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,13))) +#define TSB_EI2C0_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,14))) +#define TSB_EI2C0_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,15))) +#define TSB_EI2C0_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,0))) +#define TSB_EI2C0_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,1))) +#define TSB_EI2C0_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,2))) +#define TSB_EI2C0_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,3))) + +#define TSB_EI2C1_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AEN,0))) +#define TSB_EI2C1_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,0))) +#define TSB_EI2C1_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,1))) +#define TSB_EI2C1_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,2))) +#define TSB_EI2C1_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,3))) +#define TSB_EI2C1_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,4))) +#define TSB_EI2C1_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,8))) +#define TSB_EI2C1_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,11))) +#define TSB_EI2C1_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,0))) +#define TSB_EI2C1_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,1))) +#define TSB_EI2C1_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,2))) +#define TSB_EI2C1_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,3))) +#define TSB_EI2C1_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,4))) +#define TSB_EI2C1_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,10))) +#define TSB_EI2C1_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,0))) +#define TSB_EI2C1_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,1))) +#define TSB_EI2C1_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,2))) +#define TSB_EI2C1_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,3))) +#define TSB_EI2C1_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,0))) +#define TSB_EI2C1_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,1))) +#define TSB_EI2C1_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,2))) +#define TSB_EI2C1_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,3))) +#define TSB_EI2C1_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,4))) +#define TSB_EI2C1_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,5))) +#define TSB_EI2C1_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,6))) +#define TSB_EI2C1_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,7))) +#define TSB_EI2C1_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,8))) +#define TSB_EI2C1_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,9))) +#define TSB_EI2C1_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,10))) +#define TSB_EI2C1_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,11))) +#define TSB_EI2C1_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,12))) +#define TSB_EI2C1_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,13))) +#define TSB_EI2C1_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR1,0))) +#define TSB_EI2C1_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR1,15))) +#define TSB_EI2C1_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR2,0))) +#define TSB_EI2C1_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR2,15))) +#define TSB_EI2C1_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,0))) +#define TSB_EI2C1_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,1))) +#define TSB_EI2C1_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,2))) +#define TSB_EI2C1_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,6))) +#define TSB_EI2C1_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,7))) +#define TSB_EI2C1_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,8))) +#define TSB_EI2C1_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,9))) +#define TSB_EI2C1_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,11))) +#define TSB_EI2C1_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,12))) +#define TSB_EI2C1_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,13))) +#define TSB_EI2C1_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,14))) +#define TSB_EI2C1_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,15))) +#define TSB_EI2C1_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,0))) +#define TSB_EI2C1_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,1))) +#define TSB_EI2C1_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,2))) +#define TSB_EI2C1_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,3))) + +#define TSB_EI2C2_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AEN,0))) +#define TSB_EI2C2_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,0))) +#define TSB_EI2C2_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,1))) +#define TSB_EI2C2_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,2))) +#define TSB_EI2C2_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,3))) +#define TSB_EI2C2_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,4))) +#define TSB_EI2C2_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,8))) +#define TSB_EI2C2_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,11))) +#define TSB_EI2C2_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,0))) +#define TSB_EI2C2_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,1))) +#define TSB_EI2C2_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,2))) +#define TSB_EI2C2_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,3))) +#define TSB_EI2C2_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,4))) +#define TSB_EI2C2_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,10))) +#define TSB_EI2C2_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,0))) +#define TSB_EI2C2_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,1))) +#define TSB_EI2C2_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,2))) +#define TSB_EI2C2_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,3))) +#define TSB_EI2C2_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,0))) +#define TSB_EI2C2_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,1))) +#define TSB_EI2C2_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,2))) +#define TSB_EI2C2_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,3))) +#define TSB_EI2C2_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,4))) +#define TSB_EI2C2_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,5))) +#define TSB_EI2C2_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,6))) +#define TSB_EI2C2_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,7))) +#define TSB_EI2C2_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,8))) +#define TSB_EI2C2_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,9))) +#define TSB_EI2C2_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,10))) +#define TSB_EI2C2_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,11))) +#define TSB_EI2C2_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,12))) +#define TSB_EI2C2_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,13))) +#define TSB_EI2C2_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR1,0))) +#define TSB_EI2C2_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR1,15))) +#define TSB_EI2C2_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR2,0))) +#define TSB_EI2C2_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR2,15))) +#define TSB_EI2C2_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,0))) +#define TSB_EI2C2_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,1))) +#define TSB_EI2C2_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,2))) +#define TSB_EI2C2_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,6))) +#define TSB_EI2C2_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,7))) +#define TSB_EI2C2_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,8))) +#define TSB_EI2C2_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,9))) +#define TSB_EI2C2_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,11))) +#define TSB_EI2C2_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,12))) +#define TSB_EI2C2_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,13))) +#define TSB_EI2C2_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,14))) +#define TSB_EI2C2_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,15))) +#define TSB_EI2C2_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,0))) +#define TSB_EI2C2_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,1))) +#define TSB_EI2C2_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,2))) +#define TSB_EI2C2_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,3))) + +#define TSB_EI2C3_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AEN,0))) +#define TSB_EI2C3_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,0))) +#define TSB_EI2C3_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,1))) +#define TSB_EI2C3_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,2))) +#define TSB_EI2C3_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,3))) +#define TSB_EI2C3_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,4))) +#define TSB_EI2C3_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,8))) +#define TSB_EI2C3_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,11))) +#define TSB_EI2C3_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,0))) +#define TSB_EI2C3_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,1))) +#define TSB_EI2C3_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,2))) +#define TSB_EI2C3_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,3))) +#define TSB_EI2C3_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,4))) +#define TSB_EI2C3_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,10))) +#define TSB_EI2C3_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,0))) +#define TSB_EI2C3_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,1))) +#define TSB_EI2C3_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,2))) +#define TSB_EI2C3_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,3))) +#define TSB_EI2C3_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,0))) +#define TSB_EI2C3_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,1))) +#define TSB_EI2C3_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,2))) +#define TSB_EI2C3_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,3))) +#define TSB_EI2C3_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,4))) +#define TSB_EI2C3_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,5))) +#define TSB_EI2C3_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,6))) +#define TSB_EI2C3_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,7))) +#define TSB_EI2C3_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,8))) +#define TSB_EI2C3_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,9))) +#define TSB_EI2C3_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,10))) +#define TSB_EI2C3_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,11))) +#define TSB_EI2C3_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,12))) +#define TSB_EI2C3_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,13))) +#define TSB_EI2C3_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR1,0))) +#define TSB_EI2C3_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR1,15))) +#define TSB_EI2C3_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR2,0))) +#define TSB_EI2C3_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR2,15))) +#define TSB_EI2C3_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,0))) +#define TSB_EI2C3_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,1))) +#define TSB_EI2C3_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,2))) +#define TSB_EI2C3_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,6))) +#define TSB_EI2C3_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,7))) +#define TSB_EI2C3_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,8))) +#define TSB_EI2C3_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,9))) +#define TSB_EI2C3_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,11))) +#define TSB_EI2C3_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,12))) +#define TSB_EI2C3_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,13))) +#define TSB_EI2C3_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,14))) +#define TSB_EI2C3_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,15))) +#define TSB_EI2C3_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,0))) +#define TSB_EI2C3_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,1))) +#define TSB_EI2C3_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,2))) +#define TSB_EI2C3_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,3))) + +#define TSB_EI2C4_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AEN,0))) +#define TSB_EI2C4_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,0))) +#define TSB_EI2C4_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,1))) +#define TSB_EI2C4_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,2))) +#define TSB_EI2C4_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,3))) +#define TSB_EI2C4_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,4))) +#define TSB_EI2C4_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,8))) +#define TSB_EI2C4_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,11))) +#define TSB_EI2C4_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,0))) +#define TSB_EI2C4_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,1))) +#define TSB_EI2C4_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,2))) +#define TSB_EI2C4_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,3))) +#define TSB_EI2C4_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,4))) +#define TSB_EI2C4_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,10))) +#define TSB_EI2C4_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,0))) +#define TSB_EI2C4_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,1))) +#define TSB_EI2C4_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,2))) +#define TSB_EI2C4_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,3))) +#define TSB_EI2C4_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,0))) +#define TSB_EI2C4_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,1))) +#define TSB_EI2C4_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,2))) +#define TSB_EI2C4_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,3))) +#define TSB_EI2C4_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,4))) +#define TSB_EI2C4_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,5))) +#define TSB_EI2C4_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,6))) +#define TSB_EI2C4_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,7))) +#define TSB_EI2C4_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,8))) +#define TSB_EI2C4_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,9))) +#define TSB_EI2C4_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,10))) +#define TSB_EI2C4_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,11))) +#define TSB_EI2C4_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,12))) +#define TSB_EI2C4_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,13))) +#define TSB_EI2C4_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR1,0))) +#define TSB_EI2C4_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR1,15))) +#define TSB_EI2C4_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR2,0))) +#define TSB_EI2C4_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR2,15))) +#define TSB_EI2C4_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,0))) +#define TSB_EI2C4_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,1))) +#define TSB_EI2C4_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,2))) +#define TSB_EI2C4_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,6))) +#define TSB_EI2C4_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,7))) +#define TSB_EI2C4_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,8))) +#define TSB_EI2C4_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,9))) +#define TSB_EI2C4_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,11))) +#define TSB_EI2C4_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,12))) +#define TSB_EI2C4_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,13))) +#define TSB_EI2C4_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,14))) +#define TSB_EI2C4_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,15))) +#define TSB_EI2C4_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,0))) +#define TSB_EI2C4_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,1))) +#define TSB_EI2C4_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,2))) +#define TSB_EI2C4_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,3))) + + +/* Finite Impulse Response */ +#define TSB_FIRnore_START_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->START,0))) +#define TSB_FIRnore_CTRL_ODATAFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->CTRL,28))) +#define TSB_FIRnore_INITIALIZE_INITIALIZE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INITIALIZE,0))) +#define TSB_FIRnore_INTEN_IDATAWREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INTEN,0))) +#define TSB_FIRnore_INTEN_ODATARREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INTEN,1))) +#define TSB_FIRnore_INTEN_OVERFLOW (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INTEN,2))) +#define TSB_FIRnore_DMAEN_IDATAWREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->DMAEN,0))) +#define TSB_FIRnore_DMAEN_ODATARREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->DMAEN,1))) +#define TSB_FIRnore_RAWINTSTAT_IDATAWREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->RAWINTSTAT,0))) +#define TSB_FIRnore_RAWINTSTAT_ODATARREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->RAWINTSTAT,1))) +#define TSB_FIRnore_RAWINTSTAT_OVERFLOW (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->RAWINTSTAT,2))) + + +/* Port A */ +#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) +#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) +#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) +#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) +#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) +#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) +#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) +#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) +#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) +#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) +#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) +#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) +#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) +#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) +#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) +#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) +#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) +#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) +#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) +#define TSB_PA_FR1_PA3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,3))) +#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) +#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) +#define TSB_PA_FR1_PA6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6))) +#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) +#define TSB_PA_FR2_PA0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,0))) +#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) +#define TSB_PA_FR2_PA4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,4))) +#define TSB_PA_FR2_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7))) +#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) +#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) +#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) +#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) +#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) +#define TSB_PA_FR3_PA5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,5))) +#define TSB_PA_FR3_PA6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,6))) +#define TSB_PA_FR3_PA7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,7))) +#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) +#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) +#define TSB_PA_FR5_PA3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,3))) +#define TSB_PA_FR5_PA4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,4))) +#define TSB_PA_FR5_PA5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,5))) +#define TSB_PA_FR5_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,7))) +#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) +#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) +#define TSB_PA_FR6_PA4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,4))) +#define TSB_PA_FR6_PA5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,5))) +#define TSB_PA_FR6_PA6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,6))) +#define TSB_PA_FR6_PA7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,7))) +#define TSB_PA_FR7_PA0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,0))) +#define TSB_PA_FR7_PA1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,1))) +#define TSB_PA_FR7_PA2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,2))) +#define TSB_PA_FR7_PA3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,3))) +#define TSB_PA_FR7_PA4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,4))) +#define TSB_PA_FR7_PA5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,5))) +#define TSB_PA_FR7_PA6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,6))) +#define TSB_PA_FR7_PA7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,7))) +#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) +#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) +#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) +#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) +#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) +#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) +#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) +#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) +#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) +#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) +#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) +#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) +#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) +#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) +#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) +#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) +#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) +#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) +#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) +#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) +#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) +#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) +#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) +#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) +#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) +#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) +#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) +#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) +#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) +#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) +#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) +#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) + + +/* Port B */ +#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) +#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) +#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) +#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) +#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) +#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) +#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) +#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) +#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) +#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) +#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) +#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) +#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) +#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) +#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) +#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) +#define TSB_PB_FR1_PB0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,0))) +#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) +#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) +#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) +#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4))) +#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5))) +#define TSB_PB_FR1_PB6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,6))) +#define TSB_PB_FR1_PB7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,7))) +#define TSB_PB_FR2_PB0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,0))) +#define TSB_PB_FR2_PB1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,1))) +#define TSB_PB_FR2_PB6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,6))) +#define TSB_PB_FR2_PB7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,7))) +#define TSB_PB_FR3_PB0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,0))) +#define TSB_PB_FR3_PB1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,1))) +#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) +#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) +#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4))) +#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5))) +#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6))) +#define TSB_PB_FR3_PB7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,7))) +#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) +#define TSB_PB_FR4_PB4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,4))) +#define TSB_PB_FR4_PB5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,5))) +#define TSB_PB_FR4_PB6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,6))) +#define TSB_PB_FR4_PB7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,7))) +#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) +#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) +#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) +#define TSB_PB_FR5_PB4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,4))) +#define TSB_PB_FR5_PB6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,6))) +#define TSB_PB_FR5_PB7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,7))) +#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) +#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) +#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) +#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) +#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) +#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) +#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) +#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) +#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) +#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) +#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) +#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) +#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) +#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) +#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) +#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) +#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) +#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) +#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) +#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) +#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) +#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) +#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) +#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) +#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) +#define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0))) +#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) +#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) +#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) +#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) +#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) +#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) +#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) + + +/* Port C */ +#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) +#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) +#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) +#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) +#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) +#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) +#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) +#define TSB_PC_DATA_PC7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,7))) +#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) +#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) +#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) +#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) +#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) +#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) +#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) +#define TSB_PC_CR_PC7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,7))) +#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) +#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) +#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2))) +#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3))) +#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) +#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) +#define TSB_PC_FR1_PC6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,6))) +#define TSB_PC_FR1_PC7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,7))) +#define TSB_PC_FR3_PC0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,0))) +#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) +#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) +#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) +#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) +#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) +#define TSB_PC_FR4_PC0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,0))) +#define TSB_PC_FR4_PC1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,1))) +#define TSB_PC_FR4_PC2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,2))) +#define TSB_PC_FR4_PC3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,3))) +#define TSB_PC_FR5_PC0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,0))) +#define TSB_PC_FR5_PC1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,1))) +#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) +#define TSB_PC_FR5_PC4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,4))) +#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) +#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) +#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) +#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) +#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) +#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) +#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) +#define TSB_PC_OD_PC7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,7))) +#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) +#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) +#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) +#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) +#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) +#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) +#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) +#define TSB_PC_PUP_PC7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,7))) +#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) +#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) +#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) +#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) +#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) +#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) +#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) +#define TSB_PC_PDN_PC7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,7))) +#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) +#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) +#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) +#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) +#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) +#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) +#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) +#define TSB_PC_IE_PC7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,7))) + + +/* Port D */ +#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) +#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) +#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) +#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) +#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) +#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) +#define TSB_PD_DATA_PD6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,6))) +#define TSB_PD_DATA_PD7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,7))) +#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) +#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) +#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) +#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) +#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) +#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) +#define TSB_PD_CR_PD6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,6))) +#define TSB_PD_CR_PD7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,7))) +#define TSB_PD_FR1_PD0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,0))) +#define TSB_PD_FR1_PD1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1))) +#define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2))) +#define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3))) +#define TSB_PD_FR1_PD4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4))) +#define TSB_PD_FR1_PD5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,5))) +#define TSB_PD_FR1_PD6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,6))) +#define TSB_PD_FR1_PD7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,7))) +#define TSB_PD_FR2_PD0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,0))) +#define TSB_PD_FR2_PD1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,1))) +#define TSB_PD_FR2_PD6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,6))) +#define TSB_PD_FR2_PD7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,7))) +#define TSB_PD_FR3_PD0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,0))) +#define TSB_PD_FR3_PD1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,1))) +#define TSB_PD_FR3_PD2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,2))) +#define TSB_PD_FR3_PD3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,3))) +#define TSB_PD_FR3_PD4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,4))) +#define TSB_PD_FR3_PD5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,5))) +#define TSB_PD_FR3_PD6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,6))) +#define TSB_PD_FR3_PD7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,7))) +#define TSB_PD_FR4_PD0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,0))) +#define TSB_PD_FR4_PD1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,1))) +#define TSB_PD_FR4_PD2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,2))) +#define TSB_PD_FR4_PD3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,3))) +#define TSB_PD_FR5_PD0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,0))) +#define TSB_PD_FR5_PD1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,1))) +#define TSB_PD_FR5_PD2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,2))) +#define TSB_PD_FR5_PD4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,4))) +#define TSB_PD_FR5_PD6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,6))) +#define TSB_PD_FR5_PD7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,7))) +#define TSB_PD_FR6_PD0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,0))) +#define TSB_PD_FR6_PD4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,4))) +#define TSB_PD_FR6_PD5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,5))) +#define TSB_PD_FR6_PD6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,6))) +#define TSB_PD_FR6_PD7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,7))) +#define TSB_PD_FR7_PD0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,0))) +#define TSB_PD_FR7_PD1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,1))) +#define TSB_PD_FR7_PD2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,2))) +#define TSB_PD_FR7_PD3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,3))) +#define TSB_PD_FR7_PD4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,4))) +#define TSB_PD_FR7_PD5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,5))) +#define TSB_PD_FR7_PD6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,6))) +#define TSB_PD_FR7_PD7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,7))) +#define TSB_PD_FR8_PD2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,2))) +#define TSB_PD_FR8_PD3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,3))) +#define TSB_PD_FR8_PD4F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,4))) +#define TSB_PD_FR8_PD5F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,5))) +#define TSB_PD_FR8_PD6F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,6))) +#define TSB_PD_FR8_PD7F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,7))) +#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) +#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) +#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) +#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) +#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) +#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) +#define TSB_PD_OD_PD6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,6))) +#define TSB_PD_OD_PD7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,7))) +#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) +#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) +#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) +#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) +#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) +#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) +#define TSB_PD_PUP_PD6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,6))) +#define TSB_PD_PUP_PD7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,7))) +#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) +#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) +#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) +#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) +#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) +#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) +#define TSB_PD_PDN_PD6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,6))) +#define TSB_PD_PDN_PD7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,7))) +#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) +#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) +#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) +#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) +#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) +#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) +#define TSB_PD_IE_PD6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,6))) +#define TSB_PD_IE_PD7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,7))) + + +/* Port E */ +#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) +#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) +#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) +#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) +#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) +#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) +#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) +#define TSB_PE_DATA_PE7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,7))) +#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) +#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) +#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) +#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) +#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) +#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) +#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) +#define TSB_PE_CR_PE7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,7))) +#define TSB_PE_FR1_PE0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,0))) +#define TSB_PE_FR1_PE1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1))) +#define TSB_PE_FR1_PE2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2))) +#define TSB_PE_FR1_PE3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3))) +#define TSB_PE_FR1_PE4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4))) +#define TSB_PE_FR1_PE5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5))) +#define TSB_PE_FR1_PE6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,6))) +#define TSB_PE_FR1_PE7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,7))) +#define TSB_PE_FR2_PE0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,0))) +#define TSB_PE_FR2_PE7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,7))) +#define TSB_PE_FR3_PE0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,0))) +#define TSB_PE_FR3_PE1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,1))) +#define TSB_PE_FR3_PE2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,2))) +#define TSB_PE_FR3_PE3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,3))) +#define TSB_PE_FR3_PE4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,4))) +#define TSB_PE_FR3_PE5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,5))) +#define TSB_PE_FR3_PE6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,6))) +#define TSB_PE_FR3_PE7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,7))) +#define TSB_PE_FR4_PE0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,0))) +#define TSB_PE_FR4_PE1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,1))) +#define TSB_PE_FR4_PE2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,2))) +#define TSB_PE_FR4_PE3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,3))) +#define TSB_PE_FR4_PE4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,4))) +#define TSB_PE_FR4_PE5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,5))) +#define TSB_PE_FR4_PE6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,6))) +#define TSB_PE_FR4_PE7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,7))) +#define TSB_PE_FR5_PE0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,0))) +#define TSB_PE_FR5_PE1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,1))) +#define TSB_PE_FR5_PE2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,2))) +#define TSB_PE_FR5_PE3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,3))) +#define TSB_PE_FR5_PE4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,4))) +#define TSB_PE_FR5_PE5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,5))) +#define TSB_PE_FR5_PE6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,6))) +#define TSB_PE_FR5_PE7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,7))) +#define TSB_PE_FR6_PE4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,4))) +#define TSB_PE_FR6_PE5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,5))) +#define TSB_PE_FR6_PE6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,6))) +#define TSB_PE_FR6_PE7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,7))) +#define TSB_PE_FR7_PE0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,0))) +#define TSB_PE_FR7_PE1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,1))) +#define TSB_PE_FR7_PE2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,2))) +#define TSB_PE_FR7_PE3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,3))) +#define TSB_PE_FR8_PE0F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,0))) +#define TSB_PE_FR8_PE1F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,1))) +#define TSB_PE_FR8_PE2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,2))) +#define TSB_PE_FR8_PE3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,3))) +#define TSB_PE_FR8_PE4F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,4))) +#define TSB_PE_FR8_PE5F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,5))) +#define TSB_PE_FR8_PE6F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,6))) +#define TSB_PE_FR8_PE7F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,7))) +#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) +#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) +#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) +#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) +#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) +#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) +#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) +#define TSB_PE_OD_PE7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,7))) +#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) +#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) +#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) +#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) +#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) +#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) +#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) +#define TSB_PE_PUP_PE7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,7))) +#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) +#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) +#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) +#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) +#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) +#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) +#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) +#define TSB_PE_PDN_PE7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,7))) +#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) +#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) +#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) +#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) +#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) +#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) +#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) +#define TSB_PE_IE_PE7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,7))) + + +/* Port F */ +#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) +#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) +#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) +#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) +#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) +#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) +#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) +#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) +#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) +#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) +#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) +#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) +#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) +#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) +#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) +#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) +#define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0))) +#define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1))) +#define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4))) +#define TSB_PF_FR1_PF5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5))) +#define TSB_PF_FR1_PF6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,6))) +#define TSB_PF_FR1_PF7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,7))) +#define TSB_PF_FR4_PF7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,7))) +#define TSB_PF_FR5_PF7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,7))) +#define TSB_PF_FR6_PF2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,2))) +#define TSB_PF_FR6_PF3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,3))) +#define TSB_PF_FR7_PF2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,2))) +#define TSB_PF_FR7_PF3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,3))) +#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) +#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) +#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) +#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) +#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) +#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) +#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) +#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) +#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) +#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) +#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) +#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) +#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) +#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) +#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) +#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) +#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) +#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) +#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) +#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) +#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) +#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) +#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) +#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) +#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) +#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) +#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) +#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) +#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) +#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) +#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) +#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) + + +/* Port G */ +#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) +#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) +#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) +#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) +#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) +#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) +#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) +#define TSB_PG_DATA_PG7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7))) +#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) +#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) +#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) +#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) +#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) +#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) +#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) +#define TSB_PG_CR_PG7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7))) +#define TSB_PG_FR1_PG0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0))) +#define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1))) +#define TSB_PG_FR1_PG6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,6))) +#define TSB_PG_FR1_PG7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,7))) +#define TSB_PG_FR2_PG4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,4))) +#define TSB_PG_FR2_PG5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,5))) +#define TSB_PG_FR3_PG0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,0))) +#define TSB_PG_FR3_PG1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,1))) +#define TSB_PG_FR3_PG2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2))) +#define TSB_PG_FR3_PG3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3))) +#define TSB_PG_FR3_PG5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,5))) +#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) +#define TSB_PG_FR4_PG3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) +#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) +#define TSB_PG_FR4_PG5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,5))) +#define TSB_PG_FR4_PG6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,6))) +#define TSB_PG_FR4_PG7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,7))) +#define TSB_PG_FR5_PG0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,0))) +#define TSB_PG_FR5_PG1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,1))) +#define TSB_PG_FR5_PG2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,2))) +#define TSB_PG_FR5_PG3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,3))) +#define TSB_PG_FR5_PG4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,4))) +#define TSB_PG_FR5_PG5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,5))) +#define TSB_PG_FR5_PG6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,6))) +#define TSB_PG_FR5_PG7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,7))) +#define TSB_PG_FR6_PG2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,2))) +#define TSB_PG_FR6_PG3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,3))) +#define TSB_PG_FR6_PG4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,4))) +#define TSB_PG_FR6_PG5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,5))) +#define TSB_PG_FR6_PG6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,6))) +#define TSB_PG_FR7_PG2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,2))) +#define TSB_PG_FR7_PG3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,3))) +#define TSB_PG_FR7_PG4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,4))) +#define TSB_PG_FR7_PG5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,5))) +#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) +#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) +#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) +#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) +#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) +#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) +#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) +#define TSB_PG_OD_PG7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7))) +#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) +#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) +#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) +#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) +#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) +#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) +#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) +#define TSB_PG_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7))) +#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) +#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) +#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) +#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) +#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) +#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) +#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) +#define TSB_PG_PDN_PG7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,7))) +#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) +#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) +#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) +#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) +#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) +#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) +#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) +#define TSB_PG_IE_PG7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7))) + + +/* Port H */ +#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) +#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) +#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) +#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) +#define TSB_PH_DATA_PH4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,4))) +#define TSB_PH_DATA_PH5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,5))) +#define TSB_PH_DATA_PH6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,6))) +#define TSB_PH_DATA_PH7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,7))) +#define TSB_PH_CR_PH0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0))) +#define TSB_PH_CR_PH1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1))) +#define TSB_PH_CR_PH2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2))) +#define TSB_PH_CR_PH3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3))) +#define TSB_PH_CR_PH4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,4))) +#define TSB_PH_CR_PH5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,5))) +#define TSB_PH_CR_PH6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,6))) +#define TSB_PH_CR_PH7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,7))) +#define TSB_PH_FR1_PH0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0))) +#define TSB_PH_FR1_PH1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1))) +#define TSB_PH_FR1_PH2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2))) +#define TSB_PH_FR1_PH3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3))) +#define TSB_PH_FR1_PH4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,4))) +#define TSB_PH_FR1_PH5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,5))) +#define TSB_PH_FR1_PH6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,6))) +#define TSB_PH_FR1_PH7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,7))) +#define TSB_PH_FR3_PH0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,0))) +#define TSB_PH_FR3_PH1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,1))) +#define TSB_PH_FR3_PH2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,2))) +#define TSB_PH_FR3_PH3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,3))) +#define TSB_PH_FR3_PH4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,4))) +#define TSB_PH_FR3_PH5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,5))) +#define TSB_PH_FR3_PH6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,6))) +#define TSB_PH_FR3_PH7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,7))) +#define TSB_PH_FR4_PH0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,0))) +#define TSB_PH_FR4_PH1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,1))) +#define TSB_PH_FR4_PH2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,2))) +#define TSB_PH_FR4_PH3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,3))) +#define TSB_PH_FR5_PH0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,0))) +#define TSB_PH_FR5_PH1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,1))) +#define TSB_PH_FR5_PH2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,2))) +#define TSB_PH_FR5_PH3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,3))) +#define TSB_PH_FR5_PH4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,4))) +#define TSB_PH_FR5_PH5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,5))) +#define TSB_PH_FR5_PH6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,6))) +#define TSB_PH_FR5_PH7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,7))) +#define TSB_PH_OD_PH0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0))) +#define TSB_PH_OD_PH1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1))) +#define TSB_PH_OD_PH2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2))) +#define TSB_PH_OD_PH3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3))) +#define TSB_PH_OD_PH4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,4))) +#define TSB_PH_OD_PH5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,5))) +#define TSB_PH_OD_PH6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,6))) +#define TSB_PH_OD_PH7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,7))) +#define TSB_PH_PUP_PH0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0))) +#define TSB_PH_PUP_PH1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1))) +#define TSB_PH_PUP_PH2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2))) +#define TSB_PH_PUP_PH3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3))) +#define TSB_PH_PUP_PH4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,4))) +#define TSB_PH_PUP_PH5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,5))) +#define TSB_PH_PUP_PH6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,6))) +#define TSB_PH_PUP_PH7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,7))) +#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) +#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) +#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) +#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) +#define TSB_PH_PDN_PH4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,4))) +#define TSB_PH_PDN_PH5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,5))) +#define TSB_PH_PDN_PH6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,6))) +#define TSB_PH_PDN_PH7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,7))) +#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) +#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) +#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) +#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) +#define TSB_PH_IE_PH4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,4))) +#define TSB_PH_IE_PH5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,5))) +#define TSB_PH_IE_PH6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,6))) +#define TSB_PH_IE_PH7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,7))) + + +/* Port J */ +#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) +#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) +#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) +#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) +#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) +#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) +#define TSB_PJ_DATA_PJ6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,6))) +#define TSB_PJ_DATA_PJ7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,7))) +#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) +#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) +#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) +#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) +#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) +#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) +#define TSB_PJ_CR_PJ6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,6))) +#define TSB_PJ_CR_PJ7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,7))) +#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) +#define TSB_PJ_FR2_PJ5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,5))) +#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) +#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) +#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) +#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) +#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) +#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) +#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) +#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) +#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) +#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) +#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) +#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) +#define TSB_PJ_FR5_PJ6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,6))) +#define TSB_PJ_FR5_PJ7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,7))) +#define TSB_PJ_FR6_PJ2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,2))) +#define TSB_PJ_FR6_PJ3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,3))) +#define TSB_PJ_FR6_PJ6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,6))) +#define TSB_PJ_FR6_PJ7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,7))) +#define TSB_PJ_FR7_PJ2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,2))) +#define TSB_PJ_FR7_PJ3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,3))) +#define TSB_PJ_FR7_PJ6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,6))) +#define TSB_PJ_FR7_PJ7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,7))) +#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) +#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) +#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) +#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) +#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) +#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) +#define TSB_PJ_OD_PJ6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,6))) +#define TSB_PJ_OD_PJ7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,7))) +#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) +#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) +#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) +#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) +#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) +#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) +#define TSB_PJ_PUP_PJ6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,6))) +#define TSB_PJ_PUP_PJ7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,7))) +#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) +#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) +#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) +#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) +#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) +#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) +#define TSB_PJ_PDN_PJ6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,6))) +#define TSB_PJ_PDN_PJ7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,7))) +#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) +#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) +#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) +#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) +#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) +#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) +#define TSB_PJ_IE_PJ6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,6))) +#define TSB_PJ_IE_PJ7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,7))) + + +/* Port K */ +#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) +#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) +#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) +#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) +#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) +#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) +#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) +#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) +#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) +#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) +#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) +#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) +#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) +#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) +#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) +#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) +#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) +#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) +#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) +#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) +#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) +#define TSB_PK_FR1_PK5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,5))) +#define TSB_PK_FR1_PK6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,6))) +#define TSB_PK_FR2_PK0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,0))) +#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) +#define TSB_PK_FR2_PK6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,6))) +#define TSB_PK_FR2_PK7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,7))) +#define TSB_PK_FR3_PK0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,0))) +#define TSB_PK_FR3_PK1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,1))) +#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) +#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) +#define TSB_PK_FR4_PK1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,1))) +#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) +#define TSB_PK_FR4_PK5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,5))) +#define TSB_PK_FR4_PK6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,6))) +#define TSB_PK_FR4_PK7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,7))) +#define TSB_PK_FR5_PK1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,1))) +#define TSB_PK_FR6_PK0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,0))) +#define TSB_PK_FR6_PK1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,1))) +#define TSB_PK_FR6_PK2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,2))) +#define TSB_PK_FR6_PK3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,3))) +#define TSB_PK_FR6_PK4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,4))) +#define TSB_PK_FR6_PK5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,5))) +#define TSB_PK_FR6_PK6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,6))) +#define TSB_PK_FR6_PK7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,7))) +#define TSB_PK_FR7_PK7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR7,7))) +#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) +#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) +#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) +#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) +#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) +#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) +#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) +#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) +#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) +#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) +#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) +#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) +#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) +#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) +#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) +#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) +#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) +#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) +#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) +#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) +#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) +#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) +#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) +#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) +#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) +#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) +#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) +#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) +#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) +#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) +#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) +#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) + + +/* Port L */ +#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) +#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) +#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) +#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) +#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) +#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) +#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) +#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) +#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) +#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) +#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) +#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) +#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) +#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) +#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) +#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) +#define TSB_PL_FR1_PL7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,7))) +#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) +#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) +#define TSB_PL_FR2_PL4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,4))) +#define TSB_PL_FR2_PL5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,5))) +#define TSB_PL_FR2_PL6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,6))) +#define TSB_PL_FR2_PL7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,7))) +#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) +#define TSB_PL_FR3_PL3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3))) +#define TSB_PL_FR3_PL4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,4))) +#define TSB_PL_FR3_PL6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,6))) +#define TSB_PL_FR5_PL0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,0))) +#define TSB_PL_FR5_PL1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,1))) +#define TSB_PL_FR5_PL2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,2))) +#define TSB_PL_FR5_PL3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,3))) +#define TSB_PL_FR6_PL0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,0))) +#define TSB_PL_FR6_PL3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,3))) +#define TSB_PL_FR7_PL0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,0))) +#define TSB_PL_FR7_PL1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,1))) +#define TSB_PL_FR7_PL2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,2))) +#define TSB_PL_FR7_PL3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,3))) +#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) +#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) +#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) +#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) +#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) +#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) +#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) +#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) +#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) +#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) +#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) +#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) +#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) +#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) +#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) +#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) +#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) +#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) +#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) +#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) +#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) +#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) +#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) +#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) +#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) +#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) +#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) +#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) +#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) +#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) +#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) +#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) + + +/* Port M */ +#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) +#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) +#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) +#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) +#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) +#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) +#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) +#define TSB_PM_DATA_PM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,7))) +#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) +#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) +#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) +#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) +#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) +#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) +#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) +#define TSB_PM_CR_PM7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,7))) +#define TSB_PM_FR1_PM0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,0))) +#define TSB_PM_FR1_PM1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,1))) +#define TSB_PM_FR1_PM6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,6))) +#define TSB_PM_FR1_PM7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,7))) +#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) +#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) +#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) +#define TSB_PM_FR2_PM5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,5))) +#define TSB_PM_FR2_PM6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,6))) +#define TSB_PM_FR2_PM7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,7))) +#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) +#define TSB_PM_FR3_PM5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,5))) +#define TSB_PM_FR3_PM6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,6))) +#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) +#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) +#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) +#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) +#define TSB_PM_FR4_PM6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,6))) +#define TSB_PM_FR4_PM7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,7))) +#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) +#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) +#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) +#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) +#define TSB_PM_FR5_PM6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,6))) +#define TSB_PM_FR5_PM7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,7))) +#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) +#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) +#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) +#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) +#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) +#define TSB_PM_FR6_PM5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,5))) +#define TSB_PM_FR6_PM6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,6))) +#define TSB_PM_FR6_PM7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,7))) +#define TSB_PM_FR7_PM0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,0))) +#define TSB_PM_FR7_PM1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,1))) +#define TSB_PM_FR7_PM2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,2))) +#define TSB_PM_FR7_PM3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,3))) +#define TSB_PM_FR7_PM4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,4))) +#define TSB_PM_FR7_PM5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,5))) +#define TSB_PM_FR7_PM6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,6))) +#define TSB_PM_FR7_PM7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,7))) +#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) +#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) +#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) +#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) +#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) +#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) +#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) +#define TSB_PM_OD_PM7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,7))) +#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) +#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) +#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) +#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) +#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) +#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) +#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) +#define TSB_PM_PUP_PM7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,7))) +#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) +#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) +#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) +#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) +#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) +#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) +#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) +#define TSB_PM_PDN_PM7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,7))) +#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) +#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) +#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) +#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) +#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) +#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) +#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) +#define TSB_PM_IE_PM7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,7))) + + +/* Port N */ +#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) +#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) +#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) +#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) +#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) +#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) +#define TSB_PN_DATA_PN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,6))) +#define TSB_PN_DATA_PN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,7))) +#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) +#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) +#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) +#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) +#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) +#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) +#define TSB_PN_CR_PN6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,6))) +#define TSB_PN_CR_PN7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,7))) +#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) +#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) +#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) +#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) +#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) +#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) +#define TSB_PN_OD_PN6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,6))) +#define TSB_PN_OD_PN7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,7))) +#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) +#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) +#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) +#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) +#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) +#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) +#define TSB_PN_PUP_PN6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,6))) +#define TSB_PN_PUP_PN7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,7))) +#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) +#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) +#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) +#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) +#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) +#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) +#define TSB_PN_PDN_PN6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,6))) +#define TSB_PN_PDN_PN7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,7))) +#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) +#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) +#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) +#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) +#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) +#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) +#define TSB_PN_IE_PN6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,6))) +#define TSB_PN_IE_PN7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,7))) + + +/* Port P */ +#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) +#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) +#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) +#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) +#define TSB_PP_DATA_PP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,4))) +#define TSB_PP_DATA_PP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,5))) +#define TSB_PP_DATA_PP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,6))) +#define TSB_PP_DATA_PP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,7))) +#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) +#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) +#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) +#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) +#define TSB_PP_CR_PP4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,4))) +#define TSB_PP_CR_PP5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,5))) +#define TSB_PP_CR_PP6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,6))) +#define TSB_PP_CR_PP7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,7))) +#define TSB_PP_FR2_PP0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,0))) +#define TSB_PP_FR2_PP1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,1))) +#define TSB_PP_FR2_PP2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,2))) +#define TSB_PP_FR2_PP3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,3))) +#define TSB_PP_FR2_PP4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,4))) +#define TSB_PP_FR2_PP5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,5))) +#define TSB_PP_FR2_PP6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,6))) +#define TSB_PP_FR2_PP7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,7))) +#define TSB_PP_FR3_PP0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) +#define TSB_PP_FR3_PP1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) +#define TSB_PP_FR3_PP2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) +#define TSB_PP_FR3_PP3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,3))) +#define TSB_PP_FR3_PP4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,4))) +#define TSB_PP_FR3_PP5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,5))) +#define TSB_PP_FR3_PP6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,6))) +#define TSB_PP_FR3_PP7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,7))) +#define TSB_PP_FR5_PP0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,0))) +#define TSB_PP_FR5_PP1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,1))) +#define TSB_PP_FR5_PP2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,2))) +#define TSB_PP_FR5_PP3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,3))) +#define TSB_PP_FR5_PP4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,4))) +#define TSB_PP_FR5_PP5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,5))) +#define TSB_PP_FR5_PP6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,6))) +#define TSB_PP_FR5_PP7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,7))) +#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) +#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) +#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) +#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) +#define TSB_PP_OD_PP4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,4))) +#define TSB_PP_OD_PP5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,5))) +#define TSB_PP_OD_PP6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,6))) +#define TSB_PP_OD_PP7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,7))) +#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) +#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) +#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) +#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) +#define TSB_PP_PUP_PP4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,4))) +#define TSB_PP_PUP_PP5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,5))) +#define TSB_PP_PUP_PP6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,6))) +#define TSB_PP_PUP_PP7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,7))) +#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) +#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) +#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) +#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) +#define TSB_PP_PDN_PP4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,4))) +#define TSB_PP_PDN_PP5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,5))) +#define TSB_PP_PDN_PP6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,6))) +#define TSB_PP_PDN_PP7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,7))) +#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) +#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) +#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) +#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) +#define TSB_PP_IE_PP4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,4))) +#define TSB_PP_IE_PP5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,5))) +#define TSB_PP_IE_PP6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,6))) +#define TSB_PP_IE_PP7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,7))) + + +/* Port R */ +#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) +#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) +#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) +#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) +#define TSB_PR_DATA_PR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,4))) +#define TSB_PR_DATA_PR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,5))) +#define TSB_PR_DATA_PR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,6))) +#define TSB_PR_DATA_PR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,7))) +#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) +#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) +#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) +#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) +#define TSB_PR_CR_PR4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,4))) +#define TSB_PR_CR_PR5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,5))) +#define TSB_PR_CR_PR6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,6))) +#define TSB_PR_CR_PR7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,7))) +#define TSB_PR_FR2_PR0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,0))) +#define TSB_PR_FR2_PR1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,1))) +#define TSB_PR_FR2_PR2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,2))) +#define TSB_PR_FR2_PR3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,3))) +#define TSB_PR_FR2_PR4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,4))) +#define TSB_PR_FR2_PR5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,5))) +#define TSB_PR_FR2_PR6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,6))) +#define TSB_PR_FR2_PR7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,7))) +#define TSB_PR_FR3_PR0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) +#define TSB_PR_FR3_PR1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) +#define TSB_PR_FR3_PR2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) +#define TSB_PR_FR3_PR3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,3))) +#define TSB_PR_FR3_PR4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,4))) +#define TSB_PR_FR3_PR5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,5))) +#define TSB_PR_FR3_PR6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,6))) +#define TSB_PR_FR3_PR7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,7))) +#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) +#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) +#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) +#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) +#define TSB_PR_OD_PR4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,4))) +#define TSB_PR_OD_PR5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,5))) +#define TSB_PR_OD_PR6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,6))) +#define TSB_PR_OD_PR7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,7))) +#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) +#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) +#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) +#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) +#define TSB_PR_PUP_PR4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,4))) +#define TSB_PR_PUP_PR5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,5))) +#define TSB_PR_PUP_PR6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,6))) +#define TSB_PR_PUP_PR7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,7))) +#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) +#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) +#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) +#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) +#define TSB_PR_PDN_PR4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,4))) +#define TSB_PR_PDN_PR5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,5))) +#define TSB_PR_PDN_PR6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,6))) +#define TSB_PR_PDN_PR7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,7))) +#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) +#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) +#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) +#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) +#define TSB_PR_IE_PR4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,4))) +#define TSB_PR_IE_PR5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,5))) +#define TSB_PR_IE_PR6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,6))) +#define TSB_PR_IE_PR7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,7))) + + +/* Port T */ +#define TSB_PT_DATA_PT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,0))) +#define TSB_PT_DATA_PT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,1))) +#define TSB_PT_DATA_PT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,2))) +#define TSB_PT_DATA_PT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,3))) +#define TSB_PT_DATA_PT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,4))) +#define TSB_PT_DATA_PT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,5))) +#define TSB_PT_CR_PT0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,0))) +#define TSB_PT_CR_PT1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,1))) +#define TSB_PT_CR_PT2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,2))) +#define TSB_PT_CR_PT3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,3))) +#define TSB_PT_CR_PT4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,4))) +#define TSB_PT_CR_PT5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,5))) +#define TSB_PT_FR1_PT3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,3))) +#define TSB_PT_FR2_PT3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,3))) +#define TSB_PT_FR2_PT5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,5))) +#define TSB_PT_FR3_PT3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,3))) +#define TSB_PT_FR6_PT3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR6,3))) +#define TSB_PT_FR7_PT2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR7,2))) +#define TSB_PT_OD_PT0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,0))) +#define TSB_PT_OD_PT1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,1))) +#define TSB_PT_OD_PT2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,2))) +#define TSB_PT_OD_PT3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,3))) +#define TSB_PT_OD_PT4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,4))) +#define TSB_PT_OD_PT5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,5))) +#define TSB_PT_PUP_PT0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,0))) +#define TSB_PT_PUP_PT1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,1))) +#define TSB_PT_PUP_PT2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,2))) +#define TSB_PT_PUP_PT3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,3))) +#define TSB_PT_PUP_PT4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,4))) +#define TSB_PT_PUP_PT5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,5))) +#define TSB_PT_PDN_PT0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,0))) +#define TSB_PT_PDN_PT1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,1))) +#define TSB_PT_PDN_PT2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,2))) +#define TSB_PT_PDN_PT3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,3))) +#define TSB_PT_PDN_PT4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,4))) +#define TSB_PT_PDN_PT5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,5))) +#define TSB_PT_IE_PT0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,0))) +#define TSB_PT_IE_PT1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,1))) +#define TSB_PT_IE_PT2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,2))) +#define TSB_PT_IE_PT3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,3))) +#define TSB_PT_IE_PT4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,4))) +#define TSB_PT_IE_PT5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,5))) + + +/* Port U */ +#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) +#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1))) +#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) +#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) +#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) +#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) +#define TSB_PU_DATA_PU6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,6))) +#define TSB_PU_DATA_PU7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,7))) +#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) +#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1))) +#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) +#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) +#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) +#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) +#define TSB_PU_CR_PU6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,6))) +#define TSB_PU_CR_PU7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,7))) +#define TSB_PU_FR2_PU0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,0))) +#define TSB_PU_FR2_PU1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,1))) +#define TSB_PU_FR2_PU2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,2))) +#define TSB_PU_FR2_PU3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,3))) +#define TSB_PU_FR2_PU4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,4))) +#define TSB_PU_FR2_PU5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,5))) +#define TSB_PU_FR2_PU6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,6))) +#define TSB_PU_FR2_PU7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,7))) +#define TSB_PU_FR3_PU0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,0))) +#define TSB_PU_FR3_PU2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,2))) +#define TSB_PU_FR3_PU3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,3))) +#define TSB_PU_FR3_PU4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,4))) +#define TSB_PU_FR3_PU5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,5))) +#define TSB_PU_FR3_PU6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,6))) +#define TSB_PU_FR6_PU2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,2))) +#define TSB_PU_FR6_PU3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,3))) +#define TSB_PU_FR6_PU4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,4))) +#define TSB_PU_FR6_PU5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,5))) +#define TSB_PU_FR6_PU6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,6))) +#define TSB_PU_FR6_PU7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,7))) +#define TSB_PU_FR7_PU0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,0))) +#define TSB_PU_FR7_PU1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,1))) +#define TSB_PU_FR7_PU2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,2))) +#define TSB_PU_FR7_PU3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,3))) +#define TSB_PU_FR7_PU4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,4))) +#define TSB_PU_FR7_PU5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,5))) +#define TSB_PU_FR7_PU6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,6))) +#define TSB_PU_FR7_PU7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,7))) +#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) +#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1))) +#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) +#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) +#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) +#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) +#define TSB_PU_OD_PU6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,6))) +#define TSB_PU_OD_PU7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,7))) +#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) +#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1))) +#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) +#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) +#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) +#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) +#define TSB_PU_PUP_PU6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,6))) +#define TSB_PU_PUP_PU7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,7))) +#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) +#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1))) +#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) +#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) +#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) +#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) +#define TSB_PU_PDN_PU6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,6))) +#define TSB_PU_PDN_PU7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,7))) +#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) +#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1))) +#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) +#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) +#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) +#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) +#define TSB_PU_IE_PU6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,6))) +#define TSB_PU_IE_PU7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,7))) + + +/* Port V */ +#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) +#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) +#define TSB_PV_DATA_PV2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,2))) +#define TSB_PV_DATA_PV3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,3))) +#define TSB_PV_DATA_PV4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,4))) +#define TSB_PV_DATA_PV5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,5))) +#define TSB_PV_DATA_PV6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,6))) +#define TSB_PV_DATA_PV7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,7))) +#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) +#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) +#define TSB_PV_CR_PV2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,2))) +#define TSB_PV_CR_PV3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,3))) +#define TSB_PV_CR_PV4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,4))) +#define TSB_PV_CR_PV5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,5))) +#define TSB_PV_CR_PV6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,6))) +#define TSB_PV_CR_PV7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,7))) +#define TSB_PV_FR1_PV4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,4))) +#define TSB_PV_FR1_PV5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,5))) +#define TSB_PV_FR2_PV0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,0))) +#define TSB_PV_FR2_PV1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,1))) +#define TSB_PV_FR2_PV2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,2))) +#define TSB_PV_FR2_PV3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,3))) +#define TSB_PV_FR2_PV4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,4))) +#define TSB_PV_FR2_PV5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,5))) +#define TSB_PV_FR2_PV6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,6))) +#define TSB_PV_FR2_PV7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,7))) +#define TSB_PV_FR3_PV0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,0))) +#define TSB_PV_FR3_PV1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,1))) +#define TSB_PV_FR3_PV2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,2))) +#define TSB_PV_FR3_PV5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,5))) +#define TSB_PV_FR3_PV6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,6))) +#define TSB_PV_FR4_PV4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,4))) +#define TSB_PV_FR4_PV5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,5))) +#define TSB_PV_FR4_PV6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,6))) +#define TSB_PV_FR4_PV7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,7))) +#define TSB_PV_FR5_PV0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,0))) +#define TSB_PV_FR5_PV1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,1))) +#define TSB_PV_FR5_PV2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,2))) +#define TSB_PV_FR5_PV3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,3))) +#define TSB_PV_FR5_PV4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,4))) +#define TSB_PV_FR5_PV5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,5))) +#define TSB_PV_FR5_PV6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,6))) +#define TSB_PV_FR5_PV7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,7))) +#define TSB_PV_FR6_PV0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,0))) +#define TSB_PV_FR6_PV1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,1))) +#define TSB_PV_FR6_PV2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,2))) +#define TSB_PV_FR6_PV3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,3))) +#define TSB_PV_FR6_PV4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,4))) +#define TSB_PV_FR6_PV5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,5))) +#define TSB_PV_FR6_PV7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,7))) +#define TSB_PV_FR7_PV0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,0))) +#define TSB_PV_FR7_PV1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,1))) +#define TSB_PV_FR7_PV2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,2))) +#define TSB_PV_FR7_PV3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,3))) +#define TSB_PV_FR7_PV4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,4))) +#define TSB_PV_FR7_PV5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,5))) +#define TSB_PV_FR7_PV6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,6))) +#define TSB_PV_FR7_PV7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,7))) +#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) +#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) +#define TSB_PV_OD_PV2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,2))) +#define TSB_PV_OD_PV3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,3))) +#define TSB_PV_OD_PV4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,4))) +#define TSB_PV_OD_PV5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,5))) +#define TSB_PV_OD_PV6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,6))) +#define TSB_PV_OD_PV7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,7))) +#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) +#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) +#define TSB_PV_PUP_PV2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,2))) +#define TSB_PV_PUP_PV3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,3))) +#define TSB_PV_PUP_PV4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,4))) +#define TSB_PV_PUP_PV5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,5))) +#define TSB_PV_PUP_PV6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,6))) +#define TSB_PV_PUP_PV7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,7))) +#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) +#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) +#define TSB_PV_PDN_PV2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,2))) +#define TSB_PV_PDN_PV3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,3))) +#define TSB_PV_PDN_PV4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,4))) +#define TSB_PV_PDN_PV5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,5))) +#define TSB_PV_PDN_PV6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,6))) +#define TSB_PV_PDN_PV7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,7))) +#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) +#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) +#define TSB_PV_IE_PV2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,2))) +#define TSB_PV_IE_PV3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,3))) +#define TSB_PV_IE_PV4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,4))) +#define TSB_PV_IE_PV5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,5))) +#define TSB_PV_IE_PV6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,6))) +#define TSB_PV_IE_PV7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,7))) + + +/* Port W */ +#define TSB_PW_DATA_PW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,0))) +#define TSB_PW_DATA_PW1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,1))) +#define TSB_PW_DATA_PW2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,2))) +#define TSB_PW_DATA_PW3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,3))) +#define TSB_PW_DATA_PW4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,4))) +#define TSB_PW_DATA_PW5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,5))) +#define TSB_PW_DATA_PW6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,6))) +#define TSB_PW_DATA_PW7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,7))) +#define TSB_PW_CR_PW0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,0))) +#define TSB_PW_CR_PW1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,1))) +#define TSB_PW_CR_PW2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,2))) +#define TSB_PW_CR_PW3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,3))) +#define TSB_PW_CR_PW4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,4))) +#define TSB_PW_CR_PW5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,5))) +#define TSB_PW_CR_PW6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,6))) +#define TSB_PW_CR_PW7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,7))) +#define TSB_PW_FR3_PW4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,4))) +#define TSB_PW_FR3_PW7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,7))) +#define TSB_PW_FR4_PW0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,0))) +#define TSB_PW_FR4_PW1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,1))) +#define TSB_PW_FR4_PW2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,2))) +#define TSB_PW_FR4_PW3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,3))) +#define TSB_PW_FR5_PW0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,0))) +#define TSB_PW_FR5_PW1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,1))) +#define TSB_PW_FR5_PW2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,2))) +#define TSB_PW_FR5_PW3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,3))) +#define TSB_PW_FR5_PW4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,4))) +#define TSB_PW_FR5_PW5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,5))) +#define TSB_PW_FR5_PW6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,6))) +#define TSB_PW_FR5_PW7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,7))) +#define TSB_PW_FR6_PW0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR6,0))) +#define TSB_PW_FR7_PW1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,1))) +#define TSB_PW_FR7_PW2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,2))) +#define TSB_PW_FR7_PW4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,4))) +#define TSB_PW_FR7_PW5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,5))) +#define TSB_PW_FR7_PW6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,6))) +#define TSB_PW_FR7_PW7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,7))) +#define TSB_PW_OD_PW0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,0))) +#define TSB_PW_OD_PW1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,1))) +#define TSB_PW_OD_PW2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,2))) +#define TSB_PW_OD_PW3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,3))) +#define TSB_PW_OD_PW4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,4))) +#define TSB_PW_OD_PW5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,5))) +#define TSB_PW_OD_PW6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,6))) +#define TSB_PW_OD_PW7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,7))) +#define TSB_PW_PUP_PW0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,0))) +#define TSB_PW_PUP_PW1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,1))) +#define TSB_PW_PUP_PW2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,2))) +#define TSB_PW_PUP_PW3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,3))) +#define TSB_PW_PUP_PW4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,4))) +#define TSB_PW_PUP_PW5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,5))) +#define TSB_PW_PUP_PW6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,6))) +#define TSB_PW_PUP_PW7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,7))) +#define TSB_PW_PDN_PW0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,0))) +#define TSB_PW_PDN_PW1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,1))) +#define TSB_PW_PDN_PW2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,2))) +#define TSB_PW_PDN_PW3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,3))) +#define TSB_PW_PDN_PW4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,4))) +#define TSB_PW_PDN_PW5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,5))) +#define TSB_PW_PDN_PW6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,6))) +#define TSB_PW_PDN_PW7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,7))) +#define TSB_PW_IE_PW0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,0))) +#define TSB_PW_IE_PW1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,1))) +#define TSB_PW_IE_PW2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,2))) +#define TSB_PW_IE_PW3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,3))) +#define TSB_PW_IE_PW4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,4))) +#define TSB_PW_IE_PW5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,5))) +#define TSB_PW_IE_PW6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,6))) +#define TSB_PW_IE_PW7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,7))) + + +/* Port Y */ +#define TSB_PY_DATA_PY0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,0))) +#define TSB_PY_DATA_PY1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,1))) +#define TSB_PY_DATA_PY2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,2))) +#define TSB_PY_DATA_PY3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,3))) +#define TSB_PY_DATA_PY4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,4))) +#define TSB_PY_CR_PY4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->CR,4))) +#define TSB_PY_FR1_PY4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR1,4))) +#define TSB_PY_FR4_PY4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR4,4))) +#define TSB_PY_OD_PY4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->OD,4))) +#define TSB_PY_PUP_PY0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,0))) +#define TSB_PY_PUP_PY1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,1))) +#define TSB_PY_PUP_PY2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,2))) +#define TSB_PY_PUP_PY3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,3))) +#define TSB_PY_PUP_PY4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,4))) +#define TSB_PY_PDN_PY0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,0))) +#define TSB_PY_PDN_PY1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,1))) +#define TSB_PY_PDN_PY2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,2))) +#define TSB_PY_PDN_PY3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,3))) +#define TSB_PY_PDN_PY4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,4))) +#define TSB_PY_IE_PY0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,0))) +#define TSB_PY_IE_PY1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,1))) +#define TSB_PY_IE_PY2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,2))) +#define TSB_PY_IE_PY3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,3))) + + +/* Internal High-speed Oscillation Adjustment */ +#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) + + +/* Oscillation Frequency Detector (OFD) */ +#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) +#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) +#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) +#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) + + + +/* Consumer Electronics Control (CEC) */ +#define TSB_CEC0_EN_CECEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->EN,0))) +#define TSB_CEC0_RESET_CECRESET (*((__O uint32_t *)BITBAND_PERI(&TSB_CEC0->RESET,0))) +#define TSB_CEC0_REN_CECREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->REN,0))) +#define TSB_CEC0_RBUF_CECEOM (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,8))) +#define TSB_CEC0_RBUF_CECACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,9))) +#define TSB_CEC0_RCR1_CECOTH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,0))) +#define TSB_CEC0_RCR1_CECRIHLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,1))) +#define TSB_CEC0_RCR1_CECACKDIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,24))) +#define TSB_CEC0_RCR3_CECWAVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,0))) +#define TSB_CEC0_RCR3_CECRSTAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,1))) +#define TSB_CEC0_TEN_CECTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,0))) +#define TSB_CEC0_TEN_CECTRANS (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,1))) +#define TSB_CEC0_TBUF_CECTEOM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TBUF,8))) +#define TSB_CEC0_TCR_CECBRD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TCR,4))) +#define TSB_CEC0_RSTAT_CECRIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,0))) +#define TSB_CEC0_RSTAT_CECRISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,1))) +#define TSB_CEC0_RSTAT_CECRIMAX (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,2))) +#define TSB_CEC0_RSTAT_CECRIMIN (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,3))) +#define TSB_CEC0_RSTAT_CECRIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,4))) +#define TSB_CEC0_RSTAT_CECRIOR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,5))) +#define TSB_CEC0_RSTAT_CECRIWAV (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,6))) +#define TSB_CEC0_TSTAT_CECTISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,0))) +#define TSB_CEC0_TSTAT_CECTIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,1))) +#define TSB_CEC0_TSTAT_CECTIAL (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,2))) +#define TSB_CEC0_TSTAT_CECTIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,3))) +#define TSB_CEC0_TSTAT_CECTIUR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,4))) +#define TSB_CEC0_FSSEL_CECCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->FSSEL,0))) + + +/* Remote Control Signal Preprocessor (RMC) */ +#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) +#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) +#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) +#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) +#define TSB_RMC0_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,29))) +#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) +#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) +#define TSB_RMC0_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR3,15))) +#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) +#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) +#define TSB_RMC0_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,8))) +#define TSB_RMC0_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,11))) +#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) +#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) +#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) +#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) +#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) + +#define TSB_RMC1_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->EN,0))) +#define TSB_RMC1_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->REN,0))) +#define TSB_RMC1_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,24))) +#define TSB_RMC1_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,25))) +#define TSB_RMC1_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,29))) +#define TSB_RMC1_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,30))) +#define TSB_RMC1_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,31))) +#define TSB_RMC1_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR3,15))) +#define TSB_RMC1_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR4,7))) +#define TSB_RMC1_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,7))) +#define TSB_RMC1_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,8))) +#define TSB_RMC1_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,11))) +#define TSB_RMC1_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,12))) +#define TSB_RMC1_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,13))) +#define TSB_RMC1_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,14))) +#define TSB_RMC1_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,15))) +#define TSB_RMC1_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->FSSEL,0))) + + +/* */ +#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) +#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) +#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) +#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) +#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) +#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) +#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) +#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) +#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) +#define TSB_PMD0_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,0))) +#define TSB_PMD0_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,1))) +#define TSB_PMD0_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,2))) +#define TSB_PMD0_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,3))) +#define TSB_PMD0_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,7))) +#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) +#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) +#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) +#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) +#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) +#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) +#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) +#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) +#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) +#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) +#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) +#define TSB_PMD0_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,14))) +#define TSB_PMD0_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,15))) +#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) +#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) +#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) +#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) +#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) +#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) +#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) +#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) +#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) +#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) +#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) +#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) +#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) +#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) +#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) +#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) +#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) +#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) +#define TSB_PMD0_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->SYNCCR,0))) + + +/* */ +#define TSB_ISDA_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->EN,0))) +#define TSB_ISDA_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,0))) +#define TSB_ISDA_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,1))) +#define TSB_ISDA_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->OCR0,0))) +#define TSB_ISDA_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CR,0))) +#define TSB_ISDA_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,0))) +#define TSB_ISDA_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,1))) +#define TSB_ISDA_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,2))) +#define TSB_ISDA_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,3))) +#define TSB_ISDA_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,0))) +#define TSB_ISDA_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,1))) +#define TSB_ISDA_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,2))) +#define TSB_ISDA_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,3))) +#define TSB_ISDA_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->INTCR,0))) + +#define TSB_ISDB_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->EN,0))) +#define TSB_ISDB_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,0))) +#define TSB_ISDB_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,1))) +#define TSB_ISDB_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->OCR0,0))) +#define TSB_ISDB_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CR,0))) +#define TSB_ISDB_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,0))) +#define TSB_ISDB_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,1))) +#define TSB_ISDB_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,2))) +#define TSB_ISDB_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,3))) +#define TSB_ISDB_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,0))) +#define TSB_ISDB_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,1))) +#define TSB_ISDB_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,2))) +#define TSB_ISDB_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,3))) +#define TSB_ISDB_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->INTCR,0))) + +#define TSB_ISDC_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->EN,0))) +#define TSB_ISDC_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,0))) +#define TSB_ISDC_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,1))) +#define TSB_ISDC_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->OCR0,0))) +#define TSB_ISDC_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CR,0))) +#define TSB_ISDC_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,0))) +#define TSB_ISDC_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,1))) +#define TSB_ISDC_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,2))) +#define TSB_ISDC_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,3))) +#define TSB_ISDC_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,0))) +#define TSB_ISDC_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,1))) +#define TSB_ISDC_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,2))) +#define TSB_ISDC_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,3))) +#define TSB_ISDC_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->INTCR,0))) + +/** @} */ /* End of group Device_Peripheral_registers */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TMPM4GR_H__ */ + +/** @} */ /* End of group TMPM4GR */ +/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/startup_TMPM4GR.S b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/startup_TMPM4GR.S new file mode 100644 index 00000000000..458a5a4933a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/startup_TMPM4GR.S @@ -0,0 +1,633 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM4GR.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for the +; * TOSHIBA 'TMPM4GR' Device Series +; * @version V1.0.0 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * Copyright(C) Toshiba Electronic Device Solutions Corporation 2020 +; ******************************************************************************* +; */ + + + + + + + + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt pin 00a/00b + DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b + DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b + DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b + DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b + DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b + DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b + DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b + DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b + DCD INT09_IRQHandler ; 9: Interrupt pin 09a/09b + DCD INT10_IRQHandler ; 10: Interrupt pin 10a/10b + DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b + DCD INT12_IRQHandler ; 12: Interrupt pin 12a/12b + DCD INT13_IRQHandler ; 13: Interrupt pin 13a/13b + DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b + DCD INT15_IRQHandler ; 15: Interrupt pin 15a/15b + DCD INTRTC_IRQHandler ; 16: Real time clock(XHz) interrupt + DCD INTCEC0RX_IRQHandler ; 17: CEC reception interrupt (channel 0) + DCD INTCEC0TX_IRQHandler ; 18: CEC transmission interrupt (channel 0) + DCD INTISDA_IRQHandler ; 19: Interval Sensing Detector interrupt (Unit A) + DCD INTISDB_IRQHandler ; 20: Interval Sensing Detector interrupt (Unit B) + DCD INTISDC_IRQHandler ; 21: Interval Sensing Detector interrupt (Unit C) + DCD INTRMC0_IRQHandler ; 22: Remote control reception interrupt 0 + DCD INTRMC1_IRQHandler ; 23: Remote control reception interrupt 1 + DCD INTLTTMR0_IRQHandler ; 24: Long Term Timer Interrupt(channel 0) + DCD INTHDMAATC_IRQHandler ; 25: HDMA complete of transfer(Unit A) + DCD INTHDMAAERR_IRQHandler ; 26: HDMA transfer error(Unit A) + DCD INTHDMABTC_IRQHandler ; 27: HDMA end of transfer(Unit B) + DCD INTHDMABERR_IRQHandler ; 28: HDMA transfer error(Unit B) + DCD INTMDMAATC_IRQHandler ; 29: MDMA complete of transfer(Unit A) + DCD INTT32A00_A_CT_IRQHandler ; 30: T32A00 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A00_B_C01_CPC_IRQHandler; 31: T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A01_A_CT_IRQHandler ; 32: T32A01 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A01_B_C01_CPC_IRQHandler; 33: T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A02_A_CT_IRQHandler ; 34: T32A02 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A02_B_C01_CPC_IRQHandler; 35: T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A03_A_CT_IRQHandler ; 36: T32A03 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A03_B_C01_CPC_IRQHandler; 37: T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A04_A_CT_IRQHandler ; 38: T32A04 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A04_B_C01_CPC_IRQHandler; 39: T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A05_A_CT_IRQHandler ; 40: T32A05 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A05_B_C01_CPC_IRQHandler; 41: T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A06_A_CT_IRQHandler ; 42: T32A06 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A06_B_C01_CPC_IRQHandler; 43: T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A07_A_CT_IRQHandler ; 44: T32A07 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A07_B_C01_CPC_IRQHandler; 45: T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A08_A_CT_IRQHandler ; 46: T32A08 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A08_B_C01_CPC_IRQHandler; 47: T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A09_A_CT_IRQHandler ; 48: T32A09 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A09_B_C01_CPC_IRQHandler; 49: T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A10_A_CT_IRQHandler ; 50: T32A10 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A10_B_C01_CPC_IRQHandler; 51: T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A11_A_CT_IRQHandler ; 52: T32A11 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A11_B_C01_CPC_IRQHandler; 53: T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A12_A_CT_IRQHandler ; 54: T32A12 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A12_B_C01_CPC_IRQHandler; 55: T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A13_A_CT_IRQHandler ; 56: T32A13 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A13_B_C01_CPC_IRQHandler; 57: T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTEMG0_IRQHandler ; 58: PMD0 EMG interrupt + DCD INTOVV0_IRQHandler ; 59: PMD0 OVV interrupt + DCD INTPWM0_IRQHandler ; 60: PMD0 interrupt + DCD INTT0RX_IRQHandler ; 61: TSPI/SIO reception (channel 0) interrupt + DCD INTT0TX_IRQHandler ; 62: TSPI/SIO transmit (channel 0) interrupt + DCD INTT0ERR_IRQHandler ; 63: TSPI/SIO error (channel 0) interrupt + DCD INTT1RX_IRQHandler ; 64: TSPI/SIO reception (channel 1) interrupt + DCD INTT1TX_IRQHandler ; 65: TSPI/SIO transmit (channel 1) interrupt + DCD INTT1ERR_IRQHandler ; 66: TSPI/SIO error (channel 1) interrupt + DCD INTT2RX_IRQHandler ; 67: TSPI/SIO reception (channel 2) interrupt + DCD INTT2TX_IRQHandler ; 68: TSPI/SIO transmit (channel 2) interrupt + DCD INTT2ERR_IRQHandler ; 69: TSPI/SIO error (channel 2) interrupt + DCD INTT3RX_IRQHandler ; 70: TSPI/SIO reception (channel 3) interrupt + DCD INTT3TX_IRQHandler ; 71: TSPI/SIO transmit (channel 3) interrupt + DCD INTT3ERR_IRQHandler ; 72: TSPI/SIO error (channel 3) interrupt + DCD INTT4RX_IRQHandler ; 73: TSPI/SIO reception (channel 4) interrupt + DCD INTT4TX_IRQHandler ; 74: TSPI/SIO transmit (channel 4) interrupt + DCD INTT4ERR_IRQHandler ; 75: TSPI/SIO error (channel 4) interrupt + DCD INTT5RX_IRQHandler ; 76: TSPI/SIO reception (channel 5) interrupt + DCD INTT5TX_IRQHandler ; 77: TSPI/SIO transmit (channel 5) interrupt + DCD INTT5ERR_IRQHandler ; 78: TSPI/SIO error (channel 5) interrupt + DCD INTT6RX_IRQHandler ; 79: TSPI/SIO reception (channel 6) interrupt + DCD INTT6TX_IRQHandler ; 80: TSPI/SIO transmit (channel 6) interrupt + DCD INTT6ERR_IRQHandler ; 81: TSPI/SIO error (channel 6) interrupt + DCD INTT7RX_IRQHandler ; 82: TSPI/SIO reception (channel 7) interrupt + DCD INTT7TX_IRQHandler ; 83: TSPI/SIO transmit (channel 7) interrupt + DCD INTT7ERR_IRQHandler ; 84: TSPI/SIO error (channel 7) interrupt + DCD INTT8RX_IRQHandler ; 85: TSPI/SIO reception (channel 8) interrupt + DCD INTT8TX_IRQHandler ; 86: TSPI/SIO transmit (channel 8) interrupt + DCD INTT8ERR_IRQHandler ; 87: TSPI/SIO error (channel 8) interrupt + DCD INTSMI0_IRQHandler ; 88: Serial Memory Interface interrupt + DCD INTUART0RX_IRQHandler ; 89: UART reception (channel 0) interrupt + DCD INTUART0TX_IRQHandler ; 90: UART transmit (channel 0) interrupt + DCD INTUART0ERR_IRQHandler ; 91: UART error (channel 0) interrupt + DCD INTUART1RX_IRQHandler ; 92: UART reception (channel 1) interrupt + DCD INTUART1TX_IRQHandler ; 93: UART transmit (channel 1) interrupt + DCD INTUART1ERR_IRQHandler ; 94: UART error (channel 1) interrupt + DCD INTUART2RX_IRQHandler ; 95: UART reception (channel 2) interrupt + DCD INTUART2TX_IRQHandler ; 96: UART transmit (channel 2) interrupt + DCD INTUART2ERR_IRQHandler ; 97: UART error (channel 2) interrupt + DCD INTUART3RX_IRQHandler ; 98: UART reception (channel 3) interrupt + DCD INTUART3TX_IRQHandler ; 99: UART transmit (channel 3) interrupt + DCD INTUART3ERR_IRQHandler ; 100: UART error (channel 3) interrupt + DCD INTUART4RX_IRQHandler ; 101: UART reception (channel 4) interrupt + DCD INTUART4TX_IRQHandler ; 102: UART transmit (channel 4) interrupt + DCD INTUART4ERR_IRQHandler ; 103: UART error (channel 4) interrupt + DCD INTUART5RX_IRQHandler ; 104: UART reception (channel 5) interrupt + DCD INTUART5TX_IRQHandler ; 105: UART transmit (channel 5) interrupt + DCD INTUART5ERR_IRQHandler ; 106: UART error (channel 5) interrupt + DCD INTFUART0_IRQHandler ; 107: FUART interrupt(channel 0) + DCD INTFUART1_IRQHandler ; 108: FUART interrupt(channel 1) + DCD INTI2C0NST_IRQHandler ; 109: I2C0 interrupt / EI2C0 status interrupt + DCD INTI2C0ATX_IRQHandler ; 110: I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C0BRX_IRQHandler ; 111: I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C0NA_IRQHandler ; 112: I2C0 NACK detection interrupt + DCD INTI2C1NST_IRQHandler ; 113: I2C1 interrupt / EI2C0 status interrupt + DCD INTI2C1ATX_IRQHandler ; 114: I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C1BRX_IRQHandler ; 115: I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C1NA_IRQHandler ; 116: I2C1 NACK detection interrupt + DCD INTI2C2NST_IRQHandler ; 117: I2C2 interrupt / EI2C0 status interrupt + DCD INTI2C2ATX_IRQHandler ; 118: I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C2BRX_IRQHandler ; 119: I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C2NA_IRQHandler ; 120: I2C2 NACK detection interrupt + DCD INTI2C3NST_IRQHandler ; 121: I2C3 interrupt / EI2C0 status interrupt + DCD INTI2C3ATX_IRQHandler ; 122: I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C3BRX_IRQHandler ; 123: I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C3NA_IRQHandler ; 124: I2C3 NACK detection interrupt + DCD INTI2C4NST_IRQHandler ; 125: I2C4 interrupt / EI2C0 status interrupt + DCD INTI2C4ATX_IRQHandler ; 126: I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C4BRX_IRQHandler ; 127: I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C4NA_IRQHandler ; 128: I2C4 NACK detection interrupt + DCD INTADACP0_IRQHandler ; 129: ADC conversion monitoring function interrupt 0 + DCD INTADACP1_IRQHandler ; 130: ADC conversion monitoring function interrupt 1 + DCD INTADATRG_IRQHandler ; 131: ADC conversion triggered by General purpose is finished + DCD INTADASGL_IRQHandler ; 132: ADC conversion triggered by Single program is finished + DCD INTADACNT_IRQHandler ; 133: ADC conversion triggered by Continuity program is finished + DCD INTADAHP_IRQHandler ; 134: ADC high priority AD conversion interrupt + DCD INTFLDRDY_IRQHandler ; 135: Data FLASH Ready interrupt + DCD INTFLCRDY_IRQHandler ; 136: Code FLASH Area0/1 Ready interrupt + DCD 0 ; 137: Reserved + DCD 0 ; 138: Reserved + DCD INTMDMAABERR_IRQHandler ; 139: MDMA bus error(Unit A) interrupt + DCD INTMDMAADERR_IRQHandler ; 140: MDMA descriptor error(Unit A) interrupt + DCD INTI2S0SI_IRQHandler ; 141: I2S ch0 SI transfer end interrupt + DCD INTI2S0SIERR_IRQHandler ; 142: I2S ch0 SI error interrupt + DCD INTI2S0SO_IRQHandler ; 143: I2S ch0 SO transfer end interrupt + DCD INTI2S0SOERR_IRQHandler ; 144: I2S ch0 SO error interrupt + DCD INTI2S1SI_IRQHandler ; 145: I2S ch1 SI transfer end interrupt + DCD INTI2S1SIERR_IRQHandler ; 146: I2S ch1 SI error interrupt + DCD INTI2S1SO_IRQHandler ; 147: I2S ch1 SO transfer end interrupt + DCD INTI2S1SOERR_IRQHandler ; 148: I2S ch1 SO error interrupt + DCD INTFIR0_IRQHandler ; 149: FIR ch0 interrupt + DCD INTTSSI0RX_IRQHandler ; 150: TSSI ch0 receive interrupt + DCD INTTSSI0TX_IRQHandler ; 151: TSSI ch0 transmission interrupt + DCD INTTSSI0ERR_IRQHandler ; 152: TSSI ch0 error interrupt + DCD INTTSSI1RX_IRQHandler ; 153: TSSI ch1 receive interrupt + DCD INTTSSI1TX_IRQHandler ; 154: TSSI ch1 transmission interrupt + DCD INTTSSI1ERR_IRQHandler ; 155: TSSI ch1 error interrupt + DCD 0 ; 156: Reserved + DCD 0 ; 157: Reserved + DCD 0 ; 158: Reserved + DCD 0 ; 159: Reserved + DCD 0 ; 160: Reserved + DCD 0 ; 161: Reserved + DCD 0 ; 162: Reserved + DCD 0 ; 163: Reserved + DCD 0 ; 164: Reserved + DCD 0 ; 165: Reserved + DCD 0 ; 166: Reserved + DCD 0 ; 167: Reserved + DCD INTT32A14_A_IRQHandler ; 168: T32A14 TimerA all interrupt + DCD INTT32A14_B_IRQHandler ; 169: T32A14 TimerB all interrupt + DCD INTT32A14_CT_IRQHandler ; 170: T32A14 TimerC match, overflow, and underflow Interrupt + DCD INTT32A15_A_IRQHandler ; 171: T32A15 TimerA all interrupt + DCD INTT32A15_B_IRQHandler ; 172: T32A15 TimerB all interrupt + DCD INTT32A15_C_IRQHandler ; 173: T32A15 TimerC all interrupt + DCD INTMDMAADISR_IRQHandler ; 174: MDMAC unit A Descriptor interrupt + + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT INT00_IRQHandler [WEAK] + EXPORT INT01_IRQHandler [WEAK] + EXPORT INT02_IRQHandler [WEAK] + EXPORT INT03_IRQHandler [WEAK] + EXPORT INT04_IRQHandler [WEAK] + EXPORT INT05_IRQHandler [WEAK] + EXPORT INT06_IRQHandler [WEAK] + EXPORT INT07_IRQHandler [WEAK] + EXPORT INT08_IRQHandler [WEAK] + EXPORT INT09_IRQHandler [WEAK] + EXPORT INT10_IRQHandler [WEAK] + EXPORT INT11_IRQHandler [WEAK] + EXPORT INT12_IRQHandler [WEAK] + EXPORT INT13_IRQHandler [WEAK] + EXPORT INT14_IRQHandler [WEAK] + EXPORT INT15_IRQHandler [WEAK] + EXPORT INTRTC_IRQHandler [WEAK] + EXPORT INTCEC0RX_IRQHandler [WEAK] + EXPORT INTCEC0TX_IRQHandler [WEAK] + EXPORT INTISDA_IRQHandler [WEAK] + EXPORT INTISDB_IRQHandler [WEAK] + EXPORT INTISDC_IRQHandler [WEAK] + EXPORT INTRMC0_IRQHandler [WEAK] + EXPORT INTRMC1_IRQHandler [WEAK] + EXPORT INTLTTMR0_IRQHandler [WEAK] + EXPORT INTHDMAATC_IRQHandler [WEAK] + EXPORT INTHDMAAERR_IRQHandler [WEAK] + EXPORT INTHDMABTC_IRQHandler [WEAK] + EXPORT INTHDMABERR_IRQHandler [WEAK] + EXPORT INTMDMAATC_IRQHandler [WEAK] + EXPORT INTT32A00_A_CT_IRQHandler [WEAK] + EXPORT INTT32A00_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A01_A_CT_IRQHandler [WEAK] + EXPORT INTT32A01_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A02_A_CT_IRQHandler [WEAK] + EXPORT INTT32A02_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A03_A_CT_IRQHandler [WEAK] + EXPORT INTT32A03_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A04_A_CT_IRQHandler [WEAK] + EXPORT INTT32A04_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A05_A_CT_IRQHandler [WEAK] + EXPORT INTT32A05_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A06_A_CT_IRQHandler [WEAK] + EXPORT INTT32A06_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A07_A_CT_IRQHandler [WEAK] + EXPORT INTT32A07_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A08_A_CT_IRQHandler [WEAK] + EXPORT INTT32A08_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A09_A_CT_IRQHandler [WEAK] + EXPORT INTT32A09_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A10_A_CT_IRQHandler [WEAK] + EXPORT INTT32A10_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A11_A_CT_IRQHandler [WEAK] + EXPORT INTT32A11_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A12_A_CT_IRQHandler [WEAK] + EXPORT INTT32A12_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A13_A_CT_IRQHandler [WEAK] + EXPORT INTT32A13_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTEMG0_IRQHandler [WEAK] + EXPORT INTOVV0_IRQHandler [WEAK] + EXPORT INTPWM0_IRQHandler [WEAK] + EXPORT INTT0RX_IRQHandler [WEAK] + EXPORT INTT0TX_IRQHandler [WEAK] + EXPORT INTT0ERR_IRQHandler [WEAK] + EXPORT INTT1RX_IRQHandler [WEAK] + EXPORT INTT1TX_IRQHandler [WEAK] + EXPORT INTT1ERR_IRQHandler [WEAK] + EXPORT INTT2RX_IRQHandler [WEAK] + EXPORT INTT2TX_IRQHandler [WEAK] + EXPORT INTT2ERR_IRQHandler [WEAK] + EXPORT INTT3RX_IRQHandler [WEAK] + EXPORT INTT3TX_IRQHandler [WEAK] + EXPORT INTT3ERR_IRQHandler [WEAK] + EXPORT INTT4RX_IRQHandler [WEAK] + EXPORT INTT4TX_IRQHandler [WEAK] + EXPORT INTT4ERR_IRQHandler [WEAK] + EXPORT INTT5RX_IRQHandler [WEAK] + EXPORT INTT5TX_IRQHandler [WEAK] + EXPORT INTT5ERR_IRQHandler [WEAK] + EXPORT INTT6RX_IRQHandler [WEAK] + EXPORT INTT6TX_IRQHandler [WEAK] + EXPORT INTT6ERR_IRQHandler [WEAK] + EXPORT INTT7RX_IRQHandler [WEAK] + EXPORT INTT7TX_IRQHandler [WEAK] + EXPORT INTT7ERR_IRQHandler [WEAK] + EXPORT INTT8RX_IRQHandler [WEAK] + EXPORT INTT8TX_IRQHandler [WEAK] + EXPORT INTT8ERR_IRQHandler [WEAK] + EXPORT INTSMI0_IRQHandler [WEAK] + EXPORT INTUART0RX_IRQHandler [WEAK] + EXPORT INTUART0TX_IRQHandler [WEAK] + EXPORT INTUART0ERR_IRQHandler [WEAK] + EXPORT INTUART1RX_IRQHandler [WEAK] + EXPORT INTUART1TX_IRQHandler [WEAK] + EXPORT INTUART1ERR_IRQHandler [WEAK] + EXPORT INTUART2RX_IRQHandler [WEAK] + EXPORT INTUART2TX_IRQHandler [WEAK] + EXPORT INTUART2ERR_IRQHandler [WEAK] + EXPORT INTUART3RX_IRQHandler [WEAK] + EXPORT INTUART3TX_IRQHandler [WEAK] + EXPORT INTUART3ERR_IRQHandler [WEAK] + EXPORT INTUART4RX_IRQHandler [WEAK] + EXPORT INTUART4TX_IRQHandler [WEAK] + EXPORT INTUART4ERR_IRQHandler [WEAK] + EXPORT INTUART5RX_IRQHandler [WEAK] + EXPORT INTUART5TX_IRQHandler [WEAK] + EXPORT INTUART5ERR_IRQHandler [WEAK] + EXPORT INTFUART0_IRQHandler [WEAK] + EXPORT INTFUART1_IRQHandler [WEAK] + EXPORT INTI2C0NST_IRQHandler [WEAK] + EXPORT INTI2C0ATX_IRQHandler [WEAK] + EXPORT INTI2C0BRX_IRQHandler [WEAK] + EXPORT INTI2C0NA_IRQHandler [WEAK] + EXPORT INTI2C1NST_IRQHandler [WEAK] + EXPORT INTI2C1ATX_IRQHandler [WEAK] + EXPORT INTI2C1BRX_IRQHandler [WEAK] + EXPORT INTI2C1NA_IRQHandler [WEAK] + EXPORT INTI2C2NST_IRQHandler [WEAK] + EXPORT INTI2C2ATX_IRQHandler [WEAK] + EXPORT INTI2C2BRX_IRQHandler [WEAK] + EXPORT INTI2C2NA_IRQHandler [WEAK] + EXPORT INTI2C3NST_IRQHandler [WEAK] + EXPORT INTI2C3ATX_IRQHandler [WEAK] + EXPORT INTI2C3BRX_IRQHandler [WEAK] + EXPORT INTI2C3NA_IRQHandler [WEAK] + EXPORT INTI2C4NST_IRQHandler [WEAK] + EXPORT INTI2C4ATX_IRQHandler [WEAK] + EXPORT INTI2C4BRX_IRQHandler [WEAK] + EXPORT INTI2C4NA_IRQHandler [WEAK] + EXPORT INTADACP0_IRQHandler [WEAK] + EXPORT INTADACP1_IRQHandler [WEAK] + EXPORT INTADATRG_IRQHandler [WEAK] + EXPORT INTADASGL_IRQHandler [WEAK] + EXPORT INTADACNT_IRQHandler [WEAK] + EXPORT INTADAHP_IRQHandler [WEAK] + EXPORT INTFLDRDY_IRQHandler [WEAK] + EXPORT INTFLCRDY_IRQHandler [WEAK] + EXPORT INTMDMAABERR_IRQHandler [WEAK] + EXPORT INTMDMAADERR_IRQHandler [WEAK] + EXPORT INTI2S0SI_IRQHandler [WEAK] + EXPORT INTI2S0SIERR_IRQHandler [WEAK] + EXPORT INTI2S0SO_IRQHandler [WEAK] + EXPORT INTI2S0SOERR_IRQHandler [WEAK] + EXPORT INTI2S1SI_IRQHandler [WEAK] + EXPORT INTI2S1SIERR_IRQHandler [WEAK] + EXPORT INTI2S1SO_IRQHandler [WEAK] + EXPORT INTI2S1SOERR_IRQHandler [WEAK] + EXPORT INTFIR0_IRQHandler [WEAK] + EXPORT INTTSSI0RX_IRQHandler [WEAK] + EXPORT INTTSSI0TX_IRQHandler [WEAK] + EXPORT INTTSSI0ERR_IRQHandler [WEAK] + EXPORT INTTSSI1RX_IRQHandler [WEAK] + EXPORT INTTSSI1TX_IRQHandler [WEAK] + EXPORT INTTSSI1ERR_IRQHandler [WEAK] + EXPORT INTT32A14_A_IRQHandler [WEAK] + EXPORT INTT32A14_B_IRQHandler [WEAK] + EXPORT INTT32A14_CT_IRQHandler [WEAK] + EXPORT INTT32A15_A_IRQHandler [WEAK] + EXPORT INTT32A15_B_IRQHandler [WEAK] + EXPORT INTT32A15_C_IRQHandler [WEAK] + EXPORT INTMDMAADISR_IRQHandler [WEAK] + +INT00_IRQHandler +INT01_IRQHandler +INT02_IRQHandler +INT03_IRQHandler +INT04_IRQHandler +INT05_IRQHandler +INT06_IRQHandler +INT07_IRQHandler +INT08_IRQHandler +INT09_IRQHandler +INT10_IRQHandler +INT11_IRQHandler +INT12_IRQHandler +INT13_IRQHandler +INT14_IRQHandler +INT15_IRQHandler +INTRTC_IRQHandler +INTCEC0RX_IRQHandler +INTCEC0TX_IRQHandler +INTISDA_IRQHandler +INTISDB_IRQHandler +INTISDC_IRQHandler +INTRMC0_IRQHandler +INTRMC1_IRQHandler +INTLTTMR0_IRQHandler +INTHDMAATC_IRQHandler +INTHDMAAERR_IRQHandler +INTHDMABTC_IRQHandler +INTHDMABERR_IRQHandler +INTMDMAATC_IRQHandler +INTT32A00_A_CT_IRQHandler +INTT32A00_B_C01_CPC_IRQHandler +INTT32A01_A_CT_IRQHandler +INTT32A01_B_C01_CPC_IRQHandler +INTT32A02_A_CT_IRQHandler +INTT32A02_B_C01_CPC_IRQHandler +INTT32A03_A_CT_IRQHandler +INTT32A03_B_C01_CPC_IRQHandler +INTT32A04_A_CT_IRQHandler +INTT32A04_B_C01_CPC_IRQHandler +INTT32A05_A_CT_IRQHandler +INTT32A05_B_C01_CPC_IRQHandler +INTT32A06_A_CT_IRQHandler +INTT32A06_B_C01_CPC_IRQHandler +INTT32A07_A_CT_IRQHandler +INTT32A07_B_C01_CPC_IRQHandler +INTT32A08_A_CT_IRQHandler +INTT32A08_B_C01_CPC_IRQHandler +INTT32A09_A_CT_IRQHandler +INTT32A09_B_C01_CPC_IRQHandler +INTT32A10_A_CT_IRQHandler +INTT32A10_B_C01_CPC_IRQHandler +INTT32A11_A_CT_IRQHandler +INTT32A11_B_C01_CPC_IRQHandler +INTT32A12_A_CT_IRQHandler +INTT32A12_B_C01_CPC_IRQHandler +INTT32A13_A_CT_IRQHandler +INTT32A13_B_C01_CPC_IRQHandler +INTEMG0_IRQHandler +INTOVV0_IRQHandler +INTPWM0_IRQHandler +INTT0RX_IRQHandler +INTT0TX_IRQHandler +INTT0ERR_IRQHandler +INTT1RX_IRQHandler +INTT1TX_IRQHandler +INTT1ERR_IRQHandler +INTT2RX_IRQHandler +INTT2TX_IRQHandler +INTT2ERR_IRQHandler +INTT3RX_IRQHandler +INTT3TX_IRQHandler +INTT3ERR_IRQHandler +INTT4RX_IRQHandler +INTT4TX_IRQHandler +INTT4ERR_IRQHandler +INTT5RX_IRQHandler +INTT5TX_IRQHandler +INTT5ERR_IRQHandler +INTT6RX_IRQHandler +INTT6TX_IRQHandler +INTT6ERR_IRQHandler +INTT7RX_IRQHandler +INTT7TX_IRQHandler +INTT7ERR_IRQHandler +INTT8RX_IRQHandler +INTT8TX_IRQHandler +INTT8ERR_IRQHandler +INTSMI0_IRQHandler +INTUART0RX_IRQHandler +INTUART0TX_IRQHandler +INTUART0ERR_IRQHandler +INTUART1RX_IRQHandler +INTUART1TX_IRQHandler +INTUART1ERR_IRQHandler +INTUART2RX_IRQHandler +INTUART2TX_IRQHandler +INTUART2ERR_IRQHandler +INTUART3RX_IRQHandler +INTUART3TX_IRQHandler +INTUART3ERR_IRQHandler +INTUART4RX_IRQHandler +INTUART4TX_IRQHandler +INTUART4ERR_IRQHandler +INTUART5RX_IRQHandler +INTUART5TX_IRQHandler +INTUART5ERR_IRQHandler +INTFUART0_IRQHandler +INTFUART1_IRQHandler +INTI2C0NST_IRQHandler +INTI2C0ATX_IRQHandler +INTI2C0BRX_IRQHandler +INTI2C0NA_IRQHandler +INTI2C1NST_IRQHandler +INTI2C1ATX_IRQHandler +INTI2C1BRX_IRQHandler +INTI2C1NA_IRQHandler +INTI2C2NST_IRQHandler +INTI2C2ATX_IRQHandler +INTI2C2BRX_IRQHandler +INTI2C2NA_IRQHandler +INTI2C3NST_IRQHandler +INTI2C3ATX_IRQHandler +INTI2C3BRX_IRQHandler +INTI2C3NA_IRQHandler +INTI2C4NST_IRQHandler +INTI2C4ATX_IRQHandler +INTI2C4BRX_IRQHandler +INTI2C4NA_IRQHandler +INTADACP0_IRQHandler +INTADACP1_IRQHandler +INTADATRG_IRQHandler +INTADASGL_IRQHandler +INTADACNT_IRQHandler +INTADAHP_IRQHandler +INTFLDRDY_IRQHandler +INTFLCRDY_IRQHandler +INTMDMAABERR_IRQHandler +INTMDMAADERR_IRQHandler +INTI2S0SI_IRQHandler +INTI2S0SIERR_IRQHandler +INTI2S0SO_IRQHandler +INTI2S0SOERR_IRQHandler +INTI2S1SI_IRQHandler +INTI2S1SIERR_IRQHandler +INTI2S1SO_IRQHandler +INTI2S1SOERR_IRQHandler +INTFIR0_IRQHandler +INTTSSI0RX_IRQHandler +INTTSSI0TX_IRQHandler +INTTSSI0ERR_IRQHandler +INTTSSI1RX_IRQHandler +INTTSSI1TX_IRQHandler +INTTSSI1ERR_IRQHandler +INTT32A14_A_IRQHandler +INTT32A14_B_IRQHandler +INTT32A14_CT_IRQHandler +INTT32A15_A_IRQHandler +INTT32A15_B_IRQHandler +INTT32A15_C_IRQHandler +INTMDMAADISR_IRQHandler + + B . + + ENDP + + + ALIGN + + + + + + + + + + + + END + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/tmpm4grf20fg.sct b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/tmpm4grf20fg.sct new file mode 100644 index 00000000000..72f3717800e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/tmpm4grf20fg.sct @@ -0,0 +1,84 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +/* + * Copyright(C) 2019, Toshiba Electronic Device Solutions Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +;; TMPM4G9F15FG scatter file + +;; Vector table starts at 0 +;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) +;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) +;; Initial PC == &__main (with LSB set to indicate Thumb) +;; These two values are provided by the library +;; Other vectors must be provided by the user +;; Code starts after the last possible vector +;; Data starts at 0x20000000 +;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) +;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) +;; Compatible with ISSM model + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x000200000 +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +# if defined(MBED_BOOT_STACK_SIZE) +# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +# else +# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +# endif +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x40000 +#endif + + +#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE + +#define VECTOR_SIZE 0x300 + +; TMPM4GR: 2048 KB FLASH (0x200000) + 256 KB SRAM (0x40000) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region +{ + ER_IROM1 MBED_APP_START MBED_APP_SIZE + { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 MBED_RAM_START + VECTOR_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - Stack_Size) + { + txz_fc.o (+RO) + .ANY (+RW, +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -Stack_Size { ; stack + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4GR.S b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4GR.S new file mode 100644 index 00000000000..073218e45d2 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4GR.S @@ -0,0 +1,586 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM4GR.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for the +; * TOSHIBA 'TMPM4GR' Device Series +; * @version V1.0.0 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * Copyright(C) Toshiba Electronic Device Solutions Corporation 2020 +; ******************************************************************************* +; */ +.syntax unified +.arch armv7-m + +.section .stack +.align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.if Heap_Size +.space Heap_Size +.endif +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long INT00_IRQHandler // 0: Interrupt pin 00a/00b + .long INT01_IRQHandler // 1: Interrupt pin 01a/00b + .long INT02_IRQHandler // 2: Interrupt pin 02a/00b + .long INT03_IRQHandler // 3: Interrupt pin 03a/03b + .long INT04_IRQHandler // 4: Interrupt pin 04a/04b + .long INT05_IRQHandler // 5: Interrupt pin 05a/05b + .long INT06_IRQHandler // 6: Interrupt pin 06a/06b + .long INT07_IRQHandler // 7: Interrupt pin 07a/07b + .long INT08_IRQHandler // 8: Interrupt pin 08a/08b + .long INT09_IRQHandler // 9: Interrupt pin 09a/09b + .long INT10_IRQHandler // 10: Interrupt pin 10a/10b + .long INT11_IRQHandler // 11: Interrupt pin 11a/11b + .long INT12_IRQHandler // 12: Interrupt pin 12a/12b + .long INT13_IRQHandler // 13: Interrupt pin 13a/13b + .long INT14_IRQHandler // 14: Interrupt pin 14a/14b + .long INT15_IRQHandler // 15: Interrupt pin 15a/15b + .long INTRTC_IRQHandler // 16: Real time clock(XHz) interrupt + .long INTCEC0RX_IRQHandler // 17: CEC reception interrupt (channel 0) + .long INTCEC0TX_IRQHandler // 18: CEC transmission interrupt (channel 0) + .long INTISDA_IRQHandler // 19: Interval Sensing Detector interrupt (Unit A) + .long INTISDB_IRQHandler // 20: Interval Sensing Detector interrupt (Unit B) + .long INTISDC_IRQHandler // 21: Interval Sensing Detector interrupt (Unit C) + .long INTRMC0_IRQHandler // 22: Remote control reception interrupt 0 + .long INTRMC1_IRQHandler // 23: Remote control reception interrupt 1 + .long INTLTTMR0_IRQHandler // 24: Long Term Timer Interrupt(channel 0) + .long INTHDMAATC_IRQHandler // 25: HDMA complete of transfer(Unit A) + .long INTHDMAAERR_IRQHandler // 26: HDMA transfer error(Unit A) + .long INTHDMABTC_IRQHandler // 27: HDMA end of transfer(Unit B) + .long INTHDMABERR_IRQHandler // 28: HDMA transfer error(Unit B) + .long INTMDMAATC_IRQHandler // 29: MDMA complete of transfer(Unit A) + .long INTT32A00_A_CT_IRQHandler // 30: T32A00 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A00_B_C01_CPC_IRQHandler// 31: T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A01_A_CT_IRQHandler // 32: T32A01 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A01_B_C01_CPC_IRQHandler// 33: T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A02_A_CT_IRQHandler // 34: T32A02 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A02_B_C01_CPC_IRQHandler// 35: T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A03_A_CT_IRQHandler // 36: T32A03 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A03_B_C01_CPC_IRQHandler// 37: T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A04_A_CT_IRQHandler // 38: T32A04 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A04_B_C01_CPC_IRQHandler// 39: T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A05_A_CT_IRQHandler // 40: T32A05 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A05_B_C01_CPC_IRQHandler// 41: T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A06_A_CT_IRQHandler // 42: T32A06 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A06_B_C01_CPC_IRQHandler// 43: T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A07_A_CT_IRQHandler // 44: T32A07 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A07_B_C01_CPC_IRQHandler// 45: T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A08_A_CT_IRQHandler // 46: T32A08 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A08_B_C01_CPC_IRQHandler// 47: T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A09_A_CT_IRQHandler // 48: T32A09 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A09_B_C01_CPC_IRQHandler// 49: T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A10_A_CT_IRQHandler // 50: T32A10 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A10_B_C01_CPC_IRQHandler// 51: T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A11_A_CT_IRQHandler // 52: T32A11 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A11_B_C01_CPC_IRQHandler// 53: T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A12_A_CT_IRQHandler // 54: T32A12 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A12_B_C01_CPC_IRQHandler// 55: T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A13_A_CT_IRQHandler // 56: T32A13 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A13_B_C01_CPC_IRQHandler// 57: T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTEMG0_IRQHandler // 58: PMD0 EMG interrupt + .long INTOVV0_IRQHandler // 59: PMD0 OVV interrupt + .long INTPWM0_IRQHandler // 60: PMD0 interrupt + .long INTT0RX_IRQHandler // 61: TSPI/SIO reception (channel 0) interrupt + .long INTT0TX_IRQHandler // 62: TSPI/SIO transmit (channel 0) interrupt + .long INTT0ERR_IRQHandler // 63: TSPI/SIO error (channel 0) interrupt + .long INTT1RX_IRQHandler // 64: TSPI/SIO reception (channel 1) interrupt + .long INTT1TX_IRQHandler // 65: TSPI/SIO transmit (channel 1) interrupt + .long INTT1ERR_IRQHandler // 66: TSPI/SIO error (channel 1) interrupt + .long INTT2RX_IRQHandler // 67: TSPI/SIO reception (channel 2) interrupt + .long INTT2TX_IRQHandler // 68: TSPI/SIO transmit (channel 2) interrupt + .long INTT2ERR_IRQHandler // 69: TSPI/SIO error (channel 2) interrupt + .long INTT3RX_IRQHandler // 70: TSPI/SIO reception (channel 3) interrupt + .long INTT3TX_IRQHandler // 71: TSPI/SIO transmit (channel 3) interrupt + .long INTT3ERR_IRQHandler // 72: TSPI/SIO error (channel 3) interrupt + .long INTT4RX_IRQHandler // 73: TSPI/SIO reception (channel 4) interrupt + .long INTT4TX_IRQHandler // 74: TSPI/SIO transmit (channel 4) interrupt + .long INTT4ERR_IRQHandler // 75: TSPI/SIO error (channel 4) interrupt + .long INTT5RX_IRQHandler // 76: TSPI/SIO reception (channel 5) interrupt + .long INTT5TX_IRQHandler // 77: TSPI/SIO transmit (channel 5) interrupt + .long INTT5ERR_IRQHandler // 78: TSPI/SIO error (channel 5) interrupt + .long INTT6RX_IRQHandler // 79: TSPI/SIO reception (channel 6) interrupt + .long INTT6TX_IRQHandler // 80: TSPI/SIO transmit (channel 6) interrupt + .long INTT6ERR_IRQHandler // 81: TSPI/SIO error (channel 6) interrupt + .long INTT7RX_IRQHandler // 82: TSPI/SIO reception (channel 7) interrupt + .long INTT7TX_IRQHandler // 83: TSPI/SIO transmit (channel 7) interrupt + .long INTT7ERR_IRQHandler // 84: TSPI/SIO error (channel 7) interrupt + .long INTT8RX_IRQHandler // 85: TSPI/SIO reception (channel 8) interrupt + .long INTT8TX_IRQHandler // 86: TSPI/SIO transmit (channel 8) interrupt + .long INTT8ERR_IRQHandler // 87: TSPI/SIO error (channel 8) interrupt + .long INTSMI0_IRQHandler // 88: Serial Memory Interface interrupt + .long INTUART0RX_IRQHandler // 89: UART reception (channel 0) interrupt + .long INTUART0TX_IRQHandler // 90: UART transmit (channel 0) interrupt + .long INTUART0ERR_IRQHandler // 91: UART error (channel 0) interrupt + .long INTUART1RX_IRQHandler // 92: UART reception (channel 1) interrupt + .long INTUART1TX_IRQHandler // 93: UART transmit (channel 1) interrupt + .long INTUART1ERR_IRQHandler // 94: UART error (channel 1) interrupt + .long INTUART2RX_IRQHandler // 95: UART reception (channel 2) interrupt + .long INTUART2TX_IRQHandler // 96: UART transmit (channel 2) interrupt + .long INTUART2ERR_IRQHandler // 97: UART error (channel 2) interrupt + .long INTUART3RX_IRQHandler // 98: UART reception (channel 3) interrupt + .long INTUART3TX_IRQHandler // 99: UART transmit (channel 3) interrupt + .long INTUART3ERR_IRQHandler // 100: UART error (channel 3) interrupt + .long INTUART4RX_IRQHandler // 101: UART reception (channel 4) interrupt + .long INTUART4TX_IRQHandler // 102: UART transmit (channel 4) interrupt + .long INTUART4ERR_IRQHandler // 103: UART error (channel 4) interrupt + .long INTUART5RX_IRQHandler // 104: UART reception (channel 5) interrupt + .long INTUART5TX_IRQHandler // 105: UART transmit (channel 5) interrupt + .long INTUART5ERR_IRQHandler // 106: UART error (channel 5) interrupt + .long INTFUART0_IRQHandler // 107: FUART interrupt(channel 0) + .long INTFUART1_IRQHandler // 108: FUART interrupt(channel 1) + .long INTI2C0NST_IRQHandler // 109: I2C0 interrupt / EI2C0 status interrupt + .long INTI2C0ATX_IRQHandler // 110: I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C0BRX_IRQHandler // 111: I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C0NA_IRQHandler // 112: I2C0 NACK detection interrupt + .long INTI2C1NST_IRQHandler // 113: I2C1 interrupt / EI2C0 status interrupt + .long INTI2C1ATX_IRQHandler // 114: I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C1BRX_IRQHandler // 115: I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C1NA_IRQHandler // 116: I2C1 NACK detection interrupt + .long INTI2C2NST_IRQHandler // 117: I2C2 interrupt / EI2C0 status interrupt + .long INTI2C2ATX_IRQHandler // 118: I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C2BRX_IRQHandler // 119: I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C2NA_IRQHandler // 120: I2C2 NACK detection interrupt + .long INTI2C3NST_IRQHandler // 121: I2C3 interrupt / EI2C0 status interrupt + .long INTI2C3ATX_IRQHandler // 122: I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C3BRX_IRQHandler // 123: I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C3NA_IRQHandler // 124: I2C3 NACK detection interrupt + .long INTI2C4NST_IRQHandler // 125: I2C4 interrupt / EI2C0 status interrupt + .long INTI2C4ATX_IRQHandler // 126: I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C4BRX_IRQHandler // 127: I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C4NA_IRQHandler // 128: I2C4 NACK detection interrupt + .long INTADACP0_IRQHandler // 129: ADC conversion monitoring function interrupt 0 + .long INTADACP1_IRQHandler // 130: ADC conversion monitoring function interrupt 1 + .long INTADATRG_IRQHandler // 131: ADC conversion triggered by General purpose is finished + .long INTADASGL_IRQHandler // 132: ADC conversion triggered by Single program is finished + .long INTADACNT_IRQHandler // 133: ADC conversion triggered by Continuity program is finished + .long INTADAHP_IRQHandler // 134: ADC high priority AD conversion interrupt + .long INTFLDRDY_IRQHandler // 135: Data FLASH Ready interrupt + .long INTFLCRDY_IRQHandler // 136: Code FLASH Area0/1 Ready interrupt + .long 0 // 137: Reserved + .long 0 // 138: Reserved + .long INTMDMAABERR_IRQHandler // 139: MDMA bus error(Unit A) interrupt + .long INTMDMAADERR_IRQHandler // 140: MDMA descriptor error(Unit A) interrupt + .long INTI2S0SI_IRQHandler // 141: I2S ch0 SI transfer end interrupt + .long INTI2S0SIERR_IRQHandler // 142: I2S ch0 SI error interrupt + .long INTI2S0SO_IRQHandler // 143: I2S ch0 SO transfer end interrupt + .long INTI2S0SOERR_IRQHandler // 144: I2S ch0 SO error interrupt + .long INTI2S1SI_IRQHandler // 145: I2S ch1 SI transfer end interrupt + .long INTI2S1SIERR_IRQHandler // 146: I2S ch1 SI error interrupt + .long INTI2S1SO_IRQHandler // 147: I2S ch1 SO transfer end interrupt + .long INTI2S1SOERR_IRQHandler // 148: I2S ch1 SO error interrupt + .long INTFIR0_IRQHandler // 149: FIR ch0 interrupt + .long INTTSSI0RX_IRQHandler // 150: TSSI ch0 receive interrupt + .long INTTSSI0TX_IRQHandler // 151: TSSI ch0 transmission interrupt + .long INTTSSI0ERR_IRQHandler // 152: TSSI ch0 error interrupt + .long INTTSSI1RX_IRQHandler // 153: TSSI ch1 receive interrupt + .long INTTSSI1TX_IRQHandler // 154: TSSI ch1 transmission interrupt + .long INTTSSI1ERR_IRQHandler // 155: TSSI ch1 error interrupt + .long 0 // 156: Reserved + .long 0 // 157: Reserved + .long 0 // 158: Reserved + .long 0 // 159: Reserved + .long 0 // 160: Reserved + .long 0 // 161: Reserved + .long 0 // 162: Reserved + .long 0 // 163: Reserved + .long 0 // 164: Reserved + .long 0 // 165: Reserved + .long 0 // 166: Reserved + .long 0 // 167: Reserved + .long INTT32A14_A_IRQHandler // 168: T32A14 TimerA all interrupt + .long INTT32A14_B_IRQHandler // 169: T32A14 TimerB all interrupt + .long INTT32A14_CT_IRQHandler // 170: T32A14 TimerC match, overflow, and underflow Interrupt + .long INTT32A15_A_IRQHandler // 171: T32A15 TimerA all interrupt + .long INTT32A15_B_IRQHandler // 172: T32A15 TimerB all interrupt + .long INTT32A15_C_IRQHandler // 173: T32A15 TimerC all interrupt + .long INTMDMAADISR_IRQHandler // 174: MDMAC unit A Descriptor interrupt + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler INT00_IRQHandler + def_irq_handler INT01_IRQHandler + def_irq_handler INT02_IRQHandler + def_irq_handler INT03_IRQHandler + def_irq_handler INT04_IRQHandler + def_irq_handler INT05_IRQHandler + def_irq_handler INT06_IRQHandler + def_irq_handler INT07_IRQHandler + def_irq_handler INT08_IRQHandler + def_irq_handler INT09_IRQHandler + def_irq_handler INT10_IRQHandler + def_irq_handler INT11_IRQHandler + def_irq_handler INT12_IRQHandler + def_irq_handler INT13_IRQHandler + def_irq_handler INT14_IRQHandler + def_irq_handler INT15_IRQHandler + def_irq_handler INTRTC_IRQHandler + def_irq_handler INTCEC0RX_IRQHandler + def_irq_handler INTCEC0TX_IRQHandler + def_irq_handler INTISDA_IRQHandler + def_irq_handler INTISDB_IRQHandler + def_irq_handler INTISDC_IRQHandler + def_irq_handler INTRMC0_IRQHandler + def_irq_handler INTRMC1_IRQHandler + def_irq_handler INTLTTMR0_IRQHandler + def_irq_handler INTHDMAATC_IRQHandler + def_irq_handler INTHDMAAERR_IRQHandler + def_irq_handler INTHDMABTC_IRQHandler + def_irq_handler INTHDMABERR_IRQHandler + def_irq_handler INTMDMAATC_IRQHandler + def_irq_handler INTT32A00_A_CT_IRQHandler + def_irq_handler INTT32A00_B_C01_CPC_IRQHandler + def_irq_handler INTT32A01_A_CT_IRQHandler + def_irq_handler INTT32A01_B_C01_CPC_IRQHandler + def_irq_handler INTT32A02_A_CT_IRQHandler + def_irq_handler INTT32A02_B_C01_CPC_IRQHandler + def_irq_handler INTT32A03_A_CT_IRQHandler + def_irq_handler INTT32A03_B_C01_CPC_IRQHandler + def_irq_handler INTT32A04_A_CT_IRQHandler + def_irq_handler INTT32A04_B_C01_CPC_IRQHandler + def_irq_handler INTT32A05_A_CT_IRQHandler + def_irq_handler INTT32A05_B_C01_CPC_IRQHandler + def_irq_handler INTT32A06_A_CT_IRQHandler + def_irq_handler INTT32A06_B_C01_CPC_IRQHandler + def_irq_handler INTT32A07_A_CT_IRQHandler + def_irq_handler INTT32A07_B_C01_CPC_IRQHandler + def_irq_handler INTT32A08_A_CT_IRQHandler + def_irq_handler INTT32A08_B_C01_CPC_IRQHandler + def_irq_handler INTT32A09_A_CT_IRQHandler + def_irq_handler INTT32A09_B_C01_CPC_IRQHandler + def_irq_handler INTT32A10_A_CT_IRQHandler + def_irq_handler INTT32A10_B_C01_CPC_IRQHandler + def_irq_handler INTT32A11_A_CT_IRQHandler + def_irq_handler INTT32A11_B_C01_CPC_IRQHandler + def_irq_handler INTT32A12_A_CT_IRQHandler + def_irq_handler INTT32A12_B_C01_CPC_IRQHandler + def_irq_handler INTT32A13_A_CT_IRQHandler + def_irq_handler INTT32A13_B_C01_CPC_IRQHandler + def_irq_handler INTEMG0_IRQHandler + def_irq_handler INTOVV0_IRQHandler + def_irq_handler INTPWM0_IRQHandler + def_irq_handler INTT0RX_IRQHandler + def_irq_handler INTT0TX_IRQHandler + def_irq_handler INTT0ERR_IRQHandler + def_irq_handler INTT1RX_IRQHandler + def_irq_handler INTT1TX_IRQHandler + def_irq_handler INTT1ERR_IRQHandler + def_irq_handler INTT2RX_IRQHandler + def_irq_handler INTT2TX_IRQHandler + def_irq_handler INTT2ERR_IRQHandler + def_irq_handler INTT3RX_IRQHandler + def_irq_handler INTT3TX_IRQHandler + def_irq_handler INTT3ERR_IRQHandler + def_irq_handler INTT4RX_IRQHandler + def_irq_handler INTT4TX_IRQHandler + def_irq_handler INTT4ERR_IRQHandler + def_irq_handler INTT5RX_IRQHandler + def_irq_handler INTT5TX_IRQHandler + def_irq_handler INTT5ERR_IRQHandler + def_irq_handler INTT6RX_IRQHandler + def_irq_handler INTT6TX_IRQHandler + def_irq_handler INTT6ERR_IRQHandler + def_irq_handler INTT7RX_IRQHandler + def_irq_handler INTT7TX_IRQHandler + def_irq_handler INTT7ERR_IRQHandler + def_irq_handler INTT8RX_IRQHandler + def_irq_handler INTT8TX_IRQHandler + def_irq_handler INTT8ERR_IRQHandler + def_irq_handler INTSMI0_IRQHandler + def_irq_handler INTUART0RX_IRQHandler + def_irq_handler INTUART0TX_IRQHandler + def_irq_handler INTUART0ERR_IRQHandler + def_irq_handler INTUART1RX_IRQHandler + def_irq_handler INTUART1TX_IRQHandler + def_irq_handler INTUART1ERR_IRQHandler + def_irq_handler INTUART2RX_IRQHandler + def_irq_handler INTUART2TX_IRQHandler + def_irq_handler INTUART2ERR_IRQHandler + def_irq_handler INTUART3RX_IRQHandler + def_irq_handler INTUART3TX_IRQHandler + def_irq_handler INTUART3ERR_IRQHandler + def_irq_handler INTUART4RX_IRQHandler + def_irq_handler INTUART4TX_IRQHandler + def_irq_handler INTUART4ERR_IRQHandler + def_irq_handler INTUART5RX_IRQHandler + def_irq_handler INTUART5TX_IRQHandler + def_irq_handler INTUART5ERR_IRQHandler + def_irq_handler INTFUART0_IRQHandler + def_irq_handler INTFUART1_IRQHandler + def_irq_handler INTI2C0NST_IRQHandler + def_irq_handler INTI2C0ATX_IRQHandler + def_irq_handler INTI2C0BRX_IRQHandler + def_irq_handler INTI2C0NA_IRQHandler + def_irq_handler INTI2C1NST_IRQHandler + def_irq_handler INTI2C1ATX_IRQHandler + def_irq_handler INTI2C1BRX_IRQHandler + def_irq_handler INTI2C1NA_IRQHandler + def_irq_handler INTI2C2NST_IRQHandler + def_irq_handler INTI2C2ATX_IRQHandler + def_irq_handler INTI2C2BRX_IRQHandler + def_irq_handler INTI2C2NA_IRQHandler + def_irq_handler INTI2C3NST_IRQHandler + def_irq_handler INTI2C3ATX_IRQHandler + def_irq_handler INTI2C3BRX_IRQHandler + def_irq_handler INTI2C3NA_IRQHandler + def_irq_handler INTI2C4NST_IRQHandler + def_irq_handler INTI2C4ATX_IRQHandler + def_irq_handler INTI2C4BRX_IRQHandler + def_irq_handler INTI2C4NA_IRQHandler + def_irq_handler INTADACP0_IRQHandler + def_irq_handler INTADACP1_IRQHandler + def_irq_handler INTADATRG_IRQHandler + def_irq_handler INTADASGL_IRQHandler + def_irq_handler INTADACNT_IRQHandler + def_irq_handler INTADAHP_IRQHandler + def_irq_handler INTFLDRDY_IRQHandler + def_irq_handler INTFLCRDY_IRQHandler + def_irq_handler INTMDMAABERR_IRQHandler + def_irq_handler INTMDMAADERR_IRQHandler + def_irq_handler INTI2S0SI_IRQHandler + def_irq_handler INTI2S0SIERR_IRQHandler + def_irq_handler INTI2S0SO_IRQHandler + def_irq_handler INTI2S0SOERR_IRQHandler + def_irq_handler INTI2S1SI_IRQHandler + def_irq_handler INTI2S1SIERR_IRQHandler + def_irq_handler INTI2S1SO_IRQHandler + def_irq_handler INTI2S1SOERR_IRQHandler + def_irq_handler INTFIR0_IRQHandler + def_irq_handler INTTSSI0RX_IRQHandler + def_irq_handler INTTSSI0TX_IRQHandler + def_irq_handler INTTSSI0ERR_IRQHandler + def_irq_handler INTTSSI1RX_IRQHandler + def_irq_handler INTTSSI1TX_IRQHandler + def_irq_handler INTTSSI1ERR_IRQHandler + def_irq_handler INTT32A14_A_IRQHandler + def_irq_handler INTT32A14_B_IRQHandler + def_irq_handler INTT32A14_CT_IRQHandler + def_irq_handler INTT32A15_A_IRQHandler + def_irq_handler INTT32A15_B_IRQHandler + def_irq_handler INTT32A15_C_IRQHandler + def_irq_handler INTMDMAADISR_IRQHandler + + .end diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/tmpm4grf20fg.ld b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/tmpm4grf20fg.ld new file mode 100644 index 00000000000..ec14e95d754 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/tmpm4grf20fg.ld @@ -0,0 +1,197 @@ +/* + * Copyright(C) 2020, Toshiba Electronic Device Solutions Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* Linker script for Toshiba TMPM4GR */ + +/* Linker script to configure memory regions. */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x200000 +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + /* 8_byte_aligned((175 + 16) vect * 4 bytes) = 8_byte_aligned(0x2FC) = 0x300 */ + RAM (rwx) : ORIGIN = (0x20000000 + 0x300), LENGTH = (256K - 0x300) +} + + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + *(.ram_func*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis.h new file mode 100644 index 00000000000..56102df8fce --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis.h @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "TMPM4GR.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis_nvic.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis_nvic.h new file mode 100644 index 00000000000..fda4e009b2a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis_nvic.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + + +#if defined(__ICCARM__) +#pragma section=".intvec" +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) +#elif defined(__CC_ARM) +extern uint32_t Load$$LR$$LR_IROM1$$Base[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) +#elif defined(__GNUC__) +extern uint32_t vectors[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors) +#else +#error "Flash vector address not set for this toolchain" +#endif + + +#define NVIC_NUM_VECTORS (191) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.c new file mode 100644 index 00000000000..5372d7fea2c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.c @@ -0,0 +1,343 @@ +/** + ******************************************************************************* + * @file system_TMPM4Gx.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the + * TOSHIBA 'TMPM4Gx' Device Series + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#include "TMPM4GR.h" +#include "txz_flash.h" +#include "txz_hal.h" + +/*-------- <<< Start of configuration section >>> ----------------------------*/ + +/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ +#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ +#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ +#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ + +/* Clock Generator (CG) Configuration */ +#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ +#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */ +#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */ + +#define STBYCR_Val (0x00000000UL) + +#define CG_8M_MUL_24_FPLL (0x00245030UL<<8U) /* fPLL = 8MHz * 24 */ +#define CG_10M_MUL_19_1875_FPLL (0x002E9626UL<<8U) /* fPLL = 10MHz * 19.1875 */ +#define CG_12M_MUL_16_FPLL (0x0036D020UL<<8U) /* fPLL = 12MHz * 16 */ +#define CG_16M_MUL_12_FPLL (0x00495018UL<<8U) /* fPLL = 16MHz * 12 */ +#define CG_24M_MUL_8_FPLL (0x006D9010UL<<8U) /* fPLL = 24MHz * 8 */ + +#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL) +#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL) +#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL) +#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL) + +#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U) +#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U) +#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U) + +#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL) +#define CG_OSCCR_EOSCEN_SET (0x00000002UL) +#define CG_OSCCR_OSCSEL_SET (0x00000100UL) + +#define CG_WUPHCR_WUON_START_SET (0x00000001UL) + +#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */ +#if (CLOCK_SETUP) +#define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */ +#define PLL0SEL_Ready CG_12M_MUL_16_FPLL +#else +#define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */ +#define PLL0SEL_Ready CG_10M_MUL_19_1875_FPLL +#endif +#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) +#define PLL0SEL_MASK (0xFFFFFF00UL) + +/*-------- <<< End of configuration section >>> ------------------------------*/ + +/*-------- DEFINES -----------------------------------------------------------*/ +/* Define clocks */ +#define EOSC_8M (8000000UL) +#define EOSC_12M (12000000UL) +#define EOSC_16M (16000000UL) +#define EOSC_24M (24000000UL) +#define IOSC_10M (10000000UL) +#define EXTALH EOSC_12M /* External high-speed oscillator freq */ +#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ +#define EOSC_8M_DIV2_PLLON (192000000UL) /* 8.00MHz * 48.0000 / 2 */ +#define EOSC_12M_DIV2_PLLON (192000000UL) /* 12.00MHz * 32.0000 / 2 */ +#define EOSC_16M_DIV2_PLLON (192000000UL) /* 16.00MHz * 24.0000 / 2 */ +#define EOSC_24M_DIV2_PLLON (192000000UL) /* 24.00MHz * 16.0000 / 2 */ +#define IOSC_10M_DIV2_PLLON (191875000UL) /* 10.00MHz * 38.3750 / 2 */ + +/* Configure Warm-up time */ +#define HZ_1M (1000000UL) +#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ +#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ +#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ +#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = (warm-up time(us) * IXTALH - 16) / 16 */ +#if (CLOCK_SETUP) +#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#else +#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#endif + +/* Determine core clock frequency according to settings */ +/* System clock is high-speed clock*/ +#if (CLOCK_SETUP) +#define CORE_TALH (EXTALH) +#else +#define CORE_TALH (IXTALH) +#endif + +#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ +#if (CORE_TALH == EOSC_8M) /* If input is 8MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_24_FPLL)) +#define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 8MHz */ +#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_16_FPLL) +#define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 12MHz */ +#elif (CORE_TALH == EOSC_16M) /* If input is 16MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_16M_MUL_12_FPLL) +#define __CORE_CLK EOSC_16M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 16MHz */ +#elif (CORE_TALH == EOSC_24M) /* If input is 24MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_24M_MUL_8_FPLL) +#define __CORE_CLK EOSC_24M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 24MHz */ +#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_19_1875_FPLL) +#define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 191.875MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 10MHz */ +#else /* input clock not known */ +#define __CORE_CLK (0U) +#error "Core Oscillator Frequency invalid!" +#endif /* End switch input clock */ +#else +#define __CORE_CLK (CORE_TALH) +#endif + +#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */ +#define __CORE_SYS (__CORE_CLK) +#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */ +#define __CORE_SYS (__CORE_CLK / 2U) +#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */ +#define __CORE_SYS (__CORE_CLK / 4U ) +#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */ +#define __CORE_SYS (__CORE_CLK / 8U) +#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */ +#define __CORE_SYS (__CORE_CLK / 16U) +#else /* Gear -> reserved */ +#define __CORE_SYS (0U) +#endif + +/* Clock Variable definitions */ +uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ +uint32_t CoreClockInput = 0U; + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Update SystemCoreClock according register values. + */ +void SystemCoreClockUpdate(void) +{ + /* Get Core Clock Frequency */ + uint32_t CoreClock = 0U; + uint32_t regval = 0U; + uint32_t oscsel = 0U; + uint32_t pll0sel = 0U; + uint32_t pll0on = 0U; + + CoreClockInput = 0U; + /* Determine clock frequency according to clock register values */ + /* System clock is high-speed clock */ + regval = TSB_CG->OSCCR; + oscsel = regval & CG_OSCCR_OSCSEL_SET; + if (oscsel) { /* If system clock is External high-speed oscillator freq */ + CoreClock = EXTALH; + } else { /* If system clock is Internal high-speed oscillator freq */ + CoreClock = IXTALH; + } + regval = TSB_CG->PLL0SEL; + pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; + pll0on = regval & CG_PLL0SEL_PLL0ON_SET; + if (pll0sel && pll0on) { /* If PLL enabled */ + if (CoreClock == EOSC_8M) { /* If input is 8MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_24_FPLL) { + CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_16_FPLL) { + CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_16M) { /* If input is 16MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_16M_MUL_12_FPLL) { + CoreClockInput = EOSC_16M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_24M) { /* If input is 24MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_24M_MUL_8_FPLL) { + CoreClockInput = EOSC_24M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_19_1875_FPLL) { + CoreClockInput = IOSC_10M_DIV2_PLLON; /* output clock is 191.875MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else { + CoreClockInput = 0U; + } + } else { /* If PLL not used */ + CoreClockInput = CoreClock; + } + + switch (TSB_CG->SYSCR & 7U) { + case 0U: /* Gear -> fc */ + SystemCoreClock = CoreClockInput; + break; + case 1U: /* Gear -> fc/2 */ + SystemCoreClock = CoreClockInput / 2U; + break; + case 2U: /* Gear -> fc/4 */ + SystemCoreClock = CoreClockInput / 4U; + break; + case 3U: /* Gear -> fc/8 */ + SystemCoreClock = CoreClockInput / 8U; + break; + case 4U: /* Gear -> fc/16 */ + SystemCoreClock = CoreClockInput / 16U; + break; + case 5U: + case 6U: + case 7U: + SystemCoreClock = 0U; + break; + default: + SystemCoreClock = 0U; + break; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit(void) +{ +#if (SIWD_SETUP) /* Watchdog Setup */ + /* SIWD Disable */ + TSB_SIWD0->EN = SIWDEN_Val; + TSB_SIWD0->CR = SIWDCR_Val; +#else + /* SIWD Enable (Setting after a Reset) */ +#endif +#if defined ( __CC_ARM ) + /* set Flash Access Control Register */ + Copy_Routine(FLASH_API_RAM, FLASH_API_ROM, SIZE_FLASH_API); /* copy flash API to RAM */ +#endif + fc_read_clock_set(__CORE_SYS); + fc_ram_con_reg_set(__CORE_SYS); + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + +#if (CLOCK_SETUP) /* Clock(external) Setup */ + TSB_CG->SYSCR = SYSCR_GEAR_Val; + + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET); + TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; + while (!TSB_CG_OSCCR_OSCF) { + ; + } /* Confirm CGOSCCR="1" */ + TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; +#else + /* Internal HOSC Enable (Setting after a Reset) */ +#endif + + TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set */ + while ((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val)) + != ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))) { + ; + } + + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; + TSB_CG->PLL0SEL = PLL0SEL_Ready; + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ + TSB_CG->STBYCR = STBYCR_Val; + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Lockup */ + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; + while (!TSB_CG_PLL0SEL_PLL0ST) { + ; + } /*Confirm CGPLL0SEL = "1" */ +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.h new file mode 100644 index 00000000000..d5c53b36b1a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.h @@ -0,0 +1,67 @@ +/** + ***************************************************************************** + * @file system_TMPM4Gx.h + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4Gx' Device Series + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ***************************************************************************** + */ + +#include + +#ifndef __SYSTEM_TMPM4Gx_H +#define __SYSTEM_TMPM4Gx_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CoreClockInput; /*!< High speed Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/flash_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/flash_api.c new file mode 100644 index 00000000000..5f787850b85 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/flash_api.c @@ -0,0 +1,130 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "flash_api.h" +#include "mbed_critical.h" +#include "txz_fc.h" + +#define PROGRAM_WRITE_MAX (16U) // Page program could be written 16 bytes/4 words once +#define SECTOR_SIZE (0x8000) // 32KB each sectors or block +#define FLASH_CHIP_SIZE (0x00200000) // Flash chip size is 2048 KByte +#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL) + +#define SUCCESS (0U) +#define FAIL (-1) +// IHOSC1EN +#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask +#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable +#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable + +static void internal_hosc_enable(void); + +int32_t flash_init(flash_t *obj) +{ + obj->flash_inited = 0; + obj->flash_inited = 1; + internal_hosc_enable(); // Internal HOSC enable + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + obj->flash_inited = 0; + + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + int status = FAIL; + + if (obj->flash_inited == 0) { + flash_init(obj); + } + + // We need to prevent flash accesses during erase operation + core_util_critical_section_enter(); + + if (TXZ_SUCCESS == fc_erase_block_code_flash((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, (uint32_t *)address)) { + status = SUCCESS; + } else { + // Do nothing + } + + core_util_critical_section_exit(); + + return status; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + int status = SUCCESS; + + address &= MASK_CHIP_ID_FROM_ADD; + + // We need to prevent flash accesses during program operation + core_util_critical_section_enter(); + + if (TXZ_SUCCESS == fc_write_code_flash((uint32_t *)data, (uint32_t *)address, size)) { + // Do nothing + } else { + status = FAIL; + } + + core_util_critical_section_exit(); + + return status; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) { + return SECTOR_SIZE; + } else { + // Do nothing + } + + return MBED_FLASH_INVALID_SIZE; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return PROGRAM_WRITE_MAX; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FC_CODE_FLASH_ADDRESS_TOP; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_CHIP_SIZE; +} + +static void internal_hosc_enable(void) +{ + uint32_t work; + work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK); + TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE); +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_api.c new file mode 100644 index 00000000000..c031b499e0e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_api.c @@ -0,0 +1,127 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "txz_gpio.h" + +#define GPIO_DATA PIN_DATA(0, 2) +#define ALT_FUNC_GPIO 0 + +_gpio_t gpio_port_add = { + .p_pa_instance = TSB_PA, + .p_pb_instance = TSB_PB, + .p_pc_instance = TSB_PC, + .p_pd_instance = TSB_PD, + .p_pe_instance = TSB_PE, + .p_pf_instance = TSB_PF, + .p_pg_instance = TSB_PG, + .p_ph_instance = TSB_PH, + .p_pj_instance = TSB_PJ, + .p_pk_instance = TSB_PK, + .p_pl_instance = TSB_PL, + .p_pm_instance = TSB_PM, + .p_pn_instance = TSB_PN, + .p_pp_instance = TSB_PP, + .p_pr_instance = TSB_PR, + .p_pt_instance = TSB_PT, + .p_pu_instance = TSB_PU, + .p_pv_instance = TSB_PV, + .p_pw_instance = TSB_PW, + .p_py_instance = TSB_PY +}; + +uint32_t gpio_set(PinName pin) +{ + // Check that pin is valid + MBED_ASSERT(pin != (PinName)NC); + + // Set pin function as GPIO pin + pin_function(pin, GPIO_DATA); + + // Return pin mask + return (1 << (pin & 0x07)); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + // Store above pin mask, pin name into GPIO object + obj->pin = pin; + if (pin == (PinName)NC) { + return; + } + obj->pin_num = PIN_POS(pin); + obj->mask = gpio_set(pin); + obj->port = (PortName) PIN_PORT(pin); + // Enable clock for particular port + TSB_CG->FSYSMENB |= (1 << ((obj->port) + 2)); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + // Set pin mode + pin_mode(obj->pin, mode); +} + +// Set gpio object pin direction +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + // Set direction + switch (direction) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_INOUT); + break; + default: + break; + } +} + +void gpio_write(gpio_t *obj, int value) +{ + // Write gpio object pin data + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, value); +} + +int gpio_read(gpio_t *obj) +{ + // Read gpio object pin data + gpio_pinstate_t val = GPIO_PIN_SET; // To initialize local variable + gpio_read_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, &val); + return val; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_irq_api.c new file mode 100644 index 00000000000..ddbd7a23847 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_irq_api.c @@ -0,0 +1,297 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_irq_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_critical.h" +#include "txz_gpio.h" + +#define CHANNEL_NUM (16) +#define DISABLE (0) +#define ENABLE (1) +#define CLR_INT_FLAG (0xC0) + +const PinMap PinMap_GPIO_IRQ[] = { + {PK7, GPIO_IRQ_0, PIN_DATA(0, 0)}, + {PL0, GPIO_IRQ_1, PIN_DATA(0, 0)}, + {PA0, GPIO_IRQ_2, PIN_DATA(0, 0)}, + {PA7, GPIO_IRQ_3, PIN_DATA(0, 0)}, + {PB0, GPIO_IRQ_4, PIN_DATA(0, 0)}, + {PB1, GPIO_IRQ_5, PIN_DATA(0, 0)}, + {PB6, GPIO_IRQ_6, PIN_DATA(0, 0)}, + {PB7, GPIO_IRQ_7, PIN_DATA(0, 0)}, + {PG0, GPIO_IRQ_8, PIN_DATA(0, 0)}, + {PG1, GPIO_IRQ_9, PIN_DATA(0, 0)}, + {PK0, GPIO_IRQ_A, PIN_DATA(0, 0)}, + {PK1, GPIO_IRQ_B, PIN_DATA(0, 0)}, + {PL4, GPIO_IRQ_C, PIN_DATA(0, 0)}, + {PL5, GPIO_IRQ_D, PIN_DATA(0, 0)}, + {PC6, GPIO_IRQ_E, PIN_DATA(0, 0)}, + {PC7, GPIO_IRQ_F, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +extern _gpio_t gpio_port_add; + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; +static CG_INTActiveState CurrentState; + +static void CG_SetSTBYReleaseINTSrc(CG_INTSrc, CG_INTActiveState, uint8_t); +static void INT_IRQHandler(PinName, uint32_t); + +void INT00_IRQHandler(void) +{ + INT_IRQHandler(PK7, 0); +} + +void INT01_IRQHandler(void) +{ + INT_IRQHandler(PL0, 1); +} + +void INT02_IRQHandler(void) +{ + INT_IRQHandler(PA0, 2); +} + +void INT03_IRQHandler(void) +{ + INT_IRQHandler(PA7, 3); +} + +void INT04_IRQHandler(void) +{ + INT_IRQHandler(PB0, 4); +} + +void INT05_IRQHandler(void) +{ + INT_IRQHandler(PB1, 5); +} + +void INT06_IRQHandler(void) +{ + INT_IRQHandler(PB6, 6); +} + +void INT07_IRQHandler(void) +{ + INT_IRQHandler(PB7, 7); +} + +void INT08_IRQHandler(void) +{ + INT_IRQHandler(PG0, 8); +} + +void INT09_IRQHandler(void) +{ + INT_IRQHandler(PG1, 9); +} + +void INT10_IRQHandler(void) +{ + INT_IRQHandler(PK0, 10); +} + +void INT11_IRQHandler(void) +{ + INT_IRQHandler(PK1, 11); +} + +void INT12_IRQHandler(void) +{ + INT_IRQHandler(PL4, 12); +} +void INT13_IRQHandler(void) +{ + INT_IRQHandler(PL5, 13); +} +void INT14_IRQHandler(void) +{ + INT_IRQHandler(PC6, 14); +} +void INT15_IRQHandler(void) +{ + INT_IRQHandler(PC7, 15); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t id) +{ + // Get gpio interrupt ID + obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); + core_util_critical_section_enter(); + // Get GPIO port and pin num + obj->port = (PortName)PIN_PORT(pin); + obj->pin_num = PIN_POS(pin); + // Set pin level as LOW + gpio_write_bit(&gpio_port_add, obj->port, obj->pin_num, GPIO_Mode_DATA, 0); + // Enable gpio interrupt function + pinmap_pinout(pin, PinMap_GPIO_IRQ); + // Get GPIO irq source + obj->irq_src = (CG_INTSrc)obj->irq_id; + // Save irq handler + hal_irq_handler[obj->irq_src] = handler; + // Save irq id + channel_ids[obj->irq_src] = id; + // Initialize interrupt event as both edges detection + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Set interrupt event and enable INTx clear + CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); + core_util_critical_section_exit(); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + // Clear gpio_irq + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Reset interrupt handler + hal_irq_handler[obj->irq_src] = NULL; + // Reset interrupt id + channel_ids[obj->irq_src] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + // Disable GPIO interrupt on obj + gpio_irq_disable(obj); + + if (enable) { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || + (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || + (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else { + error("Not supported event\n"); + } + } else { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || + (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || + (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else { + error("Not supported event\n"); + } + } + + CurrentState = obj->event; + if (obj->event != CG_INT_ACTIVE_STATE_INVALID) { + // Set interrupt event and enable INTx clear + CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 0); + } else { + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 1); + } + + // Clear interrupt request + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Enable GPIO interrupt on obj + gpio_irq_enable(obj); +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + // Clear and Enable gpio_irq object + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + NVIC_EnableIRQ((IRQn_Type)obj->irq_id); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + // Disable gpio_irq object + NVIC_DisableIRQ((IRQn_Type)obj->irq_id); +} + +static void INT_IRQHandler(PinName pin, uint32_t index) +{ + PortName port; + uint8_t pin_num; + + gpio_pinstate_t data = GPIO_PIN_RESET; + pin_num = PIN_POS(pin); + port = (PortName)PIN_PORT(pin); + + // Clear interrupt request + CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, DISABLE); + // Get pin value + gpio_read_bit(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)pin_num, GPIO_Mode_DATA, &data); + + switch (data) { + // Falling edge detection + case 0: + hal_irq_handler[index](channel_ids[index], IRQ_FALL); + break; + // Rising edge detection + case 1: + hal_irq_handler[index](channel_ids[index], IRQ_RISE); + break; + default: + break; + } + + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_0 + index)); + // Enable interrupt request + CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, ENABLE); +} + +static void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource, CG_INTActiveState ActiveState, uint8_t NewState) +{ + uint8_t *ptr = NULL; + if ((INTSource == 12) || (INTSource == 13)) { + ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2) + 1); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else { + ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2)); + // Clear pending falling and rising edge bit + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } + { + uint8_t regval = *ptr; + (void)regval; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_object.h new file mode 100644 index 00000000000..284f901350b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_object.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t pin_num; + uint32_t mask; + PinName pin; + PortName port; +} gpio_t; + +typedef enum { + CG_INT_SRC_0 = 0U, + CG_INT_SRC_1, + CG_INT_SRC_2, + CG_INT_SRC_3, + CG_INT_SRC_4, + CG_INT_SRC_5, + CG_INT_SRC_6, + CG_INT_SRC_7, + CG_INT_SRC_8, + CG_INT_SRC_9, + CG_INT_SRC_A, + CG_INT_SRC_B, + CG_INT_SRC_C, + CG_INT_SRC_D, + CG_INT_SRC_E, + CG_INT_SRC_F +} CG_INTSrc; + +typedef enum { + CG_INT_ACTIVE_STATE_L = 0x00U, + CG_INT_ACTIVE_STATE_H = 0x02U, + CG_INT_ACTIVE_STATE_FALLING = 0x04U, + CG_INT_ACTIVE_STATE_RISING = 0x06U, + CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U, + CG_INT_ACTIVE_STATE_INVALID = 0x0AU +} CG_INTActiveState; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName)NC); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/i2c_api.c new file mode 100644 index 00000000000..32f333e5695 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/i2c_api.c @@ -0,0 +1,308 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "i2c_api.h" + +#if DEVICE_I2C + +#include +#include +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "txz_i2c_api.h" + +#define MAX_I2C_FREQ 1000000 +#define I2C_TRANSFER_STATE_IDLE (0x0U) + +#if DEVICE_I2C_ASYNCH +#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) +#else +#define I2C_S(obj) (struct i2c_s *) (obj) +#endif + +static const PinMap PinMap_I2C_SDA[] = { + {PG2, I2C_0, PIN_DATA(7, 2)}, + {PF2, I2C_1, PIN_DATA(7, 2)}, + {PG4, I2C_2, PIN_DATA(7, 2)}, + {PJ6, I2C_3, PIN_DATA(7, 2)}, + {PJ3, I2C_4, PIN_DATA(7, 2)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {PG3, I2C_0, PIN_DATA(7, 2)}, + {PF3, I2C_1, PIN_DATA(7, 2)}, + {PG5, I2C_2, PIN_DATA(7, 2)}, + {PJ7, I2C_3, PIN_DATA(7, 2)}, + {PJ2, I2C_4, PIN_DATA(7, 2)}, + {NC, NC, 0} +}; + +// Initialize the I2C peripheral. It sets the default parameters for I2C +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + struct i2c_s *obj_s = I2C_S(obj); + MBED_ASSERT(obj_s != NULL); + + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + + MBED_ASSERT((int)i2c_name != NC); + obj_s->index = i2c_name; + obj_s->is_master = 1; + + switch (i2c_name) { + case I2C_0: + TSB_CG_FSYSMENA_IPMENA29 = TXZ_ENABLE; // Enable clock for I2C_0 + TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; // Enable clock for GPIO G + obj_s->my_i2c.i2c.p_instance = TSB_I2C0; + obj_s->irqn = INTI2C0NST_IRQn; + break; + case I2C_1: + TSB_CG_FSYSMENA_IPMENA30 = TXZ_ENABLE; // Enable clock for I2C_1 + TSB_CG_FSYSMENB_IPMENB07 = TXZ_ENABLE; // Enable clock for GPIO F + obj_s->my_i2c.i2c.p_instance = TSB_I2C1; + obj_s->irqn = INTI2C1NST_IRQn; + break; + case I2C_2: + TSB_CG_FSYSMENA_IPMENA31 = TXZ_ENABLE; // Enable clock for I2C_2 + TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; // Enable clock for GPIO G + obj_s->my_i2c.i2c.p_instance = TSB_I2C2; + obj_s->irqn = INTI2C2NST_IRQn; + break; + case I2C_3: + TSB_CG_FSYSMENB_IPMENB00 = TXZ_ENABLE; // Enable clock for I2C_3 + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; // Enable clock for GPIO J + obj_s->my_i2c.i2c.p_instance = TSB_I2C3; + obj_s->irqn = INTI2C3NST_IRQn; + break; + case I2C_4: + TSB_CG_FSYSMENB_IPMENB01 = TXZ_ENABLE; // Enable clock for I2C_4 + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; // Enable clock for GPIO J + obj_s->my_i2c.i2c.p_instance = TSB_I2C4; + obj_s->irqn = INTI2C3NST_IRQn; + break; + default: + error("I2C is not available"); + break; + } + + pinmap_pinout(sda, PinMap_I2C_SDA); + pin_mode(sda, OpenDrain); + pin_mode(sda, PullUp); + + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(scl, OpenDrain); + pin_mode(scl, PullUp); + + i2c_reset(obj); + i2c_frequency(obj, 100000); + I2C_init(&obj_s->my_i2c.i2c); +} + +// Configure the I2C frequency +void i2c_frequency(i2c_t *obj, int hz) +{ + struct i2c_s *obj_s = I2C_S(obj); + + if (hz > MAX_I2C_FREQ) { + error("Failed : Max I2C frequency is 1000000"); + } + + i2c_frequency_t(&obj_s->my_i2c, hz); + + if (obj_s->is_master) { + I2C_init(&obj_s->my_i2c.i2c); + } else { + I2C_slave_init(&obj_s->my_i2c.i2c); + } +} + +int i2c_start(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_start_t(&obj_s->my_i2c); + + return TXZ_SUCCESS; +} + +int i2c_stop(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_stop_t(&obj_s->my_i2c); + + return TXZ_SUCCESS; +} + +void i2c_reset(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + // Software reset + i2c_reset_t(&obj_s->my_i2c); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_read_t(&obj_s->my_i2c, address, (uint8_t *)data, length, stop); + + return count; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_write_t(&obj_s->my_i2c, address, (uint8_t *)data, length, stop); + + return count; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + int32_t data = 0; + struct i2c_s *obj_s = I2C_S(obj); + + data = i2c_byte_read_t(&obj_s->my_i2c, last); + + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int32_t result = 0; + struct i2c_s *obj_s = I2C_S(obj); + + result = i2c_byte_write_t(&obj_s->my_i2c, data); + + return result; +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + struct i2c_s *obj_s = I2C_S(obj); + + obj_s->is_master = 0; + i2c_slave_mode_t(&obj_s->my_i2c, enable_slave); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_slave_address_t(&obj_s->my_i2c, address); +} + +int i2c_slave_receive(i2c_t *obj) +{ + int32_t result = 0; + struct i2c_s *obj_s = I2C_S(obj); + + result = i2c_slave_receive_t(&obj_s->my_i2c); + + return result; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_slave_read_t(&obj_s->my_i2c, (uint8_t *)data, length); + + return count; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_slave_write_t(&obj_s->my_i2c, (uint8_t *)data, length); + + return count; +} + +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +#if DEVICE_I2C_ASYNCH + +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, + uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) +{ + struct i2c_s *obj_s = I2C_S(obj); + + obj_s->event_mask = event; + //Set irqn table for future use + set_i2c(obj_s->index, &obj_s->my_i2c.info.irqn); + NVIC_SetVector(obj_s->irqn, handler); + i2c_transfer_asynch_t(&obj_s->my_i2c, (uint8_t *)tx, tx_length, (uint8_t *)rx, rx_length, address, stop); +} + +uint32_t i2c_irq_handler_asynch(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + uint32_t event = 0; + + event = i2c_irq_handler_asynch_t(&obj_s->my_i2c); + + return (event & obj_s->event_mask); +} + +uint8_t i2c_active(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + uint8_t ret = (obj_s->my_i2c.info.asynch.state != I2C_TRANSFER_STATE_IDLE); + + return ret; +} + +void i2c_abort_asynch(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_abort_asynch_t(&obj_s->my_i2c); +} + +#endif // #if DEVICE_I2C_ASYNCH + +#endif // #if DEVICE_I2C diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/objects.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/objects.h new file mode 100644 index 00000000000..921a9b94f30 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/objects.h @@ -0,0 +1,128 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include +#include "PortNames.h" +#include "PeripheralNames.h" +#include "gpio_object.h" +#include "txz_uart.h" +#include "txz_fuart.h" +#include "txz_tspi.h" +#include "txz_t32a.h" +#include "txz_cg.h" +#include "txz_driver_def.h" +#include "txz_adc.h" +#include "txz_i2c_api.h" +#include "txz_i2c.h" +#include "txz_fuart_include.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct port_s { + uint32_t mask; + PortName port; +}; + +struct dac_s { + DACName dac; + TSB_DA_TypeDef *DACx; +}; + +typedef struct { + uint32_t BaudRate; + uint32_t DataBits; + uint32_t StopBits; + uint32_t Parity; + uint32_t Mode; + uint32_t FlowCtrl; +} FUART_InitTypeDef; + +struct serial_s { + uint32_t index; + uint32_t mode; + uint8_t is_using_fuart; + TSB_UART_TypeDef *UARTx; + TSB_FURT_TypeDef *FUARTx; + uart_boudrate_t boud_obj; + fuart_boudrate_t boudrate; + FUART_InitTypeDef fuart_config; +}; + +struct pwmout_s { + uint32_t divisor; + uint32_t type; + uint32_t trailing_timing; + uint32_t leading_timing; + float period; + t32a_t p_t32a; + PinName pin; +}; + +struct spi_s { + tspi_t p_obj; + SPIName module; + uint8_t bits; + PinName Slave_SCK; +#if DEVICE_SPI_ASYNCH + uint32_t irqn; + uint32_t event; + uint32_t max_size; + uint32_t state; +#endif +}; + +struct gpio_irq_s { + PortName port; + uint8_t pin_num; + uint32_t irq_id; + CG_INTSrc irq_src; + CG_INTActiveState event; +}; + +struct flash_s { + int flash_inited; +}; + +struct analogin_s { + adc_t p_adc; + PinName pin; + ADCName adc; + adc_channel_setting_t param; +}; + +struct i2c_s { + uint8_t is_master; + uint32_t index; + IRQn_Type irqn; + _i2c_t my_i2c; +#if DEVICE_I2C_ASYNCH + uint32_t event_mask; +#endif +}; + + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pinmap.c new file mode 100644 index 00000000000..bf963874a81 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pinmap.c @@ -0,0 +1,103 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "txz_gpio.h" + +#define PIN_FUNC_MAX 8 + +extern _gpio_t gpio_port_add; + +void pin_function(PinName pin, int function) +{ + uint32_t port = 0; + uint8_t bit = 0; + uint8_t func = 0; + uint8_t dir = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Calculate pin function and pin direction + func = PIN_FUNC(function); + dir = PIN_DIR(function); + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Find function is in range or not + if (func <= PIN_FUNC_MAX) { + // Set pin function and direction if direction is in range + switch (dir) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INOUT); + break; + default: + break; + } + } else { + // Do nothing + } +} + +void pin_mode(PinName pin, PinMode mode) +{ + uint32_t port = 0; + uint8_t bit = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Check if function is in range + if (mode > OpenDrain) { + return; + } + + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Set pin mode + switch (mode) { + case PullNone: + gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); + gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); + gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); + break; + case PullUp: + gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); + break; + case PullDown: + gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); + break; + case OpenDrain: + gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); + break; + default: + break; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/port_api.c new file mode 100644 index 00000000000..4aaff9b59bf --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/port_api.c @@ -0,0 +1,144 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "txz_gpio.h" +#include "pinmap.h" + +#define PORT_PIN_NUM (8) +#define ALT_FUNC_GPIO (0) + +extern _gpio_t gpio_port_add; +static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num); + +PinName port_pin(PortName port, int pin_n) +{ + PinName pin = NC; + pin = (PinName)((port << 3) | pin_n); + return pin; +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(port <= PortY); + + // Store port and port mask for future use + obj->port = port; + obj->mask = mask; + + // Enable the clock for particular port + _gpio_init(&gpio_port_add, obj->port); + + // Set port function and port direction + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_function(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + // Set mode for masked pins + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + for (i = 0; i < PORT_PIN_NUM; i++) { + // Set direction for masked pins + if (obj->mask & (1 << i)) { + gpio_pin_dir(obj, dir, i); + } + } +} + +void port_write(port_t *obj, int value) +{ + uint32_t port_data = 0; + uint32_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + // Get current data of port + gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); + + // Calculate data to write to masked pins + data = (port_data & ~obj->mask) | (value & obj->mask); + + // Write data to masked pins of the port + gpio_write_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, data); +} + +int port_read(port_t *obj) +{ + uint32_t port_data = 0; + uint32_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + // Get current data of port + gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); + + // Calculate data of masked pins + data = port_data & obj->mask; + + return data; +} + +static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num) +{ + switch (dir) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INOUT); + break; + default: + // error("Invalid direction\n"); + break; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pwmout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pwmout_api.c new file mode 100644 index 00000000000..b4fdfa38c45 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pwmout_api.c @@ -0,0 +1,240 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pwmout_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" + +#define GPIO_CLK_OFFSET 2 +#define CALCULATE_RGC1_VAL 2.95 + +static const PinMap PinMap_PWM[] = { + {PA5, PWM_0, PIN_DATA(5, 1)}, + {PB2, PWM_1, PIN_DATA(5, 1)}, + {PB4, PWM_2, PIN_DATA(5, 1)}, + {PD2, PWM_3, PIN_DATA(5, 1)}, + {PD4, PWM_4, PIN_DATA(5, 1)}, + {PE1, PWM_5, PIN_DATA(5, 1)}, + {PE6, PWM_6, PIN_DATA(5, 1)}, + {PC2, PWM_7, PIN_DATA(5, 1)}, + {PL6, PWM_8, PIN_DATA(3, 1)}, + {PC4, PWM_9, PIN_DATA(5, 1)}, + {PM2, PWM_10, PIN_DATA(3, 1)}, + {PU0, PWM_11, PIN_DATA(3, 1)}, + {PU6, PWM_12, PIN_DATA(3, 1)}, + {NC, NC, 0} +}; + +void pwmout_init(pwmout_t *obj, PinName pin) +{ + // Determine the pwm channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + + // Assert input is valid + MBED_ASSERT(pwm != (PWMName)NC); + + switch (pwm) { + case PWM_0: + obj->p_t32a.p_instance = TSB_T32A1; + // Clock enable of T32A ch01 + TSB_CG_FSYSMENA_IPMENA07 = TXZ_ENABLE; + break; + case PWM_1: + obj->p_t32a.p_instance = TSB_T32A2; + // Clock enable of T32A ch02 + TSB_CG_FSYSMENA_IPMENA08 = TXZ_ENABLE; + break; + case PWM_2: + obj->p_t32a.p_instance = TSB_T32A3; + // Clock enable of T32A ch03 + TSB_CG_FSYSMENA_IPMENA09 = TXZ_ENABLE; + break; + case PWM_3: + obj->p_t32a.p_instance = TSB_T32A4; + // Clock enable of T32A ch04 + TSB_CG_FSYSMENA_IPMENA10 = TXZ_ENABLE; + break; + case PWM_4: + obj->p_t32a.p_instance = TSB_T32A5; + // Clock enable of T32A ch05 + TSB_CG_FSYSMENA_IPMENA11 = TXZ_ENABLE; + break; + case PWM_5: + obj->p_t32a.p_instance = TSB_T32A6; + // Clock enable of T32A ch06 + TSB_CG_FSYSMENA_IPMENA12 = TXZ_ENABLE; + break; + case PWM_6: + obj->p_t32a.p_instance = TSB_T32A7; + // Clock enable of T32A ch07 + TSB_CG_FSYSMENA_IPMENA13 = TXZ_ENABLE; + break; + case PWM_7: + obj->p_t32a.p_instance = TSB_T32A8; + // Clock enable of T32A ch08 + TSB_CG_FSYSMENA_IPMENA14 = TXZ_ENABLE; + break; + case PWM_8: + obj->p_t32a.p_instance = TSB_T32A9; + // Clock enable of T32A ch09 + TSB_CG_FSYSMENA_IPMENA15 = TXZ_ENABLE; + break; + case PWM_9: + obj->p_t32a.p_instance = TSB_T32A10; + // Clock enable of T32A ch10 + TSB_CG_FSYSMENA_IPMENA16 = TXZ_ENABLE; + break; + case PWM_10: + obj->p_t32a.p_instance = TSB_T32A11; + // Clock enable of T32A ch11 + TSB_CG_FSYSMENA_IPMENA17 = TXZ_ENABLE; + break; + case PWM_11: + obj->p_t32a.p_instance = TSB_T32A12; + // Clock enable of T32A ch12 + TSB_CG_FSYSMENA_IPMENA18 = TXZ_ENABLE; + break; + case PWM_12: + obj->p_t32a.p_instance = TSB_T32A13; + // Clock enable of T32A ch13 + TSB_CG_FSYSMENA_IPMENA19 = TXZ_ENABLE; + break; + default: + obj->p_t32a.p_instance = NULL; + break; + } + + if (obj->p_t32a.p_instance == NULL) { + return; + } + + // Enable clock for GPIO port. + TSB_CG->FSYSMENB |= (TXZ_ENABLE << ((PIN_PORT(pin)) + GPIO_CLK_OFFSET)); + + // Set pin function as PWM + pinmap_pinout(pin, PinMap_PWM); + + // Default to 20ms, 0% duty cycle + pwmout_period_ms(obj, 20); +} + +void pwmout_free(pwmout_t *obj) +{ + // Stop PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + obj->trailing_timing = TXZ_DISABLE; + obj->leading_timing = TXZ_DISABLE; + obj->p_t32a.p_instance = NULL; +} + +void pwmout_write(pwmout_t *obj, float value) +{ + // Stop PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + + if (value <= 0.0f) { + value = TXZ_DISABLE; + } else if (value >= 1.0f) { + value = TXZ_ENABLE; + } + + // Store the new leading_timing value + obj->leading_timing = obj->trailing_timing - (obj->trailing_timing * value); + + // Setting T32A_RGA0 register + obj->p_t32a.p_instance->RGC0 = obj->leading_timing; + + // Start PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +float pwmout_read(pwmout_t *obj) +{ + float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing); + return duty_cycle; +} + +void pwmout_period(pwmout_t *obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0f)); +} + +void pwmout_period_ms(pwmout_t *obj, int ms) +{ + pwmout_period_us(obj, (ms * 1000)); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t *obj, int us) +{ + uint32_t prscl = 0; + float duty_cycle = 0; + float seconds = (float)((us) / 1000000.0f); + + obj->period = seconds; + // Restore the duty-cycle + duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing); + prscl = T32A_PRSCLx_32; + + obj->trailing_timing = (us * CALCULATE_RGC1_VAL); + obj->leading_timing = ((obj->trailing_timing) - (obj->trailing_timing * duty_cycle)); + + obj->p_t32a.p_instance->MOD = T32A_MODE_32; + obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + obj->p_t32a.p_instance->CRC = (prscl | T32A_RELOAD_TREGx); + obj->p_t32a.p_instance->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ | + T32A_IMx1_MASK_REQ | T32A_IMx0_MASK_REQ); + obj->p_t32a.p_instance->RGC0 = obj->leading_timing; + obj->p_t32a.p_instance->RGC1 = obj->trailing_timing; + obj->p_t32a.p_instance->OUTCRC0 = T32A_OCR_DISABLE; + obj->p_t32a.p_instance->OUTCRC1 = (T32A_OCRCMPx1_CLR | T32A_OCRCMPx0_SET); + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +int pwmout_read_period_us(pwmout_t *obj) +{ + return obj->trailing_timing; +} + +void pwmout_pulsewidth(pwmout_t *obj, float seconds) +{ + pwmout_pulsewidth_us(obj, (seconds * 1000000.0f)); +} + +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ + pwmout_pulsewidth_us(obj, (ms * 1000)); +} + +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + float seconds = 0; + float value = 0; + + seconds = (float)(us / 1000000.0f); + value = (((seconds / obj->period) * 100.0f) / 100.0f); + pwmout_write(obj, value); +} + +int pwmout_read_pulsewidth_us(pwmout_t *obj) +{ + return obj->trailing_timing - obj->leading_timing; +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/reset_reason_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/reset_reason_api.c new file mode 100644 index 00000000000..040a86a85ec --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/reset_reason_api.c @@ -0,0 +1,132 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "reset_reason_api.h" + +#ifdef DEVICE_RESET_REASON + +#include "TMPM4GR.h" +#include + +static uint8_t set_bit_count(uint32_t reg); + +typedef enum { + POWER_ON_BIT_POS = 1 << 0, + PIN_RESET_BIT_POS = 1 << 3, + LOW_POWER_BIT_POS = 1 << 4, + BROWN_OUT_BIT_POS = 1 << 5, +} reason_flag0; + +typedef enum { + SOFTWARE_BIT_POS = 1 << 0, + LOCK_BIT_POS = 1 << 1, + WATCHDOG_BIT_POS = 1 << 2, + PLATFORM_BIT_POS = 1 << 3, +} reason_flag1; + +void hal_reset_reason_clear(void) +{ + TSB_RLM->RSTFLG0 = 0; + TSB_RLM->RSTFLG1 = 0; +} + +uint32_t hal_reset_reason_get_raw(void) +{ + uint32_t ret = 0; + + ret = (((TSB_RLM->RSTFLG1 & 0xFF) << 8) | (TSB_RLM->RSTFLG0 & 0xFF)); + + return ret; +} + +reset_reason_t hal_reset_reason_get(void) +{ + reset_reason_t ret; + + uint8_t NoOfSetBitCountReg1 = set_bit_count(TSB_RLM->RSTFLG0); + uint8_t NoOfSetBitCountReg2 = set_bit_count(TSB_RLM->RSTFLG1); + + if (NoOfSetBitCountReg1 != 0x00) { + if (NoOfSetBitCountReg1 > 0x01) { + ret = RESET_REASON_MULTIPLE; + } else { + if (TSB_RLM->RSTFLG0 & POWER_ON_BIT_POS) { + ret = RESET_REASON_POWER_ON; + } else if (TSB_RLM->RSTFLG0 & PIN_RESET_BIT_POS) { + ret = RESET_REASON_PIN_RESET; + } else if (TSB_RLM->RSTFLG0 & LOW_POWER_BIT_POS) { + ret = RESET_REASON_WAKE_LOW_POWER; + } else if (TSB_RLM->RSTFLG0 & BROWN_OUT_BIT_POS) { + ret = RESET_REASON_BROWN_OUT; + } else { + ret = RESET_REASON_UNKNOWN; + } + } + } else if (NoOfSetBitCountReg2 != 0x00) { + if (NoOfSetBitCountReg2 > 0x01) { + ret = RESET_REASON_MULTIPLE; + } else { + if (TSB_RLM->RSTFLG1 & SOFTWARE_BIT_POS) { + ret = RESET_REASON_SOFTWARE; + } else if (TSB_RLM->RSTFLG1 & LOCK_BIT_POS) { + ret = RESET_REASON_LOCKUP; + } else if (TSB_RLM->RSTFLG1 & WATCHDOG_BIT_POS) { + ret = RESET_REASON_WATCHDOG; + } else if (TSB_RLM->RSTFLG1 & PLATFORM_BIT_POS) { + ret = RESET_REASON_PLATFORM; + } else { + ret = RESET_REASON_UNKNOWN; + } + } + } else { + ret = RESET_REASON_UNKNOWN; + } + + return ret; +} + +void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap) +{ + cap->reasons = 1 << RESET_REASON_UNKNOWN; + cap->reasons |= 1 << RESET_REASON_POWER_ON; + cap->reasons |= 1 << RESET_REASON_PIN_RESET; + cap->reasons |= 1 << RESET_REASON_WAKE_LOW_POWER; + cap->reasons |= 1 << RESET_REASON_BROWN_OUT; + cap->reasons |= 1 << RESET_REASON_SOFTWARE; + cap->reasons |= 1 << RESET_REASON_LOCKUP; + cap->reasons |= 1 << RESET_REASON_WATCHDOG; + cap->reasons |= 1 << RESET_REASON_PLATFORM; + cap->reasons |= 1 << RESET_REASON_MULTIPLE; + +} + +static uint8_t set_bit_count(uint32_t reg) +{ + uint8_t count = 0; + uint8_t index = 0; + + for (index = 0; index < (sizeof(uint32_t) * 8); index++) { + if (reg & (1 << index)) { + count++; + if (count > 0x01) { + break; + } + } + } + + return count; +} + +#endif // DEVICE_RESET_REASON diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/rtc_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/rtc_api.c new file mode 100644 index 00000000000..7255dcb6e5b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/rtc_api.c @@ -0,0 +1,241 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtc_api.h" +#include "mbed_mktime.h" + +#define RTC_24_HOUR_MODE ((uint8_t)0x01) +#define PAGER_PAGE_ONE ((uint8_t)0x01) +#define PAGER_PAGE_ZERO ((uint8_t)0xEE) +#define RTC_CLK_ENABLE ((uint8_t)0x08) +#define RTC_CLK_DISABLE ((uint8_t)0xE7) +#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20) +#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20) +#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000) +#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002) +#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000) +#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001) +#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001) +#define RLMLOSCCR_DRCOSCL_RW_ENABLE ((uint32_t)0x00000004) +#define ELOSC_CFG_WARM_UP_TIME ((uint64_t)(5000)) +#define ELOSC_CFG_CLOCK ((uint64_t)(32768)) +#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro +#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro + +static int rtc_inited = 0; +static int diff_year = 100; //our RTC register only support 2000~2099 +static void external_losc_enable(void); + +void rtc_init(void) +{ + if (!rtc_inited) { + external_losc_enable(); // Enable low-speed oscillator + TSB_RTC->PAGER = 0x00; // Disable clock and alarm + while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { + // Reset RTC sec counter + } + + TSB_RTC->RESTR = 0xE7; + while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { + // Reset RTC sec counter + } + + TSB_RTC->PAGER |= PAGER_PAGE_ONE; + TSB_RTC->YEARR = 0x03; // Set leap year state + TSB_RTC->MONTHR = RTC_24_HOUR_MODE; // Set hour mode + TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Set hour mode + TSB_RTC->YEARR = 0x01; // Set year value + TSB_RTC->MONTHR = (uint8_t)0x01; // Set month value + TSB_RTC->DATER = (uint8_t)0x01; // Set date value + TSB_RTC->DAYR = (uint8_t)0x0; // Set day value + TSB_RTC->HOURR = (uint8_t)0x01; // Set hour value + TSB_RTC->MINR = (uint8_t)0x02; // Set minute value + TSB_RTC->SECR = (uint8_t)0x22; // Set second value + TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock + rtc_inited = 1; // Enable RTC initialzed status + } +} + +void rtc_free(void) +{ + rtc_inited = 0; // Set status of RTC peripheral driver as DISABLE +} + +int rtc_isenabled(void) +{ + return rtc_inited; // Return status of RTC peripheral driver +} + +time_t rtc_read(void) +{ + if (!rtc_inited) { + // Return invalid time for now! + return 0; + } + + struct tm timeinfo; + uint8_t read_1 = 0U; + uint8_t read_2 = 0U; + + timeinfo.tm_isdst = 0; //no summer time + + TSB_RTC->PAGER &= PAGER_PAGE_ZERO; + + read_1 = TSB_RTC->SECR; // Get sec value + timeinfo.tm_sec = HEX2DEC(read_1); + + // Get minute value + do { + read_1 = TSB_RTC->MINR; + read_2 = TSB_RTC->MINR; + } while (read_1 != read_2); + timeinfo.tm_min = HEX2DEC(read_1); + + // Get hour value + do { + read_1 = TSB_RTC->HOURR; + read_2 = TSB_RTC->HOURR; + } while (read_1 != read_2); + timeinfo.tm_hour = HEX2DEC(read_1); + + // Get Month date value + do { + read_1 = TSB_RTC->DATER; + read_2 = TSB_RTC->DATER; + } while (read_1 != read_2); + timeinfo.tm_mday = HEX2DEC(read_1); + + // Get Month value + do { + read_1 = TSB_RTC->MONTHR; + read_2 = TSB_RTC->MONTHR; + } while (read_1 != read_2); + timeinfo.tm_mon = HEX2DEC(read_1) - 1; + + // Get weekday value + do { + read_1 = TSB_RTC->DAYR; + read_2 = TSB_RTC->DAYR; + } while (read_1 != read_2); + timeinfo.tm_wday = HEX2DEC(read_1); + + // Get year value + do { + read_1 = TSB_RTC->YEARR; + read_2 = TSB_RTC->YEARR; + } while (read_1 != read_2); + timeinfo.tm_year = (HEX2DEC(read_1) + diff_year); + + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return 0; + } + return t; +} + +void rtc_write(time_t t) +{ + if (!rtc_inited) { + // Initialize the RTC as not yet initialized + rtc_init(); + } + + struct tm timeinfo; + if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return; + } + + diff_year = timeinfo.tm_year - (timeinfo.tm_year % 100); + TSB_RTC->PAGER &= RTC_CLK_DISABLE; // Disable clock + + // Check current year is leap year or not + if (((timeinfo.tm_year % 4) == 0 && (timeinfo.tm_year % 100) != 0) || + (timeinfo.tm_year % 400) == 0) { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is a leap year + TSB_RTC->YEARR = 0x00; + } else if ((timeinfo.tm_year % 4) == 1) { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is the year following a leap year + TSB_RTC->YEARR = 0x01; + } else if ((timeinfo.tm_year % 4) == 2) { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is two years after a leap year + TSB_RTC->YEARR = 0x02; + } else { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is three years after a leap year + TSB_RTC->YEARR = 0x03; + } + + TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Select PAGE 0 + + TSB_RTC->YEARR = (uint8_t)DEC2HEX((timeinfo.tm_year - diff_year)); // Set year value + + // Set month value, tm_mon=0 means Jan while 1 is Jan + TSB_RTC->MONTHR = (uint8_t)DEC2HEX((timeinfo.tm_mon + 1)); + TSB_RTC->DATER = (uint8_t)DEC2HEX(timeinfo.tm_mday); // Set date value + TSB_RTC->DAYR = (uint8_t)(timeinfo.tm_wday); // Set week day value + TSB_RTC->HOURR = (uint8_t)DEC2HEX(timeinfo.tm_hour); // Set hour value + TSB_RTC->MINR = (uint8_t)DEC2HEX(timeinfo.tm_min); // Set minute value + TSB_RTC->SECR = (uint8_t)DEC2HEX(timeinfo.tm_sec); // Set second value + + // Setting Wait + // When stop mode is selected, CaseA or CaseB is need. + // CaseA: Wait for RTC 1Hz interrupt. + // CaseB: Check the clock register setting. + { + uint8_t flag = 1; + time_t time_read = {0}; + while (flag) { + time_read = rtc_read(); + if (time_read == t) { // Wait for setting successfully + flag = 0; + } + } + } + TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock +} + +static void external_losc_enable(void) +{ + uint32_t work; + + // [CGWUPLCR] :Warm up time + //-------------------------------------- + // "1"counter (s) = 1 / ELOSC + // "1"counter (us) = (10^6) / ELOSC + // "x"counter (us) = time + //-------------------------------------- + // x : time = 1 : (10^6) / ELOSC + //-------------------------------------- + { + uint64_t x = (uint64_t)((uint64_t)(ELOSC_CFG_WARM_UP_TIME) * (uint64_t)(ELOSC_CFG_CLOCK)); + x = (uint64_t)(x / (uint64_t)(1000000)); + if (x > (uint64_t)(0x7FFFF)) { + /* invalid value */ + } + work = (uint32_t)x; + } + work &= (uint32_t)(0xFFFFFFF0); + work <<= 8; + TSB_CG->WUPLCR = work; + // [RLMLOSCCR] :LOSC Enable + TSB_RLM->LOSCCR = RLMLOSCCR_DRCOSCL_RW_ENABLE | RLMLOSCCR_XTEN_RW_ENABLE; + // [CGWUPLCR] :Enable + work = (uint32_t)(TSB_CG->WUPLCR & CGWUPLCR_WUPTL_HIGH_MASK); + TSB_CG->WUPLCR = (uint32_t)(work | CGWUPLCR_WULON_W_ENABLE); + // [CGWUPLCR] :Read(wait for warm-up) + while ((TSB_CG->WUPLCR & CGWUPLCR_WULEF_MASK) != CGWUPLCR_WULEF_R_DONE) { + // no processing + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/serial_api.c new file mode 100644 index 00000000000..a31c7459d61 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/serial_api.c @@ -0,0 +1,725 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "mbed_error.h" +#include "serial_api.h" +#include "pinmap.h" + +#define UART_NUM 8 +#define UART_ENABLE_RX ((uint32_t)0x00000001) +#define UART_ENABLE_TX ((uint32_t)0x00000002) +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) +#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) +#define LCR_H_WLEN_MASK ((uint32_t)0xFFFFFF9F) +#define LCR_H_STP2_MASK ((uint32_t)0xFFFFFFF7) +#define LCR_H_PARITY_MASK ((uint32_t)0xFFFFFF79) +#define CR_FLOW_CTRL_MASK ((uint32_t)0x00000F07) +#define CR_MODE_MASK ((uint32_t)0x0000CC07) +#define FUARTxCR_UARTEN_ENABLE_CLEAR ((uint32_t)0xFFFFFF7E) +#define FUART_CTS_RTS_DISABLE_MASK ((uint32_t)0XFFFF3FFF) +#define BAUDRATE_DEFAULT (9600) +#define CLR_REGISTER (0x00) +#define IMSC_TXIM_RXIM_MASK ((uint32_t)0X000007C0) +#define IMSC_RXIM_CLEAR ((uint32_t)0X000007E0) +#define IMSC_TXIM_CLEAR ((uint32_t)0X000007D0) + +static const PinMap PinMap_UART_TX[] = { + {PE3, SERIAL_0, PIN_DATA(7, 1)}, + {PH1, SERIAL_1, PIN_DATA(3, 1)}, + {PG1, SERIAL_2, PIN_DATA(3, 1)}, + {PU7, SERIAL_3, PIN_DATA(7, 1)}, + {PU0, SERIAL_4, PIN_DATA(7, 1)}, + {PJ1, SERIAL_5, PIN_DATA(3, 1)}, + {PG4, SERIAL_6, PIN_DATA(5, 1)}, + {PM7, SERIAL_7, PIN_DATA(7, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {PE2, SERIAL_0, PIN_DATA(7, 0)}, + {PH0, SERIAL_1, PIN_DATA(3, 0)}, + {PG0, SERIAL_2, PIN_DATA(3, 0)}, + {PU6, SERIAL_3, PIN_DATA(7, 0)}, + {PU1, SERIAL_4, PIN_DATA(7, 0)}, + {PJ0, SERIAL_5, PIN_DATA(3, 0)}, + {PG5, SERIAL_6, PIN_DATA(5, 0)}, + {PM6, SERIAL_7, PIN_DATA(7, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RTS[] = { + {PE0, SERIAL_0, PIN_DATA(7, 1)}, + {PH2, SERIAL_1, PIN_DATA(3, 1)}, + {PG2, SERIAL_2, PIN_DATA(3, 1)}, + {PU4, SERIAL_3, PIN_DATA(7, 1)}, + {PU3, SERIAL_4, PIN_DATA(5, 1)}, + {PJ2, SERIAL_5, PIN_DATA(3, 1)}, + {PG6, SERIAL_6, PIN_DATA(5, 1)}, + {PM5, SERIAL_7, PIN_DATA(7, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_CTS[] = { + {PE1, SERIAL_0, PIN_DATA(7, 0)}, + {PH3, SERIAL_1, PIN_DATA(3, 0)}, + {PG3, SERIAL_2, PIN_DATA(3, 0)}, + {PU5, SERIAL_3, PIN_DATA(7, 0)}, + {PU2, SERIAL_4, PIN_DATA(5, 0)}, + {PJ3, SERIAL_5, PIN_DATA(3, 0)}, + {PG7, SERIAL_6, PIN_DATA(5, 0)}, + {PM4, SERIAL_7, PIN_DATA(7, 0)}, + {NC, NC, 0} +}; + +static int serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +static void uart_swreset(TSB_UART_TypeDef *UARTx); +static void fuart_init_config(serial_t *obj, FUART_InitTypeDef *InitStruct); + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + int is_stdio_uart = 0; + obj->mode = 0; + cg_t paramCG; + paramCG.p_instance = TSB_CG; + uart_clock_t prescal = {0}; + + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); + + MBED_ASSERT((int)uart_name != NC); + + obj->is_using_fuart = 0; + obj->index = uart_name; + // Initialize UART instance + switch (uart_name) { + case SERIAL_0: + obj->UARTx = TSB_UART0; + // Enable clock for UART0 and Port E + TSB_CG_FSYSMENA_IPMENA23 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB06 = TXZ_ENABLE; + break; + case SERIAL_1: + obj->UARTx = TSB_UART1; + // Enable clock for UART1 and Port H + TSB_CG_FSYSMENA_IPMENA24 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB09 = TXZ_ENABLE; + break; + case SERIAL_2: + obj->UARTx = TSB_UART2; + // Enable clock for UART2 and Port G + TSB_CG_FSYSMENA_IPMENA25 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; + break; + case SERIAL_3: + obj->UARTx = TSB_UART3; + // Enable clock for UART3 and Port U + TSB_CG_FSYSMENA_IPMENA26 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB18 = TXZ_ENABLE; + break; + case SERIAL_4: + obj->UARTx = TSB_UART4; + // Enable clock for UART4 and Port U + TSB_CG_FSYSMENA_IPMENA27 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB18 = TXZ_ENABLE; + break; + case SERIAL_5: + obj->UARTx = TSB_UART5; + // Enable clock for UART5 and Port J + TSB_CG_FSYSMENA_IPMENA28 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; + break; + case SERIAL_6: + obj->FUARTx = TSB_FURT0; + //Enable clock for UART6 and Port G + TSB_CG_FSYSMENA_IPMENA01 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; + obj->is_using_fuart = 1; + break; + case SERIAL_7: + obj->FUARTx = TSB_FURT1; + //Enable clock for UART7 and Port M + TSB_CG_FSYSMENA_IPMENA02 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE; + obj->is_using_fuart = 1; + break; + default: + break; + } + + // Set alternate function + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (!(obj->is_using_fuart)) { + if (tx != NC && rx != NC) { + obj->mode = UART_ENABLE_RX | UART_ENABLE_TX; + } else { + if (tx != NC) { + obj->mode = UART_ENABLE_TX; + } else { + if (rx != NC) { + obj->mode = UART_ENABLE_RX; + } + } + } + //software reset + uart_swreset(obj->UARTx); + //mbed default configurations + obj->UARTx->CR0 |= (1U); // data lengh 8 bit No parity one stop bit + prescal.prsel = UART_PLESCALER_1; + uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, BAUDRATE_DEFAULT, &obj->boud_obj); + obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); + obj->UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); // Clear FIFO + obj->UARTx->TRANS |= obj->mode; // Enable TX RX block. + obj->UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); + } else { + if (tx != NC && rx != NC) { + obj->fuart_config.Mode = FUARTxCR_TXE_ENABLE | FUARTxCR_RXE_ENABLE; + } else if (tx != NC) { + obj->fuart_config.Mode = FUARTxCR_TXE_ENABLE; + } else if (rx != NC) { + obj->fuart_config.Mode = FUARTxCR_RXE_ENABLE; + } + + obj->fuart_config.BaudRate = BAUDRATE_DEFAULT; + obj->fuart_config.DataBits = FUART_DATA_LENGTH_8; + obj->fuart_config.StopBits = FUART_STOP_BIT_1; + obj->fuart_config.Parity = FUART_PARITY_DISABLE; + obj->fuart_config.FlowCtrl = FUART_CTS_DISABLE | FUART_RTS_DISABLE; + + fuart_get_boudrate_setting(cg_get_mphyt0(¶mCG), obj->fuart_config.BaudRate, &obj->boudrate); + + fuart_init_config(obj, &obj->fuart_config); + //Enable FUART + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + } + + is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + if (!(obj->is_using_fuart)) { + obj->UARTx->TRANS = CLR_REGISTER; + obj->UARTx->CR0 = CLR_REGISTER; + obj->UARTx->CR1 = CLR_REGISTER; + obj->UARTx = CLR_REGISTER; + uart_swreset(obj->UARTx); + } else { + obj->FUARTx->CR = CLR_REGISTER; + obj->FUARTx->IMSC = CLR_REGISTER; + obj->FUARTx->ICR = CLR_REGISTER; + obj->FUARTx->LCR_H = CLR_REGISTER; + obj->FUARTx = CLR_REGISTER; + } + obj->index = (uint32_t)NC; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + cg_t paramCG; + paramCG.p_instance = TSB_CG; + uart_clock_t prescal; + if (!(obj->is_using_fuart)) { + prescal.prsel = UART_PLESCALER_1; + uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, baudrate, &obj->boud_obj); + obj->UARTx->BRD = CLR_REGISTER; //clear BRD register + obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); + } else { + obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR; + obj->fuart_config.BaudRate = baudrate; + fuart_get_boudrate_setting(cg_get_mphyt0(¶mCG), obj->fuart_config.BaudRate, &obj->boudrate); + fuart_init_config(obj, &obj->fuart_config); + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + + } +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + uint32_t parity_check = 0; + uint32_t data_length = 0; + uint32_t tmp = 0; + uint32_t sblen = 0; + + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); + + if (!(obj->is_using_fuart)) { + MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits + parity_check = ((parity == ParityOdd) ? 1 : ((parity == ParityEven) ? 3 : 0)); + data_length = (data_bits == 8 ? 1 : ((data_bits == 7) ? 0 : 2)); + sblen = (stop_bits == 1) ? 0 : 1; // 0: 1 stop bits, 1: 2 stop bits + tmp = ((sblen << 4) | (parity_check << 2) | data_length); + obj->UARTx->CR0 = tmp; + } else { + MBED_ASSERT((data_bits > 6) && (data_bits < 9)); // 0: 5 data bits ... 2: 8 data bits + obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR; + // Parity bit update + if (parity == ParityOdd) { + obj->fuart_config.Parity = FUART_PARITY_BIT_ODD | FUART_PARITY_ENABLE; + } else if (parity == ParityEven) { + obj->fuart_config.Parity = FUART_PARITY_BIT_EVEN | FUART_PARITY_ENABLE; + } else { + obj->fuart_config.Parity = FUART_PARITY_DISABLE; + } + // Stop bit update + obj->fuart_config.StopBits = (stop_bits == 1) ? FUART_STOP_BIT_1 : FUART_STOP_BIT_2; + // Data length update + obj->fuart_config.DataBits = (data_bits == 7) ? FUART_DATA_LENGTH_7 : FUART_DATA_LENGTH_8; + + fuart_init_config(obj, &obj->fuart_config); + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + } +} + +// INTERRUPT HANDLING +void INTUART0RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], RxIrq); +} + +void INTUART0TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], TxIrq); +} + +void INTUART1RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], RxIrq); +} + +void INTUART1TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], TxIrq); +} + +void INTUART2RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_2], RxIrq); +} + +void INTUART2TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_2], TxIrq); +} + +void INTUART3RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_3], RxIrq); +} + +void INTUART3TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_3], TxIrq); +} + +void INTUART4RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_4], RxIrq); +} + +void INTUART4TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_4], TxIrq); +} + +void INTUART5RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_5], RxIrq); +} + +void INTUART5TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_5], TxIrq); +} + +void INTFUART0_IRQHandler(void) +{ + uint32_t int_status; + + int_status = TSB_FURT0->MIS; + if (int_status & (1 << 4U)) { + TSB_FURT0->ICR = int_status & FUARTxMIS_RXMIS_MASK; + irq_handler(serial_irq_ids[SERIAL_6], RxIrq); + } else if (int_status & (1 << 5U)) { + TSB_FURT0->ICR = int_status & FUARTxMIS_TXMIS_MASK; + irq_handler(serial_irq_ids[SERIAL_6], TxIrq); + } else { + return; + } +} + +void INTFUART1_IRQHandler(void) +{ + uint32_t int_status; + + int_status = TSB_FURT1->MIS; + if (int_status & (1 << 4U)) { + irq_handler(serial_irq_ids[SERIAL_7], RxIrq); + } else if (int_status & (1 << 5U)) { + irq_handler(serial_irq_ids[SERIAL_7], TxIrq); + } else { + return; + } +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + uint32_t tmp = 0U; + IRQn_Type irq_n = (IRQn_Type)0; + + switch (obj->index) { + case SERIAL_0: + if (irq == RxIrq) { + irq_n = INTUART0RX_IRQn; + } else { + irq_n = INTUART0TX_IRQn; + } + break; + case SERIAL_1: + if (irq == RxIrq) { + irq_n = INTUART1RX_IRQn; + } else { + irq_n = INTUART1TX_IRQn; + } + break; + case SERIAL_2: + if (irq == RxIrq) { + irq_n = INTUART2RX_IRQn; + } else { + irq_n = INTUART2TX_IRQn; + } + break; + case SERIAL_3: + if (irq == RxIrq) { + irq_n = INTUART3RX_IRQn; + } else { + irq_n = INTUART3TX_IRQn; + } + break; + case SERIAL_4: + if (irq == RxIrq) { + irq_n = INTUART4RX_IRQn; + } else { + irq_n = INTUART4TX_IRQn; + } + break; + case SERIAL_5: + if (irq == RxIrq) { + irq_n = INTUART5RX_IRQn; + } else { + irq_n = INTUART5TX_IRQn; + } + break; + case SERIAL_6: + irq_n = INTFUART0_IRQn; + break; + case SERIAL_7: + irq_n = INTFUART1_IRQn; + break; + default: + break; + } + + if (obj->is_using_fuart) { + // Set interrupt mask + if (enable) { + if (irq == RxIrq) { + obj->FUARTx->IMSC |= (1 << 4U); + } else { + obj->FUARTx->IMSC |= (1 << 5U); + } + } else { + if (irq == RxIrq) { + tmp = obj->FUARTx->IMSC; + tmp &= IMSC_RXIM_CLEAR; /* Disable Receive interrupt */ + obj->FUARTx->IMSC = tmp; + } else { + tmp = obj->FUARTx->IMSC; + tmp &= IMSC_TXIM_CLEAR; /* Disable Transmit interrupt */ + obj->FUARTx->IMSC = tmp; + } + } + } + NVIC_ClearPendingIRQ(irq_n); + + if (enable) { + NVIC_EnableIRQ(irq_n); + } else { + if (!obj->is_using_fuart) { + NVIC_DisableIRQ(irq_n); + } + } +} + +int serial_getc(serial_t *obj) +{ + int data = 0; + + while (!serial_readable(obj)) { // Wait until Rx buffer is full + // Do nothing + } + + if (!(obj->is_using_fuart)) { + //Read Data Register + data = (obj->UARTx->DR & 0xFFU); + obj->UARTx->SR |= (1U << 6); // clear RXEND flag + } else { + data = (obj->FUARTx->DR & 0xFFU); + } + + return data; +} + +void serial_putc(serial_t *obj, int c) +{ + while (!serial_writable(obj)) { + // Do nothing + } + + // Write Data Register + if (!(obj->is_using_fuart)) { + obj->UARTx->DR = (c & 0xFF); + + while ((obj->UARTx->SR & (1U << 14)) == 0) { + } + + obj->UARTx->SR |= (1U << 14); // clear TXEND flag + } else { + obj->FUARTx->DR = (c & 0xFF); + } +} + +int serial_readable(serial_t *obj) +{ + int ret = 0; + + if (!(obj->is_using_fuart)) { + if ((obj->UARTx->SR & 0x000F) != 0) { + ret = 1; + } + } else { + if (obj->FUARTx->FR & (1 << 6U)) { + ret = 1; + } + } + + return ret; +} + +int serial_writable(serial_t *obj) +{ + int ret = 0; + + if (!(obj->is_using_fuart)) { + if ((obj->UARTx->SR & 0x8000) == 0) { + ret = 1; + } + } else { + if (obj->FUARTx->FR & (1 << 7U)) { + ret = 1; + } + } + + return ret; +} + +void serial_clear(serial_t *obj) +{ + uint32_t dummy; + if (!(obj->is_using_fuart)) { + obj->UARTx->FIFOCLR = 0x03; + } else { + { + dummy = obj->FUARTx->DR; //dummy read + (void)dummy; + } + } +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +// Set flow control +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts); + + if (!(obj->is_using_fuart)) { + if (type == FlowControlCTS) { + MBED_ASSERT(uart_cts != (UARTName) NC); + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function + pin_mode(txflow, PullUp); // initial state of CTS preferably high + obj->UARTx->CR0 |= (1 << 10); // Enable CTS hardware control + + } else if (type == FlowControlRTS) { + MBED_ASSERT(uart_rts != (UARTName) NC); + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + obj->UARTx->CR0 |= (1 << 9); // Enable RTS hardware control + + } else if (type == FlowControlRTSCTS) { + MBED_ASSERT(uart_name != (UARTName) NC); + obj->UARTx->CR0 |= (3 << 9); // Enable CTS and RTS hardware flow control + + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + pin_mode(txflow, PullUp); + } else { + obj->UARTx->CR0 &= (~(3 << 9)); // Disable CTS and RTS hardware flow control + } + } else { + obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR; // Disable FUART + if (type == FlowControlCTS) { + MBED_ASSERT(uart_cts != (UARTName) NC); + obj->FUARTx->CR |= FUART_CTS_ENABLE; // Enable CTS hardware flow control + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS and RTS function + pin_mode(txflow, PullUp); + + } else if (type == FlowControlRTS) { + MBED_ASSERT(uart_rts != (UARTName) NC); + obj->FUARTx->CR |= FUART_RTS_ENABLE; // Enable RTS hardware flow control + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + + } else if (type == FlowControlRTSCTS) { + MBED_ASSERT(uart_name != (UARTName) NC); + obj->FUARTx->CR |= (FUART_CTS_ENABLE | FUART_RTS_ENABLE); // Enable CTS and RTS hardware flow control + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + pin_mode(txflow, PullUp); + + } else { + obj->FUARTx->CR &= FUART_CTS_RTS_DISABLE_MASK; // Disable CTS and RTS hardware flow control + } + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + } +} + +// Pause transmission +void serial_break_set(serial_t *obj) +{ + if (!(obj->is_using_fuart)) { + obj->UARTx->TRANS |= 0x08; + } else { + obj->FUARTx->LCR_H |= FUARTxLCR_H_BRK_SEND; + } +} + +// Switch to normal transmission +void serial_break_clear(serial_t *obj) +{ + if (!(obj->is_using_fuart)) { + obj->UARTx->TRANS &= ~(0x08); + } else { + obj->FUARTx->LCR_H &= ~(FUARTxLCR_H_BRK_SEND); + } +} + +static void uart_swreset(TSB_UART_TypeDef *UARTx) +{ + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } + + UARTx->SWRST = UARTxSWRST_SWRST_10; + UARTx->SWRST = UARTxSWRST_SWRST_01; + + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } +} + +static void fuart_init_config(serial_t *obj, FUART_InitTypeDef *InitStruct) +{ + uint32_t tmp = 0U; + + + obj->FUARTx->BRD = obj->boudrate.brn; + obj->FUARTx->FBRD = obj->boudrate.brk; + + tmp = obj->FUARTx->LCR_H; + + tmp &= LCR_H_WLEN_MASK; + tmp |= InitStruct->DataBits; + + tmp &= LCR_H_STP2_MASK; + tmp |= InitStruct->StopBits; + + tmp &= LCR_H_PARITY_MASK; + tmp |= InitStruct->Parity; + + obj->FUARTx->LCR_H = tmp; //Set DataBits, StopBits, Parity + + tmp = obj->FUARTx->IMSC; + tmp &= IMSC_TXIM_RXIM_MASK; + tmp |= (FUART_TX_INT_ENABLE | FUART_RX_INT_ENABLE); + obj->FUARTx->IMSC = tmp; + + tmp = obj->FUARTx->CR; + tmp &= CR_FLOW_CTRL_MASK; + tmp |= InitStruct->FlowCtrl; + + tmp &= CR_MODE_MASK; + tmp |= InitStruct->Mode; + + obj->FUARTx->CR = tmp; +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ + return PinMap_UART_RTS; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/sleep.c new file mode 100644 index 00000000000..692e9414dfa --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/sleep.c @@ -0,0 +1,126 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" + +// Number of warm-up cycle = (warming up time (s) / clock period (s)) - 16 +#define CG_WUODR_INT_5MS ((uint16_t)0x0C34) +#define CG_STBY_MODE_IDLE 0x0 +#define CG_STBY_MODE_STOP1 0x1 +#define EXTERNEL_OSC_MASK 0xFFFFFFF1 +#define SIWDT_DISABLE 0xB1 +#define WUPT_LOWER_MASK 0x000F +#define WUPT_UPPER_MASK 0xFFF0 + +static void external_losc_enable(void); + +void hal_sleep(void) +{ + // Set low power consumption mode IDLE + TSB_CG->STBYCR = CG_STBY_MODE_IDLE; + + // Enter idle mode + __DSB(); + __WFI(); +} + +void hal_deepsleep(void) +{ + uint32_t wupt_lower = 0; + uint32_t wupt_upper = 0; + uint32_t tmp = 0; + + TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE; + + TSB_SIWD0->EN = TXZ_DISABLE; + TSB_SIWD0->CR = SIWDT_DISABLE; + + + while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) { + // Flash wait + } + + while (TSB_CG_WUPHCR_WUEF) { + // Wait for end of Warming-up for IHOSC1 + } + + TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE; + wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U); + wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U); + TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); + TSB_CG->STBYCR = CG_STBY_MODE_STOP1; + TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE; + + + while (TSB_CG_PLL0SEL_PLL0ST) { + // Wait for PLL status of fsys until off state(fosc=0) + } + + // Stop PLL of fsys + TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE; + TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE; + TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE; + + while (TSB_CG_OSCCR_OSCF) { + // Wait for fosc status until IHOSC1 = 0 + } + + tmp = TSB_CG->OSCCR; + tmp &= EXTERNEL_OSC_MASK; + TSB_CG->OSCCR = tmp; + + + // Enter stop1 mode + __DSB(); + __WFI(); + + // Switch over from IHOSC to EHOSC + // After coming out off sleep mode, Restore the clock setting to EHOSC. + external_losc_enable(); +} + +static void external_losc_enable(void) +{ + uint32_t wupt_lower = 0; + uint32_t wupt_upper = 0; + + // Enable high-speed oscillator + TSB_CG->OSCCR |= (TXZ_ENABLE << 1); + + // Select internal(fIHOSC) as warm-up clock + wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U); + wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U); + TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); + + // Start warm-up + TSB_CG->WUPHCR |= TXZ_ENABLE; + + // Wait until EHOSC become stable + while ((TSB_CG->WUPHCR & 0x0002)) { + // Do nothing + } + + // Set fosc source + TSB_CG->OSCCR |= (1 << 8); + + // Wait for to become "1" + while (!((TSB_CG->OSCCR & 0x200) >> 9)) { + // Do nothing + } + + // Stop IHOSC + TSB_CG->OSCCR &= ~TXZ_ENABLE; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/spi_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/spi_api.c new file mode 100644 index 00000000000..7ebaef77823 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/spi_api.c @@ -0,0 +1,678 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "spi_api.h" +#include "mbed_error.h" +#include "txz_tspi.h" +#include "pinmap.h" + +#define TIMEOUT 5000 +#define INITIAL_SPI_FREQ 1000000 + +#if DEVICE_SPI_ASYNCH +#define SPI_S(obj) (struct spi_s *) (&((obj)->spi)) +#else +#define SPI_S(obj) (struct spi_s *) (obj) +#endif + +#if DEVICE_SPI_ASYNCH +static void spi_irq_handler(spi_t *obj); +static void disable_irq(uint32_t irqn); +static void clear_irq(uint32_t irqn); +enum { + SPI_TRANSFER_STATE_IDLE = 0U, + SPI_TRANSFER_STATE_BUSY +} SPI_TransferState; +typedef struct { + IRQn_Type Tx; + IRQn_Type Rx; + IRQn_Type Error; +} spi_irq_t; +static const spi_irq_t SPI_CH0_IRQN_TBL[1] = { + { INTT0RX_IRQn, INTT0TX_IRQn, INTT0ERR_IRQn } +}; +static const spi_irq_t SPI_CH1_IRQN_TBL[1] = { + { INTT1RX_IRQn, INTT1TX_IRQn, INTT1ERR_IRQn } +}; +static const spi_irq_t SPI_CH2_IRQN_TBL[1] = { + { INTT2RX_IRQn, INTT2TX_IRQn, INTT2ERR_IRQn } +}; +static const spi_irq_t SPI_CH3_IRQN_TBL[1] = { + { INTT3RX_IRQn, INTT3TX_IRQn, INTT3ERR_IRQn } +}; +static const spi_irq_t SPI_CH4_IRQN_TBL[1] = { + { INTT4RX_IRQn, INTT4TX_IRQn, INTT4ERR_IRQn } +}; +static const spi_irq_t SPI_CH5_IRQN_TBL[1] = { + { INTT5RX_IRQn, INTT5TX_IRQn, INTT5ERR_IRQn } +}; +static const spi_irq_t SPI_CH6_IRQN_TBL[1] = { + { INTT6RX_IRQn, INTT6TX_IRQn, INTT6ERR_IRQn } +}; +static const spi_irq_t SPI_CH7_IRQN_TBL[1] = { + { INTT7RX_IRQn, INTT7TX_IRQn, INTT7ERR_IRQn } +}; +static const spi_irq_t SPI_CH8_IRQN_TBL[1] = { + { INTT8RX_IRQn, INTT8TX_IRQn, INTT8ERR_IRQn } +}; +#endif + +static const PinMap PinMap_SPI_SCLK[] = { + {PA1, SPI_0, PIN_DATA(7, 1)}, + {PL1, SPI_1, PIN_DATA(7, 1)}, + {PA6, SPI_2, PIN_DATA(7, 1)}, + {PK6, SPI_3, PIN_DATA(4, 1)}, + {PD1, SPI_4, PIN_DATA(4, 1)}, + {PV6, SPI_5, PIN_DATA(4, 1)}, + {PM2, SPI_6, PIN_DATA(6, 1)}, + {PM5, SPI_7, PIN_DATA(6, 1)}, + {PW1, SPI_8, PIN_DATA(4, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SLAVE_SCLK[] = { + {PA1, SPI_0, PIN_DATA(7, 0)}, + {PL1, SPI_1, PIN_DATA(7, 0)}, + {PA6, SPI_2, PIN_DATA(7, 0)}, + {PK6, SPI_3, PIN_DATA(4, 0)}, + {PD1, SPI_4, PIN_DATA(4, 0)}, + {PV6, SPI_5, PIN_DATA(4, 0)}, + {PM2, SPI_6, PIN_DATA(6, 0)}, + {PM5, SPI_7, PIN_DATA(6, 0)}, + {PW1, SPI_8, PIN_DATA(4, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {PA3, SPI_0, PIN_DATA(7, 1)}, + {PL3, SPI_1, PIN_DATA(7, 1)}, + {PA4, SPI_2, PIN_DATA(7, 1)}, + {PK4, SPI_3, PIN_DATA(4, 1)}, + {PD3, SPI_4, PIN_DATA(4, 1)}, + {PV5, SPI_5, PIN_DATA(4, 1)}, + {PM0, SPI_6, PIN_DATA(6, 1)}, + {PM7, SPI_7, PIN_DATA(6, 1)}, + {PW3, SPI_8, PIN_DATA(4, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {PA2, SPI_0, PIN_DATA(7, 0)}, + {PL2, SPI_1, PIN_DATA(7, 0)}, + {PA5, SPI_2, PIN_DATA(7, 0)}, + {PK5, SPI_3, PIN_DATA(4, 0)}, + {PD2, SPI_4, PIN_DATA(4, 0)}, + {PV4, SPI_5, PIN_DATA(4, 0)}, + {PM1, SPI_6, PIN_DATA(6, 0)}, + {PM6, SPI_7, PIN_DATA(6, 0)}, + {PW2, SPI_8, PIN_DATA(4, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {PA0, SPI_0, PIN_DATA(7, 2)}, + {PL0, SPI_1, PIN_DATA(7, 2)}, + {PA7, SPI_2, PIN_DATA(7, 2)}, + {PK7, SPI_3, PIN_DATA(4, 2)}, + {PD0, SPI_4, PIN_DATA(4, 2)}, + {PV7, SPI_5, PIN_DATA(4, 2)}, + {PM3, SPI_6, PIN_DATA(6, 2)}, + {PM4, SPI_7, PIN_DATA(6, 2)}, + {PW0, SPI_8, PIN_DATA(4, 2)}, + {NC, NC, 0} +}; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + struct spi_s *obj_s = SPI_S(obj); + // Check pin parameters + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + + obj_s->module = (SPIName)pinmap_merge(spi_data, spi_sclk); + obj_s->module = (SPIName)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj_s->module != NC); + + // Identify SPI module to use + switch ((int)obj_s->module) { + case SPI_0: + obj_s->p_obj.p_instance = TSB_TSPI0; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA04 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH0_IRQN_TBL; +#endif + break; + case SPI_1: + obj_s->p_obj.p_instance = TSB_TSPI1; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA05 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB12 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH1_IRQN_TBL; +#endif + break; + case SPI_2: + obj_s->p_obj.p_instance = TSB_TSPI2; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA06 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH2_IRQN_TBL; +#endif + break; + case SPI_3: + obj_s->p_obj.p_instance = TSB_TSPI3; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA07 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB11 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH3_IRQN_TBL; +#endif + break; + case SPI_4: + obj_s->p_obj.p_instance = TSB_TSPI4; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA08 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB05 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH4_IRQN_TBL; +#endif + break; + case SPI_5: + obj_s->p_obj.p_instance = TSB_TSPI5; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA09 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB19 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH5_IRQN_TBL; +#endif + break; + case SPI_6: + obj_s->p_obj.p_instance = TSB_TSPI6; + // Enable clock for particular Port and SPI + TSB_CG_FSYSMENA_IPMENA20 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH6_IRQN_TBL; +#endif + break; + case SPI_7: + obj_s->p_obj.p_instance = TSB_TSPI7; + // Enable clock for particular Port and SPI + TSB_CG_FSYSMENA_IPMENA21 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH7_IRQN_TBL; +#endif + break; + case SPI_8: + obj_s->p_obj.p_instance = TSB_TSPI8; + // Enable clock for particular Port and SPI + TSB_CG_FSYSMENA_IPMENA22 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB20 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH8_IRQN_TBL; +#endif + break; + default: + obj_s->p_obj.p_instance = NULL; + obj_s->module = (SPIName)NC; + error("Cannot found SPI module corresponding with input pins."); + break; + } + + // Pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + obj_s->Slave_SCK = sclk; + + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } + + // Default configurations 8 bit, 1Mhz frequency + // Control 1 configurations + obj_s->p_obj.init.id = (uint32_t)obj_s->module; + obj_s->p_obj.init.cnt1.inf = TSPI_INF_DISABLE; // Infinite Transfer Control disabled + obj_s->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled + obj_s->p_obj.init.cnt1.trxe = TSPI_TRXE_DISABLE; // Enable Communication + obj_s->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode + obj_s->p_obj.init.cnt1.mstr = TSPI_MASTER_OPERATION; // master mode operation + obj_s->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive) + obj_s->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid + obj_s->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_CONTINUE;// transfer single frame at a time continuously + + //Control 2 configurations + obj_s->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI; + obj_s->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low + obj_s->p_obj.init.cnt2.rxdly = TSPI_RXDLY_8CLK; + obj_s->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level + obj_s->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level + obj_s->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE; + obj_s->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE; + obj_s->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE; + obj_s->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE; + obj_s->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE; + obj_s->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE; + obj_s->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE; + + //Control 3 configurations + obj_s->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear + obj_s->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear + + //baudrate settings - 1Mhz default + spi_frequency(obj_s, (int)INITIAL_SPI_FREQ); + + //Format Control 0 settings + obj_s->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first + obj_s->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8; + obj_s->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0; + + //Special control on polarity of signal and generation timing + obj_s->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE; + obj_s->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE; + obj_s->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE; + obj_s->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE; + + obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + obj_s->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1; + obj_s->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1; + obj_s->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1; + + //Format Control 1 settings tspi_fmtr1_t + obj_s->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE; + obj_s->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD; + + obj_s->p_obj.init.scr0.sect = TSPI_SECT_MODE_FRAME; + + obj_s->bits = (uint8_t)TSPI_DATA_LENGTH_8; + + //initialize SPI + tspi_init(&obj_s->p_obj); +} + +void spi_free(spi_t *obj) +{ + struct spi_s *obj_s = SPI_S(obj); + + tspi_deinit(&obj_s->p_obj); + obj_s->module = (SPIName)NC; +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + struct spi_s *obj_s = SPI_S(obj); + + MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode + MBED_ASSERT((bits >= 8) && (bits <= 32)); + + obj_s->bits = bits; + obj_s->p_obj.init.fmr0.fl = (bits << 24); + + + if ((mode >> 1) & 0x1) { + obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI; + } else { + obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + } + + if (mode & 0x1) { + obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE; + } else { + obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + } + + if (slave) { + pinmap_pinout(obj_s->Slave_SCK, PinMap_SPI_SLAVE_SCLK); + obj_s->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation + } + tspi_init(&obj_s->p_obj); +} + +void spi_frequency(spi_t *obj, int hz) +{ + struct spi_s *obj_s = SPI_S(obj); + + + uint8_t brs = 0; + uint8_t brck = 0; + uint16_t prsck = 1; + uint64_t fscl = 0; + uint64_t tmp_fscl = 0; + uint64_t fx = 0; + uint64_t tmpvar = SystemCoreClock; + + SystemCoreClockUpdate(); + tmpvar = tmpvar / 2; + for (prsck = 1; prsck <= 512; prsck *= 2) { + fx = ((uint64_t)tmpvar / prsck); + for (brs = 1; brs <= 16; brs++) { + fscl = fx / brs; + if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + obj_s->p_obj.init.brd.brck = (brck << 4); + if (brs == 16) { + obj_s->p_obj.init.brd.brs = 0; + } else { + obj_s->p_obj.init.brd.brs = brs; + } + } + } + brck ++; + } + + tspi_init(&obj_s->p_obj); +} + +int spi_master_write(spi_t *obj, int value) +{ + struct spi_s *obj_s = SPI_S(obj); + uint8_t ret_value = 0; + + tspi_transmit_t send_obj; + tspi_receive_t rec_obj; + + // Transmit data + send_obj.tx8.p_data = (uint8_t *)&value; + send_obj.tx8.num = 1; + tspi_master_write(&obj_s->p_obj, &send_obj, TIMEOUT); + + // Read received data + rec_obj.rx8.p_data = &ret_value; + rec_obj.rx8.num = 1; + tspi_master_read(&obj_s->p_obj, &rec_obj, TIMEOUT); + + return ret_value; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) +{ + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +int spi_busy(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + int ret = 1; + uint32_t status = 0; + tspi_get_status(&obj->p_obj, &status); + if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) { + ret = 0; + } + + return ret; +} + +int spi_slave_receive(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + int ret = 1; + uint32_t status; + + tspi_get_status(&obj->p_obj, &status); + if ((status & (TSPI_RX_REACH_FILL_LEVEL_MASK)) == 0) { + ret = 0; + } + return ret; +} + +int spi_slave_read(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + uint8_t ret_value = 0; + ret_value = obj->p_obj.p_instance->DR & 0xFF; + obj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR; + obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + + return ret_value; +} + +void spi_slave_write(spi_t *t_obj, int value) +{ + struct spi_s *obj = SPI_S(t_obj); + + // Enable TSPI Transmission Control. + obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + obj->p_obj.p_instance->DR = value & 0xFF; + +} + +uint8_t spi_get_module(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + return (uint8_t)(obj->module); +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SLAVE_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +#if DEVICE_SPI_ASYNCH + +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, + uint32_t handler, uint32_t event, DMAUsage hint) +{ + struct spi_s *spiobj = SPI_S(obj); + spi_irq_t *p_irqn = (spi_irq_t *)spiobj->irqn; + + + // check which use-case we have + bool use_tx = (tx != NULL && tx_length > 0); + bool use_rx = (rx != NULL && rx_length > 0); + + // don't do anything, if the buffers aren't valid + if (!use_tx && !use_rx) { + return; + } + + disable_irq(spiobj->irqn); + spiobj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + clear_irq(spiobj->irqn); + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + + obj->rx_buff.buffer = (void *)rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; + spiobj->event = 0; + spiobj->state = SPI_TRANSFER_STATE_IDLE; + + + NVIC_SetVector(p_irqn->Error, (uint32_t)handler); + NVIC_SetVector(p_irqn->Tx, (uint32_t)handler); + NVIC_SetVector(p_irqn->Rx, (uint32_t)handler); + + // Enable Error Interrupt, Receive complete interrupt and Transmit complete interrupt + spiobj->p_obj.p_instance->CR2 |= (TSPI_TX_INT_ENABLE | TSPI_RX_INT_ENABLE | TSPI_ERR_INT_ENABLE); + + if (use_tx && use_rx) { + spiobj->max_size = tx_length < rx_length ? rx_length : tx_length; + spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF; + } else if (use_tx) { + spiobj->max_size = tx_length; + spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF; + // Enable Interrupt bit in SPI peripheral - Enabled in init() + } else if (use_rx) { + spiobj->max_size = rx_length; + spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + spiobj->p_obj.p_instance->DR = 0xFF; + } + spiobj->state = SPI_TRANSFER_STATE_BUSY; + NVIC_EnableIRQ(p_irqn->Error); + NVIC_EnableIRQ(p_irqn->Tx); + NVIC_EnableIRQ(p_irqn->Rx); +} +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + spi_irq_handler(obj); + return ((spiobj->event & SPI_EVENT_ALL) | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) ; +} + +uint8_t spi_active(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + uint8_t ret_val = 0; + if (spiobj->state != SPI_TRANSFER_STATE_IDLE) { + ret_val = 1; + } + + return ret_val; +} + +void spi_abort_asynch(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + + disable_irq(spiobj->irqn); + clear_irq(spiobj->irqn); + tspi_init(&spiobj->p_obj); +} + +static void spi_irq_handler(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + if ((spiobj->p_obj.p_instance->SR & TSPI_RX_DONE) && + (spiobj->p_obj.p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK)) { + uint8_t rlvl = spiobj->p_obj.p_instance->SR & 0xF; + + while ((rlvl != 0) && (obj->rx_buff.pos < obj->rx_buff.length)) { + ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos++] = spiobj->p_obj.p_instance->DR & 0xFF; + rlvl--; + // transmit complete but receive pending - dummy write + } + + if (obj->rx_buff.pos == spiobj->max_size) { + spiobj->state = SPI_TRANSFER_STATE_IDLE; + } + spiobj->p_obj.p_instance->CR3 |= TSPI_RX_BUFF_CLR_DONE; + } + + if (spiobj->p_obj.p_instance->SR & TSPI_TX_DONE) { + + obj->tx_buff.pos++; + spiobj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR; + + if (obj->tx_buff.pos == (spiobj->max_size)) { + spiobj->state = SPI_TRANSFER_STATE_IDLE; + } + if ((obj->tx_buff.pos < obj->tx_buff.length) && (obj->tx_buff.pos < spiobj->max_size)) { + spiobj->p_obj.p_instance->DR = (((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF); + } else if (obj->tx_buff.pos < spiobj->max_size) { + spiobj->p_obj.p_instance->DR = 0xFF; + } + } + + if (spiobj->p_obj.p_instance->ERR) { + spiobj->event = SPI_EVENT_ERROR; + spiobj->state = SPI_TRANSFER_STATE_IDLE; + disable_irq(spiobj->irqn); + spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + clear_irq(spiobj->irqn); + return; + } + + if (spiobj->state == SPI_TRANSFER_STATE_IDLE) { + spiobj->event = SPI_EVENT_COMPLETE; + disable_irq(spiobj->irqn); + spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + clear_irq(spiobj->irqn); + } + + +} + +static void disable_irq(uint32_t irqn) +{ + spi_irq_t *p_irqn = (spi_irq_t *)irqn; + NVIC_DisableIRQ(p_irqn->Tx); + NVIC_DisableIRQ(p_irqn->Rx); + NVIC_DisableIRQ(p_irqn->Error); +} + +static void clear_irq(uint32_t irqn) +{ + spi_irq_t *p_irqn = (spi_irq_t *)irqn; + NVIC_ClearPendingIRQ(p_irqn->Tx); + NVIC_ClearPendingIRQ(p_irqn->Rx); + NVIC_ClearPendingIRQ(p_irqn->Error); + + //clean-up +} + +#endif //DEVICE_SPI_ASYNCH diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/us_ticker.c new file mode 100644 index 00000000000..13caede6dde --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/us_ticker.c @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "us_ticker_api.h" +#include "TMPM4GR.h" +#include "txz_t32a.h" + +#define CLR_TIMER_INT_FLAG (uint8_t)0x41 + +static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? + +const ticker_info_t *us_ticker_get_info() +{ + static const ticker_info_t info = { + 3000000, + 32 + }; + return &info; +} + +// Initialize us_ticker +void us_ticker_init(void) +{ + if (us_ticker_inited) { + us_ticker_disable_interrupt(); + return; + } + us_ticker_inited = 1; + + // Enable clock for T32A0 + TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE; + + // T32A ch0 TimerC Reg Match/Over Flow/Under Flow + TSB_IB->IMC006 = TXZ_ENABLE; + + // Configure Timer T32A0 + TSB_T32A0->MOD = T32A_MODE_32; + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->CRC = T32A_PRSCLx_32; + TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); + + NVIC_SetVector(INTT32A00_A_CT_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); +} + +uint32_t us_ticker_read(void) +{ + uint32_t ret_val = 0; + + if (!us_ticker_inited) { + us_ticker_init(); + } + + ret_val = (TSB_T32A0->TMRC); + return ret_val; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->RGC1 = timestamp ; + NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(INTT32A00_A_CT_IRQn); + NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); +} + +void us_ticker_disable_interrupt(void) +{ + // Disable interrupts in NVIC + TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; + NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); + NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); +} + +void us_ticker_clear_interrupt(void) +{ + TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; + NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); +} + +void us_ticker_free(void) +{ + TSB_T32A0->RUNC = T32A_RUN_DISABLE; + TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; + NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); + NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); + TSB_CG_FSYSMENA_IPMENA06 = TXZ_DISABLE; +} diff --git a/targets/TARGET_TOSHIBA/mbed_rtx.h b/targets/TARGET_TOSHIBA/mbed_rtx.h index df3a520c4fd..51f17763a0c 100644 --- a/targets/TARGET_TOSHIBA/mbed_rtx.h +++ b/targets/TARGET_TOSHIBA/mbed_rtx.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library * - * Copyright (C) 2019, Toshiba Electronic Device Solutions Corporation + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 * * SPDX-License-Identifier: Apache-2.0 * @@ -52,4 +52,12 @@ #endif +#if defined(TARGET_TMPM4GR) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20040000UL) +#endif + +#endif + #endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index 6d80f0ea7e0..3d8f30d3c45 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9465,6 +9465,64 @@ "small" ] } + }, + "TMPM4GR": { + "inherits": [ + "Target" + ], + "core": "Cortex-M4F", + "is_disk_virtual": true, + "extra_labels": [ + "TOSHIBA" + ], + "macros": [ + "__TMPM4GR__" + ], + "supported_toolchains": [ + "GCC_ARM", + "ARM" + ], + "device_has": [ + "ANALOGIN", + "ANALOGOUT", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "RESET_REASON", + "SERIAL", + "SERIAL_FC", + "SPI", + "SPISLAVE", + "SPI_ASYNCH", + "I2C", + "I2CSLAVE", + "I2C_ASYNCH", + "RTC", + "STDIO_MESSAGES", + "FLASH", + "SLEEP", + "USTICKER", + "MPU" - } + ], + "device_name": "TMPM4GRF20FG", + "detect_code": [ + "7021" + ], + "release_versions": [ + "5" + ], + "bootloader_supported": true, + "supported_c_libs": { + "arm": [ + "std", + "small" + ], + "gcc_arm": [ + "std", + "small" + ] + } } diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index e6855ccf9cd..d4496c12771 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -504580,6 +504580,86 @@ "family": "TXZ4A+ Series", "sub_family": "M4N(1)" }, + "TMPM4GRF20FG": { + "algorithms": [ + { + "default": true, + "file_name": "Flash/TMPM4Gx_code_2048.FLM", + "ram_size": 8192, + "ram_start": 536870912, + "size": 2097152, + "start": 0 + }, + { + "default": true, + "file_name": "Flash/TMPM4Gx_data_32.FLM", + "ram_size": 8192, + "ram_start": 536870912, + "size": 32768, + "start": 805306368 + } + ], + "family": "TXZ4A+ Series", + "from_pack": { + "pack": "TXZ4Aplus-M4G1_DFP", + "url": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/", + "vendor": "Toshiba", + "version": "1.0.1" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 262144, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 2097152, + "start": 0, + "startup": true + } + }, + "name": "TMPM4GRF20FG", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 0, + 4096 + ], + [ + 805306368, + 4096 + ] + ], + "sub_family": "M4G(1)", + "vendor": "Toshiba:92" + }, "XMC1100-Q024x0008": { "algorithms": [ { From e4db5d17b1f4fb577202608232b7d25546bb5acf Mon Sep 17 00:00:00 2001 From: "Deepak V. Shreshti" Date: Thu, 1 Dec 2022 21:27:55 +0530 Subject: [PATCH 2/2] Resolve delimeter issues for target.json --- targets/targets.json | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 3d8f30d3c45..d9dcff871b0 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9407,7 +9407,7 @@ ] } }, - "TMPM4NR": { + "TMPM4NR": { "inherits": [ "Target" ], @@ -9465,6 +9465,7 @@ "small" ] } + }, "TMPM4GR": { "inherits": [ @@ -9505,7 +9506,6 @@ "SLEEP", "USTICKER", "MPU" - ], "device_name": "TMPM4GRF20FG", "detect_code": [ @@ -9524,5 +9524,6 @@ "std", "small" ] + } } }