From 9c5ce840b905c5b894def6c3359823434fa9ac4b Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Wed, 14 Sep 2016 17:06:21 +0200 Subject: [PATCH 1/3] [EFM32] Add IAR support for remaining Silicon Labs targets Added startup files and IAR memory map files for the remaining Silicon Labs targets as part of the mbed enabled criteria. --- hal/targets.json | 10 +- .../TOOLCHAIN_IAR/efm32gg990f1024.icf | 33 ++ .../TOOLCHAIN_IAR/startup_efm32gg.S | 385 +++++++++++++++++ .../TOOLCHAIN_IAR/efm32hg322f64.icf | 33 ++ .../TOOLCHAIN_IAR/startup_efm32hg.s | 257 ++++++++++++ .../TOOLCHAIN_IAR/efm32lg990f256.icf | 33 ++ .../TOOLCHAIN_IAR/startup_efm32lg.s | 386 +++++++++++++++++ .../TOOLCHAIN_IAR/efm32wg990f256.icf | 33 ++ .../TOOLCHAIN_IAR/startup_efm32wg.s | 391 ++++++++++++++++++ .../TOOLCHAIN_IAR/efm32zg222f32.icf | 33 ++ .../TOOLCHAIN_IAR/startup_efm32zg.s | 235 +++++++++++ 11 files changed, 1824 insertions(+), 5 deletions(-) create mode 100644 hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/efm32gg990f1024.icf create mode 100644 hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/startup_efm32gg.S create mode 100644 hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_IAR/efm32hg322f64.icf create mode 100644 hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_IAR/startup_efm32hg.s create mode 100644 hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_IAR/efm32lg990f256.icf create mode 100644 hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_IAR/startup_efm32lg.s create mode 100644 hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_IAR/efm32wg990f256.icf create mode 100644 hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_IAR/startup_efm32wg.s create mode 100644 hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_IAR/efm32zg222f32.icf create mode 100644 hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_IAR/startup_efm32zg.s diff --git a/hal/targets.json b/hal/targets.json index 59ae66fc68e..390103a2be3 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -1776,7 +1776,7 @@ "core": "Cortex-M3", "macros": ["EFM32GG990F1024"], "extra_labels": ["Silicon_Labs", "EFM32"], - "supported_toolchains": ["GCC_ARM", "ARM", "uARM"], + "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "progen": {"target": "efm32gg-stk"}, "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 2, @@ -1787,7 +1787,7 @@ "core": "Cortex-M3", "macros": ["EFM32LG990F256"], "extra_labels": ["Silicon_Labs", "EFM32"], - "supported_toolchains": ["GCC_ARM", "ARM", "uARM"], + "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "progen": {"target": "efm32lg-stk"}, "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 2, @@ -1798,7 +1798,7 @@ "core": "Cortex-M4F", "macros": ["EFM32WG990F256"], "extra_labels": ["Silicon_Labs", "EFM32"], - "supported_toolchains": ["GCC_ARM", "ARM", "uARM"], + "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "progen": {"target": "efm32wg-stk"}, "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 2, @@ -1808,7 +1808,7 @@ "inherits": ["Target"], "core": "Cortex-M0+", "default_toolchain": "uARM", - "supported_toolchains": ["GCC_ARM", "uARM"], + "supported_toolchains": ["GCC_ARM", "uARM", "IAR"], "extra_labels": ["Silicon_Labs", "EFM32"], "macros": ["EFM32ZG222F32"], "progen": { @@ -1823,7 +1823,7 @@ "inherits": ["Target"], "core": "Cortex-M0+", "default_toolchain": "uARM", - "supported_toolchains": ["GCC_ARM", "uARM"], + "supported_toolchains": ["GCC_ARM", "uARM", "IAR"], "extra_labels": ["Silicon_Labs", "EFM32"], "macros": ["EFM32HG322F64"], "progen": { diff --git a/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/efm32gg990f1024.icf b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/efm32gg990f1024.icf new file mode 100644 index 00000000000..a719a891e7a --- /dev/null +++ b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/efm32gg990f1024.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x200000DB; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000DC; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __ICFEDIT_size_cstack__ = 0x4000; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; + \ No newline at end of file diff --git a/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/startup_efm32gg.S b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/startup_efm32gg.S new file mode 100644 index 00000000000..d79e80129b0 --- /dev/null +++ b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/startup_efm32gg.S @@ -0,0 +1,385 @@ +;/**************************************************************************//** +; * @file startup_efm32gg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32GG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt + DCD USB_IRQHandler ; 5: USB Interrupt + DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 7: ADC0 Interrupt + DCD DAC0_IRQHandler ; 8: DAC0 Interrupt + DCD I2C0_IRQHandler ; 9: I2C0 Interrupt + DCD I2C1_IRQHandler ; 10: I2C1 Interrupt + DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt + DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt + DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt + DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt + DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt + DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt + DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt + DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt + DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt + DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt + DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt + DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt + DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt + DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt + DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt + DCD RTC_IRQHandler ; 30: RTC Interrupt + DCD BURTC_IRQHandler ; 31: BURTC Interrupt + DCD CMU_IRQHandler ; 32: CMU Interrupt + DCD VCMP_IRQHandler ; 33: VCMP Interrupt + DCD LCD_IRQHandler ; 34: LCD Interrupt + DCD MSC_IRQHandler ; 35: MSC Interrupt + DCD AES_IRQHandler ; 36: AES Interrupt + DCD EBI_IRQHandler ; 37: EBI Interrupt + DCD EMU_IRQHandler ; 38: EMU Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK UART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_RX_IRQHandler + B UART0_RX_IRQHandler + + PUBWEAK UART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_TX_IRQHandler + B UART0_TX_IRQHandler + + PUBWEAK UART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_RX_IRQHandler + B UART1_RX_IRQHandler + + PUBWEAK UART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_TX_IRQHandler + B UART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK LEUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART1_IRQHandler + B LEUART1_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK BURTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BURTC_IRQHandler + B BURTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK EBI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EBI_IRQHandler + B EBI_IRQHandler + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + + END diff --git a/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_IAR/efm32hg322f64.icf b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_IAR/efm32hg322f64.icf new file mode 100644 index 00000000000..47ecd197d72 --- /dev/null +++ b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_IAR/efm32hg322f64.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000093; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000094; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; + \ No newline at end of file diff --git a/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_IAR/startup_efm32hg.s b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_IAR/startup_efm32hg.s new file mode 100644 index 00000000000..be5c8a72d2e --- /dev/null +++ b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_IAR/startup_efm32hg.s @@ -0,0 +1,257 @@ +;/**************************************************************************//** +; * @file startup_efm32hg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32HG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 4: ADC0 Interrupt + DCD I2C0_IRQHandler ; 5: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt + DCD RTC_IRQHandler ; 12: RTC Interrupt + DCD CMU_IRQHandler ; 13: CMU Interrupt + DCD VCMP_IRQHandler ; 14: VCMP Interrupt + DCD MSC_IRQHandler ; 15: MSC Interrupt + DCD AES_IRQHandler ; 16: AES Interrupt + DCD USART0_RX_IRQHandler ; 17: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 18: USART0_TX Interrupt + DCD USB_IRQHandler ; 19: USB Interrupt + DCD TIMER2_IRQHandler ; 20: TIMER2 Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + + END diff --git a/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_IAR/efm32lg990f256.icf b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_IAR/efm32lg990f256.icf new file mode 100644 index 00000000000..5050ed53afe --- /dev/null +++ b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_IAR/efm32lg990f256.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x200000DF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000E0; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; + \ No newline at end of file diff --git a/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_IAR/startup_efm32lg.s b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_IAR/startup_efm32lg.s new file mode 100644 index 00000000000..3bcdab4d68b --- /dev/null +++ b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_IAR/startup_efm32lg.s @@ -0,0 +1,386 @@ +;/**************************************************************************//** +; * @file startup_efm32lg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32LG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt + DCD USB_IRQHandler ; 5: USB Interrupt + DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 7: ADC0 Interrupt + DCD DAC0_IRQHandler ; 8: DAC0 Interrupt + DCD I2C0_IRQHandler ; 9: I2C0 Interrupt + DCD I2C1_IRQHandler ; 10: I2C1 Interrupt + DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt + DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt + DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt + DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt + DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt + DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt + DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt + DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt + DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt + DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt + DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt + DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt + DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt + DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt + DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt + DCD RTC_IRQHandler ; 30: RTC Interrupt + DCD BURTC_IRQHandler ; 31: BURTC Interrupt + DCD CMU_IRQHandler ; 32: CMU Interrupt + DCD VCMP_IRQHandler ; 33: VCMP Interrupt + DCD LCD_IRQHandler ; 34: LCD Interrupt + DCD MSC_IRQHandler ; 35: MSC Interrupt + DCD AES_IRQHandler ; 36: AES Interrupt + DCD EBI_IRQHandler ; 37: EBI Interrupt + DCD EMU_IRQHandler ; 38: EMU Interrupt + DCD 0 ; 39: Reserved Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK UART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_RX_IRQHandler + B UART0_RX_IRQHandler + + PUBWEAK UART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_TX_IRQHandler + B UART0_TX_IRQHandler + + PUBWEAK UART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_RX_IRQHandler + B UART1_RX_IRQHandler + + PUBWEAK UART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_TX_IRQHandler + B UART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK LEUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART1_IRQHandler + B LEUART1_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK BURTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BURTC_IRQHandler + B BURTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK EBI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EBI_IRQHandler + B EBI_IRQHandler + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + + END diff --git a/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_IAR/efm32wg990f256.icf b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_IAR/efm32wg990f256.icf new file mode 100644 index 00000000000..5050ed53afe --- /dev/null +++ b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_IAR/efm32wg990f256.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x200000DF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000E0; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; + \ No newline at end of file diff --git a/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_IAR/startup_efm32wg.s b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_IAR/startup_efm32wg.s new file mode 100644 index 00000000000..c451cb4febe --- /dev/null +++ b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_IAR/startup_efm32wg.s @@ -0,0 +1,391 @@ +;/**************************************************************************//** +; * @file startup_efm32wg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32WG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt + DCD USB_IRQHandler ; 5: USB Interrupt + DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 7: ADC0 Interrupt + DCD DAC0_IRQHandler ; 8: DAC0 Interrupt + DCD I2C0_IRQHandler ; 9: I2C0 Interrupt + DCD I2C1_IRQHandler ; 10: I2C1 Interrupt + DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt + DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt + DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt + DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt + DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt + DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt + DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt + DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt + DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt + DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt + DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt + DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt + DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt + DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt + DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt + DCD RTC_IRQHandler ; 30: RTC Interrupt + DCD BURTC_IRQHandler ; 31: BURTC Interrupt + DCD CMU_IRQHandler ; 32: CMU Interrupt + DCD VCMP_IRQHandler ; 33: VCMP Interrupt + DCD LCD_IRQHandler ; 34: LCD Interrupt + DCD MSC_IRQHandler ; 35: MSC Interrupt + DCD AES_IRQHandler ; 36: AES Interrupt + DCD EBI_IRQHandler ; 37: EBI Interrupt + DCD EMU_IRQHandler ; 38: EMU Interrupt + DCD FPUEH_IRQHandler ; 39: FPUEH Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK UART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_RX_IRQHandler + B UART0_RX_IRQHandler + + PUBWEAK UART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_TX_IRQHandler + B UART0_TX_IRQHandler + + PUBWEAK UART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_RX_IRQHandler + B UART1_RX_IRQHandler + + PUBWEAK UART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_TX_IRQHandler + B UART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK LEUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART1_IRQHandler + B LEUART1_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK BURTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BURTC_IRQHandler + B BURTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK EBI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EBI_IRQHandler + B EBI_IRQHandler + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + + END diff --git a/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_IAR/efm32zg222f32.icf b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_IAR/efm32zg222f32.icf new file mode 100644 index 00000000000..e3ec4700c90 --- /dev/null +++ b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_IAR/efm32zg222f32.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x2000008B; +define symbol __ICFEDIT_region_RAM_start__ = 0x2000008C; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +/*-Sizes-*/ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; + \ No newline at end of file diff --git a/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_IAR/startup_efm32zg.s b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_IAR/startup_efm32zg.s new file mode 100644 index 00000000000..19098da1080 --- /dev/null +++ b/hal/targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_IAR/startup_efm32zg.s @@ -0,0 +1,235 @@ +;/**************************************************************************//** +; * @file startup_efm32zg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32ZG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 4: ADC0 Interrupt + DCD I2C0_IRQHandler ; 5: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt + DCD RTC_IRQHandler ; 12: RTC Interrupt + DCD CMU_IRQHandler ; 13: CMU Interrupt + DCD VCMP_IRQHandler ; 14: VCMP Interrupt + DCD MSC_IRQHandler ; 15: MSC Interrupt + DCD AES_IRQHandler ; 16: AES Interrupt + DCD 0 ; 17: Reserved Interrupt + DCD 0 ; 18: Reserved Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + + END From 964aeec0c089b6c69ff45b8d3f80a188c898328b Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Thu, 15 Sep 2016 09:52:23 +0200 Subject: [PATCH 2/3] [EFM32] Add all platforms (except Zero) to mbed 5 build --- hal/targets.json | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hal/targets.json b/hal/targets.json index 390103a2be3..423762b5b0f 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -1780,7 +1780,7 @@ "progen": {"target": "efm32gg-stk"}, "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 2, - "release_versions": ["2"] + "release_versions": ["2", "5"] }, "EFM32LG_STK3600": { "inherits": ["Target"], @@ -1791,7 +1791,7 @@ "progen": {"target": "efm32lg-stk"}, "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 2, - "release_versions": ["2"] + "release_versions": ["2", "5"] }, "EFM32WG_STK3800": { "inherits": ["Target"], @@ -1802,7 +1802,7 @@ "progen": {"target": "efm32wg-stk"}, "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 2, - "release_versions": ["2"] + "release_versions": ["2", "5"] }, "EFM32ZG_STK3200": { "inherits": ["Target"], @@ -1832,7 +1832,7 @@ "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "default_lib": "small", "forced_reset_timeout": 2, - "release_versions": ["2"] + "release_versions": ["2", "5"] }, "EFM32PG_STK3401": { "inherits": ["Target"], From 6700ab7d0d16831a828dc9fad974b6065d7d895a Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Fri, 16 Sep 2016 10:04:51 +0200 Subject: [PATCH 3/3] [EFM32] Remove HG from mbed 5 Remove Happy Gecko from mbed 5 builds until we can verify all of the examples fit using the ARM toolchain --- hal/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hal/targets.json b/hal/targets.json index 423762b5b0f..ec694f90e4e 100644 --- a/hal/targets.json +++ b/hal/targets.json @@ -1832,7 +1832,7 @@ "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "default_lib": "small", "forced_reset_timeout": 2, - "release_versions": ["2", "5"] + "release_versions": ["2"] }, "EFM32PG_STK3401": { "inherits": ["Target"],