Strange sort order with multiple read/write ports

[antonblanchard]

The default pin sort order (human) results in strange sorting of ports:

Do0[0]
Do0[1]
Do0[2]
Do0[3]
Do0[4]
Do0[5]
Do0[6]
Do0[7]
Do0[8]
Do0[9]
Do0[10]
Do1[0]
Do0[11]
Do1[1]
Do0[12]
Do1[2]
Do1[3]
Do1[4]
Do1[5]
Do1[6]
Do1[7]
Do1[8]
Do1[9]
Do1[10]
Do1[11]
Do1[12]

I added #BUS_SORT to the pin config, which gives us:

Do0[0]
Do1[0]
Do0[1]
Do1[1]

But from looking at the resulting routing, it's not clear to me that this is the how the placer has laid things out. @donn can you confirm if we want the ports interleaved, or all Do0 pins then all Do1 pins etc.

[donnie-j]

In the FWIW dept, I think the #BUS_SORT result might be helpful for routing (or more correctly, achieving good placement) from the register files to the execution units in the J-Core processors... I'll give it a try as soon as I get a chance. Suggestion: make interleaved or each bus together a command line option?