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fou_bitUP_tb.vhd
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fou_bitUP_tb.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:07:58 12/21/2022
-- Design Name:
-- Module Name: C:/.Xilinx/lab1/fou_bitUP_tb.vhd
-- Project Name: lab1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: four_bit_up_counter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fou_bitUP_tb IS
END fou_bitUP_tb;
ARCHITECTURE behavior OF fou_bitUP_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT four_bit_up_counter
PORT(
clk : IN std_logic;
rst : IN std_logic;
count : INOUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '1';
signal rst : std_logic := '1';
--BiDirs
signal count : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: four_bit_up_counter PORT MAP (
clk => clk,
rst => rst,
count => count
);
-- Clock process definitions
clk_process :process
begin
rst <= '0';
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;