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fuse.log
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fuse.log
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Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib secureip -o C:/.Xilinx/lab1/Shift_Register_tb_isim_beh.exe -prj C:/.Xilinx/lab1/Shift_Register_tb_beh.prj work.Shift_Register_tb
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Parsing VHDL file "C:/.Xilinx/lab1/D_flipflop.vhd" into library work
Parsing VHDL file "C:/.Xilinx/lab1/Shift_Register.vhd" into library work
Parsing VHDL file "C:/.Xilinx/lab1/Shift_Register_tb.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling architecture behavioral of entity D_flipflop [d_flipflop_default]
Compiling architecture behavioral of entity Shift_Register [shift_register_default]
Compiling architecture behavior of entity shift_register_tb
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 7 VHDL Units
Built simulation executable C:/.Xilinx/lab1/Shift_Register_tb_isim_beh.exe
Fuse Memory Usage: 29540 KB
Fuse CPU Usage: 389 ms