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TESTING.md

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Tests

A documentation of all hardware tests tested on mizu.

Acid2 tests

Tests State
dmg_acid2 👍
cgb_acid2 👍
cgb_acid_hell ❌

Blargg tests

Test State
cpu_instrs 👍
instr_timing 👍
halt_bug 👍
mem_timing 👍
mem_timing-2 👍
dmg_sound 👍
cgb_sound 👍
oam_bug 👍
interrupt_time 👍

Scribble tests

Test State
lycscx 👍
lycscy 👍
palettely 👍
scxly 👍
statcount 👍

Mooneye tests

Acceptance

Test State
add_sp_e_timing 👍
boot_div-dmgABCmgb 👍
boot_hwio-dmgABCmgb 👍
boot_regs-dmgABC 👍
call_timing 👍
call_timing2 👍
call_cc_timing 👍
call_cc_timing2 👍
di_timing GS 👍
div_timing 👍
ei_sequence 👍
ei_timing 👍
halt_ime0_ei 👍
halt_ime0_nointr_timing 👍
halt_ime1_timing 👍
halt_ime1_timing2-GS 👍
if_ie_registers 👍
intr_timing 👍
jp_timing 👍
jp_cc_timing 👍
ld_hl_sp_e_timing 👍
oam_dma_restart 👍
oam_dma_start 👍
oam_dma_timing 👍
pop_timing 👍
push_timing 👍
rapid_di_ei 👍
ret_timing 👍
ret_cc_timing 👍
reti_timing 👍
reti_intr_timing 👍
rst_timing 👍

Bits (unusable bits in memory and registers)

Test State
mem_oam 👍
reg_f 👍
unused_hwio-GS 👍

Instructions

Test State
daa 👍

Interrupt handling

Test State
ie_push 👍

OAM DMA

Test State
basic 👍
reg_read 👍
sources-GS 👍/❌*

* sources-GS passes on both CGB and DMG in mizu but it should pass on DMG and fail on CGB.

PPU

Test State
hblank_ly_scx_timing-GS ❌
intr_1_2_timing-GS 👍
intr_2_0_timing 👍
intr_2_mode0_timing ❌
intr_2_mode3_timing ❌
intr_2_oam_ok_timing 👍
intr_2_mode0_timing_sprites ❌
lcdon_timing-GS ❌
lcdon_write_timing-GS ❌
stat_irq_blocking 👍
stat_lyc_onoff 👍
vblank_stat_intr-GS 👍

Serial

Test State
boot_sclk_align-dmgABCmgb 👍

Timer

Test State
div_write 👍
rapid_toggle 👍
tim00_div_trigger 👍
tim00 👍
tim01_div_trigger 👍
tim01 👍
tim10_div_trigger 👍
tim10 👍
tim11_div_trigger 👍
tim11 👍
tima_reload 👍
tima_write_reloading 👍
tma_write_reloading 👍

emulator-only

MBC1

Test State
bits_bank1 👍
bits_bank2 👍
bits_mode 👍
bits_ramg 👍
rom_512kb 👍
rom_1Mb 👍
rom_2Mb 👍
rom_4Mb 👍
rom_8Mb 👍
rom_16Mb 👍
ram_64kb 👍
ram_256kb 👍
multicart_rom_8Mb 👍

MBC2

Test State
bits_ramg 👍
bits_romb 👍
bits_unused 👍
rom_512kb 👍
rom_1Mb 👍
rom_2Mb 👍
ram 👍

MBC5

Test State
rom_512kb 👍
rom_1Mb 👍
rom_2Mb 👍
rom_4Mb 👍
rom_8Mb 👍
rom_16Mb 👍
rom_32Mb 👍
rom_64Mb 👍

manual

Test State
sprite_priority 👍

misc (CGB)

Test State
boot_div-cgbABCDE 👍
boot_hwio-C 👍
boot_regs-cgb 👍

Bits

Test State
unused_hwio-C 👍

PPU

Test State
vblank_stat_intr-C 👍

SameSuite

HDMA

Test State
gbc_dma_cont 👍
gdma_addr_mask 👍
hdma_lcd_off 👍
hdma_mode0 👍

PPU

Test State
blocking_bgpi_increase 👍

APU

Test State
div_write_trigger_10 👍
div_write_trigger 👍
div_write_trigger_volume 👍
div_write_trigger_volume_10 👍
div_trigger_volume_10 👍

Channel1

Test State
channel_1_align ❌
channel_1_align_cpu ❌
channel_1_delay ❌
channel_1_duty ❌
channel_1_duty_delay ❌
channel_1_extra_length_clocking-cgb0B ❌
channel_1_freq_change ❌
channel_1_freq_change_timing-A ❌
channel_1_freq_change_timing-cgb0BC ❌
channel_1_freq_change_timing-cgbDE ❌
channel_1_nrx2_glitch ❌
channel_1_nrx2_speed_change ❌
channel_1_restart ❌
channel_1_restart_nrx2_glitch ❌
channel_1_stop_div ❌
channel_1_stop_restart ❌
channel_1_sweep ❌
channel_1_sweep_restart ❌
channel_1_sweep_restart_2 ❌
channel_1_volume ❌
channel_1_volume_div ❌

Channel2

Test State
channel_2_align ❌
channel_2_align_cpu ❌
channel_2_delay ❌
channel_2_duty ❌
channel_2_duty_delay ❌
channel_2_extra_length_clocking-cgb0B ❌
channel_2_freq_change ❌
channel_2_nrx2_glitch ❌
channel_2_nrx2_speed_change ❌
channel_2_restart ❌
channel_2_restart_nrx2_glitch ❌
channel_2_stop_div ❌
channel_2_stop_restart ❌
channel_2_volume ❌
channel_2_volume_div ❌

Channel3

Test State
channel_3_and_glitch ❌
channel_3_delay ❌
channel_3_extra_length_clocking-cgb0 ❌
channel_3_extra_length_clocking-cgbB ❌
channel_3_first_sample ❌
channel_3_freq_change_delay ❌
channel_3_restart_delay ❌
channel_3_restart_during_delay ❌
channel_3_restart_stop_delay ❌
channel_3_shift_delay ❌
channel_3_shift_skip_delay ❌
channel_3_stop_delay 👍
channel_3_stop_div ❌
channel_3_wave_ram_locked_write 👍
channel_3_wave_ram_sync ❌

Channel4

Test State
channel_4_align ❌
channel_4_delay ❌
channel_4_equivalent_frequencies ❌
channel_4_extra_length_clocking-cgb0B ❌
channel_4_freq_change ❌
channel_4_frequency_alignment ❌
channel_4_lfsr ❌
channel_4_lfsr15 ❌
channel_4_lfsr_15_7 ❌
channel_4_lfsr_7_15 ❌
channel_4_lfsr_restart ❌
channel_4_lfsr_restart_fast ❌
channel_4_volume_div ❌

GBMicrotest

Test State
audio_testbench ❌
803-ppu-latch-bgdisplay ❌
cpu_bus_1 ❌
div_inc_timing_a 👍
div_inc_timing_b 👍
dma_0x1000 👍
dma_0x9000 👍
dma_0xA000 👍
dma_0xC000 👍
dma_0xE000 👍
dma_basic ❌
dma_timing_a 👍
400-dma ❌
flood_vram ❌
halt_bug ❌
halt_op_dupe_delay ❌
halt_op_dupe 👍
hblank_int_di_timing_a ❌
hblank_int_di_timing_b 👍
hblank_int_if_a ❌
hblank_int_if_b 👍
hblank_int_l0 ❌
hblank_int_l1 ❌
hblank_int_l2 ❌
hblank_int_scx0_if_a 👍
hblank_int_scx0_if_b 👍
hblank_int_scx0_if_c 👍
hblank_int_scx0_if_d 👍
hblank_int_scx0 ❌
hblank_int_scx1_if_a 👍
hblank_int_scx1_if_b 👍
hblank_int_scx1_if_c 👍
hblank_int_scx1_if_d 👍
hblank_int_scx1_nops_a 👍
hblank_int_scx1_nops_b 👍
hblank_int_scx1 ❌
hblank_int_scx2_if_a 👍
hblank_int_scx2_if_b ❌
hblank_int_scx2_if_c ❌
hblank_int_scx2_if_d ❌
hblank_int_scx2_nops_a ❌
hblank_int_scx2_nops_b ❌
hblank_int_scx2 ❌
hblank_int_scx3_if_a 👍
hblank_int_scx3_if_b 👍
hblank_int_scx3_if_c 👍
hblank_int_scx3_if_d 👍
hblank_int_scx3_nops_a 👍
hblank_int_scx3_nops_b 👍
hblank_int_scx3 👍
hblank_int_scx4_if_a 👍
hblank_int_scx4_if_b 👍
hblank_int_scx4_if_c 👍
hblank_int_scx4_if_d 👍
hblank_int_scx4_nops_a 👍
hblank_int_scx4_nops_b 👍
hblank_int_scx4 ❌
hblank_int_scx5_if_a 👍
hblank_int_scx5_if_b 👍
hblank_int_scx5_if_c 👍
hblank_int_scx5_if_d 👍
hblank_int_scx5_nops_a 👍
hblank_int_scx5_nops_b 👍
hblank_int_scx5 ❌
hblank_int_scx6_if_a 👍
hblank_int_scx6_if_b ❌
hblank_int_scx6_if_c ❌
hblank_int_scx6_if_d ❌
hblank_int_scx6_nops_a ❌
hblank_int_scx6_nops_b ❌
hblank_int_scx6 ❌
hblank_int_scx7_if_a 👍
hblank_int_scx7_if_b 👍
hblank_int_scx7_if_c 👍
hblank_int_scx7_if_d 👍
hblank_int_scx7_nops_a 👍
hblank_int_scx7_nops_b 👍
hblank_int_scx7 ❌
hblank_scx2_if_a ❌
hblank_scx3_if_a 👍
hblank_scx3_if_b ❌
hblank_scx3_if_c ❌
hblank_scx3_if_d ❌
hblank_scx3_int_a 👍
hblank_scx3_int_b ❌
int_hblank_halt_bug_a 👍
int_hblank_halt_bug_b 👍
int_hblank_halt_scx0 ❌
int_hblank_halt_scx1 ❌
int_hblank_halt_scx2 ❌
int_hblank_halt_scx3 ❌
int_hblank_halt_scx4 ❌
int_hblank_halt_scx5 ❌
int_hblank_halt_scx6 ❌
int_hblank_halt_scx7 ❌
int_hblank_incs_scx0 ❌
int_hblank_incs_scx1 ❌
int_hblank_incs_scx2 ❌
int_hblank_incs_scx3 ❌
int_hblank_incs_scx4 ❌
int_hblank_incs_scx5 ❌
int_hblank_incs_scx6 ❌
int_hblank_incs_scx7 ❌
int_hblank_nops_scx0 ❌
int_hblank_nops_scx1 ❌
int_hblank_nops_scx2 ❌
int_hblank_nops_scx3 ❌
int_hblank_nops_scx4 ❌
int_hblank_nops_scx5 ❌
int_hblank_nops_scx6 ❌
int_hblank_nops_scx7 ❌
int_lyc_halt ❌
int_lyc_incs 👍
int_lyc_nops ❌
int_oam_halt ❌
int_oam_incs ❌
int_oam_nops ❌
int_timer_halt_div_a 👍
int_timer_halt_div_b ❌
int_timer_halt ❌
int_timer_incs 👍
int_timer_nops_div_a 👍
int_timer_nops_div_b 👍
int_timer_nops 👍
int_vblank1_halt ❌
int_vblank1_incs ❌
int_vblank1_nops ❌
int_vblank2_halt ❌
int_vblank2_incs ❌
int_vblank2_nops ❌
is_if_set_during_ime0 👍
007-lcd_on_stat ❌
lcdon_halt_to_vblank_int_a ❌
lcdon_halt_to_vblank_int_b 👍
lcdon_nops_to_vblank_int_a ❌
lcdon_nops_to_vblank_int_b 👍
lcdon_to_if_oam_a 👍
lcdon_to_if_oam_b ❌
lcdon_to_ly1_a 👍
lcdon_to_ly1_b 👍
lcdon_to_ly2_a 👍
lcdon_to_ly2_b 👍
lcdon_to_ly3_a 👍
lcdon_to_ly3_b 👍
lcdon_to_lyc1_int 👍
lcdon_to_lyc2_int 👍
lcdon_to_lyc3_int 👍
lcdon_to_oam_int_l0 ❌
lcdon_to_oam_int_l1 ❌
lcdon_to_oam_int_l2 ❌
lcdon_to_oam_unlock_a 👍
lcdon_to_oam_unlock_b 👍
lcdon_to_oam_unlock_c 👍
lcdon_to_oam_unlock_d ❌
lcdon_to_stat0_a 👍
lcdon_to_stat0_b 👍
lcdon_to_stat0_c 👍
lcdon_to_stat0_d 👍
lcdon_to_stat1_a 👍
lcdon_to_stat1_b ❌
lcdon_to_stat1_c 👍
lcdon_to_stat1_d ❌
lcdon_to_stat1_e 👍
lcdon_to_stat2_a ❌
lcdon_to_stat2_b 👍
lcdon_to_stat2_c 👍
lcdon_to_stat2_d 👍
lcdon_to_stat3_a 👍
lcdon_to_stat3_b 👍
lcdon_to_stat3_c 👍
lcdon_to_stat3_d 👍
lcdon_write_timing ❌
line_144_oam_int_a 👍
line_144_oam_int_b ❌
line_144_oam_int_c ❌
line_144_oam_int_d ❌
line_153_ly_a 👍
line_153_ly_b 👍
line_153_ly_c ❌
line_153_ly_d 👍
line_153_ly_e ❌
line_153_ly_f 👍
line_153_lyc_a 👍
line_153_lyc_b 👍
line_153_lyc_c ❌
line_153_lyc_int_a 👍
line_153_lyc_int_b 👍
line_153_lyc0_int_inc_sled 👍
line_153_lyc0_stat_timing_a 👍
line_153_lyc0_stat_timing_b 👍
line_153_lyc0_stat_timing_c 👍
line_153_lyc0_stat_timing_d 👍
line_153_lyc0_stat_timing_e 👍
line_153_lyc0_stat_timing_f ❌
line_153_lyc0_stat_timing_g 👍
line_153_lyc0_stat_timing_h ❌
line_153_lyc0_stat_timing_i 👍
line_153_lyc0_stat_timing_j ❌
line_153_lyc0_stat_timing_k 👍
line_153_lyc0_stat_timing_l 👍
line_153_lyc0_stat_timing_m ❌
line_153_lyc0_stat_timing_n 👍
line_153_lyc153_stat_timing_a 👍
line_153_lyc153_stat_timing_b 👍
line_153_lyc153_stat_timing_c ❌
line_153_lyc153_stat_timing_d 👍
line_153_lyc153_stat_timing_e ❌
line_153_lyc153_stat_timing_f 👍
line_65_ly ❌
ly_while_lcd_off ❌
lyc_int_halt_a ❌
lyc_int_halt_b 👍
lyc1_int_halt_a ❌
lyc1_int_halt_b 👍
lyc1_int_if_edge_a 👍
lyc1_int_if_edge_b 👍
lyc1_int_if_edge_c 👍
lyc1_int_if_edge_d 👍
lyc1_int_nops_a 👍
lyc1_int_nops_b 👍
lyc1_write_timing_a 👍
lyc1_write_timing_b 👍
lyc1_write_timing_c 👍
lyc1_write_timing_d 👍
lyc2_int_halt_a ❌
lyc2_int_halt_b 👍
mbc1_ram_banks 👍
mbc1_rom_banks ❌
minimal ❌
mode2_stat_int_to_oam_unlock ❌
oam_int_halt_a ❌
oam_int_halt_b 👍
oam_int_if_edge_a 👍
oam_int_if_edge_b ❌
oam_int_if_edge_c 👍
oam_int_if_edge_d ❌
oam_int_if_level_c 👍
oam_int_if_level_d ❌
oam_int_inc_sled ❌
oam_int_nops_a ❌
oam_int_nops_b 👍
000-oam_lock ❌
oam_read_l0_a 👍
oam_read_l0_b 👍
oam_read_l0_c 👍
oam_read_l0_d ❌
oam_read_l1_a 👍
oam_read_l1_b 👍
oam_read_l1_c 👍
oam_read_l1_d ❌
oam_read_l1_e 👍
oam_read_l1_f 👍
oam_sprite_trashing ❌
oam_write_l0_a 👍
oam_write_l0_b 👍
oam_write_l0_c 👍
oam_write_l0_d ❌
oam_write_l0_e ❌
oam_write_l1_a 👍
oam_write_l1_b 👍
oam_write_l1_c ❌
oam_write_l1_d 👍
oam_write_l1_e 👍
oam_write_l1_f ❌
poweron_bgp_000 👍
poweron_div_000 ❌
poweron_div_004 ❌
poweron_div_005 ❌
poweron_dma_000 ❌
poweron_if_000 👍
poweron_joy_000 👍
poweron_lcdc_000 👍
poweron_ly_000 👍
poweron_ly_119 ❌
poweron_ly_120 👍
poweron_ly_233 ❌
poweron_ly_234 👍
poweron_lyc_000 👍
poweron_oam_000 👍
poweron_oam_005 👍
poweron_oam_006 👍
poweron_oam_069 👍
poweron_oam_070 👍
poweron_oam_119 ❌
poweron_oam_120 👍
poweron_oam_121 👍
poweron_oam_183 👍
poweron_oam_184 👍
poweron_oam_233 ❌
poweron_oam_234 👍
poweron_oam_235 👍
poweron_obp0_000 👍
poweron_obp1_000 👍
poweron_sb_000 👍
poweron_sc_000 👍
poweron_scx_000 👍
poweron_scy_000 👍
poweron_stat_000 👍
poweron_stat_005 👍
poweron_stat_006 ❌
poweron_stat_007 👍
poweron_stat_026 ❌
poweron_stat_027 👍
poweron_stat_069 ❌
poweron_stat_070 👍
poweron_stat_119 👍
poweron_stat_120 ❌
poweron_stat_121 👍
poweron_stat_140 ❌
poweron_stat_141 👍
poweron_stat_183 ❌
poweron_stat_184 👍
poweron_stat_234 ❌
poweron_stat_235 👍
poweron_tac_000 👍
poweron_tima_000 👍
poweron_tma_000 👍
poweron_vram_000 👍
poweron_vram_025 👍
poweron_vram_026 ❌
poweron_vram_069 ❌
poweron_vram_070 👍
poweron_vram_139 👍
poweron_vram_140 ❌
poweron_vram_183 ❌
poweron_vram_184 👍
poweron_wx_000 👍
poweron_wy_000 👍
poweron ❌
ppu_scx_vs_bgp ❌
ppu_sprite_testbench ❌
ppu_sprite0_scx0_a 👍
ppu_sprite0_scx0_b 👍
ppu_sprite0_scx1_a 👍
ppu_sprite0_scx1_b 👍
ppu_sprite0_scx2_a 👍
ppu_sprite0_scx2_b ❌
ppu_sprite0_scx3_a 👍
ppu_sprite0_scx3_b ❌
ppu_sprite0_scx4_a 👍
ppu_sprite0_scx4_b 👍
ppu_sprite0_scx5_a 👍
ppu_sprite0_scx5_b 👍
ppu_sprite0_scx6_a 👍
ppu_sprite0_scx6_b ❌
ppu_sprite0_scx7_a 👍
ppu_sprite0_scx7_b ❌
ppu_spritex_vs_scx ❌
ppu_win_vs_wx ❌
ppu_wx_early ❌
800-ppu-latch-scx ❌
801-ppu-latch-scy ❌
sprite_0_a ❌
sprite_0_b 👍
sprite_1_a ❌
sprite_1_b 👍
sprite4_0_a ❌
sprite4_0_b 👍
sprite4_1_a ❌
sprite4_1_b 👍
sprite4_2_a ❌
sprite4_2_b 👍
sprite4_3_a ❌
sprite4_3_b 👍
sprite4_4_a ❌
sprite4_4_b 👍
sprite4_5_a ❌
sprite4_5_b 👍
sprite4_6_a ❌
sprite4_6_b 👍
sprite4_7_a ❌
sprite4_7_b 👍
stat_write_glitch_l0_a ❌
stat_write_glitch_l0_b ❌
stat_write_glitch_l0_c 👍
stat_write_glitch_l1_a 👍
stat_write_glitch_l1_b ❌
stat_write_glitch_l1_c ❌
stat_write_glitch_l1_d 👍
stat_write_glitch_l143_a 👍
stat_write_glitch_l143_b ❌
stat_write_glitch_l143_c ❌
stat_write_glitch_l143_d ❌
stat_write_glitch_l154_a ❌
stat_write_glitch_l154_b ❌
stat_write_glitch_l154_c 👍
stat_write_glitch_l154_d ❌
temp 👍
802-ppu-latch-tileselect ❌
004-tima_boot_phase ❌
004-tima_cycle_timer ❌
timer_div_phase_c 👍
timer_div_phase_d 👍
timer_tima_inc_256k_a 👍
timer_tima_inc_256k_b 👍
timer_tima_inc_256k_c 👍
timer_tima_inc_256k_d 👍
timer_tima_inc_256k_e 👍
timer_tima_inc_256k_f 👍
timer_tima_inc_256k_g 👍
timer_tima_inc_256k_h 👍
timer_tima_inc_256k_i 👍
timer_tima_inc_256k_j 👍
timer_tima_inc_256k_k 👍
timer_tima_inc_64k_a 👍
timer_tima_inc_64k_b 👍
timer_tima_inc_64k_c 👍
timer_tima_inc_64k_d 👍
timer_tima_phase_a ❌
timer_tima_phase_b ❌
timer_tima_phase_c ❌
timer_tima_phase_d ❌
timer_tima_phase_e ❌
timer_tima_phase_f ❌
timer_tima_phase_g ❌
timer_tima_phase_h ❌
timer_tima_phase_i ❌
timer_tima_phase_j ❌
timer_tima_reload_256k_a 👍
timer_tima_reload_256k_b 👍
timer_tima_reload_256k_c 👍
timer_tima_reload_256k_d 👍
timer_tima_reload_256k_e 👍
timer_tima_reload_256k_f 👍
timer_tima_reload_256k_g 👍
timer_tima_reload_256k_h 👍
timer_tima_reload_256k_i 👍
timer_tima_reload_256k_j 👍
timer_tima_reload_256k_k 👍
timer_tima_write_a 👍
timer_tima_write_b 👍
timer_tima_write_c 👍
timer_tima_write_d 👍
timer_tima_write_e 👍
timer_tima_write_f 👍
timer_tma_write_a 👍
timer_tma_write_b 👍
500-scx-timing ❌
toggle_lcdc ❌
vblank_int_halt_a ❌
vblank_int_halt_b 👍
vblank_int_if_a 👍
vblank_int_if_b ❌
vblank_int_if_c 👍
vblank_int_if_d ❌
vblank_int_inc_sled ❌
vblank_int_nops_a ❌
vblank_int_nops_b 👍
vblank2_int_halt_a ❌
vblank2_int_halt_b 👍
vblank2_int_if_a 👍
vblank2_int_if_b ❌
vblank2_int_if_c 👍
vblank2_int_if_d ❌
vblank2_int_inc_sled ❌
vblank2_int_nops_a ❌
vblank2_int_nops_b 👍
002-vram_locked ❌
vram_read_l0_a 👍
vram_read_l0_b ❌
vram_read_l0_c ❌
vram_read_l0_d 👍
vram_read_l1_a 👍
vram_read_l1_b ❌
vram_read_l1_c ❌
vram_read_l1_d 👍
001-vram_unlocked ❌
vram_write_l0_a 👍
vram_write_l0_b ❌
vram_write_l0_c ❌
vram_write_l0_d 👍
vram_write_l1_a 👍
vram_write_l1_b ❌
vram_write_l1_c ❌
vram_write_l1_d 👍
wave_write_to_0xC003 ❌
win0_a 👍
win0_b ❌
win0_scx3_a 👍
win0_scx3_b 👍
win1_a 👍
win1_b ❌
win10_a 👍
win10_b ❌
win10_scx3_a 👍
win10_scx3_b ❌
win11_a 👍
win11_b ❌
win12_a 👍
win12_b ❌
win13_a 👍
win13_b ❌
win14_a 👍
win14_b ❌
win15_a 👍
win15_b ❌
win2_a 👍
win2_b 👍
win3_a 👍
win3_b 👍
win4_a 👍
win4_b 👍
win5_a 👍
win5_b 👍
win6_a ❌
win6_b 👍
win7_a ❌
win7_b 👍
win8_a 👍
win8_b ❌
win9_a 👍
win9_b ❌
000-write_to_x8000 ❌

TurtleTests

Test State
window_y_trigger ❌
window_y_trigger_wx_offscreen 👍

Extra

These are valuable tests, they come in a single rom, so they were grouped into a single table

Test State
rtc3test 👍
bullyGB in DMG ❓*
bullyGB in CGB ❓*
MBC3-Tester 👍

* previusly passed, but now it fails, it needs to be retested and fix the issues