-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathDesign.constraint
141 lines (117 loc) · 6.57 KB
/
Design.constraint
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
****************************************
Report : constraint
-verbose
Design : M216A_TopModule
Version: M-2016.12-SP2
Date : Thu Dec 1 18:39:07 2022
****************************************
Startpoint: Instruction_In[8]
(input port clocked by Clk_In)
Endpoint: R3/DataReg_reg[15]
(rising edge-triggered flip-flop clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
M216A_TopModule_DW_mult_uns_0
8000 saed32rvt_ff1p16vn40c
Point Incr Path
--------------------------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 f
Instruction_In[8] (in) 0.00 0.60 f
U529/Y (INVX1_RVT) 0.01 0.61 r
U586/Y (NAND4X0_RVT) 0.02 0.63 f
U587/Y (NOR4X1_RVT) 0.03 0.66 r
U552/Y (AND4X1_RVT) 0.03 0.68 r
U555/Y (NBUFFX2_RVT) 0.02 0.70 r
U518/Y (AO21X2_RVT) 0.03 0.73 r
U600/Y (AO22X1_RVT) 0.04 0.78 r
P1_MULT_0/mult_22/U331/Y (AND2X1_RVT) 0.02 0.80 r
P1_MULT_0/mult_22/U114/S (FADDX1_RVT) 0.05 0.85 f
P1_MULT_0/mult_22/U335/Y (XNOR2X1_RVT) 0.04 0.88 r
P1_MULT_0/mult_22/U310/Y (XNOR2X1_RVT) 0.04 0.92 r
P1_MULT_0/mult_22/U12/CO (FADDX1_RVT) 0.03 0.95 r
P1_MULT_0/mult_22/U11/CO (FADDX1_RVT) 0.03 0.98 r
P1_MULT_0/mult_22/U477/Y (NAND2X0_RVT) 0.01 0.99 f
P1_MULT_0/mult_22/U480/Y (NAND3X0_RVT) 0.02 1.01 r
P1_MULT_0/mult_22/U9/CO (FADDX1_RVT) 0.03 1.04 r
P1_MULT_0/mult_22/U8/CO (FADDX1_RVT) 0.03 1.07 r
P1_MULT_0/mult_22/U7/CO (FADDX1_RVT) 0.03 1.10 r
P1_MULT_0/mult_22/U6/CO (FADDX1_RVT) 0.03 1.14 r
P1_MULT_0/mult_22/U470/Y (NAND2X0_RVT) 0.01 1.15 f
P1_MULT_0/mult_22/U472/Y (NAND3X0_RVT) 0.02 1.16 r
P1_MULT_0/mult_22/U475/Y (NAND2X0_RVT) 0.01 1.17 f
P1_MULT_0/mult_22/U476/Y (NAND3X0_RVT) 0.02 1.19 r
P1_MULT_0/mult_22/U3/CO (FADDX1_RVT) 0.03 1.22 r
P1_MULT_0/mult_22/U394/Y (XNOR2X2_RVT) 0.03 1.25 r
P1_MULT_0/mult_22/U340/Y (XOR3X1_RVT) 0.02 1.27 f
P1_MULT_0/mult_22/U296/Y (XNOR2X2_RVT) 0.03 1.30 r
P1_ADD_0/add_11/U1_15/Y (XOR3X2_RVT) 0.02 1.32 f
U447/Y (AND2X1_RVT) 0.02 1.34 f
R3/DataReg_reg[15]/D (DFFX1_RVT) 0.00 1.34 f
data arrival time 1.34
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
R3/DataReg_reg[15]/CLK (DFFX1_RVT) 0.00 1.35 r
library setup time -0.01 1.34
data required time 1.34
--------------------------------------------------------------------------
data required time 1.34
data arrival time -1.34
--------------------------------------------------------------------------
slack (MET) 0.00
Startpoint: R1/DataReg_reg[3]
(rising edge-triggered flip-flop clocked by Clk_In)
Endpoint: R2/DataReg_reg[3]
(rising edge-triggered flip-flop clocked by Clk_In)
Path Group: Clk_In
Path Type: min
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
Point Incr Path
-----------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
R1/DataReg_reg[3]/CLK (DFFX1_RVT) 0.00 0.00 r
R1/DataReg_reg[3]/Q (DFFX1_RVT) 0.04 0.04 r
U628/Y (AND2X1_RVT) 0.05 0.09 r
R2/DataReg_reg[3]/D (DFFX1_RVT) 0.01 0.10 r
data arrival time 0.10
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
clock uncertainty 0.10 0.10
R2/DataReg_reg[3]/CLK (DFFX1_RVT) 0.00 0.10 r
library hold time -0.01 0.09
data required time 0.09
-----------------------------------------------------------
data required time 0.09
data arrival time -0.10
-----------------------------------------------------------
slack (MET) 0.01
Net: reg_in1_1[0]
max_transition 0.04
- Transition Time 0.01
------------------------------
Slack 0.03 (MET)
Net: mult_in1[4]
max_capacitance 8.00
- Capacitance 6.09
------------------------------
Slack 1.91 (MET)
Design: M216A_TopModule
max_area 0.00
- Current Area 2263.84
------------------------------
Slack -2263.84 (VIOLATED)
Min pulse width constraints
Required Actual
Pin pulse width pulse width Slack Scenario
--------------------------------------------------------------------------------
R3/DataReg_reg[15]/CLK(high)
0.02 0.62 0.60 (MET)
1