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Design.setuptiming
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****************************************
Report : timing
-path full
-delay max
-nworst 2
-max_paths 10
Design : M216A_TopModule
Version: M-2016.12-SP2
Date : Thu Dec 1 18:39:06 2022
****************************************
Operating Conditions: ss0p95v125c Library: saed32rvt_ss0p95v125c
Wire Load Model Mode: enclosed
Startpoint: Instruction_In[8]
(input port clocked by Clk_In)
Endpoint: R3/DataReg_reg[15]
(rising edge-triggered flip-flop clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
M216A_TopModule_DW_mult_uns_0
8000 saed32rvt_ff1p16vn40c
Point Incr Path
--------------------------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 f
Instruction_In[8] (in) 0.00 0.60 f
U529/Y (INVX1_RVT) 0.01 0.61 r
U586/Y (NAND4X0_RVT) 0.02 0.63 f
U587/Y (NOR4X1_RVT) 0.03 0.66 r
U552/Y (AND4X1_RVT) 0.03 0.68 r
U555/Y (NBUFFX2_RVT) 0.02 0.70 r
U518/Y (AO21X2_RVT) 0.03 0.73 r
U600/Y (AO22X1_RVT) 0.04 0.78 r
P1_MULT_0/mult_22/b[5] (M216A_TopModule_DW_mult_uns_0)
0.00 0.78 r
P1_MULT_0/mult_22/U331/Y (AND2X1_RVT) 0.02 0.80 r
P1_MULT_0/mult_22/U114/S (FADDX1_RVT) 0.05 0.85 f
P1_MULT_0/mult_22/U335/Y (XNOR2X1_RVT) 0.04 0.88 r
P1_MULT_0/mult_22/U310/Y (XNOR2X1_RVT) 0.04 0.92 r
P1_MULT_0/mult_22/U12/CO (FADDX1_RVT) 0.03 0.95 r
P1_MULT_0/mult_22/U11/CO (FADDX1_RVT) 0.03 0.98 r
P1_MULT_0/mult_22/U477/Y (NAND2X0_RVT) 0.01 0.99 f
P1_MULT_0/mult_22/U480/Y (NAND3X0_RVT) 0.02 1.01 r
P1_MULT_0/mult_22/U9/CO (FADDX1_RVT) 0.03 1.04 r
P1_MULT_0/mult_22/U8/CO (FADDX1_RVT) 0.03 1.07 r
P1_MULT_0/mult_22/U7/CO (FADDX1_RVT) 0.03 1.10 r
P1_MULT_0/mult_22/U6/CO (FADDX1_RVT) 0.03 1.14 r
P1_MULT_0/mult_22/U470/Y (NAND2X0_RVT) 0.01 1.15 f
P1_MULT_0/mult_22/U472/Y (NAND3X0_RVT) 0.02 1.16 r
P1_MULT_0/mult_22/U475/Y (NAND2X0_RVT) 0.01 1.17 f
P1_MULT_0/mult_22/U476/Y (NAND3X0_RVT) 0.02 1.19 r
P1_MULT_0/mult_22/U3/CO (FADDX1_RVT) 0.03 1.22 r
P1_MULT_0/mult_22/U394/Y (XNOR2X2_RVT) 0.03 1.25 r
P1_MULT_0/mult_22/U340/Y (XOR3X1_RVT) 0.02 1.27 f
P1_MULT_0/mult_22/U296/Y (XNOR2X2_RVT) 0.03 1.30 r
P1_MULT_0/mult_22/product[15] (M216A_TopModule_DW_mult_uns_0)
0.00 1.30 r
P1_ADD_0/add_11/B[15] (M216A_TopModule_DW01_add_0) 0.00 1.30 r
P1_ADD_0/add_11/U1_15/Y (XOR3X2_RVT) 0.02 1.32 f
P1_ADD_0/add_11/SUM[15] (M216A_TopModule_DW01_add_0)
0.00 1.32 f
U447/Y (AND2X1_RVT) 0.02 1.34 f
R3/DataReg_reg[15]/D (DFFX1_RVT) 0.00 1.34 f
data arrival time 1.34
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
R3/DataReg_reg[15]/CLK (DFFX1_RVT) 0.00 1.35 r
library setup time -0.01 1.34
data required time 1.34
--------------------------------------------------------------------------
data required time 1.34
data arrival time -1.34
--------------------------------------------------------------------------
slack (MET) 0.00
Startpoint: Instruction_In[8]
(input port clocked by Clk_In)
Endpoint: R3/DataReg_reg[15]
(rising edge-triggered flip-flop clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
M216A_TopModule_DW_mult_uns_0
8000 saed32rvt_ff1p16vn40c
M216A_TopModule_DW01_add_0
ForQA saed32rvt_ff1p16vn40c
Point Incr Path
--------------------------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 f
Instruction_In[8] (in) 0.00 0.60 f
U529/Y (INVX1_RVT) 0.01 0.61 r
U586/Y (NAND4X0_RVT) 0.02 0.63 f
U587/Y (NOR4X1_RVT) 0.03 0.66 r
U552/Y (AND4X1_RVT) 0.03 0.68 r
U555/Y (NBUFFX2_RVT) 0.02 0.70 r
U518/Y (AO21X2_RVT) 0.03 0.73 r
U600/Y (AO22X1_RVT) 0.04 0.78 r
P1_MULT_0/mult_22/b[5] (M216A_TopModule_DW_mult_uns_0)
0.00 0.78 r
P1_MULT_0/mult_22/U331/Y (AND2X1_RVT) 0.02 0.80 r
P1_MULT_0/mult_22/U114/S (FADDX1_RVT) 0.05 0.85 f
P1_MULT_0/mult_22/U335/Y (XNOR2X1_RVT) 0.04 0.88 r
P1_MULT_0/mult_22/U310/Y (XNOR2X1_RVT) 0.04 0.92 f
P1_MULT_0/mult_22/U12/S (FADDX1_RVT) 0.05 0.96 r
P1_MULT_0/mult_22/product[5] (M216A_TopModule_DW_mult_uns_0)
0.00 0.96 r
P1_ADD_0/add_11/B[5] (M216A_TopModule_DW01_add_0) 0.00 0.96 r
P1_ADD_0/add_11/U1_5/CO (FADDX1_RVT) 0.03 0.99 r
P1_ADD_0/add_11/U1_6/CO (FADDX1_RVT) 0.03 1.03 r
P1_ADD_0/add_11/U1_7/CO (FADDX1_RVT) 0.03 1.06 r
P1_ADD_0/add_11/U1_8/CO (FADDX1_RVT) 0.03 1.09 r
P1_ADD_0/add_11/U1_9/CO (FADDX1_RVT) 0.03 1.12 r
P1_ADD_0/add_11/U1_10/CO (FADDX1_RVT) 0.03 1.15 r
P1_ADD_0/add_11/U1_11/CO (FADDX1_RVT) 0.03 1.18 r
P1_ADD_0/add_11/U1_12/CO (FADDX1_RVT) 0.03 1.22 r
P1_ADD_0/add_11/U6/Y (NAND2X0_RVT) 0.01 1.23 f
P1_ADD_0/add_11/U5/Y (NAND3X0_RVT) 0.02 1.25 r
P1_ADD_0/add_11/U1_14/CO (FADDX1_RVT) 0.03 1.28 r
P1_ADD_0/add_11/U1_15/Y (XOR3X2_RVT) 0.04 1.32 r
P1_ADD_0/add_11/SUM[15] (M216A_TopModule_DW01_add_0)
0.00 1.32 r
U447/Y (AND2X1_RVT) 0.02 1.33 r
R3/DataReg_reg[15]/D (DFFX1_RVT) 0.00 1.33 r
data arrival time 1.33
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
R3/DataReg_reg[15]/CLK (DFFX1_RVT) 0.00 1.35 r
library setup time -0.01 1.34
data required time 1.34
--------------------------------------------------------------------------
data required time 1.34
data arrival time -1.33
--------------------------------------------------------------------------
slack (MET) 0.00
Startpoint: Instruction_In[11]
(input port clocked by Clk_In)
Endpoint: D_Out[7] (output port clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
Point Incr Path
-----------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 r
Instruction_In[11] (in) 0.00 0.60 r
U584/Y (INVX2_RVT) 0.00 0.60 f
U585/Y (NAND2X0_RVT) 0.01 0.62 r
U545/Y (NOR4X0_RVT) 0.04 0.66 f
U576/Y (AND2X1_RVT) 0.02 0.68 f
U538/Y (AND3X1_RVT) 0.02 0.70 f
U527/Y (INVX2_RVT) 0.01 0.72 r
U520/Y (INVX8_RVT) 0.01 0.73 f
U651/Y (MUX21X1_RVT) 0.02 0.75 f
D_Out[7] (out) 0.00 0.75 f
data arrival time 0.75
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
output external delay -0.60 0.75
data required time 0.75
-----------------------------------------------------------
data required time 0.75
data arrival time -0.75
-----------------------------------------------------------
slack (MET) 0.00
Startpoint: Instruction_In[11]
(input port clocked by Clk_In)
Endpoint: D_Out[6] (output port clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
Point Incr Path
-----------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 r
Instruction_In[11] (in) 0.00 0.60 r
U584/Y (INVX2_RVT) 0.00 0.60 f
U585/Y (NAND2X0_RVT) 0.01 0.62 r
U545/Y (NOR4X0_RVT) 0.04 0.66 f
U576/Y (AND2X1_RVT) 0.02 0.68 f
U538/Y (AND3X1_RVT) 0.02 0.70 f
U527/Y (INVX2_RVT) 0.01 0.72 r
U520/Y (INVX8_RVT) 0.01 0.73 f
U649/Y (MUX21X1_RVT) 0.02 0.75 f
D_Out[6] (out) 0.00 0.75 f
data arrival time 0.75
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
output external delay -0.60 0.75
data required time 0.75
-----------------------------------------------------------
data required time 0.75
data arrival time -0.75
-----------------------------------------------------------
slack (MET) 0.00
Startpoint: Instruction_In[11]
(input port clocked by Clk_In)
Endpoint: D_Out[5] (output port clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
Point Incr Path
-----------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 r
Instruction_In[11] (in) 0.00 0.60 r
U584/Y (INVX2_RVT) 0.00 0.60 f
U585/Y (NAND2X0_RVT) 0.01 0.62 r
U545/Y (NOR4X0_RVT) 0.04 0.66 f
U576/Y (AND2X1_RVT) 0.02 0.68 f
U538/Y (AND3X1_RVT) 0.02 0.70 f
U527/Y (INVX2_RVT) 0.01 0.72 r
U520/Y (INVX8_RVT) 0.01 0.73 f
U647/Y (MUX21X1_RVT) 0.02 0.75 f
D_Out[5] (out) 0.00 0.75 f
data arrival time 0.75
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
output external delay -0.60 0.75
data required time 0.75
-----------------------------------------------------------
data required time 0.75
data arrival time -0.75
-----------------------------------------------------------
slack (MET) 0.00
Startpoint: Instruction_In[11]
(input port clocked by Clk_In)
Endpoint: D_Out[4] (output port clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
Point Incr Path
-----------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 r
Instruction_In[11] (in) 0.00 0.60 r
U584/Y (INVX2_RVT) 0.00 0.60 f
U585/Y (NAND2X0_RVT) 0.01 0.62 r
U545/Y (NOR4X0_RVT) 0.04 0.66 f
U576/Y (AND2X1_RVT) 0.02 0.68 f
U538/Y (AND3X1_RVT) 0.02 0.70 f
U527/Y (INVX2_RVT) 0.01 0.72 r
U520/Y (INVX8_RVT) 0.01 0.73 f
U645/Y (MUX21X1_RVT) 0.02 0.75 f
D_Out[4] (out) 0.00 0.75 f
data arrival time 0.75
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
output external delay -0.60 0.75
data required time 0.75
-----------------------------------------------------------
data required time 0.75
data arrival time -0.75
-----------------------------------------------------------
slack (MET) 0.00
Startpoint: Instruction_In[11]
(input port clocked by Clk_In)
Endpoint: D_Out[3] (output port clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
Point Incr Path
-----------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 r
Instruction_In[11] (in) 0.00 0.60 r
U584/Y (INVX2_RVT) 0.00 0.60 f
U585/Y (NAND2X0_RVT) 0.01 0.62 r
U545/Y (NOR4X0_RVT) 0.04 0.66 f
U576/Y (AND2X1_RVT) 0.02 0.68 f
U538/Y (AND3X1_RVT) 0.02 0.70 f
U527/Y (INVX2_RVT) 0.01 0.72 r
U520/Y (INVX8_RVT) 0.01 0.73 f
U643/Y (MUX21X1_RVT) 0.02 0.75 f
D_Out[3] (out) 0.00 0.75 f
data arrival time 0.75
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
output external delay -0.60 0.75
data required time 0.75
-----------------------------------------------------------
data required time 0.75
data arrival time -0.75
-----------------------------------------------------------
slack (MET) 0.00
Startpoint: Instruction_In[11]
(input port clocked by Clk_In)
Endpoint: D_Out[2] (output port clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
Point Incr Path
-----------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 r
Instruction_In[11] (in) 0.00 0.60 r
U584/Y (INVX2_RVT) 0.00 0.60 f
U585/Y (NAND2X0_RVT) 0.01 0.62 r
U545/Y (NOR4X0_RVT) 0.04 0.66 f
U576/Y (AND2X1_RVT) 0.02 0.68 f
U538/Y (AND3X1_RVT) 0.02 0.70 f
U527/Y (INVX2_RVT) 0.01 0.72 r
U520/Y (INVX8_RVT) 0.01 0.73 f
U641/Y (MUX21X1_RVT) 0.02 0.75 f
D_Out[2] (out) 0.00 0.75 f
data arrival time 0.75
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
output external delay -0.60 0.75
data required time 0.75
-----------------------------------------------------------
data required time 0.75
data arrival time -0.75
-----------------------------------------------------------
slack (MET) 0.00
Startpoint: Instruction_In[11]
(input port clocked by Clk_In)
Endpoint: D_Out[1] (output port clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
Point Incr Path
-----------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 r
Instruction_In[11] (in) 0.00 0.60 r
U584/Y (INVX2_RVT) 0.00 0.60 f
U585/Y (NAND2X0_RVT) 0.01 0.62 r
U545/Y (NOR4X0_RVT) 0.04 0.66 f
U576/Y (AND2X1_RVT) 0.02 0.68 f
U538/Y (AND3X1_RVT) 0.02 0.70 f
U527/Y (INVX2_RVT) 0.01 0.72 r
U520/Y (INVX8_RVT) 0.01 0.73 f
U639/Y (MUX21X1_RVT) 0.02 0.75 f
D_Out[1] (out) 0.00 0.75 f
data arrival time 0.75
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
output external delay -0.60 0.75
data required time 0.75
-----------------------------------------------------------
data required time 0.75
data arrival time -0.75
-----------------------------------------------------------
slack (MET) 0.00
Startpoint: Instruction_In[11]
(input port clocked by Clk_In)
Endpoint: D_Out[0] (output port clocked by Clk_In)
Path Group: Clk_In
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
M216A_TopModule 8000 saed32rvt_ff1p16vn40c
Point Incr Path
-----------------------------------------------------------
clock Clk_In (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.60 0.60 r
Instruction_In[11] (in) 0.00 0.60 r
U584/Y (INVX2_RVT) 0.00 0.60 f
U585/Y (NAND2X0_RVT) 0.01 0.62 r
U545/Y (NOR4X0_RVT) 0.04 0.66 f
U576/Y (AND2X1_RVT) 0.02 0.68 f
U538/Y (AND3X1_RVT) 0.02 0.70 f
U527/Y (INVX2_RVT) 0.01 0.72 r
U520/Y (INVX8_RVT) 0.01 0.73 f
U637/Y (MUX21X1_RVT) 0.02 0.75 f
D_Out[0] (out) 0.00 0.75 f
data arrival time 0.75
clock Clk_In (rise edge) 1.45 1.45
clock network delay (ideal) 0.00 1.45
clock uncertainty -0.10 1.35
output external delay -0.60 0.75
data required time 0.75
-----------------------------------------------------------
data required time 0.75
data arrival time -0.75
-----------------------------------------------------------
slack (MET) 0.00
1