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1. SPI-Interface SPI-Interface Public

   UVM Testbench to verify serial transmission of data between SPI master and slave

   SystemVerilog 35 15

2. Synchronous-FIFO-UVM-TB Synchronous-FIFO-UVM-TB Public

   UVM Testbench for synchronus fifo

   SystemVerilog 15 4

3. Sequence-Detector-using-FSM Sequence-Detector-using-FSM Public

   RTL for sequence detector in verilog

   Verilog 1

4. Modulus-Counter Modulus-Counter Public

   Coq 1