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common.c
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common.c
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#define DEBUG_FLASH 0
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <fcntl.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
#include <helper.h>
#include <logging.h>
#include <md5.h>
#include <stlink.h>
#ifdef STLINK_HAVE_SYS_MMAN_H
#include <sys/mman.h>
#else
#include <mmap.h>
#endif
#ifndef O_BINARY
#define O_BINARY 0
#endif
#ifdef _MSC_VER
#define __attribute__(x)
#endif
#define BANK_1 0
#define BANK_2 1
/* stm32f FPEC flash controller interface, pm0063 manual */
// TODO - all of this needs to be abstracted out....
// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2,
// August 2012)
#define FLASH_REGS_ADDR 0x40022000
#define FLASH_REGS_SIZE 0x28
#define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08)
#define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
#define FLASH_CR (FLASH_REGS_ADDR + 0x10)
#define FLASH_AR (FLASH_REGS_ADDR + 0x14)
#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
// STM32F10x_XL has two flash memory banks with separate registers to control
// the second bank.
#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44)
#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c)
#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50)
#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54)
// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere...
#define FLASH_RDPTR_KEY 0x00a5
#define FLASH_KEY1 0x45670123
#define FLASH_KEY2 0xcdef89ab
#define FLASH_L0_PRGKEY1 0x8c9daebf
#define FLASH_L0_PRGKEY2 0x13141516
#define FLASH_L0_PEKEY1 0x89abcdef
#define FLASH_L0_PEKEY2 0x02030405
#define FLASH_OPTKEY1 0x08192A3B
#define FLASH_OPTKEY2 0x4C5D6E7F
#define FLASH_F0_OPTKEY1 0x45670123
#define FLASH_F0_OPTKEY2 0xCDEF89AB
#define FLASH_L0_OPTKEY1 0xFBEAD9C8
#define FLASH_L0_OPTKEY2 0x24252627
#define FLASH_SR_BSY 0
#define FLASH_SR_PG_ERR 2
#define FLASH_SR_WRPRT_ERR 4
#define FLASH_SR_EOP 5
#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR))
#define FLASH_CR_PG 0
#define FLASH_CR_PER 1
#define FLASH_CR_MER 2
#define FLASH_CR_OPTPG 4
#define FLASH_CR_OPTER 5
#define FLASH_CR_STRT 6
#define FLASH_CR_LOCK 7
#define FLASH_CR_OPTWRE 9
#define FLASH_CR_OBL_LAUNCH 13
#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
#define FLASH_L1_FPRG 10
#define FLASH_L1_PROG 3
// Flash registers common to STM32G0 and STM32G4 series.
#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000)
#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00)
#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08)
#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c)
#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10)
#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14)
#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18)
#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20)
// G0 (RM0444 Table 1, sec 3.7)
// Mostly the same as G4 chips, but the notation
// varies a bit after the 'OPTR' register.
#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR)
#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24)
#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28)
#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C)
#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30)
#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34)
#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38)
#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80)
// G4 (RM0440 Table 17, sec 3.7.19)
// Mostly the same as STM32G0 chips, but there are a few extra
// registers because 'cat 3' devices can have two Flash banks.
#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR)
#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04)
#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24)
#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28)
#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C)
#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30)
#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44)
#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48)
#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C)
#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50)
#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70)
#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74)
// G0/G4 FLASH control register
#define STM32Gx_FLASH_CR_PG (0) /* Program */
#define STM32Gx_FLASH_CR_PER (1) /* Page erase */
#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */
#define STM32Gx_FLASH_CR_PNB (3) /* Page number */
#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */
#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */
#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/
#define STM32Gx_FLASH_CR_STRT (16) /* Start */
#define STM32Gx_FLASH_CR_OPTSTRT \
(17) /* Start of modification of option bytes */
#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */
#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */
#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */
#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */
#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */
#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */
// G0/G4 FLASH status register
#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa)
#define STM32Gx_FLASH_SR_PROGERR (3)
#define STM32Gx_FLASH_SR_WRPERR (4)
#define STM32Gx_FLASH_SR_PGAERR (5)
#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */
#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */
// G4 FLASH option register
#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */
// WB (RM0434)
#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000)
#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00)
#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08)
#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C)
#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10)
#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14)
#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18)
#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20)
#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24)
#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28)
#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C)
#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30)
#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34)
#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38)
#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C)
#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C)
#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60)
#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64)
#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80)
#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84)
// WB Flash control register.
#define STM32WB_FLASH_CR_STRT (16) /* Start */
#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */
#define STM32WB_FLASH_CR_LOCK (31) /* Lock */
// WB Flash status register.
#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */
#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */
#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */
#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */
#define STM32WB_FLASH_SR_BSY (16) /* Busy */
// 32L4 register base is at FLASH_REGS_ADDR (0x40022000)
#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08)
#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C)
#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10)
#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14)
#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20)
#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */
#define STM32L4_FLASH_SR_PROGERR 3
#define STM32L4_FLASH_SR_WRPERR 4
#define STM32L4_FLASH_SR_PGAERR 5
#define STM32L4_FLASH_SR_BSY 16
#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */
#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */
#define STM32L4_FLASH_CR_PG 0 /* Program */
#define STM32L4_FLASH_CR_PER 1 /* Page erase */
#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */
#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */
#define STM32L4_FLASH_CR_STRT 16 /* Start command */
#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */
#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */
#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */
#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */
// Bits requesting flash operations (useful when we want to clear them)
#define STM32L4_FLASH_CR_OPBITS \
(uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \
(1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1))
// Page is fully specified by BKER and PNB
#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB)
#define STM32L4_FLASH_OPTR_DUALBANK 21
// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf
#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
#define STM32L1_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
#define STM32L0_FLASH_PELOCK (0)
#define STM32L0_FLASH_OPTLOCK (2)
#define STM32L0_FLASH_OBL_LAUNCH (18)
#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00
#define STM32L0_FLASH_SR_WRPERR 8
#define STM32L0_FLASH_SR_PGAERR 9
#define STM32L0_FLASH_SR_NOTZEROERR 16
#define FLASH_ACR_OFF ((uint32_t)0x00)
#define FLASH_PECR_OFF ((uint32_t)0x04)
#define FLASH_PDKEYR_OFF ((uint32_t)0x08)
#define FLASH_PEKEYR_OFF ((uint32_t)0x0c)
#define FLASH_PRGKEYR_OFF ((uint32_t)0x10)
#define FLASH_OPTKEYR_OFF ((uint32_t)0x14)
#define FLASH_SR_OFF ((uint32_t)0x18)
#define FLASH_OBR_OFF ((uint32_t)0x1c)
#define FLASH_WRPR_OFF ((uint32_t)0x20)
// STM32F7
#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00)
#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04)
#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08)
#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c)
#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10)
#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14)
#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18)
#define FLASH_F7_OPTCR_LOCK 0
#define FLASH_F7_OPTCR_START 1
#define FLASH_F7_CR_STRT 16
#define FLASH_F7_CR_LOCK 31
#define FLASH_F7_CR_SER 1
#define FLASH_F7_CR_SNB 3
#define FLASH_F7_CR_SNB_MASK 0xf8
#define FLASH_F7_SR_BSY 16
#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */
#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */
#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */
#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */
#define FLASH_F7_SR_OP_ERR 1 /* Operation error */
#define FLASH_F7_SR_EOP 0 /* End of operation */
#define FLASH_F7_OPTCR1_BOOT_ADD0 0
#define FLASH_F7_OPTCR1_BOOT_ADD1 16
#define FLASH_F7_SR_ERROR_MASK \
((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \
(1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \
(1 << FLASH_F7_SR_OP_ERR))
// STM32F4
#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14)
#define FLASH_F4_OPTCR_LOCK 0
#define FLASH_F4_OPTCR_START 1
#define FLASH_F4_CR_STRT 16
#define FLASH_F4_CR_LOCK 31
#define FLASH_F4_CR_SER 1
#define FLASH_F4_CR_SNB 3
#define FLASH_F4_CR_SNB_MASK 0xf8
#define FLASH_F4_SR_ERROR_MASK 0x000000F0
#define FLASH_F4_SR_PGAERR 5
#define FLASH_F4_SR_WRPERR 4
#define FLASH_F4_SR_BSY 16
// STM32F2
#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00)
#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04)
#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08)
#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c)
#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10)
#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14)
#define FLASH_F2_OPT_LOCK_BIT (1u << 0)
#define FLASH_F2_CR_STRT 16
#define FLASH_F2_CR_LOCK 31
#define FLASH_F2_CR_SER 1
#define FLASH_F2_CR_SNB 3
#define FLASH_F2_CR_SNB_MASK 0x78
#define FLASH_F2_SR_BSY 16
// STM32H7xx
#define FLASH_H7_CR_LOCK 0
#define FLASH_H7_CR_PG 1
#define FLASH_H7_CR_SER 2
#define FLASH_H7_CR_BER 3
#define FLASH_H7_CR_PSIZE 4
#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7AX ? 5 : 7)
#define FLASH_H7_CR_SNB 8
#define FLASH_H7_CR_SNB_MASK 0x700
#define FLASH_H7_SR_QW 2
#define FLASH_H7_SR_WRPERR 17
#define FLASH_H7_SR_PGSERR 18
#define FLASH_H7_SR_STRBERR 19
#define FLASH_H7_SR_ERROR_MASK \
((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \
(1 << FLASH_H7_SR_WRPERR))
#define FLASH_H7_OPTCR_OPTLOCK 0
#define FLASH_H7_OPTCR_OPTSTART 1
#define FLASH_H7_OPTCR_MER 4
#define FLASH_H7_OPTSR_OPT_BUSY 0
#define FLASH_H7_OPTSR_OPTCHANGEERR 30
#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30
#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000)
#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04)
#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104)
#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08)
#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108)
#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c)
#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c)
#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10)
#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110)
#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14)
#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114)
#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18)
#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118)
#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c)
#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24)
#define STM32F0_DBGMCU_CR 0xE0042004
#define STM32F0_DBGMCU_CR_IWDG_STOP 8
#define STM32F0_DBGMCU_CR_WWDG_STOP 9
#define STM32F4_DBGMCU_APB1FZR1 0xE0042008
#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11
#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12
#define STM32L0_DBGMCU_APB1_FZ 0x40015808
#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11
#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12
#define STM32H7_DBGMCU_APB1HFZ 0x5C001054
#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18
#define STM32WB_DBGMCU_APB1FZR1 0xE004203C
#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11
#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12
#define STM32F1_RCC_AHBENR 0x40021014
#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
#define STM32F4_RCC_AHB1ENR 0x40023830
#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN
#define STM32G0_RCC_AHBENR 0x40021038
#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
#define STM32G4_RCC_AHB1ENR 0x40021048
#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
#define STM32L0_RCC_AHBENR 0x40021030
#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN
#define STM32H7_RCC_AHB1ENR 0x58024538
#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
#define STM32WB_RCC_AHB1ENR 0x58000048
#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
#define L1_WRITE_BLOCK_SIZE 0x80
#define L0_WRITE_BLOCK_SIZE 0x40
// Endianness
// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html
// These functions encode and decode little endian uint16 and uint32 values.
void write_uint32(unsigned char *buf, uint32_t ui) {
buf[0] = ui;
buf[1] = ui >> 8;
buf[2] = ui >> 16;
buf[3] = ui >> 24;
}
void write_uint16(unsigned char *buf, uint16_t ui) {
buf[0] = ui;
buf[1] = ui >> 8;
}
uint32_t read_uint32(const unsigned char *c, const int pt) {
return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) |
((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24);
}
uint16_t read_uint16(const unsigned char *c, const int pt) {
return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8);
}
static uint32_t get_stm32l0_flash_base(stlink_t *sl) {
switch (sl->chip_id) {
case STLINK_CHIPID_STM32_L0:
case STLINK_CHIPID_STM32_L0_CAT5:
case STLINK_CHIPID_STM32_L0_CAT2:
case STLINK_CHIPID_STM32_L011:
return (STM32L0_FLASH_REGS_ADDR);
case STLINK_CHIPID_STM32_L1_CAT2:
case STLINK_CHIPID_STM32_L1_MEDIUM:
case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS:
case STLINK_CHIPID_STM32_L1_HIGH:
return (STM32L1_FLASH_REGS_ADDR);
default:
WLOG("Flash base use default L0 address");
return (STM32L0_FLASH_REGS_ADDR);
}
}
static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
uint32_t rdp;
stlink_read_debug32(sl, FLASH_WRPR, &rdp);
return (rdp & 0xff);
}
static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) {
uint32_t reg, res;
if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
reg = FLASH_F4_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F7) {
reg = FLASH_F7_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
reg = STM32L4_FLASH_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_G0 ||
sl->flash_type == STLINK_FLASH_TYPE_G4) {
reg = STM32Gx_FLASH_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
reg = STM32WB_FLASH_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2;
} else {
reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2;
}
stlink_read_debug32(sl, reg, &res);
#if DEBUG_FLASH
fprintf(stdout, "CR:0x%x\n", res);
#endif
return (res);
}
static inline unsigned int is_flash_locked(stlink_t *sl) {
/* return non zero for true */
uint32_t cr_lock_shift;
uint32_t cr_reg;
uint32_t n;
if ((sl->flash_type == STLINK_FLASH_TYPE_F0) ||
(sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) {
cr_reg = FLASH_CR;
cr_lock_shift = FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
cr_reg = FLASH_F4_CR;
cr_lock_shift = FLASH_F4_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F7) {
cr_reg = FLASH_F7_CR;
cr_lock_shift = FLASH_F7_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L0) {
cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF;
cr_lock_shift = STM32L0_FLASH_PELOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
cr_reg = STM32L4_FLASH_CR;
cr_lock_shift = STM32L4_FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_G0 ||
sl->flash_type == STLINK_FLASH_TYPE_G4) {
cr_reg = STM32Gx_FLASH_CR;
cr_lock_shift = STM32Gx_FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
cr_lock_shift = STM32WB_FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
cr_reg = FLASH_H7_CR1;
cr_lock_shift = FLASH_H7_CR_LOCK;
} else {
ELOG("unsupported flash method, abort\n");
return (-1);
}
stlink_read_debug32(sl, cr_reg, &n);
return (n & (1u << cr_lock_shift));
}
static void unlock_flash(stlink_t *sl) {
uint32_t key_reg, key2_reg = 0;
uint32_t flash_key1 = FLASH_KEY1;
uint32_t flash_key2 = FLASH_KEY2;
/* The unlock sequence consists of 2 write cycles where 2 key values are
* written to the FLASH_KEYR register. An invalid sequence results in a
* definitive lock of the FPEC block until next reset.
*/
if (sl->flash_type == STLINK_FLASH_TYPE_F0) {
key_reg = FLASH_KEYR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) {
key_reg = FLASH_KEYR;
key2_reg = FLASH_KEYR2;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
key_reg = FLASH_F4_KEYR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F7) {
key_reg = FLASH_F7_KEYR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L0) {
key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF;
flash_key1 = FLASH_L0_PEKEY1;
flash_key2 = FLASH_L0_PEKEY2;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
key_reg = STM32L4_FLASH_KEYR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_G0 ||
sl->flash_type == STLINK_FLASH_TYPE_G4) {
key_reg = STM32Gx_FLASH_KEYR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
key_reg = STM32WB_FLASH_KEYR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
key_reg = FLASH_H7_KEYR1;
if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) {
key2_reg = FLASH_H7_KEYR2;
}
} else {
ELOG("unsupported flash method, abort\n");
return;
}
stlink_write_debug32(sl, key_reg, flash_key1);
stlink_write_debug32(sl, key_reg, flash_key2);
if (key2_reg) {
stlink_write_debug32(sl, key2_reg, flash_key1);
stlink_write_debug32(sl, key2_reg, flash_key2);
}
}
/* unlock flash if already locked */
static int unlock_flash_if(stlink_t *sl) {
if (is_flash_locked(sl)) {
unlock_flash(sl);
if (is_flash_locked(sl)) {
WLOG("Failed to unlock flash!\n");
return (-1);
}
}
DLOG("Successfully unlocked flash\n");
return (0);
}
static void lock_flash(stlink_t *sl) {
uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0;
uint32_t cr_mask = 0xffffffffu;
if (sl->flash_type == STLINK_FLASH_TYPE_F0) {
cr_reg = FLASH_CR;
cr_lock_shift = FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) {
cr_reg = FLASH_CR;
cr2_reg = FLASH_CR2;
cr_lock_shift = FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
cr_reg = FLASH_F4_CR;
cr_lock_shift = FLASH_F4_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F7) {
cr_reg = FLASH_F7_CR;
cr_lock_shift = FLASH_F7_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L0) {
cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF;
cr_lock_shift = STM32L0_FLASH_PELOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
cr_reg = STM32L4_FLASH_CR;
cr_lock_shift = STM32L4_FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_G0 ||
sl->flash_type == STLINK_FLASH_TYPE_G4) {
cr_reg = STM32Gx_FLASH_CR;
cr_lock_shift = STM32Gx_FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
cr_lock_shift = STM32WB_FLASH_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
cr_reg = FLASH_H7_CR1;
if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) {
cr2_reg = FLASH_H7_CR2;
}
cr_lock_shift = FLASH_H7_CR_LOCK;
cr_mask = ~(1u << FLASH_H7_CR_SER);
} else {
ELOG("unsupported flash method, abort\n");
return;
}
stlink_read_debug32(sl, cr_reg, &n);
n &= cr_mask;
n |= (1u << cr_lock_shift);
stlink_write_debug32(sl, cr_reg, n);
if (cr2_reg) {
n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift);
stlink_write_debug32(sl, cr2_reg, n);
}
}
static bool is_flash_option_locked(stlink_t *sl) {
uint32_t optlock_shift, optcr_reg;
int active_bit_level = 1;
uint32_t n;
switch (sl->flash_type) {
case STLINK_FLASH_TYPE_F0:
case STLINK_FLASH_TYPE_F1_XL:
optcr_reg = FLASH_CR;
optlock_shift = FLASH_CR_OPTWRE;
active_bit_level = 0; /* bit is "option write enable", not lock */
break;
case STLINK_FLASH_TYPE_F4:
optcr_reg = FLASH_F4_OPTCR;
optlock_shift = FLASH_F4_OPTCR_LOCK;
break;
case STLINK_FLASH_TYPE_F7:
optcr_reg = FLASH_F7_OPTCR;
optlock_shift = FLASH_F7_OPTCR_LOCK;
break;
case STLINK_FLASH_TYPE_L0:
optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF;
optlock_shift = STM32L0_FLASH_OPTLOCK;
break;
case STLINK_FLASH_TYPE_L4:
optcr_reg = STM32L4_FLASH_CR;
optlock_shift = STM32L4_FLASH_CR_OPTLOCK;
break;
case STLINK_FLASH_TYPE_G0:
case STLINK_FLASH_TYPE_G4:
optcr_reg = STM32Gx_FLASH_CR;
optlock_shift = STM32Gx_FLASH_CR_OPTLOCK;
break;
case STLINK_FLASH_TYPE_WB:
optcr_reg = STM32WB_FLASH_CR;
optlock_shift = STM32WB_FLASH_CR_OPTLOCK;
break;
case STLINK_FLASH_TYPE_H7:
optcr_reg = FLASH_H7_OPTCR;
optlock_shift = FLASH_H7_OPTCR_OPTLOCK;
break;
default:
ELOG("unsupported flash method, abort\n");
return -1;
}
stlink_read_debug32(sl, optcr_reg, &n);
if (active_bit_level == 0) {
return (!(n & (1u << optlock_shift)));
}
return (n & (1u << optlock_shift));
}
static int lock_flash_option(stlink_t *sl) {
uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0;
int active_bit_level = 1;
switch (sl->flash_type) {
case STLINK_FLASH_TYPE_F0:
case STLINK_FLASH_TYPE_F1_XL:
optcr_reg = FLASH_CR;
optlock_shift = FLASH_CR_OPTWRE;
active_bit_level = 0;
break;
case STLINK_FLASH_TYPE_F4:
optcr_reg = FLASH_F4_OPTCR;
optlock_shift = FLASH_F4_OPTCR_LOCK;
break;
case STLINK_FLASH_TYPE_F7:
optcr_reg = FLASH_F7_OPTCR;
optlock_shift = FLASH_F7_OPTCR_LOCK;
break;
case STLINK_FLASH_TYPE_L0:
optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF;
optlock_shift = STM32L0_FLASH_OPTLOCK;
break;
case STLINK_FLASH_TYPE_L4:
optcr_reg = STM32L4_FLASH_CR;
optlock_shift = STM32L4_FLASH_CR_OPTLOCK;
break;
case STLINK_FLASH_TYPE_G0:
case STLINK_FLASH_TYPE_G4:
optcr_reg = STM32Gx_FLASH_CR;
optlock_shift = STM32Gx_FLASH_CR_OPTLOCK;
break;
case STLINK_FLASH_TYPE_WB:
optcr_reg = STM32WB_FLASH_CR;
optlock_shift = STM32WB_FLASH_CR_OPTLOCK;
break;
case STLINK_FLASH_TYPE_H7:
optcr_reg = FLASH_H7_OPTCR;
optlock_shift = FLASH_H7_OPTCR_OPTLOCK;
if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK)
optcr2_reg = FLASH_H7_OPTCR2;
break;
default:
ELOG("unsupported flash method, abort\n");
return -1;
}
stlink_read_debug32(sl, optcr_reg, &n);
if (active_bit_level == 0) {
n &= ~(1u << optlock_shift);
} else {
n |= (1u << optlock_shift);
}
stlink_write_debug32(sl, optcr_reg, n);
if (optcr2_reg) {
stlink_read_debug32(sl, optcr2_reg, &n);
if (active_bit_level == 0) {
n &= ~(1u << optlock_shift);
} else {
n |= (1u << optlock_shift);
}
stlink_write_debug32(sl, optcr2_reg, n);
}
return (0);
}
static int unlock_flash_option(stlink_t *sl) {
uint32_t optkey_reg, optkey2_reg = 0;
uint32_t optkey1 = FLASH_OPTKEY1;
uint32_t optkey2 = FLASH_OPTKEY2;
switch (sl->flash_type) {
case STLINK_FLASH_TYPE_F0:
case STLINK_FLASH_TYPE_F1_XL:
optkey_reg = FLASH_OPTKEYR;
optkey1 = FLASH_F0_OPTKEY1;
optkey2 = FLASH_F0_OPTKEY2;
break;
case STLINK_FLASH_TYPE_F4:
optkey_reg = FLASH_F4_OPT_KEYR;
break;
case STLINK_FLASH_TYPE_F7:
optkey_reg = FLASH_F7_OPT_KEYR;
break;
case STLINK_FLASH_TYPE_L0:
optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF;
optkey1 = FLASH_L0_OPTKEY1;
optkey2 = FLASH_L0_OPTKEY2;
break;
case STLINK_FLASH_TYPE_L4:
optkey_reg = STM32L4_FLASH_OPTKEYR;
break;
case STLINK_FLASH_TYPE_G0:
case STLINK_FLASH_TYPE_G4:
optkey_reg = STM32Gx_FLASH_OPTKEYR;
break;
case STLINK_FLASH_TYPE_WB:
optkey_reg = STM32WB_FLASH_OPT_KEYR;
break;
case STLINK_FLASH_TYPE_H7:
optkey_reg = FLASH_H7_OPT_KEYR;
if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK)
optkey2_reg = FLASH_H7_OPT_KEYR2;
break;
default:
ELOG("unsupported flash method, abort\n");
return (-1);
}
stlink_write_debug32(sl, optkey_reg, optkey1);
stlink_write_debug32(sl, optkey_reg, optkey2);
if (optkey2_reg) {
stlink_write_debug32(sl, optkey2_reg, optkey1);
stlink_write_debug32(sl, optkey2_reg, optkey2);
}
return (0);
}
static int unlock_flash_option_if(stlink_t *sl) {
if (is_flash_option_locked(sl)) {
if (unlock_flash_option(sl)) {
ELOG("Could not unlock flash option!\n");
return (-1);
}
if (is_flash_option_locked(sl)) {
ELOG("Failed to unlock flash option!\n");
return (-1);
}
}
DLOG("Successfully unlocked flash option\n");
return (0);
}
static void set_flash_cr_pg(stlink_t *sl, unsigned bank) {
uint32_t cr_reg, x;
x = read_flash_cr(sl, bank);
if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
cr_reg = FLASH_F4_CR;
x |= 1 << FLASH_CR_PG;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F7) {
cr_reg = FLASH_F7_CR;
x |= 1 << FLASH_CR_PG;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
cr_reg = STM32L4_FLASH_CR;
x &= ~STM32L4_FLASH_CR_OPBITS;
x |= (1 << STM32L4_FLASH_CR_PG);
} else if (sl->flash_type == STLINK_FLASH_TYPE_G0 ||
sl->flash_type == STLINK_FLASH_TYPE_G4) {
cr_reg = STM32Gx_FLASH_CR;
x |= (1 << FLASH_CR_PG);
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
x |= (1 << FLASH_CR_PG);
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2;
x |= (1 << FLASH_H7_CR_PG);
} else {
cr_reg = FLASH_CR;
x = (1 << FLASH_CR_PG);
}
stlink_write_debug32(sl, cr_reg, x);
}
static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) {
uint32_t cr_reg, n;
uint32_t bit = FLASH_CR_PG;
if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
cr_reg = FLASH_F4_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F7) {
cr_reg = FLASH_F7_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
cr_reg = STM32L4_FLASH_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_G0 ||
sl->flash_type == STLINK_FLASH_TYPE_G4) {
cr_reg = STM32Gx_FLASH_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2;
bit = FLASH_H7_CR_PG;
} else {
cr_reg = FLASH_CR;
}
n = read_flash_cr(sl, bank) & ~(1 << bit);
stlink_write_debug32(sl, cr_reg, n);
}
static void set_flash_cr_per(stlink_t *sl, unsigned bank) {
uint32_t cr_reg, val;
if (sl->flash_type == STLINK_FLASH_TYPE_G0 ||
sl->flash_type == STLINK_FLASH_TYPE_G4) {
cr_reg = STM32Gx_FLASH_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
} else {
cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2;
}
stlink_read_debug32(sl, cr_reg, &val);
val |= (1 << FLASH_CR_PER);
stlink_write_debug32(sl, cr_reg, val);
}
static void clear_flash_cr_per(stlink_t *sl, unsigned bank) {
uint32_t cr_reg;
if (sl->flash_type == STLINK_FLASH_TYPE_G0 ||
sl->flash_type == STLINK_FLASH_TYPE_G4) {
cr_reg = STM32Gx_FLASH_CR;
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
} else {
cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2;
}
const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER);
stlink_write_debug32(sl, cr_reg, n);
}
static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) {
uint32_t val, cr_reg, cr_mer, cr_pg;
if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
cr_reg = FLASH_F4_CR;
cr_mer = 1 << FLASH_CR_MER;
cr_pg = 1 << FLASH_CR_PG;
} else if (sl->flash_type == STLINK_FLASH_TYPE_F7) {
cr_reg = FLASH_F7_CR;
cr_mer = 1 << FLASH_CR_MER;
cr_pg = 1 << FLASH_CR_PG;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
cr_reg = STM32L4_FLASH_CR;
cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2);
cr_pg = (1 << STM32L4_FLASH_CR_PG);
} else if (sl->flash_type == STLINK_FLASH_TYPE_G0 ||
sl->flash_type == STLINK_FLASH_TYPE_G4) {
cr_reg = STM32Gx_FLASH_CR;
cr_mer = (1 << STM32Gx_FLASH_CR_MER1);
if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) {
cr_mer |= (1 << STM32Gx_FLASH_CR_MER2);
}
cr_pg = (1 << FLASH_CR_PG);
} else if (sl->flash_type == STLINK_FLASH_TYPE_WB) {
cr_reg = STM32WB_FLASH_CR;
cr_mer = (1 << FLASH_CR_MER);
cr_pg = (1 << FLASH_CR_PG);
} else if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2;
cr_mer = (1 << FLASH_H7_CR_BER);
cr_pg = (1 << FLASH_H7_CR_PG);
} else {
cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2;
cr_mer = (1 << FLASH_CR_MER);
cr_pg = (1 << FLASH_CR_PG);
}
stlink_read_debug32(sl, cr_reg, &val);
if (val & cr_pg) {
// STM32F030 will drop MER bit if PG was set
val &= ~cr_pg;
stlink_write_debug32(sl, cr_reg, val);
}
if (v) {
val |= cr_mer;
} else {
val &= ~cr_mer;
}
stlink_write_debug32(sl, cr_reg, val);
}
static void set_flash_cr_strt(stlink_t *sl, unsigned bank) {
uint32_t val, cr_reg, cr_strt;