-
Notifications
You must be signed in to change notification settings - Fork 0
/
scr_util.list
4289 lines (3945 loc) · 200 KB
/
scr_util.list
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
COMPILATION LISTING OF SEGMENT scr_util
Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989
Compiled at: Bull HN, Phoenix AZ, System-M
Compiled on: 11/11/89 0943.8 mst Sat
Options: optimize list
1 /****^ ***********************************************************
2* * *
3* * Copyright, (C) Honeywell Bull Inc., 1987 *
4* * *
5* * Copyright, (C) Honeywell Information Systems Inc., 1982 *
6* * *
7* *********************************************************** */
8 /* SCR_UTIL - Procedure to Manipulate System Controller Registers and Data.
9* coded 2/1/76 by Noel I. Morris
10* modified 5/11/78 by J. A. Bush for processor testing
11* modified 2/5/79 by B. Greenberg for port expanders.
12* modified May 1981 by J. Bongiovanni to set anti-hog switches,
13* validate sscr
14**/
15
16
17 /* ******************************************************
18* * *
19* * *
20* * Copyright (c) 1972 by Massachusetts Institute of *
21* * Technology and Honeywell Information Systems, Inc. *
22* * *
23* * *
24* ****************************************************** */
25
26
27 scr_util$read_cfg: proc (port);
28
29 dcl port fixed bin (3); /* controller port number on active modules */
30
31 dcl mr_data fixed bin (71), /* data from RSCR-MR */
32 i fixed bin, /* iteration variable */
33 ctag fixed bin (3), /* system controller tag */
34 bitno fixed bin, /* mask bit offset */
35 iscu fixed bin (5), /* ISOLTS SCU tag */
36 icpu fixed bin (5), /* ISOLTS CPU tag */
37 mcpu fixed bin (5), /* ISOLTS mask cpu */
38 (maska, maskb) bit (9), /* temporary mask reg storage */
39 (store_a_size, store_b_size) fixed bin (17), /* size of stores A & B */
40 scr_cfg2_temp fixed bin (71) aligned, /* temp rscr storage */
41 set_cfg_try_count fixed bin, /* number times tried sscr */
42 set_cfg_ok bit (1) aligned,
43 mask_a_val char (3),
44 mask_b_val char (3),
45 cycle_priority_bits (7) bit (1),
46 port_enable_bits (8) bit (1),
47 nea_bits (7) bit (1);
48
49
50
51
52 dcl 1 cdata aligned like scs$controller_data based (cdp), /* single element of scs$controller data */
53 cdp ptr, /* pointer to the above */
54 1 pdata aligned like scs$processor_data based (pdp), /* single element of scs$processor_data */
55 pdp ptr; /* pointer to the above */
56
57 dcl masks (3) bit (72) aligned based (mkp), /* array of interrupt masks */
58 mkp ptr; /* pointer to the above */
59
60 dcl scr_cfg2_temp_overlay bit (72) aligned defined (scr_cfg2_temp);
61
62
63 dcl SCR_CFG2_PROGRAM_MASK bit (72) aligned int static options (constant)
64 init ("777774037777777000077417"b3); /* program settable bits in config register */
65 dcl SET_CFG_TRY_LIMIT fixed bin int static options (constant)
66 init (10); /* number sscr attempts before punting */
67 dcl LETTERS char (8) int static options (constant) init ("ABCDEFGH");
68
69 dcl privileged_mode_ut$cioc entry (ptr),
70 privileged_mode_ut$rscr entry (fixed bin (3), fixed bin (6), fixed bin (71)),
71 privileged_mode_ut$sscr entry (fixed bin (3), fixed bin (6), fixed bin (71)),
72 privileged_mode_ut$smcm entry (fixed bin (3), bit (72) aligned),
73 syserr entry options (variable);
74
75
76 dcl (addr, bin, bit, convert, index, mod, string, substr, unspec) builtin;
77
78
79
1 1 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */
1 2 /* format: style4 */
1 3
1 4 /* Information about system controllers */
1 5
1 6 dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */
1 7 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */
1 8 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */
1 9 2 eima_data (4) unaligned, /* EIMA information for this controller */
1 10 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */
1 11 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */
1 12 3 mbz bit (3) unaligned,
1 13 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */
1 14 2 info aligned,
1 15 3 online bit (1) unaligned, /* ON if controller is online */
1 16 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */
1 17 3 store_a_online bit (1) unaligned, /* ON if store A is online */
1 18 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */
1 19 3 store_b_online bit (1) unaligned, /* ON if store B is online */
1 20 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */
1 21 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */
1 22 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */
1 23 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */
1 24 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */
1 25 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */
1 26 3 type bit (4) unaligned, /* Model number for this controller */
1 27 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */
1 28 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */
1 29 3 mbz bit (13) unaligned,
1 30 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */
1 31 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */
1 32
1 33 /* Information about CPUs */
1 34
1 35 dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */
1 36 (
1 37 2 online bit (1), /* "1"b if CPU is online */
1 38 2 offline bit (1), /* "1"b if CPU is offline but can be added */
1 39 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */
1 40 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */
1 41 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */
1 42 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */
1 43 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */
1 44 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */
1 45 2 mbz1 bit (6),
1 46 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache;
1 47* 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache;
1 48* 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache
1 49* 7 = ignore cache size (set by ISOLTS reconfig) */
1 50 2 mbz2 bit (12),
1 51 2 expanded_port bit (1), /* "1"b = on expanded port */
1 52 2 expander_port fixed bin (2) unsigned, /* The actual expander port */
1 53 2 controller_port fixed bin (3) unsigned
1 54 ) unaligned; /* Port on controller */
1 55
1 56 dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */
1 57 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */
1 58 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */
1 59 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */
1 60 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */
1 61 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */
1 62 /* cpu_number (0) is only one if expander_port is "0"b */
1 63 2 pad bit (12) unaligned;
1 64
1 65 dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */
1 66 2 pad bit (36) aligned, /* Expander COW's must be odd-word */
1 67 2 cow,
1 68 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */
1 69 3 mbz1 bit (13) unaligned,
1 70 3 expander_command bit (3) unaligned, /* Expander command. */
1 71 3 mbz2 bit (2) unaligned,
1 72 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */
1 73 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */
1 74 3 mbz3 bit (3) unaligned,
1 75 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */
1 76
1 77 dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */
1 78 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */
1 79 2 pad bit (12) unal,
1 80 2 tag bit (6) unal; /* Better be zero. */
1 81
1 82 dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */
1 83 2 pad bit (36) aligned,
1 84 2 cow, /* Connect operand word, in odd location. */
1 85 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */
1 86 3 mbz1 bit (13) unaligned,
1 87 3 expander_command bit (3) unaligned, /* Expander command. */
1 88 3 mbz2 bit (9) unaligned,
1 89 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */
1 90
1 91 /* MASKS and PATTERNS */
1 92
1 93 dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */
1 94 dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */
1 95 dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */
1 96 dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */
1 97 dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */
1 98 dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */
1 99 dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */
1 100
1 101 /* CAM and CACHE clear info */
1 102
1 103 dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */
1 104 dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */
1 105
1 106 /* MASKING INSTRUCTIONS & POINTERS */
1 107
1 108 dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */
1 109 dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */
1 110 dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */
1 111
1 112 /* MISCELLANEOUS */
1 113
1 114 dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */
1 115 (
1 116 2 active bit (1), /* = "1"b if cpu currently under test */
1 117 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */
1 118 2 pad1 bit (4),
1 119 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */
1 120 2 cpu_tag fixed bin (5), /* tag of cpu under test */
1 121 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */
1 122 2 mask_cpu fixed bin (5)
1 123 ) unaligned; /* tag of active cpu that has mask asigned to above scu */
1 124
1 125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */
1 126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */
1 127 /* scu_state = "10"b => all core removed from SCU, port mask changed */
1 128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */
1 129
1 130 dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */
1 131
1 132 dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */
1 133 dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */
1 134 dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */
1 135 dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */
1 136 dcl scs$nprocessors fixed bin ext; /* number of runnung processors */
1 137 dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */
1 138 dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */
1 139 dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */
1 140 dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */
1 141 dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */
1 142 dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */
1 143 dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */
1 144 dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */
1 145
1 146 dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */
1 147
1 148 dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */
1 149
1 150 dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */
1 151
1 152 dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */
1 153
1 154 dcl scs$expanded_ports bit (1) unaligned dim (0:7) external;
1 155 /* Which ports have expanders */
1 156
1 157 dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */
1 158 dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */
1 159 dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */
1 160 dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */
1 161
1 162 dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */
1 163
1 164 dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext;
1 165 /* Controller size on config card */
1 166
1 167 dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */
1 168
1 169 dcl scs$scas_page_table (0:31) bit (36) aligned external static;
1 170 /* PTWs for SCAS pages */
1 171
1 172 dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */
1 173 dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */
1 174
1 175
1 176 dcl (
1 177 IOM_PORT init (1),
1 178 CPU_PORT init (2),
1 179 BULK_PORT init (3)
1 180 ) fixed bin int static options (constant); /* values for scs$port_data.assigned */
1 181
1 182
1 183 /* END INCLUDE FILE scs.incl.pl1 */
80
81
82
2 1 /* Begin include file ...... scr.incl.pl1
2 2* modified 5/75 by Noel I. Morris
2 3* modified 10/81 by M.R. Jordan for 64K chip, M64 memory
2 4* modified '83 to make values constant */
2 5
2 6 /* This include file is to be used in conjunction with pmut$rscr and pmut$sscr.
2 7* Wherever possible the terms in the processor manual are used in the declaration. */
2 8
2 9 dcl (SC_MR init (0), /* SC Mode Register */
2 10 SC_CFG init (1), /* SC Configuration Switches */
2 11 SC_MSK init (2), /* SC Interrupt Mask */
2 12 SC_IC init (3), /* SC Interrupt Cells */
2 13 SC_ETC init (4), /* SC Elapsed Time Clock */
2 14 SC_SU init (6)) fixed bin (6) static options (constant); /* SU Mode Register */
2 15
2 16
2 17 dcl scrp ptr; /* pointer to SC data */
2 18
2 19 dcl 1 scr_cfg1 based (scrp) aligned, /* configuration data for 6000 SC */
2 20
2 21 (2 mode_a bit (3), /* 000 => on-line
2 22* 001 => test mode
2 23* 010 => off-line */
2 24 2 bdry_a bit (3), /* 000 => 32K, 001 => 64K, etc */
2 25 2 mode_b bit (3), /* see mode_a */
2 26 2 bdry_b bit (3), /* see bdry_a */
2 27 2 int bit (1), /* 1 => stores are internally interlaced */
2 28 2 lwr bit (1), /* 1 => store B is low */
2 29 2 addr_offset bit (2), /* 00 => no offset, 01 => 32K offset, etc. */
2 30 2 port_no bit (4), /* requester's port number */
2 31 2 port_enable (0:7) bit (2), /* 00 => port disabled
2 32* 01 => port under program control
2 33* 11 => port enabled */
2 34 2 pima (4) bit (9)) unaligned; /* program interrupt mask assignments
2 35* 000 => unassigned
2 36* 400 => assigned to port 0
2 37* 200 => assigned to port 1
2 38* .
2 39* .
2 40* .
2 41* 002 => assigned to port 7
2 42* 001 => assigned to maint. panel */
2 43
2 44
2 45 dcl 1 scr_cfg2 based (scrp) aligned, /* configuration data for 4MW SCU */
2 46
2 47 (2 mask_a_assign bit (9), /* interrupt mask "A" port assignment
2 48* 400 => assigned to port 0
2 49* .
2 50* .
2 51* 002 => assigned to port 7
2 52* 001 => mask off */
2 53 2 size bit (3), /* size of lower store */
2 54 2 a_online bit (1), /* 1 => store A online */
2 55 2 a1_online bit (1), /* 1 => store A1 online */
2 56 2 b_online bit (1), /* 1 => store B online */
2 57 2 b1_online bit (1), /* 1 => store B1 online */
2 58 2 port_no bit (4), /* requester's port number */
2 59 2 pad1 bit (1),
2 60 2 mode bit (1), /* 1 => programmable mode */
2 61 2 nea_enabled bit (1), /* 1 => non-existent address logic enabled */
2 62 2 nea bit (7), /* 001 => 32K, 002 => 64K, 003 => 96K, etc. */
2 63 2 int bit (1), /* 1 => stores are internally interlaced */
2 64 2 lwr bit (1), /* 1 => store B is low */
2 65 2 port_mask_0_3 bit (4), /* 1 => corresponding port enabled */
2 66
2 67 2 mask_b_assign bit (9), /* interrupt mask "B" port assignment */
2 68 2 pad2 bit (12),
2 69 2 cyclic_prior bit (7), /* cyclic port priority switches */
2 70 2 pad3 bit (4),
2 71 2 port_mask_4_7 bit (4)) unal; /* 1 => corresponding port enabled */
2 72
2 73
2 74 dcl 1 scr_mr based (scrp) aligned, /* SC mode register */
2 75
2 76 (2 pad1 bit (50),
2 77 2 identification bit (4), /* 0000 => 8034, 8035
2 78* 0001 => 6000 SC
2 79* 0010 => 4MW SCU */
2 80 2 TS_strobe_margin bit (2), /* 00 => normal timing
2 81* 01 => slow timing
2 82* 10 => inhibit strobe
2 83* 11 => fast timing */
2 84 2 G0_strobe_margin bit (2),
2 85 2 ANSWER_strobe_margin bit (2),
2 86 2 DA_strobe_margin bit (2),
2 87 2 EOC_strobe_margin bit (2),
2 88 2 PLUS_5_VOLT_margin bit (2), /* 00 => normal voltage
2 89* 01 => -5%
2 90* 10 => normal voltage
2 91* 11 => +5% */
2 92 2 parity_override bit (1), /* 1 => SU forced to accept data with incorrect parity */
2 93 2 parity_disable bit (1), /* 1 => disable data and ZAC parity checking */
2 94 2 store_IA_disable bit (1), /* 1 => disable illegal action indication */
2 95 2 ZAC_parity_error bit (1), /* 1 => cause ZAC parity error */
2 96 2 SGR_accepted bit (1), /* 1 => SGR command accepted by SC */
2 97 2 pad2 bit (1)) unal;
2 98
2 99
2 100 dcl 1 scr_msk based (scrp) aligned, /* SC mask register */
2 101
2 102 (2 interrupt_mask_1 bit (16), /* mask bits for interrupts 0 thru 15 */
2 103 2 pad1 bit (16),
2 104 2 port_mask_1 bit (4), /* mask bits for ports 0 thru 3 */
2 105
2 106 2 interrupt_mask_2 bit (16), /* mask bits for interrupts 16 thru 31 */
2 107 2 pad2 bit (16),
2 108 2 port_mask_2 bit (4)) unal; /* mask bits for ports 4 thru 7 */
2 109
2 110
2 111 dcl 1 scr_su based (scrp) aligned, /* store unit mode register */
2 112
2 113 (2 pad1 bit (36),
2 114 2 ZAC_line bit (6), /* EDAC mode only - address field */
2 115 2 syndrome bit (8), /* EDAC mode only - failure syndrome */
2 116 2 identification bit (4), /* 0000 => High Speed Core Model AA1
2 117* 0001 => High Speed Core Model AA3
2 118* 0011 => 4K, 16 pin chip, MOS memory, M32 boards
2 119* 0100 => 1K chip MOS memory with EDAC enabled
2 120* 1010 => 64K, 16 pin chip, MOS memory, M64 boards
2 121* 1011 => 16K, 16 pin chip, MOS memory, M264 boards
2 122* 1100 => 1K chip MOS memory with EDAC disabled
2 123* 1110 => 16K, 16 pin chip, MOS memory, M128 boards
2 124* 1111 => 4K, 22 pin chip MOS memory, M16 boards */
2 125 2 EDAC_disabled bit (1), /* 1 => correction disabled but detection still enabled */
2 126 2 pad2 bit (4),
2 127 2 MINUS_5_VOLT_margin bit (2),
2 128 2 PLUS_5_VOLT_margin bit (2),
2 129 2 spare_margin bit (2),
2 130 2 PLUS_19_VOLT_margin bit (2),
2 131 2 pad3 bit (1),
2 132 2 SENSE_strobe_margin bit (2), /* core only */
2 133 2 pad4 bit (1),
2 134 2 maint_functions_enabled bit (1)) unal; /* 1 => maintenance functions enabled */
2 135
2 136 /* End of include file ...... scr.incl.pl1 */
2 137
83
84
85
86
87 cdp = addr (scs$controller_data (port)); /* Get pointer to appropriate element of array. */
88
89 call privileged_mode_ut$rscr (port, SC_MR, mr_data); /* Read the controller mode register. */
90 scrp = addr (mr_data); /* Set pointer to data read. */
91 cdata.type = scr_mr.identification; /* Extract the controller ID code. */
92
93 call privileged_mode_ut$rscr (port, SC_CFG, scs$cfg_data (port));
94 scrp = addr (scs$cfg_data (port)); /* Read configuration data from controller. */
95
96 if cdata.type >= "0010"b then do; /* If 4MW SCU ... */
97 cdata.store_a_online = scr_cfg2.a_online;
98 cdata.store_a1_online = scr_cfg2.a1_online;
99 cdata.store_b_online = scr_cfg2.b_online;
100 cdata.store_b1_online = scr_cfg2.b1_online;
101 cdata.store_b_is_lower = scr_cfg2.lwr;
102 cdata.int_interlaced = scr_cfg2.int;
103 cdata.lower_store_size = power_of_two (bin (scr_cfg2.size, 3) + 5);
104 if (cdata.store_b_is_lower & cdata.store_a_online) |
105 (^cdata.store_b_is_lower & cdata.store_b_online) then
106 if scr_cfg2.nea_enabled then /* Compute size of upper store. */
107 cdata.upper_store_size =
108 bin (bit (scr_cfg2.nea, 12)) - mod (cdata.base, 4096) - cdata.lower_store_size;
109 else
110 cdata.upper_store_size = cdata.lower_store_size;
111 else
112 cdata.upper_store_size = 0;
113 string (cdata.cyclic_priority) = scr_cfg2.cyclic_prior;
114 call interpret_eima (1, scr_cfg2.mask_a_assign);
115 call interpret_eima (2, scr_cfg2.mask_b_assign);
116 cdata.eima_data (1).mask_available,
117 cdata.eima_data (2).mask_available = "1"b;
118 cdata.eima_data (3).mask_available,
119 cdata.eima_data (4).mask_available = "0"b;
120
121 cdata.program = scr_cfg2.mode;
122 end;
123
124
125
126 else do; /* If 6000 SC ... */
127 cdata.store_a_online = (scr_cfg1.mode_a = "000"b);
128 cdata.store_b_online = (scr_cfg1.mode_b = "000"b);
129 cdata.store_b_is_lower = scr_cfg1.lwr;
130 cdata.int_interlaced = scr_cfg1.int;
131 if cdata.store_a_online then
132 store_a_size = (bin (scr_cfg1.bdry_a, 3) + 1) * 32;
133 else
134 store_a_size = 0;
135 if store_a_size = 128 then
136 cdata.store_a1_online = "1"b; /* Two ports for 128K store. */
137 else
138 cdata.store_a1_online = "0"b;
139 if cdata.store_b_online then
140 store_b_size = (bin (scr_cfg1.bdry_b, 3) + 1) * 32;
141 else
142 store_b_size = 0;
143 if store_b_size = 128 then
144 cdata.store_b1_online = "1"b; /* Two ports for 128K store. */
145 else
146 cdata.store_b1_online = "0"b;
147 if cdata.store_b_is_lower then do;
148 cdata.lower_store_size = store_b_size;
149 cdata.upper_store_size = store_a_size;
150 end;
151 else do;
152 cdata.lower_store_size = store_a_size;
153 cdata.upper_store_size = store_b_size;
154 end;
155 string (cdata.cyclic_priority) = (7)"0"b;
156 do i = 1 to 4;
157 call interpret_eima (i, scr_cfg1.pima (i));
158 cdata.eima_data (i).mask_available = "1"b;
159 end;
160
161 cdata.program = "1"b;
162 end;
163
164 return;
165
166
167
168 set_port_enable: entry (port, enable_sw); /* entry to enable a controller port */
169
170 dcl enable_sw bit (1) unal; /* 1 => enable corresponding port */
171
172
173 call set_port_enable_bit (port, enable_sw); /* Set the bit first. */
174
175 do ctag = 0 to 7; /* Set ports in all controllers. */
176 cdp = addr (scs$controller_data (ctag)); /* Get pointer to controller data for this port. */
177
178 if cdata.online then /* If controller is in use ... */
179 call enable_ports (ctag); /* Go set the port enable bits. */
180 end;
181
182 return;
183
184
185
186 set_port_enable_bit: entry (port, enable_sw); /* entry to only set port enable bits */
187
188
189 mkp = addr (scs$sys_level); /* Get pointer to array of masks. */
190
191 do i = 1 to scs$number_of_masks; /* Modify all masks. */
192 scrp = addr (masks (i)); /* Get pointer to mask. */
193 if port < 4 then /* If ports 0 thru 3 ... */
194 substr (scr_msk.port_mask_1, port + 1, 1) = enable_sw;
195 else /* If ports 4 thru 7 ... */
196 substr (scr_msk.port_mask_2, port - 3, 1) = enable_sw;
197 end;
198
199 return;
200
201
202
203 enable_ports: entry (port); /* entry to set port enable bits in a controller */
204
205
206 cdp = addr (scs$controller_data (port)); /* Get pointer to data for this controller. */
207 scrp = addr (scs$cfg_data (port)); /* Get pointer to CFG data for this controller. */
208 mkp = addr (scs$sys_level); /* Get pointer to a mask. */
209
210 if cdata.type >= "0010"b then do; /* If 4MW SCU ... */
211 scr_cfg2.port_mask_0_3 = mkp -> scr_msk.port_mask_1;
212 scr_cfg2.port_mask_4_7 = mkp -> scr_msk.port_mask_2;
213 call set_cfg (port); /* Actually set the controller. */
214 end;
215
216 else /* If 6000 SC ... */
217 if port = scs$interrupt_controller then /* If bootload controller, allow interrupts. */
218 call privileged_mode_ut$smcm (port, scs$open_level);
219 else /* If not bootload controller, prevent interrupts. */
220 call privileged_mode_ut$smcm (port, scs$sys_level);
221
222 return;
223
224
225
226 disable_ports: entry (port); /* entry to clear all port enable bits in a controller */
227
228
229 cdp = addr (scs$controller_data (port)); /* Get pointer to data for this controller. */
230 scrp = addr (scs$cfg_data (port)); /* Get pointer to CFG data for this controller. */
231
232 if cdata.type >= "0010"b then do; /* If 4MW SCU ... */
233 scr_cfg2.port_mask_0_3 = "0000"b;
234 scr_cfg2.port_mask_4_7 = "0000"b;
235 call set_cfg (port); /* Actually set the controller. */
236 end;
237
238 else /* If 6000 SC ... */
239 call privileged_mode_ut$smcm (port, unspec (bin (0, 71)));
240
241 return;
242
243
244
245 assign_mask: entry (port, target); /* entry to assign a mask to a port */
246
247 dcl target fixed bin (3); /* port to which mask will be assigned */
248
249 dcl mask_assignment bit (9); /* mask assignment bits */
250
251
252 cdp = addr (scs$controller_data (port)); /* Get pointer to correct array element. */
253 scrp = addr (scs$cfg_data (port)); /* Get pointer to correct CFG data. */
254
255 if cdata.type >= "0010"b then do i = 1 to 2; /* Do this only for 4MW SCU. */
256 if ^cdata.eima_data (i).mask_assigned then do; /* Look for unused mask. */
257 cdata.eima_data (i).mask_assignment = target;
258 cdata.eima_data (i).mask_assigned = "1"b;
259 mask_assignment = set_mask_assignment (target + 1);
260 if i = 1 then /* Set appropriate field in CFG data. */
261 scr_cfg2.mask_a_assign = mask_assignment;
262 else
263 scr_cfg2.mask_b_assign = mask_assignment;
264 end;
265 end;
266
267 return;
268
269
270
271 unassign_mask: entry (port, target); /* entry to unassign a mask from a port */
272
273
274 cdp = addr (scs$controller_data (port)); /* Get pointer to correct array element. */
275 scrp = addr (scs$cfg_data (port)); /* Get pointer to correct CFG data. */
276
277 if cdata.type >= "0010"b then do i = 1 to 2; /* Do this only for 4MW SCU. */
278 if cdata.eima_data (i).mask_assigned & /* Look for mask used for this target. */
279 (cdata.eima_data (i).mask_assignment = target) then do;
280 cdata.eima_data (i).mask_assigned = "0"b;
281 mask_assignment = set_mask_assignment (9);
282 if i = 1 then /* Set appropriate field in CFG data. */
283 scr_cfg2.mask_a_assign = mask_assignment;
284 else
285 scr_cfg2.mask_b_assign = mask_assignment;
286 end;
287 end;
288
289 return;
290
291
292
293
294 reassign_mask: entry (tag1, tag2); /* entry to reassign mask to another port */
295
296 dcl tag1 fixed bin (3), /* processor tag of assigned mask */
297 tag2 fixed bin (3); /* processor tag for new assignment */
298
299
300 ctag = scs$interrupt_controller; /* Change bootload controller only. */
301
302 if tag1 ^= -1 then do; /* If assignment to be removed ... */
303 pdp = addr (scs$processor_data (tag1)); /* Get pointer to data for this processor. */
304
305 if tag2 ^= -1 then /* Check for same-port (poss. expander) case and punt */
306 if pdata.controller_port = scs$processor_data (tag2).controller_port then return;
307 call set_mask (ctag, (pdata.controller_port), 0);
308 /* Clear the mask. */
309 call unassign_mask (ctag, (pdata.controller_port));
310 /* Unassign the mask. */
311 end;
312 if tag2 ^= -1 then do; /* If new assignment to be made ... */
313 pdp = addr (scs$processor_data (tag2)); /* Get pointer to data for this processor. */
314
315 call assign_mask (ctag, (pdata.controller_port));
316 /* Make new mask assignment. */
317 call set_cfg (ctag); /* Set switches in controller. */
318 end;
319
320 return;
321
322
323 update_export_xipmsk:
324 entry (port); /* Update port-expander XIP masks */
325
326 dcl 1 rcow based (addr (scs$reconfig_general_cow)) aligned like scs$reconfig_general_cow;
327
328 unspec (rcow) = ""b; /* Zero the cow. */
329 do i = 0 to 7;
330 pdp = addr (scs$processor_data (i)); /* Address proc data element */
331 if pdata.expanded_port & pdata.controller_port = port
332 then substr (rcow.sub_mask, pdata.expander_port + 1, 1) = pdata.interrupt_cpu;
333 end;
334 rcow.expander_command = "2"b3; /* Set XIP register */
335 rcow.controller_port = port;
336 call privileged_mode_ut$cioc (addr (rcow.cow)); /* We rely on this living in the bootload controller */
337 return;
338
339 set_export_enable:
340 entry (port, subport, enable_sw);
341
342 dcl subport fixed bin (3);
343
344 unspec (rcow) = ""b; /* Clear out sutff */
345 do i = 0 to 7; /* Scan CPU's */
346 pdp = addr (scs$processor_data (i));
347 if pdata.expanded_port & pdata.controller_port = port
348 then if pdata.expander_port = subport
349 then substr (rcow.sub_mask, pdata.expander_port + 1, 1) = enable_sw;
350 else substr (rcow.sub_mask, pdata.expander_port + 1, 1) = pdata.online;
351 end;
352 substr (rcow.sub_mask, 5, 1) = "1"b; /* T. Ohlin wants exerciser bit on. */
353 rcow.expander_command = "1"b3; /* Set subport enables */
354 rcow.controller_port = port;
355 call privileged_mode_ut$cioc (addr (rcow.cow)); /* Zap the bootload SCU */
356 /* The enables on all the other SCU's will be left enabled */
357 return;
358
359
360
361 set_cfg: entry (port); /* entry to set CFG data in controller */
362
363
364 if scs$controller_data (port).type >= "0010"b then do; /* If 4MW SCU ... */
365 if scs$set_cycle_switches then
366 string (addr (scs$cfg_data (port)) -> scr_cfg2.cyclic_prior) = scs$cycle_priority_template;
367 try_to_set_cfg:
368 scrp = addr (scs$cfg_data (port));
369 unspec (port_enable_bits) = scr_cfg2.port_mask_0_3 || scr_cfg2.port_mask_4_7;
370 set_cfg_ok = "0"b;
371 do set_cfg_try_count = 1 repeat set_cfg_try_count + 1
372 while (set_cfg_try_count <= SET_CFG_TRY_LIMIT & ^set_cfg_ok);
373 call privileged_mode_ut$sscr (port, SC_CFG, scs$cfg_data (port));
374 if unspec (port_enable_bits) = "0"b then set_cfg_ok = "1"b; /* if we can't check, assume OK */
375 else do;
376 call privileged_mode_ut$rscr (port, SC_CFG, scr_cfg2_temp); /* read to make sure it took */
377 if (unspec (scr_cfg2_temp) & SCR_CFG2_PROGRAM_MASK)
378 = (unspec (scs$cfg_data (port)) & SCR_CFG2_PROGRAM_MASK) /* check all program-settable bits*/
379 then set_cfg_ok = "1"b;
380 end;
381 end;
382
383 /* If the sscr did not take within the requisite number of tries, we
384* punt by printing instructions to the operator to clear the SCU
385* manually. This involves setting switches, flipping the mode into
386* MANUAL, then back into PROGRAM. When these two actions have happened,
387* we check again, repeating the process if necessary */
388
389 if ^set_cfg_ok then do; /* drastic manual intervention */
390 call syserr (3, "scr_util: error setting configuration register. SCU ^a must be set manually",
391 substr (LETTERS, port+1, 1));
392 call syserr (0, "Set the following switches on SCU ^a",
393 substr (LETTERS, port+1,1));
394
395 unspec (cycle_priority_bits) = scr_cfg2.cyclic_prior;
396 unspec (nea_bits) = scr_cfg2.nea;
397 mask_a_val = convert_to_mask_val (substr (scr_cfg2.mask_a_assign, 1, 8));
398 mask_b_val = convert_to_mask_val (substr (scr_cfg2.mask_b_assign, 1, 8));
399
400 call syserr (0, "^/^12x--PORT ENABLE-- --CYCLIC PRIORITY---^/^12x0 1 2 3 4 5 6 7 0/1 1/2 2/3 3/4 4/5 5/6 6/7^/^8xON ^8(^[X^; ^] ^) ^7( ^[X^; ^] ^)^/^8xOFF ^8(^[ ^;X^] ^) ^7( ^[ ^;X^] ^)",
401 port_enable_bits, cycle_priority_bits,
402 port_enable_bits, cycle_priority_bits);
403 call syserr (0, "^/^8xNON-EXISTENT ADDRESS^/^17x2 3 4 5 6 7 8^/^8xON ^[X^; ^] 1 ^7(^[X^; ^] ^)^/^8xOFF ^[ ^;X^] 0 ^7(^[ ^;X^] ^)",
404 scr_cfg2.nea_enabled, nea_bits,
405 scr_cfg2.nea_enabled, nea_bits);
406 call syserr (0, "^/^8xSTORE A A1 B B1^/^8xON ^4(^[X^; ^] ^)^/^8xOFF ^4(^[ ^;X^] ^)",
407 scr_cfg2.a_online, scr_cfg2.a1_online, scr_cfg2.b_online, scr_cfg2.b1_online,
408 scr_cfg2.a_online, scr_cfg2.a1_online, scr_cfg2.b_online, scr_cfg2.b1_online);
409 call syserr (0, "^/^8xLWR STORE SIZE - ^d^/^8xINTERLACE - ^[ON^;OFF^]^/^8xLWR STORE - ^[B^;A^]^/^8xMASK A - ^a^/^8xMASK B - ^a",
410 bin (scr_cfg2.size), scr_cfg2.int, scr_cfg2.lwr,
411 mask_a_val, mask_b_val);
412
413 call syserr (0, "After setting the switches for SCU ^a place SCU ^a into Manual Mode and then into Program Mode",
414 substr (LETTERS, port+1, 1), substr (LETTERS, port+1, 1));
415
416 /* Wait for SCU to go into Manual Mode */
417
418 do while (addr (scr_cfg2_temp) -> scr_cfg2.mode);
419 call privileged_mode_ut$rscr (port, SC_CFG, scr_cfg2_temp);
420 end;
421
422 /* Wait for SCU to go into Program Mode */
423
424 do while (^addr (scr_cfg2_temp) -> scr_cfg2.mode);
425 call privileged_mode_ut$rscr (port, SC_CFG, scr_cfg2_temp);
426 end;
427
428
429 /* Check whether SCU cleared properly */
430
431 if (unspec (scr_cfg2_temp) & SCR_CFG2_PROGRAM_MASK)
432 ^= (unspec (scs$cfg_data (port)) & SCR_CFG2_PROGRAM_MASK)
433 then goto try_to_set_cfg;
434 end;
435
436
437
438
439
440 end;
441 /* Set CFG data in controller. */
442 return;
443
444
445
446 set_mask: entry (port, target, mask); /* entry to set mask for controller port */
447
448 dcl mask fixed bin (71); /* mask to be set */
449
450
451 call privileged_mode_ut$sscr (port, SC_MSK + 8 * target, mask);
452 /* Set the mask. */
453
454 return;
455
456
457
458
459 convert_to_mask_val:
460 proc (scu_mask_bits) returns (char (*)); /* procedure to convert a mask to printable form */
461
462 dcl scu_mask_bits bit (*) unaligned,
463 mask_val pic "9";
464
465
466 if index (scu_mask_bits, "1"b) >0 then do;
467 mask_val = index (scu_mask_bits, "1"b) - 1;
468 return (mask_val);
469 end;
470 else return ("Off");
471
472
473 end convert_to_mask_val;
474
475
476
477
478
479 interpret_eima: proc (n, eima); /* procedure to determine port assignment from bits */
480
481 dcl n fixed bin, /* EIMA number */
482 eima bit (9); /* mask assignment bits */
483
484 dcl x fixed bin; /* port mask assigned to */
485
486
487 x = index (eima, "1"b); /* Look for bit ON. */
488 if (x = 0) | (x = 9) then /* If no bits ON, or last bit ON ... */
489 cdata.eima_data (n).mask_assigned = "0"b; /* Mask is not assigned to any port. */
490 else do; /* Mask is assigned. */
491 cdata.eima_data (n).mask_assigned = "1"b;
492 cdata.eima_data (n).mask_assignment = x - 1; /* Remember port to which mask is assigned. */
493 end;
494
495 return;
496
497 end interpret_eima;
498
499
500
501 set_mask_assignment: proc (n) returns (bit (9) unal); /* procedure to set correct mask assignment bit */
502
503 dcl n fixed bin; /* bit to be set */
504
505 dcl m bit (9) aligned; /* prototype mask assignment bits */
506
507
508 m = "0"b; /* Clear all bits. */
509 substr (m, n, 1) = "1"b; /* Set the desired bit. */
510
511 return (m); /* Return assignment bits. */
512
513
514 end set_mask_assignment;
515
516
517
518
519 power_of_two: proc (e) returns (fixed bin); /* procedure to compute power of two */
520
521 dcl e fixed bin; /* exponent */
522
523 dcl p fixed bin; /* power of two */
524
525
526 p = 0; /* Clear the result. */
527 substr (unspec (p), 36 - e, 1) = "1"b; /* Very quick, and extremely dirty. */
528
529 return (p);
530
531
532 end power_of_two;
533
534 /* */
535
536 /* isolts_scu_p1 - entry to set config data in the SCU being used for ISOLTS, to isolate the processor under test */
537
538 isolts_scu_p1: entry;
539
540 iscu = scs$processor_test_data.scu_tag; /* pick up scu_tag, cpu_tag, and mask cpu tag */
541 icpu = scs$processor_test_data.cpu_tag; /* from processor test data structure */
542 mcpu = scs$processor_test_data.mask_cpu;
543 cdp = addr (scs$controller_data (iscu));
544 scrp = addr (scs$cfg_data (iscu));
545 pdp = addr (scs$processor_data (icpu));
546 mkp = addr (scs$cpu_test_mask);
547
548 /* do the things common to both types of SCU's first */
549
550 maska = set_mask_assignment (scs$processor_data (mcpu).controller_port + 1);
551 maskb = set_mask_assignment (pdata.controller_port + 1);
552
553 /* set up scs$cpu_test mask */
554
555 scs$cpu_test_mask = "0"b; /* initialize it first */
556 mkp -> scr_msk.port_mask_1 = substr ((maska | maskb), 1, 4); /* set port mask fields */
557 mkp -> scr_msk.port_mask_2 = substr ((maska | maskb), 5, 4);
558
559 if cdata.type >= "0010"b then do; /* if 4MW SCU ... */
560
561 scr_cfg2.mask_a_assign = maska; /* set up config data */
562 scr_cfg2.mask_b_assign = maskb;
563 scr_cfg2.port_mask_0_3 = mkp -> scr_msk.port_mask_1;
564 scr_cfg2.port_mask_4_7 = mkp -> scr_msk.port_mask_2;
565
566 call set_cfg ((iscu)); /* actually set config data in SCU */
567
568 end;
569
570 else call privileged_mode_ut$smcm ((iscu), scs$cpu_test_mask); /* 6000 SCU, just set port mask */
571 call set_mask ((iscu), (scs$processor_data (mcpu).controller_port), /* mask off interrupts */
572 fixed (scs$cpu_test_mask, 71)); /* in mask cpu */
573 mkp -> scr_msk.interrupt_mask_1 = "1001000000001000"b; /* set int mask for cells 0 and 12 */
574 /* and cell 3 for test progras */
575 scs$processor_test_data.scu_state = "10"b; /* set scu state to indicate where we are at */
576
577 return; /* thats all folks */
578
579 /* */
580
581 /* isolts_scu_p2 - entry to re-enable original SCU ports + port for test cpu */
582
583 isolts_scu_p2: entry;
584
585 iscu = scs$processor_test_data.scu_tag; /* pick up scu_tag, cpu_tag, and mask cpu tag */
586 icpu = scs$processor_test_data.cpu_tag; /* from processor test data structure */
587 mcpu = scs$processor_test_data.mask_cpu;
588 cdp = addr (scs$controller_data (iscu));
589 scrp = addr (scs$cfg_data (iscu));
590 pdp = addr (scs$processor_data (icpu));
591 mkp = addr (scs$cpu_test_mask);
592
593 /* do the things common to both types of SCU's first */
594
595 maska = set_mask_assignment (pdata.controller_port + 1);
596 pdp = addr (scs$sys_level); /* get a pointer to a mask */
597 mkp -> scr_msk.port_mask_1 = pdp -> scr_msk.port_mask_1 | substr (maska, 1, 4);
598 mkp -> scr_msk.port_mask_2 = pdp -> scr_msk.port_mask_2 | substr (maska, 5, 4);
599
600 if cdata.type >= "0010"b then do; /* if 4MW SCU ... */
601
602 scr_cfg2.port_mask_0_3 = mkp -> scr_msk.port_mask_1;
603 scr_cfg2.port_mask_4_7 = mkp -> scr_msk.port_mask_2;
604
605 call set_cfg ((iscu)); /* actually set config data in SCU */
606
607 end;
608
609 else call privileged_mode_ut$smcm ((iscu),
610 "000000000017000000000017"b3 & scs$cpu_test_mask); /* 6000 SCU, set port mask */
611 call set_mask ((iscu), (scs$processor_data (mcpu).controller_port), /* mask off interrupts */
612 fixed ("000000000017000000000017"b3 & scs$cpu_test_mask, 71)); /* in mask cpu */
613
614 return; /* thats all folks */
615
616
617 /* */
618
619 /* isolts_scu_p3 - entry to restore orignial SCU port masks upon termination of ISOLTS CPU testing */
620
621 isolts_scu_p3: entry;
622
623 iscu = scs$processor_test_data.scu_tag; /* pick up scu_tag */
624 cdp = addr (scs$controller_data (iscu));
625
626 scs$cfg_data (iscu) = scs$cfg_data_save; /* restoe orignial config data */
627
628 if cdata.type >= "0010"b then /* if 4MW SCU */
629 call set_cfg ((iscu)); /* actually set config data */
630 else call privileged_mode_ut$smcm ((iscu), scs$sys_level); /* if 6000 SC */
631
632 return; /* thats all */
633
634
635 /* BEGIN MESSAGE DOCUMENTATION
636*
637* Message:
638* scr_util: error setting configuration register. SCU X must be set manually.
639* Set the following switches on SCU X
640* < Diagram of SCU Maintenance Panel is Printed Here>
641* After setting the switches for SCU X place SCU S into Manual Mode and then into Program Mode
642*
643* S: $beep
644*
645* T: Reconfiguration (e.g., adding or deleting a CPU)
646*
647* M: The supervisor was unable to set the configuration register in the SCU
648* indicated after 10 attempts. To avoid a system crash, the SCU must be
649* cleared manually. In this message, the supervisor will print a diagram
650* of the SCU Maintenance Panel, indicating how each switch should be set.
651*
652* A: The operator should copy the diagram of the SCU Maintenance Panel
653* printed by the supervisor (or take the copy printed, if possible). The
654* operator should then go to the Maintenance Panel of the SCU indicated
655* and set each switch on the diagram to the indicated position, and then
656* verify that each switch is in the correct position. Following this, the
657* operator should set the Program/Manual switch into the Manual position
658* briefly, and then return it to the Program position. If this procedure
659* does not remedy the problem, the message will be repeated, and the
660* System Programming Staff should be contacted.
661*
662* END MESSAGE DOCUMENTATION */
663
664 end scr_util$read_cfg;
SOURCE FILES USED IN THIS COMPILATION.
LINE NUMBER DATE MODIFIED NAME PATHNAME
0 11/11/89 0853.8 scr_util.pl1 >spec>install>1115>scr_util.pl1
80 1 10/12/83 0943.5 scs.incl.pl1 >ldd>include>scs.incl.pl1
83 2 08/17/83 1135.7 scr.incl.pl1 >ldd>include>scr.incl.pl1
NAMES DECLARED IN THIS COMPILATION.
IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES
(* indicates a set context)