forked from castano/icbc
-
Notifications
You must be signed in to change notification settings - Fork 0
/
icbc.h
3929 lines (3156 loc) · 123 KB
/
icbc.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// icbc.h v1.05
// A High Quality SIMD BC1 Encoder by Ignacio Castano <castano@gmail.com>.
//
// LICENSE:
// MIT license at the end of this file.
#ifndef ICBC_H
#define ICBC_H
namespace icbc {
enum Decoder {
Decoder_D3D10 = 0,
Decoder_NVIDIA = 1,
Decoder_AMD = 2, // Apple's M1 decoder appears to match AMD's
Decoder_Intel = 3
};
void init(Decoder decoder = Decoder_D3D10);
enum Quality {
Quality_Level0, // Box fit only.
Quality_Level1, // Box fit + least squares fit.
Quality_Level2, // Cluster fit 4, threshold = 24.
Quality_Level3, // Cluster fit 4, threshold = 32.
Quality_Level4, // Cluster fit 4, threshold = 48.
Quality_Level5, // Cluster fit 4, threshold = 64.
Quality_Level6, // Cluster fit 4, threshold = 96.
Quality_Level7, // Cluster fit 4, threshold = 128.
Quality_Level8, // Cluster fit 4+3, threshold = 256.
Quality_Level9, // Cluster fit 4+3, threshold = 256 + Refinement.
Quality_Fast = Quality_Level1,
Quality_Default = Quality_Level8,
Quality_Max = Quality_Level9,
};
void decode_bc1(const void * block, unsigned char rgba_block[16 * 4], Decoder decoder = Decoder_D3D10);
void decode_bc3(const void * block, unsigned char rgba_block[16 * 4], Decoder decoder = Decoder_D3D10);
//void decode_bc4(const void * block, bool snorm, unsigned char rgba_block[16 * 4], Decoder decoder = Decoder_D3D10);
//void decode_bc5(const void * block, bool snorm, unsigned char rgba_block[16 * 4], Decoder decoder = Decoder_D3D10);
float evaluate_bc1_error(const unsigned char rgba_block[16 * 4], const void * block, Decoder decoder = Decoder_D3D10);
float evaluate_bc3_error(const unsigned char rgba_block[16 * 4], const void * block, bool alpha_blend, Decoder decoder = Decoder_D3D10);
//float evaluate_bc4_error(const float rgba_block[16 * 4], const void * block, bool snorm, Decoder decoder = Decoder_D3D10);
//float evaluate_bc5_error(const float rgba_block[16 * 4], const void * block, bool snorm, Decoder decoder = Decoder_D3D10);
float compress_bc1(Quality level, const float * input_colors, bool three_color_mode, bool three_color_black, void * output);
float compress_bc3(Quality level, const float * input_colors, const float * input_weights, const float color_weights[3], bool six_alpha_mode, void * output);
//float compress_bc4(Quality level, const float * input_colors, const float * input_weights, bool snorm, bool six_alpha_mode, void * output);
//float compress_bc5(Quality level, const float * input_colors, const float * input_weights, bool snorm, bool six_alpha_mode, void * output);
}
#endif // ICBC_H
#ifdef ICBC_IMPLEMENTATION
// Instruction level support must be chosen at compile time setting ICBC_SIMD to one of these values:
#define ICBC_SCALAR 0
#define ICBC_SSE2 1
#define ICBC_SSE41 2
#define ICBC_AVX1 3
#define ICBC_AVX2 4
#define ICBC_AVX512 5
#define ICBC_NEON -1
#define ICBC_VMX -2
#if defined(__i386__) || defined(_M_IX86) || defined(__x86_64__) || defined(_M_X64)
#define ICBC_X86 1
#endif
#if defined(__x86_64__) || defined(_M_X64)
#define ICBC_X64 1
#endif
#if defined(__arm__) || defined(_M_ARM) || defined(__aarch64__) || defined(_M_ARM64)
#define ICBC_ARM 1
#endif
#if defined(__aarch64__) || defined(_M_ARM64)
#define ICBC_ARM64 1
#endif
#if (defined(__PPC__) || defined(_M_PPC))
#define ICBC_PPC 1
#endif
// SIMD version.
#ifndef ICBC_SIMD
#if ICBC_X86
#if __AVX512F__
#define ICBC_SIMD ICBC_AVX512
#elif __AVX2__
#define ICBC_SIMD ICBC_AVX2
#elif __AVX__
#define ICBC_SIMD ICBC_AVX1
#elif __SSE4_1__
#define ICBC_SIMD ICBC_SSE41
#elif __SSE2__ || ICBC_X64
#define ICBC_SIMD ICBC_SSE2
#else
#define ICBC_SIMD ICBC_SCALAR
#endif
#endif
#if ICBC_ARM
#if __ARM_NEON__
#define ICBC_SIMD ICBC_NEON
#else
#define ICBC_SIMD ICBC_SCALAR
#endif
#endif
#if ICBC_PPC
#define ICBC_SIMD ICBC_VMX
#endif
#endif
// AVX1 does not require FMA, and depending on whether it's Intel or AMD you may have FMA3 or FMA4. What a mess.
#ifndef ICBC_USE_FMA
//#define ICBC_USE_FMA 3
//#define ICBC_USE_FMA 4
#endif
#if ICBC_SIMD >= ICBC_AVX2
#define ICBC_BMI2 1
#endif
// Apparently rcp is not deterministic (different precision on Intel and AMD), enable if you don't care about that for a small performance boost.
//#define ICBC_USE_RCP 1
#if ICBC_SIMD == ICBC_AVX2
#define ICBC_USE_AVX2_PERMUTE2 1 // Using permutevar8x32 and bitops.
#endif
#if ICBC_SIMD == ICBC_AVX512
#define ICBC_USE_AVX512_PERMUTE 1
#endif
#if ICBC_SIMD == ICBC_NEON
#define ICBC_USE_NEON_VTL 1 // Enable this for a 0.89x performance improvement.
#endif
#if ICBC_SIMD == ICBC_SSE41
#define ICBC_USE_SSSE3_SHUFFLEB 1 // Enable this for 0.88x performance improvement.
#endif
// Some experimental knobs:
#define ICBC_PERFECT_ROUND 0 // Enable perfect rounding to compute cluster fit residual.
#if ICBC_SIMD >= ICBC_SSE2
#include <emmintrin.h>
#endif
#if ICBC_SIMD >= ICBC_SSE41
#include <smmintrin.h>
#endif
#if ICBC_SIMD >= ICBC_AVX1
#include <immintrin.h>
#endif
#if ICBC_SIMD >= ICBC_AVX512 && _MSC_VER
#include <zmmintrin.h>
#endif
#if ICBC_SIMD == ICBC_NEON
#include <arm_neon.h>
#endif
#if ICBC_SIMD == ICBC_VMX
#include <altivec.h>
#endif
#if _MSC_VER
#include <intrin.h> // _BitScanReverse
#endif
#include <stdint.h>
#include <stdlib.h> // abs
#include <string.h> // memset
#include <math.h> // fabsf
#include <float.h> // FLT_MAX
#ifndef ICBC_ASSERT
#if _DEBUG
#define ICBC_ASSERT assert
#include <assert.h>
#else
#define ICBC_ASSERT(x)
#endif
#endif
namespace icbc {
///////////////////////////////////////////////////////////////////////////////////////////////////
// Basic Templates
template <typename T> inline void swap(T & a, T & b) {
T temp(a);
a = b;
b = temp;
}
template <typename T> inline T max(const T & a, const T & b) {
return (b < a) ? a : b;
}
template <typename T> inline T min(const T & a, const T & b) {
return (a < b) ? a : b;
}
template <typename T> inline T clamp(const T & x, const T & a, const T & b) {
return min(max(x, a), b);
}
template <typename T> inline T square(const T & a) {
return a * a;
}
///////////////////////////////////////////////////////////////////////////////////////////////////
// Basic Types
typedef uint8_t uint8;
typedef int8_t int8;
typedef uint16_t uint16;
typedef uint32_t uint32;
typedef uint32_t uint;
struct Color16 {
union {
struct {
uint16 b : 5;
uint16 g : 6;
uint16 r : 5;
};
uint16 u;
};
};
struct Color32 {
union {
struct {
uint8 b, g, r, a;
};
uint32 u;
};
};
struct BlockBC1 {
Color16 col0;
Color16 col1;
uint32 indices;
};
struct BlockBC4 {
uint8 alpha0;
uint8 alpha1;
uint8 indices[6];
};
struct BlockBC3 {
BlockBC4 alpha;
BlockBC1 rgb;
};
struct BlockBC5 {
BlockBC4 x;
BlockBC1 y;
};
struct Vector3 {
float x;
float y;
float z;
inline void operator+=(Vector3 v) {
x += v.x; y += v.y; z += v.z;
}
inline void operator*=(Vector3 v) {
x *= v.x; y *= v.y; z *= v.z;
}
inline void operator*=(float s) {
x *= s; y *= s; z *= s;
}
};
struct Vector4 {
union {
struct {
float x, y, z, w;
};
Vector3 xyz;
};
};
inline Vector3 operator*(Vector3 v, float s) {
return { v.x * s, v.y * s, v.z * s };
}
inline Vector3 operator*(float s, Vector3 v) {
return { v.x * s, v.y * s, v.z * s };
}
inline Vector3 operator*(Vector3 a, Vector3 b) {
return { a.x * b.x, a.y * b.y, a.z * b.z };
}
inline float dot(Vector3 a, Vector3 b) {
return a.x * b.x + a.y * b.y + a.z * b.z;
}
inline Vector3 operator+(Vector3 a, Vector3 b) {
return { a.x + b.x, a.y + b.y, a.z + b.z };
}
inline Vector3 operator-(Vector3 a, Vector3 b) {
return { a.x - b.x, a.y - b.y, a.z - b.z };
}
inline Vector3 operator/(Vector3 v, float s) {
return { v.x / s, v.y / s, v.z / s };
}
inline float saturate(float x) {
return clamp(x, 0.0f, 1.0f);
}
inline Vector3 saturate(Vector3 v) {
return { saturate(v.x), saturate(v.y), saturate(v.z) };
}
inline Vector3 min(Vector3 a, Vector3 b) {
return { min(a.x, b.x), min(a.y, b.y), min(a.z, b.z) };
}
inline Vector3 max(Vector3 a, Vector3 b) {
return { max(a.x, b.x), max(a.y, b.y), max(a.z, b.z) };
}
inline bool operator==(const Vector3 & a, const Vector3 & b) {
return a.x == b.x && a.y == b.y && a.z == b.z;
}
inline Vector3 scalar_to_vector3(float f) {
return {f, f, f};
}
inline float lengthSquared(Vector3 v) {
return dot(v, v);
}
inline bool equal(float a, float b, float epsilon = 0.0001) {
// http://realtimecollisiondetection.net/blog/?p=89
//return fabsf(a - b) < epsilon * max(1.0f, max(fabsf(a), fabsf(b)));
return fabsf(a - b) < epsilon;
}
inline bool equal(Vector3 a, Vector3 b, float epsilon) {
return equal(a.x, b.x, epsilon) && equal(a.y, b.y, epsilon) && equal(a.z, b.z, epsilon);
}
///////////////////////////////////////////////////////////////////////////////////////////////////
// SIMD
#ifndef ICBC_ALIGN
#if __GNUC__
# define ICBC_ALIGN __attribute__ ((__aligned__ (icbc::VEC_SIZE*4)))
#else // _MSC_VER
# define ICBC_ALIGN __declspec(align(icbc::VEC_SIZE*4))
#endif
#endif
#if __GNUC__
#define ICBC_FORCEINLINE inline __attribute__((always_inline))
#else
#define ICBC_FORCEINLINE __forceinline
#endif
// Count trailing zeros (BSR).
ICBC_FORCEINLINE int ctz(uint mask) {
#if __GNUC__
return __builtin_ctz(mask);
#else
unsigned long index;
_BitScanReverse(&index, mask);
return (int)index;
#endif
}
#if ICBC_SIMD == ICBC_SCALAR // Purely scalar version.
constexpr int VEC_SIZE = 1;
using VFloat = float;
using VMask = bool;
ICBC_FORCEINLINE float & lane(VFloat & v, int i) { return v; }
ICBC_FORCEINLINE VFloat vzero() { return 0.0f; }
ICBC_FORCEINLINE VFloat vbroadcast(float x) { return x; }
ICBC_FORCEINLINE VFloat vload(const float * ptr) { return *ptr; }
ICBC_FORCEINLINE VFloat vrcp(VFloat a) { return 1.0f / a; }
ICBC_FORCEINLINE VFloat vmadd(VFloat a, VFloat b, VFloat c) { return a * b + c; }
ICBC_FORCEINLINE VFloat vmsub(VFloat a, VFloat b, VFloat c) { return a * b - c; }
ICBC_FORCEINLINE VFloat vm2sub(VFloat a, VFloat b, VFloat c, VFloat d) { return a * b - c * d; }
ICBC_FORCEINLINE VFloat vsaturate(VFloat a) { return min(max(a, 0.0f), 1.0f); }
ICBC_FORCEINLINE VFloat vround01(VFloat a) { return float(int(a + 0.5f)); }
ICBC_FORCEINLINE VFloat lane_id() { return 0; }
ICBC_FORCEINLINE VFloat vselect(VMask mask, VFloat a, VFloat b) { return mask ? b : a; }
ICBC_FORCEINLINE VMask vbroadcast(bool b) { return b; }
ICBC_FORCEINLINE bool all(VMask m) { return m; }
ICBC_FORCEINLINE bool any(VMask m) { return m; }
ICBC_FORCEINLINE uint mask(VMask m) { return (uint)m; }
ICBC_FORCEINLINE int reduce_min_index(VFloat v) { return 0; }
ICBC_FORCEINLINE void vtranspose4(VFloat & a, VFloat & b, VFloat & c, VFloat & d) {}
#elif ICBC_SIMD == ICBC_SSE2 || ICBC_SIMD == ICBC_SSE41
constexpr int VEC_SIZE = 4;
#if __GNUC__
// GCC needs a struct so that we can overload operators.
union VFloat {
__m128 v;
float m128_f32[VEC_SIZE];
VFloat() {}
VFloat(__m128 v) : v(v) {}
operator __m128 & () { return v; }
};
union VMask {
__m128 m;
VMask() {}
VMask(__m128 m) : m(m) {}
operator __m128 & () { return m; }
};
#else
using VFloat = __m128;
using VMask = __m128;
#endif
ICBC_FORCEINLINE float & lane(VFloat & v, int i) {
return v.m128_f32[i];
}
ICBC_FORCEINLINE VFloat vzero() {
return _mm_setzero_ps();
}
ICBC_FORCEINLINE VFloat vbroadcast(float x) {
return _mm_set1_ps(x);
}
ICBC_FORCEINLINE VFloat vload(const float * ptr) {
return _mm_load_ps(ptr);
}
ICBC_FORCEINLINE VFloat vgather(const float * base, VFloat index) {
VFloat v;
for (int i = 0; i < VEC_SIZE; i++) {
lane(v, i) = base[int(lane(index, i))];
}
return v;
}
ICBC_FORCEINLINE VFloat operator+(VFloat a, VFloat b) {
return _mm_add_ps(a, b);
}
ICBC_FORCEINLINE VFloat operator-(VFloat a, VFloat b) {
return _mm_sub_ps(a, b);
}
ICBC_FORCEINLINE VFloat operator*(VFloat a, VFloat b) {
return _mm_mul_ps(a, b);
}
ICBC_FORCEINLINE VFloat vrcp(VFloat a) {
#if ICBC_USE_RCP
VFloat r = _mm_rcp_ps(a);
return _mm_mul_ps(r, _mm_sub_ps(vbroadcast(2.0f), _mm_mul_ps(r, a))); // r * (2 - r * a)
#else
return _mm_div_ps(vbroadcast(1.0f), a);
#endif
}
// a*b+c
ICBC_FORCEINLINE VFloat vmadd(VFloat a, VFloat b, VFloat c) {
return a * b + c;
}
ICBC_FORCEINLINE VFloat vmsub(VFloat a, VFloat b, VFloat c) {
return a * b - c;
}
ICBC_FORCEINLINE VFloat vm2sub(VFloat a, VFloat b, VFloat c, VFloat d) {
return a * b - c * d;
}
ICBC_FORCEINLINE VFloat vsaturate(VFloat a) {
auto zero = _mm_setzero_ps();
auto one = _mm_set1_ps(1.0f);
return _mm_min_ps(_mm_max_ps(a, zero), one);
}
// Assumes a is in [0, 1] range.
ICBC_FORCEINLINE VFloat vround01(VFloat a) {
#if ICBC_SIMD == ICBC_SSE41
return _mm_round_ps(a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
#else
return _mm_cvtepi32_ps(_mm_cvttps_epi32(a + vbroadcast(0.5f)));
#endif
}
ICBC_FORCEINLINE VFloat vtruncate(VFloat a) {
#if ICBC_SIMD == ICBC_SSE41
return _mm_round_ps(a, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
#else
return _mm_cvtepi32_ps(_mm_cvttps_epi32(a));
#endif
}
ICBC_FORCEINLINE VFloat lane_id() {
return _mm_set_ps(3, 2, 1, 0);
}
ICBC_FORCEINLINE VMask operator> (VFloat A, VFloat B) { return _mm_cmpgt_ps(A, B); }
ICBC_FORCEINLINE VMask operator>=(VFloat A, VFloat B) { return _mm_cmpge_ps(A, B); }
ICBC_FORCEINLINE VMask operator< (VFloat A, VFloat B) { return _mm_cmplt_ps(A, B); }
ICBC_FORCEINLINE VMask operator<=(VFloat A, VFloat B) { return _mm_cmple_ps(A, B); }
ICBC_FORCEINLINE VMask operator| (VMask A, VMask B) { return _mm_or_ps(A, B); }
ICBC_FORCEINLINE VMask operator& (VMask A, VMask B) { return _mm_and_ps(A, B); }
ICBC_FORCEINLINE VMask operator^ (VMask A, VMask B) { return _mm_xor_ps(A, B); }
// mask ? b : a
ICBC_FORCEINLINE VFloat vselect(VMask mask, VFloat a, VFloat b) {
#if ICBC_SIMD == ICBC_SSE41
return _mm_blendv_ps(a, b, mask);
#else
return _mm_or_ps(_mm_andnot_ps(mask, a), _mm_and_ps(mask, b));
#endif
}
ICBC_FORCEINLINE VMask vbroadcast(bool b) {
return _mm_castsi128_ps(_mm_set1_epi32(-int32_t(b)));
}
ICBC_FORCEINLINE bool all(VMask m) {
int value = _mm_movemask_ps(m);
return value == 0x7;
}
ICBC_FORCEINLINE bool any(VMask m) {
int value = _mm_movemask_ps(m);
return value != 0;
}
ICBC_FORCEINLINE uint mask(VMask m) {
return (uint)_mm_movemask_ps(m);
}
ICBC_FORCEINLINE int reduce_min_index(VFloat v) {
// First do an horizontal reduction. // v = [ D C | B A ]
VFloat shuf = _mm_shuffle_ps(v, v, _MM_SHUFFLE(2, 3, 0, 1)); // [ C D | A B ]
VFloat mins = _mm_min_ps(v, shuf); // mins = [ D+C C+D | B+A A+B ]
shuf = _mm_movehl_ps(shuf, mins); // [ C D | D+C C+D ] // let the compiler avoid a mov by reusing shuf
mins = _mm_min_ss(mins, shuf);
mins = _mm_shuffle_ps(mins, mins, _MM_SHUFFLE(0, 0, 0, 0));
// Then find the index.
uint mask = _mm_movemask_ps(v <= mins);
return ctz(mask);
}
// https://gcc.gnu.org/legacy-ml/gcc-patches/2005-10/msg00324.html
ICBC_FORCEINLINE void vtranspose4(VFloat & r0, VFloat & r1, VFloat & r2, VFloat & r3) {
VFloat t0 = _mm_unpacklo_ps(r0, r1);
VFloat t1 = _mm_unpacklo_ps(r2, r3);
VFloat t2 = _mm_unpackhi_ps(r0, r1);
VFloat t3 = _mm_unpackhi_ps(r2, r3);
r0 = _mm_movelh_ps(t0, t1);
r1 = _mm_movehl_ps(t1, t0);
r2 = _mm_movelh_ps(t2, t3);
r3 = _mm_movehl_ps(t3, t2);
}
#if ICBC_SIMD == ICBC_SSE41
ICBC_FORCEINLINE VFloat vpermute2(VFloat tab0, VFloat tab1, __m128i idx) {
// @@ Precompute this:
tab1 = _mm_xor_ps(tab1, tab0);
__m128i result = _mm_shuffle_epi8(_mm_castps_si128(tab0), idx);
idx = _mm_sub_epi8(idx, _mm_set1_epi8(16));
result = _mm_xor_si128(result, _mm_shuffle_epi8(_mm_castps_si128(tab1), idx));
return _mm_castsi128_ps(result);
}
ICBC_FORCEINLINE VFloat vpermute4(VFloat tab0, VFloat tab1, VFloat tab2, VFloat tab3, __m128i idx) {
// @@ Precompute this:
tab3 = _mm_xor_ps(tab3, tab2);
tab2 = _mm_xor_ps(tab2, tab1);
tab1 = _mm_xor_ps(tab1, tab0);
__m128i result = _mm_shuffle_epi8(_mm_castps_si128(tab0), idx);
idx = _mm_sub_epi8(idx, _mm_set1_epi8(16));
result = _mm_xor_si128(result, _mm_shuffle_epi8(_mm_castps_si128(tab1), idx));
idx = _mm_sub_epi8(idx, _mm_set1_epi8(16));
result = _mm_xor_si128(result, _mm_shuffle_epi8(_mm_castps_si128(tab2), idx));
idx = _mm_sub_epi8(idx, _mm_set1_epi8(16));
result = _mm_xor_si128(result, _mm_shuffle_epi8(_mm_castps_si128(tab3), idx));
return _mm_castsi128_ps(result);
}
#endif
#elif ICBC_SIMD == ICBC_AVX1 || ICBC_SIMD == ICBC_AVX2
constexpr int VEC_SIZE = 8;
#if __GNUC__
union VFloat {
__m256 v;
float m256_f32[VEC_SIZE];
VFloat() {}
VFloat(__m256 v) : v(v) {}
operator __m256 & () { return v; }
};
union VInt {
__m256i v;
int m256_i32[VEC_SIZE];
VInt() {}
VInt(__m256i v) : v(v) {}
operator __m256i & () { return v; }
};
union VMask {
__m256 m;
VMask() {}
VMask(__m256 m) : m(m) {}
operator __m256 & () { return m; }
};
#else
using VFloat = __m256;
using VInt = __m256i;
using VMask = __m256; // Emulate mask vector using packed float.
#endif
ICBC_FORCEINLINE float & lane(VFloat & v, int i) {
return v.m256_f32[i];
}
ICBC_FORCEINLINE VFloat vzero() {
return _mm256_setzero_ps();
}
ICBC_FORCEINLINE VFloat vbroadcast(float a) {
return _mm256_set1_ps(a);
}
ICBC_FORCEINLINE VFloat vload(const float * ptr) {
return _mm256_load_ps(ptr);
}
ICBC_FORCEINLINE VFloat vgather(const float * base, VFloat index) {
#if ICBC_SIMD == ICBC_AVX2
return _mm256_i32gather_ps(base, _mm256_cvtps_epi32(index), 4);
#else
VFloat v;
for (int i = 0; i < VEC_SIZE; i++) {
lane(v, i) = base[int(lane(index, i))];
}
return v;
#endif
}
ICBC_FORCEINLINE VFloat operator+(VFloat a, VFloat b) {
return _mm256_add_ps(a, b);
}
ICBC_FORCEINLINE VFloat operator-(VFloat a, VFloat b) {
return _mm256_sub_ps(a, b);
}
ICBC_FORCEINLINE VFloat operator*(VFloat a, VFloat b) {
return _mm256_mul_ps(a, b);
}
ICBC_FORCEINLINE VFloat vrcp(VFloat a) {
#if ICBC_USE_RCP
#if ICBC_SIMD == ICBC_AVX512
VFloat r = _mm256_rcp14_ps(a);
#else
VFloat r = _mm256_rcp_ps(a);
#endif
// r = r * (2 - r * a)
#if ICBC_USE_FMA == 3 || ICBC_AVX2
return _mm256_mul_ps(r, _mm256_fnmadd_ps(r, a, vbroadcast(2.0f)));
#else
return _mm256_mul_ps(r, _mm256_sub_ps(vbroadcast(2.0f), _mm256_mul_ps(r, a)));
#endif
#else
return _mm256_div_ps(vbroadcast(1.0f), a);
#endif
}
// a*b+c
ICBC_FORCEINLINE VFloat vmadd(VFloat a, VFloat b, VFloat c) {
#if ICBC_USE_FMA == 3 || ICBC_SIMD == ICBC_AVX2
return _mm256_fmadd_ps(a, b, c);
#elif ICBC_USE_FMA == 4
return _mm256_macc_ps(a, b, c);
#else
return ((a * b) + c);
#endif
}
ICBC_FORCEINLINE VFloat vmsub(VFloat a, VFloat b, VFloat c) {
#if ICBC_USE_FMA == 3 || ICBC_SIMD == ICBC_AVX2
return _mm256_fmsub_ps(a, b, c);
#elif ICBC_USE_FMA == 4
return _mm256_msub_ps(a, b, c);
#else
return ((a * b) - c);
#endif
}
ICBC_FORCEINLINE VFloat vm2sub(VFloat a, VFloat b, VFloat c, VFloat d) {
return vmsub(a, b, c * d);
}
ICBC_FORCEINLINE VFloat vsaturate(VFloat a) {
__m256 zero = _mm256_setzero_ps();
__m256 one = _mm256_set1_ps(1.0f);
return _mm256_min_ps(_mm256_max_ps(a, zero), one);
}
ICBC_FORCEINLINE VFloat vround01(VFloat a) {
return _mm256_round_ps(a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
}
ICBC_FORCEINLINE VFloat vtruncate(VFloat a) {
return _mm256_round_ps(a, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
}
ICBC_FORCEINLINE VFloat lane_id() {
return _mm256_set_ps(7, 6, 5, 4, 3, 2, 1, 0);
}
ICBC_FORCEINLINE VMask operator> (VFloat A, VFloat B) { return _mm256_cmp_ps(A, B, _CMP_GT_OQ); }
ICBC_FORCEINLINE VMask operator>=(VFloat A, VFloat B) { return _mm256_cmp_ps(A, B, _CMP_GE_OQ); }
ICBC_FORCEINLINE VMask operator< (VFloat A, VFloat B) { return _mm256_cmp_ps(A, B, _CMP_LT_OQ); }
ICBC_FORCEINLINE VMask operator<=(VFloat A, VFloat B) { return _mm256_cmp_ps(A, B, _CMP_LE_OQ); }
ICBC_FORCEINLINE VMask operator| (VMask A, VMask B) { return _mm256_or_ps(A, B); }
ICBC_FORCEINLINE VMask operator& (VMask A, VMask B) { return _mm256_and_ps(A, B); }
ICBC_FORCEINLINE VMask operator^ (VMask A, VMask B) { return _mm256_xor_ps(A, B); }
// mask ? b : a
ICBC_FORCEINLINE VFloat vselect(VMask mask, VFloat a, VFloat b) {
return _mm256_blendv_ps(a, b, mask);
}
ICBC_FORCEINLINE VMask vbroadcast(bool b) {
return _mm256_castsi256_ps(_mm256_set1_epi32(-int32_t(b)));
}
ICBC_FORCEINLINE bool all(VMask m) {
__m256 zero = _mm256_setzero_ps();
return _mm256_testc_ps(_mm256_cmp_ps(zero, zero, _CMP_EQ_UQ), m) == 0;
}
ICBC_FORCEINLINE bool any(VMask m) {
return _mm256_testz_ps(m, m) == 0;
}
ICBC_FORCEINLINE uint mask(VMask m) {
return (uint)_mm256_movemask_ps(m);
}
// This is missing on some GCC versions.
#if !defined _mm256_set_m128
#define _mm256_set_m128(hi, lo) _mm256_insertf128_ps(_mm256_castps128_ps256(lo), (hi), 0x1)
#endif
ICBC_FORCEINLINE int reduce_min_index(VFloat v) {
__m128 vlow = _mm256_castps256_ps128(v);
__m128 vhigh = _mm256_extractf128_ps(v, 1);
vlow = _mm_min_ps(vlow, vhigh);
// First do an horizontal reduction. // v = [ D C | B A ]
__m128 shuf = _mm_shuffle_ps(vlow, vlow, _MM_SHUFFLE(2, 3, 0, 1)); // [ C D | A B ]
__m128 mins = _mm_min_ps(vlow, shuf); // mins = [ D+C C+D | B+A A+B ]
shuf = _mm_movehl_ps(shuf, mins); // [ C D | D+C C+D ]
mins = _mm_min_ss(mins, shuf);
VFloat vmin = _mm256_permute_ps(_mm256_set_m128(mins, mins), 0); // _MM256_PERMUTE(0, 0, 0, 0, 0, 0, 0, 0)
// Then find the index.
uint mask = _mm256_movemask_ps(v <= vmin);
return ctz(mask);
}
// AoS to SoA
ICBC_FORCEINLINE void vtranspose4(VFloat & a, VFloat & b, VFloat & c, VFloat & d) {
VFloat r0 = _mm256_unpacklo_ps(a, b);
VFloat r1 = _mm256_unpacklo_ps(c, d);
VFloat r2 = _mm256_permute2f128_ps(r0, r1, 0x20);
VFloat r3 = _mm256_permute2f128_ps(r0, r1, 0x31);
r0 = _mm256_unpackhi_ps(a, b);
r1 = _mm256_unpackhi_ps(c, d);
a = _mm256_unpacklo_ps(r2, r3);
b = _mm256_unpackhi_ps(r2, r3);
r2 = _mm256_permute2f128_ps(r0, r1, 0x20);
r3 = _mm256_permute2f128_ps(r0, r1, 0x31);
c = _mm256_unpacklo_ps(r2, r3);
d = _mm256_unpackhi_ps(r2, r3);
}
ICBC_FORCEINLINE VInt vzeroi() {
return _mm256_setzero_si256();
}
ICBC_FORCEINLINE VInt vbroadcast(int a) {
return _mm256_set1_epi32(a);
}
ICBC_FORCEINLINE VInt vload(const int * ptr) {
return _mm256_load_si256((const __m256i*)ptr);
}
ICBC_FORCEINLINE VInt operator- (VInt A, int b) { return _mm256_sub_epi32(A, _mm256_set1_epi32(b)); }
ICBC_FORCEINLINE VInt operator& (VInt A, int b) { return _mm256_and_si256(A, _mm256_set1_epi32(b)); }
ICBC_FORCEINLINE VInt operator>> (VInt A, int b) { return _mm256_srli_epi32(A, b); }
ICBC_FORCEINLINE VMask operator> (VInt A, int b) { return _mm256_castsi256_ps(_mm256_cmpgt_epi32(A, _mm256_set1_epi32(b))); }
ICBC_FORCEINLINE VMask operator>= (VInt A, int b) { return _mm256_castsi256_ps(_mm256_cmpgt_epi32(A, _mm256_set1_epi32(b-1))); }
ICBC_FORCEINLINE VMask operator== (VInt A, int b) { return _mm256_castsi256_ps(_mm256_cmpeq_epi32(A, _mm256_set1_epi32(b))); }
// mask ? v[idx] : 0
ICBC_FORCEINLINE VFloat vpermuteif(VMask mask, VFloat v, VInt idx) {
return _mm256_and_ps(_mm256_permutevar8x32_ps(v, idx), mask);
}
// mask ? (idx > 8 ? vhi[idx] : vlo[idx]) : 0
ICBC_FORCEINLINE VFloat vpermute2if(VMask mask, VFloat vlo, VFloat vhi, VInt idx) {
#if 0
VMask mhi = idx > 7;
vlo = _mm256_permutevar8x32_ps(vlo, idx);
vhi = _mm256_permutevar8x32_ps(vhi, idx);
VFloat v = _mm256_blendv_ps(vlo, vhi, mhi);
return _mm256_and_ps(v, mask);
#else
// Fabian Giesen says not to mix _mm256_blendv_ps and _mm256_permutevar8x32_ps since they contend for the same gates and instead suggests the following:
vhi = _mm256_xor_ps(vhi, vlo);
VFloat v = _mm256_permutevar8x32_ps(vlo, idx);
VMask mhi = idx > 7;
v = _mm256_xor_ps(v, _mm256_and_ps(_mm256_permutevar8x32_ps(vhi, idx), mhi));
return _mm256_and_ps(v, mask);
#endif
}
#elif ICBC_SIMD == ICBC_AVX512
constexpr int VEC_SIZE = 16;
#if __GNUC__
union VFloat {
__m512 v;
float m512_f32[VEC_SIZE];
VFloat() {}
VFloat(__m512 v) : v(v) {}
operator __m512 & () { return v; }
};
union VInt {
__m512i v;
int m512i_i32[VEC_SIZE];
VInt() {}
VInt(__m512i v) : v(v) {}
operator __m512i & () { return v; }
};
#else
using VFloat = __m512;
using VInt = __m512i;
#endif
struct VMask { __mmask16 m; };
ICBC_FORCEINLINE float & lane(VFloat & v, int i) {
return v.m512_f32[i];
}
ICBC_FORCEINLINE VFloat vzero() {
return _mm512_setzero_ps();
}
ICBC_FORCEINLINE VFloat vbroadcast(float a) {
return _mm512_set1_ps(a);
}
ICBC_FORCEINLINE VFloat vload(const float * ptr) {
return _mm512_load_ps(ptr);
}
ICBC_FORCEINLINE VFloat vload(VMask mask, const float * ptr) {
return _mm512_mask_load_ps(_mm512_undefined(), mask.m, ptr);
}
ICBC_FORCEINLINE VFloat vload(VMask mask, const float * ptr, float fallback) {
return _mm512_mask_load_ps(_mm512_set1_ps(fallback), mask.m, ptr);
}
ICBC_FORCEINLINE VFloat vgather(const float * base, VFloat index) {
return _mm512_i32gather_ps(_mm512_cvtps_epi32(index), base, 4);
}
ICBC_FORCEINLINE VFloat operator+(VFloat a, VFloat b) {
return _mm512_add_ps(a, b);
}
ICBC_FORCEINLINE VFloat operator-(VFloat a, VFloat b) {
return _mm512_sub_ps(a, b);
}
ICBC_FORCEINLINE VFloat operator*(VFloat a, VFloat b) {
return _mm512_mul_ps(a, b);
}
ICBC_FORCEINLINE VFloat vrcp(VFloat a) {
#if ICBC_USE_RCP
VFloat r = _mm512_rcp14_ps(a);
// r = r * (2 - r * a)
return _mm512_mul_ps(r, _mm512_fnmadd_ps(r, a, vbroadcast(2.0f)));
#else
return _mm512_div_ps(vbroadcast(1.0f), a);
#endif
}
// a*b+c
ICBC_FORCEINLINE VFloat vmadd(VFloat a, VFloat b, VFloat c) {
return _mm512_fmadd_ps(a, b, c);
}
ICBC_FORCEINLINE VFloat vmsub(VFloat a, VFloat b, VFloat c) {
return _mm512_fmsub_ps(a, b, c);
}
ICBC_FORCEINLINE VFloat vm2sub(VFloat a, VFloat b, VFloat c, VFloat d) {
return vmsub(a, b, c * d);
}
ICBC_FORCEINLINE VFloat vsaturate(VFloat a) {
auto zero = _mm512_setzero_ps();
auto one = _mm512_set1_ps(1.0f);
return _mm512_min_ps(_mm512_max_ps(a, zero), one);
}
ICBC_FORCEINLINE VFloat vround01(VFloat a) {
return _mm512_roundscale_ps(a, _MM_FROUND_TO_NEAREST_INT);
}
ICBC_FORCEINLINE VFloat vtruncate(VFloat a) {
return _mm512_roundscale_ps(a, _MM_FROUND_TO_ZERO);
}
ICBC_FORCEINLINE VFloat lane_id() {
return _mm512_set_ps(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
}
ICBC_FORCEINLINE VMask operator> (VFloat A, VFloat B) { return { _mm512_cmp_ps_mask(A, B, _CMP_GT_OQ) }; }