slave_1_tb.vcd

$date
	Fri Apr 16 15:40:11 2021
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module slave_1_tb $end
$var wire 4 ! slave_out [3:0] $end
$var wire 1 " slave_done $end
$var reg 1 # clk $end
$var reg 1 $ rst_n $end
$var reg 1 % slave_en $end
$scope module obey $end
$var wire 1 # clk $end
$var wire 1 $ rst_n $end
$var wire 1 % slave_en $end
$var wire 1 " slave_done $end
$var reg 4 & slave_out [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 &
0%
0$
1#
0"
b0 !
$end
#5
0#
#10
b1 !
b1 &
1#
1%
1$
#15
0#
#20
b10 !
b10 &
1#
#25
0#
#30
b11 !
b11 &
1#
#35
0#
#40
1"
b100 !
b100 &
1#
#45
0#
#50
0"
b0 !
b0 &
1#
0%
#55
0#
#60
1#
#65
0#
#70
1#
#75
0#
#80
1#
#85
0#
#90
1#
#95
0#
#100
1#
#105
0#
#110
1#
#115
0#
#120
1#
#125
0#
#130
1#
#135
0#
#140
1#
#145
0#
#150
1#
#155
0#
#160
1#
#165
0#
#170
1#
#175
0#
#180
1#
#185
0#
#190
1#
#195
0#
#200
1#
#205
0#
#210
1#
#215
0#
#220
1#
#225
0#
#230
1#
#235
0#
#240
1#
#245
0#
#250
1#