filter5x5.vcd

$date
	Sun Apr 25 13:24:18 2021
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module filter5x5_tb $end
$var wire 1 ! fill_now $end
$var wire 16 " Dout [15:0] $end
$var reg 8 # Din [7:0] $end
$var reg 1 $ clk $end
$var reg 1 % data_valid $end
$var reg 1 & rst $end
$scope module UUT $end
$var wire 8 ' Din [7:0] $end
$var wire 1 $ clk $end
$var wire 1 % data_valid $end
$var wire 1 & rst $end
$var wire 1 ! fill_now $end
$var wire 16 ( Dout [15:0] $end
$var reg 2 ) NS [1:0] $end
$var reg 2 * PS [1:0] $end
$var reg 8 + r0 [7:0] $end
$var reg 8 , r1 [7:0] $end
$var reg 8 - r2 [7:0] $end
$var reg 8 . r3 [7:0] $end
$var reg 8 / r4 [7:0] $end
$var reg 8 0 r5 [7:0] $end
$var reg 8 1 r6 [7:0] $end
$var reg 8 2 r7 [7:0] $end
$var reg 8 3 r8 [7:0] $end
$var reg 16 4 result [15:0] $end
$var integer 32 5 count [31:0] $end
$var integer 32 6 i [31:0] $end
$var integer 32 7 j [31:0] $end
$var integer 32 8 k [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 8
b0 7
b0 6
b0 5
b0 4
bx 3
bx 2
bx 1
bx 0
bx /
bx .
bx -
bx ,
bx +
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1!
$end
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