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andg2.vhd
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andg2.vhd
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-------------------------------------------------------------------------
-- Joseph Zambreno
-- Department of Electrical and Computer Engineering
-- Iowa State University
-------------------------------------------------------------------------
-- andg2.vhd
-------------------------------------------------------------------------
-- DESCRIPTION: This file contains an implementation of a 2-input AND
-- gate.
--
--
-- NOTES:
-- 8/19/16 by JAZ::Design created.
-- 1/16/19 by H3::Changed name to avoid name conflict with Quartus
-- primitives.
-------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity andg2 is
port(i_A : in std_logic;
i_B : in std_logic;
o_F : out std_logic);
end andg2;
architecture dataflow of andg2 is
begin
o_F <= i_A and i_B;
end dataflow;