Underlying projectq ValueError

[sjdilkes]

Sorry for terrible title and please let me konw if this is the wrong place for this request. I'm finding that passing QuantinuumBackend(device_name="H1-1LE", api_handler=QuantinuumAPIOffline()) the following circuit that makes use of a size 3 bit register is causing a couple of underlying errors with projectq, one related to measures and one with the classically controlled gates. Controlling of a size 2 bit register seems to be fine.

# ----
# Working circuit
# ----
c: Circuit = Circuit()
q_bits: List[Qubit] = [Qubit("qb", i) for i in range(4)]
m_bits: List[Bit] = [Bit("mb", i) for i in range(4)]
s_bits: List[Bit] = [Bit("s", i) for i in range(2)]
for q in q_bits:
    c.add_qubit(q)
for b in s_bits + m_bits:
    c.add_bit(b)

c.X(q_bits[0], condition_bits = s_bits, condition_value = 0)
c.X(q_bits[1], condition_bits = s_bits, condition_value = 1)
c.X(q_bits[2], condition_bits = s_bits, condition_value = 2)
c.X(q_bits[3], condition_bits = s_bits, condition_value = 3)

for q,b in zip(q_bits, m_bits):
    c.Measure(q,b)
    

# ----    
# Failing Circuit:
# ----
c: Circuit = Circuit()
q_bits: List[Qubit] = [Qubit("qb", i) for i in range(8)]
m_bits: List[Bit] = [Bit("mb", i) for i in range(8)]
s_bits: List[Bit] = [Bit("s", i) for i in range(3)]
for q in q_bits:
    c.add_qubit(q)
for b in s_bits + m_bits:
    c.add_bit(b)

c.X(q_bits[0], condition_bits = s_bits, condition_value = 0)
c.X(q_bits[1], condition_bits = s_bits, condition_value = 1)
c.X(q_bits[2], condition_bits = s_bits, condition_value = 2)
c.X(q_bits[3], condition_bits = s_bits, condition_value = 3)
c.X(q_bits[4], condition_bits = s_bits, condition_value = 4)
c.X(q_bits[5], condition_bits = s_bits, condition_value = 5)
c.X(q_bits[6], condition_bits = s_bits, condition_value = 6)
c.X(q_bits[7], condition_bits = s_bits, condition_value = 7)

for q,b in zip(q_bits, m_bits):
    c.Measure(q,b)

[sjdilkes]

Updating the "working circuit" such that s_bits has 3 bits also seems to cause the same issue:

c: Circuit = Circuit()
q_bits: List[Qubit] = [Qubit("qb", i) for i in range(4)]
m_bits: List[Bit] = [Bit("mb", i) for i in range(4)]
s_bits: List[Bit] = [Bit("s", i) for i in range(3)]
for q in q_bits:
    c.add_qubit(q)
for b in s_bits + m_bits:
    c.add_bit(b)

c.X(q_bits[0], condition_bits = s_bits, condition_value = 0)
c.X(q_bits[1], condition_bits = s_bits, condition_value = 1)
c.X(q_bits[2], condition_bits = s_bits, condition_value = 2)
c.X(q_bits[3], condition_bits = s_bits, condition_value = 3)

for q,b in zip(q_bits, m_bits):
    c.Measure(q,b)

[cqc-alec]

Probably an issue with pytket-phir or pecos; looking into it.

[cqc-alec]

Root cause seems to be CQCL/pytket-phir#215 .

[qartik]

New release of pytket-phir with the fix: https://github.com/CQCL/pytket-phir/releases/tag/v0.8.1

[cqc-alec]

Updating to pytket-phir 0.8.1 should fix this issue. Closing.