From 0689ae86297ebb36c0416ee6da9e218ca8c8e030 Mon Sep 17 00:00:00 2001 From: Hansem Ro Date: Sat, 4 May 2024 22:24:30 -0700 Subject: [PATCH] HT32: Add generic HT32F1655/6 board --- os/hal/boards/HT_HT32F1655_6/board.c | 113 ++++ os/hal/boards/HT_HT32F1655_6/board.h | 757 ++++++++++++++++++++++++++ os/hal/boards/HT_HT32F1655_6/board.mk | 9 + 3 files changed, 879 insertions(+) create mode 100644 os/hal/boards/HT_HT32F1655_6/board.c create mode 100644 os/hal/boards/HT_HT32F1655_6/board.h create mode 100644 os/hal/boards/HT_HT32F1655_6/board.mk diff --git a/os/hal/boards/HT_HT32F1655_6/board.c b/os/hal/boards/HT_HT32F1655_6/board.c new file mode 100644 index 0000000000..a03581b6c6 --- /dev/null +++ b/os/hal/boards/HT_HT32F1655_6/board.c @@ -0,0 +1,113 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + // GPIO A + .setup[0] = + { + .DIR = VAL_GPIOA_DIRCR, + .INE = VAL_GPIOA_INER, + .PU = VAL_GPIOA_PUR, + .PD = VAL_GPIOA_PDR, + .OD = VAL_GPIOA_ODR, + .DRV = VAL_GPIOA_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOA_AFCFGR0, + .CFG[1] = VAL_GPIOA_AFCFGR1, + }, + // GPIO B + .setup[1] = + { + .DIR = VAL_GPIOB_DIRCR, + .INE = VAL_GPIOB_INER, + .PU = VAL_GPIOB_PUR, + .PD = VAL_GPIOB_PDR, + .OD = VAL_GPIOB_ODR, + .DRV = VAL_GPIOB_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOB_AFCFGR0, + .CFG[1] = VAL_GPIOB_AFCFGR1, + }, + // GPIO C + .setup[2] = + { + .DIR = VAL_GPIOC_DIRCR, + .INE = VAL_GPIOC_INER, + .PU = VAL_GPIOC_PUR, + .PD = VAL_GPIOC_PDR, + .OD = VAL_GPIOC_ODR, + .DRV = VAL_GPIOC_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOC_AFCFGR0, + .CFG[1] = VAL_GPIOC_AFCFGR1, + }, + // GPIO D + .setup[3] = + { + .DIR = VAL_GPIOD_DIRCR, + .INE = VAL_GPIOD_INER, + .PU = VAL_GPIOD_PUR, + .PD = VAL_GPIOD_PDR, + .OD = VAL_GPIOD_ODR, + .DRV = VAL_GPIOD_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOD_AFCFGR0, + .CFG[1] = VAL_GPIOD_AFCFGR1, + }, + // GPIO E + .setup[4] = + { + .DIR = VAL_GPIOE_DIRCR, + .INE = VAL_GPIOE_INER, + .PU = VAL_GPIOE_PUR, + .PD = VAL_GPIOE_PDR, + .OD = VAL_GPIOE_ODR, + .DRV = VAL_GPIOE_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOE_AFCFGR0, + .CFG[1] = VAL_GPIOE_AFCFGR1, + }, + .ESSR[0] = VAL_ESSR0, + .ESSR[1] = VAL_ESSR1, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + ht32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) {} diff --git a/os/hal/boards/HT_HT32F1655_6/board.h b/os/hal/boards/HT_HT32F1655_6/board.h new file mode 100644 index 0000000000..fe9ec9c876 --- /dev/null +++ b/os/hal/boards/HT_HT32F1655_6/board.h @@ -0,0 +1,757 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#pragma once + +/* + * Setup for a Generic HT32F1655/6 board. + */ + +/* + * Board identifier. + */ +#define BOARD_HT32_F1655_6 +#define BOARD_NAME "Generic HT32F1655/6 Board" + +/* + * Board frequencies. + */ +#define HT32_LSECLK 32768 +#define HT32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define HT32F1656 + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the HT32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << (n)) +#define PIN_MODE_OUTPUT(n) (1U << (n)) +#define PIN_INPUT_DISABLE(n) (0U << (n)) +#define PIN_INPUT_ENABLE(n) (1U << (n)) +#define PIN_PULLUP_DISABLE(n) (0U << (n)) +#define PIN_PULLUP_ENABLE(n) (1U << (n)) +#define PIN_PULLDOWN_DISABLE(n) (0U << (n)) +#define PIN_PULLDOWN_ENABLE(n) (1U << (n)) +#define PIN_ODR_PUSHPULL(n) (0U << (n)) +#define PIN_ODR_OPENDRAIN(n) (1U << (n)) +#define PIN_DRVR_4MA(n) (0U << (n)) +#define PIN_DRVR_8MA(n) (0U << (n)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * Port A setup. + * Everything GPIO input with pull-up except: + * PA12 - AF0 - SWCLK + * PA13 - AF0 - SWDIO + */ +#define VAL_GPIOA_DIRCR (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_INPUT(GPIOA_PIN13) | \ + PIN_MODE_INPUT(GPIOA_PIN14) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_INER (PIN_INPUT_ENABLE(GPIOA_PIN0) | \ + PIN_INPUT_ENABLE(GPIOA_PIN1) | \ + PIN_INPUT_ENABLE(GPIOA_PIN2) | \ + PIN_INPUT_ENABLE(GPIOA_PIN3) | \ + PIN_INPUT_ENABLE(GPIOA_PIN4) | \ + PIN_INPUT_ENABLE(GPIOA_PIN5) | \ + PIN_INPUT_ENABLE(GPIOA_PIN6) | \ + PIN_INPUT_ENABLE(GPIOA_PIN7) | \ + PIN_INPUT_ENABLE(GPIOA_PIN8) | \ + PIN_INPUT_ENABLE(GPIOA_PIN9) | \ + PIN_INPUT_ENABLE(GPIOA_PIN10) | \ + PIN_INPUT_ENABLE(GPIOA_PIN11) | \ + PIN_INPUT_DISABLE(GPIOA_PIN12) | \ + PIN_INPUT_DISABLE(GPIOA_PIN13) | \ + PIN_INPUT_ENABLE(GPIOA_PIN14) | \ + PIN_INPUT_ENABLE(GPIOA_PIN15)) +#define VAL_GPIOA_PUR (PIN_PULLUP_ENABLE(GPIOA_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN11) | \ + PIN_PULLUP_DISABLE(GPIOA_PIN12) | \ + PIN_PULLUP_DISABLE(GPIOA_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN15)) +#define VAL_GPIOA_PDR (PIN_PULLDOWN_DISABLE(GPIOA_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_PUSHPULL(GPIOA_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_DRVR (PIN_DRVR_4MA(GPIOA_PIN0) | \ + PIN_DRVR_4MA(GPIOA_PIN1) | \ + PIN_DRVR_4MA(GPIOA_PIN2) | \ + PIN_DRVR_4MA(GPIOA_PIN3) | \ + PIN_DRVR_4MA(GPIOA_PIN4) | \ + PIN_DRVR_4MA(GPIOA_PIN5) | \ + PIN_DRVR_4MA(GPIOA_PIN6) | \ + PIN_DRVR_4MA(GPIOA_PIN7) | \ + PIN_DRVR_4MA(GPIOA_PIN8) | \ + PIN_DRVR_4MA(GPIOA_PIN9) | \ + PIN_DRVR_4MA(GPIOA_PIN10) | \ + PIN_DRVR_4MA(GPIOA_PIN11) | \ + PIN_DRVR_4MA(GPIOA_PIN12) | \ + PIN_DRVR_4MA(GPIOA_PIN13) | \ + PIN_DRVR_4MA(GPIOA_PIN14) | \ + PIN_DRVR_4MA(GPIOA_PIN15)) +#define VAL_GPIOA_AFCFGR0 (PIN_AFIO_AF(GPIOA_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN7, AFIO_GPIO)) +#define VAL_GPIOA_AFCFGR1 (PIN_AFIO_AF(GPIOA_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN12, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOA_PIN13, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOA_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN15, AFIO_GPIO)) + +/* + * Port B setup. + * Everything GPIO input with pull-up except: + * PB12 - AF0 - USBD- + * PB13 - AF0 - USBD+ + * PB14 - AF0 - XTALIN + * PB15 - AF0 - XTALOUT + */ +#define VAL_GPIOB_DIRCR (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_INPUT(GPIOB_PIN3) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_INER (PIN_INPUT_ENABLE(GPIOB_PIN0) | \ + PIN_INPUT_ENABLE(GPIOB_PIN1) | \ + PIN_INPUT_ENABLE(GPIOB_PIN2) | \ + PIN_INPUT_ENABLE(GPIOB_PIN3) | \ + PIN_INPUT_ENABLE(GPIOB_PIN4) | \ + PIN_INPUT_ENABLE(GPIOB_PIN5) | \ + PIN_INPUT_ENABLE(GPIOB_PIN6) | \ + PIN_INPUT_ENABLE(GPIOB_PIN7) | \ + PIN_INPUT_ENABLE(GPIOB_PIN8) | \ + PIN_INPUT_ENABLE(GPIOB_PIN9) | \ + PIN_INPUT_ENABLE(GPIOB_PIN10) | \ + PIN_INPUT_ENABLE(GPIOB_PIN11) | \ + PIN_INPUT_DISABLE(GPIOB_PIN12) | \ + PIN_INPUT_DISABLE(GPIOB_PIN13) | \ + PIN_INPUT_DISABLE(GPIOB_PIN14) | \ + PIN_INPUT_DISABLE(GPIOB_PIN15)) +#define VAL_GPIOB_PUR (PIN_PULLUP_ENABLE(GPIOB_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN11) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN12) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN13) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN14) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN15)) +#define VAL_GPIOB_PDR (PIN_PULLDOWN_DISABLE(GPIOB_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_PUSHPULL(GPIOB_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_DRVR (PIN_DRVR_4MA(GPIOB_PIN0) | \ + PIN_DRVR_4MA(GPIOB_PIN1) | \ + PIN_DRVR_4MA(GPIOB_PIN2) | \ + PIN_DRVR_4MA(GPIOB_PIN3) | \ + PIN_DRVR_4MA(GPIOB_PIN4) | \ + PIN_DRVR_4MA(GPIOB_PIN5) | \ + PIN_DRVR_4MA(GPIOB_PIN6) | \ + PIN_DRVR_4MA(GPIOB_PIN7) | \ + PIN_DRVR_4MA(GPIOB_PIN8) | \ + PIN_DRVR_4MA(GPIOB_PIN9) | \ + PIN_DRVR_4MA(GPIOB_PIN10) | \ + PIN_DRVR_4MA(GPIOB_PIN11) | \ + PIN_DRVR_4MA(GPIOB_PIN12) | \ + PIN_DRVR_4MA(GPIOB_PIN13) | \ + PIN_DRVR_4MA(GPIOB_PIN14) | \ + PIN_DRVR_4MA(GPIOB_PIN15)) +#define VAL_GPIOB_AFCFGR0 (PIN_AFIO_AF(GPIOB_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN7, AFIO_GPIO)) +#define VAL_GPIOB_AFCFGR1 (PIN_AFIO_AF(GPIOB_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN12, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN13, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN14, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN15, AFIO_DEFAULT)) + +/* + * Port C setup. + * Everything GPIO input with pull-up + */ +#define VAL_GPIOC_DIRCR (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_INER (PIN_INPUT_ENABLE(GPIOC_PIN0) | \ + PIN_INPUT_ENABLE(GPIOC_PIN1) | \ + PIN_INPUT_ENABLE(GPIOC_PIN2) | \ + PIN_INPUT_ENABLE(GPIOC_PIN3) | \ + PIN_INPUT_ENABLE(GPIOC_PIN4) | \ + PIN_INPUT_ENABLE(GPIOC_PIN5) | \ + PIN_INPUT_ENABLE(GPIOC_PIN6) | \ + PIN_INPUT_ENABLE(GPIOC_PIN7) | \ + PIN_INPUT_ENABLE(GPIOC_PIN8) | \ + PIN_INPUT_ENABLE(GPIOC_PIN9) | \ + PIN_INPUT_ENABLE(GPIOC_PIN10) | \ + PIN_INPUT_ENABLE(GPIOC_PIN11) | \ + PIN_INPUT_ENABLE(GPIOC_PIN12) | \ + PIN_INPUT_ENABLE(GPIOC_PIN13) | \ + PIN_INPUT_ENABLE(GPIOC_PIN14) | \ + PIN_INPUT_ENABLE(GPIOC_PIN15)) +#define VAL_GPIOC_PUR (PIN_PULLUP_ENABLE(GPIOC_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN12) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN15)) +#define VAL_GPIOC_PDR (PIN_PULLDOWN_DISABLE(GPIOC_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_PUSHPULL(GPIOC_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_DRVR (PIN_DRVR_4MA(GPIOC_PIN0) | \ + PIN_DRVR_4MA(GPIOC_PIN1) | \ + PIN_DRVR_4MA(GPIOC_PIN2) | \ + PIN_DRVR_4MA(GPIOC_PIN3) | \ + PIN_DRVR_4MA(GPIOC_PIN4) | \ + PIN_DRVR_4MA(GPIOC_PIN5) | \ + PIN_DRVR_4MA(GPIOC_PIN6) | \ + PIN_DRVR_4MA(GPIOC_PIN7) | \ + PIN_DRVR_4MA(GPIOC_PIN8) | \ + PIN_DRVR_4MA(GPIOC_PIN9) | \ + PIN_DRVR_4MA(GPIOC_PIN10) | \ + PIN_DRVR_4MA(GPIOC_PIN11) | \ + PIN_DRVR_4MA(GPIOC_PIN12) | \ + PIN_DRVR_4MA(GPIOC_PIN13) | \ + PIN_DRVR_4MA(GPIOC_PIN14) | \ + PIN_DRVR_4MA(GPIOC_PIN15)) +#define VAL_GPIOC_AFCFGR0 (PIN_AFIO_AF(GPIOC_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN7, AFIO_GPIO)) +#define VAL_GPIOC_AFCFGR1 (PIN_AFIO_AF(GPIOC_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN13, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN15, AFIO_GPIO)) + +/* + * Port D setup. + * Everything GPIO input with pull-up + */ +#define VAL_GPIOD_DIRCR (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_INER (PIN_INPUT_ENABLE(GPIOD_PIN0) | \ + PIN_INPUT_ENABLE(GPIOD_PIN1) | \ + PIN_INPUT_ENABLE(GPIOD_PIN2) | \ + PIN_INPUT_ENABLE(GPIOD_PIN3) | \ + PIN_INPUT_ENABLE(GPIOD_PIN4) | \ + PIN_INPUT_ENABLE(GPIOD_PIN5) | \ + PIN_INPUT_ENABLE(GPIOD_PIN6) | \ + PIN_INPUT_ENABLE(GPIOD_PIN7) | \ + PIN_INPUT_ENABLE(GPIOD_PIN8) | \ + PIN_INPUT_ENABLE(GPIOD_PIN9) | \ + PIN_INPUT_ENABLE(GPIOD_PIN10) | \ + PIN_INPUT_ENABLE(GPIOD_PIN11) | \ + PIN_INPUT_ENABLE(GPIOD_PIN12) | \ + PIN_INPUT_ENABLE(GPIOD_PIN13) | \ + PIN_INPUT_ENABLE(GPIOD_PIN14) | \ + PIN_INPUT_ENABLE(GPIOD_PIN15)) +#define VAL_GPIOD_PUR (PIN_PULLUP_ENABLE(GPIOD_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN12) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN15)) +#define VAL_GPIOD_PDR (PIN_PULLDOWN_DISABLE(GPIOD_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_PUSHPULL(GPIOD_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_DRVR (PIN_DRVR_4MA(GPIOD_PIN0) | \ + PIN_DRVR_4MA(GPIOD_PIN1) | \ + PIN_DRVR_4MA(GPIOD_PIN2) | \ + PIN_DRVR_4MA(GPIOD_PIN3) | \ + PIN_DRVR_4MA(GPIOD_PIN4) | \ + PIN_DRVR_4MA(GPIOD_PIN5) | \ + PIN_DRVR_4MA(GPIOD_PIN6) | \ + PIN_DRVR_4MA(GPIOD_PIN7) | \ + PIN_DRVR_4MA(GPIOD_PIN8) | \ + PIN_DRVR_4MA(GPIOD_PIN9) | \ + PIN_DRVR_4MA(GPIOD_PIN10) | \ + PIN_DRVR_4MA(GPIOD_PIN11) | \ + PIN_DRVR_4MA(GPIOD_PIN12) | \ + PIN_DRVR_4MA(GPIOD_PIN13) | \ + PIN_DRVR_4MA(GPIOD_PIN14) | \ + PIN_DRVR_4MA(GPIOD_PIN15)) +#define VAL_GPIOD_AFCFGR0 (PIN_AFIO_AF(GPIOD_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN7, AFIO_GPIO)) +#define VAL_GPIOD_AFCFGR1 (PIN_AFIO_AF(GPIOD_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN13, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN15, AFIO_GPIO)) + +/* + * Port E setup. + * Everything GPIO input with pull-up + */ +#define VAL_GPIOE_DIRCR (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_INER (PIN_INPUT_ENABLE(GPIOE_PIN0) | \ + PIN_INPUT_ENABLE(GPIOE_PIN1) | \ + PIN_INPUT_ENABLE(GPIOE_PIN2) | \ + PIN_INPUT_ENABLE(GPIOE_PIN3) | \ + PIN_INPUT_ENABLE(GPIOE_PIN4) | \ + PIN_INPUT_ENABLE(GPIOE_PIN5) | \ + PIN_INPUT_ENABLE(GPIOE_PIN6) | \ + PIN_INPUT_ENABLE(GPIOE_PIN7) | \ + PIN_INPUT_ENABLE(GPIOE_PIN8) | \ + PIN_INPUT_ENABLE(GPIOE_PIN9) | \ + PIN_INPUT_ENABLE(GPIOE_PIN10) | \ + PIN_INPUT_ENABLE(GPIOE_PIN11) | \ + PIN_INPUT_ENABLE(GPIOE_PIN12) | \ + PIN_INPUT_ENABLE(GPIOE_PIN13) | \ + PIN_INPUT_ENABLE(GPIOE_PIN14) | \ + PIN_INPUT_ENABLE(GPIOE_PIN15)) +#define VAL_GPIOE_PUR (PIN_PULLUP_ENABLE(GPIOE_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN12) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN15)) +#define VAL_GPIOE_PDR (PIN_PULLDOWN_DISABLE(GPIOE_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_PUSHPULL(GPIOE_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_DRVR (PIN_DRVR_4MA(GPIOE_PIN0) | \ + PIN_DRVR_4MA(GPIOE_PIN1) | \ + PIN_DRVR_4MA(GPIOE_PIN2) | \ + PIN_DRVR_4MA(GPIOE_PIN3) | \ + PIN_DRVR_4MA(GPIOE_PIN4) | \ + PIN_DRVR_4MA(GPIOE_PIN5) | \ + PIN_DRVR_4MA(GPIOE_PIN6) | \ + PIN_DRVR_4MA(GPIOE_PIN7) | \ + PIN_DRVR_4MA(GPIOE_PIN8) | \ + PIN_DRVR_4MA(GPIOE_PIN9) | \ + PIN_DRVR_4MA(GPIOE_PIN10) | \ + PIN_DRVR_4MA(GPIOE_PIN11) | \ + PIN_DRVR_4MA(GPIOE_PIN12) | \ + PIN_DRVR_4MA(GPIOE_PIN13) | \ + PIN_DRVR_4MA(GPIOE_PIN14) | \ + PIN_DRVR_4MA(GPIOE_PIN15)) +#define VAL_GPIOE_AFCFGR0 (PIN_AFIO_AF(GPIOE_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN7, AFIO_GPIO)) +#define VAL_GPIOE_AFCFGR1 (PIN_AFIO_AF(GPIOE_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN13, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN15, AFIO_GPIO)) + +/* + * EXTI setup. + */ +#define VAL_ESSR0 0x00000000 +#define VAL_ESSR1 0x00000000 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ diff --git a/os/hal/boards/HT_HT32F1655_6/board.mk b/os/hal/boards/HT_HT32F1655_6/board.mk new file mode 100644 index 0000000000..96ce816866 --- /dev/null +++ b/os/hal/boards/HT_HT32F1655_6/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/HT_HT32F1655_6/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/HT_HT32F1655_6 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC)