From 77cb0a4f7589f89e724f5e6ecb1d76d514dd1212 Mon Sep 17 00:00:00 2001 From: Joy Lee Date: Wed, 3 Apr 2024 20:39:24 +0800 Subject: [PATCH] [WB32 MCU] Added RTC hal. (#399) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Fixed usb remote wakeup, i2c Added more rate configurations * Added RTC configuration in hal_lld.h * 初步测试通过 实现RTC功能 * update * update rtc_lld * UPDATE * update * update 正式版本2 * update 正式版 * update 正式发布 * update 正式发布 * update 3G71 * update * update * update * update * update * update * update * update * update * Revert "Update keil project" This reverts commit 212316772920ef63174a3d4c0253c79b79b511a4. # Conflicts: # demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx * update 修改格式 * Update demos/WB32/RT-WB32F3G71-RTC/debug.h Co-authored-by: Joy Lee * Update demos/WB32/RT-WB32F3G71-RTC/main.c Co-authored-by: Joy Lee * Update demos/WB32/RT-WB32F3G71-RTC/main.c Co-authored-by: Joy Lee * Update demos/WB32/RT-WB32F3G71-RTC/main.c Co-authored-by: Joy Lee * Revert "Update keil project" This reverts commit 212316772920ef63174a3d4c0253c79b79b511a4. # Conflicts: # demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx * update * update * update * update * Update os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c Co-authored-by: Joy Lee * Update os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c Co-authored-by: Joy Lee * Update os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c Co-authored-by: Joy Lee * Update os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c Co-authored-by: Joy Lee * Update os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c Co-authored-by: Joy Lee * UPDATE * update * update * update * update * update * Update hal_usb_lld.c * Update --------- Co-authored-by: bingkun.li Co-authored-by: wind <108604699+yelishang@users.noreply.github.com> Co-authored-by: wb --- demos/WB32/RT-WB32F3G71-RTC/Makefile | 204 ++ demos/WB32/RT-WB32F3G71-RTC/board/board.c | 82 + demos/WB32/RT-WB32F3G71-RTC/board/board.h | 56 + demos/WB32/RT-WB32F3G71-RTC/board/board.mk | 9 + demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h | 834 ++++++ demos/WB32/RT-WB32F3G71-RTC/cfg/halconf.h | 531 ++++ demos/WB32/RT-WB32F3G71-RTC/cfg/mcuconf.h | 182 ++ demos/WB32/RT-WB32F3G71-RTC/debug.c | 36 + demos/WB32/RT-WB32F3G71-RTC/debug.h | 25 + demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvoptx | 2478 +++++++++++++++++ demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvprojx | 1364 +++++++++ demos/WB32/RT-WB32F3G71-RTC/main.c | 236 ++ demos/WB32/RT-WB32F3G71-RTC/readme.md | 4 + demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h | 12 +- demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx | 224 +- .../WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx | 11 +- os/hal/ports/WB32/LLD/EXTIv1/driver.mk | 2 + os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c | 145 + os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.h | 117 + os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c | 8 +- os/hal/ports/WB32/LLD/RTCv1/driver.mk | 8 + os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c | 617 ++++ os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.h | 164 ++ os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c | 42 +- os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h | 2 +- os/hal/ports/WB32/WB32F3G71xx/hal_lld.c | 36 + os/hal/ports/WB32/WB32F3G71xx/hal_lld.h | 86 + os/hal/ports/WB32/WB32F3G71xx/platform.mk | 2 + os/hal/ports/WB32/WB32F3G71xx/wb32_rcc.h | 87 +- os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h | 2 + os/hal/ports/WB32/WB32FQ95xx/hal_lld.c | 36 + os/hal/ports/WB32/WB32FQ95xx/hal_lld.h | 86 + os/hal/ports/WB32/WB32FQ95xx/platform.mk | 2 + os/hal/ports/WB32/WB32FQ95xx/wb32_rcc.h | 87 +- os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h | 2 + 35 files changed, 7664 insertions(+), 155 deletions(-) create mode 100644 demos/WB32/RT-WB32F3G71-RTC/Makefile create mode 100644 demos/WB32/RT-WB32F3G71-RTC/board/board.c create mode 100644 demos/WB32/RT-WB32F3G71-RTC/board/board.h create mode 100644 demos/WB32/RT-WB32F3G71-RTC/board/board.mk create mode 100644 demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h create mode 100644 demos/WB32/RT-WB32F3G71-RTC/cfg/halconf.h create mode 100644 demos/WB32/RT-WB32F3G71-RTC/cfg/mcuconf.h create mode 100644 demos/WB32/RT-WB32F3G71-RTC/debug.c create mode 100644 demos/WB32/RT-WB32F3G71-RTC/debug.h create mode 100644 demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvoptx create mode 100644 demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvprojx create mode 100644 demos/WB32/RT-WB32F3G71-RTC/main.c create mode 100644 demos/WB32/RT-WB32F3G71-RTC/readme.md create mode 100644 os/hal/ports/WB32/LLD/EXTIv1/driver.mk create mode 100644 os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c create mode 100644 os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.h create mode 100644 os/hal/ports/WB32/LLD/RTCv1/driver.mk create mode 100644 os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c create mode 100644 os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.h diff --git a/demos/WB32/RT-WB32F3G71-RTC/Makefile b/demos/WB32/RT-WB32F3G71-RTC/Makefile new file mode 100644 index 0000000000..92711c3f92 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/Makefile @@ -0,0 +1,204 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m3 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep +BOARDDIR := ./board + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_wb32f3g71xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/WB32F3G71xx/platform.mk +include $(BOARDDIR)/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +# include $(CHIBIOS)/test/lib/test.mk +# include $(CHIBIOS)/test/rt/rt_test.mk +# include $(CHIBIOS)/test/oslib/oslib_test.mk +# include $(CHIBIOS)/os/hal/lib/streams/streams.mk +# include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/WB32F3G71xC.ld + + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/hal/lib/streams/chprintf.c \ + debug.c \ + main.c + +ALLINC += ./ \ + $(CHIBIOS)/os/common/lib/include \ + $(CHIBIOS)/os/common/oop/include \ + $(CHIBIOS)/os/hal/lib/streams + + + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/WB32/RT-WB32F3G71-RTC/board/board.c b/demos/WB32/RT-WB32F3G71-RTC/board/board.c new file mode 100644 index 0000000000..d76353f822 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/board/board.c @@ -0,0 +1,82 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void wb32_gpio_init(void) { + +#if WB32_HAS_GPIOA + rccEnableAPB1(RCC_APB1ENR_GPIOAEN); +#endif + +#if WB32_HAS_GPIOB + rccEnableAPB1(RCC_APB1ENR_GPIOBEN); +#endif + +#if WB32_HAS_GPIOC + rccEnableAPB1(RCC_APB1ENR_GPIOCEN); +#endif + +#if WB32_HAS_GPIOD + rccEnableAPB1(RCC_APB1ENR_GPIODEN); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + wb32_clock_init(); + wb32_gpio_init(); +} +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/demos/WB32/RT-WB32F3G71-RTC/board/board.h b/demos/WB32/RT-WB32F3G71-RTC/board/board.h new file mode 100644 index 0000000000..64439c3791 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/board/board.h @@ -0,0 +1,56 @@ +#pragma once +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup board. + */ + +/* + * Board identifier. + */ +#define WB32FQ95xC +#if !defined(WB32F3G71xx) + #define WB32F3G71xx +#endif + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/demos/WB32/RT-WB32F3G71-RTC/board/board.mk b/demos/WB32/RT-WB32F3G71-RTC/board/board.mk new file mode 100644 index 0000000000..60673b374e --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARDDIR)/board.c + +# Required include directories +BOARDINC = $(BOARDDIR) + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h b/demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h new file mode 100644 index 0000000000..3fd3c65f9e --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h @@ -0,0 +1,834 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/WB32/RT-WB32F3G71-RTC/cfg/halconf.h b/demos/WB32/RT-WB32F3G71-RTC/cfg/halconf.h new file mode 100644 index 0000000000..05807866c2 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/cfg/halconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/WB32/RT-WB32F3G71-RTC/cfg/mcuconf.h b/demos/WB32/RT-WB32F3G71-RTC/cfg/mcuconf.h new file mode 100644 index 0000000000..77cef7df98 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/cfg/mcuconf.h @@ -0,0 +1,182 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define WB32F3G71xx_MCUCONF TRUE + +/* + * WB32FQ95 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + */ + +/** + * @name Internal clock sources + * @{ + */ +#define WB32_HSECLK 12000000 +#define WB32_LSECLK 32768 + +/* + * HAL driver system settings. + */ +#define WB32_NO_INIT FALSE +#define WB32_MHSI_ENABLED TRUE +#define WB32_FHSI_ENABLED FALSE +#define WB32_LSI_ENABLED TRUE +#define WB32_HSE_ENABLED TRUE +#define WB32_LSE_ENABLED TRUE +#define WB32_PLL_ENABLED TRUE +#define WB32_MAINCLKSRC WB32_MAINCLKSRC_PLL +#define WB32_HSE_STATE ANCTL_HSECR0_HSEON +#define WB32_PLLSRC WB32_PLLSRC_HSE +#define WB32_PLLDIV_VALUE 2 +#define WB32_PLLMUL_VALUE 12 // The allowed range is 12,16,20,24. +#define WB32_HPRE 1 +#define WB32_PPRE1 1 +#define WB32_PPRE2 1 +#define WB32_USBPRE WB32_USBPRE_DIV1P5 +#define WB32_RTCSEL WB32_RTCSEL_HSEDIV +#define WB32_RTCLP_SEL WB32_RTCSEL_LSI +/* + * EXTI driver system settings. + */ +#define WB32_EXTI_REQUIRED +#define WB32_IRQ_EXTI0_PRIORITY 6 +#define WB32_IRQ_EXTI1_PRIORITY 6 +#define WB32_IRQ_EXTI2_PRIORITY 6 +#define WB32_IRQ_EXTI3_PRIORITY 6 +#define WB32_IRQ_EXTI4_PRIORITY 6 +#define WB32_IRQ_EXTI5_9_PRIORITY 6 +#define WB32_IRQ_EXTI10_15_PRIORITY 6 +#define WB32_IRQ_EXTI16_PRIORITY 6 +#define WB32_IRQ_EXTI17_PRIORITY 6 +#define WB32_IRQ_EXTI18_PRIORITY 6 +#define WB32_IRQ_EXTI19_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define WB32_TIM_MAX_CHANNELS 4 +#define WB32_GPT_USE_TIM1 FALSE +#define WB32_GPT_USE_TIM2 FALSE +#define WB32_GPT_USE_TIM3 FALSE +#define WB32_GPT_USE_TIM4 FALSE +#define WB32_GPT_TIM1_IRQ_PRIORITY 7 +#define WB32_GPT_TIM2_IRQ_PRIORITY 7 +#define WB32_GPT_TIM3_IRQ_PRIORITY 7 +#define WB32_GPT_TIM4_IRQ_PRIORITY 7 +/* + * RTC driver system settings. + */ +#define WB32_RTCAlarm_IRQ_PRIORITY 14 +#define WB32_RTC_IRQ_PRIORITY 15 + +/* + * ICU driver system settings. + */ +#define WB32_ICU_USE_TIM1 FALSE +#define WB32_ICU_USE_TIM2 FALSE +#define WB32_ICU_USE_TIM3 FALSE +#define WB32_ICU_USE_TIM4 FALSE +#define WB32_ICU_TIM1_IRQ_PRIORITY 7 +#define WB32_ICU_TIM2_IRQ_PRIORITY 7 +#define WB32_ICU_TIM3_IRQ_PRIORITY 7 +#define WB32_ICU_TIM4_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define WB32_PWM_USE_ADVANCED FALSE +#define WB32_PWM_USE_TIM1 FALSE +#define WB32_PWM_USE_TIM2 FALSE +#define WB32_PWM_USE_TIM3 FALSE +#define WB32_PWM_USE_TIM4 FALSE +#define WB32_PWM_TIM1_IRQ_PRIORITY 7 +#define WB32_PWM_TIM2_IRQ_PRIORITY 7 +#define WB32_PWM_TIM3_IRQ_PRIORITY 7 +#define WB32_PWM_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define WB32_I2C_USE_I2C1 FALSE +#define WB32_I2C_USE_I2C2 FALSE +#define WB32_I2C_BUSY_TIMEOUT 50 +#define WB32_I2C_I2C1_IRQ_PRIORITY 5 +#define WB32_I2C_I2C2_IRQ_PRIORITY 5 + +/* + * SERIAL driver system settings. + */ +#define WB32_SERIAL_USE_UART1 TRUE +#define WB32_SERIAL_USE_UART2 FALSE +#define WB32_SERIAL_USE_UART3 FALSE +#define WB32_SERIAL_UART1_PRIORITY 12 +#define WB32_SERIAL_UART2_PRIORITY 12 +#define WB32_SERIAL_UART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define WB32_SPI_USE_QSPI FALSE +#define WB32_SPI_USE_SPIM2 FALSE +#define WB32_SPI_USE_SPIS1 FALSE +#define WB32_SPI_USE_SPIS2 FALSE +#define WB32_SPI_QSPI_IRQ_PRIORITY 10 +#define WB32_SPI_SPIM2_IRQ_PRIORITY 10 +#define WB32_SPI_SPIS1_IRQ_PRIORITY 10 +#define WB32_SPI_SPIS2_IRQ_PRIORITY 10 + +/* + * ST driver system settings. + */ +#define WB32_ST_IRQ_PRIORITY 8 +#define WB32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define WB32_UART_USE_UART1 FALSE +#define WB32_UART_USE_UART2 FALSE +#define WB32_UART_USE_UART3 FALSE +#define WB32_UART_UART1_IRQ_PRIORITY 12 +#define WB32_UART_UART2_IRQ_PRIORITY 12 +#define WB32_UART_UART3_IRQ_PRIORITY 12 + +/* + * USB driver system settings. + */ +#define WB32_USB_USE_USB1 TRUE +#define WB32_USB_USB1_IRQ_PRIORITY 13 +#define WB32_USB_HOST_WAKEUP_DURATION 10 + +/* + * ADC driver system settings. + */ +#define WB32_ADC_USE_ADC1 FALSE +#define WB32_ADC_ADC1_DMA_PRIORITY 2 +#define WB32_ADC_ADC1_IRQ_PRIORITY 6 + +#endif /* MCUCONF_H */ diff --git a/demos/WB32/RT-WB32F3G71-RTC/debug.c b/demos/WB32/RT-WB32F3G71-RTC/debug.c new file mode 100644 index 0000000000..bb2933b16c --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/debug.c @@ -0,0 +1,36 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "debug.h" + +#define SERIAL_DEBUG_DRIVER SD1 +#define SERIAL_DEBUG_BAUND 115200 +#define SERIAL_DEBUG_TX_PIN PAL_LINE(GPIOA, 9U) +#define SERIAL_DEBUG_RX_PIN PAL_LINE(GPIOA, 10U) +#define SERIAL_DEBUG_TX_PAL_MODE 7 +#define SERIAL_DEBUG_RX_PAL_MODE 7 + +static SerialConfig serialConfig = {SERIAL_DEBUG_BAUND, 3, 0, 0, 0}; + +void serial_debug_init(void) { + + serialConfig.speed = SERIAL_DEBUG_BAUND; + palSetPadMode(PAL_PORT(SERIAL_DEBUG_TX_PIN), PAL_PAD(SERIAL_DEBUG_TX_PIN),PAL_MODE_ALTERNATE(SERIAL_DEBUG_TX_PAL_MODE) | PAL_WB32_PUPDR_PULLUP | PAL_WB32_OSPEED_HIGH); + palSetPadMode(PAL_PORT(SERIAL_DEBUG_RX_PIN), PAL_PAD(SERIAL_DEBUG_RX_PIN),PAL_MODE_ALTERNATE(SERIAL_DEBUG_RX_PAL_MODE) | PAL_WB32_PUPDR_PULLUP | PAL_WB32_OSPEED_HIGH); + + sdStart(&SERIAL_DEBUG_DRIVER, &serialConfig); +} + diff --git a/demos/WB32/RT-WB32F3G71-RTC/debug.h b/demos/WB32/RT-WB32F3G71-RTC/debug.h new file mode 100644 index 0000000000..12e35b6127 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/debug.h @@ -0,0 +1,25 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#pragma once + +#include +#include + +#define SERIAL_DEBUG_DRIVER SD1 + +void serial_debug_init(void); + diff --git a/demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvoptx b/demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvoptx new file mode 100644 index 0000000000..72563be4aa --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvoptx @@ -0,0 +1,2478 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\;..\cfg;..\..\..\..\..\ChibiOS\os\license;..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32F3G71xx;..\..\..\..\..\ChibiOS\os\common\ext\ARM\CMSIS\Core\Include;..\..\..\..\..\ChibiOS-Contrib\os\common\ext\CMSIS\WB32\WB32F3G71xx;..\..\..\..\..\ChibiOS\os\common\portability\Keil;..\..\..\..\..\ChibiOS\os\common\ports\ARM-common;..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M;..\..\..\..\..\ChibiOS\os\rt\include;..\..\..\..\..\ChibiOS\os\oslib\include;..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil;..\..\..\..\..\ChibiOS\os\hal\include;..\board;..\..\..\..\..\ChibiOS\os\hal\ports\common\ARMCMx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32F3G71xx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\LLD\GPIOv1;..\..\..\..\os\hal\ports\WB32\LLD\DMAv1;..\..\..\..\os\hal\ports\WB32\LLD\TIMv1;..\..\..\..\..\ChibiOS\os\test\include;..\..\..\..\..\ChibiOS\test\rt\source\test;..\..\..\..\..\ChibiOS\test\oslib\source\test;..\..\..\..\os\hal\ports\WB32\LLD\RTCv1;..\..\..\..\os\hal\ports\WB32\LLD\UARTv1;..\..\..\..\..\ChibiOS\os\hal\templates;..\..\..\..\os\hal\include;..\..\..\..\os\hal\ports\WB32\LLD\EXTIv1;..\..\..\..\..\ChibiOS\os\common\lib\include;..\..\..\..\..\ChibiOS\os\common\oop\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc --cpreproc_opts=-DCORTEX_USE_FPU=0 + + + ..\;..\cfg;..\..\..\..\..\ChibiOS\os\license;..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32F3G71xx;..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M;..\board + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + license + + + chcustomer.h + 5 + ..\..\..\..\..\ChibiOS\os\license\chcustomer.h + + + chlicense.h + 5 + ..\..\..\..\..\ChibiOS\os\license\chlicense.h + + + chversion.h + 5 + ..\..\..\..\..\ChibiOS\os\license\chversion.h + + + + + startup + + + cstartup.s + 2 + ..\..\..\..\..\ChibiOS\os\common\startup\ARMCMx\compilers\RVCT\cstartup.s + + + vectors.s + 2 + ..\..\..\..\..\ChibiOS\os\common\startup\ARMCMx\compilers\RVCT\vectors.s + + + cmparams.h + 5 + ..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32F3G71xx\cmparams.h + + + + + cmsis + + + core_cm3.h + 5 + ..\..\..\..\..\ChibiOS\os\common\ext\ARM\CMSIS\Core\Include\core_cm3.h + + + wb32f3g71xx.h + 5 + ..\..\..\..\..\ChibiOS-Contrib\os\common\ext\CMSIS\WB32\WB32F3G71xx\wb32f3g71xx.h + + + + + kernel port + + + chcore.c + 1 + ..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M\chcore.c + + + chcore.h + 5 + ..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M\chcore.h + + + mpu.h + 5 + ..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M\mpu.h + + + chcoreasm.s + 2 + ..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M\compilers\RVCT\chcoreasm.s + + + + + kernel + + + chalign.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chalign.h + + + ch.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\ch.h + + + chcond.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chcond.h + + + chdebug.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chevents.h + + + chmsg.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chmtx.h + + + chregistry.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chregistry.h + + + chschd.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chschd.h + + + chsem.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chsem.h + + + chstats.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chstats.h + + + chsys.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chsys.h + + + chthreads.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chthreads.h + + + chtm.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chtm.h + + + chvt.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chvt.h + + + chcond.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chcond.c + + + chdebug.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chevents.c + + + chmsg.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chmtx.c + + + chregistry.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chregistry.c + + + chschd.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chschd.c + + + chsem.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chsem.c + + + chstats.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chstats.c + + + chsys.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chsys.c + + + chthreads.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chthreads.c + + + chtm.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chtm.c + + + chvt.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chvt.c + + + chrfcu.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chrfcu.c + + + chinstances.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chinstances.c + + + chchecks.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chchecks.h + + + chtrace.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chtrace.h + + + chtrace.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chtrace.c + + + chrestrictions.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chrestrictions.h + + + chtime.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chtime.h + + + + + oslib + + + chbsem.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chbsem.h + + + chdelegates.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chdelegates.h + + + chfactory.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chfactory.h + + + chjobs.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chjobs.h + + + chlib.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chlib.h + + + chmboxes.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chmemcore.h + + + chmemheaps.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chmemheaps.h + + + chmempools.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chmempools.h + + + chobjcaches.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chobjcaches.h + + + chobjfifos.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chobjfifos.h + + + chpipes.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chpipes.h + + + chdelegates.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chdelegates.c + + + chfactory.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chfactory.c + + + chmboxes.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmemcore.c + + + chmemheaps.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmemheaps.c + + + chmempools.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmempools.c + + + chobjcaches.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chobjcaches.c + + + chpipes.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chpipes.c + + + chmemchecks.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmemchecks.c + + + + + osal + + + osal.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil\osal.c + + + osal.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil\osal.h + + + + + hal + + + hal.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal.h + + + hal_adc.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_adc.h + + + hal_buffers.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_buffers.h + + + hal_can.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_can.h + + + hal_channels.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_channels.h + + + hal_dac.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_dac.h + + + hal_files.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_files.h + + + hal_gpt.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_gpt.h + + + hal_i2c.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_i2c.h + + + hal_i2s.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_i2s.h + + + hal_icu.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_icu.h + + + hal_ioblock.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_ioblock.h + + + hal_mac.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_mac.h + + + hal_mii.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_mii.h + + + hal_mmc_spi.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_mmc_spi.h + + + hal_mmcsd.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_mmcsd.h + + + hal_pal.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_pal.h + + + hal_pwm.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_pwm.h + + + hal_queues.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_queues.h + + + hal_rtc.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_rtc.h + + + hal_sdc.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_sdc.h + + + hal_serial.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_serial.h + + + hal_serial_usb.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_serial_usb.h + + + hal_spi.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_spi.h + + + hal_st.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_st.h + + + hal_streams.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_streams.h + + + hal_uart.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_uart.h + + + hal_usb.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_usb.h + + + hal_usb_cdc.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_usb_cdc.h + + + hal_wdg.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_wdg.h + + + hal.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal.c + + + hal_adc.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_adc.c + + + hal_buffers.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_buffers.c + + + hal_can.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_can.c + + + hal_dac.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_dac.c + + + hal_gpt.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_gpt.c + + + hal_i2c.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_i2c.c + + + hal_i2s.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_i2s.c + + + hal_icu.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_icu.c + + + hal_mac.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_mac.c + + + hal_mmc_spi.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_mmc_spi.c + + + hal_mmcsd.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_mmcsd.c + + + hal_pal.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_pal.c + + + hal_pwm.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_pwm.c + + + hal_queues.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_queues.c + + + hal_rtc.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_rtc.c + + + hal_sdc.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_sdc.c + + + hal_serial.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_serial.c + + + hal_serial_usb.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_serial_usb.c + + + hal_spi.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_spi.c + + + hal_st.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_st.c + + + hal_uart.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_uart.c + + + hal_usb.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_usb.c + + + hal_wdg.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_wdg.c + + + hal_crypto.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_crypto.h + + + hal_efl.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_efl.h + + + hal_flash.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_flash.h + + + hal_objects.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_objects.h + + + hal_persistent.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_persistent.h + + + hal_sio.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_sio.h + + + hal_trng.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_trng.h + + + hal_wspi.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_wspi.h + + + hal_crypto.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_crypto.c + + + hal_efl.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_efl.c + + + hal_flash.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_flash.c + + + hal_sio.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_sio.c + + + hal_trng.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_trng.c + + + hal_wspi.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_wspi.c + + + + + hal_port + + + hal_pal_lld.c + 1 + ..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\LLD\GPIOv1\hal_pal_lld.c + + + hal_lld.c + 1 + ..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32F3G71xx\hal_lld.c + + + wb32_isr.c + 1 + ..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32F3G71xx\wb32_isr.c + + + nvic.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\ports\common\ARMCMx\nvic.c + + + hal_st_lld.c + 1 + ..\..\..\..\os\hal\ports\WB32\LLD\TIMv1\hal_st_lld.c + + + hal_rtc_lld.c + 1 + ..\..\..\..\os\hal\ports\WB32\LLD\RTCv1\hal_rtc_lld.c + + + hal_serial_lld.c + 1 + ..\..\..\..\os\hal\ports\WB32\LLD\UARTv1\hal_serial_lld.c + + + wb32_exti.c + 1 + ..\..\..\..\os\hal\ports\WB32\LLD\EXTIv1\wb32_exti.c + + + + + board + + + board.c + 1 + ..\board\board.c + + + board.h + 5 + ..\board\board.h + + + + + test + + + rt_test_root.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_root.c + + + rt_test_sequence_001.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_001.c + + + rt_test_sequence_002.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_002.c + + + rt_test_sequence_003.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_003.c + + + rt_test_sequence_004.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_004.c + + + rt_test_sequence_005.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_005.c + + + rt_test_sequence_006.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_006.c + + + rt_test_sequence_007.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_007.c + + + rt_test_sequence_008.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_008.c + + + rt_test_sequence_009.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_009.c + + + rt_test_sequence_010.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_010.c + + + rt_test_sequence_011.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_011.c + + + rt_test_sequence_012.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_012.c + + + oslib_test_root.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_root.c + + + oslib_test_sequence_001.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_001.c + + + oslib_test_sequence_002.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_002.c + + + oslib_test_sequence_003.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_003.c + + + oslib_test_sequence_004.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_004.c + + + oslib_test_sequence_005.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_005.c + + + oslib_test_sequence_006.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_006.c + + + oslib_test_sequence_007.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_007.c + + + oslib_test_sequence_008.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_008.c + + + oslib_test_sequence_009.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_009.c + + + ch_test.c + 1 + ..\..\..\..\..\ChibiOS\os\test\src\ch_test.c + + + ch_test_printf.c + 1 + ..\..\..\..\..\ChibiOS\os\test\src\ch_test_printf.c + + + + + demo + + + main.c + 1 + ..\main.c + + + chconf.h + 5 + ..\cfg\chconf.h + + + halconf.h + 5 + ..\cfg\halconf.h + + + mcuconf.h + 5 + ..\cfg\mcuconf.h + + + debug.c + 1 + ..\debug.c + + + chprintf.c + 1 + ..\..\..\..\..\ChibiOS\os\common\lib\src\chprintf.c + + + memstreams.c + 1 + ..\..\..\..\..\ChibiOS\os\common\lib\src\memstreams.c + + + oop_base_object.c + 1 + ..\..\..\..\..\ChibiOS\os\common\oop\src\oop_base_object.c + + + + + + + + + + + + + + diff --git a/demos/WB32/RT-WB32F3G71-RTC/main.c b/demos/WB32/RT-WB32F3G71-RTC/main.c new file mode 100644 index 0000000000..534b0f94c2 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/main.c @@ -0,0 +1,236 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "debug.h" +#include "chprintf.h" + +#define PORTAB_LINE_LED1 PAL_LINE(GPIOB, 14U) +#define PORTAB_LINE_LED2 PAL_LINE(GPIOB, 13U) +#define PORTAB_LED_OFF PAL_HIGH +#define PORTAB_LED_ON AL_LOW +#define RTC_ALARMPERIOD 10 +#define TEST_ALARM_WAKEUP TRUE + +RTCDateTime timespec; +RTCAlarm alarmspec; + +extern void __early_init(void); + +#if TEST_ALARM_WAKEUP + +static const uint32_t pre_lp_code[] = {553863175u,554459777u,1208378049u,4026624001u,688390415u,554227969u,3204472833u,1198571264u,1073807360u,1073808388u}; +#define PRE_LP() ((void(*)(void))((unsigned int)(pre_lp_code) | 0x01))() + +static const uint32_t post_lp_code[] = {553863177u,554459777u,1208509121u,51443856u,4026550535u,1745485839u,3489677954u,536895496u,673389632u,1198578684u,1073807360u,536866816u,1073808388u}; +#define POST_LP() ((void(*)(void))((unsigned int)(post_lp_code) | 0x01))() + +static void stop_mode_entry(void) { + + EXTI->PR = 0x7FFFF; + for (uint8_t i = 0; i < 8; i++) { + for (uint8_t j = 0; j < 32; j++) { + if (NVIC->ISPR[i] & (0x01UL < j)) { + NVIC->ICPR[i] = (0x01UL < j); + } + } + } + SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk; // Clear Systick IRQ Pending + + /* Clear all bits except DBP and FCLKSD bit */ + PWR->CR0 &= 0x09U; + + /* STOP LP4 MODE S32KON */ + PWR->CR0 |= 0x3B004U; + PWR->CFGR = 0x3B3; + + PRE_LP(); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Request Wait For Interrupt */ + __WFI(); + + POST_LP(); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (~SCB_SCR_SLEEPDEEP_Msk); +} + +/* + * Running indicator thread. + */ +static THD_WORKING_AREA(blinkWA, 128); +static THD_FUNCTION(blink_thd, arg) { + (void)arg; + while (true) { + chThdSleepMilliseconds(100); + palToggleLine(PORTAB_LINE_LED2); + } +} + +static void my_cb(RTCDriver *rtcp, rtcevent_t event) { + + (void)rtcp; + + switch (event) { + case RTC_EVENT_OVERFLOW: break; + case RTC_EVENT_SECOND: { + palToggleLine(PORTAB_LINE_LED1); + } break; + case RTC_EVENT_ALARM: { + osalSysLockFromISR(); + NVIC_DisableIRQ(RTCAlarm_IRQn); + osalSysUnlockFromISR(); + } break; + } +} + +int main(void) { + + uint32_t tv_sec; + + halInit(); + chSysInit(); + + serial_debug_init(); + + /* + * Init LED port and pad. + */ + palSetPadMode(PAL_PORT(PORTAB_LINE_LED1), PAL_PAD(PORTAB_LINE_LED1), PAL_WB32_MODE_OUTPUT | PAL_WB32_OTYPE_PUSHPULL); + palSetPadMode(PAL_PORT(PORTAB_LINE_LED2), PAL_PAD(PORTAB_LINE_LED2), PAL_WB32_MODE_OUTPUT | PAL_WB32_OTYPE_PUSHPULL); + + chThdCreateStatic(blinkWA, sizeof(blinkWA), NORMALPRIO, blink_thd, NULL); + + while (true){ + chThdSleepSeconds(2); + rtcGetTime(&RTCD1, ×pec); + chprintf((BaseSequentialStream *)&SERIAL_DEBUG_DRIVER, + "lsi sleep %ds year = %d month = %d dstflag=%d dayofweek = %d day = %d millisecond = %d\r\n", + RTC_ALARMPERIOD, timespec.year, timespec.month, timespec.dstflag, timespec.dayofweek, timespec.day, timespec.millisecond); + chThdSleepSeconds(3); + + chSysDisable(); + wb32_set_main_clock_to_mhsi(); + + rtclp_lld_init(); + rtcSetCallback(&RTCD1, my_cb); + rtcWB32GetSecMsec(&RTCD1, &tv_sec, NULL); + alarmspec.tv_sec = tv_sec + RTC_ALARMPERIOD; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + NVIC_EnableIRQ(RTCAlarm_IRQn); + + stop_mode_entry(); + + /* Recovery clock */ + __early_init(); + rtc_lld_init(); + rccEnableEXTI(); + rccEnableUART1(); + rtcSetCallback(&RTCD1, my_cb); + + chSysEnable(); + } +} + +#else /* TEST_ALARM_WAKEUP */ + +binary_semaphore_t alarm_sem; + +/* + * Alarm callback. + */ +static void my_cb(RTCDriver *rtcp, rtcevent_t event) { + + (void)rtcp; + + switch (event) { + case RTC_EVENT_OVERFLOW: break; + case RTC_EVENT_SECOND: { + palToggleLine(PORTAB_LINE_LED2); + } break; + case RTC_EVENT_ALARM: { + palToggleLine(PORTAB_LINE_LED1); + osalSysLockFromISR(); + chBSemSignalI(&alarm_sem); + osalSysUnlockFromISR(); + } break; + } +} + +static time_measurement_t sett, gett; + +int main(void) { + + msg_t status = MSG_TIMEOUT; + uint32_t tv_sec; + + halInit(); + chSysInit(); + + /* + * Init LED port and pad. + */ + palSetPadMode(PAL_PORT(PORTAB_LINE_LED1), PAL_PAD(PORTAB_LINE_LED1), PAL_WB32_MODE_OUTPUT | PAL_WB32_OTYPE_PUSHPULL); + palSetPadMode(PAL_PORT(PORTAB_LINE_LED2), PAL_PAD(PORTAB_LINE_LED2), PAL_WB32_MODE_OUTPUT | PAL_WB32_OTYPE_PUSHPULL); + + chBSemObjectInit(&alarm_sem, TRUE); + chTMObjectInit(&sett); + chTMObjectInit(&gett); + + /* compile ability test */ + chTMStartMeasurementX(&gett); + rtcGetTime(&RTCD1, ×pec); + chTMStopMeasurementX(&gett); + + rtcWB32SetSec(&RTCD1, 1414845464); + osalThreadSleepMilliseconds(10); + rtcGetTime(&RTCD1, ×pec); + timespec.month -= 1; + + chTMStartMeasurementX(&sett); + rtcSetTime(&RTCD1, ×pec); + chTMStopMeasurementX(&sett); + osalThreadSleepMilliseconds(10); + + rtcGetTime(&RTCD1, ×pec); + + rtcWB32GetSecMsec(&RTCD1, &tv_sec, NULL); + alarmspec.tv_sec = tv_sec + RTC_ALARMPERIOD; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + + rtcSetCallback(&RTCD1, my_cb); + + while (true){ + /* Wait until alarm callback signaled semaphore.*/ + status = chBSemWaitTimeout(&alarm_sem, TIME_S2I(RTC_ALARMPERIOD + 5)); + + if (status == MSG_TIMEOUT){ + osalSysHalt("time is out"); + } else { + rtcWB32GetSecMsec(&RTCD1, &tv_sec, NULL); + alarmspec.tv_sec = tv_sec + RTC_ALARMPERIOD; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + } + } +} +#endif /* TEST_ALARM_WAKEUP */ + + + diff --git a/demos/WB32/RT-WB32F3G71-RTC/readme.md b/demos/WB32/RT-WB32F3G71-RTC/readme.md new file mode 100644 index 0000000000..78d9433f55 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/readme.md @@ -0,0 +1,4 @@ +# WB32F3G71xx Serial MCU Demo + +This is an example. + diff --git a/demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h b/demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h index a24a1e9543..2e00d1eb1b 100644 --- a/demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h +++ b/demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h @@ -123,12 +123,12 @@ /* * SERIAL driver system settings. */ -#define WB32_SERIAL_USE_UART1 FALSE -#define WB32_SERIAL_USE_UART2 FALSE -#define WB32_SERIAL_USE_UART3 FALSE -#define WB32_SERIAL_USART1_PRIORITY 12 -#define WB32_SERIAL_USART2_PRIORITY 12 -#define WB32_SERIAL_USART3_PRIORITY 12 +#define WB32_SERIAL_USE_UART1 FALSE +#define WB32_SERIAL_USE_UART2 FALSE +#define WB32_SERIAL_USE_UART3 FALSE +#define WB32_SERIAL_UART1_PRIORITY 12 +#define WB32_SERIAL_UART2_PRIORITY 12 +#define WB32_SERIAL_UART3_PRIORITY 12 /* * SPI driver system settings. diff --git a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx index 9adafd96d1..fac19b7670 100644 --- a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx +++ b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx @@ -1062,6 +1062,18 @@ 0 0 + + 6 + 70 + 1 + 0 + 0 + 0 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmemchecks.c + chmemchecks.c + 0 + 0 + @@ -1072,7 +1084,7 @@ 0 7 - 70 + 71 1 0 0 @@ -1084,7 +1096,7 @@ 7 - 71 + 72 5 0 0 @@ -1104,7 +1116,7 @@ 0 8 - 72 + 73 5 0 0 @@ -1116,7 +1128,7 @@ 8 - 73 + 74 5 0 0 @@ -1128,7 +1140,7 @@ 8 - 74 + 75 5 0 0 @@ -1140,7 +1152,7 @@ 8 - 75 + 76 5 0 0 @@ -1152,7 +1164,7 @@ 8 - 76 + 77 5 0 0 @@ -1164,7 +1176,7 @@ 8 - 77 + 78 5 0 0 @@ -1176,7 +1188,7 @@ 8 - 78 + 79 5 0 0 @@ -1188,7 +1200,7 @@ 8 - 79 + 80 5 0 0 @@ -1200,7 +1212,7 @@ 8 - 80 + 81 5 0 0 @@ -1212,7 +1224,7 @@ 8 - 81 + 82 5 0 0 @@ -1224,7 +1236,7 @@ 8 - 82 + 83 5 0 0 @@ -1236,7 +1248,7 @@ 8 - 83 + 84 5 0 0 @@ -1248,7 +1260,7 @@ 8 - 84 + 85 5 0 0 @@ -1260,7 +1272,7 @@ 8 - 85 + 86 5 0 0 @@ -1272,7 +1284,7 @@ 8 - 86 + 87 5 0 0 @@ -1284,7 +1296,7 @@ 8 - 87 + 88 5 0 0 @@ -1296,7 +1308,7 @@ 8 - 88 + 89 5 0 0 @@ -1308,7 +1320,7 @@ 8 - 89 + 90 5 0 0 @@ -1320,7 +1332,7 @@ 8 - 90 + 91 5 0 0 @@ -1332,7 +1344,7 @@ 8 - 91 + 92 5 0 0 @@ -1344,7 +1356,7 @@ 8 - 92 + 93 5 0 0 @@ -1356,7 +1368,7 @@ 8 - 93 + 94 5 0 0 @@ -1368,7 +1380,7 @@ 8 - 94 + 95 5 0 0 @@ -1380,7 +1392,7 @@ 8 - 95 + 96 5 0 0 @@ -1392,7 +1404,7 @@ 8 - 96 + 97 5 0 0 @@ -1404,7 +1416,7 @@ 8 - 97 + 98 5 0 0 @@ -1416,7 +1428,7 @@ 8 - 98 + 99 5 0 0 @@ -1428,7 +1440,7 @@ 8 - 99 + 100 5 0 0 @@ -1440,7 +1452,7 @@ 8 - 100 + 101 5 0 0 @@ -1452,7 +1464,7 @@ 8 - 101 + 102 5 0 0 @@ -1464,7 +1476,7 @@ 8 - 102 + 103 1 0 0 @@ -1476,7 +1488,7 @@ 8 - 103 + 104 1 0 0 @@ -1488,7 +1500,7 @@ 8 - 104 + 105 1 0 0 @@ -1500,7 +1512,7 @@ 8 - 105 + 106 1 0 0 @@ -1512,7 +1524,7 @@ 8 - 106 + 107 1 0 0 @@ -1524,7 +1536,7 @@ 8 - 107 + 108 1 0 0 @@ -1536,7 +1548,7 @@ 8 - 108 + 109 1 0 0 @@ -1548,7 +1560,7 @@ 8 - 109 + 110 1 0 0 @@ -1560,7 +1572,7 @@ 8 - 110 + 111 1 0 0 @@ -1572,7 +1584,7 @@ 8 - 111 + 112 1 0 0 @@ -1584,7 +1596,7 @@ 8 - 112 + 113 1 0 0 @@ -1596,7 +1608,7 @@ 8 - 113 + 114 1 0 0 @@ -1608,7 +1620,7 @@ 8 - 114 + 115 1 0 0 @@ -1620,7 +1632,7 @@ 8 - 115 + 116 1 0 0 @@ -1632,7 +1644,7 @@ 8 - 116 + 117 1 0 0 @@ -1644,7 +1656,7 @@ 8 - 117 + 118 1 0 0 @@ -1656,7 +1668,7 @@ 8 - 118 + 119 1 0 0 @@ -1668,7 +1680,7 @@ 8 - 119 + 120 1 0 0 @@ -1680,7 +1692,7 @@ 8 - 120 + 121 1 0 0 @@ -1692,7 +1704,7 @@ 8 - 121 + 122 1 0 0 @@ -1704,7 +1716,7 @@ 8 - 122 + 123 1 0 0 @@ -1716,7 +1728,7 @@ 8 - 123 + 124 1 0 0 @@ -1728,7 +1740,7 @@ 8 - 124 + 125 1 0 0 @@ -1740,7 +1752,7 @@ 8 - 125 + 126 1 0 0 @@ -1752,7 +1764,7 @@ 8 - 126 + 127 5 0 0 @@ -1764,7 +1776,7 @@ 8 - 127 + 128 5 0 0 @@ -1776,7 +1788,7 @@ 8 - 128 + 129 5 0 0 @@ -1788,7 +1800,7 @@ 8 - 129 + 130 5 0 0 @@ -1800,7 +1812,7 @@ 8 - 130 + 131 5 0 0 @@ -1812,7 +1824,7 @@ 8 - 131 + 132 5 0 0 @@ -1824,7 +1836,7 @@ 8 - 132 + 133 5 0 0 @@ -1836,7 +1848,7 @@ 8 - 133 + 134 5 0 0 @@ -1848,7 +1860,7 @@ 8 - 134 + 135 1 0 0 @@ -1860,7 +1872,7 @@ 8 - 135 + 136 1 0 0 @@ -1872,7 +1884,7 @@ 8 - 136 + 137 1 0 0 @@ -1884,7 +1896,7 @@ 8 - 137 + 138 1 0 0 @@ -1896,7 +1908,7 @@ 8 - 138 + 139 1 0 0 @@ -1908,7 +1920,7 @@ 8 - 139 + 140 1 0 0 @@ -1928,7 +1940,7 @@ 0 9 - 140 + 141 1 0 0 @@ -1940,7 +1952,7 @@ 9 - 141 + 142 1 0 0 @@ -1952,7 +1964,7 @@ 9 - 142 + 143 1 0 0 @@ -1964,7 +1976,7 @@ 9 - 143 + 144 1 0 0 @@ -1976,7 +1988,7 @@ 9 - 144 + 145 1 0 0 @@ -1996,7 +2008,7 @@ 0 10 - 145 + 146 1 0 0 @@ -2008,7 +2020,7 @@ 10 - 146 + 147 5 0 0 @@ -2028,7 +2040,7 @@ 0 11 - 147 + 148 1 0 0 @@ -2040,7 +2052,7 @@ 11 - 148 + 149 1 0 0 @@ -2052,7 +2064,7 @@ 11 - 149 + 150 1 0 0 @@ -2064,7 +2076,7 @@ 11 - 150 + 151 1 0 0 @@ -2076,7 +2088,7 @@ 11 - 151 + 152 1 0 0 @@ -2088,7 +2100,7 @@ 11 - 152 + 153 1 0 0 @@ -2100,7 +2112,7 @@ 11 - 153 + 154 1 0 0 @@ -2112,7 +2124,7 @@ 11 - 154 + 155 1 0 0 @@ -2124,7 +2136,7 @@ 11 - 155 + 156 1 0 0 @@ -2136,7 +2148,7 @@ 11 - 156 + 157 1 0 0 @@ -2148,7 +2160,7 @@ 11 - 157 + 158 1 0 0 @@ -2160,7 +2172,7 @@ 11 - 158 + 159 1 0 0 @@ -2172,7 +2184,7 @@ 11 - 159 + 160 1 0 0 @@ -2184,7 +2196,7 @@ 11 - 160 + 161 1 0 0 @@ -2196,7 +2208,7 @@ 11 - 161 + 162 1 0 0 @@ -2208,7 +2220,7 @@ 11 - 162 + 163 1 0 0 @@ -2220,7 +2232,7 @@ 11 - 163 + 164 1 0 0 @@ -2232,7 +2244,7 @@ 11 - 164 + 165 1 0 0 @@ -2244,7 +2256,7 @@ 11 - 165 + 166 1 0 0 @@ -2256,7 +2268,7 @@ 11 - 166 + 167 1 0 0 @@ -2268,7 +2280,7 @@ 11 - 167 + 168 1 0 0 @@ -2280,7 +2292,7 @@ 11 - 168 + 169 1 0 0 @@ -2292,7 +2304,7 @@ 11 - 169 + 170 1 0 0 @@ -2304,7 +2316,7 @@ 11 - 170 + 171 1 0 0 @@ -2316,7 +2328,7 @@ 11 - 171 + 172 1 0 0 @@ -2336,7 +2348,7 @@ 0 12 - 172 + 173 1 0 0 @@ -2348,7 +2360,7 @@ 12 - 173 + 174 5 0 0 @@ -2360,7 +2372,7 @@ 12 - 174 + 175 5 0 0 @@ -2372,7 +2384,7 @@ 12 - 175 + 176 5 0 0 diff --git a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx index 7947c2040b..f182a7e70c 100644 --- a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx +++ b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx @@ -15,7 +15,7 @@ ARMCM3 ARM - ARM.CMSIS.5.6.0 + ARM.CMSIS.5.1.1 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE @@ -32,7 +32,7 @@ - + $$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd 0 0 @@ -335,7 +335,7 @@ -UWB32FQ95xx CORTEX_USE_FPU=0 TEST_CFG_SIZE_REPORT=0 __heap_base__=Image$$$$RW_IRAM1$$$$ZI$$$$Limit __heap_end__=Image$$$$RW_IRAM1$$$$Base - ..\;..\cfg;..\..\..\..\..\ChibiOS\os\license;..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\ext\ARM\CMSIS\Core\Include;..\..\..\..\..\ChibiOS-Contrib\os\common\ext\CMSIS\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\portability\Keil;..\..\..\..\..\ChibiOS\os\common\ports\ARM-common;..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M;..\..\..\..\..\ChibiOS\os\rt\include;..\..\..\..\..\ChibiOS\os\oslib\include;..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil;..\..\..\..\..\ChibiOS\os\hal\include;..\board;..\..\..\..\..\ChibiOS\os\hal\ports\common\ARMCMx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\LLD\GPIOv1;..\..\..\..\os\hal\ports\WB32\LLD\DMAv1;..\..\..\..\os\hal\ports\WB32\LLD\TIMv1;..\..\..\..\..\ChibiOS\os\test\include;..\..\..\..\..\ChibiOS\test\rt\source\test;..\..\..\..\..\ChibiOS\test\oslib\source\test + ..\;..\cfg;..\..\..\..\..\ChibiOS\os\license;..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\ext\ARM\CMSIS\Core\Include;..\..\..\..\..\ChibiOS-Contrib\os\common\ext\CMSIS\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\portability\Keil;..\..\..\..\..\ChibiOS\os\common\ports\ARM-common;..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M;..\..\..\..\..\ChibiOS\os\rt\include;..\..\..\..\..\ChibiOS\os\oslib\include;..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil;..\..\..\..\..\ChibiOS\os\hal\include;..\board;..\..\..\..\..\ChibiOS\os\hal\ports\common\ARMCMx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\LLD\GPIOv1;..\..\..\..\os\hal\ports\WB32\LLD\DMAv1;..\..\..\..\os\hal\ports\WB32\LLD\TIMv1;..\..\..\..\..\ChibiOS\os\test\include;..\..\..\..\..\ChibiOS\test\rt\source\test;..\..\..\..\..\ChibiOS\test\oslib\source\test;..\..\..\..\os\hal\ports\WB32\LLD\EXTIv1 @@ -749,6 +749,11 @@ 1 ..\..\..\..\..\ChibiOS\os\oslib\src\chpipes.c + + chmemchecks.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmemchecks.c + diff --git a/os/hal/ports/WB32/LLD/EXTIv1/driver.mk b/os/hal/ports/WB32/LLD/EXTIv1/driver.mk new file mode 100644 index 0000000000..317b621071 --- /dev/null +++ b/os/hal/ports/WB32/LLD/EXTIv1/driver.mk @@ -0,0 +1,2 @@ +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/EXTIv1 diff --git a/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c b/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c new file mode 100644 index 0000000000..a30a4e9700 --- /dev/null +++ b/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c @@ -0,0 +1,145 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXTIv1/WB32_exti.c + * @brief EXTI helper driver code. + * + * @addtogroup WB32_EXTI + * @details EXTI sharing helper driver. + * @{ + */ + +#include "hal.h" + +/* The following macro is only defined if some driver requiring EXTI services + has been enabled.*/ +#if defined(WB32_EXTI_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief WB32 EXTI group 1 lines initialization. + * + * @param[in] mask mask of group 1 lines to be initialized + * @param[in] mode initialization mode + * + * @api + */ +void extiEnable(uint32_t mask, extimode_t mode) { + uint32_t cmask; + /* Enable EXTI clock.*/ + rccEnableEXTI(); + + /* Mask including only configurable lines.*/ + cmask = mask & ~WB32_EXTI_IMR1_MASK; + + if ((mode & EXTI_MODE_EDGES_MASK) == 0U) { + /* Disabling channels.*/ + EXTI->IMR &= ~mask; + EXTI->EMR &= ~mask; + EXTI->RTSR &= ~cmask; + EXTI->FTSR &= ~cmask; + EXTI->PR = cmask; + } else { + /* Programming edge registers.*/ + if (mode & EXTI_MODE_RISING_EDGE) { + EXTI->RTSR |= cmask; + } + else { + EXTI->RTSR &= ~cmask; + } + if (mode & EXTI_MODE_FALLING_EDGE) { + EXTI->FTSR |= cmask; + } + else { + EXTI->FTSR &= ~cmask; + } + + /* Programming interrupt and event registers.*/ + if ((mode & EXTI_MODE_ACTION_MASK) == EXTI_MODE_ACTION_INTERRUPT) { + EXTI->IMR |= mask; + EXTI->EMR &= ~mask; + } + else { + EXTI->EMR |= mask; + EXTI->IMR &= ~mask; + } + } + + if ((!EXTI->IMR) && (!EXTI->EMR)) { + /* Disable EXTI clock.*/ + rccDisableEXTI(); + } +} + +/** + * @brief WB32 EXTI line initialization. + * + * @param[in] line line to be initialized + * @param[in] mode initialization mode + * + * @api + */ +void extiEnableLine(extiline_t line, extimode_t mode) { + uint32_t mask = (1U << (line & 0x1FU)); + + osalDbgCheck(line < WB32_EXTI_NUM_LINES); + osalDbgCheck((mode & ~EXTI_MODE_MASK) == 0U); + + extiEnable(mask, mode); +} + +/** + * @brief WB32 EXTI line IRQ status clearing. + * + * @param[in] line line to be initialized + * + * @api + */ +void extiClearLine(extiline_t line) { + uint32_t mask = (1U << (line & 0x1FU)); + + osalDbgCheck(line < WB32_EXTI_NUM_LINES); + + extiClear(mask); +} + +#endif /* WB32_EXTI_REQUIRED */ + +/** @} */ diff --git a/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.h b/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.h new file mode 100644 index 0000000000..7266915660 --- /dev/null +++ b/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.h @@ -0,0 +1,117 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXTIv1/WB32_exti.h + * @brief EXTI helper driver header. + * + * @addtogroup WB32_EXTI + * @{ + */ + +#ifndef WB32_EXTI_H +#define WB32_EXTI_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* EXTI attributes.*/ +#define WB32_EXTI_IMR1_MASK 0xFFF00000U + +/** + * @name EXTI channel modes + * @{ + */ +#define EXTI_MODE_MASK 7U /**< @brief Mode parameter mask. */ +#define EXTI_MODE_EDGES_MASK 3U /**< @brief Edges field mask. */ +#define EXTI_MODE_DISABLED 0U /**< @brief Channel disabled. */ +#define EXTI_MODE_RISING_EDGE 1U /**< @brief Rising edge callback. */ +#define EXTI_MODE_FALLING_EDGE 2U /**< @brief Falling edge callback. */ +#define EXTI_MODE_BOTH_EDGES 3U /**< @brief Both edges callback. */ +#define EXTI_MODE_ACTION_MASK 4U /**< @brief Action field mask. */ +#define EXTI_MODE_ACTION_INTERRUPT 0U /**< @brief Interrupt mode. */ +#define EXTI_MODE_ACTION_EVENT 4U /**< @brief Event mode. */ +/** @} */ + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(WB32_EXTI_NUM_LINES) +#error "WB32_EXTI_NUM_LINES not defined in registry" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an EXTI line identifier. + */ +typedef uint32_t extiline_t; + +/** + * @brief Type of an EXTI line mode. + */ +typedef uint32_t extimode_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief From group 1 line number to mask. + * + * @param[in] line line number in range 0..31 + */ +#define EXTI_MASK(line) (uint32_t)(1U << (line)) + +/** + * @brief WB32 EXTI group 1 IRQ status clearing. + * + * @param[in] mask mask of group 1 lines to be initialized + * + * @special + */ + +#define extiClear(mask) do { \ + osalDbgAssert(((mask) & WB32_EXTI_IMR1_MASK) == 0U, "fixed lines"); \ + EXTI->PR = (uint32_t)(mask); \ +} while (false) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void extiEnable(uint32_t mask, extimode_t mode); + void extiEnableLine(extiline_t line, extimode_t mode); + void extiClearLine(extiline_t line); + #ifdef __cplusplus +} +#endif + +#endif /* WB32_EXTI_H */ + +/** @} */ diff --git a/os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c index 9273cee265..06ed87a9a9 100644 --- a/os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c +++ b/os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c @@ -114,7 +114,7 @@ static void i2c_lld_configuration(I2CDriver *i2cp) { osalDbgCheck((i2cp != NULL) && (clock_speed > 0) && - (clock_speed <= 400000)); + (clock_speed <= 3400000)); con_reg = I2C_CON_SLAVE_DISABLE | I2C_CON_RESTART_EN | I2C_CON_MASTER_MODE; @@ -149,6 +149,12 @@ static void i2c_lld_configuration(I2CDriver *i2cp) { dp->FS_SCL_HCNT = (uint32_t)(tval - 7 - dp->FS_SPKLEN); dp->FS_SCL_LCNT = (uint32_t)(tval - 1); } + else if (clock_speed <= 3400000) { + con_reg |= I2C_CON_SPEED_HIGH; + dp->SDA_SETUP = (uint32_t)(WB32_PCLK2 / 1000000 * 0.01); // 10ns + dp->FS_SCL_HCNT = (uint32_t)(tval - 7 - dp->FS_SPKLEN); + dp->FS_SCL_LCNT = (uint32_t)(tval - 1); + } dp->CON = con_reg; } diff --git a/os/hal/ports/WB32/LLD/RTCv1/driver.mk b/os/hal/ports/WB32/LLD/RTCv1/driver.mk new file mode 100644 index 0000000000..55d083207b --- /dev/null +++ b/os/hal/ports/WB32/LLD/RTCv1/driver.mk @@ -0,0 +1,8 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c +endif +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/RTCv1 diff --git a/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c b/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c new file mode 100644 index 0000000000..a8e20e8819 --- /dev/null +++ b/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c @@ -0,0 +1,617 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file RTCv1/hal_rtc_lld.c + * @brief WB32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +static bool rtc_mod_flag; +static uint32_t last_rtc_cnt = 0; +/** + * @brief Initializes the backup domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BKP domain. + */ +static void hal_lld_backup_domain_init(void) { + + PWR_BackupAccessEnable(); + + rccResetBKP(); + /* Turn on the backup domain clock.*/ + rccEnableBKP(); + +#if HAL_USE_RTC + /* If enabled then the LSE is started.*/ +# if WB32_LSE_ENABLED +# if defined(WB32_LSE_BYPASS) + /* No LSE Bypass.*/ + BKP->BDCR = BKP_LSE_Bypass; +# else + /*LSE Bypass.*/ + BKP->BDCR = BKP_LSE_ON; +# endif + while ((BKP->BDCR & 0x2U) == 0) + ; /* Waits until LSE is stable. */ +# endif /* WB32_LSE_ENABLED */ + +# if WB32_RTCSEL == WB32_RTCSEL_HSEDIV + RCC->HSE2RTCENR = 1; + BKP->BDCR = (BKP->BDCR & (~(WB32_RTCSEL_MASK))) | (WB32_RTCSEL_HSEDIV); +# elif WB32_RTCSEL == WB32_RTCSEL_LSE + BKP->BDCR = (BKP->BDCR & (~(WB32_RTCSEL_MASK))) | (WB32_RTCSEL_LSE); +# elif WB32_RTCSEL == WB32_RTCSEL_LSI || WB32_RTCSEL == WB32_RTCSEL_NOCLOCK +# error 'The LSI clock cannot be used under normal use of the RTC' +# endif + + /* Prescaler value loaded in registers.*/ + rtc_lld_set_prescaler(rtc_mod_flag); + + /* RTC clock enabled.*/ + BKP->BDCR |= (1 << 15); +#endif /* HAL_USE_RTC */ + + rccDisableBKP(); +} +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief RTC driver identifier. + */ +RTCDriver RTCD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wait for synchronization of RTC registers with APB1 bus. + * @details This function must be invoked before trying to read RTC registers + * in the backup domain: DIV, CNT, ALR. CR registers can always + * be read. + * + * @notapi + */ +static void rtc_apb1_sync(void) { + + /* RSF bit must be cleared by software after an APB1 reset or an APB1 clock + stop. Otherwise its value will not be actual. */ + RTCD1.rtc->CRL &= ~RTC_CRL_RSF; + + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_CRL_RSF) == 0) + ; +} + +/** + * @brief Wait for for previous write operation complete. + * @details This function must be invoked before writing to any RTC registers + * + * @notapi + */ +static void rtc_wait_write_completed(void) { + + while ((RTC->CRL & RTC_CRL_RTOFF) == 0) + ; +} + +/** + * @brief Acquires write access to RTC registers. + * @details Before writing to the backup domain RTC registers the previous + * write operation must be completed. Use this function before + * writing to PRL, CNT, ALR registers. + * + * @notapi + */ +static void rtc_acquire_access(void) { + + rtc_wait_write_completed(); + RTC->CRL |= RTC_CRL_CNF; +} + +/** + * @brief Releases write access to RTC registers. + * + * @notapi + */ +static void rtc_release_access(void) { + + RTC->CRL &= ~RTC_CRL_CNF; +} + +/** + * @brief Converts time from timespec to seconds counter. + * + * @param[in] timespec pointer to a @p RTCDateTime structure + * @return the TR register encoding. + * + * @notapi + */ +static time_t rtc_encode(const RTCDateTime *timespec) { + struct tm tim; + + rtcConvertDateTimeToStructTm(timespec, &tim, NULL); + return mktime(&tim); +} + +/** + * @brief Converts time from seconds/milliseconds to timespec. + * + * @param[in] tv_sec seconds value + * @param[in] tv_msec milliseconds value + * @param[out] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +static void rtc_decode(uint32_t tv_sec, + uint32_t tv_msec, + RTCDateTime *timespec) { + struct tm tim; + struct tm *t; + const time_t time = (time_t)tv_sec; /* Could be 64 bits.*/ + + /* If the conversion is successful the function returns a pointer + to the object the result was written into.*/ +#if defined(__GNUC__) || defined(__CC_ARM) + t = localtime_r(&time, &tim); + osalDbgAssert(t != NULL, "conversion failed"); +#else + t = localtime(&time); + memcpy(&tim, t, sizeof(struct tm)); +#endif + + rtcConvertStructTmToDateTime(&tim, tv_msec, timespec); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief RTC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(WB32_RTCAlarm_IRQ_VECTOR) { + uint16_t flags; + + OSAL_IRQ_PROLOGUE(); + + /* Code hits this wait only when AHB1 bus was previously powered off by any + reason (standby, reset, etc). In other cases there is no waiting.*/ + rtc_apb1_sync(); + + /* Mask of all enabled and pending sources.*/ + flags = RTCD1.rtc->CRL; + RTCD1.rtc->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + + extiClearLine(WB32_RTC_ALARM_EXTI); + + if (flags & RTC_CRL_SECF) + RTCD1.callback(&RTCD1, RTC_EVENT_SECOND); + + if (flags & RTC_CRL_ALRF) + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM); + + if (flags & RTC_CRL_OWF) + RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief RTC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(WB32_RTC_IRQ_VECTOR) { + uint16_t flags; + + OSAL_IRQ_PROLOGUE(); + + /* Code hits this wait only when AHB1 bus was previously powered off by any + reason (standby, reset, etc). In other cases there is no waiting.*/ + rtc_apb1_sync(); + + /* Mask of all enabled and pending sources.*/ + flags = RTCD1.rtc->CRL; + RTCD1.rtc->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + + if (flags & RTC_CRL_SECF) + RTCD1.callback(&RTCD1, RTC_EVENT_SECOND); + + if (flags & RTC_CRL_ALRF) + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM); + + if (flags & RTC_CRL_OWF) + RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW); + + OSAL_IRQ_EPILOGUE(); +} +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Load value of RTCCLK to prescaler registers. + * @note The pre-scaler must not be set on every reset as RTC clock + * counts are lost when it is set. + * @note This function designed to be called from + * hal_lld_backup_domain_init(). Because there is only place + * where possible to detect BKP domain reset event reliably. + * + * @notapi + */ +void rtc_lld_set_prescaler(bool rtc_mod) { + syssts_t sts; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + rtc_acquire_access(); + if (rtc_mod != true) { + RTC->PRLH = (uint16_t)((WB32_RTCCLK - 1) >> 16) & 0x000F; + RTC->PRLL = (uint16_t)(((WB32_RTCCLK - 1)) & 0xFFFF); + } else { + RTC->PRLH = (uint16_t)((WB32_RTCLPCLK - 1) >> 16) & 0x000F; + RTC->PRLL = (uint16_t)(((WB32_RTCLPCLK - 1)) & 0xFFFF); + } + rtc_release_access(); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Initialize RTC. + * + * @notapi + */ +void rtc_lld_init(void) { + + /* RTC object initialization.*/ + rtcObjectInit(&RTCD1); + + rtc_mod_flag = false; + + /* RTC pointer initialization.*/ + RTCD1.rtc = RTC; + + last_rtc_cnt = ((uint32_t)(RTCD1.rtc->CNTH) << 16) + RTCD1.rtc->CNTL; + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + + /* Required because access to PRL.*/ + rtc_apb1_sync(); + + /* All interrupts initially disabled.*/ + rtc_wait_write_completed(); + RTCD1.rtc->CRH = 0; + + /* Callback initially disabled.*/ + RTCD1.callback = NULL; + + rtcWB32SetSec(&RTCD1, last_rtc_cnt); + /* IRQ vector permanently assigned to this driver.*/ + nvicEnableVector(WB32_RTC_NUMBER, WB32_RTC_IRQ_PRIORITY); +} + +/** + * @brief Initialize RTC_LP. + * + * @notapi + */ +void rtclp_lld_init(void) { + + /* RTC object initialization.*/ + rtcObjectInit(&RTCD1); + rtc_mod_flag = true; + /* RTC pointer initialization.*/ + RTCD1.rtc = RTC; + + last_rtc_cnt = ((uint32_t)(RTCD1.rtc->CNTH) << 16) + RTCD1.rtc->CNTL; + + PWR_BackupAccessEnable(); + + rccResetBKP(); + /* Turn on the backup domain clock.*/ + rccEnableBKP(); + +#if HAL_USE_RTC +# if WB32_RTCLP_SEL == WB32_RTCSEL_LSE + /* If enabled then the LSE is started.*/ +# if WB32_LSE_ENABLED +# if defined(WB32_LSE_BYPASS) + /* No LSE Bypass.*/ + BKP->BDCR = BKP_LSE_Bypass; +# else + /*LSE Bypass.*/ + BKP->BDCR = (1 << 0); +# endif + while ((BKP->BDCR & 0x2U) == 0) + ; /* Waits until LSE is stable. */ + BKP->BDCR = (BKP->BDCR & (~(WB32_RTCSEL_MASK))) | (WB32_RTCSEL_LSE); +# endif /* WB32_LSE_ENABLED */ +# elif WB32_RTCLP_SEL == WB32_RTCSEL_LSI + RCC->LSI2RTCENR = 1; + /* Select the RTC clock source */ + BKP->BDCR = (BKP->BDCR & (~(WB32_RTCSEL_MASK))) | (WB32_RTCSEL_LSI); + + /* Prescaler value loaded in registers.*/ + rtc_lld_set_prescaler(rtc_mod_flag); +# else +# error 'The RTC LP clock is selected incorrectly' +# endif + /* RTC clock enabled.*/ + BKP->BDCR |= (1 << 15); +#endif + + rccDisableBKP(); + /* RSF bit must be cleared by software after an APB1 reset or an APB1 clock + stop. Otherwise its value will not be actual. */ + RTCD1.rtc->CRL &= ~RTC_CRL_RSF; + + /* Required because access to PRL.*/ + rtc_apb1_sync(); + + /* All interrupts initially disabled.*/ + rtc_wait_write_completed(); + + RTCD1.rtc->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF); + RTCD1.rtc->CRH = 0; + + /* Callback initially disabled.*/ + RTCD1.callback = NULL; + + rtcWB32SetSec(&RTCD1, last_rtc_cnt); + + extiEnableLine(WB32_RTC_ALARM_EXTI, EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); + + /* IRQ vector permanently assigned to this driver.*/ + nvicEnableVector(WB32_RTCAlarm_NUMBER, WB32_RTCAlarm_IRQ_PRIORITY); +} + +/** + * @brief Set current time. + * @note Fractional part will be silently ignored. There is no possibility + * to change it on STM32F1xx platform. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { + time_t tv_sec = rtc_encode(timespec); + + rtcWB32SetSec(rtcp, tv_sec); +} + +/** + * @brief Get current time. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { + uint32_t tv_sec, tv_msec; + + rtcWB32GetSecMsec(rtcp, &tv_sec, &tv_msec); + rtc_decode(tv_sec, tv_msec, timespec); +} + +/** + * @brief Set alarm time. + * + * @note Default value after BKP domain reset is 0xFFFFFFFF + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[in] alarmspec pointer to a @p RTCAlarm structure + * + * @notapi + */ +void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + const RTCAlarm *alarmspec) { + syssts_t sts; + + (void)alarm_number; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + rtc_lld_set_prescaler(rtc_mod_flag); + + rtc_acquire_access(); + if (alarmspec != NULL) { + rtcp->rtc->ALRH = (uint16_t)(alarmspec->tv_sec >> 16); + rtcp->rtc->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF); + } else { + rtcp->rtc->ALRH = 0; + rtcp->rtc->ALRL = 0; + } + rtc_release_access(); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Get current alarm. + * @note If an alarm has not been set then the returned alarm specification + * is not meaningful. + * @note The function can be called from any context. + * @note Default value after BKP domain reset is 0xFFFFFFFF. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @notapi + */ +void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + RTCAlarm *alarmspec) { + syssts_t sts; + + (void)alarm_number; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + /* Required because access to ALR.*/ + rtc_apb1_sync(); + + alarmspec->tv_sec = ((rtcp->rtc->ALRH << 16) + rtcp->rtc->ALRL); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @notapi + */ +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { + syssts_t sts; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + if (callback != NULL) { + + /* IRQ sources enabled only after setting up the callback.*/ + rtcp->callback = callback; + + rtc_wait_write_completed(); + rtcp->rtc->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF); + rtcp->rtc->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE; + } else { + rtc_wait_write_completed(); + rtcp->rtc->CRH = 0; + + /* Callback set to NULL only after disabling the IRQ sources.*/ + rtcp->callback = NULL; + } + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Get seconds and (optionally) milliseconds from RTC. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] tv_sec pointer to seconds value + * @param[out] tv_msec pointer to milliseconds value, set it + * to @p NULL if not needed + * + * @api + */ +void rtcWB32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec) { + uint32_t time_frac; + syssts_t sts; + + osalDbgCheck((NULL != tv_sec) && (NULL != rtcp)); + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + /* Required because access to CNT and DIV.*/ + rtc_apb1_sync(); + + /* wait for previous write accesses to complete.*/ + rtc_wait_write_completed(); + + /* Loops until two consecutive read returning the same value.*/ + do { + *tv_sec = ((uint32_t)(rtcp->rtc->CNTH) << 16) + rtcp->rtc->CNTL; + time_frac = (((uint32_t)rtcp->rtc->DIVH) << 16) + (uint32_t)rtcp->rtc->DIVL; + } while ((*tv_sec) != (((uint32_t)(rtcp->rtc->CNTH) << 16) + rtcp->rtc->CNTL)); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); + + if (NULL != tv_msec) + *tv_msec = (((uint32_t)WB32_RTCCLK - 1 - time_frac) * 1000) / WB32_RTCCLK; +} + +/** + * @brief Set seconds in RTC. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] tv_sec seconds value + * + * @api + */ +void rtcWB32SetSec(RTCDriver *rtcp, uint32_t tv_sec) { + syssts_t sts; + + osalDbgCheck(NULL != rtcp); + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + rtc_lld_set_prescaler(rtc_mod_flag); + + rtc_acquire_access(); + rtcp->rtc->CNTH = (uint16_t)(tv_sec >> 16); + rtcp->rtc->CNTL = (uint16_t)(tv_sec & 0xFFFF); + rtc_release_access(); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.h b/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.h new file mode 100644 index 0000000000..75bc0222f7 --- /dev/null +++ b/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.h @@ -0,0 +1,164 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file RTCv1/hal_rtc_lld.h + * @brief WB32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef HAL_RTC_LLD_H +#define HAL_RTC_LLD_H + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Implementation capabilities + */ +/** + * @brief This RTC implementation supports callbacks. + */ +#ifndef RTC_SUPPORTS_CALLBACKS +# define RTC_SUPPORTS_CALLBACKS TRUE +#endif + +/** + * @brief One alarm comparator available. + */ +#ifndef RTC_ALARMS +# define RTC_ALARMS 1 +#endif + +/** + * @brief Presence of a local persistent storage. + */ +#ifndef RTC_HAS_STORAGE +# define RTC_HAS_STORAGE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/* + * RTC driver system settings. + */ +#ifndef WB32_RTC_IRQ_PRIORITY +# define WB32_RTC_IRQ_PRIORITY 15 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !WB32_HAS_RTC +#error "RTC not present in the selected device" +#endif + +#if WB32_RTCCLK == 0 +#error "RTC clock not enabled" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_SECOND = 0, /** Triggered every second. */ + RTC_EVENT_ALARM = 1, /** Triggered on alarm. */ + RTC_EVENT_OVERFLOW = 2 /** Triggered on counter overflow. */ +} rtcevent_t; + +/** + * @brief Type of a generic RTC callback. + */ +typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); + +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct hal_rtc_alarm { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; +} RTCAlarm; + +/** + * @brief Implementation-specific @p RTCDriver fields. + */ +#define rtc_lld_driver_fields \ + /* Pointer to the RTC registers block.*/ \ + RTC_TypeDef *rtc; \ + /* Callback pointer.*/ \ + rtccb_t callback + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_set_prescaler(bool rtc_mod); + void rtc_lld_init(void); + void rtclp_lld_init(void); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec); + void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + const RTCAlarm *alarmspec); + void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + RTCAlarm *alarmspec); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); + void rtcWB32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec); + void rtcWB32SetSec(RTCDriver *rtcp, uint32_t tv_sec); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ + +#endif /* HAL_RTC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c b/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c index 740f943887..6cfb9887bc 100644 --- a/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c +++ b/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c @@ -501,6 +501,16 @@ OSAL_IRQ_HANDLER(WB32_USB1_IRQ_VECTOR) { /* SOF handling.*/ if (IntrUSB & USB_INTRUSB_SOFIS) { + + /* SOF interrupt was used to detect resume of the USB bus after issuing a + remote wake up of the host, therefore we disable it again.*/ + if (USBD1.config->sof_cb == NULL) { + WB32_USB->INTRUSBE &= ~USB_INTRUSBE_SOFIE; + } + if (USBD1.state == USB_SUSPENDED) { + _usb_wakeup(&USBD1); + } + /* sof hook function */ _usb_isr_invoke_sof_cb(&USBD1); } @@ -517,38 +527,6 @@ OSAL_IRQ_HANDLER(WB32_USB1_IRQ_VECTOR) { } #endif -#if defined(WB32_USB1_DMA_IRQ_VECTOR) -/** - * @brief USB DMA interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(WB32_USB1_DMA_IRQ_VECTOR) { - - OSAL_IRQ_PROLOGUE(); - - /* USB1 DMA handling.*/ - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(WB32_USBP1_WKUP_IRQ_VECTOR) -/** - * @brief USB WKUP interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(WB32_USBP1_WKUP_IRQ_VECTOR) { - - OSAL_IRQ_PROLOGUE(); - - /* USB1 DMA handling.*/ - - OSAL_IRQ_EPILOGUE(); -} -#endif - #endif /* WB32_USB_USE_USB1 */ /*===========================================================================*/ diff --git a/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h b/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h index 6c052ec4bb..c8ff67469d 100644 --- a/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h +++ b/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h @@ -469,10 +469,10 @@ struct USBDriver { */ #define usb_lld_wakeup_host(usbp) do { \ /* Remote Wakeup */ \ + WB32_USB->INTRUSBE |= USB_INTRUSBE_SOFIE; \ WB32_USB->POWER |= USB_POWER_RESUME; \ osalThreadSleepMilliseconds(WB32_USB_HOST_WAKEUP_DURATION); \ WB32_USB->POWER &= ~USB_POWER_RESUME; \ - _usb_wakeup(usbp); \ } while (false) /*===========================================================================*/ diff --git a/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c b/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c index e67e4dae35..d336c01f79 100644 --- a/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c +++ b/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c @@ -45,6 +45,27 @@ uint32_t SystemCoreClock = WB32_MAINCLK; /* Driver local functions. */ /*===========================================================================*/ +void wb32_set_main_clock_to_mhsi(void) { + + /* Unlocks write to ANCTL registers */ + PWR->ANAKEY1 = 0x03; + PWR->ANAKEY2 = 0x0C; + + /* Configure Flash prefetch, Cache and wait state */ + CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_0WS; + + /* Select FHSI as system clock source */ + RCC->MAINCLKSRC = RCC_MAINCLKSRC_MHSI; + RCC->MAINCLKUEN = RCC_MAINCLKUEN_ENA; + + /* PLL Disable */ + ANCTL->PLLENR = 0x00; + + /* Locks write to ANCTL registers */ + PWR->ANAKEY1 = 0x00; + PWR->ANAKEY2 = 0x00; +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -254,6 +275,21 @@ void wb32_clock_init(void) { SetSysClock(); +#if WB32_LSI_ENABLED == TRUE + /* Unlocks write to ANCTL registers */ + PWR->ANAKEY1 = 0x03; + PWR->ANAKEY2 = 0x0C; + + /* LSI activation.*/ + ANCTL->LSIENR |= 0x1; + while ((ANCTL->LSISR & 0x1) == 0) + ; /* Waits until LSI is stable. */ + + /* Locks write to ANCTL registers */ + PWR->ANAKEY1 = 0x00; + PWR->ANAKEY2 = 0x00; +#endif + rccEnableAPB1(RCC_APB1ENR_BMX1EN); rccEnableAPB2(RCC_APB2ENR_BMX2EN); diff --git a/os/hal/ports/WB32/WB32F3G71xx/hal_lld.h b/os/hal/ports/WB32/WB32F3G71xx/hal_lld.h index f9b32529dd..6c84cd9a0c 100644 --- a/os/hal/ports/WB32/WB32F3G71xx/hal_lld.h +++ b/os/hal/ports/WB32/WB32F3G71xx/hal_lld.h @@ -35,6 +35,7 @@ #include "wb32_registry.h" #include "wb32_tim.h" #include "wb32_dma.h" +#include "wb32_exti.h" /*===========================================================================*/ /* Driver constants. */ @@ -59,6 +60,13 @@ * @{ */ +/** + * @brief LSI clock frequency. + */ +#ifndef WB32_LSICLK +#define WB32_LSICLK 40000 +#endif + /** * @brief Maximum HSE clock frequency. */ @@ -140,6 +148,16 @@ #define WB32_USBPRE_DIV3 (0x3U) /** @} */ +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define WB32_RTCSEL_MASK (3U << 8) +#define WB32_RTCSEL_NOCLOCK (0U << 8) +#define WB32_RTCSEL_LSE (1U << 8) +#define WB32_RTCSEL_LSI (2U << 8) +#define WB32_RTCSEL_HSEDIV (3U << 8) +/** @} */ /*===========================================================================*/ /* Platform capabilities. */ @@ -229,6 +247,13 @@ #define WB32_PLLSRC WB32_PLLSRC_HSE #endif +/** + * @brief RTC clock source. + */ +#if !defined(WB32_RTCSEL) || defined(__DOXYGEN__) +#define WB32_RTCSEL WB32_RTCSEL_NOCLOCK +#endif + /** * @brief Crystal PLL pre-divider. * @note This setting has only effect if the PLL is selected as the @@ -338,6 +363,10 @@ #error "HSE not enabled, required by WB32_MAINCLKSRC and WB32_PLLSRC" #endif +#if WB32_RTCSEL == WB32_RTCSEL_HSEDIV +#error "HSE not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_HSE_ENABLED */ /* @@ -345,6 +374,11 @@ */ #if WB32_LSI_ENABLED #else /* !WB32_LSI_ENABLED */ + +#if HAL_USE_RTC && (WB32_RTCSEL == WB32_RTCSEL_LSI) +#error "LSI not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_LSI_ENABLED */ /* @@ -361,6 +395,11 @@ #endif #else /* !WB32_LSE_ENABLED */ + +#if WB32_RTCSEL == WB32_RTCSEL_LSE +#error "LSE not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_LSE_ENABLED */ /** @@ -466,6 +505,32 @@ #error "WB32_PCLK2 exceeding maximum frequency (WB32_PCLK2_MAX)" #endif +/** + * @brief RTC clock. + */ +#if (WB32_RTCSEL == WB32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define WB32_RTCCLK WB32_LSECLK +#elif WB32_RTCSEL == WB32_RTCSEL_HSEDIV +#define WB32_RTCCLK (WB32_HSECLK / 128) +#elif WB32_RTCSEL == WB32_RTCSEL_NOCLOCK +#define WB32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief RTC Low Power clock. + */ +#if (WB32_RTCLP_SEL == WB32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define WB32_RTCLPCLK WB32_LSECLK +#elif WB32_RTCLP_SEL == WB32_RTCSEL_LSI +#define WB32_RTCLPCLK WB32_LSICLK +#elif WB32_RTCLP_SEL == WB32_RTCSEL_NOCLOCK +#define WB32_RTCLPCLK 0 +#else +#error "invalid source selected for RTC Low Power clock" +#endif + /** * @brief USB frequency. */ @@ -498,6 +563,26 @@ /* Driver macros. */ /*===========================================================================*/ +/** + * @name PWR interface specific BKP operations + * @{ + */ +/** + * @brief Enables the PWR interface. + * + * @api + */ +#define PWR_BackupAccessEnable() (PWR->CR0 |= 0x1U) + +/** + * @brief Disables PWR interface. + * + * @api + */ +#define PWR_BackupAccessDISABLE() (PWR->CR0 &= (~(0x1U))) + +/** @} */ + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ @@ -512,6 +597,7 @@ extern "C" { #endif void hal_lld_init(void); void wb32_clock_init(void); + void wb32_set_main_clock_to_mhsi(void); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/WB32/WB32F3G71xx/platform.mk b/os/hal/ports/WB32/WB32F3G71xx/platform.mk index 6ed97ed041..4edcf40a02 100644 --- a/os/hal/ports/WB32/WB32F3G71xx/platform.mk +++ b/os/hal/ports/WB32/WB32F3G71xx/platform.mk @@ -32,6 +32,8 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/UARTv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/SPIv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/USBv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/ADCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/RTCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/EXTIv1/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC_CONTRIB) diff --git a/os/hal/ports/WB32/WB32F3G71xx/wb32_rcc.h b/os/hal/ports/WB32/WB32F3G71xx/wb32_rcc.h index d7038a40d6..06c7a1d034 100644 --- a/os/hal/ports/WB32/WB32F3G71xx/wb32_rcc.h +++ b/os/hal/ports/WB32/WB32F3G71xx/wb32_rcc.h @@ -31,6 +31,32 @@ /* Driver constants. */ /*===========================================================================*/ +/** @defgroup AHB_peripheral + * @{ + */ +#define RCC_AHBPeriph_IWDG ((uint32_t)0x00000004) +#define RCC_AHBPeriph_USB ((uint32_t)0x00000200) +#define RCC_AHBPeriph_ISO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_FLASH ((uint32_t)0x00000800) +#define RCC_AHBPeriph_CACHE ((uint32_t)0x00001000) +#define RCC_AHBPeriph_SYS ((uint32_t)0x00002000) +#define RCC_AHBPeriph_DMAC1Bridge ((uint32_t)0x00004000) +#define RCC_AHBPeriph_DMAC2Bridge ((uint32_t)0x00008000) +#define RCC_AHBPeriph_CRC_SFM ((uint32_t)0x00010000) +#define RCC_AHBPeriph_BKP ((uint32_t)0x04000000) +/** + * @} + */ + +/** @defgroup LSE_Configuration + * @{ + */ +#define BKP_LSE_OFF ((uint32_t)0x00000000) +#define BKP_LSE_ON ((uint32_t)0x00000001) +#define BKP_LSE_Bypass ((uint32_t)0x00000004) +/** + * @} + */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -149,6 +175,30 @@ (void)RCC->AHBENR1; \ } +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccEnableAHB2(mask) { \ + RCC->AHBENR2 |= (mask); \ + (void)RCC->AHBENR2; \ + } + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccDisableAHB2(mask) { \ + RCC->AHBENR2 &= ~(mask); \ + (void)RCC->AHBENR2; \ + } + /** * @brief Resets one or more peripheral on the AHB bus. * @@ -163,9 +213,6 @@ } /** @} */ - - - /** * @name EXTI peripherals specific RCC operations * @{ @@ -589,6 +636,40 @@ #define rccResetDMAC2() rccResetAPB2(RCC_APB2RSTR_DMAC2RST) /** @} */ +/** + * @name BKP peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the BKP peripheral clock. + * + * @api + */ +#define rccEnableBKP() do { \ + rccEnableAHB2(RCC_AHBPeriph_BKP >> 24); \ + } while (false) + +/** + * @brief Disables the BKP peripheral clock. + * + * @api + */ +#define rccDisableBKP() do { \ + rccDisableAHB2(RCC_AHBPeriph_BKP >> 24); \ + } while (false) + +/** + * @brief Resets the BKP peripheral. + * + * @api + */ +#define rccResetBKP() { \ + RCC->BDRSTR = (uint32_t)ENABLE; \ + RCC->BDRSTR = (uint32_t)DISABLE; \ + (void)RCC->BDRSTR; \ + } +/** @} */ + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ diff --git a/os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h b/os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h index 155812719f..e18ab027e4 100644 --- a/os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h +++ b/os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h @@ -137,6 +137,8 @@ /* CRC attributes.*/ #define WB32_HAS_CRC TRUE +/* RTC attributes.*/ +#define WB32_RTC_ALARM_EXTI 17 /** @} */ #endif /* defined(WB32F3G71xx) */ diff --git a/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c b/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c index 62a3ca74e5..c3031258ca 100644 --- a/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c +++ b/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c @@ -45,6 +45,27 @@ uint32_t SystemCoreClock = WB32_MAINCLK; /* Driver local functions. */ /*===========================================================================*/ +void wb32_set_main_clock_to_mhsi(void) { + + /* Unlocks write to ANCTL registers */ + PWR->ANAKEY1 = 0x03; + PWR->ANAKEY2 = 0x0C; + + /* Configure Flash prefetch, Cache and wait state */ + CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_0WS; + + /* Select FHSI as system clock source */ + RCC->MAINCLKSRC = RCC_MAINCLKSRC_MHSI; + RCC->MAINCLKUEN = RCC_MAINCLKUEN_ENA; + + /* PLL Disable */ + ANCTL->PLLENR = 0x00; + + /* Locks write to ANCTL registers */ + PWR->ANAKEY1 = 0x00; + PWR->ANAKEY2 = 0x00; +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -254,6 +275,21 @@ void wb32_clock_init(void) { SetSysClock(); +#if WB32_LSI_ENABLED == TRUE + /* Unlocks write to ANCTL registers */ + PWR->ANAKEY1 = 0x03; + PWR->ANAKEY2 = 0x0C; + + /* LSI activation.*/ + ANCTL->LSIENR |= 0x1; + while ((ANCTL->LSISR & 0x1) == 0) + ; /* Waits until LSI is stable. */ + + /* Locks write to ANCTL registers */ + PWR->ANAKEY1 = 0x00; + PWR->ANAKEY2 = 0x00; +#endif + rccEnableAPB1(RCC_APB1ENR_BMX1EN); rccEnableAPB2(RCC_APB2ENR_BMX2EN); diff --git a/os/hal/ports/WB32/WB32FQ95xx/hal_lld.h b/os/hal/ports/WB32/WB32FQ95xx/hal_lld.h index ebb0a1b232..269de4692c 100644 --- a/os/hal/ports/WB32/WB32FQ95xx/hal_lld.h +++ b/os/hal/ports/WB32/WB32FQ95xx/hal_lld.h @@ -35,6 +35,7 @@ #include "wb32_registry.h" #include "wb32_tim.h" #include "wb32_dma.h" +#include "wb32_exti.h" /*===========================================================================*/ /* Driver constants. */ @@ -59,6 +60,13 @@ * @{ */ +/** + * @brief LSI clock frequency. + */ +#ifndef WB32_LSICLK +#define WB32_LSICLK 40000 +#endif + /** * @brief Maximum HSE clock frequency. */ @@ -140,6 +148,16 @@ #define WB32_USBPRE_DIV3 (0x3U) /** @} */ +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define WB32_RTCSEL_MASK (3U << 8) +#define WB32_RTCSEL_NOCLOCK (0U << 8) +#define WB32_RTCSEL_LSE (1U << 8) +#define WB32_RTCSEL_LSI (2U << 8) +#define WB32_RTCSEL_HSEDIV (3U << 8) +/** @} */ /*===========================================================================*/ /* Platform capabilities. */ @@ -229,6 +247,13 @@ #define WB32_PLLSRC WB32_PLLSRC_HSE #endif +/** + * @brief RTC clock source. + */ +#if !defined(WB32_RTCSEL) || defined(__DOXYGEN__) +#define WB32_RTCSEL WB32_RTCSEL_NOCLOCK +#endif + /** * @brief Crystal PLL pre-divider. * @note This setting has only effect if the PLL is selected as the @@ -338,6 +363,10 @@ #error "HSE not enabled, required by WB32_MAINCLKSRC and WB32_PLLSRC" #endif +#if WB32_RTCSEL == WB32_RTCSEL_HSEDIV +#error "HSE not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_HSE_ENABLED */ /* @@ -345,6 +374,11 @@ */ #if WB32_LSI_ENABLED #else /* !WB32_LSI_ENABLED */ + +#if HAL_USE_RTC && (WB32_RTCSEL == WB32_RTCSEL_LSI) +#error "LSI not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_LSI_ENABLED */ /* @@ -361,6 +395,11 @@ #endif #else /* !WB32_LSE_ENABLED */ + +#if WB32_RTCSEL == WB32_RTCSEL_LSE +#error "LSE not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_LSE_ENABLED */ /** @@ -466,6 +505,32 @@ #error "WB32_PCLK2 exceeding maximum frequency (WB32_PCLK2_MAX)" #endif +/** + * @brief RTC clock. + */ +#if (WB32_RTCSEL == WB32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define WB32_RTCCLK WB32_LSECLK +#elif WB32_RTCSEL == WB32_RTCSEL_HSEDIV +#define WB32_RTCCLK (WB32_HSECLK / 128) +#elif WB32_RTCSEL == WB32_RTCSEL_NOCLOCK +#define WB32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief RTC Low Power clock. + */ +#if (WB32_RTCLP_SEL == WB32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define WB32_RTCLPCLK WB32_LSECLK +#elif WB32_RTCLP_SEL == WB32_RTCSEL_LSI +#define WB32_RTCLPCLK WB32_LSICLK +#elif WB32_RTCLP_SEL == WB32_RTCSEL_NOCLOCK +#define WB32_RTCLPCLK 0 +#else +#error "invalid source selected for RTC Low Power clock" +#endif + /** * @brief USB frequency. */ @@ -498,6 +563,26 @@ /* Driver macros. */ /*===========================================================================*/ +/** + * @name PWR interface specific BKP operations + * @{ + */ +/** + * @brief Enables the PWR interface. + * + * @api + */ +#define PWR_BackupAccessEnable() (PWR->CR0 |= 0x1U) + +/** + * @brief Disables PWR interface. + * + * @api + */ +#define PWR_BackupAccessDISABLE() (PWR->CR0 &= (~(0x1U))) + +/** @} */ + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ @@ -512,6 +597,7 @@ extern "C" { #endif void hal_lld_init(void); void wb32_clock_init(void); + void wb32_set_main_clock_to_mhsi(void); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/WB32/WB32FQ95xx/platform.mk b/os/hal/ports/WB32/WB32FQ95xx/platform.mk index 9f8a9afcc9..2b0f0589da 100644 --- a/os/hal/ports/WB32/WB32FQ95xx/platform.mk +++ b/os/hal/ports/WB32/WB32FQ95xx/platform.mk @@ -32,6 +32,8 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/UARTv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/SPIv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/USBv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/ADCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/RTCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/EXTIv1/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC_CONTRIB) diff --git a/os/hal/ports/WB32/WB32FQ95xx/wb32_rcc.h b/os/hal/ports/WB32/WB32FQ95xx/wb32_rcc.h index aea6c5af38..e3d7a115cd 100644 --- a/os/hal/ports/WB32/WB32FQ95xx/wb32_rcc.h +++ b/os/hal/ports/WB32/WB32FQ95xx/wb32_rcc.h @@ -31,6 +31,32 @@ /* Driver constants. */ /*===========================================================================*/ +/** @defgroup AHB_peripheral + * @{ + */ +#define RCC_AHBPeriph_IWDG ((uint32_t)0x00000004) +#define RCC_AHBPeriph_USB ((uint32_t)0x00000200) +#define RCC_AHBPeriph_ISO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_FLASH ((uint32_t)0x00000800) +#define RCC_AHBPeriph_CACHE ((uint32_t)0x00001000) +#define RCC_AHBPeriph_SYS ((uint32_t)0x00002000) +#define RCC_AHBPeriph_DMAC1Bridge ((uint32_t)0x00004000) +#define RCC_AHBPeriph_DMAC2Bridge ((uint32_t)0x00008000) +#define RCC_AHBPeriph_CRC_SFM ((uint32_t)0x00010000) +#define RCC_AHBPeriph_BKP ((uint32_t)0x04000000) +/** + * @} + */ + +/** @defgroup LSE_Configuration + * @{ + */ +#define BKP_LSE_OFF ((uint32_t)0x00000000) +#define BKP_LSE_ON ((uint32_t)0x00000001) +#define BKP_LSE_Bypass ((uint32_t)0x00000004) +/** + * @} + */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -149,6 +175,30 @@ (void)RCC->AHBENR1; \ } +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccEnableAHB2(mask) { \ + RCC->AHBENR2 |= (mask); \ + (void)RCC->AHBENR2; \ + } + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccDisableAHB2(mask) { \ + RCC->AHBENR2 &= ~(mask); \ + (void)RCC->AHBENR2; \ + } + /** * @brief Resets one or more peripheral on the AHB bus. * @@ -163,9 +213,6 @@ } /** @} */ - - - /** * @name EXTI peripherals specific RCC operations * @{ @@ -589,6 +636,40 @@ #define rccResetDMAC2() rccResetAPB2(RCC_APB2RSTR_DMAC2RST) /** @} */ +/** + * @name BKP peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the BKP peripheral clock. + * + * @api + */ +#define rccEnableBKP() do { \ + rccEnableAHB2(RCC_AHBPeriph_BKP >> 24); \ + } while (false) + +/** + * @brief Disables the BKP peripheral clock. + * + * @api + */ +#define rccDisableBKP() do { \ + rccDisableAHB2(RCC_AHBPeriph_BKP >> 24); \ + } while (false) + +/** + * @brief Resets the BKP peripheral. + * + * @api + */ +#define rccResetBKP() { \ + RCC->BDRSTR = (uint32_t)ENABLE; \ + RCC->BDRSTR = (uint32_t)DISABLE; \ + (void)RCC->BDRSTR; \ + } +/** @} */ + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ diff --git a/os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h b/os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h index bbc1672634..ab8d897657 100644 --- a/os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h +++ b/os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h @@ -137,6 +137,8 @@ /* CRC attributes.*/ #define WB32_HAS_CRC TRUE +/* RTC attributes.*/ +#define WB32_RTC_ALARM_EXTI 17 /** @} */ #endif /* defined(WB32FQ95xx) */