From efd1086138e69cdc48327b5fd7973d7b517c6f51 Mon Sep 17 00:00:00 2001 From: liuhy Date: Thu, 28 Mar 2024 16:13:36 +0800 Subject: [PATCH] Added support for MCU FS026 --- .github/workflows/build.yml | 4 + demos/ES32/.keep | 0 demos/ES32/FS026/Makefile | 191 + demos/ES32/FS026/cfg/chconf.h | 834 +++ demos/ES32/FS026/cfg/halconf.h | 532 ++ demos/ES32/FS026/cfg/halconf_community.h | 180 + demos/ES32/FS026/cfg/mcuconf.h | 162 + demos/ES32/FS026/main.c | 70 + demos/ES32/FS026/readme.txt | 25 + .../ext/CMSIS/ES32/FS026/FS026/reg_adc.h | 850 +++ .../ext/CMSIS/ES32/FS026/FS026/reg_aes.h | 237 + .../ext/CMSIS/ES32/FS026/FS026/reg_calc.h | 118 + .../ext/CMSIS/ES32/FS026/FS026/reg_cmp.h | 188 + .../ext/CMSIS/ES32/FS026/FS026/reg_crc.h | 159 + .../ext/CMSIS/ES32/FS026/FS026/reg_csu.h | 278 + .../ext/CMSIS/ES32/FS026/FS026/reg_dma.h | 345 + .../ext/CMSIS/ES32/FS026/FS026/reg_exti.h | 289 + os/common/ext/CMSIS/ES32/FS026/FS026/reg_fc.h | 227 + .../ext/CMSIS/ES32/FS026/FS026/reg_gpio.h | 924 +++ .../ext/CMSIS/ES32/FS026/FS026/reg_i2c.h | 710 +++ .../ext/CMSIS/ES32/FS026/FS026/reg_iwdt.h | 96 + .../ext/CMSIS/ES32/FS026/FS026/reg_kbcu.h | 595 ++ .../ext/CMSIS/ES32/FS026/FS026/reg_mswd.h | 217 + .../ext/CMSIS/ES32/FS026/FS026/reg_rcu.h | 905 +++ .../ext/CMSIS/ES32/FS026/FS026/reg_rtc.h | 793 +++ .../ext/CMSIS/ES32/FS026/FS026/reg_spi.h | 598 ++ .../ext/CMSIS/ES32/FS026/FS026/reg_syscfg.h | 646 ++ .../ext/CMSIS/ES32/FS026/FS026/reg_tick.h | 109 + .../ext/CMSIS/ES32/FS026/FS026/reg_timer.h | 901 +++ .../ext/CMSIS/ES32/FS026/FS026/reg_uart.h | 697 ++ .../ext/CMSIS/ES32/FS026/FS026/reg_usb.h | 1211 ++++ .../ext/CMSIS/ES32/FS026/FS026/reg_wwdt.h | 115 + os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.c | 1658 +++++ os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.h | 820 +++ os/common/ext/CMSIS/ES32/FS026/ald/utils.c | 436 ++ os/common/ext/CMSIS/ES32/FS026/ald/utils.h | 180 + os/common/ext/CMSIS/ES32/FS026/fs026.h | 437 ++ os/common/ext/CMSIS/ES32/FS026/md/md_adc.c | 346 + os/common/ext/CMSIS/ES32/FS026/md/md_adc.h | 5289 +++++++++++++++ os/common/ext/CMSIS/ES32/FS026/md/md_aes.h | 829 +++ os/common/ext/CMSIS/ES32/FS026/md/md_calc.h | 364 ++ os/common/ext/CMSIS/ES32/FS026/md/md_cmp.h | 765 +++ os/common/ext/CMSIS/ES32/FS026/md/md_crc.c | 107 + os/common/ext/CMSIS/ES32/FS026/md/md_crc.h | 602 ++ os/common/ext/CMSIS/ES32/FS026/md/md_csu.c | 115 + os/common/ext/CMSIS/ES32/FS026/md/md_csu.h | 968 +++ os/common/ext/CMSIS/ES32/FS026/md/md_dma.c | 163 + os/common/ext/CMSIS/ES32/FS026/md/md_dma.h | 2035 ++++++ os/common/ext/CMSIS/ES32/FS026/md/md_exti.h | 1699 +++++ os/common/ext/CMSIS/ES32/FS026/md/md_fc.c | 642 ++ os/common/ext/CMSIS/ES32/FS026/md/md_fc.h | 893 +++ os/common/ext/CMSIS/ES32/FS026/md/md_gpio.c | 219 + os/common/ext/CMSIS/ES32/FS026/md/md_gpio.h | 1093 ++++ os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c | 353 + os/common/ext/CMSIS/ES32/FS026/md/md_i2c.h | 3107 +++++++++ os/common/ext/CMSIS/ES32/FS026/md/md_iwdt.h | 272 + os/common/ext/CMSIS/ES32/FS026/md/md_kbcu.h | 3128 +++++++++ os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c | 408 ++ os/common/ext/CMSIS/ES32/FS026/md/md_rcu.h | 5579 ++++++++++++++++ os/common/ext/CMSIS/ES32/FS026/md/md_rtc.c | 296 + os/common/ext/CMSIS/ES32/FS026/md/md_rtc.h | 2929 +++++++++ os/common/ext/CMSIS/ES32/FS026/md/md_spi.c | 231 + os/common/ext/CMSIS/ES32/FS026/md/md_spi.h | 3535 ++++++++++ os/common/ext/CMSIS/ES32/FS026/md/md_syscfg.h | 2494 ++++++++ os/common/ext/CMSIS/ES32/FS026/md/md_tick.c | 234 + os/common/ext/CMSIS/ES32/FS026/md/md_tick.h | 338 + os/common/ext/CMSIS/ES32/FS026/md/md_timer.h | 5671 +++++++++++++++++ os/common/ext/CMSIS/ES32/FS026/md/md_uart.c | 194 + os/common/ext/CMSIS/ES32/FS026/md/md_uart.h | 2916 +++++++++ os/common/ext/CMSIS/ES32/FS026/md/md_usb.h | 4365 +++++++++++++ os/common/ext/CMSIS/ES32/FS026/md/md_utils.c | 207 + os/common/ext/CMSIS/ES32/FS026/md/md_utils.h | 108 + os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.c | 94 + os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.h | 500 ++ os/common/ext/CMSIS/ES32/FS026/md/type.h | 144 + .../ext/CMSIS/ES32/FS026/startup_fs026.s | 260 + os/common/ext/CMSIS/ES32/FS026/system_fs026.c | 85 + os/common/ext/CMSIS/ES32/FS026/system_fs026.h | 99 + .../startup/ARMCMx/compilers/GCC/ld/FS026.ld | 85 + .../ARMCMx/compilers/GCC/mk/startup_FS026.mk | 30 + .../startup/ARMCMx/devices/FS026/cmparams.h | 85 + os/hal/boards/FS026/board.c | 54 + os/hal/boards/FS026/board.h | 58 + os/hal/boards/FS026/board.mk | 9 + os/hal/ports/ES32/FS026/es32_registry.h | 120 + os/hal/ports/ES32/FS026/hal_lld.c | 152 + os/hal/ports/ES32/FS026/hal_lld.h | 80 + os/hal/ports/ES32/FS026/platform.mk | 38 + os/hal/ports/ES32/LLD/ADCv1/driver.mk | 9 + os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c | 149 + os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.h | 130 + os/hal/ports/ES32/LLD/ADCv1/notes.txt | 16 + os/hal/ports/ES32/LLD/GPIOv1/driver.mk | 9 + os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.c | 232 + os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h | 440 ++ os/hal/ports/ES32/LLD/I2Cv1/driver.mk | 9 + os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c | 248 + os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.h | 195 + os/hal/ports/ES32/LLD/SPIv1/driver.mk | 9 + os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c | 374 ++ os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h | 120 + os/hal/ports/ES32/LLD/TIMv1/driver.mk | 15 + os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.c | 238 + os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.h | 197 + os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.c | 673 ++ os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.h | 609 ++ os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.c | 92 + os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.h | 151 + os/hal/ports/ES32/LLD/UARTv1/driver.mk | 13 + os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c | 116 + os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.h | 128 + os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.c | 173 + os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.h | 231 + os/hal/ports/ES32/LLD/USBv1/driver.mk | 9 + os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c | 1186 ++++ os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.h | 398 ++ os/hal/ports/ES32/LLD/WDTv1/driver.mk | 9 + os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.c | 137 + os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.h | 150 + testhal/ES32/.keep | 0 120 files changed, 77589 insertions(+) create mode 100644 demos/ES32/.keep create mode 100644 demos/ES32/FS026/Makefile create mode 100644 demos/ES32/FS026/cfg/chconf.h create mode 100644 demos/ES32/FS026/cfg/halconf.h create mode 100644 demos/ES32/FS026/cfg/halconf_community.h create mode 100644 demos/ES32/FS026/cfg/mcuconf.h create mode 100644 demos/ES32/FS026/main.c create mode 100644 demos/ES32/FS026/readme.txt create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_adc.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_aes.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_calc.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_cmp.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_crc.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_csu.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_dma.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_exti.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_fc.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_gpio.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_i2c.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_iwdt.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_kbcu.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_mswd.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_rcu.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_rtc.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_spi.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_syscfg.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_tick.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_timer.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_uart.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_usb.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/FS026/reg_wwdt.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/ald/utils.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/ald/utils.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/fs026.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_adc.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_adc.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_aes.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_calc.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_cmp.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_crc.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_crc.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_csu.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_csu.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_dma.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_dma.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_exti.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_fc.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_fc.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_gpio.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_gpio.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_i2c.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_iwdt.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_kbcu.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_rcu.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_rtc.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_rtc.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_spi.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_spi.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_syscfg.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_tick.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_tick.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_timer.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_uart.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_uart.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_usb.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_utils.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_utils.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/md/type.h create mode 100644 os/common/ext/CMSIS/ES32/FS026/startup_fs026.s create mode 100644 os/common/ext/CMSIS/ES32/FS026/system_fs026.c create mode 100644 os/common/ext/CMSIS/ES32/FS026/system_fs026.h create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/FS026.ld create mode 100644 os/common/startup/ARMCMx/compilers/GCC/mk/startup_FS026.mk create mode 100644 os/common/startup/ARMCMx/devices/FS026/cmparams.h create mode 100644 os/hal/boards/FS026/board.c create mode 100644 os/hal/boards/FS026/board.h create mode 100644 os/hal/boards/FS026/board.mk create mode 100644 os/hal/ports/ES32/FS026/es32_registry.h create mode 100644 os/hal/ports/ES32/FS026/hal_lld.c create mode 100644 os/hal/ports/ES32/FS026/hal_lld.h create mode 100644 os/hal/ports/ES32/FS026/platform.mk create mode 100644 os/hal/ports/ES32/LLD/ADCv1/driver.mk create mode 100644 os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c create mode 100644 os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.h create mode 100644 os/hal/ports/ES32/LLD/ADCv1/notes.txt create mode 100644 os/hal/ports/ES32/LLD/GPIOv1/driver.mk create mode 100644 os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.c create mode 100644 os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h create mode 100644 os/hal/ports/ES32/LLD/I2Cv1/driver.mk create mode 100644 os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c create mode 100644 os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.h create mode 100644 os/hal/ports/ES32/LLD/SPIv1/driver.mk create mode 100644 os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c create mode 100644 os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h create mode 100644 os/hal/ports/ES32/LLD/TIMv1/driver.mk create mode 100644 os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.c create mode 100644 os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.h create mode 100644 os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.c create mode 100644 os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.h create mode 100644 os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.c create mode 100644 os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.h create mode 100644 os/hal/ports/ES32/LLD/UARTv1/driver.mk create mode 100644 os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c create mode 100644 os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.h create mode 100644 os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.c create mode 100644 os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.h create mode 100644 os/hal/ports/ES32/LLD/USBv1/driver.mk create mode 100644 os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c create mode 100644 os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.h create mode 100644 os/hal/ports/ES32/LLD/WDTv1/driver.mk create mode 100644 os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.c create mode 100644 os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.h create mode 100644 testhal/ES32/.keep diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 5ecc6d7424f..274f0957b9f 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -69,3 +69,7 @@ jobs: run: | $CHC_PATH/tools/chbuild.sh $CHC_PATH/testhal/AT32 $CHC_PATH/tools/chbuild.sh $CHC_PATH/demos/AT32 + - name: build ES32 + run: | + $CHC_PATH/tools/chbuild.sh $CHC_PATH/testhal/ES32 + $CHC_PATH/tools/chbuild.sh $CHC_PATH/demos/ES32 diff --git a/demos/ES32/.keep b/demos/ES32/.keep new file mode 100644 index 00000000000..e69de29bb2d diff --git a/demos/ES32/FS026/Makefile b/demos/ES32/FS026/Makefile new file mode 100644 index 00000000000..ae4e4e8a0ca --- /dev/null +++ b/demos/ES32/FS026/Makefile @@ -0,0 +1,191 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -Os -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m0 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../ +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep +BOARDDIR := $(CHIBIOS_CONTRIB)/os/hal/boards/FS026 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_FS026.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/FS026/platform.mk +include $(BOARDDIR)/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv6-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/FS026.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wno-unused-function + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef -Wno-unused-function + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DPORT_IGNORE_GCC_VERSION_CHECK + +# Define ASM defines here +UADEFS = -DPORT_IGNORE_GCC_VERSION_CHECK + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/ES32/FS026/cfg/chconf.h b/demos/ES32/FS026/cfg/chconf.h new file mode 100644 index 00000000000..093a1bae367 --- /dev/null +++ b/demos/ES32/FS026/cfg/chconf.h @@ -0,0 +1,834 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/ES32/FS026/cfg/halconf.h b/demos/ES32/FS026/cfg/halconf.h new file mode 100644 index 00000000000..165aedf0256 --- /dev/null +++ b/demos/ES32/FS026/cfg/halconf.h @@ -0,0 +1,532 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE FALSE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS FALSE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING FALSE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/ES32/FS026/cfg/halconf_community.h b/demos/ES32/FS026/cfg/halconf_community.h new file mode 100644 index 00000000000..34677960f82 --- /dev/null +++ b/demos/ES32/FS026/cfg/halconf_community.h @@ -0,0 +1,180 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY FALSE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/demos/ES32/FS026/cfg/mcuconf.h b/demos/ES32/FS026/cfg/mcuconf.h new file mode 100644 index 00000000000..a6c050d0b56 --- /dev/null +++ b/demos/ES32/FS026/cfg/mcuconf.h @@ -0,0 +1,162 @@ +/* + Copyright (C) 2021 essemi + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/** + * @name Internal clock sources + * @{ + */ +#define ES32_PLLCLK 72000000 +#define ES32_HRCCLK 48000000 +#define ES32_LSECLK 32768 + +/* + * HAL driver system settings. + */ +#define ES32_NO_INIT FALSE +#define ES32_MHSI_ENABLED TRUE +#define ES32_FHSI_ENABLED FALSE +#define ES32_LSI_ENABLED FALSE +#define ES32_HSE_ENABLED TRUE +#define ES32_LSE_ENABLED FALSE +#define ES32_PLL_ENABLED TRUE +#define ES32_MAINCLKSRC ES32_MAINCLKSRC_PLL +#define ES32_HSE_STATE ANCTL_HSECR0_HSEON +#define ES32_PLLSRC ES32_PLLSRC_HSE +#define ES32_PLLDIV_VALUE 2 +#define ES32_PLLMUL_VALUE 12 // The allowed range is 12,16,20,24. +#define ES32_HPRE 1 +#define ES32_PPRE1 1 +#define ES32_PPRE2 1 +#define ES32_USBPRE ES32_USBPRE_DIV1P5 + +/* + * EXTI driver system settings. + */ +#define ES32_IRQ_EXTI0_PRIORITY 6 +#define ES32_IRQ_EXTI1_PRIORITY 6 +#define ES32_IRQ_EXTI2_PRIORITY 6 +#define ES32_IRQ_EXTI3_PRIORITY 6 +#define ES32_IRQ_EXTI4_PRIORITY 6 +#define ES32_IRQ_EXTI5_9_PRIORITY 6 +#define ES32_IRQ_EXTI10_15_PRIORITY 6 +#define ES32_IRQ_EXTI16_PRIORITY 6 +#define ES32_IRQ_EXTI17_PRIORITY 6 +#define ES32_IRQ_EXTI18_PRIORITY 6 +#define ES32_IRQ_EXTI19_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define ES32_TIM_MAX_CHANNELS 4 +#define ES32_GPT_USE_TIM1 FALSE +#define ES32_GPT_USE_TIM2 FALSE +#define ES32_GPT_USE_TIM3 FALSE +#define ES32_GPT_USE_TIM4 FALSE +#define ES32_GPT_TIM1_IRQ_PRIORITY 7 +#define ES32_GPT_TIM2_IRQ_PRIORITY 7 +#define ES32_GPT_TIM3_IRQ_PRIORITY 7 +#define ES32_GPT_TIM4_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define ES32_ICU_USE_TIM1 FALSE +#define ES32_ICU_USE_TIM2 FALSE +#define ES32_ICU_USE_TIM3 FALSE +#define ES32_ICU_USE_TIM4 FALSE +#define ES32_ICU_TIM1_IRQ_PRIORITY 7 +#define ES32_ICU_TIM2_IRQ_PRIORITY 7 +#define ES32_ICU_TIM3_IRQ_PRIORITY 7 +#define ES32_ICU_TIM4_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define ES32_PWM_USE_ADVANCED FALSE +#define ES32_PWM_USE_TIM1 FALSE +#define ES32_PWM_USE_TIM2 FALSE +#define ES32_PWM_USE_TIM3 FALSE +#define ES32_PWM_USE_TIM4 FALSE +#define ES32_PWM_TIM1_IRQ_PRIORITY 7 +#define ES32_PWM_TIM2_IRQ_PRIORITY 7 +#define ES32_PWM_TIM3_IRQ_PRIORITY 7 +#define ES32_PWM_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define ES32_I2C_USE_I2C1 FALSE +#define ES32_I2C_USE_I2C2 FALSE +#define ES32_I2C_BUSY_TIMEOUT 50 +#define ES32_I2C_I2C1_IRQ_PRIORITY 5 +#define ES32_I2C_I2C2_IRQ_PRIORITY 5 + +/* + * SERIAL driver system settings. + */ +#define ES32_SERIAL_USE_UART1 FALSE +#define ES32_SERIAL_USE_UART2 FALSE +#define ES32_SERIAL_USE_UART3 FALSE +#define ES32_SERIAL_USART1_PRIORITY 12 +#define ES32_SERIAL_USART2_PRIORITY 12 +#define ES32_SERIAL_USART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define ES32_SPI_USE_QSPI FALSE +#define ES32_SPI_USE_SPIM2 FALSE +#define ES32_SPI_USE_SPIS1 FALSE +#define ES32_SPI_USE_SPIS2 FALSE +#define ES32_SPI_QSPI_IRQ_PRIORITY 10 +#define ES32_SPI_SPIM2_IRQ_PRIORITY 10 +#define ES32_SPI_SPIS1_IRQ_PRIORITY 10 +#define ES32_SPI_SPIS2_IRQ_PRIORITY 10 + +/* + * ST driver system settings. + */ +#define ES32_ST_IRQ_PRIORITY 8 +#define ES32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define ES32_UART_USE_UART1 FALSE +#define ES32_UART_USE_UART2 FALSE +#define ES32_UART_USE_UART3 FALSE +#define ES32_UART_UART1_IRQ_PRIORITY 12 +#define ES32_UART_UART2_IRQ_PRIORITY 12 +#define ES32_UART_UART3_IRQ_PRIORITY 12 + +/* + * USB driver system settings. + */ +#define ES32_USB_USE_USB1 TRUE +#define ES32_USB_USB1_IRQ_PRIORITY 13 +#define ES32_USB_HOST_WAKEUP_DURATION 10 + +/* + * ADC driver system settings. + */ +#define ES32_ADC_USE_ADC1 FALSE +#define ES32_ADC_ADC1_DMA_PRIORITY 2 +#define ES32_ADC_ADC1_IRQ_PRIORITY 6 + +#endif /* MCUCONF_H */ diff --git a/demos/ES32/FS026/main.c b/demos/ES32/FS026/main.c new file mode 100644 index 00000000000..81c4668f55c --- /dev/null +++ b/demos/ES32/FS026/main.c @@ -0,0 +1,70 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + while (true) { + palClearLine(2); + chThdSleepMilliseconds(500); + palSetLine(2); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + chThdSleepMilliseconds(1000); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), 5, Thread1, NULL); + + /* + * Normal main() thread activity, spawning shells. + */ + while (true) { + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/ES32/FS026/readme.txt b/demos/ES32/FS026/readme.txt new file mode 100644 index 00000000000..fff7bf55d21 --- /dev/null +++ b/demos/ES32/FS026/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/HAL - driver demo for ES32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ES-PDS ES32F0283_FS026 board. + +** The Demo ** + +The application demonstrates the use of the FS026 drivers. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +essemi and are licensed under a different license. +Also note that not all the files present in the essemi library are distributed +with ChibiOS/RT, you can find the whole library on the essemi web site: + + http://www.essemi.com diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_adc.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_adc.h new file mode 100644 index 00000000000..9a34929af31 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_adc.h @@ -0,0 +1,850 @@ +/********************************************************************************** + * + * @file reg_adc.h + * @brief ADC Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __ADC_H__ +#define __ADC_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + +/****************** Bit definition for ADC_IER register ************************/ + +# define ADC_IER_TO_POS 15U +# define ADC_IER_TO_MSK BIT(ADC_IER_TO_POS) +# define ADC_IER_TO ADC_IER_TO_MSK + +# define ADC_IER_AWDF_POS 7U +# define ADC_IER_AWDF_MSK BIT(ADC_IER_AWDF_POS) +# define ADC_IER_AWDF ADC_IER_AWDF_MSK + +# define ADC_IER_ISE_POS 6U +# define ADC_IER_ISE_MSK BIT(ADC_IER_ISE_POS) +# define ADC_IER_ISE ADC_IER_ISE_MSK + +# define ADC_IER_ICHE_POS 5U +# define ADC_IER_ICHE_MSK BIT(ADC_IER_ICHE_POS) +# define ADC_IER_ICHE ADC_IER_ICHE_MSK + +# define ADC_IER_OVR_POS 4U +# define ADC_IER_OVR_MSK BIT(ADC_IER_OVR_POS) +# define ADC_IER_OVR ADC_IER_OVR_MSK + +# define ADC_IER_NSE_POS 3U +# define ADC_IER_NSE_MSK BIT(ADC_IER_NSE_POS) +# define ADC_IER_NSE ADC_IER_NSE_MSK + +# define ADC_IER_NCHE_POS 2U +# define ADC_IER_NCHE_MSK BIT(ADC_IER_NCHE_POS) +# define ADC_IER_NCHE ADC_IER_NCHE_MSK + +# define ADC_IER_SMPE_POS 1U +# define ADC_IER_SMPE_MSK BIT(ADC_IER_SMPE_POS) +# define ADC_IER_SMPE ADC_IER_SMPE_MSK + +# define ADC_IER_ARDY_POS 0U +# define ADC_IER_ARDY_MSK BIT(ADC_IER_ARDY_POS) +# define ADC_IER_ARDY ADC_IER_ARDY_MSK + +/****************** Bit definition for ADC_IDR register ************************/ + +# define ADC_IDR_TO_POS 15U +# define ADC_IDR_TO_MSK BIT(ADC_IDR_TO_POS) +# define ADC_IDR_TO ADC_IDR_TO_MSK + +# define ADC_IDR_AWDF_POS 7U +# define ADC_IDR_AWDF_MSK BIT(ADC_IDR_AWDF_POS) +# define ADC_IDR_AWDF ADC_IDR_AWDF_MSK + +# define ADC_IDR_ISE_POS 6U +# define ADC_IDR_ISE_MSK BIT(ADC_IDR_ISE_POS) +# define ADC_IDR_ISE ADC_IDR_ISE_MSK + +# define ADC_IDR_ICHE_POS 5U +# define ADC_IDR_ICHE_MSK BIT(ADC_IDR_ICHE_POS) +# define ADC_IDR_ICHE ADC_IDR_ICHE_MSK + +# define ADC_IDR_OVR_POS 4U +# define ADC_IDR_OVR_MSK BIT(ADC_IDR_OVR_POS) +# define ADC_IDR_OVR ADC_IDR_OVR_MSK + +# define ADC_IDR_NSE_POS 3U +# define ADC_IDR_NSE_MSK BIT(ADC_IDR_NSE_POS) +# define ADC_IDR_NSE ADC_IDR_NSE_MSK + +# define ADC_IDR_NCHE_POS 2U +# define ADC_IDR_NCHE_MSK BIT(ADC_IDR_NCHE_POS) +# define ADC_IDR_NCHE ADC_IDR_NCHE_MSK + +# define ADC_IDR_SMPE_POS 1U +# define ADC_IDR_SMPE_MSK BIT(ADC_IDR_SMPE_POS) +# define ADC_IDR_SMPE ADC_IDR_SMPE_MSK + +# define ADC_IDR_ARDY_POS 0U +# define ADC_IDR_ARDY_MSK BIT(ADC_IDR_ARDY_POS) +# define ADC_IDR_ARDY ADC_IDR_ARDY_MSK + +/****************** Bit definition for ADC_IVS register ************************/ + +# define ADC_IVS_TO_POS 15U +# define ADC_IVS_TO_MSK BIT(ADC_IVS_TO_POS) +# define ADC_IVS_TO ADC_IVS_TO_MSK + +# define ADC_IVS_AWDF_POS 7U +# define ADC_IVS_AWDF_MSK BIT(ADC_IVS_AWDF_POS) +# define ADC_IVS_AWDF ADC_IVS_AWDF_MSK + +# define ADC_IVS_ISE_POS 6U +# define ADC_IVS_ISE_MSK BIT(ADC_IVS_ISE_POS) +# define ADC_IVS_ISE ADC_IVS_ISE_MSK + +# define ADC_IVS_ICHE_POS 5U +# define ADC_IVS_ICHE_MSK BIT(ADC_IVS_ICHE_POS) +# define ADC_IVS_ICHE ADC_IVS_ICHE_MSK + +# define ADC_IVS_OVR_POS 4U +# define ADC_IVS_OVR_MSK BIT(ADC_IVS_OVR_POS) +# define ADC_IVS_OVR ADC_IVS_OVR_MSK + +# define ADC_IVS_NSE_POS 3U +# define ADC_IVS_NSE_MSK BIT(ADC_IVS_NSE_POS) +# define ADC_IVS_NSE ADC_IVS_NSE_MSK + +# define ADC_IVS_NCHE_POS 2U +# define ADC_IVS_NCHE_MSK BIT(ADC_IVS_NCHE_POS) +# define ADC_IVS_NCHE ADC_IVS_NCHE_MSK + +# define ADC_IVS_SMPE_POS 1U +# define ADC_IVS_SMPE_MSK BIT(ADC_IVS_SMPE_POS) +# define ADC_IVS_SMPE ADC_IVS_SMPE_MSK + +# define ADC_IVS_ARDY_POS 0U +# define ADC_IVS_ARDY_MSK BIT(ADC_IVS_ARDY_POS) +# define ADC_IVS_ARDY ADC_IVS_ARDY_MSK + +/****************** Bit definition for ADC_RIF register ************************/ + +# define ADC_RIF_TO_POS 15U +# define ADC_RIF_TO_MSK BIT(ADC_RIF_TO_POS) +# define ADC_RIF_TO ADC_RIF_TO_MSK + +# define ADC_RIF_AWDF_POS 7U +# define ADC_RIF_AWDF_MSK BIT(ADC_RIF_AWDF_POS) +# define ADC_RIF_AWDF ADC_RIF_AWDF_MSK + +# define ADC_RIF_ISE_POS 6U +# define ADC_RIF_ISE_MSK BIT(ADC_RIF_ISE_POS) +# define ADC_RIF_ISE ADC_RIF_ISE_MSK + +# define ADC_RIF_ICHE_POS 5U +# define ADC_RIF_ICHE_MSK BIT(ADC_RIF_ICHE_POS) +# define ADC_RIF_ICHE ADC_RIF_ICHE_MSK + +# define ADC_RIF_OVR_POS 4U +# define ADC_RIF_OVR_MSK BIT(ADC_RIF_OVR_POS) +# define ADC_RIF_OVR ADC_RIF_OVR_MSK + +# define ADC_RIF_NSE_POS 3U +# define ADC_RIF_NSE_MSK BIT(ADC_RIF_NSE_POS) +# define ADC_RIF_NSE ADC_RIF_NSE_MSK + +# define ADC_RIF_NCHE_POS 2U +# define ADC_RIF_NCHE_MSK BIT(ADC_RIF_NCHE_POS) +# define ADC_RIF_NCHE ADC_RIF_NCHE_MSK + +# define ADC_RIF_SMPE_POS 1U +# define ADC_RIF_SMPE_MSK BIT(ADC_RIF_SMPE_POS) +# define ADC_RIF_SMPE ADC_RIF_SMPE_MSK + +# define ADC_RIF_ARDY_POS 0U +# define ADC_RIF_ARDY_MSK BIT(ADC_RIF_ARDY_POS) +# define ADC_RIF_ARDY ADC_RIF_ARDY_MSK + +/****************** Bit definition for ADC_IFM register ************************/ + +# define ADC_IFM_TO_POS 15U +# define ADC_IFM_TO_MSK BIT(ADC_IFM_TO_POS) +# define ADC_IFM_TO ADC_IFM_TO_MSK + +# define ADC_IFM_AWDF_POS 7U +# define ADC_IFM_AWDF_MSK BIT(ADC_IFM_AWDF_POS) +# define ADC_IFM_AWDF ADC_IFM_AWDF_MSK + +# define ADC_IFM_ISE_POS 6U +# define ADC_IFM_ISE_MSK BIT(ADC_IFM_ISE_POS) +# define ADC_IFM_ISE ADC_IFM_ISE_MSK + +# define ADC_IFM_ICHE_POS 5U +# define ADC_IFM_ICHE_MSK BIT(ADC_IFM_ICHE_POS) +# define ADC_IFM_ICHE ADC_IFM_ICHE_MSK + +# define ADC_IFM_OVR_POS 4U +# define ADC_IFM_OVR_MSK BIT(ADC_IFM_OVR_POS) +# define ADC_IFM_OVR ADC_IFM_OVR_MSK + +# define ADC_IFM_NSE_POS 3U +# define ADC_IFM_NSE_MSK BIT(ADC_IFM_NSE_POS) +# define ADC_IFM_NSE ADC_IFM_NSE_MSK + +# define ADC_IFM_NCHE_POS 2U +# define ADC_IFM_NCHE_MSK BIT(ADC_IFM_NCHE_POS) +# define ADC_IFM_NCHE ADC_IFM_NCHE_MSK + +# define ADC_IFM_SMPE_POS 1U +# define ADC_IFM_SMPE_MSK BIT(ADC_IFM_SMPE_POS) +# define ADC_IFM_SMPE ADC_IFM_SMPE_MSK + +# define ADC_IFM_ARDY_POS 0U +# define ADC_IFM_ARDY_MSK BIT(ADC_IFM_ARDY_POS) +# define ADC_IFM_ARDY ADC_IFM_ARDY_MSK + +/****************** Bit definition for ADC_ICR register ************************/ + +# define ADC_ICR_TO_POS 15U +# define ADC_ICR_TO_MSK BIT(ADC_ICR_TO_POS) +# define ADC_ICR_TO ADC_ICR_TO_MSK + +# define ADC_ICR_AWDF_POS 7U +# define ADC_ICR_AWDF_MSK BIT(ADC_ICR_AWDF_POS) +# define ADC_ICR_AWDF ADC_ICR_AWDF_MSK + +# define ADC_ICR_ISE_POS 6U +# define ADC_ICR_ISE_MSK BIT(ADC_ICR_ISE_POS) +# define ADC_ICR_ISE ADC_ICR_ISE_MSK + +# define ADC_ICR_ICHE_POS 5U +# define ADC_ICR_ICHE_MSK BIT(ADC_ICR_ICHE_POS) +# define ADC_ICR_ICHE ADC_ICR_ICHE_MSK + +# define ADC_ICR_OVR_POS 4U +# define ADC_ICR_OVR_MSK BIT(ADC_ICR_OVR_POS) +# define ADC_ICR_OVR ADC_ICR_OVR_MSK + +# define ADC_ICR_NSE_POS 3U +# define ADC_ICR_NSE_MSK BIT(ADC_ICR_NSE_POS) +# define ADC_ICR_NSE ADC_ICR_NSE_MSK + +# define ADC_ICR_NCHE_POS 2U +# define ADC_ICR_NCHE_MSK BIT(ADC_ICR_NCHE_POS) +# define ADC_ICR_NCHE ADC_ICR_NCHE_MSK + +# define ADC_ICR_SMPE_POS 1U +# define ADC_ICR_SMPE_MSK BIT(ADC_ICR_SMPE_POS) +# define ADC_ICR_SMPE ADC_ICR_SMPE_MSK + +# define ADC_ICR_ARDY_POS 0U +# define ADC_ICR_ARDY_MSK BIT(ADC_ICR_ARDY_POS) +# define ADC_ICR_ARDY ADC_ICR_ARDY_MSK + +/****************** Bit definition for ADC_CON register ************************/ + +# define ADC_CON_ADCAL_POS 31U +# define ADC_CON_ADCAL_MSK BIT(ADC_CON_ADCAL_POS) +# define ADC_CON_ADCAL ADC_CON_ADCAL_MSK + +# define ADC_CON_DLYDATA_POS 7U +# define ADC_CON_DLYDATA_MSK BIT(ADC_CON_DLYDATA_POS) +# define ADC_CON_DLYDATA ADC_CON_DLYDATA_MSK + +# define ADC_CON_ISTPC_POS 5U +# define ADC_CON_ISTPC_MSK BIT(ADC_CON_ISTPC_POS) +# define ADC_CON_ISTPC ADC_CON_ISTPC_MSK + +# define ADC_CON_NSTPC_POS 4U +# define ADC_CON_NSTPC_MSK BIT(ADC_CON_NSTPC_POS) +# define ADC_CON_NSTPC ADC_CON_NSTPC_MSK + +# define ADC_CON_ISTART_POS 3U +# define ADC_CON_ISTART_MSK BIT(ADC_CON_ISTART_POS) +# define ADC_CON_ISTART ADC_CON_ISTART_MSK + +# define ADC_CON_NSTART_POS 2U +# define ADC_CON_NSTART_MSK BIT(ADC_CON_NSTART_POS) +# define ADC_CON_NSTART ADC_CON_NSTART_MSK + +# define ADC_CON_ADCDIS_POS 1U +# define ADC_CON_ADCDIS_MSK BIT(ADC_CON_ADCDIS_POS) +# define ADC_CON_ADCDIS ADC_CON_ADCDIS_MSK + +# define ADC_CON_ADCEN_POS 0U +# define ADC_CON_ADCEN_MSK BIT(ADC_CON_ADCEN_POS) +# define ADC_CON_ADCEN ADC_CON_ADCEN_MSK + +/****************** Bit definition for ADC_CFG register ************************/ + +# define ADC_CFG_AWDCH_POSS 26U +# define ADC_CFG_AWDCH_POSE 30U +# define ADC_CFG_AWDCH_MSK BITS(ADC_CFG_AWDCH_POSS, ADC_CFG_AWDCH_POSE) +# define ADC_CFG_AWDCH ADC_CFG_AWDCH_MSK + +# define ADC_CFG_IAUTO_POS 25U +# define ADC_CFG_IAUTO_MSK BIT(ADC_CFG_IAUTO_POS) +# define ADC_CFG_IAUTO ADC_CFG_IAUTO_MSK + +# define ADC_CFG_IAWDEN_POS 24U +# define ADC_CFG_IAWDEN_MSK BIT(ADC_CFG_IAWDEN_POS) +# define ADC_CFG_IAWDEN ADC_CFG_IAWDEN_MSK + +# define ADC_CFG_NAWDEN_POS 23U +# define ADC_CFG_NAWDEN_MSK BIT(ADC_CFG_NAWDEN_POS) +# define ADC_CFG_NAWDEN ADC_CFG_NAWDEN_MSK + +# define ADC_CFG_AWDSGL_POS 22U +# define ADC_CFG_AWDSGL_MSK BIT(ADC_CFG_AWDSGL_POS) +# define ADC_CFG_AWDSGL ADC_CFG_AWDSGL_MSK + +# define ADC_CFG_ICHDCEN_POS 20U +# define ADC_CFG_ICHDCEN_MSK BIT(ADC_CFG_ICHDCEN_POS) +# define ADC_CFG_ICHDCEN ADC_CFG_ICHDCEN_MSK + +# define ADC_CFG_ETRGN_POSS 17U +# define ADC_CFG_ETRGN_POSE 19U +# define ADC_CFG_ETRGN_MSK BITS(ADC_CFG_ETRGN_POSS, ADC_CFG_ETRGN_POSE) +# define ADC_CFG_ETRGN ADC_CFG_ETRGN_MSK + +# define ADC_CFG_NCHDCEN_POS 16U +# define ADC_CFG_NCHDCEN_MSK BIT(ADC_CFG_NCHDCEN_POS) +# define ADC_CFG_NCHDCEN ADC_CFG_NCHDCEN_MSK + +# define ADC_CFG_AUTOFF_POS 15U +# define ADC_CFG_AUTOFF_MSK BIT(ADC_CFG_AUTOFF_POS) +# define ADC_CFG_AUTOFF ADC_CFG_AUTOFF_MSK + +# define ADC_CFG_AUTODLY_POS 14U +# define ADC_CFG_AUTODLY_MSK BIT(ADC_CFG_AUTODLY_POS) +# define ADC_CFG_AUTODLY ADC_CFG_AUTODLY_MSK + +# define ADC_CFG_CM_POS 13U +# define ADC_CFG_CM_MSK BIT(ADC_CFG_CM_POS) +# define ADC_CFG_CM ADC_CFG_CM_MSK + +# define ADC_CFG_OVRMOD_POS 12U +# define ADC_CFG_OVRMOD_MSK BIT(ADC_CFG_OVRMOD_POS) +# define ADC_CFG_OVRMOD ADC_CFG_OVRMOD_MSK + +# define ADC_CFG_NETS_POSS 10U +# define ADC_CFG_NETS_POSE 11U +# define ADC_CFG_NETS_MSK BITS(ADC_CFG_NETS_POSS, ADC_CFG_NETS_POSE) +# define ADC_CFG_NETS ADC_CFG_NETS_MSK + +# define ADC_CFG_NEXTSEL_POSS 6U +# define ADC_CFG_NEXTSEL_POSE 9U +# define ADC_CFG_NEXTSEL_MSK BITS(ADC_CFG_NEXTSEL_POSS, ADC_CFG_NEXTSEL_POSE) +# define ADC_CFG_NEXTSEL ADC_CFG_NEXTSEL_MSK + +# define ADC_CFG_ALIGN_POS 5U +# define ADC_CFG_ALIGN_MSK BIT(ADC_CFG_ALIGN_POS) +# define ADC_CFG_ALIGN ADC_CFG_ALIGN_MSK + +# define ADC_CFG_RSEL_POSS 3U +# define ADC_CFG_RSEL_POSE 4U +# define ADC_CFG_RSEL_MSK BITS(ADC_CFG_RSEL_POSS, ADC_CFG_RSEL_POSE) +# define ADC_CFG_RSEL ADC_CFG_RSEL_MSK + +# define ADC_CFG_DMAEN_POS 0U +# define ADC_CFG_DMAEN_MSK BIT(ADC_CFG_DMAEN_POS) +# define ADC_CFG_DMAEN ADC_CFG_DMAEN_MSK + +/****************** Bit definition for ADC_SMPT1 register ************************/ + +# define ADC_SMPT1_CHTy_POSS 8U +# define ADC_SMPT1_CHTy_POSE 31U +# define ADC_SMPT1_CHTy_MSK BITS(ADC_SMPT1_CHTy_POSS, ADC_SMPT1_CHTy_POSE) +# define ADC_SMPT1_CHTy ADC_SMPT1_CHTy_MSK + +# define ADC_SMPT1_CHT2_POSS 24U +# define ADC_SMPT1_CHT2_POSE 31U +# define ADC_SMPT1_CHT2_MSK BITS(ADC_SMPT1_CHT2_POSS, ADC_SMPT1_CHT2_POSE) +# define ADC_SMPT1_CHT2 ADC_SMPT1_CHT2_MSK + +# define ADC_SMPT1_CHT1_POSS 16U +# define ADC_SMPT1_CHT1_POSE 23U +# define ADC_SMPT1_CHT1_MSK BITS(ADC_SMPT1_CHT1_POSS, ADC_SMPT1_CHT1_POSE) +# define ADC_SMPT1_CHT1 ADC_SMPT1_CHT1_MSK + +# define ADC_SMPT1_CHT0_POSS 8U +# define ADC_SMPT1_CHT0_POSE 15U +# define ADC_SMPT1_CHT0_MSK BITS(ADC_SMPT1_CHT0_POSS, ADC_SMPT1_CHT0_POSE) +# define ADC_SMPT1_CHT0 ADC_SMPT1_CHT0_MSK + +# define ADC_SMPT1_CKDIV_POSS 0U +# define ADC_SMPT1_CKDIV_POSE 2U +# define ADC_SMPT1_CKDIV_MSK BITS(ADC_SMPT1_CKDIV_POSS, ADC_SMPT1_CKDIV_POSE) +# define ADC_SMPT1_CKDIV ADC_SMPT1_CKDIV_MSK + +/****************** Bit definition for ADC_SMPT2 register ************************/ + +# define ADC_SMPT2_CHTy_POSS 0U +# define ADC_SMPT2_CHTy_POSE 31U +# define ADC_SMPT2_CHTy_MSK BITS(ADC_SMPT2_CHTy_POSS, ADC_SMPT2_CHTy_POSE) +# define ADC_SMPT2_CHTy ADC_SMPT2_CHTy_MSK + +# define ADC_SMPT2_CHT6_POSS 24U +# define ADC_SMPT2_CHT6_POSE 31U +# define ADC_SMPT2_CHT6_MSK BITS(ADC_SMPT2_CHT6_POSS, ADC_SMPT2_CHT6_POSE) +# define ADC_SMPT2_CHT6 ADC_SMPT2_CHT6_MSK + +# define ADC_SMPT2_CHT5_POSS 16U +# define ADC_SMPT2_CHT5_POSE 23U +# define ADC_SMPT2_CHT5_MSK BITS(ADC_SMPT2_CHT5_POSS, ADC_SMPT2_CHT5_POSE) +# define ADC_SMPT2_CHT5 ADC_SMPT2_CHT5_MSK + +# define ADC_SMPT2_CHT4_POSS 8U +# define ADC_SMPT2_CHT4_POSE 15U +# define ADC_SMPT2_CHT4_MSK BITS(ADC_SMPT2_CHT4_POSS, ADC_SMPT2_CHT4_POSE) +# define ADC_SMPT2_CHT4 ADC_SMPT2_CHT4_MSK + +# define ADC_SMPT2_CHT3_POSS 0U +# define ADC_SMPT2_CHT3_POSE 7U +# define ADC_SMPT2_CHT3_MSK BITS(ADC_SMPT2_CHT3_POSS, ADC_SMPT2_CHT3_POSE) +# define ADC_SMPT2_CHT3 ADC_SMPT2_CHT3_MSK + +/****************** Bit definition for ADC_SMPT3 register ************************/ + +# define ADC_SMPT3_CHTy_POSS 0U +# define ADC_SMPT3_CHTy_POSE 31U +# define ADC_SMPT3_CHTy_MSK BITS(ADC_SMPT3_CHTy_POSS, ADC_SMPT3_CHTy_POSE) +# define ADC_SMPT3_CHTy ADC_SMPT3_CHTy_MSK + +# define ADC_SMPT3_CHT10_POSS 24U +# define ADC_SMPT3_CHT10_POSE 31U +# define ADC_SMPT3_CHT10_MSK BITS(ADC_SMPT3_CHT10_POSS, ADC_SMPT3_CHT10_POSE) +# define ADC_SMPT3_CHT10 ADC_SMPT3_CHT10_MSK + +# define ADC_SMPT3_CHT9_POSS 16U +# define ADC_SMPT3_CHT9_POSE 23U +# define ADC_SMPT3_CHT9_MSK BITS(ADC_SMPT3_CHT9_POSS, ADC_SMPT3_CHT9_POSE) +# define ADC_SMPT3_CHT9 ADC_SMPT3_CHT9_MSK + +# define ADC_SMPT3_CHT8_POSS 8U +# define ADC_SMPT3_CHT8_POSE 15U +# define ADC_SMPT3_CHT8_MSK BITS(ADC_SMPT3_CHT8_POSS, ADC_SMPT3_CHT8_POSE) +# define ADC_SMPT3_CHT8 ADC_SMPT3_CHT8_MSK + +# define ADC_SMPT3_CHT7_POSS 0U +# define ADC_SMPT3_CHT7_POSE 7U +# define ADC_SMPT3_CHT7_MSK BITS(ADC_SMPT3_CHT7_POSS, ADC_SMPT3_CHT7_POSE) +# define ADC_SMPT3_CHT7 ADC_SMPT3_CHT7_MSK + +/****************** Bit definition for ADC_SMPT4 register ************************/ + +# define ADC_SMPT4_CHTy_POSS 0U +# define ADC_SMPT4_CHTy_POSE 31U +# define ADC_SMPT4_CHTy_MSK BITS(ADC_SMPT4_CHTy_POSS, ADC_SMPT4_CHTy_POSE) +# define ADC_SMPT4_CHTy ADC_SMPT4_CHTy_MSK + +# define ADC_SMPT4_CHT14_POSS 24U +# define ADC_SMPT4_CHT14_POSE 31U +# define ADC_SMPT4_CHT14_MSK BITS(ADC_SMPT4_CHT14_POSS, ADC_SMPT4_CHT14_POSE) +# define ADC_SMPT4_CHT14 ADC_SMPT4_CHT14_MSK + +# define ADC_SMPT4_CHT13_POSS 16U +# define ADC_SMPT4_CHT13_POSE 23U +# define ADC_SMPT4_CHT13_MSK BITS(ADC_SMPT4_CHT13_POSS, ADC_SMPT4_CHT13_POSE) +# define ADC_SMPT4_CHT13 ADC_SMPT4_CHT13_MSK + +# define ADC_SMPT4_CHT12_POSS 8U +# define ADC_SMPT4_CHT12_POSE 15U +# define ADC_SMPT4_CHT12_MSK BITS(ADC_SMPT4_CHT12_POSS, ADC_SMPT4_CHT12_POSE) +# define ADC_SMPT4_CHT12 ADC_SMPT4_CHT12_MSK + +# define ADC_SMPT4_CHT11_POSS 0U +# define ADC_SMPT4_CHT11_POSE 7U +# define ADC_SMPT4_CHT11_MSK BITS(ADC_SMPT4_CHT11_POSS, ADC_SMPT4_CHT11_POSE) +# define ADC_SMPT4_CHT11 ADC_SMPT4_CHT11_MSK + +/****************** Bit definition for ADC_SMPT5 register ************************/ + +# define ADC_SMPT5_CHTy_POSS 0U +# define ADC_SMPT5_CHTy_POSE 31U +# define ADC_SMPT5_CHTy_MSK BITS(ADC_SMPT5_CHTy_POSS, ADC_SMPT5_CHTy_POSE) +# define ADC_SMPT5_CHTy ADC_SMPT5_CHTy_MSK + +# define ADC_SMPT5_CHT18_POSS 24U +# define ADC_SMPT5_CHT18_POSE 31U +# define ADC_SMPT5_CHT18_MSK BITS(ADC_SMPT5_CHT18_POSS, ADC_SMPT5_CHT18_POSE) +# define ADC_SMPT5_CHT18 ADC_SMPT5_CHT18_MSK + +# define ADC_SMPT5_CHT17_POSS 16U +# define ADC_SMPT5_CHT17_POSE 23U +# define ADC_SMPT5_CHT17_MSK BITS(ADC_SMPT5_CHT17_POSS, ADC_SMPT5_CHT17_POSE) +# define ADC_SMPT5_CHT17 ADC_SMPT5_CHT17_MSK + +# define ADC_SMPT5_CHT16_POSS 8U +# define ADC_SMPT5_CHT16_POSE 15U +# define ADC_SMPT5_CHT16_MSK BITS(ADC_SMPT5_CHT16_POSS, ADC_SMPT5_CHT16_POSE) +# define ADC_SMPT5_CHT16 ADC_SMPT5_CHT16_MSK + +# define ADC_SMPT5_CHT15_POSS 0U +# define ADC_SMPT5_CHT15_POSE 7U +# define ADC_SMPT5_CHT15_MSK BITS(ADC_SMPT5_CHT15_POSS, ADC_SMPT5_CHT15_POSE) +# define ADC_SMPT5_CHT15 ADC_SMPT5_CHT15_MSK + +/****************** Bit definition for ADC_WDTH register ************************/ + +# define ADC_WDTH_HT_POSS 16U +# define ADC_WDTH_HT_POSE 27U +# define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS, ADC_WDTH_HT_POSE) +# define ADC_WDTH_HT ADC_WDTH_HT_MSK + +# define ADC_WDTH_LT_POSS 0U +# define ADC_WDTH_LT_POSE 11U +# define ADC_WDTH_LT_MSK BITS(ADC_WDTH_LT_POSS, ADC_WDTH_LT_POSE) +# define ADC_WDTH_LT ADC_WDTH_LT_MSK + +/****************** Bit definition for ADC_NCHS1 register ************************/ + +# define ADC_NCHS1_NS4_POSS 24U +# define ADC_NCHS1_NS4_POSE 28U +# define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS, ADC_NCHS1_NS4_POSE) +# define ADC_NCHS1_NS4 ADC_NCHS1_NS4_MSK + +# define ADC_NCHS1_NS3_POSS 18U +# define ADC_NCHS1_NS3_POSE 22U +# define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS, ADC_NCHS1_NS3_POSE) +# define ADC_NCHS1_NS3 ADC_NCHS1_NS3_MSK + +# define ADC_NCHS1_NS2_POSS 12U +# define ADC_NCHS1_NS2_POSE 16U +# define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS, ADC_NCHS1_NS2_POSE) +# define ADC_NCHS1_NS2 ADC_NCHS1_NS2_MSK + +# define ADC_NCHS1_NS1_POSS 6U +# define ADC_NCHS1_NS1_POSE 10U +# define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS, ADC_NCHS1_NS1_POSE) +# define ADC_NCHS1_NS1 ADC_NCHS1_NS1_MSK + +# define ADC_NCHS1_NSL_POSS 0U +# define ADC_NCHS1_NSL_POSE 3U +# define ADC_NCHS1_NSL_MSK BITS(ADC_NCHS1_NSL_POSS, ADC_NCHS1_NSL_POSE) +# define ADC_NCHS1_NSL ADC_NCHS1_NSL_MSK + +/****************** Bit definition for ADC_NCHS2 register ************************/ + +# define ADC_NCHS2_NS9_POSS 24U +# define ADC_NCHS2_NS9_POSE 28U +# define ADC_NCHS2_NS9_MSK BITS(ADC_NCHS2_NS9_POSS, ADC_NCHS2_NS9_POSE) +# define ADC_NCHS2_NS9 ADC_NCHS2_NS9_MSK + +# define ADC_NCHS2_NS8_POSS 18U +# define ADC_NCHS2_NS8_POSE 22U +# define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS, ADC_NCHS2_NS8_POSE) +# define ADC_NCHS2_NS8 ADC_NCHS2_NS8_MSK + +# define ADC_NCHS2_NS7_POSS 12U +# define ADC_NCHS2_NS7_POSE 16U +# define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS, ADC_NCHS2_NS7_POSE) +# define ADC_NCHS2_NS7 ADC_NCHS2_NS7_MSK + +# define ADC_NCHS2_NS6_POSS 6U +# define ADC_NCHS2_NS6_POSE 10U +# define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS, ADC_NCHS2_NS6_POSE) +# define ADC_NCHS2_NS6 ADC_NCHS2_NS6_MSK + +# define ADC_NCHS2_NS5_POSS 0U +# define ADC_NCHS2_NS5_POSE 4U +# define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS, ADC_NCHS2_NS5_POSE) +# define ADC_NCHS2_NS5 ADC_NCHS2_NS5_MSK + +/****************** Bit definition for ADC_NCHS3 register ************************/ + +# define ADC_NCHS3_NS14_POSS 24U +# define ADC_NCHS3_NS14_POSE 28U +# define ADC_NCHS3_NS14_MSK BITS(ADC_NCHS3_NS14_POSS, ADC_NCHS3_NS14_POSE) +# define ADC_NCHS3_NS14 ADC_NCHS3_NS14_MSK + +# define ADC_NCHS3_NS13_POSS 18U +# define ADC_NCHS3_NS13_POSE 22U +# define ADC_NCHS3_NS13_MSK BITS(ADC_NCHS3_NS13_POSS, ADC_NCHS3_NS13_POSE) +# define ADC_NCHS3_NS13 ADC_NCHS3_NS13_MSK + +# define ADC_NCHS3_NS12_POSS 12U +# define ADC_NCHS3_NS12_POSE 16U +# define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS, ADC_NCHS3_NS12_POSE) +# define ADC_NCHS3_NS12 ADC_NCHS3_NS12_MSK + +# define ADC_NCHS3_NS11_POSS 6U +# define ADC_NCHS3_NS11_POSE 10U +# define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS, ADC_NCHS3_NS11_POSE) +# define ADC_NCHS3_NS11 ADC_NCHS3_NS11_MSK + +# define ADC_NCHS3_NS10_POSS 0U +# define ADC_NCHS3_NS10_POSE 4U +# define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS, ADC_NCHS3_NS10_POSE) +# define ADC_NCHS3_NS10 ADC_NCHS3_NS10_MSK + +/****************** Bit definition for ADC_NCHS4 register ************************/ + +# define ADC_NCHS4_NS16_POSS 6U +# define ADC_NCHS4_NS16_POSE 10U +# define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS, ADC_NCHS4_NS16_POSE) +# define ADC_NCHS4_NS16 ADC_NCHS4_NS16_MSK + +# define ADC_NCHS4_NS15_POSS 0U +# define ADC_NCHS4_NS15_POSE 4U +# define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS, ADC_NCHS4_NS15_POSE) +# define ADC_NCHS4_NS15 ADC_NCHS4_NS15_MSK + +/****************** Bit definition for ADC_NCHDR register ************************/ + +# define ADC_NCHDR_VAL_POSS 0U +# define ADC_NCHDR_VAL_POSE 15U +# define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS, ADC_NCHDR_VAL_POSE) +# define ADC_NCHDR_VAL ADC_NCHDR_VAL_MSK + +/****************** Bit definition for ADC_ICHS register ************************/ + +# define ADC_ICHS_IS4_POSS 26U +# define ADC_ICHS_IS4_POSE 30U +# define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS, ADC_ICHS_IS4_POSE) +# define ADC_ICHS_IS4 ADC_ICHS_IS4_MSK + +# define ADC_ICHS_IS3_POSS 20U +# define ADC_ICHS_IS3_POSE 24U +# define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS, ADC_ICHS_IS3_POSE) +# define ADC_ICHS_IS3 ADC_ICHS_IS3_MSK + +# define ADC_ICHS_IS2_POSS 14U +# define ADC_ICHS_IS2_POSE 18U +# define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS, ADC_ICHS_IS2_POSE) +# define ADC_ICHS_IS2 ADC_ICHS_IS2_MSK + +# define ADC_ICHS_IS1_POSS 8U +# define ADC_ICHS_IS1_POSE 12U +# define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS, ADC_ICHS_IS1_POSE) +# define ADC_ICHS_IS1 ADC_ICHS_IS1_MSK + +# define ADC_ICHS_IETS_POSS 6U +# define ADC_ICHS_IETS_POSE 7U +# define ADC_ICHS_IETS_MSK BITS(ADC_ICHS_IETS_POSS, ADC_ICHS_IETS_POSE) +# define ADC_ICHS_IETS ADC_ICHS_IETS_MSK + +# define ADC_ICHS_IEXTSEL_POSS 2U +# define ADC_ICHS_IEXTSEL_POSE 5U +# define ADC_ICHS_IEXTSEL_MSK BITS(ADC_ICHS_IEXTSEL_POSS, ADC_ICHS_IEXTSEL_POSE) +# define ADC_ICHS_IEXTSEL ADC_ICHS_IEXTSEL_MSK + +# define ADC_ICHS_ISL_POSS 0U +# define ADC_ICHS_ISL_POSE 1U +# define ADC_ICHS_ISL_MSK BITS(ADC_ICHS_ISL_POSS, ADC_ICHS_ISL_POSE) +# define ADC_ICHS_ISL ADC_ICHS_ISL_MSK + +/****************** Bit definition for ADC_OFF1 register ************************/ + +# define ADC_OFF1_OFFEN_POS 31U +# define ADC_OFF1_OFFEN_MSK BIT(ADC_OFF1_OFFEN_POS) +# define ADC_OFF1_OFFEN ADC_OFF1_OFFEN_MSK + +# define ADC_OFF1_OFFCH_POSS 26U +# define ADC_OFF1_OFFCH_POSE 30U +# define ADC_OFF1_OFFCH_MSK BITS(ADC_OFF1_OFFCH_POSS, ADC_OFF1_OFFCH_POSE) +# define ADC_OFF1_OFFCH ADC_OFF1_OFFCH_MSK + +# define ADC_OFF1_SATEN_POS 25U +# define ADC_OFF1_SATEN_MSK BIT(ADC_OFF1_SATEN_POS) +# define ADC_OFF1_SATEN ADC_OFF1_SATEN_MSK + +# define ADC_OFF1_OFFPEN_POS 24U +# define ADC_OFF1_OFFPEN_MSK BIT(ADC_OFF1_OFFPEN_POS) +# define ADC_OFF1_OFFPEN ADC_OFF1_OFFPEN_MSK + +# define ADC_OFF1_OFF_POSS 0U +# define ADC_OFF1_OFF_POSE 11U +# define ADC_OFF1_OFF_MSK BITS(ADC_OFF1_OFF_POSS, ADC_OFF1_OFF_POSE) +# define ADC_OFF1_OFF ADC_OFF1_OFF_MSK + +/****************** Bit definition for ADC_OFF2 register ************************/ + +# define ADC_OFF2_OFFEN_POS 31U +# define ADC_OFF2_OFFEN_MSK BIT(ADC_OFF2_OFFEN_POS) +# define ADC_OFF2_OFFEN ADC_OFF2_OFFEN_MSK + +# define ADC_OFF2_OFFCH_POSS 26U +# define ADC_OFF2_OFFCH_POSE 30U +# define ADC_OFF2_OFFCH_MSK BITS(ADC_OFF2_OFFCH_POSS, ADC_OFF2_OFFCH_POSE) +# define ADC_OFF2_OFFCH ADC_OFF2_OFFCH_MSK + +# define ADC_OFF2_SATEN_POS 25U +# define ADC_OFF2_SATEN_MSK BIT(ADC_OFF2_SATEN_POS) +# define ADC_OFF2_SATEN ADC_OFF2_SATEN_MSK + +# define ADC_OFF2_OFFPEN_POS 24U +# define ADC_OFF2_OFFPEN_MSK BIT(ADC_OFF2_OFFPEN_POS) +# define ADC_OFF2_OFFPEN ADC_OFF2_OFFPEN_MSK + +# define ADC_OFF2_OFF_POSS 0U +# define ADC_OFF2_OFF_POSE 11U +# define ADC_OFF2_OFF_MSK BITS(ADC_OFF2_OFF_POSS, ADC_OFF2_OFF_POSE) +# define ADC_OFF2_OFF ADC_OFF2_OFF_MSK + +/****************** Bit definition for ADC_OFF3 register ************************/ + +# define ADC_OFF3_OFFEN_POS 31U +# define ADC_OFF3_OFFEN_MSK BIT(ADC_OFF3_OFFEN_POS) +# define ADC_OFF3_OFFEN ADC_OFF3_OFFEN_MSK + +# define ADC_OFF3_OFFCH_POSS 26U +# define ADC_OFF3_OFFCH_POSE 30U +# define ADC_OFF3_OFFCH_MSK BITS(ADC_OFF3_OFFCH_POSS, ADC_OFF3_OFFCH_POSE) +# define ADC_OFF3_OFFCH ADC_OFF3_OFFCH_MSK + +# define ADC_OFF3_SATEN_POS 25U +# define ADC_OFF3_SATEN_MSK BIT(ADC_OFF3_SATEN_POS) +# define ADC_OFF3_SATEN ADC_OFF3_SATEN_MSK + +# define ADC_OFF3_OFFPEN_POS 24U +# define ADC_OFF3_OFFPEN_MSK BIT(ADC_OFF3_OFFPEN_POS) +# define ADC_OFF3_OFFPEN ADC_OFF3_OFFPEN_MSK + +# define ADC_OFF3_OFF_POSS 0U +# define ADC_OFF3_OFF_POSE 11U +# define ADC_OFF3_OFF_MSK BITS(ADC_OFF3_OFF_POSS, ADC_OFF3_OFF_POSE) +# define ADC_OFF3_OFF ADC_OFF3_OFF_MSK + +/****************** Bit definition for ADC_OFF4 register ************************/ + +# define ADC_OFF4_OFFEN_POS 31U +# define ADC_OFF4_OFFEN_MSK BIT(ADC_OFF4_OFFEN_POS) +# define ADC_OFF4_OFFEN ADC_OFF4_OFFEN_MSK + +# define ADC_OFF4_OFFCH_POSS 26U +# define ADC_OFF4_OFFCH_POSE 30U +# define ADC_OFF4_OFFCH_MSK BITS(ADC_OFF4_OFFCH_POSS, ADC_OFF4_OFFCH_POSE) +# define ADC_OFF4_OFFCH ADC_OFF4_OFFCH_MSK + +# define ADC_OFF4_SATEN_POS 25U +# define ADC_OFF4_SATEN_MSK BIT(ADC_OFF4_SATEN_POS) +# define ADC_OFF4_SATEN ADC_OFF4_SATEN_MSK + +# define ADC_OFF4_OFFPEN_POS 24U +# define ADC_OFF4_OFFPEN_MSK BIT(ADC_OFF4_OFFPEN_POS) +# define ADC_OFF4_OFFPEN ADC_OFF4_OFFPEN_MSK + +# define ADC_OFF4_OFF_POSS 0U +# define ADC_OFF4_OFF_POSE 11U +# define ADC_OFF4_OFF_MSK BITS(ADC_OFF4_OFF_POSS, ADC_OFF4_OFF_POSE) +# define ADC_OFF4_OFF ADC_OFF4_OFF_MSK + +/****************** Bit definition for ADC_ICHDR1 register ************************/ + +# define ADC_ICHDR1_VAL_POSS 0U +# define ADC_ICHDR1_VAL_POSE 15U +# define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS, ADC_ICHDR1_VAL_POSE) +# define ADC_ICHDR1_VAL ADC_ICHDR1_VAL_MSK + +/****************** Bit definition for ADC_ICHDR2 register ************************/ + +# define ADC_ICHDR2_VAL_POSS 0U +# define ADC_ICHDR2_VAL_POSE 15U +# define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS, ADC_ICHDR2_VAL_POSE) +# define ADC_ICHDR2_VAL ADC_ICHDR2_VAL_MSK + +/****************** Bit definition for ADC_ICHDR3 register ************************/ + +# define ADC_ICHDR3_VAL_POSS 0U +# define ADC_ICHDR3_VAL_POSE 15U +# define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS, ADC_ICHDR3_VAL_POSE) +# define ADC_ICHDR3_VAL ADC_ICHDR3_VAL_MSK + +/****************** Bit definition for ADC_ICHDR4 register ************************/ + +# define ADC_ICHDR4_VAL_POSS 0U +# define ADC_ICHDR4_VAL_POSE 15U +# define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS, ADC_ICHDR4_VAL_POSE) +# define ADC_ICHDR4_VAL ADC_ICHDR4_VAL_MSK + +/****************** Bit definition for ADC_CALCR register ************************/ + +# define ADC_CALCR_OCOMCOE_POSS 16U +# define ADC_CALCR_OCOMCOE_POSE 23U +# define ADC_CALCR_OCOMCOE_MSK BITS(ADC_CALCR_OCOMCOE_POSS, ADC_CALCR_OCOMCOE_POSE) +# define ADC_CALCR_OCOMCOE ADC_CALCR_OCOMCOE_MSK + +# define ADC_CALCR_GCOMCOE_POSS 0U +# define ADC_CALCR_GCOMCOE_POSE 11U +# define ADC_CALCR_GCOMCOE_MSK BITS(ADC_CALCR_GCOMCOE_POSS, ADC_CALCR_GCOMCOE_POSE) +# define ADC_CALCR_GCOMCOE ADC_CALCR_GCOMCOE_MSK + +/****************** Bit definition for ADC_CCR register ************************/ + +# define ADC_CCR_REFINTS_POSS 24U +# define ADC_CCR_REFINTS_POSE 26U +# define ADC_CCR_REFINTS_MSK BITS(ADC_CCR_REFINTS_POSS, ADC_CCR_REFINTS_POSE) +# define ADC_CCR_REFINTS ADC_CCR_REFINTS_MSK + +/****************** Bit definition for ADC_SR register ************************/ + +# define ADC_SR_NDRE_POS 2U +# define ADC_SR_NDRE_MSK BIT(ADC_SR_NDRE_POS) +# define ADC_SR_NDRE ADC_SR_NDRE_MSK + +typedef struct +{ + __O uint32_t IER; // 0x000 + __O uint32_t IDR; // 0x004 + __I uint32_t IVS; // 0x008 + __I uint32_t RIF; // 0x00c + __I uint32_t IFM; // 0x010 + __O uint32_t ICR; // 0x014 + __IO uint32_t CON; // 0x018 + __IO uint32_t CFG; // 0x01c + __IO uint32_t SMPT1; // 0x020 + __IO uint32_t SMPT2; // 0x024 + __IO uint32_t SMPT3; // 0x028 + __IO uint32_t SMPT4; // 0x02c + __IO uint32_t SMPT5; // 0x030 + __IO uint32_t RESERVED0[2]; // 0x034-0x038 + __IO uint32_t WDTH; // 0x03c + __IO uint32_t NCHS1; // 0x040 + __IO uint32_t NCHS2; // 0x044 + __IO uint32_t NCHS3; // 0x048 + __IO uint32_t NCHS4; // 0x04c + __I uint32_t NCHDR; // 0x050 + __IO uint32_t ICHS; // 0x054 + __IO uint32_t OFF1; // 0x058 + __IO uint32_t OFF2; // 0x05c + __IO uint32_t OFF3; // 0x060 + __IO uint32_t OFF4; // 0x064 + __I uint32_t ICHDR1; // 0x068 + __I uint32_t ICHDR2; // 0x06c + __I uint32_t ICHDR3; // 0x070 + __I uint32_t ICHDR4; // 0x074 + __IO uint32_t CALCR; // 0x078 + __IO uint32_t CCR; // 0x07c + __I uint32_t SR; // 0x080 +} ADC_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_aes.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_aes.h new file mode 100644 index 00000000000..4bcd6c351bb --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_aes.h @@ -0,0 +1,237 @@ +/********************************************************************************** + * + * @file reg_aes.h + * @brief AES Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __AES_H__ +#define __AES_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +////#pragma anon_unions + +/****************** Bit definition for AES_CON register ************************/ + +#define AES_CON_READY_POS 22U +#define AES_CON_READY_MSK BIT(AES_CON_READY_POS) +#define AES_CON_READY AES_CON_READY_MSK + +#define AES_CON_OT_DMA_ST_POS 21U +#define AES_CON_OT_DMA_ST_MSK BIT(AES_CON_OT_DMA_ST_POS) +#define AES_CON_OT_DMA_ST AES_CON_OT_DMA_ST_MSK + +#define AES_CON_IT_DMA_ST_POS 20U +#define AES_CON_IT_DMA_ST_MSK BIT(AES_CON_IT_DMA_ST_POS) +#define AES_CON_IT_DMA_ST AES_CON_IT_DMA_ST_MSK + +#define AES_CON_OT_DEPTH_POSS 18U +#define AES_CON_OT_DEPTH_POSE 19U +#define AES_CON_OT_DEPTH_MSK BITS(AES_CON_OT_DEPTH_POSS,AES_CON_OT_DEPTH_POSE) +#define AES_CON_OT_DEPTH AES_CON_OT_DEPTH_MSK + +#define AES_CON_IT_DEPTH_POSS 16U +#define AES_CON_IT_DEPTH_POSE 17U +#define AES_CON_IT_DEPTH_MSK BITS(AES_CON_IT_DEPTH_POSS,AES_CON_IT_DEPTH_POSE) +#define AES_CON_IT_DEPTH AES_CON_IT_DEPTH_MSK + +#define AES_CON_RE_INIT_POS 8U +#define AES_CON_RE_INIT_MSK BIT(AES_CON_RE_INIT_POS) +#define AES_CON_RE_INIT AES_CON_RE_INIT_MSK + +#define AES_CON_DMA_EN_POSS 6U +#define AES_CON_DMA_EN_POSE 7U +#define AES_CON_DMA_EN_MSK BITS(AES_CON_DMA_EN_POSS,AES_CON_DMA_EN_POSE) +#define AES_CON_DMA_EN AES_CON_DMA_EN_MSK + +#define AES_CON_BL_POSS 3U +#define AES_CON_BL_POSE 5U +#define AES_CON_BL_MSK BITS(AES_CON_BL_POSS,AES_CON_BL_POSE) +#define AES_CON_BL AES_CON_BL_MSK + +#define AES_CON_REV_POS 2U +#define AES_CON_REV_MSK BIT(AES_CON_REV_POS) +#define AES_CON_REV AES_CON_REV_MSK + +#define AES_CON_MODE_POS 1U +#define AES_CON_MODE_MSK BIT(AES_CON_MODE_POS) +#define AES_CON_MODE AES_CON_MODE_MSK + +#define AES_CON_START_POS 0U +#define AES_CON_START_MSK BIT(AES_CON_START_POS) +#define AES_CON_START AES_CON_START_MSK + +/****************** Bit definition for AES_IER register ************************/ + +#define AES_IER_DEC_POS 1U +#define AES_IER_DEC_MSK BIT(AES_IER_DEC_POS) +#define AES_IER_DEC AES_IER_DEC_MSK + +#define AES_IER_ENC_POS 0U +#define AES_IER_ENC_MSK BIT(AES_IER_ENC_POS) +#define AES_IER_ENC AES_IER_ENC_MSK + +/****************** Bit definition for AES_IDR register ************************/ + +#define AES_IDR_DEC_POS 1U +#define AES_IDR_DEC_MSK BIT(AES_IDR_DEC_POS) +#define AES_IDR_DEC AES_IDR_DEC_MSK + +#define AES_IDR_ENC_POS 0U +#define AES_IDR_ENC_MSK BIT(AES_IDR_ENC_POS) +#define AES_IDR_ENC AES_IDR_ENC_MSK + +/****************** Bit definition for AES_IVS register ************************/ + +#define AES_IVS_DEC_POS 1U +#define AES_IVS_DEC_MSK BIT(AES_IVS_DEC_POS) +#define AES_IVS_DEC AES_IVS_DEC_MSK + +#define AES_IVS_ENC_POS 0U +#define AES_IVS_ENC_MSK BIT(AES_IVS_ENC_POS) +#define AES_IVS_ENC AES_IVS_ENC_MSK + +/****************** Bit definition for AES_RIF register ************************/ + +#define AES_RIF_DEC_POS 1U +#define AES_RIF_DEC_MSK BIT(AES_RIF_DEC_POS) +#define AES_RIF_DEC AES_RIF_DEC_MSK + +#define AES_RIF_ENC_POS 0U +#define AES_RIF_ENC_MSK BIT(AES_RIF_ENC_POS) +#define AES_RIF_ENC AES_RIF_ENC_MSK + +/****************** Bit definition for AES_IFM register ************************/ + +#define AES_IFM_DEC_POS 1U +#define AES_IFM_DEC_MSK BIT(AES_IFM_DEC_POS) +#define AES_IFM_DEC AES_IFM_DEC_MSK + +#define AES_IFM_ENC_POS 0U +#define AES_IFM_ENC_MSK BIT(AES_IFM_ENC_POS) +#define AES_IFM_ENC AES_IFM_ENC_MSK + +/****************** Bit definition for AES_ICR register ************************/ + +#define AES_ICR_DEC_POS 1U +#define AES_ICR_DEC_MSK BIT(AES_ICR_DEC_POS) +#define AES_ICR_DEC AES_ICR_DEC_MSK + +#define AES_ICR_ENC_POS 0U +#define AES_ICR_ENC_MSK BIT(AES_ICR_ENC_POS) +#define AES_ICR_ENC AES_ICR_ENC_MSK + +/****************** Bit definition for AES_DIO register ************************/ + +#define AES_DIO_DIO_POSS 0U +#define AES_DIO_DIO_POSE 31U +#define AES_DIO_DIO_MSK BITS(AES_DIO_DIO_POSS,AES_DIO_DIO_POSE) +#define AES_DIO_DIO AES_DIO_DIO_MSK + +/****************** Bit definition for AES_KEY0 register ************************/ + +#define AES_KEY0_KEY0_POSS 0U +#define AES_KEY0_KEY0_POSE 31U +#define AES_KEY0_KEY0_MSK BITS(AES_KEY0_KEY0_POSS,AES_KEY0_KEY0_POSE) +#define AES_KEY0_KEY0 AES_KEY0_KEY0_MSK + +/****************** Bit definition for AES_KEY1 register ************************/ + +#define AES_KEY1_KEY1_POSS 0U +#define AES_KEY1_KEY1_POSE 31U +#define AES_KEY1_KEY1_MSK BITS(AES_KEY1_KEY1_POSS,AES_KEY1_KEY1_POSE) +#define AES_KEY1_KEY1 AES_KEY1_KEY1_MSK + +/****************** Bit definition for AES_KEY2 register ************************/ + +#define AES_KEY2_KEY2_POSS 0U +#define AES_KEY2_KEY2_POSE 31U +#define AES_KEY2_KEY2_MSK BITS(AES_KEY2_KEY2_POSS,AES_KEY2_KEY2_POSE) +#define AES_KEY2_KEY2 AES_KEY2_KEY2_MSK + +/****************** Bit definition for AES_KEY3 register ************************/ + +#define AES_KEY3_KEY3_POSS 0U +#define AES_KEY3_KEY3_POSE 31U +#define AES_KEY3_KEY3_MSK BITS(AES_KEY3_KEY3_POSS,AES_KEY3_KEY3_POSE) +#define AES_KEY3_KEY3 AES_KEY3_KEY3_MSK + +/****************** Bit definition for AES_IV0 register ************************/ + +#define AES_IV0_IV0_POSS 0U +#define AES_IV0_IV0_POSE 31U +#define AES_IV0_IV0_MSK BITS(AES_IV0_IV0_POSS,AES_IV0_IV0_POSE) +#define AES_IV0_IV0 AES_IV0_IV0_MSK + +/****************** Bit definition for AES_IV1 register ************************/ + +#define AES_IV1_IV1_POSS 0U +#define AES_IV1_IV1_POSE 31U +#define AES_IV1_IV1_MSK BITS(AES_IV1_IV1_POSS,AES_IV1_IV1_POSE) +#define AES_IV1_IV1 AES_IV1_IV1_MSK + +/****************** Bit definition for AES_IV2 register ************************/ + +#define AES_IV2_IV2_POSS 0U +#define AES_IV2_IV2_POSE 31U +#define AES_IV2_IV2_MSK BITS(AES_IV2_IV2_POSS,AES_IV2_IV2_POSE) +#define AES_IV2_IV2 AES_IV2_IV2_MSK + +/****************** Bit definition for AES_IV3 register ************************/ + +#define AES_IV3_IV3_POSS 0U +#define AES_IV3_IV3_POSE 31U +#define AES_IV3_IV3_MSK BITS(AES_IV3_IV3_POSS,AES_IV3_IV3_POSE) +#define AES_IV3_IV3 AES_IV3_IV3_MSK + +typedef struct +{ + __IO uint32_t CON ; /* 0x000 AES_CON AES Control Register */ + __O uint32_t IER; /* 0x004 AES_IER AES Interrupt Enable Register */ + __O uint32_t IDR; /* 0x008 AES_IDR AES Interrupt Disable Register */ + __I uint32_t IVS; /* 0x00C AES_IVS AES Interrupt Valid Status Register */ + __I uint32_t RIF; /* 0x010 AES_RIF AES Raw Interrupt Flag Status Register */ + __I uint32_t IFM; /* 0x014 AES_IFM AES Interrupt Flag Masked Register */ + __O uint32_t ICR; /* 0x018 AES_ICR AES Interrupt Clear Register */ + __IO uint32_t DIO; /* 0x01C AES_DIO AES 128-bit Input/Output Data Register */ + __IO uint32_t KEY0; /* 0x020 AES_KEY0 AES 128-bit Keyword Register 0 */ + __IO uint32_t KEY1; /* 0x024 AES_KEY1 AES 128-bit Keyword Register 1 */ + __IO uint32_t KEY2; /* 0x028 AES_KEY2 AES 128-bit Keyword Register 2 */ + __IO uint32_t KEY3; /* 0x02C AES_KEY3 AES 128-bit Keyword Register 3 */ + uint32_t RESERVED0[4] ; + __IO uint32_t IV0; /* 0x040 AES_IV0 AES 128-bit Initial Vector Register 0 */ + __IO uint32_t IV1; /* 0x044 AES_IV1 AES 128-bit Initial Vector Register 1 */ + __IO uint32_t IV2; /* 0x048 AES_IV2 AES 128-bit Initial Vector Register 2 */ + __IO uint32_t IV3; /* 0x04C AES_IV3 AES 128-bit Initial Vector Register 3 */ +} AES_TypeDef; + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_calc.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_calc.h new file mode 100644 index 00000000000..7b7d0cef418 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_calc.h @@ -0,0 +1,118 @@ +/********************************************************************************** + * + * @file reg_calc.h + * @brief CALC Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __CALC_H__ +#define __CALC_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +////#pragma anon_unions + +/****************** Bit definition for CALC_DIVDR register ************************/ + +#define CALC_DIVDR_DIVD_POSS 0U +#define CALC_DIVDR_DIVD_POSE 31U +#define CALC_DIVDR_DIVD_MSK BITS(CALC_DIVDR_DIVD_POSS,CALC_DIVDR_DIVD_POSE) +#define CALC_DIVDR_DIVD CALC_DIVDR_DIVD_MSK + +/****************** Bit definition for CALC_DIVSR register ************************/ + +#define CALC_DIVSR_DIVS_POSS 0U +#define CALC_DIVSR_DIVS_POSE 31U +#define CALC_DIVSR_DIVS_MSK BITS(CALC_DIVSR_DIVS_POSS,CALC_DIVSR_DIVS_POSE) +#define CALC_DIVSR_DIVS CALC_DIVSR_DIVS_MSK + +/****************** Bit definition for CALC_DIVQR register ************************/ + +#define CALC_DIVQR_DIVQ_POSS 0U +#define CALC_DIVQR_DIVQ_POSE 31U +#define CALC_DIVQR_DIVQ_MSK BITS(CALC_DIVQR_DIVQ_POSS,CALC_DIVQR_DIVQ_POSE) +#define CALC_DIVQR_DIVQ CALC_DIVQR_DIVQ_MSK + +/****************** Bit definition for CALC_DIVRR register ************************/ + +#define CALC_DIVRR_DIVR_POSS 0U +#define CALC_DIVRR_DIVR_POSE 31U +#define CALC_DIVRR_DIVR_MSK BITS(CALC_DIVRR_DIVR_POSS,CALC_DIVRR_DIVR_POSE) +#define CALC_DIVRR_DIVR CALC_DIVRR_DIVR_MSK + +/****************** Bit definition for CALC_DIVCON register ************************/ + +#define CALC_DIVCON_TRM_POS 1U +#define CALC_DIVCON_TRM_MSK BIT(CALC_DIVCON_TRM_POS) +#define CALC_DIVCON_TRM CALC_DIVCON_TRM_MSK + +#define CALC_DIVCON_SIGN_POS 0U +#define CALC_DIVCON_SIGN_MSK BIT(CALC_DIVCON_SIGN_POS) +#define CALC_DIVCON_SIGN CALC_DIVCON_SIGN_MSK + +/****************** Bit definition for CALC_RDCND register ************************/ + +#define CALC_RDCND_RADICAND_POSS 0U +#define CALC_RDCND_RADICAND_POSE 31U +#define CALC_RDCND_RADICAND_MSK BITS(CALC_RDCND_RADICAND_POSS,CALC_RDCND_RADICAND_POSE) +#define CALC_RDCND_RADICAND CALC_RDCND_RADICAND_MSK + +/****************** Bit definition for CALC_SQRTRES register ************************/ + +#define CALC_SQRTRES_RESULT_POSS 0U +#define CALC_SQRTRES_RESULT_POSE 15U +#define CALC_SQRTRES_RESULT_MSK BITS(CALC_SQRTRES_RESULT_POSS,CALC_SQRTRES_RESULT_POSE) +#define CALC_SQRTRES_RESULT CALC_SQRTRES_RESULT_MSK + +/****************** Bit definition for CALC_STAT register ************************/ + +#define CALC_STAT_DZ_POS 1U +#define CALC_STAT_DZ_MSK BIT(CALC_STAT_DZ_POS) +#define CALC_STAT_DZ CALC_STAT_DZ_MSK + +#define CALC_STAT_BUSY_POS 0U +#define CALC_STAT_BUSY_MSK BIT(CALC_STAT_BUSY_POS) +#define CALC_STAT_BUSY CALC_STAT_BUSY_MSK + +typedef struct +{ + __IO uint32_t DIVDR; + __IO uint32_t DIVSR; + __I uint32_t DIVQR; + __I uint32_t DIVRR; + __IO uint32_t DIVCON; + __IO uint32_t RDCND; + __I uint32_t SQRTRES; + __IO uint32_t RESERVED0; + __I uint32_t STAT; +} CALC_TypeDef; + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_cmp.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_cmp.h new file mode 100644 index 00000000000..be16dc9496c --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_cmp.h @@ -0,0 +1,188 @@ +/********************************************************************************** + * + * @file reg_cmp.h + * @brief CMP Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __CMP_H__ +#define __CMP_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +////#pragma anon_unions + +/****************** Bit definition for CMP_CFG1 register ************************/ + +# define CMP_CFG1_LOCK_POS 31U +# define CMP_CFG1_LOCK_MSK BIT(CMP_CFG1_LOCK_POS) +# define CMP_CFG1_LOCK CMP_CFG1_LOCK_MSK + +# define CMP_CFG1_VALUE_POS 30U +# define CMP_CFG1_VALUE_MSK BIT(CMP_CFG1_VALUE_POS) +# define CMP_CFG1_VALUE CMP_CFG1_VALUE_MSK + +# define CMP_CFG1_BLANKSEL_POSS 20U +# define CMP_CFG1_BLANKSEL_POSE 24U +# define CMP_CFG1_BLANKSEL_MSK BITS(CMP_CFG1_BLANKSEL_POSS, CMP_CFG1_BLANKSEL_POSE) +# define CMP_CFG1_BLANKSEL CMP_CFG1_BLANKSEL_MSK + +# define CMP_CFG1_FILT_POS 18U +# define CMP_CFG1_FILT_MSK BIT(CMP_CFG1_FILT_POS) +# define CMP_CFG1_FILT CMP_CFG1_FILT_MSK + +# define CMP_CFG1_HYST_POS 16U +# define CMP_CFG1_HYST_MSK BIT(CMP_CFG1_HYST_POS) +# define CMP_CFG1_HYST CMP_CFG1_HYST_MSK + +# define CMP_CFG1_POLARITY_POS 15U +# define CMP_CFG1_POLARITY_MSK BIT(CMP_CFG1_POLARITY_POS) +# define CMP_CFG1_POLARITY CMP_CFG1_POLARITY_MSK + +# define CMP_CFG1_OUTSEL_POSS 12U +# define CMP_CFG1_OUTSEL_POSE 14U +# define CMP_CFG1_OUTSEL_MSK BITS(CMP_CFG1_OUTSEL_POSS, CMP_CFG1_OUTSEL_POSE) +# define CMP_CFG1_OUTSEL CMP_CFG1_OUTSEL_MSK + +# define CMP_CFG1_INNSEL_POSS 4U +# define CMP_CFG1_INNSEL_POSE 6U +# define CMP_CFG1_INNSEL_MSK BITS(CMP_CFG1_INNSEL_POSS, CMP_CFG1_INNSEL_POSE) +# define CMP_CFG1_INNSEL CMP_CFG1_INNSEL_MSK + +# define CMP_CFG1_EN_POS 0U +# define CMP_CFG1_EN_MSK BIT(CMP_CFG1_EN_POS) +# define CMP_CFG1_EN CMP_CFG1_EN_MSK + +/****************** Bit definition for CMP_CFG2 register ************************/ + +# define CMP_CFG2_LOCK_POS 31U +# define CMP_CFG2_LOCK_MSK BIT(CMP_CFG2_LOCK_POS) +# define CMP_CFG2_LOCK CMP_CFG2_LOCK_MSK + +# define CMP_CFG2_VALUE_POS 30U +# define CMP_CFG2_VALUE_MSK BIT(CMP_CFG2_VALUE_POS) +# define CMP_CFG2_VALUE CMP_CFG2_VALUE_MSK + +# define CMP_CFG2_BLANKSEL_POSS 20U +# define CMP_CFG2_BLANKSEL_POSE 24U +# define CMP_CFG2_BLANKSEL_MSK BITS(CMP_CFG2_BLANKSEL_POSS, CMP_CFG2_BLANKSEL_POSE) +# define CMP_CFG2_BLANKSEL CMP_CFG2_BLANKSEL_MSK + +# define CMP_CFG2_FILT_POS 18U +# define CMP_CFG2_FILT_MSK BIT(CMP_CFG2_FILT_POS) +# define CMP_CFG2_FILT CMP_CFG2_FILT_MSK + +# define CMP_CFG2_HYST_POS 16U +# define CMP_CFG2_HYST_MSK BIT(CMP_CFG2_HYST_POS) +# define CMP_CFG2_HYST CMP_CFG2_HYST_MSK + +# define CMP_CFG2_POLARITY_POS 15U +# define CMP_CFG2_POLARITY_MSK BIT(CMP_CFG2_POLARITY_POS) +# define CMP_CFG2_POLARITY CMP_CFG2_POLARITY_MSK + +# define CMP_CFG2_OUTSEL_POSS 12U +# define CMP_CFG2_OUTSEL_POSE 14U +# define CMP_CFG2_OUTSEL_MSK BITS(CMP_CFG2_OUTSEL_POSS, CMP_CFG2_OUTSEL_POSE) +# define CMP_CFG2_OUTSEL CMP_CFG2_OUTSEL_MSK + +# define CMP_CFG2_WINOUT_POS 9U +# define CMP_CFG2_WINOUT_MSK BIT(CMP_CFG2_WINOUT_POS) +# define CMP_CFG2_WINOUT CMP_CFG2_WINOUT_MSK + +# define CMP_CFG2_WINMODE_POS 8U +# define CMP_CFG2_WINMODE_MSK BIT(CMP_CFG2_WINMODE_POS) +# define CMP_CFG2_WINMODE CMP_CFG2_WINMODE_MSK + +# define CMP_CFG2_INNSEL_POSS 4U +# define CMP_CFG2_INNSEL_POSE 6U +# define CMP_CFG2_INNSEL_MSK BITS(CMP_CFG2_INNSEL_POSS, CMP_CFG2_INNSEL_POSE) +# define CMP_CFG2_INNSEL CMP_CFG2_INNSEL_MSK + +# define CMP_CFG2_EN_POS 0U +# define CMP_CFG2_EN_MSK BIT(CMP_CFG2_EN_POS) +# define CMP_CFG2_EN CMP_CFG2_EN_MSK + +/****************** Bit definition for CMP_TRIM1 register ************************/ + +# define CMP_TRIM1_TRIM_SEL_POS 31U +# define CMP_TRIM1_TRIM_SEL_MSK BIT(CMP_TRIM1_TRIM_SEL_POS) +# define CMP_TRIM1_TRIM_SEL CMP_TRIM1_TRIM_SEL_MSK + +# define CMP_TRIM1_CAL_STAT_POS 30U +# define CMP_TRIM1_CAL_STAT_MSK BIT(CMP_TRIM1_CAL_STAT_POS) +# define CMP_TRIM1_CAL_STAT CMP_TRIM1_CAL_STAT_MSK + +# define CMP_TRIM1_INSW_STAT_POS 29U +# define CMP_TRIM1_INSW_STAT_MSK BIT(CMP_TRIM1_INSW_STAT_POS) +# define CMP_TRIM1_INSW_STAT CMP_TRIM1_INSW_STAT_MSK + +# define CMP_TRIM1_CAL_EN_POSS 8U +# define CMP_TRIM1_CAL_EN_POSE 15U +# define CMP_TRIM1_CAL_EN_MSK BITS(CMP_TRIM1_CAL_EN_POSS, CMP_TRIM1_CAL_EN_POSE) +# define CMP_TRIM1_CAL_EN CMP_TRIM1_CAL_EN_MSK + +# define CMP_TRIM1_INSW_EN_POSS 0U +# define CMP_TRIM1_INSW_EN_POSE 7U +# define CMP_TRIM1_INSW_EN_MSK BITS(CMP_TRIM1_INSW_EN_POSS, CMP_TRIM1_INSW_EN_POSE) +# define CMP_TRIM1_INSW_EN CMP_TRIM1_INSW_EN_MSK + +/****************** Bit definition for CMP_TRIM2 register ************************/ + +# define CMP_TRIM2_OPT_TRIM2_POSS 24U +# define CMP_TRIM2_OPT_TRIM2_POSE 31U +# define CMP_TRIM2_OPT_TRIM2_MSK BITS(CMP_TRIM2_OPT_TRIM2_POSS, CMP_TRIM2_OPT_TRIM2_POSE) +# define CMP_TRIM2_OPT_TRIM2 CMP_TRIM2_OPT_TRIM2_MSK + +# define CMP_TRIM2_REG_TRIM2_POSS 16U +# define CMP_TRIM2_REG_TRIM2_POSE 23U +# define CMP_TRIM2_REG_TRIM2_MSK BITS(CMP_TRIM2_REG_TRIM2_POSS, CMP_TRIM2_REG_TRIM2_POSE) +# define CMP_TRIM2_REG_TRIM2 CMP_TRIM2_REG_TRIM2_MSK + +# define CMP_TRIM2_OPT_TRIM1_POSS 8U +# define CMP_TRIM2_OPT_TRIM1_POSE 15U +# define CMP_TRIM2_OPT_TRIM1_MSK BITS(CMP_TRIM2_OPT_TRIM1_POSS, CMP_TRIM2_OPT_TRIM1_POSE) +# define CMP_TRIM2_OPT_TRIM1 CMP_TRIM2_OPT_TRIM1_MSK + +# define CMP_TRIM2_REG_TRIM1_POSS 0U +# define CMP_TRIM2_REG_TRIM1_POSE 7U +# define CMP_TRIM2_REG_TRIM1_MSK BITS(CMP_TRIM2_REG_TRIM1_POSS, CMP_TRIM2_REG_TRIM1_POSE) +# define CMP_TRIM2_REG_TRIM1 CMP_TRIM2_REG_TRIM1_MSK + +typedef struct +{ + __IO uint32_t CFG1; // 0x000 + __IO uint32_t CFG2; // 0x004 + __IO uint32_t TRIM1; // 0x008 + __IO uint32_t TRIM2; // 0x00c +} CMP_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_crc.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_crc.h new file mode 100644 index 00000000000..0f85350394b --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_crc.h @@ -0,0 +1,159 @@ +/********************************************************************************** + * + * @file reg_crc.h + * @brief CRC Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __CRC_H__ +#define __CRC_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +////#pragma anon_unions + +/****************** Bit definition for CRC_INIT register ************************/ + +#define CRC_INIT_INIT_POSS 0U +#define CRC_INIT_INIT_POSE 31U +#define CRC_INIT_INIT_MSK BITS(CRC_INIT_INIT_POSS,CRC_INIT_INIT_POSE) +#define CRC_INIT_INIT CRC_INIT_INIT_MSK + +/****************** Bit definition for CRC_POLY register ************************/ + +#define CRC_POLY_POLY_POSS 0U +#define CRC_POLY_POLY_POSE 31U +#define CRC_POLY_POLY_MSK BITS(CRC_POLY_POLY_POSS,CRC_POLY_POLY_POSE) +#define CRC_POLY_POLY CRC_POLY_POLY_MSK + +/****************** Bit definition for CRC_DATA register ************************/ + +#define CRC_DATA_DATA_POSS 0U +#define CRC_DATA_DATA_POSE 31U +#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) +#define CRC_DATA_DATA CRC_DATA_DATA_MSK + +/****************** Bit definition for CRC_COMP register ************************/ + +#define CRC_COMP_COMP_POSS 0U +#define CRC_COMP_COMP_POSE 31U +#define CRC_COMP_COMP_MSK BITS(CRC_COMP_COMP_POSS,CRC_COMP_COMP_POSE) +#define CRC_COMP_COMP CRC_COMP_COMP_MSK + +/****************** Bit definition for CRC_REMA register ************************/ + +#define CRC_REMA_REMA_POSS 0U +#define CRC_REMA_REMA_POSE 31U +#define CRC_REMA_REMA_MSK BITS(CRC_REMA_REMA_POSS,CRC_REMA_REMA_POSE) +#define CRC_REMA_REMA CRC_REMA_REMA_MSK + +/****************** Bit definition for CRC_CON register ************************/ + +#define CRC_CON_DMA_POS 16U +#define CRC_CON_DMA_MSK BIT(CRC_CON_DMA_POS) +#define CRC_CON_DMA CRC_CON_DMA_MSK + +#define CRC_CON_MSB_POS 12U +#define CRC_CON_MSB_MSK BIT(CRC_CON_MSB_POS) +#define CRC_CON_MSB CRC_CON_MSB_MSK + +#define CRC_CON_REOUT_POS 10U +#define CRC_CON_REOUT_MSK BIT(CRC_CON_REOUT_POS) +#define CRC_CON_REOUT CRC_CON_REOUT_MSK + +#define CRC_CON_REIN_POS 8U +#define CRC_CON_REIN_MSK BIT(CRC_CON_REIN_POS) +#define CRC_CON_REIN CRC_CON_REIN_MSK + +#define CRC_CON_SIZE_POSS 4U +#define CRC_CON_SIZE_POSE 5U +#define CRC_CON_SIZE_MSK BITS(CRC_CON_SIZE_POSS,CRC_CON_SIZE_POSE) +#define CRC_CON_SIZE CRC_CON_SIZE_MSK + +#define CRC_CON_MODE_POSS 2U +#define CRC_CON_MODE_POSE 3U +#define CRC_CON_MODE_MSK BITS(CRC_CON_MODE_POSS,CRC_CON_MODE_POSE) +#define CRC_CON_MODE CRC_CON_MODE_MSK + +#define CRC_CON_RESET_POS 0U +#define CRC_CON_RESET_MSK BIT(CRC_CON_RESET_POS) +#define CRC_CON_RESET CRC_CON_RESET_MSK + +/****************** Bit definition for CRC_DOUT register ************************/ + +#define CRC_DOUT_DOUT_POSS 0U +#define CRC_DOUT_DOUT_POSE 31U +#define CRC_DOUT_DOUT_MSK BITS(CRC_DOUT_DOUT_POSS,CRC_DOUT_DOUT_POSE) +#define CRC_DOUT_DOUT CRC_DOUT_DOUT_MSK + +/****************** Bit definition for CRC_DOUT_XOR register ************************/ + +#define CRC_DOUT_XOR_DOUT_XOR_POSS 0U +#define CRC_DOUT_XOR_DOUT_XOR_POSE 31U +#define CRC_DOUT_XOR_DOUT_XOR_MSK BITS(CRC_DOUT_XOR_DOUT_XOR_POSS,CRC_DOUT_XOR_DOUT_XOR_POSE) +#define CRC_DOUT_XOR_DOUT_XOR CRC_DOUT_XOR_DOUT_XOR_MSK + +/****************** Bit definition for CRC_STAT register ************************/ + +#define CRC_STAT_FAIL_POS 8U +#define CRC_STAT_FAIL_MSK BIT(CRC_STAT_FAIL_POS) +#define CRC_STAT_FAIL CRC_STAT_FAIL_MSK + +#define CRC_STAT_EMPTY_POS 2U +#define CRC_STAT_EMPTY_MSK BIT(CRC_STAT_EMPTY_POS) +#define CRC_STAT_EMPTY CRC_STAT_EMPTY_MSK + +#define CRC_STAT_BUSY_POS 1U +#define CRC_STAT_BUSY_MSK BIT(CRC_STAT_BUSY_POS) +#define CRC_STAT_BUSY CRC_STAT_BUSY_MSK + +#define CRC_STAT_DONE_POS 0U +#define CRC_STAT_DONE_MSK BIT(CRC_STAT_DONE_POS) +#define CRC_STAT_DONE CRC_STAT_DONE_MSK + +typedef struct +{ + __IO uint32_t INIT; /* 0x000 CRC_INIT CRC Iintial Value Register */ + __IO uint32_t POLY; /* 0x004 CRC_POLY CRC Polynomial Register */ + __IO uint32_t DATA; /* 0x008 CRC_DATA CRC Input Data Register */ + __IO uint32_t COMP; /* 0x00C CRC_COMP CRC Compare Data Register */ + __IO uint32_t REMA; /* 0x010 CRC_REMA CRC Remainder Register */ + __IO uint32_t CON; /* 0x014 CRC_CTRL CRC Control Register */ + __I uint32_t DOUT; /* 0x018 CRC_DOUT CRC Output Data Register */ + __I uint32_t DOUT_XOR; /* 0x01C CRC_DOUT_XOR CRC Output Data Register */ + __I uint32_t STAT; /* 0x020 CRC_STA CRC Status Register */ +} CRC_TypeDef; + + + + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_csu.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_csu.h new file mode 100644 index 00000000000..06210f24943 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_csu.h @@ -0,0 +1,278 @@ +/********************************************************************************** + * + * @file reg_csu.h + * @brief CSU Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __CSU_H__ +#define __CSU_H__ + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +////#pragma anon_unions + +/****************** Bit definition for CSU_CON register ************************/ + +#define CSU_CON_TRIM_POSS 8U +#define CSU_CON_TRIM_POSE 16U +#define CSU_CON_TRIM_MSK BITS(CSU_CON_TRIM_POSS,CSU_CON_TRIM_POSE) +#define CSU_CON_TRIM CSU_CON_TRIM_MSK + +#define CSU_CON_SYNCGEN_POS 2U +#define CSU_CON_SYNCGEN_MSK BIT(CSU_CON_SYNCGEN_POS) +#define CSU_CON_SYNCGEN CSU_CON_SYNCGEN_MSK + +#define CSU_CON_AUTOEN_POS 1U +#define CSU_CON_AUTOEN_MSK BIT(CSU_CON_AUTOEN_POS) +#define CSU_CON_AUTOEN CSU_CON_AUTOEN_MSK + +#define CSU_CON_CNTEN_POS 0U +#define CSU_CON_CNTEN_MSK BIT(CSU_CON_CNTEN_POS) +#define CSU_CON_CNTEN CSU_CON_CNTEN_MSK + +/****************** Bit definition for CSU_CFG register ************************/ + +#define CSU_CFG_TRIMSEL_POS 31U +#define CSU_CFG_TRIMSEL_MSK BIT(CSU_CFG_TRIMSEL_POS) +#define CSU_CFG_TRIMSEL CSU_CFG_TRIMSEL_MSK + +#define CSU_CFG_POLSEL_POS 30U +#define CSU_CFG_POLSEL_MSK BIT(CSU_CFG_POLSEL_POS) +#define CSU_CFG_POLSEL CSU_CFG_POLSEL_MSK + +#define CSU_CFG_SYNCSRC_POSS 28U +#define CSU_CFG_SYNCSRC_POSE 29U +#define CSU_CFG_SYNCSRC_MSK BITS(CSU_CFG_SYNCSRC_POSS,CSU_CFG_SYNCSRC_POSE) +#define CSU_CFG_SYNCSRC CSU_CFG_SYNCSRC_MSK + +#define CSU_CFG_SYNCDIV_POSS 24U +#define CSU_CFG_SYNCDIV_POSE 26U +#define CSU_CFG_SYNCDIV_MSK BITS(CSU_CFG_SYNCDIV_POSS,CSU_CFG_SYNCDIV_POSE) +#define CSU_CFG_SYNCDIV CSU_CFG_SYNCDIV_MSK + +#define CSU_CFG_CNTTH_POSS 16U +#define CSU_CFG_CNTTH_POSE 23U +#define CSU_CFG_CNTTH_MSK BITS(CSU_CFG_CNTTH_POSS,CSU_CFG_CNTTH_POSE) +#define CSU_CFG_CNTTH CSU_CFG_CNTTH_MSK + +#define CSU_CFG_RELOAD_POSS 0U +#define CSU_CFG_RELOAD_POSE 15U +#define CSU_CFG_RELOAD_MSK BITS(CSU_CFG_RELOAD_POSS,CSU_CFG_RELOAD_POSE) +#define CSU_CFG_RELOAD CSU_CFG_RELOAD_MSK + +/****************** Bit definition for CSU_STAT register ************************/ + +#define CSU_STAT_OPT_TRIM_POSS 23U +#define CSU_STAT_OPT_TRIM_POSE 31U +#define CSU_STAT_OPT_TRIM_MSK BITS(CSU_STAT_OPT_TRIM_POSS,CSU_STAT_OPT_TRIM_POSE) +#define CSU_STAT_OPT_TRIM CSU_STAT_OPT_TRIM_MSK + +#define CSU_STAT_CNTDIR_POS 16U +#define CSU_STAT_CNTDIR_MSK BIT(CSU_STAT_CNTDIR_POS) +#define CSU_STAT_CNTDIR CSU_STAT_CNTDIR_MSK + +#define CSU_STAT_CNTCAP_POSS 0U +#define CSU_STAT_CNTCAP_POSE 15U +#define CSU_STAT_CNTCAP_MSK BITS(CSU_STAT_CNTCAP_POSS,CSU_STAT_CNTCAP_POSE) +#define CSU_STAT_CNTCAP CSU_STAT_CNTCAP_MSK + +/****************** Bit definition for CSU_IER register ************************/ + +#define CSU_IER_FHIT_POS 5U +#define CSU_IER_FHIT_MSK BIT(CSU_IER_FHIT_POS) +#define CSU_IER_FHIT CSU_IER_FHIT_MSK + +#define CSU_IER_TRIMERR_POS 4U +#define CSU_IER_TRIMERR_MSK BIT(CSU_IER_TRIMERR_POS) +#define CSU_IER_TRIMERR CSU_IER_TRIMERR_MSK + +#define CSU_IER_FFAULT_POS 3U +#define CSU_IER_FFAULT_MSK BIT(CSU_IER_FFAULT_POS) +#define CSU_IER_FFAULT CSU_IER_FFAULT_MSK + +#define CSU_IER_FERROR_POS 2U +#define CSU_IER_FERROR_MSK BIT(CSU_IER_FERROR_POS) +#define CSU_IER_FERROR CSU_IER_FERROR_MSK + +#define CSU_IER_FWARN_POS 1U +#define CSU_IER_FWARN_MSK BIT(CSU_IER_FWARN_POS) +#define CSU_IER_FWARN CSU_IER_FWARN_MSK + +#define CSU_IER_FMATCH_POS 0U +#define CSU_IER_FMATCH_MSK BIT(CSU_IER_FMATCH_POS) +#define CSU_IER_FMATCH CSU_IER_FMATCH_MSK + +/****************** Bit definition for CSU_IDR register ************************/ + +#define CSU_IDR_FHIT_POS 5U +#define CSU_IDR_FHIT_MSK BIT(CSU_IDR_FHIT_POS) +#define CSU_IDR_FHIT CSU_IDR_FHIT_MSK + +#define CSU_IDR_TRIMERR_POS 4U +#define CSU_IDR_TRIMERR_MSK BIT(CSU_IDR_TRIMERR_POS) +#define CSU_IDR_TRIMERR CSU_IDR_TRIMERR_MSK + +#define CSU_IDR_FFAULT_POS 3U +#define CSU_IDR_FFAULT_MSK BIT(CSU_IDR_FFAULT_POS) +#define CSU_IDR_FFAULT CSU_IDR_FFAULT_MSK + +#define CSU_IDR_FERROR_POS 2U +#define CSU_IDR_FERROR_MSK BIT(CSU_IDR_FERROR_POS) +#define CSU_IDR_FERROR CSU_IDR_FERROR_MSK + +#define CSU_IDR_FWARN_POS 1U +#define CSU_IDR_FWARN_MSK BIT(CSU_IDR_FWARN_POS) +#define CSU_IDR_FWARN CSU_IDR_FWARN_MSK + +#define CSU_IDR_FMATCH_POS 0U +#define CSU_IDR_FMATCH_MSK BIT(CSU_IDR_FMATCH_POS) +#define CSU_IDR_FMATCH CSU_IDR_FMATCH_MSK + +/****************** Bit definition for CSU_IVS register ************************/ + +#define CSU_IVS_FHIT_POS 5U +#define CSU_IVS_FHIT_MSK BIT(CSU_IVS_FHIT_POS) +#define CSU_IVS_FHIT CSU_IVS_FHIT_MSK + +#define CSU_IVS_TRIMERR_POS 4U +#define CSU_IVS_TRIMERR_MSK BIT(CSU_IVS_TRIMERR_POS) +#define CSU_IVS_TRIMERR CSU_IVS_TRIMERR_MSK + +#define CSU_IVS_FFAULT_POS 3U +#define CSU_IVS_FFAULT_MSK BIT(CSU_IVS_FFAULT_POS) +#define CSU_IVS_FFAULT CSU_IVS_FFAULT_MSK + +#define CSU_IVS_FERROR_POS 2U +#define CSU_IVS_FERROR_MSK BIT(CSU_IVS_FERROR_POS) +#define CSU_IVS_FERROR CSU_IVS_FERROR_MSK + +#define CSU_IVS_FWARN_POS 1U +#define CSU_IVS_FWARN_MSK BIT(CSU_IVS_FWARN_POS) +#define CSU_IVS_FWARN CSU_IVS_FWARN_MSK + +#define CSU_IVS_FMATCH_POS 0U +#define CSU_IVS_FMATCH_MSK BIT(CSU_IVS_FMATCH_POS) +#define CSU_IVS_FMATCH CSU_IVS_FMATCH_MSK + + +/****************** Bit definition for CSU_RIF register ************************/ + +#define CSU_RIF_FHIT_POS 5U +#define CSU_RIF_FHIT_MSK BIT(CSU_RIF_FHIT_POS) +#define CSU_RIF_FHIT CSU_RIF_FHIT_MSK + +#define CSU_RIF_TRIMERR_POS 4U +#define CSU_RIF_TRIMERR_MSK BIT(CSU_RIF_TRIMERR_POS) +#define CSU_RIF_TRIMERR CSU_RIF_TRIMERR_MSK + +#define CSU_RIF_FFAULT_POS 3U +#define CSU_RIF_FFAULT_MSK BIT(CSU_RIF_FFAULT_POS) +#define CSU_RIF_FFAULT CSU_RIF_FFAULT_MSK + +#define CSU_RIF_FERROR_POS 2U +#define CSU_RIF_FERROR_MSK BIT(CSU_RIF_FERROR_POS) +#define CSU_RIF_FERROR CSU_RIF_FERROR_MSK + +#define CSU_RIF_FWARN_POS 1U +#define CSU_RIF_FWARN_MSK BIT(CSU_RIF_FWARN_POS) +#define CSU_RIF_FWARN CSU_RIF_FWARN_MSK + +#define CSU_RIF_FMATCH_POS 0U +#define CSU_RIF_FMATCH_MSK BIT(CSU_RIF_FMATCH_POS) +#define CSU_RIF_FMATCH CSU_RIF_FMATCH_MSK + +/****************** Bit definition for CSU_IFM register ************************/ + +#define CSU_IFM_FHIT_POS 5U +#define CSU_IFM_FHIT_MSK BIT(CSU_IFM_FHIT_POS) +#define CSU_IFM_FHIT CSU_IFM_FHIT_MSK + +#define CSU_IFM_TRIMERR_POS 4U +#define CSU_IFM_TRIMERR_MSK BIT(CSU_IFM_TRIMERR_POS) +#define CSU_IFM_TRIMERR CSU_IFM_TRIMERR_MSK + +#define CSU_IFM_FFAULT_POS 3U +#define CSU_IFM_FFAULT_MSK BIT(CSU_IFM_FFAULT_POS) +#define CSU_IFM_FFAULT CSU_IFM_FFAULT_MSK + +#define CSU_IFM_FERROR_POS 2U +#define CSU_IFM_FERROR_MSK BIT(CSU_IFM_FERROR_POS) +#define CSU_IFM_FERROR CSU_IFM_FERROR_MSK + +#define CSU_IFM_FWARN_POS 1U +#define CSU_IFM_FWARN_MSK BIT(CSU_IFM_FWARN_POS) +#define CSU_IFM_FWARN CSU_IFM_FWARN_MSK + +#define CSU_IFM_FMATCH_POS 0U +#define CSU_IFM_FMATCH_MSK BIT(CSU_IFM_FMATCH_POS) +#define CSU_IFM_FMATCH CSU_IFM_FMATCH_MSK + +/****************** Bit definition for CSU_ICR register ************************/ + +#define CSU_ICR_FHIT_POS 5U +#define CSU_ICR_FHIT_MSK BIT(CSU_ICR_FHIT_POS) +#define CSU_ICR_FHIT CSU_ICR_FHIT_MSK + +#define CSU_ICR_TRIMERR_POS 4U +#define CSU_ICR_TRIMERR_MSK BIT(CSU_ICR_TRIMERR_POS) +#define CSU_ICR_TRIMERR CSU_ICR_TRIMERR_MSK + +#define CSU_ICR_FFAULT_POS 3U +#define CSU_ICR_FFAULT_MSK BIT(CSU_ICR_FFAULT_POS) +#define CSU_ICR_FFAULT CSU_ICR_FFAULT_MSK + +#define CSU_ICR_FERROR_POS 2U +#define CSU_ICR_FERROR_MSK BIT(CSU_ICR_FERROR_POS) +#define CSU_ICR_FERROR CSU_ICR_FERROR_MSK + +#define CSU_ICR_FWARN_POS 1U +#define CSU_ICR_FWARN_MSK BIT(CSU_ICR_FWARN_POS) +#define CSU_ICR_FWARN CSU_ICR_FWARN_MSK + +#define CSU_ICR_FMATCH_POS 0U +#define CSU_ICR_FMATCH_MSK BIT(CSU_ICR_FMATCH_POS) +#define CSU_ICR_FMATCH CSU_ICR_FMATCH_MSK + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t CFG; + __I uint32_t STAT; + uint32_t RESERVEDC; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} CSU_TypeDef; + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_dma.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_dma.h new file mode 100644 index 00000000000..eb71e5b838d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_dma.h @@ -0,0 +1,345 @@ +/********************************************************************************** + * + * @file reg_dma.h + * @brief DMA Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 25 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __DMA_H__ +#define __DMA_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + + +/****************** Bit definition for DMA_STATUS register ************************/ + +# define DMA_STATUS_CHNLS_MINUS1_POSS 16U +# define DMA_STATUS_CHNLS_MINUS1_POSE 20U +# define DMA_STATUS_CHNLS_MINUS1_MSK BITS(DMA_STATUS_CHNLS_MINUS1_POSS, DMA_STATUS_CHNLS_MINUS1_POSE) +# define DMA_STATUS_CHNLS_MINUS1 DMA_STATUS_CHNLS_MINUS1_MSK + +# define DMA_STATUS_STATUS_POSS 4U +# define DMA_STATUS_STATUS_POSE 7U +# define DMA_STATUS_STATUS_MSK BITS(DMA_STATUS_STATUS_POSS, DMA_STATUS_STATUS_POSE) +# define DMA_STATUS_STATUS DMA_STATUS_STATUS_MSK + +# define DMA_STATUS_MASTER_ENABLE_POS 0U +# define DMA_STATUS_MASTER_ENABLE_MSK BIT(DMA_STATUS_MASTER_ENABLE_POS) +# define DMA_STATUS_MASTER_ENABLE DMA_STATUS_MASTER_ENABLE_MSK + +/****************** Bit definition for DMA_CFG register ************************/ + +# define DMA_CFG_CHNL_PROT_CTRL_POSS 5U +# define DMA_CFG_CHNL_PROT_CTRL_POSE 7U +# define DMA_CFG_CHNL_PROT_CTRL_MSK BITS(DMA_CFG_CHNL_PROT_CTRL_POSS, DMA_CFG_CHNL_PROT_CTRL_POSE) +# define DMA_CFG_CHNL_PROT_CTRL DMA_CFG_CHNL_PROT_CTRL_MSK + +# define DMA_CFG_MASTER_ENABLE_POS 0U +# define DMA_CFG_MASTER_ENABLE_MSK BIT(DMA_CFG_MASTER_ENABLE_POS) +# define DMA_CFG_MASTER_ENABLE DMA_CFG_MASTER_ENABLE_MSK + +/****************** Bit definition for DMA_CHWAITSTATUS register ************************/ + +# define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS 0U +# define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE 5U +# define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_MSK BITS(DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS, DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE) +# define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_MSK + +/****************** Bit definition for DMA_CHSWREQ register ************************/ + +# define DMA_CHSWREQ_CHSWREQ_POSS 0U +# define DMA_CHSWREQ_CHSWREQ_POSE 5U +# define DMA_CHSWREQ_CHSWREQ_MSK BITS(DMA_CHSWREQ_CHSWREQ_POSS, DMA_CHSWREQ_CHSWREQ_POSE) +# define DMA_CHSWREQ_CHSWREQ DMA_CHSWREQ_CHSWREQ_MSK + +/****************** Bit definition for DMA_CHUSEBURSTSET register ************************/ + +# define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS 0U +# define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE 5U +# define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_MSK BITS(DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS, DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE) +# define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_MSK + +/****************** Bit definition for DMA_CHUSEBURSTCLR register ************************/ + +# define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS 0U +# define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE 5U +# define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_MSK BITS(DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS, DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE) +# define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_MSK + +/****************** Bit definition for DMA_CHREQMASKSET register ************************/ + +# define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS 0U +# define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE 5U +# define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_MSK BITS(DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS, DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE) +# define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_MSK + +/****************** Bit definition for DMA_CHREQMASKCLR register ************************/ + +# define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS 0U +# define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE 5U +# define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_MSK BITS(DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS, DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE) +# define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_MSK + +/****************** Bit definition for DMA_CHENSET register ************************/ + +# define DMA_CHENSET_CHNL_ENABLE_SET_POSS 0U +# define DMA_CHENSET_CHNL_ENABLE_SET_POSE 5U +# define DMA_CHENSET_CHNL_ENABLE_SET_MSK BITS(DMA_CHENSET_CHNL_ENABLE_SET_POSS, DMA_CHENSET_CHNL_ENABLE_SET_POSE) +# define DMA_CHENSET_CHNL_ENABLE_SET DMA_CHENSET_CHNL_ENABLE_SET_MSK + +/****************** Bit definition for DMA_CHENCLR register ************************/ + +# define DMA_CHENCLR_CHNL_ENABLE_CLR_POSS 0U +# define DMA_CHENCLR_CHNL_ENABLE_CLR_POSE 5U +# define DMA_CHENCLR_CHNL_ENABLE_CLR_MSK BITS(DMA_CHENCLR_CHNL_ENABLE_CLR_POSS, DMA_CHENCLR_CHNL_ENABLE_CLR_POSE) +# define DMA_CHENCLR_CHNL_ENABLE_CLR DMA_CHENCLR_CHNL_ENABLE_CLR_MSK + +/****************** Bit definition for DMA_CHPRIALTSET register ************************/ + +# define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS 0U +# define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE 5U +# define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_MSK BITS(DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS, DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE) +# define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_MSK + +/****************** Bit definition for DMA_CHPRIALTCLR register ************************/ + +# define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS 0U +# define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE 5U +# define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_MSK BITS(DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS, DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE) +# define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_MSK + +/****************** Bit definition for DMA_CHPRSET register ************************/ + +# define DMA_CHPRSET_CHNL_PRIORITY_SET_POSS 0U +# define DMA_CHPRSET_CHNL_PRIORITY_SET_POSE 5U +# define DMA_CHPRSET_CHNL_PRIORITY_SET_MSK BITS(DMA_CHPRSET_CHNL_PRIORITY_SET_POSS, DMA_CHPRSET_CHNL_PRIORITY_SET_POSE) +# define DMA_CHPRSET_CHNL_PRIORITY_SET DMA_CHPRSET_CHNL_PRIORITY_SET_MSK + +/****************** Bit definition for DMA_CHPRCLR register ************************/ + +# define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS 0U +# define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE 5U +# define DMA_CHPRCLR_CHNL_PRIORITY_CLR_MSK BITS(DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS, DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE) +# define DMA_CHPRCLR_CHNL_PRIORITY_CLR DMA_CHPRCLR_CHNL_PRIORITY_CLR_MSK + +/****************** Bit definition for DMA_ERRCLR register ************************/ + +# define DMA_ERRCLR_ERR_CLR_POS 0U +# define DMA_ERRCLR_ERR_CLR_MSK BIT(DMA_ERRCLR_ERR_CLR_POS) +# define DMA_ERRCLR_ERR_CLR DMA_ERRCLR_ERR_CLR_MSK + +/****************** Bit definition for DMA Interrupt register ************************/ + +# define DMA_II_CH5DONE_POS 5U +# define DMA_II_CH5DONE_MSK BIT(DMA_II_CH5DONE_POS) +# define DMA_II_CH5DONE DMA_II_CH5DONE_MSK + +# define DMA_II_CH4DONE_POS 4U +# define DMA_II_CH4DONE_MSK BIT(DMA_II_CH4DONE_POS) +# define DMA_II_CH4DONE DMA_II_CH4DONE_MSK + +# define DMA_II_CH3DONE_POS 3U +# define DMA_II_CH3DONE_MSK BIT(DMA_II_CH3DONE_POS) +# define DMA_II_CH3DONE DMA_II_CH3DONE_MSK + +# define DMA_II_CH2DONE_POS 2U +# define DMA_II_CH2DONE_MSK BIT(DMA_II_CH2DONE_POS) +# define DMA_II_CH2DONE DMA_II_CH2DONE_MSK + +# define DMA_II_CH1DONE_POS 1U +# define DMA_II_CH1DONE_MSK BIT(DMA_II_CH1DONE_POS) +# define DMA_II_CH1DONE DMA_II_CH1DONE_MSK + +# define DMA_II_CH0DONE_POS 0U +# define DMA_II_CH0DONE_MSK BIT(DMA_II_CH0DONE_POS) +# define DMA_II_CH0DONE DMA_II_CH0DONE_MSK + +/****************** Bit definition for DMA_CH_SELCON register ************************/ + +# define DMA_CH_SELCON_MSIGSEL_POSS 0U +# define DMA_CH_SELCON_MSIGSEL_POSE 6U +# define DMA_CH_SELCON_MSIGSEL_MSK BITS(DMA_CH_SELCON_MSIGSEL_POSS, DMA_CH_SELCON_MSIGSEL_POSE) +# define DMA_CH_SELCON_MSIGSEL DMA_CH_SELCON_MSIGSEL_MSK + +/****************** Bit definition for CHANNEL_SRC_DATA_END_PTR register ************************/ + +# define CHANNEL_SRC_DATA_END_PTR_SRC_DATA_END_PTR_POSS 0U +# define CHANNEL_SRC_DATA_END_PTR_SRC_DATA_END_PTR_POSE 31U +# define CHANNEL_SRC_DATA_END_PTR_SRC_DATA_END_PTR_MSK BITS(CHANNEL_SRC_DATA_END_PTR_SRC_DATA_END_PTR_POSS, CHANNEL_SRC_DATA_END_PTR_SRC_DATA_END_PTR_POSE) +# define CHANNEL_SRC_DATA_END_PTR_SRC_DATA_END_PTR CHANNEL_SRC_DATA_END_PTR_SRC_DATA_END_PTR_MSK + +/****************** Bit definition for CHANNEL_DST_DATA_END_PTR register ************************/ + +# define CHANNEL_DST_DATA_END_PTR_DST_DATA_END_PTR_POSS 0U +# define CHANNEL_DST_DATA_END_PTR_DST_DATA_END_PTR_POSE 31U +# define CHANNEL_DST_DATA_END_PTR_DST_DATA_END_PTR_MSK BITS(CHANNEL_DST_DATA_END_PTR_DST_DATA_END_PTR_POSS, CHANNEL_DST_DATA_END_PTR_DST_DATA_END_PTR_POSE) +# define CHANNEL_DST_DATA_END_PTR_DST_DATA_END_PTR CHANNEL_DST_DATA_END_PTR_DST_DATA_END_PTR_MSK + +/****************** Bit definition for CHANNEL_CFG register ************************/ + +# define CHANNEL_CFG_DST_INC_POSS 30U +# define CHANNEL_CFG_DST_INC_POSE 31U +# define CHANNEL_CFG_DST_INC_MSK BITS(CHANNEL_CFG_DST_INC_POSS, CHANNEL_CFG_DST_INC_POSE) +# define CHANNEL_CFG_DST_INC CHANNEL_CFG_DST_INC_MSK + +# define CHANNEL_CFG_DST_SIZE_POSS 28U +# define CHANNEL_CFG_DST_SIZE_POSE 29U +# define CHANNEL_CFG_DST_SIZE_MSK BITS(CHANNEL_CFG_DST_SIZE_POSS, CHANNEL_CFG_DST_SIZE_POSE) +# define CHANNEL_CFG_DST_SIZE CHANNEL_CFG_DST_SIZE_MSK + +# define CHANNEL_CFG_SRC_INC_POSS 26U +# define CHANNEL_CFG_SRC_INC_POSE 27U +# define CHANNEL_CFG_SRC_INC_MSK BITS(CHANNEL_CFG_SRC_INC_POSS, CHANNEL_CFG_SRC_INC_POSE) +# define CHANNEL_CFG_SRC_INC CHANNEL_CFG_SRC_INC_MSK + +# define CHANNEL_CFG_SRC_SIZE_POSS 24U +# define CHANNEL_CFG_SRC_SIZE_POSE 25U +# define CHANNEL_CFG_SRC_SIZE_MSK BITS(CHANNEL_CFG_SRC_SIZE_POSS, CHANNEL_CFG_SRC_SIZE_POSE) +# define CHANNEL_CFG_SRC_SIZE CHANNEL_CFG_SRC_SIZE_MSK + +# define CHANNEL_CFG_DST_PROT_CTRL_POSS 21U +# define CHANNEL_CFG_DST_PROT_CTRL_POSE 23U +# define CHANNEL_CFG_DST_PROT_CTRL_MSK BITS(CHANNEL_CFG_DST_PROT_CTRL_POSS, CHANNEL_CFG_DST_PROT_CTRL_POSE) +# define CHANNEL_CFG_DST_PROT_CTRL CHANNEL_CFG_DST_PROT_CTRL_MSK + +# define CHANNEL_CFG_SRC_PROT_CTRL_POSS 18U +# define CHANNEL_CFG_SRC_PROT_CTRL_POSE 20U +# define CHANNEL_CFG_SRC_PROT_CTRL_MSK BITS(CHANNEL_CFG_SRC_PROT_CTRL_POSS, CHANNEL_CFG_SRC_PROT_CTRL_POSE) +# define CHANNEL_CFG_SRC_PROT_CTRL CHANNEL_CFG_SRC_PROT_CTRL_MSK + +# define CHANNEL_CFG_R_POWER_POSS 14U +# define CHANNEL_CFG_R_POWER_POSE 17U +# define CHANNEL_CFG_R_POWER_MSK BITS(CHANNEL_CFG_R_POWER_POSS, CHANNEL_CFG_R_POWER_POSE) +# define CHANNEL_CFG_R_POWER CHANNEL_CFG_R_POWER_MSK + +# define CHANNEL_CFG_N_MINUS_1_POSS 4U +# define CHANNEL_CFG_N_MINUS_1_POSE 13U +# define CHANNEL_CFG_N_MINUS_1_MSK BITS(CHANNEL_CFG_N_MINUS_1_POSS, CHANNEL_CFG_N_MINUS_1_POSE) +# define CHANNEL_CFG_N_MINUS_1 CHANNEL_CFG_N_MINUS_1_MSK + +# define CHANNEL_CFG_NEXT_USEBURST_POS 3U +# define CHANNEL_CFG_NEXT_USEBURST_MSK BIT(CHANNEL_CFG_NEXT_USEBURST_POS) +# define CHANNEL_CFG_NEXT_USEBURST CHANNEL_CFG_NEXT_USEBURST_MSK + +# define CHANNEL_CFG_CYCLE_CTRL_POSS 0U +# define CHANNEL_CFG_CYCLE_CTRL_POSE 2U +# define CHANNEL_CFG_CYCLE_CTRL_MSK BITS(CHANNEL_CFG_CYCLE_CTRL_POSS, CHANNEL_CFG_CYCLE_CTRL_POSE) +# define CHANNEL_CFG_CYCLE_CTRL CHANNEL_CFG_CYCLE_CTRL_MSK + +typedef struct +{ + __I uint32_t STATUS; // 0x000 + __O uint32_t CFG; // 0x004 + __IO uint32_t RESERVED0[2]; // 0x008-0x00c + __I uint32_t CHWAITSTATUS; // 0x010 + __O uint32_t CHSWREQ; // 0x014 + __IO uint32_t CHUSEBURSTSET; // 0x018 + __O uint32_t CHUSEBURSTCLR; // 0x01c + __IO uint32_t CHREQMASKSET; // 0x020 + __O uint32_t CHREQMASKCLR; // 0x024 + __IO uint32_t CHENSET; // 0x028 + __O uint32_t CHENCLR; // 0x02c + __IO uint32_t CHPRIALTSET; // 0x030 + __O uint32_t CHPRIALTCLR; // 0x034 + __IO uint32_t CHPRSET; // 0x038 + __O uint32_t CHPRCLR; // 0x03c + __IO uint32_t RESERVED1[3]; // 0x040-0x048 + __IO uint32_t ERRCLR; // 0x04c + __O uint32_t IER; // 0x050 + __O uint32_t IDR; // 0x054 + __I uint32_t IVS; // 0x058 + __I uint32_t RIF; // 0x05c + __I uint32_t IFM; // 0x060 + __O uint32_t ICR; // 0x064 + __IO uint32_t RESERVED2[2]; // 0x068-0x06c + __IO uint32_t CH0_SELCON; // 0x070 + __IO uint32_t CH1_SELCON; // 0x074 + __IO uint32_t CH2_SELCON; // 0x078 + __IO uint32_t CH3_SELCON; // 0x07c + __IO uint32_t CH4_SELCON; // 0x080 + __IO uint32_t CH5_SELCON; // 0x084 + __IO uint32_t RESERVED3[30]; // 0x088-0x0fc + __IO uint32_t PRI_CH00_SRC_DATA_END_PTR; // 0x100 + __IO uint32_t PRI_CH00_DST_DATA_END_PTR; // 0x104 + __IO uint32_t PRI_CH00_CHANNEL_CFG; // 0x108 + __IO uint32_t RESERVED4; // 0x10c + __IO uint32_t PRI_CH01_SRC_DATA_END_PTR; // 0x110 + __IO uint32_t PRI_CH01_DST_DATA_END_PTR; // 0x114 + __IO uint32_t PRI_CH01_CHANNEL_CFG; // 0x118 + __IO uint32_t RESERVED5; // 0x11c + __IO uint32_t PRI_CH02_SRC_DATA_END_PTR; // 0x120 + __IO uint32_t PRI_CH02_DST_DATA_END_PTR; // 0x124 + __IO uint32_t PRI_CH02_CHANNEL_CFG; // 0x128 + __IO uint32_t RESERVED6; // 0x12c + __IO uint32_t PRI_CH03_SRC_DATA_END_PTR; // 0x130 + __IO uint32_t PRI_CH03_DST_DATA_END_PTR; // 0x134 + __IO uint32_t PRI_CH03_CHANNEL_CFG; // 0x138 + __IO uint32_t RESERVED7; // 0x13c + __IO uint32_t PRI_CH04_SRC_DATA_END_PTR; // 0x140 + __IO uint32_t PRI_CH04_DST_DATA_END_PTR; // 0x144 + __IO uint32_t PRI_CH04_CHANNEL_CFG; // 0x148 + __IO uint32_t RESERVED8; // 0x14c + __IO uint32_t PRI_CH05_SRC_DATA_END_PTR; // 0x150 + __IO uint32_t PRI_CH05_DST_DATA_END_PTR; // 0x154 + __IO uint32_t PRI_CH05_CHANNEL_CFG; // 0x158 + __IO uint32_t RESERVED9; // 0x15c + __IO uint32_t RESERVED10[40]; // 0x160-0x1fc + __IO uint32_t ALT_CH00_SRC_DATA_END_PTR; // 0x200 + __IO uint32_t ALT_CH00_DST_DATA_END_PTR; // 0x204 + __IO uint32_t ALT_CH00_CHANNEL_CFG; // 0x208 + __IO uint32_t RESERVED11; // 0x20c + __IO uint32_t ALT_CH01_SRC_DATA_END_PTR; // 0x210 + __IO uint32_t ALT_CH01_DST_DATA_END_PTR; // 0x214 + __IO uint32_t ALT_CH01_CHANNEL_CFG; // 0x218 + __IO uint32_t RESERVED12; // 0x21c + __IO uint32_t ALT_CH02_SRC_DATA_END_PTR; // 0x220 + __IO uint32_t ALT_CH02_DST_DATA_END_PTR; // 0x224 + __IO uint32_t ALT_CH02_CHANNEL_CFG; // 0x228 + __IO uint32_t RESERVED13; // 0x22c + __IO uint32_t ALT_CH03_SRC_DATA_END_PTR; // 0x230 + __IO uint32_t ALT_CH03_DST_DATA_END_PTR; // 0x234 + __IO uint32_t ALT_CH03_CHANNEL_CFG; // 0x238 + __IO uint32_t RESERVED14; // 0x23c + __IO uint32_t ALT_CH04_SRC_DATA_END_PTR; // 0x240 + __IO uint32_t ALT_CH04_DST_DATA_END_PTR; // 0x244 + __IO uint32_t ALT_CH04_CHANNEL_CFG; // 0x248 + __IO uint32_t RESERVED15; // 0x24c + __IO uint32_t ALT_CH05_SRC_DATA_END_PTR; // 0x250 + __IO uint32_t ALT_CH05_DST_DATA_END_PTR; // 0x254 + __IO uint32_t ALT_CH05_CHANNEL_CFG; // 0x258 + __IO uint32_t RESERVED16; // 0x25c +} DMA_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_exti.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_exti.h new file mode 100644 index 00000000000..c8dd2253f84 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_exti.h @@ -0,0 +1,289 @@ +/********************************************************************************** + * + * @file reg_exti.h + * @brief EXTI Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __EXTI_H__ +#define __EXTI_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +////#pragma anon_unions + +/****************** Bit definition for EXTI_IER register ************************/ + +# define EXTI_IER_WAKEUP_POS 21U +# define EXTI_IER_WAKEUP_MSK BIT(EXTI_IER_WAKEUP_POS) +# define EXTI_IER_WAKEUP EXTI_IER_WAKEUP_MSK + +# define EXTI_IER_LVD_POS 20U +# define EXTI_IER_LVD_MSK BIT(EXTI_IER_LVD_POS) +# define EXTI_IER_LVD EXTI_IER_LVD_MSK + +# define EXTI_IER_CMP2_POS 17U +# define EXTI_IER_CMP2_MSK BIT(EXTI_IER_CMP2_POS) +# define EXTI_IER_CMP2 EXTI_IER_CMP2_MSK + +# define EXTI_IER_CMP1_POS 16U +# define EXTI_IER_CMP1_MSK BIT(EXTI_IER_CMP1_POS) +# define EXTI_IER_CMP1 EXTI_IER_CMP1_MSK + +# define EXTI_IER_GPIOy_POSS 0U +# define EXTI_IER_GPIOy_POSE 15U +# define EXTI_IER_GPIOy_MSK BITS(EXTI_IER_GPIOy_POSS, EXTI_IER_GPIOy_POSE) +# define EXTI_IER_GPIOy EXTI_IER_GPIOy_MSK + +/****************** Bit definition for EXTI_IDR register ************************/ + +# define EXTI_IDR_WAKEUP_POS 21U +# define EXTI_IDR_WAKEUP_MSK BIT(EXTI_IDR_WAKEUP_POS) +# define EXTI_IDR_WAKEUP EXTI_IDR_WAKEUP_MSK + +# define EXTI_IDR_LVD_POS 20U +# define EXTI_IDR_LVD_MSK BIT(EXTI_IDR_LVD_POS) +# define EXTI_IDR_LVD EXTI_IDR_LVD_MSK + +# define EXTI_IDR_CMP2_POS 17U +# define EXTI_IDR_CMP2_MSK BIT(EXTI_IDR_CMP2_POS) +# define EXTI_IDR_CMP2 EXTI_IDR_CMP2_MSK + +# define EXTI_IDR_CMP1_POS 16U +# define EXTI_IDR_CMP1_MSK BIT(EXTI_IDR_CMP1_POS) +# define EXTI_IDR_CMP1 EXTI_IDR_CMP1_MSK + +# define EXTI_IDR_GPIOy_POSS 0U +# define EXTI_IDR_GPIOy_POSE 15U +# define EXTI_IDR_GPIOy_MSK BITS(EXTI_IDR_GPIOy_POSS, EXTI_IDR_GPIOy_POSE) +# define EXTI_IDR_GPIOy EXTI_IDR_GPIOy_MSK + +/****************** Bit definition for EXTI_IVS register ************************/ + +# define EXTI_IVS_WAKEUP_POS 21U +# define EXTI_IVS_WAKEUP_MSK BIT(EXTI_IVS_WAKEUP_POS) +# define EXTI_IVS_WAKEUP EXTI_IVS_WAKEUP_MSK + +# define EXTI_IVS_LVD_POS 20U +# define EXTI_IVS_LVD_MSK BIT(EXTI_IVS_LVD_POS) +# define EXTI_IVS_LVD EXTI_IVS_LVD_MSK + +# define EXTI_IVS_CMP2_POS 17U +# define EXTI_IVS_CMP2_MSK BIT(EXTI_IVS_CMP2_POS) +# define EXTI_IVS_CMP2 EXTI_IVS_CMP2_MSK + +# define EXTI_IVS_CMP1_POS 16U +# define EXTI_IVS_CMP1_MSK BIT(EXTI_IVS_CMP1_POS) +# define EXTI_IVS_CMP1 EXTI_IVS_CMP1_MSK + +# define EXTI_IVS_GPIOy_POSS 0U +# define EXTI_IVS_GPIOy_POSE 15U +# define EXTI_IVS_GPIOy_MSK BITS(EXTI_IVS_GPIOy_POSS, EXTI_IVS_GPIOy_POSE) +# define EXTI_IVS_GPIOy EXTI_IVS_GPIOy_MSK + +/****************** Bit definition for EXTI_RIF register ************************/ + +# define EXTI_RIF_WAKEUP_POS 21U +# define EXTI_RIF_WAKEUP_MSK BIT(EXTI_RIF_WAKEUP_POS) +# define EXTI_RIF_WAKEUP EXTI_RIF_WAKEUP_MSK + +# define EXTI_RIF_LVD_POS 20U +# define EXTI_RIF_LVD_MSK BIT(EXTI_RIF_LVD_POS) +# define EXTI_RIF_LVD EXTI_RIF_LVD_MSK + +# define EXTI_RIF_CMP2_POS 17U +# define EXTI_RIF_CMP2_MSK BIT(EXTI_RIF_CMP2_POS) +# define EXTI_RIF_CMP2 EXTI_RIF_CMP2_MSK + +# define EXTI_RIF_CMP1_POS 16U +# define EXTI_RIF_CMP1_MSK BIT(EXTI_RIF_CMP1_POS) +# define EXTI_RIF_CMP1 EXTI_RIF_CMP1_MSK + +# define EXTI_RIF_GPIOy_POSS 0U +# define EXTI_RIF_GPIOy_POSE 15U +# define EXTI_RIF_GPIOy_MSK BITS(EXTI_RIF_GPIOy_POSS, EXTI_RIF_GPIOy_POSE) +# define EXTI_RIF_GPIOy EXTI_RIF_GPIOy_MSK + +/****************** Bit definition for EXTI_IFM register ************************/ + +# define EXTI_IFM_WAKEUP_POS 21U +# define EXTI_IFM_WAKEUP_MSK BIT(EXTI_IFM_WAKEUP_POS) +# define EXTI_IFM_WAKEUP EXTI_IFM_WAKEUP_MSK + +# define EXTI_IFM_LVD_POS 20U +# define EXTI_IFM_LVD_MSK BIT(EXTI_IFM_LVD_POS) +# define EXTI_IFM_LVD EXTI_IFM_LVD_MSK + +# define EXTI_IFM_CMP2_POS 17U +# define EXTI_IFM_CMP2_MSK BIT(EXTI_IFM_CMP2_POS) +# define EXTI_IFM_CMP2 EXTI_IFM_CMP2_MSK + +# define EXTI_IFM_CMP1_POS 16U +# define EXTI_IFM_CMP1_MSK BIT(EXTI_IFM_CMP1_POS) +# define EXTI_IFM_CMP1 EXTI_IFM_CMP1_MSK + +# define EXTI_IFM_GPIOy_POSS 0U +# define EXTI_IFM_GPIOy_POSE 15U +# define EXTI_IFM_GPIOy_MSK BITS(EXTI_IFM_GPIOy_POSS, EXTI_IFM_GPIOy_POSE) +# define EXTI_IFM_GPIOy EXTI_IFM_GPIOy_MSK + +/****************** Bit definition for EXTI_ICR register ************************/ + +# define EXTI_ICR_WAKEUP_POS 21U +# define EXTI_ICR_WAKEUP_MSK BIT(EXTI_ICR_WAKEUP_POS) +# define EXTI_ICR_WAKEUP EXTI_ICR_WAKEUP_MSK + +# define EXTI_ICR_LVD_POS 20U +# define EXTI_ICR_LVD_MSK BIT(EXTI_ICR_LVD_POS) +# define EXTI_ICR_LVD EXTI_ICR_LVD_MSK + +# define EXTI_ICR_CMP2_POS 17U +# define EXTI_ICR_CMP2_MSK BIT(EXTI_ICR_CMP2_POS) +# define EXTI_ICR_CMP2 EXTI_ICR_CMP2_MSK + +# define EXTI_ICR_CMP1_POS 16U +# define EXTI_ICR_CMP1_MSK BIT(EXTI_ICR_CMP1_POS) +# define EXTI_ICR_CMP1 EXTI_ICR_CMP1_MSK + +# define EXTI_ICR_GPIOy_POSS 0U +# define EXTI_ICR_GPIOy_POSE 15U +# define EXTI_ICR_GPIOy_MSK BITS(EXTI_ICR_GPIOy_POSS, EXTI_ICR_GPIOy_POSE) +# define EXTI_ICR_GPIOy EXTI_ICR_GPIOy_MSK + +/****************** Bit definition for EXTI_RTS register ************************/ + +//# define EXTI_RTS_RTSy_POSS 20U +//# define EXTI_RTS_RTSy_POSE 21U +//# define EXTI_RTS_RTSy_MSK BITS(EXTI_RTS_RTSy_POSS, EXTI_RTS_RTSy_POSE) +//# define EXTI_RTS_RTSy EXTI_RTS_RTSy_MSK + +# define EXTI_RTS_RTSy_POSS 0U +# define EXTI_RTS_RTSy_POSE 21U +# define EXTI_RTS_RTSy_MSK BITS(EXTI_RTS_RTSy_POSS, EXTI_RTS_RTSy_POSE) +# define EXTI_RTS_RTSy EXTI_RTS_RTSy_MSK + +/****************** Bit definition for EXTI_FTS register ************************/ + +//# define EXTI_FTS_FTSy_POSS 20U +//# define EXTI_FTS_FTSy_POSE 21U +//# define EXTI_FTS_FTSy_MSK BITS(EXTI_FTS_FTSy_POSS, EXTI_FTS_FTSy_POSE) +//# define EXTI_FTS_FTSy EXTI_FTS_FTSy_MSK + +# define EXTI_FTS_FTSy_POSS 0U +# define EXTI_FTS_FTSy_POSE 21U +# define EXTI_FTS_FTSy_MSK BITS(EXTI_FTS_FTSy_POSS, EXTI_FTS_FTSy_POSE) +# define EXTI_FTS_FTSy EXTI_FTS_FTSy_MSK + +/****************** Bit definition for EXTI_SWI register ************************/ + +//# define EXTI_SWI_SWIy_POSS 20U +//# define EXTI_SWI_SWIy_POSE 21U +//# define EXTI_SWI_SWIy_MSK BITS(EXTI_SWI_SWIy_POSS, EXTI_SWI_SWIy_POSE) +//# define EXTI_SWI_SWIy EXTI_SWI_SWIy_MSK + +# define EXTI_SWI_SWIy_POSS 0U +# define EXTI_SWI_SWIy_POSE 21U +# define EXTI_SWI_SWIy_MSK BITS(EXTI_SWI_SWIy_POSS, EXTI_SWI_SWIy_POSE) +# define EXTI_SWI_SWIy EXTI_SWI_SWIy_MSK + +/****************** Bit definition for EXTI_ADTE1 register ************************/ + +# define EXTI_ADTE1_ADTEy_POSS 0U +# define EXTI_ADTE1_ADTEy_POSE 17U +# define EXTI_ADTE1_ADTEy_MSK BITS(EXTI_ADTE1_ADTEy_POSS, EXTI_ADTE1_ADTEy_POSE) +# define EXTI_ADTE1_ADTEy EXTI_ADTE1_ADTEy_MSK + +/****************** Bit definition for EXTI_ADTE2 register ************************/ + +# define EXTI_ADTE2_ADTEy_POSS 0U +# define EXTI_ADTE2_ADTEy_POSE 17U +# define EXTI_ADTE2_ADTEy_MSK BITS(EXTI_ADTE2_ADTEy_POSS, EXTI_ADTE2_ADTEy_POSE) +# define EXTI_ADTE2_ADTEy EXTI_ADTE2_ADTEy_MSK + +/****************** Bit definition for EXTI_DB register ************************/ + +//# define EXTI_DB_DBENy_POSS 20U +//# define EXTI_DB_DBENy_POSE 21U +//# define EXTI_DB_DBENy_MSK BITS(EXTI_DB_DBENy_POSS, EXTI_DB_DBENy_POSE) +//# define EXTI_DB_DBENy EXTI_DB_DBENy_MSK + +# define EXTI_DB_DBENy_POSS 0U +# define EXTI_DB_DBENy_POSE 21U +# define EXTI_DB_DBENy_MSK BITS(EXTI_DB_DBENy_POSS, EXTI_DB_DBENy_POSE) +# define EXTI_DB_DBENy EXTI_DB_DBENy_MSK + +/****************** Bit definition for EXTI_DBC register ************************/ + +# define EXTI_DBC_DBPRE_POSS 8U +# define EXTI_DBC_DBPRE_POSE 15U +# define EXTI_DBC_DBPRE_MSK BITS(EXTI_DBC_DBPRE_POSS, EXTI_DBC_DBPRE_POSE) +# define EXTI_DBC_DBPRE EXTI_DBC_DBPRE_MSK + +# define EXTI_DBC_DBCNT_POSS 0U +# define EXTI_DBC_DBCNT_POSE 2U +# define EXTI_DBC_DBCNT_MSK BITS(EXTI_DBC_DBCNT_POSS, EXTI_DBC_DBCNT_POSE) +# define EXTI_DBC_DBCNT EXTI_DBC_DBCNT_MSK + +/****************** Bit definition for EXTI_ICFG1 register ************************/ + +# define EXTI_ICFG1_EXTIy_POSS 0U +# define EXTI_ICFG1_EXTIy_POSE 31U +# define EXTI_ICFG1_EXTIy_MSK BITS(EXTI_ICFG1_EXTIy_POSS, EXTI_ICFG1_EXTIy_POSE) +# define EXTI_ICFG1_EXTIy EXTI_ICFG1_EXTIy_MSK + +/****************** Bit definition for EXTI_ICFG2 register ************************/ + +# define EXTI_ICFG2_EXTIy_POSS 0U +# define EXTI_ICFG2_EXTIy_POSE 31U +# define EXTI_ICFG2_EXTIy_MSK BITS(EXTI_ICFG2_EXTIy_POSS, EXTI_ICFG2_EXTIy_POSE) +# define EXTI_ICFG2_EXTIy EXTI_ICFG2_EXTIy_MSK + +typedef struct +{ + __O uint32_t IER; // 0x000 + __O uint32_t IDR; // 0x004 + __I uint32_t IVS; // 0x008 + __I uint32_t RIF; // 0x00c + __I uint32_t IFM; // 0x010 + __O uint32_t ICR; // 0x014 + __IO uint32_t RTS; // 0x018 + __IO uint32_t FTS; // 0x01c + __IO uint32_t SWI; // 0x020 + __IO uint32_t ADTE1; // 0x024 + __IO uint32_t ADTE2; // 0x028 + __IO uint32_t DB; // 0x02c + __IO uint32_t DBC; // 0x030 + __IO uint32_t ICFG1; // 0x034 + __IO uint32_t ICFG2; // 0x038 +} EXTI_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_fc.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_fc.h new file mode 100644 index 00000000000..e717c08a269 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_fc.h @@ -0,0 +1,227 @@ +/********************************************************************************** + * + * @file reg_fc.h + * @brief FC Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __FC_H__ +#define __FC_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* ////#pragma anon_unions */ + +/****************** Bit definition for FC_CMD register ************************/ + +#define FC_CMD_CMD_POSS 0U +#define FC_CMD_CMD_POSE 7U +#define FC_CMD_CMD_MSK BITS(FC_CMD_CMD_POSS,FC_CMD_CMD_POSE) +#define FC_CMD_CMD FC_CMD_CMD_MSK + +/****************** Bit definition for FC_PA register ************************/ + +#define FC_PA_PCNT_POSS 25U +#define FC_PA_PCNT_POSE 31U +#define FC_PA_PCNT_MSK BITS(FC_PA_PCNT_POSS,FC_PA_PCNT_POSE) +#define FC_PA_PCNT FC_PA_PCNT_MSK + +#define FC_PA_IFREN_POS 24U +#define FC_PA_IFREN_MSK BIT(FC_PA_IFREN_POS) +#define FC_PA_IFREN FC_PA_IFREN_MSK + +#define FC_PA_PA_POSS 0U +#define FC_PA_PA_POSE 23U +#define FC_PA_PA_MSK BITS(FC_PA_PA_POSS,FC_PA_PA_POSE) +#define FC_PA_PA FC_PA_PA_MSK + +/****************** Bit definition for FC_PLD register ************************/ + +#define FC_PLD_PLD_POSS 0U +#define FC_PLD_PLD_POSE 31U +#define FC_PLD_PLD_MSK BITS(FC_PLD_PLD_POSS,FC_PLD_PLD_POSE) +#define FC_PLD_PLD FC_PLD_PLD_MSK + +/****************** Bit definition for FC_CTL register ************************/ + +#define FC_CTL_FCSLEEP_POS 10U +#define FC_CTL_FCSLEEP_MSK BIT(FC_CTL_FCSLEEP_POS) +#define FC_CTL_FCSLEEP FC_CTL_FCSLEEP_MSK + +#define FC_CTL_PFEN_POS 8U +#define FC_CTL_PFEN_MSK BIT(FC_CTL_PFEN_POS) +#define FC_CTL_PFEN FC_CTL_PFEN_MSK + +#define FC_CTL_OPRLD_POSS 4U +#define FC_CTL_OPRLD_POSE 7U +#define FC_CTL_OPRLD_MSK BITS(FC_CTL_OPRLD_POSS, FC_CTL_OPRLD_POSE) +#define FC_CTL_OPRLD FC_CTL_OPRLD_MSK + +#define FC_CTL_WAIT_POSS 0U +#define FC_CTL_WAIT_POSE 1U +#define FC_CTL_WAIT_MSK BITS(FC_CTL_WAIT_POSS, FC_CTL_WAIT_POSE) +#define FC_CTL_WAIT FC_CTL_WAIT_MSK + +/****************** Bit definition for FC_STA register ************************/ + +#define FC_STA_OPRLDLOOP_POSS 8U +#define FC_STA_OPRLDLOOP_POSE 11U +#define FC_STA_OPRLDLOOP_MSK BITS(FC_STA_OPRLDLOOP_POSS, FC_STA_OPRLDLOOP_POSE) +#define FC_STA_OPRLDLOOP FC_STA_OPRLDLOOP_MSK + +#define FC_STA_PRTAREARD_POS 7U +#define FC_STA_PRTAREARD_MSK BIT(FC_STA_PRTAREARD_POS) +#define FC_STA_PRTAREARD FC_STA_PRTAREARD_MSK + +#define FC_STA_PRTAREAWR_POS 6U +#define FC_STA_PRTAREAWR_MSK BIT(FC_STA_PRTAREAWR_POS) +#define FC_STA_PRTAREAWR FC_STA_PRTAREAWR_MSK + +#define FC_STA_CMDULK_POS 5U +#define FC_STA_CMDULK_MSK BIT(FC_STA_CMDULK_POS) +#define FC_STA_CMDULK FC_STA_CMDULK_MSK + +#define FC_STA_FCBUSY_POS 4U +#define FC_STA_FCBUSY_MSK BIT(FC_STA_FCBUSY_POS) +#define FC_STA_FCBUSY FC_STA_FCBUSY_MSK + +#define FC_STA_WPDIS_POS 3U +#define FC_STA_WPDIS_MSK BIT(FC_STA_WPDIS_POS) +#define FC_STA_WPDIS FC_STA_WPDIS_MSK + +#define FC_STA_RPLV_POSS 1U +#define FC_STA_RPLV_POSE 2U +#define FC_STA_RPLV_MSK BITS(FC_STA_RPLV_POSS, FC_STA_RPLV_POSE) +#define FC_STA_RPLV FC_STA_RPLV_MSK + +#define FC_STA_UCRPDIS_POS 0U +#define FC_STA_UCRPDIS_MSK BIT(FC_STA_UCRPDIS_POS) +#define FC_STA_UCRPDIS FC_STA_UCRPDIS_MSK + +/****************** Bit definition for FC_UPL register ************************/ + +#define FC_UPL_UPL_POSS 0U +#define FC_UPL_UPL_POSE 31U +#define FC_UPL_UPL_MSK BITS(FC_UPL_UPL_POSS,FC_UPL_UPL_POSE) +#define FC_UPL_UPL FC_UPL_UPL_MSK + +/****************** Bit definition for FC_UPH register ************************/ + +#define FC_UPH_UPH_POSS 0U +#define FC_UPH_UPH_POSE 31U +#define FC_UPH_UPH_MSK BITS(FC_UPH_UPH_POSS,FC_UPH_UPH_POSE) +#define FC_UPH_UPH FC_UPH_UPH_MSK + +/****************** Bit definition for FC_UL register ************************/ + +#define FC_UL_UL_POSS 0U +#define FC_UL_UL_POSE 31U +#define FC_UL_UL_MSK BITS(FC_UL_UL_POSS,FC_UL_UL_POSE) +#define FC_UL_UL FC_UL_UL_MSK + +/****************** Bit definition for FC_UCRPL register ************************/ + +#define FC_UCRPL_UCRPL_POSS 0U +#define FC_UCRPL_UCRPL_POSE 31U +#define FC_UCRPL_UCRPL_MSK BITS(FC_UCRPL_UCRPL_POSS,FC_UCRPL_UCRPL_POSE) +#define FC_UCRPL_UCRPL FC_UCRPL_UCRPL_MSK + +/****************** Bit definition for FC_UCRPH register ************************/ + +#define FC_UCRPH_UCRPH_POSS 0U +#define FC_UCRPH_UCRPH_POSE 31U +#define FC_UCRPH_UCRPH_MSK BITS(FC_UCRPH_UCRPH_POSS,FC_UCRPH_UCRPH_POSE) +#define FC_UCRPH_UCRPH FC_UCRPH_UCRPH_MSK + +/****************** Bit definition for FC_RP register ************************/ + +#define FC_RP_RP_POSS 0U +#define FC_RP_RP_POSE 31U +#define FC_RP_RP_MSK BITS(FC_RP_RP_POSS,FC_RP_RP_POSE) +#define FC_RP_RP FC_RP_RP_MSK + +/****************** Bit definition for FC_WPL register ************************/ + +#define FC_WPL_WPL_POSS 0U +#define FC_WPL_WPL_POSE 31U +#define FC_WPL_WPL_MSK BITS(FC_WPL_WPL_POSS,FC_WPL_WPL_POSE) +#define FC_WPL_WPL FC_WPL_WPL_MSK + +/****************** Bit definition for FC_WPH register ************************/ + +#define FC_WPH_WPH_POSS 0U +#define FC_WPH_WPH_POSE 31U +#define FC_WPH_WPH_MSK BITS(FC_WPH_WPH_POSS,FC_WPH_WPH_POSE) +#define FC_WPH_WPH FC_WPH_WPH_MSK + +/****************** Bit definition for FC_REMAP register ************************/ + +#define FC_REMAP_BOOTBYP_POSS 16U +#define FC_REMAP_BOOTBYP_POSE 23U +#define FC_REMAP_BOOTBYP_MSK BITS(FC_REMAP_BOOTBYP_POSS,FC_REMAP_BOOTBYP_POSE) +#define FC_REMAP_BOOTBYP FC_REMAP_BOOTBYP_MSK + +#define FC_REMAP_SELECT_POSS 8U +#define FC_REMAP_SELECT_POSE 15U +#define FC_REMAP_SELECT_MSK BITS(FC_REMAP_SELECT_POSS,FC_REMAP_SELECT_POSE) +#define FC_REMAP_SELECT FC_REMAP_SELECT_MSK + +#define FC_REMAP_SEFBASE_POSS 0U +#define FC_REMAP_SEFBASE_POSE 7U +#define FC_REMAP_SEFBASE_MSK BITS(FC_REMAP_SEFBASE_POSS,FC_REMAP_SEFBASE_POSE) +#define FC_REMAP_SEFBASE FC_REMAP_SEFBASE_MSK + +typedef struct +{ + __IO uint32_t CMD; + __IO uint32_t PA; + __IO uint32_t PLD; + uint32_t RESERVED0 ; + __IO uint32_t CTL; + __IO uint32_t STAT; + uint32_t RESERVED1[2] ; + __IO uint32_t UPL; + __IO uint32_t UPH; + __IO uint32_t UL; + uint32_t RESERVED2[5] ; + __I uint32_t UCRPL; + __I uint32_t UCRPH; + __I uint32_t RP; + __I uint32_t WPL; + __I uint32_t WPH; + __I uint32_t REMAP; +} FC_TypeDef; + + + + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_gpio.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_gpio.h new file mode 100644 index 00000000000..80025083dfa --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_gpio.h @@ -0,0 +1,924 @@ +/********************************************************************************** + * + * @file reg_gpio.h + * @brief GPIO Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __GPIO_H__ +#define __GPIO_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + +/****************** Bit definition for GPIO_ID register ************************/ + +#define GPIO_ID_ID15_POS 15U +#define GPIO_ID_ID15_MSK BIT(GPIO_ID_ID15_POS) +#define GPIO_ID_ID15 GPIO_ID_ID15_MSK + +#define GPIO_ID_ID14_POS 14U +#define GPIO_ID_ID14_MSK BIT(GPIO_ID_ID14_POS) +#define GPIO_ID_ID14 GPIO_ID_ID14_MSK + +#define GPIO_ID_ID13_POS 13U +#define GPIO_ID_ID13_MSK BIT(GPIO_ID_ID13_POS) +#define GPIO_ID_ID13 GPIO_ID_ID13_MSK + +#define GPIO_ID_ID12_POS 12U +#define GPIO_ID_ID12_MSK BIT(GPIO_ID_ID12_POS) +#define GPIO_ID_ID12 GPIO_ID_ID12_MSK + +#define GPIO_ID_ID11_POS 11U +#define GPIO_ID_ID11_MSK BIT(GPIO_ID_ID11_POS) +#define GPIO_ID_ID11 GPIO_ID_ID11_MSK + +#define GPIO_ID_ID10_POS 10U +#define GPIO_ID_ID10_MSK BIT(GPIO_ID_ID10_POS) +#define GPIO_ID_ID10 GPIO_ID_ID10_MSK + +#define GPIO_ID_ID9_POS 9U +#define GPIO_ID_ID9_MSK BIT(GPIO_ID_ID9_POS) +#define GPIO_ID_ID9 GPIO_ID_ID9_MSK + +#define GPIO_ID_ID8_POS 8U +#define GPIO_ID_ID8_MSK BIT(GPIO_ID_ID8_POS) +#define GPIO_ID_ID8 GPIO_ID_ID8_MSK + +#define GPIO_ID_ID7_POS 7U +#define GPIO_ID_ID7_MSK BIT(GPIO_ID_ID7_POS) +#define GPIO_ID_ID7 GPIO_ID_ID7_MSK + +#define GPIO_ID_ID6_POS 6U +#define GPIO_ID_ID6_MSK BIT(GPIO_ID_ID6_POS) +#define GPIO_ID_ID6 GPIO_ID_ID6_MSK + +#define GPIO_ID_ID5_POS 5U +#define GPIO_ID_ID5_MSK BIT(GPIO_ID_ID5_POS) +#define GPIO_ID_ID5 GPIO_ID_ID5_MSK + +#define GPIO_ID_ID4_POS 4U +#define GPIO_ID_ID4_MSK BIT(GPIO_ID_ID4_POS) +#define GPIO_ID_ID4 GPIO_ID_ID4_MSK + +#define GPIO_ID_ID3_POS 3U +#define GPIO_ID_ID3_MSK BIT(GPIO_ID_ID3_POS) +#define GPIO_ID_ID3 GPIO_ID_ID3_MSK + +#define GPIO_ID_ID2_POS 2U +#define GPIO_ID_ID2_MSK BIT(GPIO_ID_ID2_POS) +#define GPIO_ID_ID2 GPIO_ID_ID2_MSK + +#define GPIO_ID_ID1_POS 1U +#define GPIO_ID_ID1_MSK BIT(GPIO_ID_ID1_POS) +#define GPIO_ID_ID1 GPIO_ID_ID1_MSK + +#define GPIO_ID_ID0_POS 0U +#define GPIO_ID_ID0_MSK BIT(GPIO_ID_ID0_POS) +#define GPIO_ID_ID0 GPIO_ID_ID0_MSK + +/****************** Bit definition for GPIO_OD register ************************/ + +#define GPIO_OD_OD15_POS 15U +#define GPIO_OD_OD15_MSK BIT(GPIO_OD_OD15_POS) +#define GPIO_OD_OD15 GPIO_OD_OD15_MSK + +#define GPIO_OD_OD14_POS 14U +#define GPIO_OD_OD14_MSK BIT(GPIO_OD_OD14_POS) +#define GPIO_OD_OD14 GPIO_OD_OD14_MSK + +#define GPIO_OD_OD13_POS 13U +#define GPIO_OD_OD13_MSK BIT(GPIO_OD_OD13_POS) +#define GPIO_OD_OD13 GPIO_OD_OD13_MSK + +#define GPIO_OD_OD12_POS 12U +#define GPIO_OD_OD12_MSK BIT(GPIO_OD_OD12_POS) +#define GPIO_OD_OD12 GPIO_OD_OD12_MSK + +#define GPIO_OD_OD11_POS 11U +#define GPIO_OD_OD11_MSK BIT(GPIO_OD_OD11_POS) +#define GPIO_OD_OD11 GPIO_OD_OD11_MSK + +#define GPIO_OD_OD10_POS 10U +#define GPIO_OD_OD10_MSK BIT(GPIO_OD_OD10_POS) +#define GPIO_OD_OD10 GPIO_OD_OD10_MSK + +#define GPIO_OD_OD9_POS 9U +#define GPIO_OD_OD9_MSK BIT(GPIO_OD_OD9_POS) +#define GPIO_OD_OD9 GPIO_OD_OD9_MSK + +#define GPIO_OD_OD8_POS 8U +#define GPIO_OD_OD8_MSK BIT(GPIO_OD_OD8_POS) +#define GPIO_OD_OD8 GPIO_OD_OD8_MSK + +#define GPIO_OD_OD7_POS 7U +#define GPIO_OD_OD7_MSK BIT(GPIO_OD_OD7_POS) +#define GPIO_OD_OD7 GPIO_OD_OD7_MSK + +#define GPIO_OD_OD6_POS 6U +#define GPIO_OD_OD6_MSK BIT(GPIO_OD_OD6_POS) +#define GPIO_OD_OD6 GPIO_OD_OD6_MSK + +#define GPIO_OD_OD5_POS 5U +#define GPIO_OD_OD5_MSK BIT(GPIO_OD_OD5_POS) +#define GPIO_OD_OD5 GPIO_OD_OD5_MSK + +#define GPIO_OD_OD4_POS 4U +#define GPIO_OD_OD4_MSK BIT(GPIO_OD_OD4_POS) +#define GPIO_OD_OD4 GPIO_OD_OD4_MSK + +#define GPIO_OD_OD3_POS 3U +#define GPIO_OD_OD3_MSK BIT(GPIO_OD_OD3_POS) +#define GPIO_OD_OD3 GPIO_OD_OD3_MSK + +#define GPIO_OD_OD2_POS 2U +#define GPIO_OD_OD2_MSK BIT(GPIO_OD_OD2_POS) +#define GPIO_OD_OD2 GPIO_OD_OD2_MSK + +#define GPIO_OD_OD1_POS 1U +#define GPIO_OD_OD1_MSK BIT(GPIO_OD_OD1_POS) +#define GPIO_OD_OD1 GPIO_OD_OD1_MSK + +#define GPIO_OD_OD0_POS 0U +#define GPIO_OD_OD0_MSK BIT(GPIO_OD_OD0_POS) +#define GPIO_OD_OD0 GPIO_OD_OD0_MSK + +/****************** Bit definition for GPIO_BSBR register ************************/ + +#define GPIO_BSBR_BR15_POS 31U +#define GPIO_BSBR_BR15_MSK BIT(GPIO_BSBR_BR15_POS) +#define GPIO_BSBR_BR15 GPIO_BSBR_BR15_MSK + +#define GPIO_BSBR_BR14_POS 30U +#define GPIO_BSBR_BR14_MSK BIT(GPIO_BSBR_BR14_POS) +#define GPIO_BSBR_BR14 GPIO_BSBR_BR14_MSK + +#define GPIO_BSBR_BR13_POS 29U +#define GPIO_BSBR_BR13_MSK BIT(GPIO_BSBR_BR13_POS) +#define GPIO_BSBR_BR13 GPIO_BSBR_BR13_MSK + +#define GPIO_BSBR_BR12_POS 28U +#define GPIO_BSBR_BR12_MSK BIT(GPIO_BSBR_BR12_POS) +#define GPIO_BSBR_BR12 GPIO_BSBR_BR12_MSK + +#define GPIO_BSBR_BR11_POS 27U +#define GPIO_BSBR_BR11_MSK BIT(GPIO_BSBR_BR11_POS) +#define GPIO_BSBR_BR11 GPIO_BSBR_BR11_MSK + +#define GPIO_BSBR_BR10_POS 26U +#define GPIO_BSBR_BR10_MSK BIT(GPIO_BSBR_BR10_POS) +#define GPIO_BSBR_BR10 GPIO_BSBR_BR10_MSK + +#define GPIO_BSBR_BR9_POS 25U +#define GPIO_BSBR_BR9_MSK BIT(GPIO_BSBR_BR9_POS) +#define GPIO_BSBR_BR9 GPIO_BSBR_BR9_MSK + +#define GPIO_BSBR_BR8_POS 24U +#define GPIO_BSBR_BR8_MSK BIT(GPIO_BSBR_BR8_POS) +#define GPIO_BSBR_BR8 GPIO_BSBR_BR8_MSK + +#define GPIO_BSBR_BR7_POS 23U +#define GPIO_BSBR_BR7_MSK BIT(GPIO_BSBR_BR7_POS) +#define GPIO_BSBR_BR7 GPIO_BSBR_BR7_MSK + +#define GPIO_BSBR_BR6_POS 22U +#define GPIO_BSBR_BR6_MSK BIT(GPIO_BSBR_BR6_POS) +#define GPIO_BSBR_BR6 GPIO_BSBR_BR6_MSK + +#define GPIO_BSBR_BR5_POS 21U +#define GPIO_BSBR_BR5_MSK BIT(GPIO_BSBR_BR5_POS) +#define GPIO_BSBR_BR5 GPIO_BSBR_BR5_MSK + +#define GPIO_BSBR_BR4_POS 20U +#define GPIO_BSBR_BR4_MSK BIT(GPIO_BSBR_BR4_POS) +#define GPIO_BSBR_BR4 GPIO_BSBR_BR4_MSK + +#define GPIO_BSBR_BR3_POS 19U +#define GPIO_BSBR_BR3_MSK BIT(GPIO_BSBR_BR3_POS) +#define GPIO_BSBR_BR3 GPIO_BSBR_BR3_MSK + +#define GPIO_BSBR_BR2_POS 18U +#define GPIO_BSBR_BR2_MSK BIT(GPIO_BSBR_BR2_POS) +#define GPIO_BSBR_BR2 GPIO_BSBR_BR2_MSK + +#define GPIO_BSBR_BR1_POS 17U +#define GPIO_BSBR_BR1_MSK BIT(GPIO_BSBR_BR1_POS) +#define GPIO_BSBR_BR1 GPIO_BSBR_BR1_MSK + +#define GPIO_BSBR_BR0_POS 16U +#define GPIO_BSBR_BR0_MSK BIT(GPIO_BSBR_BR0_POS) +#define GPIO_BSBR_BR0 GPIO_BSBR_BR0_MSK + +#define GPIO_BSBR_BS15_POS 15U +#define GPIO_BSBR_BS15_MSK BIT(GPIO_BSBR_BS15_POS) +#define GPIO_BSBR_BS15 GPIO_BSBR_BS15_MSK + +#define GPIO_BSBR_BS14_POS 14U +#define GPIO_BSBR_BS14_MSK BIT(GPIO_BSBR_BS14_POS) +#define GPIO_BSBR_BS14 GPIO_BSBR_BS14_MSK + +#define GPIO_BSBR_BS13_POS 13U +#define GPIO_BSBR_BS13_MSK BIT(GPIO_BSBR_BS13_POS) +#define GPIO_BSBR_BS13 GPIO_BSBR_BS13_MSK + +#define GPIO_BSBR_BS12_POS 12U +#define GPIO_BSBR_BS12_MSK BIT(GPIO_BSBR_BS12_POS) +#define GPIO_BSBR_BS12 GPIO_BSBR_BS12_MSK + +#define GPIO_BSBR_BS11_POS 11U +#define GPIO_BSBR_BS11_MSK BIT(GPIO_BSBR_BS11_POS) +#define GPIO_BSBR_BS11 GPIO_BSBR_BS11_MSK + +#define GPIO_BSBR_BS10_POS 10U +#define GPIO_BSBR_BS10_MSK BIT(GPIO_BSBR_BS10_POS) +#define GPIO_BSBR_BS10 GPIO_BSBR_BS10_MSK + +#define GPIO_BSBR_BS9_POS 9U +#define GPIO_BSBR_BS9_MSK BIT(GPIO_BSBR_BS9_POS) +#define GPIO_BSBR_BS9 GPIO_BSBR_BS9_MSK + +#define GPIO_BSBR_BS8_POS 8U +#define GPIO_BSBR_BS8_MSK BIT(GPIO_BSBR_BS8_POS) +#define GPIO_BSBR_BS8 GPIO_BSBR_BS8_MSK + +#define GPIO_BSBR_BS7_POS 7U +#define GPIO_BSBR_BS7_MSK BIT(GPIO_BSBR_BS7_POS) +#define GPIO_BSBR_BS7 GPIO_BSBR_BS7_MSK + +#define GPIO_BSBR_BS6_POS 6U +#define GPIO_BSBR_BS6_MSK BIT(GPIO_BSBR_BS6_POS) +#define GPIO_BSBR_BS6 GPIO_BSBR_BS6_MSK + +#define GPIO_BSBR_BS5_POS 5U +#define GPIO_BSBR_BS5_MSK BIT(GPIO_BSBR_BS5_POS) +#define GPIO_BSBR_BS5 GPIO_BSBR_BS5_MSK + +#define GPIO_BSBR_BS4_POS 4U +#define GPIO_BSBR_BS4_MSK BIT(GPIO_BSBR_BS4_POS) +#define GPIO_BSBR_BS4 GPIO_BSBR_BS4_MSK + +#define GPIO_BSBR_BS3_POS 3U +#define GPIO_BSBR_BS3_MSK BIT(GPIO_BSBR_BS3_POS) +#define GPIO_BSBR_BS3 GPIO_BSBR_BS3_MSK + +#define GPIO_BSBR_BS2_POS 2U +#define GPIO_BSBR_BS2_MSK BIT(GPIO_BSBR_BS2_POS) +#define GPIO_BSBR_BS2 GPIO_BSBR_BS2_MSK + +#define GPIO_BSBR_BS1_POS 1U +#define GPIO_BSBR_BS1_MSK BIT(GPIO_BSBR_BS1_POS) +#define GPIO_BSBR_BS1 GPIO_BSBR_BS1_MSK + +#define GPIO_BSBR_BS0_POS 0U +#define GPIO_BSBR_BS0_MSK BIT(GPIO_BSBR_BS0_POS) +#define GPIO_BSBR_BS0 GPIO_BSBR_BS0_MSK + +/****************** Bit definition for GPIO_LCK register ************************/ + +#define GPIO_LCK_LCKK_POSS 16U +#define GPIO_LCK_LCKK_POSE 31U +#define GPIO_LCK_LCKK_MSK BITS(GPIO_LCK_LCKK_POSS, GPIO_LCK_LCKK_POSE) +#define GPIO_LCK_LCKK GPIO_LCK_LCKK_MSK + +#define GPIO_LCK_LCK15_POS 15U +#define GPIO_LCK_LCK15_MSK BIT(GPIO_LCK_LCK15_POS) +#define GPIO_LCK_LCK15 GPIO_LCK_LCK15_MSK + +#define GPIO_LCK_LCK14_POS 14U +#define GPIO_LCK_LCK14_MSK BIT(GPIO_LCK_LCK14_POS) +#define GPIO_LCK_LCK14 GPIO_LCK_LCK14_MSK + +#define GPIO_LCK_LCK13_POS 13U +#define GPIO_LCK_LCK13_MSK BIT(GPIO_LCK_LCK13_POS) +#define GPIO_LCK_LCK13 GPIO_LCK_LCK13_MSK + +#define GPIO_LCK_LCK12_POS 12U +#define GPIO_LCK_LCK12_MSK BIT(GPIO_LCK_LCK12_POS) +#define GPIO_LCK_LCK12 GPIO_LCK_LCK12_MSK + +#define GPIO_LCK_LCK11_POS 11U +#define GPIO_LCK_LCK11_MSK BIT(GPIO_LCK_LCK11_POS) +#define GPIO_LCK_LCK11 GPIO_LCK_LCK11_MSK + +#define GPIO_LCK_LCK10_POS 10U +#define GPIO_LCK_LCK10_MSK BIT(GPIO_LCK_LCK10_POS) +#define GPIO_LCK_LCK10 GPIO_LCK_LCK10_MSK + +#define GPIO_LCK_LCK9_POS 9U +#define GPIO_LCK_LCK9_MSK BIT(GPIO_LCK_LCK9_POS) +#define GPIO_LCK_LCK9 GPIO_LCK_LCK9_MSK + +#define GPIO_LCK_LCK8_POS 8U +#define GPIO_LCK_LCK8_MSK BIT(GPIO_LCK_LCK8_POS) +#define GPIO_LCK_LCK8 GPIO_LCK_LCK8_MSK + +#define GPIO_LCK_LCK7_POS 7U +#define GPIO_LCK_LCK7_MSK BIT(GPIO_LCK_LCK7_POS) +#define GPIO_LCK_LCK7 GPIO_LCK_LCK7_MSK + +#define GPIO_LCK_LCK6_POS 6U +#define GPIO_LCK_LCK6_MSK BIT(GPIO_LCK_LCK6_POS) +#define GPIO_LCK_LCK6 GPIO_LCK_LCK6_MSK + +#define GPIO_LCK_LCK5_POS 5U +#define GPIO_LCK_LCK5_MSK BIT(GPIO_LCK_LCK5_POS) +#define GPIO_LCK_LCK5 GPIO_LCK_LCK5_MSK + +#define GPIO_LCK_LCK4_POS 4U +#define GPIO_LCK_LCK4_MSK BIT(GPIO_LCK_LCK4_POS) +#define GPIO_LCK_LCK4 GPIO_LCK_LCK4_MSK + +#define GPIO_LCK_LCK3_POS 3U +#define GPIO_LCK_LCK3_MSK BIT(GPIO_LCK_LCK3_POS) +#define GPIO_LCK_LCK3 GPIO_LCK_LCK3_MSK + +#define GPIO_LCK_LCK2_POS 2U +#define GPIO_LCK_LCK2_MSK BIT(GPIO_LCK_LCK2_POS) +#define GPIO_LCK_LCK2 GPIO_LCK_LCK2_MSK + +#define GPIO_LCK_LCK1_POS 1U +#define GPIO_LCK_LCK1_MSK BIT(GPIO_LCK_LCK1_POS) +#define GPIO_LCK_LCK1 GPIO_LCK_LCK1_MSK + +#define GPIO_LCK_LCK0_POS 0U +#define GPIO_LCK_LCK0_MSK BIT(GPIO_LCK_LCK0_POS) +#define GPIO_LCK_LCK0 GPIO_LCK_LCK0_MSK + +/****************** Bit definition for GPIO_MOD register ************************/ + +#define GPIO_MOD_MOD15_POSS 30U +#define GPIO_MOD_MOD15_POSE 31U +#define GPIO_MOD_MOD15_MSK BITS(GPIO_MOD_MOD15_POSS,GPIO_MOD_MOD15_POSE) +#define GPIO_MOD_MOD15 GPIO_MOD_MOD15_MSK + +#define GPIO_MOD_MOD14_POSS 28U +#define GPIO_MOD_MOD14_POSE 29U +#define GPIO_MOD_MOD14_MSK BITS(GPIO_MOD_MOD14_POSS,GPIO_MOD_MOD14_POSE) +#define GPIO_MOD_MOD14 GPIO_MOD_MOD14_MSK + +#define GPIO_MOD_MOD13_POSS 26U +#define GPIO_MOD_MOD13_POSE 27U +#define GPIO_MOD_MOD13_MSK BITS(GPIO_MOD_MOD13_POSS,GPIO_MOD_MOD13_POSE) +#define GPIO_MOD_MOD13 GPIO_MOD_MOD13_MSK + +#define GPIO_MOD_MOD12_POSS 24U +#define GPIO_MOD_MOD12_POSE 25U +#define GPIO_MOD_MOD12_MSK BITS(GPIO_MOD_MOD12_POSS,GPIO_MOD_MOD12_POSE) +#define GPIO_MOD_MOD12 GPIO_MOD_MOD12_MSK + +#define GPIO_MOD_MOD11_POSS 22U +#define GPIO_MOD_MOD11_POSE 23U +#define GPIO_MOD_MOD11_MSK BITS(GPIO_MOD_MOD11_POSS,GPIO_MOD_MOD11_POSE) +#define GPIO_MOD_MOD11 GPIO_MOD_MOD11_MSK + +#define GPIO_MOD_MOD10_POSS 20U +#define GPIO_MOD_MOD10_POSE 21U +#define GPIO_MOD_MOD10_MSK BITS(GPIO_MOD_MOD10_POSS,GPIO_MOD_MOD10_POSE) +#define GPIO_MOD_MOD10 GPIO_MOD_MOD10_MSK + +#define GPIO_MOD_MOD9_POSS 18U +#define GPIO_MOD_MOD9_POSE 19U +#define GPIO_MOD_MOD9_MSK BITS(GPIO_MOD_MOD9_POSS,GPIO_MOD_MOD9_POSE) +#define GPIO_MOD_MOD9 GPIO_MOD_MOD9_MSK + +#define GPIO_MOD_MOD8_POSS 16U +#define GPIO_MOD_MOD8_POSE 17U +#define GPIO_MOD_MOD8_MSK BITS(GPIO_MOD_MOD8_POSS,GPIO_MOD_MOD8_POSE) +#define GPIO_MOD_MOD8 GPIO_MOD_MOD8_MSK + +#define GPIO_MOD_MOD7_POSS 14U +#define GPIO_MOD_MOD7_POSE 15U +#define GPIO_MOD_MOD7_MSK BITS(GPIO_MOD_MOD7_POSS,GPIO_MOD_MOD7_POSE) +#define GPIO_MOD_MOD7 GPIO_MOD_MOD7_MSK + +#define GPIO_MOD_MOD6_POSS 12U +#define GPIO_MOD_MOD6_POSE 13U +#define GPIO_MOD_MOD6_MSK BITS(GPIO_MOD_MOD6_POSS,GPIO_MOD_MOD6_POSE) +#define GPIO_MOD_MOD6 GPIO_MOD_MOD6_MSK + +#define GPIO_MOD_MOD5_POSS 10U +#define GPIO_MOD_MOD5_POSE 11U +#define GPIO_MOD_MOD5_MSK BITS(GPIO_MOD_MOD5_POSS,GPIO_MOD_MOD5_POSE) +#define GPIO_MOD_MOD5 GPIO_MOD_MOD5_MSK + +#define GPIO_MOD_MOD4_POSS 8U +#define GPIO_MOD_MOD4_POSE 9U +#define GPIO_MOD_MOD4_MSK BITS(GPIO_MOD_MOD4_POSS,GPIO_MOD_MOD4_POSE) +#define GPIO_MOD_MOD4 GPIO_MOD_MOD4_MSK + +#define GPIO_MOD_MOD3_POSS 6U +#define GPIO_MOD_MOD3_POSE 7U +#define GPIO_MOD_MOD3_MSK BITS(GPIO_MOD_MOD3_POSS,GPIO_MOD_MOD3_POSE) +#define GPIO_MOD_MOD3 GPIO_MOD_MOD3_MSK + +#define GPIO_MOD_MOD2_POSS 4U +#define GPIO_MOD_MOD2_POSE 5U +#define GPIO_MOD_MOD2_MSK BITS(GPIO_MOD_MOD2_POSS,GPIO_MOD_MOD2_POSE) +#define GPIO_MOD_MOD2 GPIO_MOD_MOD2_MSK + +#define GPIO_MOD_MOD1_POSS 2U +#define GPIO_MOD_MOD1_POSE 3U +#define GPIO_MOD_MOD1_MSK BITS(GPIO_MOD_MOD1_POSS,GPIO_MOD_MOD1_POSE) +#define GPIO_MOD_MOD1 GPIO_MOD_MOD1_MSK + +#define GPIO_MOD_MOD0_POSS 0U +#define GPIO_MOD_MOD0_POSE 1U +#define GPIO_MOD_MOD0_MSK BITS(GPIO_MOD_MOD0_POSS,GPIO_MOD_MOD0_POSE) +#define GPIO_MOD_MOD0 GPIO_MOD_MOD0_MSK + +/****************** Bit definition for GPIO_PUD register ************************/ + +#define GPIO_PUD_PUD15_POSS 30U +#define GPIO_PUD_PUD15_POSE 31U +#define GPIO_PUD_PUD15_MSK BITS(GPIO_PUD_PUD15_POSS,GPIO_PUD_PUD15_POSE) +#define GPIO_PUD_PUD15 GPIO_PUD_PUD15_MSK + +#define GPIO_PUD_PUD14_POSS 28U +#define GPIO_PUD_PUD14_POSE 29U +#define GPIO_PUD_PUD14_MSK BITS(GPIO_PUD_PUD14_POSS,GPIO_PUD_PUD14_POSE) +#define GPIO_PUD_PUD14 GPIO_PUD_PUD14_MSK + +#define GPIO_PUD_PUD13_POSS 26U +#define GPIO_PUD_PUD13_POSE 27U +#define GPIO_PUD_PUD13_MSK BITS(GPIO_PUD_PUD13_POSS,GPIO_PUD_PUD13_POSE) +#define GPIO_PUD_PUD13 GPIO_PUD_PUD13_MSK + +#define GPIO_PUD_PUD12_POSS 24U +#define GPIO_PUD_PUD12_POSE 25U +#define GPIO_PUD_PUD12_MSK BITS(GPIO_PUD_PUD12_POSS,GPIO_PUD_PUD12_POSE) +#define GPIO_PUD_PUD12 GPIO_PUD_PUD12_MSK + +#define GPIO_PUD_PUD11_POSS 22U +#define GPIO_PUD_PUD11_POSE 23U +#define GPIO_PUD_PUD11_MSK BITS(GPIO_PUD_PUD11_POSS,GPIO_PUD_PUD11_POSE) +#define GPIO_PUD_PUD11 GPIO_PUD_PUD11_MSK + +#define GPIO_PUD_PUD10_POSS 20U +#define GPIO_PUD_PUD10_POSE 21U +#define GPIO_PUD_PUD10_MSK BITS(GPIO_PUD_PUD10_POSS,GPIO_PUD_PUD10_POSE) +#define GPIO_PUD_PUD10 GPIO_PUD_PUD10_MSK + +#define GPIO_PUD_PUD9_POSS 18U +#define GPIO_PUD_PUD9_POSE 19U +#define GPIO_PUD_PUD9_MSK BITS(GPIO_PUD_PUD9_POSS,GPIO_PUD_PUD9_POSE) +#define GPIO_PUD_PUD9 GPIO_PUD_PUD9_MSK + +#define GPIO_PUD_PUD8_POSS 16U +#define GPIO_PUD_PUD8_POSE 17U +#define GPIO_PUD_PUD8_MSK BITS(GPIO_PUD_PUD8_POSS,GPIO_PUD_PUD8_POSE) +#define GPIO_PUD_PUD8 GPIO_PUD_PUD8_MSK + +#define GPIO_PUD_PUD7_POSS 14U +#define GPIO_PUD_PUD7_POSE 15U +#define GPIO_PUD_PUD7_MSK BITS(GPIO_PUD_PUD7_POSS,GPIO_PUD_PUD7_POSE) +#define GPIO_PUD_PUD7 GPIO_PUD_PUD7_MSK + +#define GPIO_PUD_PUD6_POSS 12U +#define GPIO_PUD_PUD6_POSE 13U +#define GPIO_PUD_PUD6_MSK BITS(GPIO_PUD_PUD6_POSS,GPIO_PUD_PUD6_POSE) +#define GPIO_PUD_PUD6 GPIO_PUD_PUD6_MSK + +#define GPIO_PUD_PUD5_POSS 10U +#define GPIO_PUD_PUD5_POSE 11U +#define GPIO_PUD_PUD5_MSK BITS(GPIO_PUD_PUD5_POSS,GPIO_PUD_PUD5_POSE) +#define GPIO_PUD_PUD5 GPIO_PUD_PUD5_MSK + +#define GPIO_PUD_PUD4_POSS 8U +#define GPIO_PUD_PUD4_POSE 9U +#define GPIO_PUD_PUD4_MSK BITS(GPIO_PUD_PUD4_POSS,GPIO_PUD_PUD4_POSE) +#define GPIO_PUD_PUD4 GPIO_PUD_PUD4_MSK + +#define GPIO_PUD_PUD3_POSS 6U +#define GPIO_PUD_PUD3_POSE 7U +#define GPIO_PUD_PUD3_MSK BITS(GPIO_PUD_PUD3_POSS,GPIO_PUD_PUD3_POSE) +#define GPIO_PUD_PUD3 GPIO_PUD_PUD3_MSK + +#define GPIO_PUD_PUD2_POSS 4U +#define GPIO_PUD_PUD2_POSE 5U +#define GPIO_PUD_PUD2_MSK BITS(GPIO_PUD_PUD2_POSS,GPIO_PUD_PUD2_POSE) +#define GPIO_PUD_PUD2 GPIO_PUD_PUD2_MSK + +#define GPIO_PUD_PUD1_POSS 2U +#define GPIO_PUD_PUD1_POSE 3U +#define GPIO_PUD_PUD1_MSK BITS(GPIO_PUD_PUD1_POSS,GPIO_PUD_PUD1_POSE) +#define GPIO_PUD_PUD1 GPIO_PUD_PUD1_MSK + +#define GPIO_PUD_PUD0_POSS 0U +#define GPIO_PUD_PUD0_POSE 1U +#define GPIO_PUD_PUD0_MSK BITS(GPIO_PUD_PUD0_POSS,GPIO_PUD_PUD0_POSE) +#define GPIO_PUD_PUD0 GPIO_PUD_PUD0_MSK + +/****************** Bit definition for GPIO_OT register ************************/ + +#define GPIO_OT_OT15_POS 15U +#define GPIO_OT_OT15_MSK BIT(GPIO_OT_OT15_POS) +#define GPIO_OT_OT15 GPIO_OT_OT15_MSK + +#define GPIO_OT_OT14_POS 14U +#define GPIO_OT_OT14_MSK BIT(GPIO_OT_OT14_POS) +#define GPIO_OT_OT14 GPIO_OT_OT14_MSK + +#define GPIO_OT_OT13_POS 13U +#define GPIO_OT_OT13_MSK BIT(GPIO_OT_OT13_POS) +#define GPIO_OT_OT13 GPIO_OT_OT13_MSK + +#define GPIO_OT_OT12_POS 12U +#define GPIO_OT_OT12_MSK BIT(GPIO_OT_OT12_POS) +#define GPIO_OT_OT12 GPIO_OT_OT12_MSK + +#define GPIO_OT_OT11_POS 11U +#define GPIO_OT_OT11_MSK BIT(GPIO_OT_OT11_POS) +#define GPIO_OT_OT11 GPIO_OT_OT11_MSK + +#define GPIO_OT_OT10_POS 10U +#define GPIO_OT_OT10_MSK BIT(GPIO_OT_OT10_POS) +#define GPIO_OT_OT10 GPIO_OT_OT10_MSK + +#define GPIO_OT_OT9_POS 9U +#define GPIO_OT_OT9_MSK BIT(GPIO_OT_OT9_POS) +#define GPIO_OT_OT9 GPIO_OT_OT9_MSK + +#define GPIO_OT_OT8_POS 8U +#define GPIO_OT_OT8_MSK BIT(GPIO_OT_OT8_POS) +#define GPIO_OT_OT8 GPIO_OT_OT8_MSK + +#define GPIO_OT_OT7_POS 7U +#define GPIO_OT_OT7_MSK BIT(GPIO_OT_OT7_POS) +#define GPIO_OT_OT7 GPIO_OT_OT7_MSK + +#define GPIO_OT_OT6_POS 6U +#define GPIO_OT_OT6_MSK BIT(GPIO_OT_OT6_POS) +#define GPIO_OT_OT6 GPIO_OT_OT6_MSK + +#define GPIO_OT_OT5_POS 5U +#define GPIO_OT_OT5_MSK BIT(GPIO_OT_OT5_POS) +#define GPIO_OT_OT5 GPIO_OT_OT5_MSK + +#define GPIO_OT_OT4_POS 4U +#define GPIO_OT_OT4_MSK BIT(GPIO_OT_OT4_POS) +#define GPIO_OT_OT4 GPIO_OT_OT4_MSK + +#define GPIO_OT_OT3_POS 3U +#define GPIO_OT_OT3_MSK BIT(GPIO_OT_OT3_POS) +#define GPIO_OT_OT3 GPIO_OT_OT3_MSK + +#define GPIO_OT_OT2_POS 2U +#define GPIO_OT_OT2_MSK BIT(GPIO_OT_OT2_POS) +#define GPIO_OT_OT2 GPIO_OT_OT2_MSK + +#define GPIO_OT_OT1_POS 1U +#define GPIO_OT_OT1_MSK BIT(GPIO_OT_OT1_POS) +#define GPIO_OT_OT1 GPIO_OT_OT1_MSK + +#define GPIO_OT_OT0_POS 0U +#define GPIO_OT_OT0_MSK BIT(GPIO_OT_OT0_POS) +#define GPIO_OT_OT0 GPIO_OT_OT0_MSK + +//#define GPIO_OT_OT_POSS 0U +//#define GPIO_OT_OT_POSE 15U +//#define GPIO_OT_OT_MSK BITS(GPIO_OT_OT_POSS,GPIO_OT_OT_POSE) +//#define GPIO_OT_OT GPIO_OT_OT_MSK + +/****************** Bit definition for GPIO_DS register ************************/ + +#define GPIO_DS_DS15_POS 15U +#define GPIO_DS_DS15_MSK BIT(GPIO_DS_DS15_POS) +#define GPIO_DS_DS15 GPIO_DS_DS15_MSK + +#define GPIO_DS_DS14_POS 14U +#define GPIO_DS_DS14_MSK BIT(GPIO_DS_DS14_POS) +#define GPIO_DS_DS14 GPIO_DS_DS14_MSK + +#define GPIO_DS_DS13_POS 13U +#define GPIO_DS_DS13_MSK BIT(GPIO_DS_DS13_POS) +#define GPIO_DS_DS13 GPIO_DS_DS13_MSK + +#define GPIO_DS_DS12_POS 12U +#define GPIO_DS_DS12_MSK BIT(GPIO_DS_DS12_POS) +#define GPIO_DS_DS12 GPIO_DS_DS12_MSK + +#define GPIO_DS_DS11_POS 11U +#define GPIO_DS_DS11_MSK BIT(GPIO_DS_DS11_POS) +#define GPIO_DS_DS11 GPIO_DS_DS11_MSK + +#define GPIO_DS_DS10_POS 10U +#define GPIO_DS_DS10_MSK BIT(GPIO_DS_DS10_POS) +#define GPIO_DS_DS10 GPIO_DS_DS10_MSK + +#define GPIO_DS_DS9_POS 9U +#define GPIO_DS_DS9_MSK BIT(GPIO_DS_DS9_POS) +#define GPIO_DS_DS9 GPIO_DS_DS9_MSK + +#define GPIO_DS_DS8_POS 8U +#define GPIO_DS_DS8_MSK BIT(GPIO_DS_DS8_POS) +#define GPIO_DS_DS8 GPIO_DS_DS8_MSK + +#define GPIO_DS_DS7_POS 7U +#define GPIO_DS_DS7_MSK BIT(GPIO_DS_DS7_POS) +#define GPIO_DS_DS7 GPIO_DS_DS7_MSK + +#define GPIO_DS_DS6_POS 6U +#define GPIO_DS_DS6_MSK BIT(GPIO_DS_DS6_POS) +#define GPIO_DS_DS6 GPIO_DS_DS6_MSK + +#define GPIO_DS_DS5_POS 5U +#define GPIO_DS_DS5_MSK BIT(GPIO_DS_DS5_POS) +#define GPIO_DS_DS5 GPIO_DS_DS5_MSK + +#define GPIO_DS_DS4_POS 4U +#define GPIO_DS_DS4_MSK BIT(GPIO_DS_DS4_POS) +#define GPIO_DS_DS4 GPIO_DS_DS4_MSK + +#define GPIO_DS_DS3_POS 3U +#define GPIO_DS_DS3_MSK BIT(GPIO_DS_DS3_POS) +#define GPIO_DS_DS3 GPIO_DS_DS3_MSK + +#define GPIO_DS_DS2_POS 2U +#define GPIO_DS_DS2_MSK BIT(GPIO_DS_DS2_POS) +#define GPIO_DS_DS2 GPIO_DS_DS2_MSK + +#define GPIO_DS_DS1_POS 1U +#define GPIO_DS_DS1_MSK BIT(GPIO_DS_DS1_POS) +#define GPIO_DS_DS1 GPIO_DS_DS1_MSK + +#define GPIO_DS_DS0_POS 0U +#define GPIO_DS_DS0_MSK BIT(GPIO_DS_DS0_POS) +#define GPIO_DS_DS0 GPIO_DS_DS0_MSK + +//#define GPIO_DS_DS_POSS 0U +//#define GPIO_DS_DS_POSE 15U +//#define GPIO_DS_DS_MSK BITS(GPIO_DS_DS_POSS,GPIO_DS_DS_POSE) +//#define GPIO_DS_DS GPIO_DS_DS_MSK + +/****************** Bit definition for GPIO_FIR register ************************/ + +#define GPIO_FIR_FIR15_POS 15U +#define GPIO_FIR_FIR15_MSK BIT(GPIO_FIR_FIR15_POS) +#define GPIO_FIR_FIR15 GPIO_FIR_FIR15_MSK + +#define GPIO_FIR_FIR14_POS 14U +#define GPIO_FIR_FIR14_MSK BIT(GPIO_FIR_FIR14_POS) +#define GPIO_FIR_FIR14 GPIO_FIR_FIR14_MSK + +#define GPIO_FIR_FIR13_POS 13U +#define GPIO_FIR_FIR13_MSK BIT(GPIO_FIR_FIR13_POS) +#define GPIO_FIR_FIR13 GPIO_FIR_FIR13_MSK + +#define GPIO_FIR_FIR12_POS 12U +#define GPIO_FIR_FIR12_MSK BIT(GPIO_FIR_FIR12_POS) +#define GPIO_FIR_FIR12 GPIO_FIR_FIR12_MSK + +#define GPIO_FIR_FIR11_POS 11U +#define GPIO_FIR_FIR11_MSK BIT(GPIO_FIR_FIR11_POS) +#define GPIO_FIR_FIR11 GPIO_FIR_FIR11_MSK + +#define GPIO_FIR_FIR10_POS 10U +#define GPIO_FIR_FIR10_MSK BIT(GPIO_FIR_FIR10_POS) +#define GPIO_FIR_FIR10 GPIO_FIR_FIR10_MSK + +#define GPIO_FIR_FIR9_POS 9U +#define GPIO_FIR_FIR9_MSK BIT(GPIO_FIR_FIR9_POS) +#define GPIO_FIR_FIR9 GPIO_FIR_FIR9_MSK + +#define GPIO_FIR_FIR8_POS 8U +#define GPIO_FIR_FIR8_MSK BIT(GPIO_FIR_FIR8_POS) +#define GPIO_FIR_FIR8 GPIO_FIR_FIR8_MSK + +#define GPIO_FIR_FIR7_POS 7U +#define GPIO_FIR_FIR7_MSK BIT(GPIO_FIR_FIR7_POS) +#define GPIO_FIR_FIR7 GPIO_FIR_FIR7_MSK + +#define GPIO_FIR_FIR6_POS 6U +#define GPIO_FIR_FIR6_MSK BIT(GPIO_FIR_FIR6_POS) +#define GPIO_FIR_FIR6 GPIO_FIR_FIR6_MSK + +#define GPIO_FIR_FIR5_POS 5U +#define GPIO_FIR_FIR5_MSK BIT(GPIO_FIR_FIR5_POS) +#define GPIO_FIR_FIR5 GPIO_FIR_FIR5_MSK + +#define GPIO_FIR_FIR4_POS 4U +#define GPIO_FIR_FIR4_MSK BIT(GPIO_FIR_FIR4_POS) +#define GPIO_FIR_FIR4 GPIO_FIR_FIR4_MSK + +#define GPIO_FIR_FIR3_POS 3U +#define GPIO_FIR_FIR3_MSK BIT(GPIO_FIR_FIR3_POS) +#define GPIO_FIR_FIR3 GPIO_FIR_FIR3_MSK + +#define GPIO_FIR_FIR2_POS 2U +#define GPIO_FIR_FIR2_MSK BIT(GPIO_FIR_FIR2_POS) +#define GPIO_FIR_FIR2 GPIO_FIR_FIR2_MSK + +#define GPIO_FIR_FIR1_POS 1U +#define GPIO_FIR_FIR1_MSK BIT(GPIO_FIR_FIR1_POS) +#define GPIO_FIR_FIR1 GPIO_FIR_FIR1_MSK + +#define GPIO_FIR_FIR0_POS 0U +#define GPIO_FIR_FIR0_MSK BIT(GPIO_FIR_FIR0_POS) +#define GPIO_FIR_FIR0 GPIO_FIR_FIR0_MSK + +//#define GPIO_FIR_FIR_POSS 0U +//#define GPIO_FIR_FIR_POSE 15U +//#define GPIO_FIR_FIR_MSK BITS(GPIO_FIR_FIR_POSS,GPIO_FIR_FIR_POSE) +//#define GPIO_FIR_FIR GPIO_FIR_FIR_MSK + +/****************** Bit definition for GPIO_IST register ************************/ + +#define GPIO_IST_IST15_POS 15U +#define GPIO_IST_IST15_MSK BIT(GPIO_IST_IST15_POS) +#define GPIO_IST_IST15 GPIO_IST_IST15_MSK + +#define GPIO_IST_IST14_POS 14U +#define GPIO_IST_IST14_MSK BIT(GPIO_IST_IST14_POS) +#define GPIO_IST_IST14 GPIO_IST_IST14_MSK + +#define GPIO_IST_IST13_POS 13U +#define GPIO_IST_IST13_MSK BIT(GPIO_IST_IST13_POS) +#define GPIO_IST_IST13 GPIO_IST_IST13_MSK + +#define GPIO_IST_IST12_POS 12U +#define GPIO_IST_IST12_MSK BIT(GPIO_IST_IST12_POS) +#define GPIO_IST_IST12 GPIO_IST_IST12_MSK + +#define GPIO_IST_IST11_POS 11U +#define GPIO_IST_IST11_MSK BIT(GPIO_IST_IST11_POS) +#define GPIO_IST_IST11 GPIO_IST_IST11_MSK + +#define GPIO_IST_IST10_POS 10U +#define GPIO_IST_IST10_MSK BIT(GPIO_IST_IST10_POS) +#define GPIO_IST_IST10 GPIO_IST_IST10_MSK + +#define GPIO_IST_IST9_POS 9U +#define GPIO_IST_IST9_MSK BIT(GPIO_IST_IST9_POS) +#define GPIO_IST_IST9 GPIO_IST_IST9_MSK + +#define GPIO_IST_IST8_POS 8U +#define GPIO_IST_IST8_MSK BIT(GPIO_IST_IST8_POS) +#define GPIO_IST_IST8 GPIO_IST_IST8_MSK + +#define GPIO_IST_IST7_POS 7U +#define GPIO_IST_IST7_MSK BIT(GPIO_IST_IST7_POS) +#define GPIO_IST_IST7 GPIO_IST_IST7_MSK + +#define GPIO_IST_IST6_POS 6U +#define GPIO_IST_IST6_MSK BIT(GPIO_IST_IST6_POS) +#define GPIO_IST_IST6 GPIO_IST_IST6_MSK + +#define GPIO_IST_IST5_POS 5U +#define GPIO_IST_IST5_MSK BIT(GPIO_IST_IST5_POS) +#define GPIO_IST_IST5 GPIO_IST_IST5_MSK + +#define GPIO_IST_IST4_POS 4U +#define GPIO_IST_IST4_MSK BIT(GPIO_IST_IST4_POS) +#define GPIO_IST_IST4 GPIO_IST_IST4_MSK + +#define GPIO_IST_IST3_POS 3U +#define GPIO_IST_IST3_MSK BIT(GPIO_IST_IST3_POS) +#define GPIO_IST_IST3 GPIO_IST_IST3_MSK + +#define GPIO_IST_IST2_POS 2U +#define GPIO_IST_IST2_MSK BIT(GPIO_IST_IST2_POS) +#define GPIO_IST_IST2 GPIO_IST_IST2_MSK + +#define GPIO_IST_IST1_POS 1U +#define GPIO_IST_IST1_MSK BIT(GPIO_IST_IST1_POS) +#define GPIO_IST_IST1 GPIO_IST_IST1_MSK + +#define GPIO_IST_IST0_POS 0U +#define GPIO_IST_IST0_MSK BIT(GPIO_IST_IST0_POS) +#define GPIO_IST_IST0 GPIO_IST_IST0_MSK + +//#define GPIO_IST_IST_POSS 0U +//#define GPIO_IST_IST_POSE 15U +//#define GPIO_IST_IST_MSK BITS(GPIO_IST_IST_POSS, GPIO_IST_IST_POSE) +//#define GPIO_IST_IST GPIO_IST_IST_MSK + +/****************** Bit definition for GPIO_AFL register ************************/ + +#define GPIO_AFL_AF7_POSS 28U +#define GPIO_AFL_AF7_POSE 31U +#define GPIO_AFL_AF7_MSK BITS(GPIO_AFL_AF7_POSS,GPIO_AFL_AF7_POSE) +#define GPIO_AFL_AF7 GPIO_AFL_AF7_MSK + +#define GPIO_AFL_AF6_POSS 24U +#define GPIO_AFL_AF6_POSE 27U +#define GPIO_AFL_AF6_MSK BITS(GPIO_AFL_AF6_POSS,GPIO_AFL_AF6_POSE) +#define GPIO_AFL_AF6 GPIO_AFL_AF6_MSK + +#define GPIO_AFL_AF5_POSS 20U +#define GPIO_AFL_AF5_POSE 23U +#define GPIO_AFL_AF5_MSK BITS(GPIO_AFL_AF5_POSS,GPIO_AFL_AF5_POSE) +#define GPIO_AFL_AF5 GPIO_AFL_AF5_MSK + +#define GPIO_AFL_AF4_POSS 16U +#define GPIO_AFL_AF4_POSE 19U +#define GPIO_AFL_AF4_MSK BITS(GPIO_AFL_AF4_POSS,GPIO_AFL_AF4_POSE) +#define GPIO_AFL_AF4 GPIO_AFL_AF4_MSK + +#define GPIO_AFL_AF3_POSS 12U +#define GPIO_AFL_AF3_POSE 15U +#define GPIO_AFL_AF3_MSK BITS(GPIO_AFL_AF3_POSS,GPIO_AFL_AF3_POSE) +#define GPIO_AFL_AF3 GPIO_AFL_AF3_MSK + +#define GPIO_AFL_AF2_POSS 8U +#define GPIO_AFL_AF2_POSE 11U +#define GPIO_AFL_AF2_MSK BITS(GPIO_AFL_AF2_POSS,GPIO_AFL_AF2_POSE) +#define GPIO_AFL_AF2 GPIO_AFL_AF2_MSK + +#define GPIO_AFL_AF1_POSS 4U +#define GPIO_AFL_AF1_POSE 7U +#define GPIO_AFL_AF1_MSK BITS(GPIO_AFL_AF1_POSS,GPIO_AFL_AF1_POSE) +#define GPIO_AFL_AF1 GPIO_AFL_AF1_MSK + +#define GPIO_AFL_AF0_POSS 0U +#define GPIO_AFL_AF0_POSE 3U +#define GPIO_AFL_AF0_MSK BITS(GPIO_AFL_AF0_POSS,GPIO_AFL_AF0_POSE) +#define GPIO_AFL_AF0 GPIO_AFL_AF0_MSK + +/****************** Bit definition for GPIO_AFH register ************************/ + +#define GPIO_AFH_AF15_POSS 28U +#define GPIO_AFH_AF15_POSE 31U +#define GPIO_AFH_AF15_MSK BITS(GPIO_AFH_AF15_POSS,GPIO_AFH_AF15_POSE) +#define GPIO_AFH_AF15 GPIO_AFH_AF15_MSK + +#define GPIO_AFH_AF14_POSS 24U +#define GPIO_AFH_AF14_POSE 27U +#define GPIO_AFH_AF14_MSK BITS(GPIO_AFH_AF14_POSS,GPIO_AFH_AF14_POSE) +#define GPIO_AFH_AF14 GPIO_AFH_AF14_MSK + +#define GPIO_AFH_AF13_POSS 20U +#define GPIO_AFH_AF13_POSE 23U +#define GPIO_AFH_AF13_MSK BITS(GPIO_AFH_AF13_POSS,GPIO_AFH_AF13_POSE) +#define GPIO_AFH_AF13 GPIO_AFH_AF13_MSK + +#define GPIO_AFH_AF12_POSS 16U +#define GPIO_AFH_AF12_POSE 19U +#define GPIO_AFH_AF12_MSK BITS(GPIO_AFH_AF12_POSS,GPIO_AFH_AF12_POSE) +#define GPIO_AFH_AF12 GPIO_AFH_AF12_MSK + +#define GPIO_AFH_AF11_POSS 12U +#define GPIO_AFH_AF11_POSE 15U +#define GPIO_AFH_AF11_MSK BITS(GPIO_AFH_AF11_POSS,GPIO_AFH_AF11_POSE) +#define GPIO_AFH_AF11 GPIO_AFH_AF11_MSK + +#define GPIO_AFH_AF10_POSS 8U +#define GPIO_AFH_AF10_POSE 11U +#define GPIO_AFH_AF10_MSK BITS(GPIO_AFH_AF10_POSS,GPIO_AFH_AF10_POSE) +#define GPIO_AFH_AF10 GPIO_AFH_AF10_MSK + +#define GPIO_AFH_AF9_POSS 4U +#define GPIO_AFH_AF9_POSE 7U +#define GPIO_AFH_AF9_MSK BITS(GPIO_AFH_AF9_POSS,GPIO_AFH_AF9_POSE) +#define GPIO_AFH_AF9 GPIO_AFH_AF9_MSK + +#define GPIO_AFH_AF8_POSS 0U +#define GPIO_AFH_AF8_POSE 3U +#define GPIO_AFH_AF8_MSK BITS(GPIO_AFH_AF8_POSS,GPIO_AFH_AF8_POSE) +#define GPIO_AFH_AF8 GPIO_AFH_AF8_MSK + +typedef struct +{ + __I uint32_t ID; + __IO uint32_t OD; + __O uint32_t BSBR; + __IO uint32_t LCK; + __IO uint32_t MOD; + __IO uint32_t PUD; + __IO uint32_t OT; + __IO uint32_t DS; + __IO uint32_t FIR; + __IO uint32_t IST; + __IO uint32_t AFL; + __IO uint32_t AFH; +} GPIO_TypeDef; + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_i2c.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_i2c.h new file mode 100644 index 00000000000..bb8c2f1cc10 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_i2c.h @@ -0,0 +1,710 @@ +/********************************************************************************** + * + * @file reg_i2c.h + * @brief I2C Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __I2C_H__ +#define __I2C_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + +/****************** Bit definition for I2C_CON1 register ************************/ + +# define I2C_CON1_NBYTES_POSS 24U +# define I2C_CON1_NBYTES_POSE 31U +# define I2C_CON1_NBYTES_MSK BITS(I2C_CON1_NBYTES_POSS, I2C_CON1_NBYTES_POSE) +# define I2C_CON1_NBYTES I2C_CON1_NBYTES_MSK + +# define I2C_CON1_PECEN_POS 23U +# define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) +# define I2C_CON1_PECEN I2C_CON1_PECEN_MSK + +# define I2C_CON1_ALERTEN_POS 22U +# define I2C_CON1_ALERTEN_MSK BIT(I2C_CON1_ALERTEN_POS) +# define I2C_CON1_ALERTEN I2C_CON1_ALERTEN_MSK + +# define I2C_CON1_SMBDEN_POS 21U +# define I2C_CON1_SMBDEN_MSK BIT(I2C_CON1_SMBDEN_POS) +# define I2C_CON1_SMBDEN I2C_CON1_SMBDEN_MSK + +# define I2C_CON1_SMBHEN_POS 20U +# define I2C_CON1_SMBHEN_MSK BIT(I2C_CON1_SMBHEN_POS) +# define I2C_CON1_SMBHEN I2C_CON1_SMBHEN_MSK + +# define I2C_CON1_GCEN_POS 19U +# define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) +# define I2C_CON1_GCEN I2C_CON1_GCEN_MSK + +# define I2C_CON1_NOSTRETCH_POS 17U +# define I2C_CON1_NOSTRETCH_MSK BIT(I2C_CON1_NOSTRETCH_POS) +# define I2C_CON1_NOSTRETCH I2C_CON1_NOSTRETCH_MSK + +# define I2C_CON1_SBC_POS 16U +# define I2C_CON1_SBC_MSK BIT(I2C_CON1_SBC_POS) +# define I2C_CON1_SBC I2C_CON1_SBC_MSK + +# define I2C_CON1_RXDMAEN_POS 15U +# define I2C_CON1_RXDMAEN_MSK BIT(I2C_CON1_RXDMAEN_POS) +# define I2C_CON1_RXDMAEN I2C_CON1_RXDMAEN_MSK + +# define I2C_CON1_TXDMAEN_POS 14U +# define I2C_CON1_TXDMAEN_MSK BIT(I2C_CON1_TXDMAEN_POS) +# define I2C_CON1_TXDMAEN I2C_CON1_TXDMAEN_MSK + +# define I2C_CON1_DNF_POSS 8U +# define I2C_CON1_DNF_POSE 11U +# define I2C_CON1_DNF_MSK BITS(I2C_CON1_DNF_POSS, I2C_CON1_DNF_POSE) +# define I2C_CON1_DNF I2C_CON1_DNF_MSK + +# define I2C_CON1_PE_POS 0U +# define I2C_CON1_PE_MSK BIT(I2C_CON1_PE_POS) +# define I2C_CON1_PE I2C_CON1_PE_MSK + +/****************** Bit definition for I2C_CON2 register ************************/ + +# define I2C_CON2_PECBYTE_POS 26U +# define I2C_CON2_PECBYTE_MSK BIT(I2C_CON2_PECBYTE_POS) +# define I2C_CON2_PECBYTE I2C_CON2_PECBYTE_MSK + +# define I2C_CON2_AUTOEND_POS 25U +# define I2C_CON2_AUTOEND_MSK BIT(I2C_CON2_AUTOEND_POS) +# define I2C_CON2_AUTOEND I2C_CON2_AUTOEND_MSK + +# define I2C_CON2_RELOAD_POS 24U +# define I2C_CON2_RELOAD_MSK BIT(I2C_CON2_RELOAD_POS) +# define I2C_CON2_RELOAD I2C_CON2_RELOAD_MSK + +# define I2C_CON2_NBYTES_POSS 16U +# define I2C_CON2_NBYTES_POSE 23U +# define I2C_CON2_NBYTES_MSK BITS(I2C_CON2_NBYTES_POSS, I2C_CON2_NBYTES_POSE) +# define I2C_CON2_NBYTES I2C_CON2_NBYTES_MSK + +# define I2C_CON2_NACK_POS 15U +# define I2C_CON2_NACK_MSK BIT(I2C_CON2_NACK_POS) +# define I2C_CON2_NACK I2C_CON2_NACK_MSK + +# define I2C_CON2_STOP_POS 14U +# define I2C_CON2_STOP_MSK BIT(I2C_CON2_STOP_POS) +# define I2C_CON2_STOP I2C_CON2_STOP_MSK + +# define I2C_CON2_START_POS 13U +# define I2C_CON2_START_MSK BIT(I2C_CON2_START_POS) +# define I2C_CON2_START I2C_CON2_START_MSK + +# define I2C_CON2_HEAD10R_POS 12U +# define I2C_CON2_HEAD10R_MSK BIT(I2C_CON2_HEAD10R_POS) +# define I2C_CON2_HEAD10R I2C_CON2_HEAD10R_MSK + +# define I2C_CON2_ADD10_POS 11U +# define I2C_CON2_ADD10_MSK BIT(I2C_CON2_ADD10_POS) +# define I2C_CON2_ADD10 I2C_CON2_ADD10_MSK + +# define I2C_CON2_RD_WRN_POS 10U +# define I2C_CON2_RD_WRN_MSK BIT(I2C_CON2_RD_WRN_POS) +# define I2C_CON2_RD_WRN I2C_CON2_RD_WRN_MSK + +# define I2C_CON2_SADD_POSS 0U +# define I2C_CON2_SADD_POSE 9U +# define I2C_CON2_SADD_MSK BITS(I2C_CON2_SADD_POSS, I2C_CON2_SADD_POSE) +# define I2C_CON2_SADD I2C_CON2_SADD_MSK + +/****************** Bit definition for I2C_ADDR1 register ************************/ + +# define I2C_ADDR1_OA1EN_POS 15U +# define I2C_ADDR1_OA1EN_MSK BIT(I2C_ADDR1_OA1EN_POS) +# define I2C_ADDR1_OA1EN I2C_ADDR1_OA1EN_MSK + +# define I2C_ADDR1_OA1MODE_POS 10U +# define I2C_ADDR1_OA1MODE_MSK BIT(I2C_ADDR1_OA1MODE_POS) +# define I2C_ADDR1_OA1MODE I2C_ADDR1_OA1MODE_MSK + +# define I2C_ADDR1_OA1_POSS 0U +# define I2C_ADDR1_OA1_POSE 9U +# define I2C_ADDR1_OA1_MSK BITS(I2C_ADDR1_OA1_POSS, I2C_ADDR1_OA1_POSE) +# define I2C_ADDR1_OA1 I2C_ADDR1_OA1_MSK + +/****************** Bit definition for I2C_ADDR2 register ************************/ + +# define I2C_ADDR2_OA2EN_POS 15U +# define I2C_ADDR2_OA2EN_MSK BIT(I2C_ADDR2_OA2EN_POS) +# define I2C_ADDR2_OA2EN I2C_ADDR2_OA2EN_MSK + +# define I2C_ADDR2_OA2MSK_POSS 8U +# define I2C_ADDR2_OA2MSK_POSE 10U +# define I2C_ADDR2_OA2MSK_MSK BITS(I2C_ADDR2_OA2MSK_POSS, I2C_ADDR2_OA2MSK_POSE) +# define I2C_ADDR2_OA2MSK I2C_ADDR2_OA2MSK_MSK + +# define I2C_ADDR2_OA2_POSS 1U +# define I2C_ADDR2_OA2_POSE 7U +# define I2C_ADDR2_OA2_MSK BITS(I2C_ADDR2_OA2_POSS, I2C_ADDR2_OA2_POSE) +# define I2C_ADDR2_OA2 I2C_ADDR2_OA2_MSK + +/****************** Bit definition for I2C_TIMINGR register ************************/ + +# define I2C_TIMINGR_PRESC_POSS 28U +# define I2C_TIMINGR_PRESC_POSE 31U +# define I2C_TIMINGR_PRESC_MSK BITS(I2C_TIMINGR_PRESC_POSS, I2C_TIMINGR_PRESC_POSE) +# define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_MSK + +# define I2C_TIMINGR_SCLDEL_POSS 20U +# define I2C_TIMINGR_SCLDEL_POSE 23U +# define I2C_TIMINGR_SCLDEL_MSK BITS(I2C_TIMINGR_SCLDEL_POSS, I2C_TIMINGR_SCLDEL_POSE) +# define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_MSK + +# define I2C_TIMINGR_SDADEL_POSS 16U +# define I2C_TIMINGR_SDADEL_POSE 19U +# define I2C_TIMINGR_SDADEL_MSK BITS(I2C_TIMINGR_SDADEL_POSS, I2C_TIMINGR_SDADEL_POSE) +# define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_MSK + +# define I2C_TIMINGR_SCLH_POSS 8U +# define I2C_TIMINGR_SCLH_POSE 15U +# define I2C_TIMINGR_SCLH_MSK BITS(I2C_TIMINGR_SCLH_POSS, I2C_TIMINGR_SCLH_POSE) +# define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_MSK + +# define I2C_TIMINGR_SCLL_POSS 0U +# define I2C_TIMINGR_SCLL_POSE 7U +# define I2C_TIMINGR_SCLL_MSK BITS(I2C_TIMINGR_SCLL_POSS, I2C_TIMINGR_SCLL_POSE) +# define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_MSK + +/****************** Bit definition for I2C_TIMEOUTR register ************************/ + +# define I2C_TIMEOUTR_TEXTEN_POS 31U +# define I2C_TIMEOUTR_TEXTEN_MSK BIT(I2C_TIMEOUTR_TEXTEN_POS) +# define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_MSK + +# define I2C_TIMEOUTR_TIMEOUTB_POSS 16U +# define I2C_TIMEOUTR_TIMEOUTB_POSE 27U +# define I2C_TIMEOUTR_TIMEOUTB_MSK BITS(I2C_TIMEOUTR_TIMEOUTB_POSS, I2C_TIMEOUTR_TIMEOUTB_POSE) +# define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_MSK + +# define I2C_TIMEOUTR_TIMEOUTEN_POS 15U +# define I2C_TIMEOUTR_TIMEOUTEN_MSK BIT(I2C_TIMEOUTR_TIMEOUTEN_POS) +# define I2C_TIMEOUTR_TIMEOUTEN I2C_TIMEOUTR_TIMEOUTEN_MSK + +# define I2C_TIMEOUTR_TIDLE_POS 12U +# define I2C_TIMEOUTR_TIDLE_MSK BIT(I2C_TIMEOUTR_TIDLE_POS) +# define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_MSK + +# define I2C_TIMEOUTR_TIMEOUTA_POSS 0U +# define I2C_TIMEOUTR_TIMEOUTA_POSE 11U +# define I2C_TIMEOUTR_TIMEOUTA_MSK BITS(I2C_TIMEOUTR_TIMEOUTA_POSS, I2C_TIMEOUTR_TIMEOUTA_POSE) +# define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_MSK + +/****************** Bit definition for I2C_STAT register ************************/ + +# define I2C_STAT_ADDCODE_POSS 17U +# define I2C_STAT_ADDCODE_POSE 23U +# define I2C_STAT_ADDCODE_MSK BITS(I2C_STAT_ADDCODE_POSS, I2C_STAT_ADDCODE_POSE) +# define I2C_STAT_ADDCODE I2C_STAT_ADDCODE_MSK + +# define I2C_STAT_DIR_POS 16U +# define I2C_STAT_DIR_MSK BIT(I2C_STAT_DIR_POS) +# define I2C_STAT_DIR I2C_STAT_DIR_MSK + +# define I2C_STAT_BUSY_POS 15U +# define I2C_STAT_BUSY_MSK BIT(I2C_STAT_BUSY_POS) +# define I2C_STAT_BUSY I2C_STAT_BUSY_MSK + +# define I2C_STAT_TCR_POS 11U +# define I2C_STAT_TCR_MSK BIT(I2C_STAT_TCR_POS) +# define I2C_STAT_TCR I2C_STAT_TCR_MSK + +# define I2C_STAT_TC_POS 10U +# define I2C_STAT_TC_MSK BIT(I2C_STAT_TC_POS) +# define I2C_STAT_TC I2C_STAT_TC_MSK + +# define I2C_STAT_RXUD_POS 8U +# define I2C_STAT_RXUD_MSK BIT(I2C_STAT_RXUD_POS) +# define I2C_STAT_RXUD I2C_STAT_RXUD_MSK + +# define I2C_STAT_RXOV_POS 7U +# define I2C_STAT_RXOV_MSK BIT(I2C_STAT_RXOV_POS) +# define I2C_STAT_RXOV I2C_STAT_RXOV_MSK + +# define I2C_STAT_RXNE_POS 5U +# define I2C_STAT_RXNE_MSK BIT(I2C_STAT_RXNE_POS) +# define I2C_STAT_RXNE I2C_STAT_RXNE_MSK + +# define I2C_STAT_TXUD_POS 3U +# define I2C_STAT_TXUD_MSK BIT(I2C_STAT_TXUD_POS) +# define I2C_STAT_TXUD I2C_STAT_TXUD_MSK + +# define I2C_STAT_TXOV_POS 2U +# define I2C_STAT_TXOV_MSK BIT(I2C_STAT_TXOV_POS) +# define I2C_STAT_TXOV I2C_STAT_TXOV_MSK + +# define I2C_STAT_TXE_POS 0U +# define I2C_STAT_TXE_MSK BIT(I2C_STAT_TXE_POS) +# define I2C_STAT_TXE I2C_STAT_TXE_MSK + +/****************** Bit definition for I2C_PECR register ************************/ + +# define I2C_PECR_PEC_POSS 0U +# define I2C_PECR_PEC_POSE 7U +# define I2C_PECR_PEC_MSK BITS(I2C_PECR_PEC_POSS, I2C_PECR_PEC_POSE) +# define I2C_PECR_PEC I2C_PECR_PEC_MSK + +/****************** Bit definition for I2C_RXDATA register ************************/ + +# define I2C_RXDATA_RXDATA_POSS 0U +# define I2C_RXDATA_RXDATA_POSE 7U +# define I2C_RXDATA_RXDATA_MSK BITS(I2C_RXDATA_RXDATA_POSS, I2C_RXDATA_RXDATA_POSE) +# define I2C_RXDATA_RXDATA I2C_RXDATA_RXDATA_MSK + +/****************** Bit definition for I2C_TXDATA register ************************/ + +# define I2C_TXDATA_TXDATA_POSS 0U +# define I2C_TXDATA_TXDATA_POSE 7U +# define I2C_TXDATA_TXDATA_MSK BITS(I2C_TXDATA_TXDATA_POSS, I2C_TXDATA_TXDATA_POSE) +# define I2C_TXDATA_TXDATA I2C_TXDATA_TXDATA_MSK + +/****************** Bit definition for I2C_IER register ************************/ + +# define I2C_IER_ALERT_POS 20U +# define I2C_IER_ALERT_MSK BIT(I2C_IER_ALERT_POS) +# define I2C_IER_ALERT I2C_IER_ALERT_MSK + +# define I2C_IER_TOUT_POS 19U +# define I2C_IER_TOUT_MSK BIT(I2C_IER_TOUT_POS) +# define I2C_IER_TOUT I2C_IER_TOUT_MSK + +# define I2C_IER_PECE_POS 18U +# define I2C_IER_PECE_MSK BIT(I2C_IER_PECE_POS) +# define I2C_IER_PECE I2C_IER_PECE_MSK + +# define I2C_IER_ARLO_POS 17U +# define I2C_IER_ARLO_MSK BIT(I2C_IER_ARLO_POS) +# define I2C_IER_ARLO I2C_IER_ARLO_MSK + +# define I2C_IER_BERR_POS 16U +# define I2C_IER_BERR_MSK BIT(I2C_IER_BERR_POS) +# define I2C_IER_BERR I2C_IER_BERR_MSK + +# define I2C_IER_STOP_POS 14U +# define I2C_IER_STOP_MSK BIT(I2C_IER_STOP_POS) +# define I2C_IER_STOP I2C_IER_STOP_MSK + +# define I2C_IER_NACK_POS 13U +# define I2C_IER_NACK_MSK BIT(I2C_IER_NACK_POS) +# define I2C_IER_NACK I2C_IER_NACK_MSK + +# define I2C_IER_ADDR_POS 12U +# define I2C_IER_ADDR_MSK BIT(I2C_IER_ADDR_POS) +# define I2C_IER_ADDR I2C_IER_ADDR_MSK + +# define I2C_IER_TCR_POS 11U +# define I2C_IER_TCR_MSK BIT(I2C_IER_TCR_POS) +# define I2C_IER_TCR I2C_IER_TCR_MSK + +# define I2C_IER_TC_POS 10U +# define I2C_IER_TC_MSK BIT(I2C_IER_TC_POS) +# define I2C_IER_TC I2C_IER_TC_MSK + +# define I2C_IER_RXUD_POS 8U +# define I2C_IER_RXUD_MSK BIT(I2C_IER_RXUD_POS) +# define I2C_IER_RXUD I2C_IER_RXUD_MSK + +# define I2C_IER_RXOV_POS 7U +# define I2C_IER_RXOV_MSK BIT(I2C_IER_RXOV_POS) +# define I2C_IER_RXOV I2C_IER_RXOV_MSK + +# define I2C_IER_RXNE_POS 5U +# define I2C_IER_RXNE_MSK BIT(I2C_IER_RXNE_POS) +# define I2C_IER_RXNE I2C_IER_RXNE_MSK + +# define I2C_IER_TXUD_POS 3U +# define I2C_IER_TXUD_MSK BIT(I2C_IER_TXUD_POS) +# define I2C_IER_TXUD I2C_IER_TXUD_MSK + +# define I2C_IER_TXOV_POS 2U +# define I2C_IER_TXOV_MSK BIT(I2C_IER_TXOV_POS) +# define I2C_IER_TXOV I2C_IER_TXOV_MSK + +# define I2C_IER_TXE_POS 0U +# define I2C_IER_TXE_MSK BIT(I2C_IER_TXE_POS) +# define I2C_IER_TXE I2C_IER_TXE_MSK + +/****************** Bit definition for I2C_IDR register ************************/ + +# define I2C_IDR_ALERT_POS 20U +# define I2C_IDR_ALERT_MSK BIT(I2C_IDR_ALERT_POS) +# define I2C_IDR_ALERT I2C_IDR_ALERT_MSK + +# define I2C_IDR_TOUT_POS 19U +# define I2C_IDR_TOUT_MSK BIT(I2C_IDR_TOUT_POS) +# define I2C_IDR_TOUT I2C_IDR_TOUT_MSK + +# define I2C_IDR_PECE_POS 18U +# define I2C_IDR_PECE_MSK BIT(I2C_IDR_PECE_POS) +# define I2C_IDR_PECE I2C_IDR_PECE_MSK + +# define I2C_IDR_ARLO_POS 17U +# define I2C_IDR_ARLO_MSK BIT(I2C_IDR_ARLO_POS) +# define I2C_IDR_ARLO I2C_IDR_ARLO_MSK + +# define I2C_IDR_BERR_POS 16U +# define I2C_IDR_BERR_MSK BIT(I2C_IDR_BERR_POS) +# define I2C_IDR_BERR I2C_IDR_BERR_MSK + +# define I2C_IDR_STOP_POS 14U +# define I2C_IDR_STOP_MSK BIT(I2C_IDR_STOP_POS) +# define I2C_IDR_STOP I2C_IDR_STOP_MSK + +# define I2C_IDR_NACK_POS 13U +# define I2C_IDR_NACK_MSK BIT(I2C_IDR_NACK_POS) +# define I2C_IDR_NACK I2C_IDR_NACK_MSK + +# define I2C_IDR_ADDR_POS 12U +# define I2C_IDR_ADDR_MSK BIT(I2C_IDR_ADDR_POS) +# define I2C_IDR_ADDR I2C_IDR_ADDR_MSK + +# define I2C_IDR_TCR_POS 11U +# define I2C_IDR_TCR_MSK BIT(I2C_IDR_TCR_POS) +# define I2C_IDR_TCR I2C_IDR_TCR_MSK + +# define I2C_IDR_TC_POS 10U +# define I2C_IDR_TC_MSK BIT(I2C_IDR_TC_POS) +# define I2C_IDR_TC I2C_IDR_TC_MSK + +# define I2C_IDR_RXUD_POS 8U +# define I2C_IDR_RXUD_MSK BIT(I2C_IDR_RXUD_POS) +# define I2C_IDR_RXUD I2C_IDR_RXUD_MSK + +# define I2C_IDR_RXOV_POS 7U +# define I2C_IDR_RXOV_MSK BIT(I2C_IDR_RXOV_POS) +# define I2C_IDR_RXOV I2C_IDR_RXOV_MSK + +# define I2C_IDR_RXNE_POS 5U +# define I2C_IDR_RXNE_MSK BIT(I2C_IDR_RXNE_POS) +# define I2C_IDR_RXNE I2C_IDR_RXNE_MSK + +# define I2C_IDR_TXUD_POS 3U +# define I2C_IDR_TXUD_MSK BIT(I2C_IDR_TXUD_POS) +# define I2C_IDR_TXUD I2C_IDR_TXUD_MSK + +# define I2C_IDR_TXOV_POS 2U +# define I2C_IDR_TXOV_MSK BIT(I2C_IDR_TXOV_POS) +# define I2C_IDR_TXOV I2C_IDR_TXOV_MSK + +# define I2C_IDR_TXE_POS 0U +# define I2C_IDR_TXE_MSK BIT(I2C_IDR_TXE_POS) +# define I2C_IDR_TXE I2C_IDR_TXE_MSK +/****************** Bit definition for I2C_IVS register ************************/ + +# define I2C_IVS_ALERT_POS 20U +# define I2C_IVS_ALERT_MSK BIT(I2C_IVS_ALERT_POS) +# define I2C_IVS_ALERT I2C_IVS_ALERT_MSK + +# define I2C_IVS_TOUT_POS 19U +# define I2C_IVS_TOUT_MSK BIT(I2C_IVS_TOUT_POS) +# define I2C_IVS_TOUT I2C_IVS_TOUT_MSK + +# define I2C_IVS_PECE_POS 18U +# define I2C_IVS_PECE_MSK BIT(I2C_IVS_PECE_POS) +# define I2C_IVS_PECE I2C_IVS_PECE_MSK + +# define I2C_IVS_ARLO_POS 17U +# define I2C_IVS_ARLO_MSK BIT(I2C_IVS_ARLO_POS) +# define I2C_IVS_ARLO I2C_IVS_ARLO_MSK + +# define I2C_IVS_BERR_POS 16U +# define I2C_IVS_BERR_MSK BIT(I2C_IVS_BERR_POS) +# define I2C_IVS_BERR I2C_IVS_BERR_MSK + +# define I2C_IVS_STOP_POS 14U +# define I2C_IVS_STOP_MSK BIT(I2C_IVS_STOP_POS) +# define I2C_IVS_STOP I2C_IVS_STOP_MSK + +# define I2C_IVS_NACK_POS 13U +# define I2C_IVS_NACK_MSK BIT(I2C_IVS_NACK_POS) +# define I2C_IVS_NACK I2C_IVS_NACK_MSK + +# define I2C_IVS_ADDR_POS 12U +# define I2C_IVS_ADDR_MSK BIT(I2C_IVS_ADDR_POS) +# define I2C_IVS_ADDR I2C_IVS_ADDR_MSK + +# define I2C_IVS_TCR_POS 11U +# define I2C_IVS_TCR_MSK BIT(I2C_IVS_TCR_POS) +# define I2C_IVS_TCR I2C_IVS_TCR_MSK + +# define I2C_IVS_TC_POS 10U +# define I2C_IVS_TC_MSK BIT(I2C_IVS_TC_POS) +# define I2C_IVS_TC I2C_IVS_TC_MSK + +# define I2C_IVS_RXUD_POS 8U +# define I2C_IVS_RXUD_MSK BIT(I2C_IVS_RXUD_POS) +# define I2C_IVS_RXUD I2C_IVS_RXUD_MSK + +# define I2C_IVS_RXOV_POS 7U +# define I2C_IVS_RXOV_MSK BIT(I2C_IVS_RXOV_POS) +# define I2C_IVS_RXOV I2C_IVS_RXOV_MSK + +# define I2C_IVS_RXNE_POS 5U +# define I2C_IVS_RXNE_MSK BIT(I2C_IVS_RXNE_POS) +# define I2C_IVS_RXNE I2C_IVS_RXNE_MSK + +# define I2C_IVS_TXUD_POS 3U +# define I2C_IVS_TXUD_MSK BIT(I2C_IVS_TXUD_POS) +# define I2C_IVS_TXUD I2C_IVS_TXUD_MSK + +# define I2C_IVS_TXOV_POS 2U +# define I2C_IVS_TXOV_MSK BIT(I2C_IVS_TXOV_POS) +# define I2C_IVS_TXOV I2C_IVS_TXOV_MSK + +# define I2C_IVS_TXE_POS 0U +# define I2C_IVS_TXE_MSK BIT(I2C_IVS_TXE_POS) +# define I2C_IVS_TXE I2C_IVS_TXE_MSK + +/****************** Bit definition for I2C_RIF register ************************/ + +# define I2C_RIF_ALERT_POS 20U +# define I2C_RIF_ALERT_MSK BIT(I2C_RIF_ALERT_POS) +# define I2C_RIF_ALERT I2C_RIF_ALERT_MSK + +# define I2C_RIF_TOUT_POS 19U +# define I2C_RIF_TOUT_MSK BIT(I2C_RIF_TOUT_POS) +# define I2C_RIF_TOUT I2C_RIF_TOUT_MSK + +# define I2C_RIF_PECE_POS 18U +# define I2C_RIF_PECE_MSK BIT(I2C_RIF_PECE_POS) +# define I2C_RIF_PECE I2C_RIF_PECE_MSK + +# define I2C_RIF_ARLO_POS 17U +# define I2C_RIF_ARLO_MSK BIT(I2C_RIF_ARLO_POS) +# define I2C_RIF_ARLO I2C_RIF_ARLO_MSK + +# define I2C_RIF_BERR_POS 16U +# define I2C_RIF_BERR_MSK BIT(I2C_RIF_BERR_POS) +# define I2C_RIF_BERR I2C_RIF_BERR_MSK + +# define I2C_RIF_STOP_POS 14U +# define I2C_RIF_STOP_MSK BIT(I2C_RIF_STOP_POS) +# define I2C_RIF_STOP I2C_RIF_STOP_MSK + +# define I2C_RIF_NACK_POS 13U +# define I2C_RIF_NACK_MSK BIT(I2C_RIF_NACK_POS) +# define I2C_RIF_NACK I2C_RIF_NACK_MSK + +# define I2C_RIF_ADDR_POS 12U +# define I2C_RIF_ADDR_MSK BIT(I2C_RIF_ADDR_POS) +# define I2C_RIF_ADDR I2C_RIF_ADDR_MSK + +# define I2C_RIF_TCR_POS 11U +# define I2C_RIF_TCR_MSK BIT(I2C_RIF_TCR_POS) +# define I2C_RIF_TCR I2C_RIF_TCR_MSK + +# define I2C_RIF_TC_POS 10U +# define I2C_RIF_TC_MSK BIT(I2C_RIF_TC_POS) +# define I2C_RIF_TC I2C_RIF_TC_MSK + +# define I2C_RIF_RXUD_POS 8U +# define I2C_RIF_RXUD_MSK BIT(I2C_RIF_RXUD_POS) +# define I2C_RIF_RXUD I2C_RIF_RXUD_MSK + +# define I2C_RIF_RXOV_POS 7U +# define I2C_RIF_RXOV_MSK BIT(I2C_RIF_RXOV_POS) +# define I2C_RIF_RXOV I2C_RIF_RXOV_MSK + +# define I2C_RIF_RXNE_POS 5U +# define I2C_RIF_RXNE_MSK BIT(I2C_RIF_RXNE_POS) +# define I2C_RIF_RXNE I2C_RIF_RXNE_MSK + +# define I2C_RIF_TXUD_POS 3U +# define I2C_RIF_TXUD_MSK BIT(I2C_RIF_TXUD_POS) +# define I2C_RIF_TXUD I2C_RIF_TXUD_MSK + +# define I2C_RIF_TXOV_POS 2U +# define I2C_RIF_TXOV_MSK BIT(I2C_RIF_TXOV_POS) +# define I2C_RIF_TXOV I2C_RIF_TXOV_MSK + +# define I2C_RIF_TXE_POS 0U +# define I2C_RIF_TXE_MSK BIT(I2C_RIF_TXE_POS) +# define I2C_RIF_TXE I2C_RIF_TXE_MSK + +/****************** Bit definition for I2C_IFM register ************************/ + +# define I2C_IFM_ALERT_POS 20U +# define I2C_IFM_ALERT_MSK BIT(I2C_IFM_ALERT_POS) +# define I2C_IFM_ALERT I2C_IFM_ALERT_MSK + +# define I2C_IFM_TOUT_POS 19U +# define I2C_IFM_TOUT_MSK BIT(I2C_IFM_TOUT_POS) +# define I2C_IFM_TOUT I2C_IFM_TOUT_MSK + +# define I2C_IFM_PECE_POS 18U +# define I2C_IFM_PECE_MSK BIT(I2C_IFM_PECE_POS) +# define I2C_IFM_PECE I2C_IFM_PECE_MSK + +# define I2C_IFM_ARLO_POS 17U +# define I2C_IFM_ARLO_MSK BIT(I2C_IFM_ARLO_POS) +# define I2C_IFM_ARLO I2C_IFM_ARLO_MSK + +# define I2C_IFM_BERR_POS 16U +# define I2C_IFM_BERR_MSK BIT(I2C_IFM_BERR_POS) +# define I2C_IFM_BERR I2C_IFM_BERR_MSK + +# define I2C_IFM_STOP_POS 14U +# define I2C_IFM_STOP_MSK BIT(I2C_IFM_STOP_POS) +# define I2C_IFM_STOP I2C_IFM_STOP_MSK + +# define I2C_IFM_NACK_POS 13U +# define I2C_IFM_NACK_MSK BIT(I2C_IFM_NACK_POS) +# define I2C_IFM_NACK I2C_IFM_NACK_MSK + +# define I2C_IFM_ADDR_POS 12U +# define I2C_IFM_ADDR_MSK BIT(I2C_IFM_ADDR_POS) +# define I2C_IFM_ADDR I2C_IFM_ADDR_MSK + +# define I2C_IFM_TCR_POS 11U +# define I2C_IFM_TCR_MSK BIT(I2C_IFM_TCR_POS) +# define I2C_IFM_TCR I2C_IFM_TCR_MSK + +# define I2C_IFM_TC_POS 10U +# define I2C_IFM_TC_MSK BIT(I2C_IFM_TC_POS) +# define I2C_IFM_TC I2C_IFM_TC_MSK + +# define I2C_IFM_RXUD_POS 8U +# define I2C_IFM_RXUD_MSK BIT(I2C_IFM_RXUD_POS) +# define I2C_IFM_RXUD I2C_IFM_RXUD_MSK + +# define I2C_IFM_RXOV_POS 7U +# define I2C_IFM_RXOV_MSK BIT(I2C_IFM_RXOV_POS) +# define I2C_IFM_RXOV I2C_IFM_RXOV_MSK + +# define I2C_IFM_RXNE_POS 5U +# define I2C_IFM_RXNE_MSK BIT(I2C_IFM_RXNE_POS) +# define I2C_IFM_RXNE I2C_IFM_RXNE_MSK + +# define I2C_IFM_TXUD_POS 3U +# define I2C_IFM_TXUD_MSK BIT(I2C_IFM_TXUD_POS) +# define I2C_IFM_TXUD I2C_IFM_TXUD_MSK + +# define I2C_IFM_TXOV_POS 2U +# define I2C_IFM_TXOV_MSK BIT(I2C_IFM_TXOV_POS) +# define I2C_IFM_TXOV I2C_IFM_TXOV_MSK + +# define I2C_IFM_TXE_POS 0U +# define I2C_IFM_TXE_MSK BIT(I2C_IFM_TXE_POS) +# define I2C_IFM_TXE I2C_IFM_TXE_MSK + +/****************** Bit definition for I2C_ICR register ************************/ + +# define I2C_ICR_ALERT_POS 20U +# define I2C_ICR_ALERT_MSK BIT(I2C_ICR_ALERT_POS) +# define I2C_ICR_ALERT I2C_ICR_ALERT_MSK + +# define I2C_ICR_TOUT_POS 19U +# define I2C_ICR_TOUT_MSK BIT(I2C_ICR_TOUT_POS) +# define I2C_ICR_TOUT I2C_ICR_TOUT_MSK + +# define I2C_ICR_PECE_POS 18U +# define I2C_ICR_PECE_MSK BIT(I2C_ICR_PECE_POS) +# define I2C_ICR_PECE I2C_ICR_PECE_MSK + +# define I2C_ICR_ARLO_POS 17U +# define I2C_ICR_ARLO_MSK BIT(I2C_ICR_ARLO_POS) +# define I2C_ICR_ARLO I2C_ICR_ARLO_MSK + +# define I2C_ICR_BERR_POS 16U +# define I2C_ICR_BERR_MSK BIT(I2C_ICR_BERR_POS) +# define I2C_ICR_BERR I2C_ICR_BERR_MSK + +# define I2C_ICR_STOP_POS 14U +# define I2C_ICR_STOP_MSK BIT(I2C_ICR_STOP_POS) +# define I2C_ICR_STOP I2C_ICR_STOP_MSK + +# define I2C_ICR_NACK_POS 13U +# define I2C_ICR_NACK_MSK BIT(I2C_ICR_NACK_POS) +# define I2C_ICR_NACK I2C_ICR_NACK_MSK + +# define I2C_ICR_ADDR_POS 12U +# define I2C_ICR_ADDR_MSK BIT(I2C_ICR_ADDR_POS) +# define I2C_ICR_ADDR I2C_ICR_ADDR_MSK + +# define I2C_ICR_TCR_POS 11U +# define I2C_ICR_TCR_MSK BIT(I2C_ICR_TCR_POS) +# define I2C_ICR_TCR I2C_ICR_TCR_MSK + +# define I2C_ICR_TC_POS 10U +# define I2C_ICR_TC_MSK BIT(I2C_ICR_TC_POS) +# define I2C_ICR_TC I2C_ICR_TC_MSK + +# define I2C_ICR_RXUD_POS 8U +# define I2C_ICR_RXUD_MSK BIT(I2C_ICR_RXUD_POS) +# define I2C_ICR_RXUD I2C_ICR_RXUD_MSK + +# define I2C_ICR_RXOV_POS 7U +# define I2C_ICR_RXOV_MSK BIT(I2C_ICR_RXOV_POS) +# define I2C_ICR_RXOV I2C_ICR_RXOV_MSK + +# define I2C_ICR_RXNE_POS 5U +# define I2C_ICR_RXNE_MSK BIT(I2C_ICR_RXNE_POS) +# define I2C_ICR_RXNE I2C_ICR_RXNE_MSK + +# define I2C_ICR_TXUD_POS 3U +# define I2C_ICR_TXUD_MSK BIT(I2C_ICR_TXUD_POS) +# define I2C_ICR_TXUD I2C_ICR_TXUD_MSK + +# define I2C_ICR_TXOV_POS 2U +# define I2C_ICR_TXOV_MSK BIT(I2C_ICR_TXOV_POS) +# define I2C_ICR_TXOV I2C_ICR_TXOV_MSK + +# define I2C_ICR_TXE_POS 0U +# define I2C_ICR_TXE_MSK BIT(I2C_ICR_TXE_POS) +# define I2C_ICR_TXE I2C_ICR_TXE_MSK + +typedef struct +{ + __IO uint32_t CON1; // 0x000 + __IO uint32_t CON2; // 0x004 + __IO uint32_t ADDR1; // 0x008 + __IO uint32_t ADDR2; // 0x00c + __IO uint32_t TIMINGR; // 0x010 + __IO uint32_t TIMEOUTR; // 0x014 + __I uint32_t STAT; // 0x018 + __IO uint32_t RESERVED0; // 0x01c + __IO uint32_t PECR; // 0x020 + __I uint32_t RXDATA; // 0x024 + __O uint32_t TXDATA; // 0x028 + __O uint32_t IER; // 0x02c + __O uint32_t IDR; // 0x030 + __I uint32_t IVS; // 0x034 + __I uint32_t RIF; // 0x038 + __I uint32_t IFM; // 0x03c + __O uint32_t ICR; // 0x040 +} I2C_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_iwdt.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_iwdt.h new file mode 100644 index 00000000000..181fd6508f1 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_iwdt.h @@ -0,0 +1,96 @@ +/********************************************************************************** + * + * @file reg_iwdt.h + * @brief IWDT Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __IWDT_H__ +#define __IWDT_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +////#pragma anon_unions + +/****************** Bit definition for IWDT_BKKR register ************************/ + +# define IWDT_BKKR_KEY_POSS 0U +# define IWDT_BKKR_KEY_POSE 15U +# define IWDT_BKKR_KEY_MSK BITS(IWDT_BKKR_KEY_POSS, IWDT_BKKR_KEY_POSE) +# define IWDT_BKKR_KEY IWDT_BKKR_KEY_MSK + +/****************** Bit definition for IWDT_BKPR register ************************/ + +# define IWDT_BKPR_PR_POSS 0U +# define IWDT_BKPR_PR_POSE 2U +# define IWDT_BKPR_PR_MSK BITS(IWDT_BKPR_PR_POSS, IWDT_BKPR_PR_POSE) +# define IWDT_BKPR_PR IWDT_BKPR_PR_MSK + +/****************** Bit definition for IWDT_BKRLR register ************************/ + +# define IWDT_BKRLR_RL_POSS 0U +# define IWDT_BKRLR_RL_POSE 11U +# define IWDT_BKRLR_RL_MSK BITS(IWDT_BKRLR_RL_POSS, IWDT_BKRLR_RL_POSE) +# define IWDT_BKRLR_RL IWDT_BKRLR_RL_MSK + +/****************** Bit definition for IWDT_BKFR register ************************/ + +# define IWDT_BKFR_BUSY_POS 15U +# define IWDT_BKFR_BUSY_MSK BIT(IWDT_BKFR_BUSY_POS) +# define IWDT_BKFR_BUSY IWDT_BKFR_BUSY_MSK + +/****************** Bit definition for IWDT_BKWINR register ************************/ + +# define IWDT_BKWINR_WIN_POSS 0U +# define IWDT_BKWINR_WIN_POSE 11U +# define IWDT_BKWINR_WIN_MSK BITS(IWDT_BKWINR_WIN_POSS, IWDT_BKWINR_WIN_POSE) +# define IWDT_BKWINR_WIN IWDT_BKWINR_WIN_MSK + +/****************** Bit definition for IWDT_BKSR register ************************/ + +# define IWDT_BKSR_CNT_POSS 0U +# define IWDT_BKSR_CNT_POSE 11U +# define IWDT_BKSR_CNT_MSK BITS(IWDT_BKSR_CNT_POSS, IWDT_BKSR_CNT_POSE) +# define IWDT_BKSR_CNT IWDT_BKSR_CNT_MSK + +typedef struct +{ + __IO uint32_t RESERVED0[32]; // 0x000-0x07c + __O uint32_t BKKR; // 0x080 + __IO uint32_t BKPR; // 0x084 + __IO uint32_t BKRLR; // 0x088 + __I uint32_t BKFR; // 0x08c + __IO uint32_t BKWINR; // 0x090 + __I uint32_t BKSR; // 0x094 +} IWDT_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_kbcu.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_kbcu.h new file mode 100644 index 00000000000..a6aaafece96 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_kbcu.h @@ -0,0 +1,595 @@ +/********************************************************************************** + * + * @file reg_kbcu.h + * @brief KBCU Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __KBCU_H__ +#define __KBCU_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + +/****************** Bit definition for KBCU_IER register ************************/ + +# define KBCU_IER_KEY_POS 2U +# define KBCU_IER_KEY_MSK BIT(KBCU_IER_KEY_POS) +# define KBCU_IER_KEY KBCU_IER_KEY_MSK + +# define KBCU_IER_COLUMN_POS 1U +# define KBCU_IER_COLUMN_MSK BIT(KBCU_IER_COLUMN_POS) +# define KBCU_IER_COLUMN KBCU_IER_COLUMN_MSK + +# define KBCU_IER_FRAME_POS 0U +# define KBCU_IER_FRAME_MSK BIT(KBCU_IER_FRAME_POS) +# define KBCU_IER_FRAME KBCU_IER_FRAME_MSK + +/****************** Bit definition for KBCU_IDR register ************************/ + +# define KBCU_IDR_KEY_POS 2U +# define KBCU_IDR_KEY_MSK BIT(KBCU_IDR_KEY_POS) +# define KBCU_IDR_KEY KBCU_IDR_KEY_MSK + +# define KBCU_IDR_COLUMN_POS 1U +# define KBCU_IDR_COLUMN_MSK BIT(KBCU_IDR_COLUMN_POS) +# define KBCU_IDR_COLUMN KBCU_IDR_COLUMN_MSK + +# define KBCU_IDR_FRAME_POS 0U +# define KBCU_IDR_FRAME_MSK BIT(KBCU_IDR_FRAME_POS) +# define KBCU_IDR_FRAME KBCU_IDR_FRAME_MSK + +/****************** Bit definition for KBCU_IVS register ************************/ + +# define KBCU_IVS_KEY_POS 2U +# define KBCU_IVS_KEY_MSK BIT(KBCU_IVS_KEY_POS) +# define KBCU_IVS_KEY KBCU_IVS_KEY_MSK + +# define KBCU_IVS_COLUMN_POS 1U +# define KBCU_IVS_COLUMN_MSK BIT(KBCU_IVS_COLUMN_POS) +# define KBCU_IVS_COLUMN KBCU_IVS_COLUMN_MSK + +# define KBCU_IVS_FRAME_POS 0U +# define KBCU_IVS_FRAME_MSK BIT(KBCU_IVS_FRAME_POS) +# define KBCU_IVS_FRAME KBCU_IVS_FRAME_MSK + +/****************** Bit definition for KBCU_RIF register ************************/ + +# define KBCU_RIF_KEY_POS 2U +# define KBCU_RIF_KEY_MSK BIT(KBCU_RIF_KEY_POS) +# define KBCU_RIF_KEY KBCU_RIF_KEY_MSK + +# define KBCU_RIF_COLUMN_POS 1U +# define KBCU_RIF_COLUMN_MSK BIT(KBCU_RIF_COLUMN_POS) +# define KBCU_RIF_COLUMN KBCU_RIF_COLUMN_MSK + +# define KBCU_RIF_FRAME_POS 0U +# define KBCU_RIF_FRAME_MSK BIT(KBCU_RIF_FRAME_POS) +# define KBCU_RIF_FRAME KBCU_RIF_FRAME_MSK + +/****************** Bit definition for KBCU_IFM register ************************/ + +# define KBCU_IFM_KEY_POS 2U +# define KBCU_IFM_KEY_MSK BIT(KBCU_IFM_KEY_POS) +# define KBCU_IFM_KEY KBCU_IFM_KEY_MSK + +# define KBCU_IFM_COLUMN_POS 1U +# define KBCU_IFM_COLUMN_MSK BIT(KBCU_IFM_COLUMN_POS) +# define KBCU_IFM_COLUMN KBCU_IFM_COLUMN_MSK + +# define KBCU_IFM_FRAME_POS 0U +# define KBCU_IFM_FRAME_MSK BIT(KBCU_IFM_FRAME_POS) +# define KBCU_IFM_FRAME KBCU_IFM_FRAME_MSK + +/****************** Bit definition for KBCU_ICR register ************************/ + +# define KBCU_ICR_KEY_POS 2U +# define KBCU_ICR_KEY_MSK BIT(KBCU_ICR_KEY_POS) +# define KBCU_ICR_KEY KBCU_ICR_KEY_MSK + +# define KBCU_ICR_COLUMN_POS 1U +# define KBCU_ICR_COLUMN_MSK BIT(KBCU_ICR_COLUMN_POS) +# define KBCU_ICR_COLUMN KBCU_ICR_COLUMN_MSK + +# define KBCU_ICR_FRAME_POS 0U +# define KBCU_ICR_FRAME_MSK BIT(KBCU_ICR_FRAME_POS) +# define KBCU_ICR_FRAME KBCU_ICR_FRAME_MSK + +/****************** Bit definition for KBCU_CON1 register ************************/ + +# define KBCU_CON1_COL_CTRL_POS 18U +# define KBCU_CON1_COL_CTRL_MSK BIT(KBCU_CON1_COL_CTRL_POS) +# define KBCU_CON1_COL_CTRL KBCU_CON1_COL_CTRL_MSK + +# define KBCU_CON1_LED_CTRL_POS 17U +# define KBCU_CON1_LED_CTRL_MSK BIT(KBCU_CON1_LED_CTRL_POS) +# define KBCU_CON1_LED_CTRL KBCU_CON1_LED_CTRL_MSK + +# define KBCU_CON1_KEY_CTRL_POS 16U +# define KBCU_CON1_KEY_CTRL_MSK BIT(KBCU_CON1_KEY_CTRL_POS) +# define KBCU_CON1_KEY_CTRL KBCU_CON1_KEY_CTRL_MSK + +# define KBCU_CON1_COL_FLAG_POS 15U +# define KBCU_CON1_COL_FLAG_MSK BIT(KBCU_CON1_COL_FLAG_POS) +# define KBCU_CON1_COL_FLAG KBCU_CON1_COL_FLAG_MSK + +# define KBCU_CON1_COL_MASK_POSS 8U +# define KBCU_CON1_COL_MASK_POSE 12U +# define KBCU_CON1_COL_MASK_MSK BITS(KBCU_CON1_COL_MASK_POSS, KBCU_CON1_COL_MASK_POSE) +# define KBCU_CON1_COL_MASK KBCU_CON1_COL_MASK_MSK + +# define KBCU_CON1_COLUMN_SEL_POSS 2U +# define KBCU_CON1_COLUMN_SEL_POSE 5U +# define KBCU_CON1_COLUMN_SEL_MSK BITS(KBCU_CON1_COLUMN_SEL_POSS, KBCU_CON1_COLUMN_SEL_POSE) +# define KBCU_CON1_COLUMN_SEL KBCU_CON1_COLUMN_SEL_MSK + +# define KBCU_CON1_BLINK_POS 1U +# define KBCU_CON1_BLINK_MSK BIT(KBCU_CON1_BLINK_POS) +# define KBCU_CON1_BLINK KBCU_CON1_BLINK_MSK + +# define KBCU_CON1_KBEN_POS 0U +# define KBCU_CON1_KBEN_MSK BIT(KBCU_CON1_KBEN_POS) +# define KBCU_CON1_KBEN KBCU_CON1_KBEN_MSK + +/****************** Bit definition for KBCU_CON2 register ************************/ + +# define KBCU_CON2_COLVALUE_POSS 27U +# define KBCU_CON2_COLVALUE_POSE 31U +# define KBCU_CON2_COLVALUE_MSK BITS(KBCU_CON2_COLVALUE_POSS, KBCU_CON2_COLVALUE_POSE) +# define KBCU_CON2_COLVALUE KBCU_CON2_COLVALUE_MSK + +# define KBCU_CON2_DTVALUE_POSS 24U +# define KBCU_CON2_DTVALUE_POSE 26U +# define KBCU_CON2_DTVALUE_MSK BITS(KBCU_CON2_DTVALUE_POSS, KBCU_CON2_DTVALUE_POSE) +# define KBCU_CON2_DTVALUE KBCU_CON2_DTVALUE_MSK + +# define KBCU_CON2_FCVALUE_POSS 16U +# define KBCU_CON2_FCVALUE_POSE 23U +# define KBCU_CON2_FCVALUE_MSK BITS(KBCU_CON2_FCVALUE_POSS, KBCU_CON2_FCVALUE_POSE) +# define KBCU_CON2_FCVALUE KBCU_CON2_FCVALUE_MSK + +# define KBCU_CON2_FRDIV_POSS 8U +# define KBCU_CON2_FRDIV_POSE 15U +# define KBCU_CON2_FRDIV_MSK BITS(KBCU_CON2_FRDIV_POSS, KBCU_CON2_FRDIV_POSE) +# define KBCU_CON2_FRDIV KBCU_CON2_FRDIV_MSK + +# define KBCU_CON2_ARVALUE_POSS 0U +# define KBCU_CON2_ARVALUE_POSE 7U +# define KBCU_CON2_ARVALUE_MSK BITS(KBCU_CON2_ARVALUE_POSS, KBCU_CON2_ARVALUE_POSE) +# define KBCU_CON2_ARVALUE KBCU_CON2_ARVALUE_MSK + +/****************** Bit definition for KBCU_SCAN0 register ************************/ + +# define KBCU_SCAN0_COLUMN3_POSS 24U +# define KBCU_SCAN0_COLUMN3_POSE 30U +# define KBCU_SCAN0_COLUMN3_MSK BITS(KBCU_SCAN0_COLUMN3_POSS, KBCU_SCAN0_COLUMN3_POSE) +# define KBCU_SCAN0_COLUMN3 KBCU_SCAN0_COLUMN3_MSK + +# define KBCU_SCAN0_COLUMN2_POSS 16U +# define KBCU_SCAN0_COLUMN2_POSE 22U +# define KBCU_SCAN0_COLUMN2_MSK BITS(KBCU_SCAN0_COLUMN2_POSS, KBCU_SCAN0_COLUMN2_POSE) +# define KBCU_SCAN0_COLUMN2 KBCU_SCAN0_COLUMN2_MSK + +# define KBCU_SCAN0_COLUMN1_POSS 8U +# define KBCU_SCAN0_COLUMN1_POSE 14U +# define KBCU_SCAN0_COLUMN1_MSK BITS(KBCU_SCAN0_COLUMN1_POSS, KBCU_SCAN0_COLUMN1_POSE) +# define KBCU_SCAN0_COLUMN1 KBCU_SCAN0_COLUMN1_MSK + +# define KBCU_SCAN0_COLUMN0_POSS 0U +# define KBCU_SCAN0_COLUMN0_POSE 6U +# define KBCU_SCAN0_COLUMN0_MSK BITS(KBCU_SCAN0_COLUMN0_POSS, KBCU_SCAN0_COLUMN0_POSE) +# define KBCU_SCAN0_COLUMN0 KBCU_SCAN0_COLUMN0_MSK + +/****************** Bit definition for KBCU_SCAN1 register ************************/ + +# define KBCU_SCAN1_COLUMN7_POSS 24U +# define KBCU_SCAN1_COLUMN7_POSE 30U +# define KBCU_SCAN1_COLUMN7_MSK BITS(KBCU_SCAN1_COLUMN7_POSS, KBCU_SCAN1_COLUMN7_POSE) +# define KBCU_SCAN1_COLUMN7 KBCU_SCAN1_COLUMN7_MSK + +# define KBCU_SCAN1_COLUMN6_POSS 16U +# define KBCU_SCAN1_COLUMN6_POSE 22U +# define KBCU_SCAN1_COLUMN6_MSK BITS(KBCU_SCAN1_COLUMN6_POSS, KBCU_SCAN1_COLUMN6_POSE) +# define KBCU_SCAN1_COLUMN6 KBCU_SCAN1_COLUMN6_MSK + +# define KBCU_SCAN1_COLUMN5_POSS 8U +# define KBCU_SCAN1_COLUMN5_POSE 14U +# define KBCU_SCAN1_COLUMN5_MSK BITS(KBCU_SCAN1_COLUMN5_POSS, KBCU_SCAN1_COLUMN5_POSE) +# define KBCU_SCAN1_COLUMN5 KBCU_SCAN1_COLUMN5_MSK + +# define KBCU_SCAN1_COLUMN4_POSS 0U +# define KBCU_SCAN1_COLUMN4_POSE 6U +# define KBCU_SCAN1_COLUMN4_MSK BITS(KBCU_SCAN1_COLUMN4_POSS, KBCU_SCAN1_COLUMN4_POSE) +# define KBCU_SCAN1_COLUMN4 KBCU_SCAN1_COLUMN4_MSK + +/****************** Bit definition for KBCU_SCAN2 register ************************/ + +# define KBCU_SCAN2_COLUMN11_POSS 24U +# define KBCU_SCAN2_COLUMN11_POSE 30U +# define KBCU_SCAN2_COLUMN11_MSK BITS(KBCU_SCAN2_COLUMN11_POSS, KBCU_SCAN2_COLUMN11_POSE) +# define KBCU_SCAN2_COLUMN11 KBCU_SCAN2_COLUMN11_MSK + +# define KBCU_SCAN2_COLUMN10_POSS 16U +# define KBCU_SCAN2_COLUMN10_POSE 22U +# define KBCU_SCAN2_COLUMN10_MSK BITS(KBCU_SCAN2_COLUMN10_POSS, KBCU_SCAN2_COLUMN10_POSE) +# define KBCU_SCAN2_COLUMN10 KBCU_SCAN2_COLUMN10_MSK + +# define KBCU_SCAN2_COLUMN9_POSS 8U +# define KBCU_SCAN2_COLUMN9_POSE 14U +# define KBCU_SCAN2_COLUMN9_MSK BITS(KBCU_SCAN2_COLUMN9_POSS, KBCU_SCAN2_COLUMN9_POSE) +# define KBCU_SCAN2_COLUMN9 KBCU_SCAN2_COLUMN9_MSK + +# define KBCU_SCAN2_COLUMN8_POSS 0U +# define KBCU_SCAN2_COLUMN8_POSE 6U +# define KBCU_SCAN2_COLUMN8_MSK BITS(KBCU_SCAN2_COLUMN8_POSS, KBCU_SCAN2_COLUMN8_POSE) +# define KBCU_SCAN2_COLUMN8 KBCU_SCAN2_COLUMN8_MSK + +/****************** Bit definition for KBCU_SCAN3 register ************************/ + +# define KBCU_SCAN3_COLUMN15_POSS 24U +# define KBCU_SCAN3_COLUMN15_POSE 30U +# define KBCU_SCAN3_COLUMN15_MSK BITS(KBCU_SCAN3_COLUMN15_POSS, KBCU_SCAN3_COLUMN15_POSE) +# define KBCU_SCAN3_COLUMN15 KBCU_SCAN3_COLUMN15_MSK + +# define KBCU_SCAN3_COLUMN14_POSS 16U +# define KBCU_SCAN3_COLUMN14_POSE 22U +# define KBCU_SCAN3_COLUMN14_MSK BITS(KBCU_SCAN3_COLUMN14_POSS, KBCU_SCAN3_COLUMN14_POSE) +# define KBCU_SCAN3_COLUMN14 KBCU_SCAN3_COLUMN14_MSK + +# define KBCU_SCAN3_COLUMN13_POSS 8U +# define KBCU_SCAN3_COLUMN13_POSE 14U +# define KBCU_SCAN3_COLUMN13_MSK BITS(KBCU_SCAN3_COLUMN13_POSS, KBCU_SCAN3_COLUMN13_POSE) +# define KBCU_SCAN3_COLUMN13 KBCU_SCAN3_COLUMN13_MSK + +# define KBCU_SCAN3_COLUMN12_POSS 0U +# define KBCU_SCAN3_COLUMN12_POSE 6U +# define KBCU_SCAN3_COLUMN12_MSK BITS(KBCU_SCAN3_COLUMN12_POSS, KBCU_SCAN3_COLUMN12_POSE) +# define KBCU_SCAN3_COLUMN12 KBCU_SCAN3_COLUMN12_MSK + +/****************** Bit definition for KBCU_SCAN4 register ************************/ + +# define KBCU_SCAN4_COLUMN19_POSS 24U +# define KBCU_SCAN4_COLUMN19_POSE 30U +# define KBCU_SCAN4_COLUMN19_MSK BITS(KBCU_SCAN4_COLUMN19_POSS, KBCU_SCAN4_COLUMN19_POSE) +# define KBCU_SCAN4_COLUMN19 KBCU_SCAN4_COLUMN19_MSK + +# define KBCU_SCAN4_COLUMN18_POSS 16U +# define KBCU_SCAN4_COLUMN18_POSE 22U +# define KBCU_SCAN4_COLUMN18_MSK BITS(KBCU_SCAN4_COLUMN18_POSS, KBCU_SCAN4_COLUMN18_POSE) +# define KBCU_SCAN4_COLUMN18 KBCU_SCAN4_COLUMN18_MSK + +# define KBCU_SCAN4_COLUMN17_POSS 8U +# define KBCU_SCAN4_COLUMN17_POSE 14U +# define KBCU_SCAN4_COLUMN17_MSK BITS(KBCU_SCAN4_COLUMN17_POSS, KBCU_SCAN4_COLUMN17_POSE) +# define KBCU_SCAN4_COLUMN17 KBCU_SCAN4_COLUMN17_MSK + +# define KBCU_SCAN4_COLUMN16_POSS 0U +# define KBCU_SCAN4_COLUMN16_POSE 6U +# define KBCU_SCAN4_COLUMN16_MSK BITS(KBCU_SCAN4_COLUMN16_POSS, KBCU_SCAN4_COLUMN16_POSE) +# define KBCU_SCAN4_COLUMN16 KBCU_SCAN4_COLUMN16_MSK + +/****************** Bit definition for KBCU_SCAN5 register ************************/ + +# define KBCU_SCAN5_COLUMN23_POSS 24U +# define KBCU_SCAN5_COLUMN23_POSE 30U +# define KBCU_SCAN5_COLUMN23_MSK BITS(KBCU_SCAN5_COLUMN23_POSS, KBCU_SCAN5_COLUMN23_POSE) +# define KBCU_SCAN5_COLUMN23 KBCU_SCAN5_COLUMN23_MSK + +# define KBCU_SCAN5_COLUMN22_POSS 16U +# define KBCU_SCAN5_COLUMN22_POSE 22U +# define KBCU_SCAN5_COLUMN22_MSK BITS(KBCU_SCAN5_COLUMN22_POSS, KBCU_SCAN5_COLUMN22_POSE) +# define KBCU_SCAN5_COLUMN22 KBCU_SCAN5_COLUMN22_MSK + +# define KBCU_SCAN5_COLUMN21_POSS 8U +# define KBCU_SCAN5_COLUMN21_POSE 14U +# define KBCU_SCAN5_COLUMN21_MSK BITS(KBCU_SCAN5_COLUMN21_POSS, KBCU_SCAN5_COLUMN21_POSE) +# define KBCU_SCAN5_COLUMN21 KBCU_SCAN5_COLUMN21_MSK + +# define KBCU_SCAN5_COLUMN20_POSS 0U +# define KBCU_SCAN5_COLUMN20_POSE 6U +# define KBCU_SCAN5_COLUMN20_MSK BITS(KBCU_SCAN5_COLUMN20_POSS, KBCU_SCAN5_COLUMN20_POSE) +# define KBCU_SCAN5_COLUMN20 KBCU_SCAN5_COLUMN20_MSK + +/****************** Bit definition for KBCU_STAT register ************************/ + +# define KBCU_STAT_COLUMN_POSS 0U +# define KBCU_STAT_COLUMN_POSE 23U +# define KBCU_STAT_COLUMN_MSK BITS(KBCU_STAT_COLUMN_POSS, KBCU_STAT_COLUMN_POSE) +# define KBCU_STAT_COLUMN KBCU_STAT_COLUMN_MSK + +/****************** Bit definition for KBCU_LED0 register ************************/ + +# define KBCU_LED0_MASK_POSS 27U +# define KBCU_LED0_MASK_POSE 31U +# define KBCU_LED0_MASK_MSK BITS(KBCU_LED0_MASK_POSS, KBCU_LED0_MASK_POSE) +# define KBCU_LED0_MASK KBCU_LED0_MASK_MSK + +# define KBCU_LED0_DUTY2_H_POS 26U +# define KBCU_LED0_DUTY2_H_MSK BIT(KBCU_LED0_DUTY2_H_POS) +# define KBCU_LED0_DUTY2_H KBCU_LED0_DUTY2_H_MSK + +# define KBCU_LED0_DUTY1_H_POS 25U +# define KBCU_LED0_DUTY1_H_MSK BIT(KBCU_LED0_DUTY1_H_POS) +# define KBCU_LED0_DUTY1_H KBCU_LED0_DUTY1_H_MSK + +# define KBCU_LED0_DUTY0_H_POS 24U +# define KBCU_LED0_DUTY0_H_MSK BIT(KBCU_LED0_DUTY0_H_POS) +# define KBCU_LED0_DUTY0_H KBCU_LED0_DUTY0_H_MSK + +# define KBCU_LED0_DUTY2_POSS 16U +# define KBCU_LED0_DUTY2_POSE 23U +# define KBCU_LED0_DUTY2_MSK BITS(KBCU_LED0_DUTY2_POSS, KBCU_LED0_DUTY2_POSE) +# define KBCU_LED0_DUTY2 KBCU_LED0_DUTY2_MSK + +# define KBCU_LED0_DUTY1_POSS 8U +# define KBCU_LED0_DUTY1_POSE 15U +# define KBCU_LED0_DUTY1_MSK BITS(KBCU_LED0_DUTY1_POSS, KBCU_LED0_DUTY1_POSE) +# define KBCU_LED0_DUTY1 KBCU_LED0_DUTY1_MSK + +# define KBCU_LED0_DUTY0_POSS 0U +# define KBCU_LED0_DUTY0_POSE 7U +# define KBCU_LED0_DUTY0_MSK BITS(KBCU_LED0_DUTY0_POSS, KBCU_LED0_DUTY0_POSE) +# define KBCU_LED0_DUTY0 KBCU_LED0_DUTY0_MSK + +/****************** Bit definition for KBCU_LED1 register ************************/ + +# define KBCU_LED1_MASK_POSS 27U +# define KBCU_LED1_MASK_POSE 31U +# define KBCU_LED1_MASK_MSK BITS(KBCU_LED1_MASK_POSS, KBCU_LED1_MASK_POSE) +# define KBCU_LED1_MASK KBCU_LED1_MASK_MSK + +# define KBCU_LED1_DUTY2_H_POS 26U +# define KBCU_LED1_DUTY2_H_MSK BIT(KBCU_LED1_DUTY2_H_POS) +# define KBCU_LED1_DUTY2_H KBCU_LED1_DUTY2_H_MSK + +# define KBCU_LED1_DUTY1_H_POS 25U +# define KBCU_LED1_DUTY1_H_MSK BIT(KBCU_LED1_DUTY1_H_POS) +# define KBCU_LED1_DUTY1_H KBCU_LED1_DUTY1_H_MSK + +# define KBCU_LED1_DUTY0_H_POS 24U +# define KBCU_LED1_DUTY0_H_MSK BIT(KBCU_LED1_DUTY0_H_POS) +# define KBCU_LED1_DUTY0_H KBCU_LED1_DUTY0_H_MSK + +# define KBCU_LED1_DUTY2_POSS 16U +# define KBCU_LED1_DUTY2_POSE 23U +# define KBCU_LED1_DUTY2_MSK BITS(KBCU_LED1_DUTY2_POSS, KBCU_LED1_DUTY2_POSE) +# define KBCU_LED1_DUTY2 KBCU_LED1_DUTY2_MSK + +# define KBCU_LED1_DUTY1_POSS 8U +# define KBCU_LED1_DUTY1_POSE 15U +# define KBCU_LED1_DUTY1_MSK BITS(KBCU_LED1_DUTY1_POSS, KBCU_LED1_DUTY1_POSE) +# define KBCU_LED1_DUTY1 KBCU_LED1_DUTY1_MSK + +# define KBCU_LED1_DUTY0_POSS 0U +# define KBCU_LED1_DUTY0_POSE 7U +# define KBCU_LED1_DUTY0_MSK BITS(KBCU_LED1_DUTY0_POSS, KBCU_LED1_DUTY0_POSE) +# define KBCU_LED1_DUTY0 KBCU_LED1_DUTY0_MSK + +/****************** Bit definition for KBCU_LED2 register ************************/ + +# define KBCU_LED2_MASK_POSS 27U +# define KBCU_LED2_MASK_POSE 31U +# define KBCU_LED2_MASK_MSK BITS(KBCU_LED2_MASK_POSS, KBCU_LED2_MASK_POSE) +# define KBCU_LED2_MASK KBCU_LED2_MASK_MSK + +# define KBCU_LED2_DUTY2_H_POS 26U +# define KBCU_LED2_DUTY2_H_MSK BIT(KBCU_LED2_DUTY2_H_POS) +# define KBCU_LED2_DUTY2_H KBCU_LED2_DUTY2_H_MSK + +# define KBCU_LED2_DUTY1_H_POS 25U +# define KBCU_LED2_DUTY1_H_MSK BIT(KBCU_LED2_DUTY1_H_POS) +# define KBCU_LED2_DUTY1_H KBCU_LED2_DUTY1_H_MSK + +# define KBCU_LED2_DUTY0_H_POS 24U +# define KBCU_LED2_DUTY0_H_MSK BIT(KBCU_LED2_DUTY0_H_POS) +# define KBCU_LED2_DUTY0_H KBCU_LED2_DUTY0_H_MSK + +# define KBCU_LED2_DUTY2_POSS 16U +# define KBCU_LED2_DUTY2_POSE 23U +# define KBCU_LED2_DUTY2_MSK BITS(KBCU_LED2_DUTY2_POSS, KBCU_LED2_DUTY2_POSE) +# define KBCU_LED2_DUTY2 KBCU_LED2_DUTY2_MSK + +# define KBCU_LED2_DUTY1_POSS 8U +# define KBCU_LED2_DUTY1_POSE 15U +# define KBCU_LED2_DUTY1_MSK BITS(KBCU_LED2_DUTY1_POSS, KBCU_LED2_DUTY1_POSE) +# define KBCU_LED2_DUTY1 KBCU_LED2_DUTY1_MSK + +# define KBCU_LED2_DUTY0_POSS 0U +# define KBCU_LED2_DUTY0_POSE 7U +# define KBCU_LED2_DUTY0_MSK BITS(KBCU_LED2_DUTY0_POSS, KBCU_LED2_DUTY0_POSE) +# define KBCU_LED2_DUTY0 KBCU_LED2_DUTY0_MSK + +/****************** Bit definition for KBCU_LED3 register ************************/ + +# define KBCU_LED3_MASK_POSS 27U +# define KBCU_LED3_MASK_POSE 31U +# define KBCU_LED3_MASK_MSK BITS(KBCU_LED3_MASK_POSS, KBCU_LED3_MASK_POSE) +# define KBCU_LED3_MASK KBCU_LED3_MASK_MSK + +# define KBCU_LED3_DUTY2_H_POS 26U +# define KBCU_LED3_DUTY2_H_MSK BIT(KBCU_LED3_DUTY2_H_POS) +# define KBCU_LED3_DUTY2_H KBCU_LED3_DUTY2_H_MSK + +# define KBCU_LED3_DUTY1_H_POS 25U +# define KBCU_LED3_DUTY1_H_MSK BIT(KBCU_LED3_DUTY1_H_POS) +# define KBCU_LED3_DUTY1_H KBCU_LED3_DUTY1_H_MSK + +# define KBCU_LED3_DUTY0_H_POS 24U +# define KBCU_LED3_DUTY0_H_MSK BIT(KBCU_LED3_DUTY0_H_POS) +# define KBCU_LED3_DUTY0_H KBCU_LED3_DUTY0_H_MSK + +# define KBCU_LED3_DUTY2_POSS 16U +# define KBCU_LED3_DUTY2_POSE 23U +# define KBCU_LED3_DUTY2_MSK BITS(KBCU_LED3_DUTY2_POSS, KBCU_LED3_DUTY2_POSE) +# define KBCU_LED3_DUTY2 KBCU_LED3_DUTY2_MSK + +# define KBCU_LED3_DUTY1_POSS 8U +# define KBCU_LED3_DUTY1_POSE 15U +# define KBCU_LED3_DUTY1_MSK BITS(KBCU_LED3_DUTY1_POSS, KBCU_LED3_DUTY1_POSE) +# define KBCU_LED3_DUTY1 KBCU_LED3_DUTY1_MSK + +# define KBCU_LED3_DUTY0_POSS 0U +# define KBCU_LED3_DUTY0_POSE 7U +# define KBCU_LED3_DUTY0_MSK BITS(KBCU_LED3_DUTY0_POSS, KBCU_LED3_DUTY0_POSE) +# define KBCU_LED3_DUTY0 KBCU_LED3_DUTY0_MSK + +/****************** Bit definition for KBCU_LED4 register ************************/ + +# define KBCU_LED4_MASK_POSS 27U +# define KBCU_LED4_MASK_POSE 31U +# define KBCU_LED4_MASK_MSK BITS(KBCU_LED4_MASK_POSS, KBCU_LED4_MASK_POSE) +# define KBCU_LED4_MASK KBCU_LED4_MASK_MSK + +# define KBCU_LED4_DUTY2_H_POS 26U +# define KBCU_LED4_DUTY2_H_MSK BIT(KBCU_LED4_DUTY2_H_POS) +# define KBCU_LED4_DUTY2_H KBCU_LED4_DUTY2_H_MSK + +# define KBCU_LED4_DUTY1_H_POS 25U +# define KBCU_LED4_DUTY1_H_MSK BIT(KBCU_LED4_DUTY1_H_POS) +# define KBCU_LED4_DUTY1_H KBCU_LED4_DUTY1_H_MSK + +# define KBCU_LED4_DUTY0_H_POS 24U +# define KBCU_LED4_DUTY0_H_MSK BIT(KBCU_LED4_DUTY0_H_POS) +# define KBCU_LED4_DUTY0_H KBCU_LED4_DUTY0_H_MSK + +# define KBCU_LED4_DUTY2_POSS 16U +# define KBCU_LED4_DUTY2_POSE 23U +# define KBCU_LED4_DUTY2_MSK BITS(KBCU_LED4_DUTY2_POSS, KBCU_LED4_DUTY2_POSE) +# define KBCU_LED4_DUTY2 KBCU_LED4_DUTY2_MSK + +# define KBCU_LED4_DUTY1_POSS 8U +# define KBCU_LED4_DUTY1_POSE 15U +# define KBCU_LED4_DUTY1_MSK BITS(KBCU_LED4_DUTY1_POSS, KBCU_LED4_DUTY1_POSE) +# define KBCU_LED4_DUTY1 KBCU_LED4_DUTY1_MSK + +# define KBCU_LED4_DUTY0_POSS 0U +# define KBCU_LED4_DUTY0_POSE 7U +# define KBCU_LED4_DUTY0_MSK BITS(KBCU_LED4_DUTY0_POSS, KBCU_LED4_DUTY0_POSE) +# define KBCU_LED4_DUTY0 KBCU_LED4_DUTY0_MSK + +/****************** Bit definition for KBCU_LED5 register ************************/ + +# define KBCU_LED5_MASK_POSS 27U +# define KBCU_LED5_MASK_POSE 31U +# define KBCU_LED5_MASK_MSK BITS(KBCU_LED5_MASK_POSS, KBCU_LED5_MASK_POSE) +# define KBCU_LED5_MASK KBCU_LED5_MASK_MSK + +# define KBCU_LED5_DUTY2_H_POS 26U +# define KBCU_LED5_DUTY2_H_MSK BIT(KBCU_LED5_DUTY2_H_POS) +# define KBCU_LED5_DUTY2_H KBCU_LED5_DUTY2_H_MSK + +# define KBCU_LED5_DUTY1_H_POS 25U +# define KBCU_LED5_DUTY1_H_MSK BIT(KBCU_LED5_DUTY1_H_POS) +# define KBCU_LED5_DUTY1_H KBCU_LED5_DUTY1_H_MSK + +# define KBCU_LED5_DUTY0_H_POS 24U +# define KBCU_LED5_DUTY0_H_MSK BIT(KBCU_LED5_DUTY0_H_POS) +# define KBCU_LED5_DUTY0_H KBCU_LED5_DUTY0_H_MSK + +# define KBCU_LED5_DUTY2_POSS 16U +# define KBCU_LED5_DUTY2_POSE 23U +# define KBCU_LED5_DUTY2_MSK BITS(KBCU_LED5_DUTY2_POSS, KBCU_LED5_DUTY2_POSE) +# define KBCU_LED5_DUTY2 KBCU_LED5_DUTY2_MSK + +# define KBCU_LED5_DUTY1_POSS 8U +# define KBCU_LED5_DUTY1_POSE 15U +# define KBCU_LED5_DUTY1_MSK BITS(KBCU_LED5_DUTY1_POSS, KBCU_LED5_DUTY1_POSE) +# define KBCU_LED5_DUTY1 KBCU_LED5_DUTY1_MSK + +# define KBCU_LED5_DUTY0_POSS 0U +# define KBCU_LED5_DUTY0_POSE 7U +# define KBCU_LED5_DUTY0_MSK BITS(KBCU_LED5_DUTY0_POSS, KBCU_LED5_DUTY0_POSE) +# define KBCU_LED5_DUTY0 KBCU_LED5_DUTY0_MSK + +/****************** Bit definition for KBCU_LED6 register ************************/ + +# define KBCU_LED6_MASK_POSS 27U +# define KBCU_LED6_MASK_POSE 31U +# define KBCU_LED6_MASK_MSK BITS(KBCU_LED6_MASK_POSS, KBCU_LED6_MASK_POSE) +# define KBCU_LED6_MASK KBCU_LED6_MASK_MSK + +# define KBCU_LED6_DUTY2_H_POS 26U +# define KBCU_LED6_DUTY2_H_MSK BIT(KBCU_LED6_DUTY2_H_POS) +# define KBCU_LED6_DUTY2_H KBCU_LED6_DUTY2_H_MSK + +# define KBCU_LED6_DUTY1_H_POS 25U +# define KBCU_LED6_DUTY1_H_MSK BIT(KBCU_LED6_DUTY1_H_POS) +# define KBCU_LED6_DUTY1_H KBCU_LED6_DUTY1_H_MSK + +# define KBCU_LED6_DUTY0_H_POS 24U +# define KBCU_LED6_DUTY0_H_MSK BIT(KBCU_LED6_DUTY0_H_POS) +# define KBCU_LED6_DUTY0_H KBCU_LED6_DUTY0_H_MSK + +# define KBCU_LED6_DUTY2_POSS 16U +# define KBCU_LED6_DUTY2_POSE 23U +# define KBCU_LED6_DUTY2_MSK BITS(KBCU_LED6_DUTY2_POSS, KBCU_LED6_DUTY2_POSE) +# define KBCU_LED6_DUTY2 KBCU_LED6_DUTY2_MSK + +# define KBCU_LED6_DUTY1_POSS 8U +# define KBCU_LED6_DUTY1_POSE 15U +# define KBCU_LED6_DUTY1_MSK BITS(KBCU_LED6_DUTY1_POSS, KBCU_LED6_DUTY1_POSE) +# define KBCU_LED6_DUTY1 KBCU_LED6_DUTY1_MSK + +# define KBCU_LED6_DUTY0_POSS 0U +# define KBCU_LED6_DUTY0_POSE 7U +# define KBCU_LED6_DUTY0_MSK BITS(KBCU_LED6_DUTY0_POSS, KBCU_LED6_DUTY0_POSE) +# define KBCU_LED6_DUTY0 KBCU_LED6_DUTY0_MSK + +typedef struct +{ + __O uint32_t IER; // 0x000 + __O uint32_t IDR; // 0x004 + __I uint32_t IVS; // 0x008 + __I uint32_t RIF; // 0x00c + __I uint32_t IFM; // 0x010 + __O uint32_t ICR; // 0x014 + __IO uint32_t CON1; // 0x018 + __IO uint32_t CON2; // 0x01c + __I uint32_t SCAN0; // 0x020 + __I uint32_t SCAN1; // 0x024 + __I uint32_t SCAN2; // 0x028 + __I uint32_t SCAN3; // 0x02c + __I uint32_t SCAN4; // 0x030 + __I uint32_t SCAN5; // 0x034 + __I uint32_t STAT; // 0x038 + __IO uint32_t RESERVED0; // 0x03c + __IO uint32_t LED0; // 0x040 + __IO uint32_t LED1; // 0x044 + __IO uint32_t LED2; // 0x048 + __IO uint32_t LED3; // 0x04c + __IO uint32_t LED4; // 0x050 + __IO uint32_t LED5; // 0x054 + __IO uint32_t LED6; // 0x058 +} KBCU_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_mswd.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_mswd.h new file mode 100644 index 00000000000..d1b69e2d94f --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_mswd.h @@ -0,0 +1,217 @@ +/********************************************************************************** + * + * @file reg_mswd.h + * @brief MSWD Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MSWD_H__ +#define __MSWD_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +////#pragma anon_unions + +/****************** Bit definition for MSWD_CFG register ************************/ + +# define MSWD_CFG_RTSPA_POSS 22U +# define MSWD_CFG_RTSPA_POSE 31U +# define MSWD_CFG_RTSPA_MSK BITS(MSWD_CFG_RTSPA_POSS, MSWD_CFG_RTSPA_POSE) + +# define MSWD_CFG_RETRY_POSS 9U +# define MSWD_CFG_RETRY_POSE 21U +# define MSWD_CFG_RETRY_MSK BITS(MSWD_CFG_RETRY_POSS, MSWD_CFG_RETRY_POSE) + +# define MSWD_CFG_DOCP_POS 8U +# define MSWD_CFG_DOCP_MSK BIT(MSWD_CFG_DOCP_POS) + +# define MSWD_CFG_DAWC_POSS 6U +# define MSWD_CFG_DAWC_POSE 7U +# define MSWD_CFG_DAWC_MSK BITS(MSWD_CFG_DAWC_POSS, MSWD_CFG_DAWC_POSE) + +# define MSWD_CFG_DHAC_POSS 4U +# define MSWD_CFG_DHAC_POSE 5U +# define MSWD_CFG_DHAC_MSK BITS(MSWD_CFG_DHAC_POSS, MSWD_CFG_DHAC_POSE) + +# define MSWD_CFG_FREQ_POSS 0U +# define MSWD_CFG_FREQ_POSE 3U +# define MSWD_CFG_FREQ_MSK BITS(MSWD_CFG_FREQ_POSS, MSWD_CFG_FREQ_POSE) + +/****************** Bit definition for MSWD_JTAG2SWD register ************************/ + +# define MSWD_JTAG2SWD_JTAG2SWD_POSS 0U +# define MSWD_JTAG2SWD_JTAG2SWD_POSE 31U +# define MSWD_JTAG2SWD_JTAG2SWD_MSK BITS(MSWD_JTAG2SWD_JTAG2SWD_POSS, MSWD_JTAG2SWD_JTAG2SWD_POSE) + +/****************** Bit definition for MSWD_LINERESET register ************************/ + +# define MSWD_LINERESET_LINERESET_POSS 0U +# define MSWD_LINERESET_LINERESET_POSE 31U +# define MSWD_LINERESET_LINERESET_MSK BITS(MSWD_LINERESET_LINERESET_POSS, MSWD_LINERESET_LINERESET_POSE) + +/****************** Bit definition for MSWD_STS register ************************/ + +# define MSWD_STS_PARITY_POS 3U +# define MSWD_STS_PARITY_MSK BIT(MSWD_STS_PARITY_POS) + +# define MSWD_STS_ACK_POSS 0U +# define MSWD_STS_ACK_POSE 2U +# define MSWD_STS_ACK_MSK BITS(MSWD_STS_ACK_POSS, MSWD_STS_ACK_POSE) + +/****************** Bit definition for MSWD_DP_IDR_ABORT register ************************/ + +# define MSWD_DP_IDR_ABORT_DP_IDR_ABORT_POSS 0U +# define MSWD_DP_IDR_ABORT_DP_IDR_ABORT_POSE 31U +# define MSWD_DP_IDR_ABORT_DP_IDR_ABORT_MSK BITS(MSWD_DP_IDR_ABORT_DP_IDR_ABORT_POSS, MSWD_DP_IDR_ABORT_DP_IDR_ABORT_POSE) + +/****************** Bit definition for MSWD_DP_CSR_WCR register ************************/ + +# define MSWD_DP_CSR_WCR_DP_CSR_WCR_POSS 0U +# define MSWD_DP_CSR_WCR_DP_CSR_WCR_POSE 31U +# define MSWD_DP_CSR_WCR_DP_CSR_WCR_MSK BITS(MSWD_DP_CSR_WCR_DP_CSR_WCR_POSS, MSWD_DP_CSR_WCR_DP_CSR_WCR_POSE) + +/****************** Bit definition for MSWD_DP_RESEND_SELECT register ************************/ + +# define MSWD_DP_RESEND_SELECT_DP_RESEND_SELECT_POSS 0U +# define MSWD_DP_RESEND_SELECT_DP_RESEND_SELECT_POSE 31U +# define MSWD_DP_RESEND_SELECT_DP_RESEND_SELECT_MSK BITS(MSWD_DP_RESEND_SELECT_DP_RESEND_SELECT_POSS, MSWD_DP_RESEND_SELECT_DP_RESEND_SELECT_POSE) + +/****************** Bit definition for MSWD_DP_RDBUF_ROUTESEL register ************************/ + +# define MSWD_DP_RDBUF_ROUTESEL_DP_RDBUF_ROUTESEL_POSS 0U +# define MSWD_DP_RDBUF_ROUTESEL_DP_RDBUF_ROUTESEL_POSE 31U +# define MSWD_DP_RDBUF_ROUTESEL_DP_RDBUF_ROUTESEL_MSK BITS(MSWD_DP_RDBUF_ROUTESEL_DP_RDBUF_ROUTESEL_POSS, MSWD_DP_RDBUF_ROUTESEL_DP_RDBUF_ROUTESEL_POSE) + +/****************** Bit definition for MSWD_AP_CSW register ************************/ + +# define MSWD_AP_CSW_AP_CSW_POSS 0U +# define MSWD_AP_CSW_AP_CSW_POSE 31U +# define MSWD_AP_CSW_AP_CSW_MSK BITS(MSWD_AP_CSW_AP_CSW_POSS, MSWD_AP_CSW_AP_CSW_POSE) + +/****************** Bit definition for MSWD_AP_TAR register ************************/ + +# define MSWD_AP_TAR_AP_TAR_POSS 0U +# define MSWD_AP_TAR_AP_TAR_POSE 31U +# define MSWD_AP_TAR_AP_TAR_MSK BITS(MSWD_AP_TAR_AP_TAR_POSS, MSWD_AP_TAR_AP_TAR_POSE) + +/****************** Bit definition for MSWD_AP_DRW register ************************/ + +# define MSWD_AP_DRW_AP_DRW_POSS 0U +# define MSWD_AP_DRW_AP_DRW_POSE 31U +# define MSWD_AP_DRW_AP_DRW_MSK BITS(MSWD_AP_DRW_AP_DRW_POSS, MSWD_AP_DRW_AP_DRW_POSE) + +/****************** Bit definition for MSWD_AP_BD0 register ************************/ + +# define MSWD_AP_BD0_AP_BD0_POSS 0U +# define MSWD_AP_BD0_AP_BD0_POSE 31U +# define MSWD_AP_BD0_AP_BD0_MSK BITS(MSWD_AP_BD0_AP_BD0_POSS, MSWD_AP_BD0_AP_BD0_POSE) + +/****************** Bit definition for MSWD_AP_BD1 register ************************/ + +# define MSWD_AP_BD1_AP_BD1_POSS 0U +# define MSWD_AP_BD1_AP_BD1_POSE 31U +# define MSWD_AP_BD1_AP_BD1_MSK BITS(MSWD_AP_BD1_AP_BD1_POSS, MSWD_AP_BD1_AP_BD1_POSE) + +/****************** Bit definition for MSWD_AP_BD2 register ************************/ + +# define MSWD_AP_BD2_AP_BD2_POSS 0U +# define MSWD_AP_BD2_AP_BD2_POSE 31U +# define MSWD_AP_BD2_AP_BD2_MSK BITS(MSWD_AP_BD2_AP_BD2_POSS, MSWD_AP_BD2_AP_BD2_POSE) + +/****************** Bit definition for MSWD_AP_BD3 register ************************/ + +# define MSWD_AP_BD3_AP_BD3_POSS 0U +# define MSWD_AP_BD3_AP_BD3_POSE 31U +# define MSWD_AP_BD3_AP_BD3_MSK BITS(MSWD_AP_BD3_AP_BD3_POSS, MSWD_AP_BD3_AP_BD3_POSE) + +/****************** Bit definition for MSWD_AP_CFG register ************************/ + +# define MSWD_AP_CFG_AP_CFG_POSS 0U +# define MSWD_AP_CFG_AP_CFG_POSE 31U +# define MSWD_AP_CFG_AP_CFG_MSK BITS(MSWD_AP_CFG_AP_CFG_POSS, MSWD_AP_CFG_AP_CFG_POSE) + +/****************** Bit definition for MSWD_AP_BASE register ************************/ + +# define MSWD_AP_BASE_AP_BASE_POSS 0U +# define MSWD_AP_BASE_AP_BASE_POSE 31U +# define MSWD_AP_BASE_AP_BASE_MSK BITS(MSWD_AP_BASE_AP_BASE_POSS, MSWD_AP_BASE_AP_BASE_POSE) + +/****************** Bit definition for MSWD_AP_IDR register ************************/ + +# define MSWD_AP_IDR_AP_IDR_POSS 0U +# define MSWD_AP_IDR_AP_IDR_POSE 31U +# define MSWD_AP_IDR_AP_IDR_MSK BITS(MSWD_AP_IDR_AP_IDR_POSS, MSWD_AP_IDR_AP_IDR_POSE) + +/****************** Bit definition for MSWD_ISP_CMD register ************************/ + +# define MSWD_ISP_CMD_ISP_CMD_POSS 0U +# define MSWD_ISP_CMD_ISP_CMD_POSE 7U +# define MSWD_ISP_CMD_ISP_CMD_MSK BITS(MSWD_ISP_CMD_ISP_CMD_POSS, MSWD_ISP_CMD_ISP_CMD_POSE) + +/****************** Bit definition for MSWD_ISP_DAT register ************************/ + +# define MSWD_ISP_DAT_ISP_DAT_POSS 0U +# define MSWD_ISP_DAT_ISP_DAT_POSE 31U +# define MSWD_ISP_DAT_ISP_DAT_MSK BITS(MSWD_ISP_DAT_ISP_DAT_POSS, MSWD_ISP_DAT_ISP_DAT_POSE) + +/****************** Bit definition for MSWD_ISP_CFG register ************************/ + +# define MSWD_ISP_CFG_ISP_GCKOI_POS 0U +# define MSWD_ISP_CFG_ISP_GCKOI_MSK BIT(MSWD_ISP_CFG_ISP_GCKOI_POS) + +typedef struct +{ + __IO uint32_t CFG; // 0x000 + __IO uint32_t JTAG2SWD; // 0x004 + __IO uint32_t LINERESET; // 0x008 + __I uint32_t STS; // 0x00c + __IO uint32_t DP_IDR_ABORT; // 0x010 + __IO uint32_t DP_CSR_WCR; // 0x014 + __IO uint32_t DP_RESEND_SELECT; // 0x018 + __IO uint32_t DP_RDBUF_ROUTESEL; // 0x01c + __IO uint32_t AP_CSW; // 0x020 + __IO uint32_t AP_TAR; // 0x024 + __IO uint32_t AP_DRW; // 0x028 + __IO uint32_t AP_BD0; // 0x02c + __IO uint32_t AP_BD1; // 0x030 + __IO uint32_t AP_BD2; // 0x034 + __IO uint32_t AP_BD3; // 0x038 + __IO uint32_t AP_CFG; // 0x03c + __IO uint32_t AP_BASE; // 0x040 + __IO uint32_t AP_IDR; // 0x044 + __IO uint32_t RESERVED0[2]; // 0x048-0x04c + __IO uint32_t ISP_CMD; // 0x050 + __IO uint32_t ISP_DAT; // 0x054 + __IO uint32_t ISP_CFG; // 0x058 +} MSWD_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_rcu.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_rcu.h new file mode 100644 index 00000000000..82c6e46f71a --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_rcu.h @@ -0,0 +1,905 @@ +/********************************************************************************** + * + * @file reg_rcu.h + * @brief RCU Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __RCU_H__ +#define __RCU_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + +/****************** Bit definition for RCU_CON register ************************/ + +# define RCU_CON_CSSON_POS 24U +# define RCU_CON_CSSON_MSK BIT(RCU_CON_CSSON_POS) +# define RCU_CON_CSSON RCU_CON_CSSON_MSK + +# define RCU_CON_PLL0RDY_POS 21U +# define RCU_CON_PLL0RDY_MSK BIT(RCU_CON_PLL0RDY_POS) +# define RCU_CON_PLL0RDY RCU_CON_PLL0RDY_MSK + +# define RCU_CON_PLL0ON_POS 20U +# define RCU_CON_PLL0ON_MSK BIT(RCU_CON_PLL0ON_POS) +# define RCU_CON_PLL0ON RCU_CON_PLL0ON_MSK + +# define RCU_CON_HRC48RDY_POS 17U +# define RCU_CON_HRC48RDY_MSK BIT(RCU_CON_HRC48RDY_POS) +# define RCU_CON_HRC48RDY RCU_CON_HRC48RDY_MSK + +# define RCU_CON_HRC48ON_POS 16U +# define RCU_CON_HRC48ON_MSK BIT(RCU_CON_HRC48ON_POS) +# define RCU_CON_HRC48ON RCU_CON_HRC48ON_MSK + +# define RCU_CON_HOSCBYP_POS 6U +# define RCU_CON_HOSCBYP_MSK BIT(RCU_CON_HOSCBYP_POS) +# define RCU_CON_HOSCBYP RCU_CON_HOSCBYP_MSK + +# define RCU_CON_HOSCRDY_POS 5U +# define RCU_CON_HOSCRDY_MSK BIT(RCU_CON_HOSCRDY_POS) +# define RCU_CON_HOSCRDY RCU_CON_HOSCRDY_MSK + +# define RCU_CON_HOSCON_POS 4U +# define RCU_CON_HOSCON_MSK BIT(RCU_CON_HOSCON_POS) +# define RCU_CON_HOSCON RCU_CON_HOSCON_MSK + +# define RCU_CON_HRCRDY_POS 1U +# define RCU_CON_HRCRDY_MSK BIT(RCU_CON_HRCRDY_POS) +# define RCU_CON_HRCRDY RCU_CON_HRCRDY_MSK + +# define RCU_CON_HRCON_POS 0U +# define RCU_CON_HRCON_MSK BIT(RCU_CON_HRCON_POS) +# define RCU_CON_HRCON RCU_CON_HRCON_MSK + +/****************** Bit definition for RCU_CFG register ************************/ + +# define RCU_CFG_MPRE_POSS 28U +# define RCU_CFG_MPRE_POSE 30U +# define RCU_CFG_MPRE_MSK BITS(RCU_CFG_MPRE_POSS, RCU_CFG_MPRE_POSE) +# define RCU_CFG_MPRE RCU_CFG_MPRE_MSK + +# define RCU_CFG_MSW_POSS 24U +# define RCU_CFG_MSW_POSE 27U +# define RCU_CFG_MSW_MSK BITS(RCU_CFG_MSW_POSS, RCU_CFG_MSW_POSE) +# define RCU_CFG_MSW RCU_CFG_MSW_MSK + +# define RCU_CFG_PLLSRC_POSS 20U +# define RCU_CFG_PLLSRC_POSE 21U +# define RCU_CFG_PLLSRC_MSK BITS(RCU_CFG_PLLSRC_POSS, RCU_CFG_PLLSRC_POSE) +# define RCU_CFG_PLLSRC RCU_CFG_PLLSRC_MSK + +# define RCU_CFG_PREDIV_POSS 16U +# define RCU_CFG_PREDIV_POSE 19U +# define RCU_CFG_PREDIV_MSK BITS(RCU_CFG_PREDIV_POSS, RCU_CFG_PREDIV_POSE) +# define RCU_CFG_PREDIV RCU_CFG_PREDIV_MSK + +# define RCU_CFG_PPRE_POSS 12U +# define RCU_CFG_PPRE_POSE 14U +# define RCU_CFG_PPRE_MSK BITS(RCU_CFG_PPRE_POSS, RCU_CFG_PPRE_POSE) +# define RCU_CFG_PPRE RCU_CFG_PPRE_MSK + +# define RCU_CFG_HPRE_POSS 8U +# define RCU_CFG_HPRE_POSE 11U +# define RCU_CFG_HPRE_MSK BITS(RCU_CFG_HPRE_POSS, RCU_CFG_HPRE_POSE) +# define RCU_CFG_HPRE RCU_CFG_HPRE_MSK + +# define RCU_CFG_SWS_POSS 3U +# define RCU_CFG_SWS_POSE 5U +# define RCU_CFG_SWS_MSK BITS(RCU_CFG_SWS_POSS, RCU_CFG_SWS_POSE) +# define RCU_CFG_SWS RCU_CFG_SWS_MSK + +# define RCU_CFG_SW_POSS 0U +# define RCU_CFG_SW_POSE 2U +# define RCU_CFG_SW_MSK BITS(RCU_CFG_SW_POSS, RCU_CFG_SW_POSE) +# define RCU_CFG_SW RCU_CFG_SW_MSK + +/****************** Bit definition for RCU_PLL0 register ************************/ + +# define RCU_PLL0_FK_POSS 12U +# define RCU_PLL0_FK_POSE 30U +# define RCU_PLL0_FK_MSK BITS(RCU_PLL0_FK_POSS, RCU_PLL0_FK_POSE) +# define RCU_PLL0_FK RCU_PLL0_FK_MSK + +# define RCU_PLL0_FN_POSS 4U +# define RCU_PLL0_FN_POSE 11U +# define RCU_PLL0_FN_MSK BITS(RCU_PLL0_FN_POSS, RCU_PLL0_FN_POSE) +# define RCU_PLL0_FN RCU_PLL0_FN_MSK + +# define RCU_PLL0_FM_POSS 0U +# define RCU_PLL0_FM_POSE 1U +# define RCU_PLL0_FM_MSK BITS(RCU_PLL0_FM_POSS, RCU_PLL0_FM_POSE) +# define RCU_PLL0_FM RCU_PLL0_FM_MSK + +/****************** Bit definition for RCU_CFG2 register ************************/ + +# define RCU_CFG2_SYSFREQ_POSS 8U +# define RCU_CFG2_SYSFREQ_POSE 15U +# define RCU_CFG2_SYSFREQ_MSK BITS(RCU_CFG2_SYSFREQ_POSS, RCU_CFG2_SYSFREQ_POSE) +# define RCU_CFG2_SYSFREQ RCU_CFG2_SYSFREQ_MSK + +# define RCU_CFG2_USBSW_POSS 4U +# define RCU_CFG2_USBSW_POSE 5U +# define RCU_CFG2_USBSW_MSK BITS(RCU_CFG2_USBSW_POSS, RCU_CFG2_USBSW_POSE) +# define RCU_CFG2_USBSW RCU_CFG2_USBSW_MSK + +# define RCU_CFG2_I2SSW_POSS 0U +# define RCU_CFG2_I2SSW_POSE 1U +# define RCU_CFG2_I2SSW_MSK BITS(RCU_CFG2_I2SSW_POSS, RCU_CFG2_I2SSW_POSE) +# define RCU_CFG2_I2SSW RCU_CFG2_I2SSW_MSK + +/****************** Bit definition for RCU_IER register ************************/ + +# define RCU_IER_CSSHOSC_POS 8U +# define RCU_IER_CSSHOSC_MSK BIT(RCU_IER_CSSHOSC_POS) +# define RCU_IER_CSSHOSC RCU_IER_CSSHOSC_MSK + +# define RCU_IER_PLL0RDY_POS 5U +# define RCU_IER_PLL0RDY_MSK BIT(RCU_IER_PLL0RDY_POS) +# define RCU_IER_PLL0RDY RCU_IER_PLL0RDY_MSK + +# define RCU_IER_HRC48RDY_POS 4U +# define RCU_IER_HRC48RDY_MSK BIT(RCU_IER_HRC48RDY_POS) +# define RCU_IER_HRC48RDY RCU_IER_HRC48RDY_MSK + +# define RCU_IER_HOSCRDY_POS 3U +# define RCU_IER_HOSCRDY_MSK BIT(RCU_IER_HOSCRDY_POS) +# define RCU_IER_HOSCRDY RCU_IER_HOSCRDY_MSK + +# define RCU_IER_HRCRDY_POS 2U +# define RCU_IER_HRCRDY_MSK BIT(RCU_IER_HRCRDY_POS) +# define RCU_IER_HRCRDY RCU_IER_HRCRDY_MSK + +# define RCU_IER_LOSCRDY_POS 1U +# define RCU_IER_LOSCRDY_MSK BIT(RCU_IER_LOSCRDY_POS) +# define RCU_IER_LOSCRDY RCU_IER_LOSCRDY_MSK + +# define RCU_IER_LRCRDY_POS 0U +# define RCU_IER_LRCRDY_MSK BIT(RCU_IER_LRCRDY_POS) +# define RCU_IER_LRCRDY RCU_IER_LRCRDY_MSK + +/****************** Bit definition for RCU_IDR register ************************/ + +# define RCU_IDR_CSSHOSC_POS 8U +# define RCU_IDR_CSSHOSC_MSK BIT(RCU_IDR_CSSHOSC_POS) +# define RCU_IDR_CSSHOSC RCU_IDR_CSSHOSC_MSK + +# define RCU_IDR_PLL0RDY_POS 5U +# define RCU_IDR_PLL0RDY_MSK BIT(RCU_IDR_PLL0RDY_POS) +# define RCU_IDR_PLL0RDY RCU_IDR_PLL0RDY_MSK + +# define RCU_IDR_HRC48RDY_POS 4U +# define RCU_IDR_HRC48RDY_MSK BIT(RCU_IDR_HRC48RDY_POS) +# define RCU_IDR_HRC48RDY RCU_IDR_HRC48RDY_MSK + +# define RCU_IDR_HOSCRDY_POS 3U +# define RCU_IDR_HOSCRDY_MSK BIT(RCU_IDR_HOSCRDY_POS) +# define RCU_IDR_HOSCRDY RCU_IDR_HOSCRDY_MSK + +# define RCU_IDR_HRCRDY_POS 2U +# define RCU_IDR_HRCRDY_MSK BIT(RCU_IDR_HRCRDY_POS) +# define RCU_IDR_HRCRDY RCU_IDR_HRCRDY_MSK + +# define RCU_IDR_LOSCRDY_POS 1U +# define RCU_IDR_LOSCRDY_MSK BIT(RCU_IDR_LOSCRDY_POS) +# define RCU_IDR_LOSCRDY RCU_IDR_LOSCRDY_MSK + +# define RCU_IDR_LRCRDY_POS 0U +# define RCU_IDR_LRCRDY_MSK BIT(RCU_IDR_LRCRDY_POS) +# define RCU_IDR_LRCRDY RCU_IDR_LRCRDY_MSK + +/****************** Bit definition for RCU_IVS register ************************/ + +# define RCU_IVS_CSSHOSC_POS 8U +# define RCU_IVS_CSSHOSC_MSK BIT(RCU_IVS_CSSHOSC_POS) +# define RCU_IVS_CSSHOSC RCU_IVS_CSSHOSC_MSK + +# define RCU_IVS_PLL0RDY_POS 5U +# define RCU_IVS_PLL0RDY_MSK BIT(RCU_IVS_PLL0RDY_POS) +# define RCU_IVS_PLL0RDY RCU_IVS_PLL0RDY_MSK + +# define RCU_IVS_HRC48RDY_POS 4U +# define RCU_IVS_HRC48RDY_MSK BIT(RCU_IVS_HRC48RDY_POS) +# define RCU_IVS_HRC48RDY RCU_IVS_HRC48RDY_MSK + +# define RCU_IVS_HOSCRDY_POS 3U +# define RCU_IVS_HOSCRDY_MSK BIT(RCU_IVS_HOSCRDY_POS) +# define RCU_IVS_HOSCRDY RCU_IVS_HOSCRDY_MSK + +# define RCU_IVS_HRCRDY_POS 2U +# define RCU_IVS_HRCRDY_MSK BIT(RCU_IVS_HRCRDY_POS) +# define RCU_IVS_HRCRDY RCU_IVS_HRCRDY_MSK + +# define RCU_IVS_LOSCRDY_POS 1U +# define RCU_IVS_LOSCRDY_MSK BIT(RCU_IVS_LOSCRDY_POS) +# define RCU_IVS_LOSCRDY RCU_IVS_LOSCRDY_MSK + +# define RCU_IVS_LRCRDY_POS 0U +# define RCU_IVS_LRCRDY_MSK BIT(RCU_IVS_LRCRDY_POS) +# define RCU_IVS_LRCRDY RCU_IVS_LRCRDY_MSK + +/****************** Bit definition for RCU_RIF register ************************/ + +# define RCU_RIF_CSSHOSC_POS 8U +# define RCU_RIF_CSSHOSC_MSK BIT(RCU_RIF_CSSHOSC_POS) +# define RCU_RIF_CSSHOSC RCU_RIF_CSSHOSC_MSK + +# define RCU_RIF_PLL0RDY_POS 5U +# define RCU_RIF_PLL0RDY_MSK BIT(RCU_RIF_PLL0RDY_POS) +# define RCU_RIF_PLL0RDY RCU_RIF_PLL0RDY_MSK + +# define RCU_RIF_HRC48RDY_POS 4U +# define RCU_RIF_HRC48RDY_MSK BIT(RCU_RIF_HRC48RDY_POS) +# define RCU_RIF_HRC48RDY RCU_RIF_HRC48RDY_MSK + +# define RCU_RIF_HOSCRDY_POS 3U +# define RCU_RIF_HOSCRDY_MSK BIT(RCU_RIF_HOSCRDY_POS) +# define RCU_RIF_HOSCRDY RCU_RIF_HOSCRDY_MSK + +# define RCU_RIF_HRCRDY_POS 2U +# define RCU_RIF_HRCRDY_MSK BIT(RCU_RIF_HRCRDY_POS) +# define RCU_RIF_HRCRDY RCU_RIF_HRCRDY_MSK + +# define RCU_RIF_LOSCRDY_POS 1U +# define RCU_RIF_LOSCRDY_MSK BIT(RCU_RIF_LOSCRDY_POS) +# define RCU_RIF_LOSCRDY RCU_RIF_LOSCRDY_MSK + +# define RCU_RIF_LRCRDY_POS 0U +# define RCU_RIF_LRCRDY_MSK BIT(RCU_RIF_LRCRDY_POS) +# define RCU_RIF_LRCRDY RCU_RIF_LRCRDY_MSK + +/****************** Bit definition for RCU_IFM register ************************/ + +# define RCU_IFM_CSSHOSC_POS 8U +# define RCU_IFM_CSSHOSC_MSK BIT(RCU_IFM_CSSHOSC_POS) +# define RCU_IFM_CSSHOSC RCU_IFM_CSSHOSC_MSK + +# define RCU_IFM_PLL0RDY_POS 5U +# define RCU_IFM_PLL0RDY_MSK BIT(RCU_IFM_PLL0RDY_POS) +# define RCU_IFM_PLL0RDY RCU_IFM_PLL0RDY_MSK + +# define RCU_IFM_HRC48RDY_POS 4U +# define RCU_IFM_HRC48RDY_MSK BIT(RCU_IFM_HRC48RDY_POS) +# define RCU_IFM_HRC48RDY RCU_IFM_HRC48RDY_MSK + +# define RCU_IFM_HOSCRDY_POS 3U +# define RCU_IFM_HOSCRDY_MSK BIT(RCU_IFM_HOSCRDY_POS) +# define RCU_IFM_HOSCRDY RCU_IFM_HOSCRDY_MSK + +# define RCU_IFM_HRCRDY_POS 2U +# define RCU_IFM_HRCRDY_MSK BIT(RCU_IFM_HRCRDY_POS) +# define RCU_IFM_HRCRDY RCU_IFM_HRCRDY_MSK + +# define RCU_IFM_LOSCRDY_POS 1U +# define RCU_IFM_LOSCRDY_MSK BIT(RCU_IFM_LOSCRDY_POS) +# define RCU_IFM_LOSCRDY RCU_IFM_LOSCRDY_MSK + +# define RCU_IFM_LRCRDY_POS 0U +# define RCU_IFM_LRCRDY_MSK BIT(RCU_IFM_LRCRDY_POS) +# define RCU_IFM_LRCRDY RCU_IFM_LRCRDY_MSK + +/****************** Bit definition for RCU_ICR register ************************/ + +# define RCU_ICR_CSSHOSC_POS 8U +# define RCU_ICR_CSSHOSC_MSK BIT(RCU_ICR_CSSHOSC_POS) +# define RCU_ICR_CSSHOSC RCU_ICR_CSSHOSC_MSK + +# define RCU_ICR_PLL0RDY_POS 5U +# define RCU_ICR_PLL0RDY_MSK BIT(RCU_ICR_PLL0RDY_POS) +# define RCU_ICR_PLL0RDY RCU_ICR_PLL0RDY_MSK + +# define RCU_ICR_HRC48RDY_POS 4U +# define RCU_ICR_HRC48RDY_MSK BIT(RCU_ICR_HRC48RDY_POS) +# define RCU_ICR_HRC48RDY RCU_ICR_HRC48RDY_MSK + +# define RCU_ICR_HOSCRDY_POS 3U +# define RCU_ICR_HOSCRDY_MSK BIT(RCU_ICR_HOSCRDY_POS) +# define RCU_ICR_HOSCRDY RCU_ICR_HOSCRDY_MSK + +# define RCU_ICR_HRCRDY_POS 2U +# define RCU_ICR_HRCRDY_MSK BIT(RCU_ICR_HRCRDY_POS) +# define RCU_ICR_HRCRDY RCU_ICR_HRCRDY_MSK + +# define RCU_ICR_LOSCRDY_POS 1U +# define RCU_ICR_LOSCRDY_MSK BIT(RCU_ICR_LOSCRDY_POS) +# define RCU_ICR_LOSCRDY RCU_ICR_LOSCRDY_MSK + +# define RCU_ICR_LRCRDY_POS 0U +# define RCU_ICR_LRCRDY_MSK BIT(RCU_ICR_LRCRDY_POS) +# define RCU_ICR_LRCRDY RCU_ICR_LRCRDY_MSK + +/****************** Bit definition for RCU_AHBRST register ************************/ + +# define RCU_AHBRST_MBISTEN_POS 31U +# define RCU_AHBRST_MBISTEN_MSK BIT(RCU_AHBRST_MBISTEN_POS) +# define RCU_AHBRST_MBISTEN RCU_AHBRST_MBISTEN_MSK + +# define RCU_AHBRST_GPDEN_POS 19U +# define RCU_AHBRST_GPDEN_MSK BIT(RCU_AHBRST_GPDEN_POS) +# define RCU_AHBRST_GPDEN RCU_AHBRST_GPDEN_MSK + +# define RCU_AHBRST_GPCEN_POS 18U +# define RCU_AHBRST_GPCEN_MSK BIT(RCU_AHBRST_GPCEN_POS) +# define RCU_AHBRST_GPCEN RCU_AHBRST_GPCEN_MSK + +# define RCU_AHBRST_GPBEN_POS 17U +# define RCU_AHBRST_GPBEN_MSK BIT(RCU_AHBRST_GPBEN_POS) +# define RCU_AHBRST_GPBEN RCU_AHBRST_GPBEN_MSK + +# define RCU_AHBRST_GPAEN_POS 16U +# define RCU_AHBRST_GPAEN_MSK BIT(RCU_AHBRST_GPAEN_POS) +# define RCU_AHBRST_GPAEN RCU_AHBRST_GPAEN_MSK + +# define RCU_AHBRST_CALCEN_POS 15U +# define RCU_AHBRST_CALCEN_MSK BIT(RCU_AHBRST_CALCEN_POS) +# define RCU_AHBRST_CALCEN RCU_AHBRST_CALCEN_MSK + +# define RCU_AHBRST_USBEN_POS 14U +# define RCU_AHBRST_USBEN_MSK BIT(RCU_AHBRST_USBEN_POS) +# define RCU_AHBRST_USBEN RCU_AHBRST_USBEN_MSK + +# define RCU_AHBRST_AESEN_POS 13U +# define RCU_AHBRST_AESEN_MSK BIT(RCU_AHBRST_AESEN_POS) +# define RCU_AHBRST_AESEN RCU_AHBRST_AESEN_MSK + +# define RCU_AHBRST_CRCEN_POS 12U +# define RCU_AHBRST_CRCEN_MSK BIT(RCU_AHBRST_CRCEN_POS) +# define RCU_AHBRST_CRCEN RCU_AHBRST_CRCEN_MSK + +# define RCU_AHBRST_MSWDEN_POS 11U +# define RCU_AHBRST_MSWDEN_MSK BIT(RCU_AHBRST_MSWDEN_POS) +# define RCU_AHBRST_MSWDEN RCU_AHBRST_MSWDEN_MSK + +# define RCU_AHBRST_CSUEN_POS 10U +# define RCU_AHBRST_CSUEN_MSK BIT(RCU_AHBRST_CSUEN_POS) +# define RCU_AHBRST_CSUEN RCU_AHBRST_CSUEN_MSK + +# define RCU_AHBRST_KBCUEN_POS 7U +# define RCU_AHBRST_KBCUEN_MSK BIT(RCU_AHBRST_KBCUEN_POS) +# define RCU_AHBRST_KBCUEN RCU_AHBRST_KBCUEN_MSK + +# define RCU_AHBRST_RTCEN_POS 6U +# define RCU_AHBRST_RTCEN_MSK BIT(RCU_AHBRST_RTCEN_POS) +# define RCU_AHBRST_RTCEN RCU_AHBRST_RTCEN_MSK + +# define RCU_AHBRST_DMA1EN_POS 0U +# define RCU_AHBRST_DMA1EN_MSK BIT(RCU_AHBRST_DMA1EN_POS) +# define RCU_AHBRST_DMA1EN RCU_AHBRST_DMA1EN_MSK + +/****************** Bit definition for RCU_APB1RST register ************************/ + +# define RCU_APB1RST_I2C2EN_POS 22U +# define RCU_APB1RST_I2C2EN_MSK BIT(RCU_APB1RST_I2C2EN_POS) +# define RCU_APB1RST_I2C2EN RCU_APB1RST_I2C2EN_MSK + +# define RCU_APB1RST_I2C1EN_POS 21U +# define RCU_APB1RST_I2C1EN_MSK BIT(RCU_APB1RST_I2C1EN_POS) +# define RCU_APB1RST_I2C1EN RCU_APB1RST_I2C1EN_MSK + +# define RCU_APB1RST_UART4EN_POS 19U +# define RCU_APB1RST_UART4EN_MSK BIT(RCU_APB1RST_UART4EN_POS) +# define RCU_APB1RST_UART4EN RCU_APB1RST_UART4EN_MSK + +# define RCU_APB1RST_UART3EN_POS 18U +# define RCU_APB1RST_UART3EN_MSK BIT(RCU_APB1RST_UART3EN_POS) +# define RCU_APB1RST_UART3EN RCU_APB1RST_UART3EN_MSK + +# define RCU_APB1RST_UART2EN_POS 17U +# define RCU_APB1RST_UART2EN_MSK BIT(RCU_APB1RST_UART2EN_POS) +# define RCU_APB1RST_UART2EN RCU_APB1RST_UART2EN_MSK + +# define RCU_APB1RST_SPI3EN_POS 15U +# define RCU_APB1RST_SPI3EN_MSK BIT(RCU_APB1RST_SPI3EN_POS) +# define RCU_APB1RST_SPI3EN RCU_APB1RST_SPI3EN_MSK + +# define RCU_APB1RST_SPI2EN_POS 14U +# define RCU_APB1RST_SPI2EN_MSK BIT(RCU_APB1RST_SPI2EN_POS) +# define RCU_APB1RST_SPI2EN RCU_APB1RST_SPI2EN_MSK + +# define RCU_APB1RST_WWDTEN_POS 11U +# define RCU_APB1RST_WWDTEN_MSK BIT(RCU_APB1RST_WWDTEN_POS) +# define RCU_APB1RST_WWDTEN RCU_APB1RST_WWDTEN_MSK + +# define RCU_APB1RST_BS16T1EN_POS 4U +# define RCU_APB1RST_BS16T1EN_MSK BIT(RCU_APB1RST_BS16T1EN_POS) +# define RCU_APB1RST_BS16T1EN RCU_APB1RST_BS16T1EN_MSK + +# define RCU_APB1RST_GP16C4T3EN_POS 3U +# define RCU_APB1RST_GP16C4T3EN_MSK BIT(RCU_APB1RST_GP16C4T3EN_POS) +# define RCU_APB1RST_GP16C4T3EN RCU_APB1RST_GP16C4T3EN_MSK + +# define RCU_APB1RST_GP16C4T2EN_POS 2U +# define RCU_APB1RST_GP16C4T2EN_MSK BIT(RCU_APB1RST_GP16C4T2EN_POS) +# define RCU_APB1RST_GP16C4T2EN RCU_APB1RST_GP16C4T2EN_MSK + +# define RCU_APB1RST_GP16C4T1EN_POS 1U +# define RCU_APB1RST_GP16C4T1EN_MSK BIT(RCU_APB1RST_GP16C4T1EN_POS) +# define RCU_APB1RST_GP16C4T1EN RCU_APB1RST_GP16C4T1EN_MSK + +# define RCU_APB1RST_GP32C4T1EN_POS 0U +# define RCU_APB1RST_GP32C4T1EN_MSK BIT(RCU_APB1RST_GP32C4T1EN_POS) +# define RCU_APB1RST_GP32C4T1EN RCU_APB1RST_GP32C4T1EN_MSK + +/****************** Bit definition for RCU_APB2RST register ************************/ + +# define RCU_APB2RST_CMPEN_POS 23U +# define RCU_APB2RST_CMPEN_MSK BIT(RCU_APB2RST_CMPEN_POS) +# define RCU_APB2RST_CMPEN RCU_APB2RST_CMPEN_MSK + +# define RCU_APB2RST_GP16C2T4EN_POS 19U +# define RCU_APB2RST_GP16C2T4EN_MSK BIT(RCU_APB2RST_GP16C2T4EN_POS) +# define RCU_APB2RST_GP16C2T4EN RCU_APB2RST_GP16C2T4EN_MSK + +# define RCU_APB2RST_GP16C2T3EN_POS 18U +# define RCU_APB2RST_GP16C2T3EN_MSK BIT(RCU_APB2RST_GP16C2T3EN_POS) +# define RCU_APB2RST_GP16C2T3EN RCU_APB2RST_GP16C2T3EN_MSK + +# define RCU_APB2RST_GP16C2T2EN_POS 17U +# define RCU_APB2RST_GP16C2T2EN_MSK BIT(RCU_APB2RST_GP16C2T2EN_POS) +# define RCU_APB2RST_GP16C2T2EN RCU_APB2RST_GP16C2T2EN_MSK + +# define RCU_APB2RST_GP16C2T1EN_POS 16U +# define RCU_APB2RST_GP16C2T1EN_MSK BIT(RCU_APB2RST_GP16C2T1EN_POS) +# define RCU_APB2RST_GP16C2T1EN RCU_APB2RST_GP16C2T1EN_MSK + +# define RCU_APB2RST_UART1EN_POS 14U +# define RCU_APB2RST_UART1EN_MSK BIT(RCU_APB2RST_UART1EN_POS) +# define RCU_APB2RST_UART1EN RCU_APB2RST_UART1EN_MSK + +# define RCU_APB2RST_SPI1EN_POS 12U +# define RCU_APB2RST_SPI1EN_MSK BIT(RCU_APB2RST_SPI1EN_POS) +# define RCU_APB2RST_SPI1EN RCU_APB2RST_SPI1EN_MSK + +# define RCU_APB2RST_AD16C4T1EN_POS 11U +# define RCU_APB2RST_AD16C4T1EN_MSK BIT(RCU_APB2RST_AD16C4T1EN_POS) +# define RCU_APB2RST_AD16C4T1EN RCU_APB2RST_AD16C4T1EN_MSK + +# define RCU_APB2RST_ADCEN_POS 9U +# define RCU_APB2RST_ADCEN_MSK BIT(RCU_APB2RST_ADCEN_POS) +# define RCU_APB2RST_ADCEN RCU_APB2RST_ADCEN_MSK + +/****************** Bit definition for RCU_AHBEN register ************************/ + +# define RCU_AHBEN_MBISTEN_POS 31U +# define RCU_AHBEN_MBISTEN_MSK BIT(RCU_AHBEN_MBISTEN_POS) +# define RCU_AHBEN_MBISTEN RCU_AHBEN_MBISTEN_MSK + +# define RCU_AHBEN_GPDEN_POS 19U +# define RCU_AHBEN_GPDEN_MSK BIT(RCU_AHBEN_GPDEN_POS) +# define RCU_AHBEN_GPDEN RCU_AHBEN_GPDEN_MSK + +# define RCU_AHBEN_GPCEN_POS 18U +# define RCU_AHBEN_GPCEN_MSK BIT(RCU_AHBEN_GPCEN_POS) +# define RCU_AHBEN_GPCEN RCU_AHBEN_GPCEN_MSK + +# define RCU_AHBEN_GPBEN_POS 17U +# define RCU_AHBEN_GPBEN_MSK BIT(RCU_AHBEN_GPBEN_POS) +# define RCU_AHBEN_GPBEN RCU_AHBEN_GPBEN_MSK + +# define RCU_AHBEN_GPAEN_POS 16U +# define RCU_AHBEN_GPAEN_MSK BIT(RCU_AHBEN_GPAEN_POS) +# define RCU_AHBEN_GPAEN RCU_AHBEN_GPAEN_MSK + +# define RCU_AHBEN_CALCEN_POS 15U +# define RCU_AHBEN_CALCEN_MSK BIT(RCU_AHBEN_CALCEN_POS) +# define RCU_AHBEN_CALCEN RCU_AHBEN_CALCEN_MSK + +# define RCU_AHBEN_USBEN_POS 14U +# define RCU_AHBEN_USBEN_MSK BIT(RCU_AHBEN_USBEN_POS) +# define RCU_AHBEN_USBEN RCU_AHBEN_USBEN_MSK + +# define RCU_AHBEN_AESEN_POS 13U +# define RCU_AHBEN_AESEN_MSK BIT(RCU_AHBEN_AESEN_POS) +# define RCU_AHBEN_AESEN RCU_AHBEN_AESEN_MSK + +# define RCU_AHBEN_CRCEN_POS 12U +# define RCU_AHBEN_CRCEN_MSK BIT(RCU_AHBEN_CRCEN_POS) +# define RCU_AHBEN_CRCEN RCU_AHBEN_CRCEN_MSK + +# define RCU_AHBEN_MSWDEN_POS 11U +# define RCU_AHBEN_MSWDEN_MSK BIT(RCU_AHBEN_MSWDEN_POS) +# define RCU_AHBEN_MSWDEN RCU_AHBEN_MSWDEN_MSK + +# define RCU_AHBEN_CSUEN_POS 10U +# define RCU_AHBEN_CSUEN_MSK BIT(RCU_AHBEN_CSUEN_POS) +# define RCU_AHBEN_CSUEN RCU_AHBEN_CSUEN_MSK + +# define RCU_AHBEN_KBCUEN_POS 7U +# define RCU_AHBEN_KBCUEN_MSK BIT(RCU_AHBEN_KBCUEN_POS) +# define RCU_AHBEN_KBCUEN RCU_AHBEN_KBCUEN_MSK + +# define RCU_AHBEN_RTCEN_POS 6U +# define RCU_AHBEN_RTCEN_MSK BIT(RCU_AHBEN_RTCEN_POS) +# define RCU_AHBEN_RTCEN RCU_AHBEN_RTCEN_MSK + +# define RCU_AHBEN_DMA1EN_POS 0U +# define RCU_AHBEN_DMA1EN_MSK BIT(RCU_AHBEN_DMA1EN_POS) +# define RCU_AHBEN_DMA1EN RCU_AHBEN_DMA1EN_MSK + +/****************** Bit definition for RCU_APB1EN register ************************/ + +# define RCU_APB1EN_I2C2EN_POS 22U +# define RCU_APB1EN_I2C2EN_MSK BIT(RCU_APB1EN_I2C2EN_POS) +# define RCU_APB1EN_I2C2EN RCU_APB1EN_I2C2EN_MSK + +# define RCU_APB1EN_I2C1EN_POS 21U +# define RCU_APB1EN_I2C1EN_MSK BIT(RCU_APB1EN_I2C1EN_POS) +# define RCU_APB1EN_I2C1EN RCU_APB1EN_I2C1EN_MSK + +# define RCU_APB1EN_UART4EN_POS 19U +# define RCU_APB1EN_UART4EN_MSK BIT(RCU_APB1EN_UART4EN_POS) +# define RCU_APB1EN_UART4EN RCU_APB1EN_UART4EN_MSK + +# define RCU_APB1EN_UART3EN_POS 18U +# define RCU_APB1EN_UART3EN_MSK BIT(RCU_APB1EN_UART3EN_POS) +# define RCU_APB1EN_UART3EN RCU_APB1EN_UART3EN_MSK + +# define RCU_APB1EN_UART2EN_POS 17U +# define RCU_APB1EN_UART2EN_MSK BIT(RCU_APB1EN_UART2EN_POS) +# define RCU_APB1EN_UART2EN RCU_APB1EN_UART2EN_MSK + +# define RCU_APB1EN_SPI3EN_POS 15U +# define RCU_APB1EN_SPI3EN_MSK BIT(RCU_APB1EN_SPI3EN_POS) +# define RCU_APB1EN_SPI3EN RCU_APB1EN_SPI3EN_MSK + +# define RCU_APB1EN_SPI2EN_POS 14U +# define RCU_APB1EN_SPI2EN_MSK BIT(RCU_APB1EN_SPI2EN_POS) +# define RCU_APB1EN_SPI2EN RCU_APB1EN_SPI2EN_MSK + +# define RCU_APB1EN_WWDTEN_POS 11U +# define RCU_APB1EN_WWDTEN_MSK BIT(RCU_APB1EN_WWDTEN_POS) +# define RCU_APB1EN_WWDTEN RCU_APB1EN_WWDTEN_MSK + +# define RCU_APB1EN_BS16T1EN_POS 4U +# define RCU_APB1EN_BS16T1EN_MSK BIT(RCU_APB1EN_BS16T1EN_POS) +# define RCU_APB1EN_BS16T1EN RCU_APB1EN_BS16T1EN_MSK + +# define RCU_APB1EN_GP16C4T3EN_POS 3U +# define RCU_APB1EN_GP16C4T3EN_MSK BIT(RCU_APB1EN_GP16C4T3EN_POS) +# define RCU_APB1EN_GP16C4T3EN RCU_APB1EN_GP16C4T3EN_MSK + +# define RCU_APB1EN_GP16C4T2EN_POS 2U +# define RCU_APB1EN_GP16C4T2EN_MSK BIT(RCU_APB1EN_GP16C4T2EN_POS) +# define RCU_APB1EN_GP16C4T2EN RCU_APB1EN_GP16C4T2EN_MSK + +# define RCU_APB1EN_GP16C4T1EN_POS 1U +# define RCU_APB1EN_GP16C4T1EN_MSK BIT(RCU_APB1EN_GP16C4T1EN_POS) +# define RCU_APB1EN_GP16C4T1EN RCU_APB1EN_GP16C4T1EN_MSK + +# define RCU_APB1EN_GP32C4T1EN_POS 0U +# define RCU_APB1EN_GP32C4T1EN_MSK BIT(RCU_APB1EN_GP32C4T1EN_POS) +# define RCU_APB1EN_GP32C4T1EN RCU_APB1EN_GP32C4T1EN_MSK + +/****************** Bit definition for RCU_APB2EN register ************************/ + +# define RCU_APB2EN_CMPEN_POS 23U +# define RCU_APB2EN_CMPEN_MSK BIT(RCU_APB2EN_CMPEN_POS) +# define RCU_APB2EN_CMPEN RCU_APB2EN_CMPEN_MSK + +# define RCU_APB2EN_GP16C2T4EN_POS 19U +# define RCU_APB2EN_GP16C2T4EN_MSK BIT(RCU_APB2EN_GP16C2T4EN_POS) +# define RCU_APB2EN_GP16C2T4EN RCU_APB2EN_GP16C2T4EN_MSK + +# define RCU_APB2EN_GP16C2T3EN_POS 18U +# define RCU_APB2EN_GP16C2T3EN_MSK BIT(RCU_APB2EN_GP16C2T3EN_POS) +# define RCU_APB2EN_GP16C2T3EN RCU_APB2EN_GP16C2T3EN_MSK + +# define RCU_APB2EN_GP16C2T2EN_POS 17U +# define RCU_APB2EN_GP16C2T2EN_MSK BIT(RCU_APB2EN_GP16C2T2EN_POS) +# define RCU_APB2EN_GP16C2T2EN RCU_APB2EN_GP16C2T2EN_MSK + +# define RCU_APB2EN_GP16C2T1EN_POS 16U +# define RCU_APB2EN_GP16C2T1EN_MSK BIT(RCU_APB2EN_GP16C2T1EN_POS) +# define RCU_APB2EN_GP16C2T1EN RCU_APB2EN_GP16C2T1EN_MSK + +# define RCU_APB2EN_UART1EN_POS 14U +# define RCU_APB2EN_UART1EN_MSK BIT(RCU_APB2EN_UART1EN_POS) +# define RCU_APB2EN_UART1EN RCU_APB2EN_UART1EN_MSK + +# define RCU_APB2EN_SPI1EN_POS 12U +# define RCU_APB2EN_SPI1EN_MSK BIT(RCU_APB2EN_SPI1EN_POS) +# define RCU_APB2EN_SPI1EN RCU_APB2EN_SPI1EN_MSK + +# define RCU_APB2EN_AD16C4T1EN_POS 11U +# define RCU_APB2EN_AD16C4T1EN_MSK BIT(RCU_APB2EN_AD16C4T1EN_POS) +# define RCU_APB2EN_AD16C4T1EN RCU_APB2EN_AD16C4T1EN_MSK + +# define RCU_APB2EN_ADCEN_POS 9U +# define RCU_APB2EN_ADCEN_MSK BIT(RCU_APB2EN_ADCEN_POS) +# define RCU_APB2EN_ADCEN RCU_APB2EN_ADCEN_MSK + +/****************** Bit definition for RCU_AHBSL register ************************/ + +# define RCU_AHBSL_MBISTEN_POS 31U +# define RCU_AHBSL_MBISTEN_MSK BIT(RCU_AHBSL_MBISTEN_POS) +# define RCU_AHBSL_MBISTEN RCU_AHBSL_MBISTEN_MSK + +# define RCU_AHBSL_GPDEN_POS 19U +# define RCU_AHBSL_GPDEN_MSK BIT(RCU_AHBSL_GPDEN_POS) +# define RCU_AHBSL_GPDEN RCU_AHBSL_GPDEN_MSK + +# define RCU_AHBSL_GPCEN_POS 18U +# define RCU_AHBSL_GPCEN_MSK BIT(RCU_AHBSL_GPCEN_POS) +# define RCU_AHBSL_GPCEN RCU_AHBSL_GPCEN_MSK + +# define RCU_AHBSL_GPBEN_POS 17U +# define RCU_AHBSL_GPBEN_MSK BIT(RCU_AHBSL_GPBEN_POS) +# define RCU_AHBSL_GPBEN RCU_AHBSL_GPBEN_MSK + +# define RCU_AHBSL_GPAEN_POS 16U +# define RCU_AHBSL_GPAEN_MSK BIT(RCU_AHBSL_GPAEN_POS) +# define RCU_AHBSL_GPAEN RCU_AHBSL_GPAEN_MSK + +# define RCU_AHBSL_CALCEN_POS 15U +# define RCU_AHBSL_CALCEN_MSK BIT(RCU_AHBSL_CALCEN_POS) +# define RCU_AHBSL_CALCEN RCU_AHBSL_CALCEN_MSK + +# define RCU_AHBSL_USBEN_POS 14U +# define RCU_AHBSL_USBEN_MSK BIT(RCU_AHBSL_USBEN_POS) +# define RCU_AHBSL_USBEN RCU_AHBSL_USBEN_MSK + +# define RCU_AHBSL_AESEN_POS 13U +# define RCU_AHBSL_AESEN_MSK BIT(RCU_AHBSL_AESEN_POS) +# define RCU_AHBSL_AESEN RCU_AHBSL_AESEN_MSK + +# define RCU_AHBSL_CRCEN_POS 12U +# define RCU_AHBSL_CRCEN_MSK BIT(RCU_AHBSL_CRCEN_POS) +# define RCU_AHBSL_CRCEN RCU_AHBSL_CRCEN_MSK + +# define RCU_AHBSL_MSWDEN_POS 11U +# define RCU_AHBSL_MSWDEN_MSK BIT(RCU_AHBSL_MSWDEN_POS) +# define RCU_AHBSL_MSWDEN RCU_AHBSL_MSWDEN_MSK + +# define RCU_AHBSL_CSUEN_POS 10U +# define RCU_AHBSL_CSUEN_MSK BIT(RCU_AHBSL_CSUEN_POS) +# define RCU_AHBSL_CSUEN RCU_AHBSL_CSUEN_MSK + +# define RCU_AHBSL_KBCUEN_POS 7U +# define RCU_AHBSL_KBCUEN_MSK BIT(RCU_AHBSL_KBCUEN_POS) +# define RCU_AHBSL_KBCUEN RCU_AHBSL_KBCUEN_MSK + +# define RCU_AHBSL_RTCEN_POS 6U +# define RCU_AHBSL_RTCEN_MSK BIT(RCU_AHBSL_RTCEN_POS) +# define RCU_AHBSL_RTCEN RCU_AHBSL_RTCEN_MSK + +# define RCU_AHBSL_DMA1EN_POS 0U +# define RCU_AHBSL_DMA1EN_MSK BIT(RCU_AHBSL_DMA1EN_POS) +# define RCU_AHBSL_DMA1EN RCU_AHBSL_DMA1EN_MSK + +/****************** Bit definition for RCU_APB1SL register ************************/ + +# define RCU_APB1SL_I2C2EN_POS 22U +# define RCU_APB1SL_I2C2EN_MSK BIT(RCU_APB1SL_I2C2EN_POS) +# define RCU_APB1SL_I2C2EN RCU_APB1SL_I2C2EN_MSK + +# define RCU_APB1SL_I2C1EN_POS 21U +# define RCU_APB1SL_I2C1EN_MSK BIT(RCU_APB1SL_I2C1EN_POS) +# define RCU_APB1SL_I2C1EN RCU_APB1SL_I2C1EN_MSK + +# define RCU_APB1SL_UART4EN_POS 19U +# define RCU_APB1SL_UART4EN_MSK BIT(RCU_APB1SL_UART4EN_POS) +# define RCU_APB1SL_UART4EN RCU_APB1SL_UART4EN_MSK + +# define RCU_APB1SL_UART3EN_POS 18U +# define RCU_APB1SL_UART3EN_MSK BIT(RCU_APB1SL_UART3EN_POS) +# define RCU_APB1SL_UART3EN RCU_APB1SL_UART3EN_MSK + +# define RCU_APB1SL_UART2EN_POS 17U +# define RCU_APB1SL_UART2EN_MSK BIT(RCU_APB1SL_UART2EN_POS) +# define RCU_APB1SL_UART2EN RCU_APB1SL_UART2EN_MSK + +# define RCU_APB1SL_SPI3EN_POS 15U +# define RCU_APB1SL_SPI3EN_MSK BIT(RCU_APB1SL_SPI3EN_POS) +# define RCU_APB1SL_SPI3EN RCU_APB1SL_SPI3EN_MSK + +# define RCU_APB1SL_SPI2EN_POS 14U +# define RCU_APB1SL_SPI2EN_MSK BIT(RCU_APB1SL_SPI2EN_POS) +# define RCU_APB1SL_SPI2EN RCU_APB1SL_SPI2EN_MSK + +# define RCU_APB1SL_WWDTEN_POS 11U +# define RCU_APB1SL_WWDTEN_MSK BIT(RCU_APB1SL_WWDTEN_POS) +# define RCU_APB1SL_WWDTEN RCU_APB1SL_WWDTEN_MSK + +# define RCU_APB1SL_BS16T1EN_POS 4U +# define RCU_APB1SL_BS16T1EN_MSK BIT(RCU_APB1SL_BS16T1EN_POS) +# define RCU_APB1SL_BS16T1EN RCU_APB1SL_BS16T1EN_MSK + +# define RCU_APB1SL_GP16C4T3EN_POS 3U +# define RCU_APB1SL_GP16C4T3EN_MSK BIT(RCU_APB1SL_GP16C4T3EN_POS) +# define RCU_APB1SL_GP16C4T3EN RCU_APB1SL_GP16C4T3EN_MSK + +# define RCU_APB1SL_GP16C4T2EN_POS 2U +# define RCU_APB1SL_GP16C4T2EN_MSK BIT(RCU_APB1SL_GP16C4T2EN_POS) +# define RCU_APB1SL_GP16C4T2EN RCU_APB1SL_GP16C4T2EN_MSK + +# define RCU_APB1SL_GP16C4T1EN_POS 1U +# define RCU_APB1SL_GP16C4T1EN_MSK BIT(RCU_APB1SL_GP16C4T1EN_POS) +# define RCU_APB1SL_GP16C4T1EN RCU_APB1SL_GP16C4T1EN_MSK + +# define RCU_APB1SL_GP32C4T1EN_POS 0U +# define RCU_APB1SL_GP32C4T1EN_MSK BIT(RCU_APB1SL_GP32C4T1EN_POS) +# define RCU_APB1SL_GP32C4T1EN RCU_APB1SL_GP32C4T1EN_MSK + +/****************** Bit definition for RCU_APB2SL register ************************/ + +# define RCU_APB2SL_CMPEN_POS 23U +# define RCU_APB2SL_CMPEN_MSK BIT(RCU_APB2SL_CMPEN_POS) +# define RCU_APB2SL_CMPEN RCU_APB2SL_CMPEN_MSK + +# define RCU_APB2SL_GP16C2T4EN_POS 19U +# define RCU_APB2SL_GP16C2T4EN_MSK BIT(RCU_APB2SL_GP16C2T4EN_POS) +# define RCU_APB2SL_GP16C2T4EN RCU_APB2SL_GP16C2T4EN_MSK + +# define RCU_APB2SL_GP16C2T3EN_POS 18U +# define RCU_APB2SL_GP16C2T3EN_MSK BIT(RCU_APB2SL_GP16C2T3EN_POS) +# define RCU_APB2SL_GP16C2T3EN RCU_APB2SL_GP16C2T3EN_MSK + +# define RCU_APB2SL_GP16C2T2EN_POS 17U +# define RCU_APB2SL_GP16C2T2EN_MSK BIT(RCU_APB2SL_GP16C2T2EN_POS) +# define RCU_APB2SL_GP16C2T2EN RCU_APB2SL_GP16C2T2EN_MSK + +# define RCU_APB2SL_GP16C2T1EN_POS 16U +# define RCU_APB2SL_GP16C2T1EN_MSK BIT(RCU_APB2SL_GP16C2T1EN_POS) +# define RCU_APB2SL_GP16C2T1EN RCU_APB2SL_GP16C2T1EN_MSK + +# define RCU_APB2SL_UART1EN_POS 14U +# define RCU_APB2SL_UART1EN_MSK BIT(RCU_APB2SL_UART1EN_POS) +# define RCU_APB2SL_UART1EN RCU_APB2SL_UART1EN_MSK + +# define RCU_APB2SL_SPI1EN_POS 12U +# define RCU_APB2SL_SPI1EN_MSK BIT(RCU_APB2SL_SPI1EN_POS) +# define RCU_APB2SL_SPI1EN RCU_APB2SL_SPI1EN_MSK + +# define RCU_APB2SL_AD16C4T1EN_POS 11U +# define RCU_APB2SL_AD16C4T1EN_MSK BIT(RCU_APB2SL_AD16C4T1EN_POS) +# define RCU_APB2SL_AD16C4T1EN RCU_APB2SL_AD16C4T1EN_MSK + +# define RCU_APB2SL_ADCEN_POS 9U +# define RCU_APB2SL_ADCEN_MSK BIT(RCU_APB2SL_ADCEN_POS) +# define RCU_APB2SL_ADCEN RCU_APB2SL_ADCEN_MSK + +/****************** Bit definition for RCU_LCON register ************************/ + +# define RCU_LCON_LOSCBYP_POS 10U +# define RCU_LCON_LOSCBYP_MSK BIT(RCU_LCON_LOSCBYP_POS) +# define RCU_LCON_LOSCBYP RCU_LCON_LOSCBYP_MSK + +# define RCU_LCON_LOSCRDY_POS 9U +# define RCU_LCON_LOSCRDY_MSK BIT(RCU_LCON_LOSCRDY_POS) +# define RCU_LCON_LOSCRDY RCU_LCON_LOSCRDY_MSK + +# define RCU_LCON_LOSCON_POS 8U +# define RCU_LCON_LOSCON_MSK BIT(RCU_LCON_LOSCON_POS) +# define RCU_LCON_LOSCON RCU_LCON_LOSCON_MSK + +# define RCU_LCON_LRCRDY_POS 1U +# define RCU_LCON_LRCRDY_MSK BIT(RCU_LCON_LRCRDY_POS) +# define RCU_LCON_LRCRDY RCU_LCON_LRCRDY_MSK + +# define RCU_LCON_LRCON_POS 0U +# define RCU_LCON_LRCON_MSK BIT(RCU_LCON_LRCON_POS) +# define RCU_LCON_LRCON RCU_LCON_LRCON_MSK + +/****************** Bit definition for RCU_RSTF register ************************/ + +# define RCU_RSTF_LPRSTF_POS 23U +# define RCU_RSTF_LPRSTF_MSK BIT(RCU_RSTF_LPRSTF_POS) +# define RCU_RSTF_LPRSTF RCU_RSTF_LPRSTF_MSK + +# define RCU_RSTF_WWDTRSTF_POS 22U +# define RCU_RSTF_WWDTRSTF_MSK BIT(RCU_RSTF_WWDTRSTF_POS) +# define RCU_RSTF_WWDTRSTF RCU_RSTF_WWDTRSTF_MSK + +# define RCU_RSTF_IWDTRSTF_POS 21U +# define RCU_RSTF_IWDTRSTF_MSK BIT(RCU_RSTF_IWDTRSTF_POS) +# define RCU_RSTF_IWDTRSTF RCU_RSTF_IWDTRSTF_MSK + +# define RCU_RSTF_SWRSTF_POS 20U +# define RCU_RSTF_SWRSTF_MSK BIT(RCU_RSTF_SWRSTF_POS) +# define RCU_RSTF_SWRSTF RCU_RSTF_SWRSTF_MSK + +# define RCU_RSTF_OBLRSTF_POS 19U +# define RCU_RSTF_OBLRSTF_MSK BIT(RCU_RSTF_OBLRSTF_POS) +# define RCU_RSTF_OBLRSTF RCU_RSTF_OBLRSTF_MSK + +# define RCU_RSTF_NRSTF_POS 18U +# define RCU_RSTF_NRSTF_MSK BIT(RCU_RSTF_NRSTF_POS) +# define RCU_RSTF_NRSTF RCU_RSTF_NRSTF_MSK + +# define RCU_RSTF_BORRSTF_POS 17U +# define RCU_RSTF_BORRSTF_MSK BIT(RCU_RSTF_BORRSTF_POS) +# define RCU_RSTF_BORRSTF RCU_RSTF_BORRSTF_MSK + +# define RCU_RSTF_PORRSTF_POS 16U +# define RCU_RSTF_PORRSTF_MSK BIT(RCU_RSTF_PORRSTF_POS) +# define RCU_RSTF_PORRSTF RCU_RSTF_PORRSTF_MSK + +# define RCU_RSTF_CLRFLG_POS 15U +# define RCU_RSTF_CLRFLG_MSK BIT(RCU_RSTF_CLRFLG_POS) +# define RCU_RSTF_CLRFLG RCU_RSTF_CLRFLG_MSK + +/****************** Bit definition for RCU_CKTRIM register ************************/ + +# define RCU_CKTRIM_HRC48UE_POS 31U +# define RCU_CKTRIM_HRC48UE_MSK BIT(RCU_CKTRIM_HRC48UE_POS) +# define RCU_CKTRIM_HRC48UE RCU_CKTRIM_HRC48UE_MSK + +# define RCU_CKTRIM_HRC48SEL_POS 30U +# define RCU_CKTRIM_HRC48SEL_MSK BIT(RCU_CKTRIM_HRC48SEL_POS) +# define RCU_CKTRIM_HRC48SEL RCU_CKTRIM_HRC48SEL_MSK + +# define RCU_CKTRIM_HRCSEL_POS 28U +# define RCU_CKTRIM_HRCSEL_MSK BIT(RCU_CKTRIM_HRCSEL_POS) +# define RCU_CKTRIM_HRCSEL RCU_CKTRIM_HRCSEL_MSK + +# define RCU_CKTRIM_HRC48TRIM_POSS 16U +# define RCU_CKTRIM_HRC48TRIM_POSE 24U +# define RCU_CKTRIM_HRC48TRIM_MSK BITS(RCU_CKTRIM_HRC48TRIM_POSS, RCU_CKTRIM_HRC48TRIM_POSE) +# define RCU_CKTRIM_HRC48TRIM RCU_CKTRIM_HRC48TRIM_MSK + +# define RCU_CKTRIM_HRCTRIM_POSS 8U +# define RCU_CKTRIM_HRCTRIM_POSE 15U +# define RCU_CKTRIM_HRCTRIM_MSK BITS(RCU_CKTRIM_HRCTRIM_POSS, RCU_CKTRIM_HRCTRIM_POSE) +# define RCU_CKTRIM_HRCTRIM RCU_CKTRIM_HRCTRIM_MSK + +typedef struct +{ + __IO uint32_t CON; // 0x000 + __IO uint32_t CFG; // 0x004 + __IO uint32_t PLL0; // 0x008 + __IO uint32_t CFG2; // 0x00c + __O uint32_t IER; // 0x010 + __O uint32_t IDR; // 0x014 + __I uint32_t IVS; // 0x018 + __I uint32_t RIF; // 0x01c + __I uint32_t IFM; // 0x020 + __O uint32_t ICR; // 0x024 + __IO uint32_t RESERVED0[2]; // 0x028-0x02c + __IO uint32_t AHBRST; // 0x030 + __IO uint32_t APB1RST; // 0x034 + __IO uint32_t APB2RST; // 0x038 + __IO uint32_t AHBEN; // 0x03c + __IO uint32_t APB1EN; // 0x040 + __IO uint32_t APB2EN; // 0x044 + __IO uint32_t AHBSL; // 0x048 + __IO uint32_t APB1SL; // 0x04c + __IO uint32_t APB2SL; // 0x050 + __IO uint32_t RESERVED1[3]; // 0x054-0x05c + __IO uint32_t LCON; // 0x060 + __IO uint32_t RSTF; // 0x064 + __IO uint32_t RESERVED2[10]; // 0x068-0x08c + __IO uint32_t CKTRIM; // 0x090 +} RCU_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_rtc.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_rtc.h new file mode 100644 index 00000000000..0a350a128bb --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_rtc.h @@ -0,0 +1,793 @@ +/********************************************************************************** + * + * @file reg_rtc.h + * @brief RTC Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __RTC_H__ +#define __RTC_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + +/****************** Bit definition for RTC_CTRL register ************************/ + +#define RTC_CTRL_SCALE_POSS 16U +#define RTC_CTRL_SCALE_POSE 23U +#define RTC_CTRL_SCALE_MSK BITS(RTC_CTRL_SCALE_POSS,RTC_CTRL_SCALE_POSE) +#define RTC_CTRL_SCALE RTC_CTRL_SCALE_MSK + +#define RTC_CTRL_PSCALE_POSS 8U +#define RTC_CTRL_PSCALE_POSE 14U +#define RTC_CTRL_PSCALE_MSK BITS(RTC_CTRL_PSCALE_POSS,RTC_CTRL_PSCALE_POSE) +#define RTC_CTRL_PSCALE RTC_CTRL_PSCALE_MSK + +#define RTC_CTRL_CKSEL_POSS 2U +#define RTC_CTRL_CKSEL_POSE 3U +#define RTC_CTRL_CKSEL_MSK BITS(RTC_CTRL_CKSEL_POSS,RTC_CTRL_CKSEL_POSE) +#define RTC_CTRL_CKSEL RTC_CTRL_CKSEL_MSK + +#define RTC_CTRL_RTCEN_POS 0U +#define RTC_CTRL_RTCEN_MSK BIT(RTC_CTRL_RTCEN_POS) +#define RTC_CTRL_RTCEN RTC_CTRL_RTCEN_MSK + +/****************** Bit definition for RTC_WKUP register ************************/ + +#define RTC_WKUP_WKSCAL_POSS 26U +#define RTC_WKUP_WKSCAL_POSE 29U +#define RTC_WKUP_WKSCAL_MSK BITS(RTC_WKUP_WKSCAL_POSS,RTC_WKUP_WKSCAL_POSE) +#define RTC_WKUP_WKSCAL RTC_WKUP_WKSCAL_MSK + +#define RTC_WKUP_WKSEL_POSS 24U +#define RTC_WKUP_WKSEL_POSE 25U +#define RTC_WKUP_WKSEL_MSK BITS(RTC_WKUP_WKSEL_POSS,RTC_WKUP_WKSEL_POSE) +#define RTC_WKUP_WKSEL RTC_WKUP_WKSEL_MSK + +#define RTC_WKUP_WKCAL_POSS 0U +#define RTC_WKUP_WKCAL_POSE 23U +#define RTC_WKUP_WKCAL_MSK BITS(RTC_WKUP_WKCAL_POSS,RTC_WKUP_WKCAL_POSE) +#define RTC_WKUP_WKCAL RTC_WKUP_WKCAL_MSK + +/****************** Bit definition for RTC_TIME register ************************/ + +#define RTC_TIME_WEEK_POSS 24U +#define RTC_TIME_WEEK_POSE 26U +#define RTC_TIME_WEEK_MSK BITS(RTC_TIME_WEEK_POSS,RTC_TIME_WEEK_POSE) +#define RTC_TIME_WEEK RTC_TIME_WEEK_MSK + +#define RTC_TIME_HOUR_T_POSS 20U +#define RTC_TIME_HOUR_T_POSE 21U +#define RTC_TIME_HOUR_T_MSK BITS(RTC_TIME_HOUR_T_POSS,RTC_TIME_HOUR_T_POSE) +#define RTC_TIME_HOUR_T RTC_TIME_HOUR_T_MSK + +#define RTC_TIME_HOUR_U_POSS 16U +#define RTC_TIME_HOUR_U_POSE 19U +#define RTC_TIME_HOUR_U_MSK BITS(RTC_TIME_HOUR_U_POSS,RTC_TIME_HOUR_U_POSE) +#define RTC_TIME_HOUR_U RTC_TIME_HOUR_U_MSK + +#define RTC_TIME_MIN_T_POSS 12U +#define RTC_TIME_MIN_T_POSE 14U +#define RTC_TIME_MIN_T_MSK BITS(RTC_TIME_MIN_T_POSS,RTC_TIME_MIN_T_POSE) +#define RTC_TIME_MIN_T RTC_TIME_MIN_T_MSK + +#define RTC_TIME_MIN_U_POSS 8U +#define RTC_TIME_MIN_U_POSE 11U +#define RTC_TIME_MIN_U_MSK BITS(RTC_TIME_MIN_U_POSS,RTC_TIME_MIN_U_POSE) +#define RTC_TIME_MIN_U RTC_TIME_MIN_U_MSK + +#define RTC_TIME_SEC_T_POSS 4U +#define RTC_TIME_SEC_T_POSE 6U +#define RTC_TIME_SEC_T_MSK BITS(RTC_TIME_SEC_T_POSS,RTC_TIME_SEC_T_POSE) +#define RTC_TIME_SEC_T RTC_TIME_SEC_T_MSK + +#define RTC_TIME_SEC_U_POSS 0U +#define RTC_TIME_SEC_U_POSE 3U +#define RTC_TIME_SEC_U_MSK BITS(RTC_TIME_SEC_U_POSS,RTC_TIME_SEC_U_POSE) +#define RTC_TIME_SEC_U RTC_TIME_SEC_U_MSK + +/****************** Bit definition for RTC_CAL register ************************/ + +#define RTC_CAL_YEAR_T_POSS 20U +#define RTC_CAL_YEAR_T_POSE 23U +#define RTC_CAL_YEAR_T_MSK BITS(RTC_CAL_YEAR_T_POSS,RTC_CAL_YEAR_T_POSE) +#define RTC_CAL_YEAR_T RTC_CAL_YEAR_T_MSK + +#define RTC_CAL_YEAR_U_POSS 16U +#define RTC_CAL_YEAR_U_POSE 19U +#define RTC_CAL_YEAR_U_MSK BITS(RTC_CAL_YEAR_U_POSS,RTC_CAL_YEAR_U_POSE) +#define RTC_CAL_YEAR_U RTC_CAL_YEAR_U_MSK + +#define RTC_CAL_MON_T_POS 12U +#define RTC_CAL_MON_T_MSK BIT(RTC_CAL_MON_T_POS) +#define RTC_CAL_MON_T RTC_CAL_MON_T_MSK + +#define RTC_CAL_MON_U_POSS 8U +#define RTC_CAL_MON_U_POSE 11U +#define RTC_CAL_MON_U_MSK BITS(RTC_CAL_MON_U_POSS,RTC_CAL_MON_U_POSE) +#define RTC_CAL_MON_U RTC_CAL_MON_U_MSK + +#define RTC_CAL_DATE_T_POSS 4U +#define RTC_CAL_DATE_T_POSE 5U +#define RTC_CAL_DATE_T_MSK BITS(RTC_CAL_DATE_T_POSS,RTC_CAL_DATE_T_POSE) +#define RTC_CAL_DATE_T RTC_CAL_DATE_T_MSK + +#define RTC_CAL_DATE_U_POSS 0U +#define RTC_CAL_DATE_U_POSE 3U +#define RTC_CAL_DATE_U_MSK BITS(RTC_CAL_DATE_U_POSS,RTC_CAL_DATE_U_POSE) +#define RTC_CAL_DATE_U RTC_CAL_DATE_U_MSK + +/****************** Bit definition for RTC_CALIB register ************************/ + +#define RTC_CALIB_CALIB_POSS 16U +#define RTC_CALIB_CALIB_POSE 31U +#define RTC_CALIB_CALIB_MSK BITS(RTC_CALIB_CALIB_POSS,RTC_CALIB_CALIB_POSE) +#define RTC_CALIB_CALIB RTC_CALIB_CALIB_MSK + +#define RTC_CALIB_MODE_POS 1U +#define RTC_CALIB_MODE_MSK BIT(RTC_CALIB_MODE_POS) +#define RTC_CALIB_MODE RTC_CALIB_MODE_MSK + +#define RTC_CALIB_CALIBEN_POS 0U +#define RTC_CALIB_CALIBEN_MSK BIT(RTC_CALIB_CALIBEN_POS) +#define RTC_CALIB_CALIBEN RTC_CALIB_CALIBEN_MSK + +/****************** Bit definition for RTC_ALTIME register ************************/ + +#define RTC_ALTIME_WEEK_POSS 24U +#define RTC_ALTIME_WEEK_POSE 26U +#define RTC_ALTIME_WEEK_MSK BITS(RTC_ALTIME_WEEK_POSS,RTC_ALTIME_WEEK_POSE) +#define RTC_ALTIME_WEEK RTC_ALTIME_WEEK_MSK + +#define RTC_ALTIME_HOUR_T_POSS 20U +#define RTC_ALTIME_HOUR_T_POSE 21U +#define RTC_ALTIME_HOUR_T_MSK BITS(RTC_ALTIME_HOUR_T_POSS,RTC_ALTIME_HOUR_T_POSE) +#define RTC_ALTIME_HOUR_T RTC_ALTIME_HOUR_T_MSK + +#define RTC_ALTIME_HOUR_U_POSS 16U +#define RTC_ALTIME_HOUR_U_POSE 19U +#define RTC_ALTIME_HOUR_U_MSK BITS(RTC_ALTIME_HOUR_U_POSS,RTC_ALTIME_HOUR_U_POSE) +#define RTC_ALTIME_HOUR_U RTC_ALTIME_HOUR_U_MSK + +#define RTC_ALTIME_MIN_T_POSS 12U +#define RTC_ALTIME_MIN_T_POSE 14U +#define RTC_ALTIME_MIN_T_MSK BITS(RTC_ALTIME_MIN_T_POSS,RTC_ALTIME_MIN_T_POSE) +#define RTC_ALTIME_MIN_T RTC_ALTIME_MIN_T_MSK + +#define RTC_ALTIME_MIN_U_POSS 8U +#define RTC_ALTIME_MIN_U_POSE 11U +#define RTC_ALTIME_MIN_U_MSK BITS(RTC_ALTIME_MIN_U_POSS,RTC_ALTIME_MIN_U_POSE) +#define RTC_ALTIME_MIN_U RTC_ALTIME_MIN_U_MSK + +#define RTC_ALTIME_SEC_T_POSS 4U +#define RTC_ALTIME_SEC_T_POSE 6U +#define RTC_ALTIME_SEC_T_MSK BITS(RTC_ALTIME_SEC_T_POSS,RTC_ALTIME_SEC_T_POSE) +#define RTC_ALTIME_SEC_T RTC_ALTIME_SEC_T_MSK + +#define RTC_ALTIME_SEC_U_POSS 0U +#define RTC_ALTIME_SEC_U_POSE 3U +#define RTC_ALTIME_SEC_U_MSK BITS(RTC_ALTIME_SEC_U_POSS,RTC_ALTIME_SEC_U_POSE) +#define RTC_ALTIME_SEC_U RTC_ALTIME_SEC_U_MSK + +/****************** Bit definition for RTC_ALCAL register ************************/ + +#define RTC_ALCAL_YEAR_T_POSS 20U +#define RTC_ALCAL_YEAR_T_POSE 23U +#define RTC_ALCAL_YEAR_T_MSK BITS(RTC_ALCAL_YEAR_T_POSS,RTC_ALCAL_YEAR_T_POSE) +#define RTC_ALCAL_YEAR_T RTC_ALCAL_YEAR_T_MSK + +#define RTC_ALCAL_YEAR_U_POSS 16U +#define RTC_ALCAL_YEAR_U_POSE 19U +#define RTC_ALCAL_YEAR_U_MSK BITS(RTC_ALCAL_YEAR_U_POSS,RTC_ALCAL_YEAR_U_POSE) +#define RTC_ALCAL_YEAR_U RTC_ALCAL_YEAR_U_MSK + +#define RTC_ALCAL_MON_T_POS 12U +#define RTC_ALCAL_MON_T_MSK BIT(RTC_ALCAL_MON_T_POS) +#define RTC_ALCAL_MON_T RTC_ALCAL_MON_T_MSK + +#define RTC_ALCAL_MON_U_POSS 8U +#define RTC_ALCAL_MON_U_POSE 11U +#define RTC_ALCAL_MON_U_MSK BITS(RTC_ALCAL_MON_U_POSS,RTC_ALCAL_MON_U_POSE) +#define RTC_ALCAL_MON_U RTC_ALCAL_MON_U_MSK + +#define RTC_ALCAL_DATE_T_POSS 4U +#define RTC_ALCAL_DATE_T_POSE 5U +#define RTC_ALCAL_DATE_T_MSK BITS(RTC_ALCAL_DATE_T_POSS,RTC_ALCAL_DATE_T_POSE) +#define RTC_ALCAL_DATE_T RTC_ALCAL_DATE_T_MSK + +#define RTC_ALCAL_DATE_U_POSS 0U +#define RTC_ALCAL_DATE_U_POSE 3U +#define RTC_ALCAL_DATE_U_MSK BITS(RTC_ALCAL_DATE_U_POSS,RTC_ALCAL_DATE_U_POSE) +#define RTC_ALCAL_DATE_U RTC_ALCAL_DATE_U_MSK + +/****************** Bit definition for RTC_ALEN register ************************/ + +#define RTC_ALEN_YEAR_POS 6U +#define RTC_ALEN_YEAR_MSK BIT(RTC_ALEN_YEAR_POS) +#define RTC_ALEN_YEAR RTC_ALEN_YEAR_MSK + +#define RTC_ALEN_MONTH_POS 5U +#define RTC_ALEN_MONTH_MSK BIT(RTC_ALEN_MONTH_POS) +#define RTC_ALEN_MONTH RTC_ALEN_MONTH_MSK + +#define RTC_ALEN_DATE_POS 4U +#define RTC_ALEN_DATE_MSK BIT(RTC_ALEN_DATE_POS) +#define RTC_ALEN_DATE RTC_ALEN_DATE_MSK + +#define RTC_ALEN_WEEK_POS 3U +#define RTC_ALEN_WEEK_MSK BIT(RTC_ALEN_WEEK_POS) +#define RTC_ALEN_WEEK RTC_ALEN_WEEK_MSK + +#define RTC_ALEN_HOUR_POS 2U +#define RTC_ALEN_HOUR_MSK BIT(RTC_ALEN_HOUR_POS) +#define RTC_ALEN_HOUR RTC_ALEN_HOUR_MSK + +#define RTC_ALEN_MIN_POS 1U +#define RTC_ALEN_MIN_MSK BIT(RTC_ALEN_MIN_POS) +#define RTC_ALEN_MIN RTC_ALEN_MIN_MSK + +#define RTC_ALEN_SEC_POS 0U +#define RTC_ALEN_SEC_MSK BIT(RTC_ALEN_SEC_POS) +#define RTC_ALEN_SEC RTC_ALEN_SEC_MSK + +/****************** Bit definition for RTC_TRIG register ************************/ + +#define RTC_TRIG_WKTM_POS 16U +#define RTC_TRIG_WKTM_MSK BIT(RTC_TRIG_WKTM_POS) +#define RTC_TRIG_WKTM RTC_TRIG_WKTM_MSK + +#define RTC_TRIG_F1HZ_POS 15U +#define RTC_TRIG_F1HZ_MSK BIT(RTC_TRIG_F1HZ_POS) +#define RTC_TRIG_F1HZ RTC_TRIG_F1HZ_MSK + +#define RTC_TRIG_RYEAR_POS 14U +#define RTC_TRIG_RYEAR_MSK BIT(RTC_TRIG_RYEAR_POS) +#define RTC_TRIG_RYEAR RTC_TRIG_RYEAR_MSK + +#define RTC_TRIG_RMON_POS 13U +#define RTC_TRIG_RMON_MSK BIT(RTC_TRIG_RMON_POS) +#define RTC_TRIG_RMON RTC_TRIG_RMON_MSK + +#define RTC_TRIG_RDATE_POS 12U +#define RTC_TRIG_RDATE_MSK BIT(RTC_TRIG_RDATE_POS) +#define RTC_TRIG_RDATE RTC_TRIG_RDATE_MSK + +#define RTC_TRIG_RWEEK_POS 11U +#define RTC_TRIG_RWEEK_MSK BIT(RTC_TRIG_RWEEK_POS) +#define RTC_TRIG_RWEEK RTC_TRIG_RWEEK_MSK + +#define RTC_TRIG_RHOUR_POS 10U +#define RTC_TRIG_RHOUR_MSK BIT(RTC_TRIG_RHOUR_POS) +#define RTC_TRIG_RHOUR RTC_TRIG_RHOUR_MSK + +#define RTC_TRIG_RMIN_POS 9U +#define RTC_TRIG_RMIN_MSK BIT(RTC_TRIG_RMIN_POS) +#define RTC_TRIG_RMIN RTC_TRIG_RMIN_MSK + +#define RTC_TRIG_RSEC_POS 8U +#define RTC_TRIG_RSEC_MSK BIT(RTC_TRIG_RSEC_POS) +#define RTC_TRIG_RSEC RTC_TRIG_RSEC_MSK + +#define RTC_TRIG_AMALL_POS 7U +#define RTC_TRIG_AMALL_MSK BIT(RTC_TRIG_AMALL_POS) +#define RTC_TRIG_AMALL RTC_TRIG_AMALL_MSK + +#define RTC_TRIG_AYEAR_POS 6U +#define RTC_TRIG_AYEAR_MSK BIT(RTC_TRIG_AYEAR_POS) +#define RTC_TRIG_AYEAR RTC_TRIG_AYEAR_MSK + +#define RTC_TRIG_AMONTH_POS 5U +#define RTC_TRIG_AMONTH_MSK BIT(RTC_TRIG_AMONTH_POS) +#define RTC_TRIG_AMONTH RTC_TRIG_AMONTH_MSK + +#define RTC_TRIG_ADTAE_POS 4U +#define RTC_TRIG_ADTAE_MSK BIT(RTC_TRIG_ADTAE_POS) +#define RTC_TRIG_ADTAE RTC_TRIG_ADTAE_MSK + +#define RTC_TRIG_AWEEK_POS 3U +#define RTC_TRIG_AWEEK_MSK BIT(RTC_TRIG_AWEEK_POS) +#define RTC_TRIG_AWEEK RTC_TRIG_AWEEK_MSK + +#define RTC_TRIG_AHOUR_POS 2U +#define RTC_TRIG_AHOUR_MSK BIT(RTC_TRIG_AHOUR_POS) +#define RTC_TRIG_AHOUR RTC_TRIG_AHOUR_MSK + +#define RTC_TRIG_AMIN_POS 1U +#define RTC_TRIG_AMIN_MSK BIT(RTC_TRIG_AMIN_POS) +#define RTC_TRIG_AMIN RTC_TRIG_AMIN_MSK + +#define RTC_TRIG_ASEC_POS 0U +#define RTC_TRIG_ASEC_MSK BIT(RTC_TRIG_ASEC_POS) +#define RTC_TRIG_ASEC RTC_TRIG_ASEC_MSK + +/****************** Bit definition for RTC_IER register ************************/ + +#define RTC_IER_WKTM_POS 16U +#define RTC_IER_WKTM_MSK BIT(RTC_IER_WKTM_POS) +#define RTC_IER_WKTM RTC_IER_WKTM_MSK + +#define RTC_IER_F1HZ_POS 15U +#define RTC_IER_F1HZ_MSK BIT(RTC_IER_F1HZ_POS) +#define RTC_IER_F1HZ RTC_IER_F1HZ_MSK + +#define RTC_IER_RYEAR_POS 14U +#define RTC_IER_RYEAR_MSK BIT(RTC_IER_RYEAR_POS) +#define RTC_IER_RYEAR RTC_IER_RYEAR_MSK + +#define RTC_IER_RMON_POS 13U +#define RTC_IER_RMON_MSK BIT(RTC_IER_RMON_POS) +#define RTC_IER_RMON RTC_IER_RMON_MSK + +#define RTC_IER_RDATE_POS 12U +#define RTC_IER_RDATE_MSK BIT(RTC_IER_RDATE_POS) +#define RTC_IER_RDATE RTC_IER_RDATE_MSK + +#define RTC_IER_RWEEK_POS 11U +#define RTC_IER_RWEEK_MSK BIT(RTC_IER_RWEEK_POS) +#define RTC_IER_RWEEK RTC_IER_RWEEK_MSK + +#define RTC_IER_RHOUR_POS 10U +#define RTC_IER_RHOUR_MSK BIT(RTC_IER_RHOUR_POS) +#define RTC_IER_RHOUR RTC_IER_RHOUR_MSK + +#define RTC_IER_RMIN_POS 9U +#define RTC_IER_RMIN_MSK BIT(RTC_IER_RMIN_POS) +#define RTC_IER_RMIN RTC_IER_RMIN_MSK + +#define RTC_IER_RSEC_POS 8U +#define RTC_IER_RSEC_MSK BIT(RTC_IER_RSEC_POS) +#define RTC_IER_RSEC RTC_IER_RSEC_MSK + +#define RTC_IER_AMALL_POS 7U +#define RTC_IER_AMALL_MSK BIT(RTC_IER_AMALL_POS) +#define RTC_IER_AMALL RTC_IER_AMALL_MSK + +#define RTC_IER_AYEAR_POS 6U +#define RTC_IER_AYEAR_MSK BIT(RTC_IER_AYEAR_POS) +#define RTC_IER_AYEAR RTC_IER_AYEAR_MSK + +#define RTC_IER_AMONTH_POS 5U +#define RTC_IER_AMONTH_MSK BIT(RTC_IER_AMONTH_POS) +#define RTC_IER_AMONTH RTC_IER_AMONTH_MSK + +#define RTC_IER_ADTAE_POS 4U +#define RTC_IER_ADTAE_MSK BIT(RTC_IER_ADTAE_POS) +#define RTC_IER_ADTAE RTC_IER_ADTAE_MSK + +#define RTC_IER_AWEEK_POS 3U +#define RTC_IER_AWEEK_MSK BIT(RTC_IER_AWEEK_POS) +#define RTC_IER_AWEEK RTC_IER_AWEEK_MSK + +#define RTC_IER_AHOUR_POS 2U +#define RTC_IER_AHOUR_MSK BIT(RTC_IER_AHOUR_POS) +#define RTC_IER_AHOUR RTC_IER_AHOUR_MSK + +#define RTC_IER_AMIN_POS 1U +#define RTC_IER_AMIN_MSK BIT(RTC_IER_AMIN_POS) +#define RTC_IER_AMIN RTC_IER_AMIN_MSK + +#define RTC_IER_ASEC_POS 0U +#define RTC_IER_ASEC_MSK BIT(RTC_IER_ASEC_POS) +#define RTC_IER_ASEC RTC_IER_ASEC_MSK + +/****************** Bit definition for RTC_IDR register ************************/ + +#define RTC_IDR_WKTM_POS 16U +#define RTC_IDR_WKTM_MSK BIT(RTC_IDR_WKTM_POS) +#define RTC_IDR_WKTM RTC_IDR_WKTM_MSK + +#define RTC_IDR_F1HZ_POS 15U +#define RTC_IDR_F1HZ_MSK BIT(RTC_IDR_F1HZ_POS) +#define RTC_IDR_F1HZ RTC_IDR_F1HZ_MSK + +#define RTC_IDR_RYEAR_POS 14U +#define RTC_IDR_RYEAR_MSK BIT(RTC_IDR_RYEAR_POS) +#define RTC_IDR_RYEAR RTC_IDR_RYEAR_MSK + +#define RTC_IDR_RMON_POS 13U +#define RTC_IDR_RMON_MSK BIT(RTC_IDR_RMON_POS) +#define RTC_IDR_RMON RTC_IDR_RMON_MSK + +#define RTC_IDR_RDATE_POS 12U +#define RTC_IDR_RDATE_MSK BIT(RTC_IDR_RDATE_POS) +#define RTC_IDR_RDATE RTC_IDR_RDATE_MSK + +#define RTC_IDR_RWEEK_POS 11U +#define RTC_IDR_RWEEK_MSK BIT(RTC_IDR_RWEEK_POS) +#define RTC_IDR_RWEEK RTC_IDR_RWEEK_MSK + +#define RTC_IDR_RHOUR_POS 10U +#define RTC_IDR_RHOUR_MSK BIT(RTC_IDR_RHOUR_POS) +#define RTC_IDR_RHOUR RTC_IDR_RHOUR_MSK + +#define RTC_IDR_RMIN_POS 9U +#define RTC_IDR_RMIN_MSK BIT(RTC_IDR_RMIN_POS) +#define RTC_IDR_RMIN RTC_IDR_RMIN_MSK + +#define RTC_IDR_RSEC_POS 8U +#define RTC_IDR_RSEC_MSK BIT(RTC_IDR_RSEC_POS) +#define RTC_IDR_RSEC RTC_IDR_RSEC_MSK + +#define RTC_IDR_AMALL_POS 7U +#define RTC_IDR_AMALL_MSK BIT(RTC_IDR_AMALL_POS) +#define RTC_IDR_AMALL RTC_IDR_AMALL_MSK + +#define RTC_IDR_AYEAR_POS 6U +#define RTC_IDR_AYEAR_MSK BIT(RTC_IDR_AYEAR_POS) +#define RTC_IDR_AYEAR RTC_IDR_AYEAR_MSK + +#define RTC_IDR_AMONTH_POS 5U +#define RTC_IDR_AMONTH_MSK BIT(RTC_IDR_AMONTH_POS) +#define RTC_IDR_AMONTH RTC_IDR_AMONTH_MSK + +#define RTC_IDR_ADTAE_POS 4U +#define RTC_IDR_ADTAE_MSK BIT(RTC_IDR_ADTAE_POS) +#define RTC_IDR_ADTAE RTC_IDR_ADTAE_MSK + +#define RTC_IDR_AWEEK_POS 3U +#define RTC_IDR_AWEEK_MSK BIT(RTC_IDR_AWEEK_POS) +#define RTC_IDR_AWEEK RTC_IDR_AWEEK_MSK + +#define RTC_IDR_AHOUR_POS 2U +#define RTC_IDR_AHOUR_MSK BIT(RTC_IDR_AHOUR_POS) +#define RTC_IDR_AHOUR RTC_IDR_AHOUR_MSK + +#define RTC_IDR_AMIN_POS 1U +#define RTC_IDR_AMIN_MSK BIT(RTC_IDR_AMIN_POS) +#define RTC_IDR_AMIN RTC_IDR_AMIN_MSK + +#define RTC_IDR_ASEC_POS 0U +#define RTC_IDR_ASEC_MSK BIT(RTC_IDR_ASEC_POS) +#define RTC_IDR_ASEC RTC_IDR_ASEC_MSK +/****************** Bit definition for RTC_IVS register ************************/ + +#define RTC_IVS_WKTM_POS 16U +#define RTC_IVS_WKTM_MSK BIT(RTC_IVS_WKTM_POS) +#define RTC_IVS_WKTM RTC_IVS_WKTM_MSK + +#define RTC_IVS_F1HZ_POS 15U +#define RTC_IVS_F1HZ_MSK BIT(RTC_IVS_F1HZ_POS) +#define RTC_IVS_F1HZ RTC_IVS_F1HZ_MSK + +#define RTC_IVS_RYEAR_POS 14U +#define RTC_IVS_RYEAR_MSK BIT(RTC_IVS_RYEAR_POS) +#define RTC_IVS_RYEAR RTC_IVS_RYEAR_MSK + +#define RTC_IVS_RMON_POS 13U +#define RTC_IVS_RMON_MSK BIT(RTC_IVS_RMON_POS) +#define RTC_IVS_RMON RTC_IVS_RMON_MSK + +#define RTC_IVS_RDATE_POS 12U +#define RTC_IVS_RDATE_MSK BIT(RTC_IVS_RDATE_POS) +#define RTC_IVS_RDATE RTC_IVS_RDATE_MSK + +#define RTC_IVS_RWEEK_POS 11U +#define RTC_IVS_RWEEK_MSK BIT(RTC_IVS_RWEEK_POS) +#define RTC_IVS_RWEEK RTC_IVS_RWEEK_MSK + +#define RTC_IVS_RHOUR_POS 10U +#define RTC_IVS_RHOUR_MSK BIT(RTC_IVS_RHOUR_POS) +#define RTC_IVS_RHOUR RTC_IVS_RHOUR_MSK + +#define RTC_IVS_RMIN_POS 9U +#define RTC_IVS_RMIN_MSK BIT(RTC_IVS_RMIN_POS) +#define RTC_IVS_RMIN RTC_IVS_RMIN_MSK + +#define RTC_IVS_RSEC_POS 8U +#define RTC_IVS_RSEC_MSK BIT(RTC_IVS_RSEC_POS) +#define RTC_IVS_RSEC RTC_IVS_RSEC_MSK + +#define RTC_IVS_AMALL_POS 7U +#define RTC_IVS_AMALL_MSK BIT(RTC_IVS_AMALL_POS) +#define RTC_IVS_AMALL RTC_IVS_AMALL_MSK + +#define RTC_IVS_AYEAR_POS 6U +#define RTC_IVS_AYEAR_MSK BIT(RTC_IVS_AYEAR_POS) +#define RTC_IVS_AYEAR RTC_IVS_AYEAR_MSK + +#define RTC_IVS_AMONTH_POS 5U +#define RTC_IVS_AMONTH_MSK BIT(RTC_IVS_AMONTH_POS) +#define RTC_IVS_AMONTH RTC_IVS_AMONTH_MSK + +#define RTC_IVS_ADTAE_POS 4U +#define RTC_IVS_ADTAE_MSK BIT(RTC_IVS_ADTAE_POS) +#define RTC_IVS_ADTAE RTC_IVS_ADTAE_MSK + +#define RTC_IVS_AWEEK_POS 3U +#define RTC_IVS_AWEEK_MSK BIT(RTC_IVS_AWEEK_POS) +#define RTC_IVS_AWEEK RTC_IVS_AWEEK_MSK + +#define RTC_IVS_AHOUR_POS 2U +#define RTC_IVS_AHOUR_MSK BIT(RTC_IVS_AHOUR_POS) +#define RTC_IVS_AHOUR RTC_IVS_AHOUR_MSK + +#define RTC_IVS_AMIN_POS 1U +#define RTC_IVS_AMIN_MSK BIT(RTC_IVS_AMIN_POS) +#define RTC_IVS_AMIN RTC_IVS_AMIN_MSK + +#define RTC_IVS_ASEC_POS 0U +#define RTC_IVS_ASEC_MSK BIT(RTC_IVS_ASEC_POS) +#define RTC_IVS_ASEC RTC_IVS_ASEC_MSK + +/****************** Bit definition for RTC_RIF register ************************/ + +#define RTC_RIF_WKTM_POS 16U +#define RTC_RIF_WKTM_MSK BIT(RTC_RIF_WKTM_POS) +#define RTC_RIF_WKTM RTC_RIF_WKTM_MSK + +#define RTC_RIF_F1HZ_POS 15U +#define RTC_RIF_F1HZ_MSK BIT(RTC_RIF_F1HZ_POS) +#define RTC_RIF_F1HZ RTC_RIF_F1HZ_MSK + +#define RTC_RIF_RYEAR_POS 14U +#define RTC_RIF_RYEAR_MSK BIT(RTC_RIF_RYEAR_POS) +#define RTC_RIF_RYEAR RTC_RIF_RYEAR_MSK + +#define RTC_RIF_RMON_POS 13U +#define RTC_RIF_RMON_MSK BIT(RTC_RIF_RMON_POS) +#define RTC_RIF_RMON RTC_RIF_RMON_MSK + +#define RTC_RIF_RDATE_POS 12U +#define RTC_RIF_RDATE_MSK BIT(RTC_RIF_RDATE_POS) +#define RTC_RIF_RDATE RTC_RIF_RDATE_MSK + +#define RTC_RIF_RWEEK_POS 11U +#define RTC_RIF_RWEEK_MSK BIT(RTC_RIF_RWEEK_POS) +#define RTC_RIF_RWEEK RTC_RIF_RWEEK_MSK + +#define RTC_RIF_RHOUR_POS 10U +#define RTC_RIF_RHOUR_MSK BIT(RTC_RIF_RHOUR_POS) +#define RTC_RIF_RHOUR RTC_RIF_RHOUR_MSK + +#define RTC_RIF_RMIN_POS 9U +#define RTC_RIF_RMIN_MSK BIT(RTC_RIF_RMIN_POS) +#define RTC_RIF_RMIN RTC_RIF_RMIN_MSK + +#define RTC_RIF_RSEC_POS 8U +#define RTC_RIF_RSEC_MSK BIT(RTC_RIF_RSEC_POS) +#define RTC_RIF_RSEC RTC_RIF_RSEC_MSK + +#define RTC_RIF_AMALL_POS 7U +#define RTC_RIF_AMALL_MSK BIT(RTC_RIF_AMALL_POS) +#define RTC_RIF_AMALL RTC_RIF_AMALL_MSK + +#define RTC_RIF_AYEAR_POS 6U +#define RTC_RIF_AYEAR_MSK BIT(RTC_RIF_AYEAR_POS) +#define RTC_RIF_AYEAR RTC_RIF_AYEAR_MSK + +#define RTC_RIF_AMONTH_POS 5U +#define RTC_RIF_AMONTH_MSK BIT(RTC_RIF_AMONTH_POS) +#define RTC_RIF_AMONTH RTC_RIF_AMONTH_MSK + +#define RTC_RIF_ADTAE_POS 4U +#define RTC_RIF_ADTAE_MSK BIT(RTC_RIF_ADTAE_POS) +#define RTC_RIF_ADTAE RTC_RIF_ADTAE_MSK + +#define RTC_RIF_AWEEK_POS 3U +#define RTC_RIF_AWEEK_MSK BIT(RTC_RIF_AWEEK_POS) +#define RTC_RIF_AWEEK RTC_RIF_AWEEK_MSK + +#define RTC_RIF_AHOUR_POS 2U +#define RTC_RIF_AHOUR_MSK BIT(RTC_RIF_AHOUR_POS) +#define RTC_RIF_AHOUR RTC_RIF_AHOUR_MSK + +#define RTC_RIF_AMIN_POS 1U +#define RTC_RIF_AMIN_MSK BIT(RTC_RIF_AMIN_POS) +#define RTC_RIF_AMIN RTC_RIF_AMIN_MSK + +#define RTC_RIF_ASEC_POS 0U +#define RTC_RIF_ASEC_MSK BIT(RTC_RIF_ASEC_POS) +#define RTC_RIF_ASEC RTC_RIF_ASEC_MSK + +/****************** Bit definition for RTC_IFM register ************************/ + +#define RTC_IFM_WKTM_POS 16U +#define RTC_IFM_WKTM_MSK BIT(RTC_IFM_WKTM_POS) +#define RTC_IFM_WKTM RTC_IFM_WKTM_MSK + +#define RTC_IFM_F1HZ_POS 15U +#define RTC_IFM_F1HZ_MSK BIT(RTC_IFM_F1HZ_POS) +#define RTC_IFM_F1HZ RTC_IFM_F1HZ_MSK + +#define RTC_IFM_RYEAR_POS 14U +#define RTC_IFM_RYEAR_MSK BIT(RTC_IFM_RYEAR_POS) +#define RTC_IFM_RYEAR RTC_IFM_RYEAR_MSK + +#define RTC_IFM_RMON_POS 13U +#define RTC_IFM_RMON_MSK BIT(RTC_IFM_RMON_POS) +#define RTC_IFM_RMON RTC_IFM_RMON_MSK + +#define RTC_IFM_RDATE_POS 12U +#define RTC_IFM_RDATE_MSK BIT(RTC_IFM_RDATE_POS) +#define RTC_IFM_RDATE RTC_IFM_RDATE_MSK + +#define RTC_IFM_RWEEK_POS 11U +#define RTC_IFM_RWEEK_MSK BIT(RTC_IFM_RWEEK_POS) +#define RTC_IFM_RWEEK RTC_IFM_RWEEK_MSK + +#define RTC_IFM_RHOUR_POS 10U +#define RTC_IFM_RHOUR_MSK BIT(RTC_IFM_RHOUR_POS) +#define RTC_IFM_RHOUR RTC_IFM_RHOUR_MSK + +#define RTC_IFM_RMIN_POS 9U +#define RTC_IFM_RMIN_MSK BIT(RTC_IFM_RMIN_POS) +#define RTC_IFM_RMIN RTC_IFM_RMIN_MSK + +#define RTC_IFM_RSEC_POS 8U +#define RTC_IFM_RSEC_MSK BIT(RTC_IFM_RSEC_POS) +#define RTC_IFM_RSEC RTC_IFM_RSEC_MSK + +#define RTC_IFM_AMALL_POS 7U +#define RTC_IFM_AMALL_MSK BIT(RTC_IFM_AMALL_POS) +#define RTC_IFM_AMALL RTC_IFM_AMALL_MSK + +#define RTC_IFM_AYEAR_POS 6U +#define RTC_IFM_AYEAR_MSK BIT(RTC_IFM_AYEAR_POS) +#define RTC_IFM_AYEAR RTC_IFM_AYEAR_MSK + +#define RTC_IFM_AMONTH_POS 5U +#define RTC_IFM_AMONTH_MSK BIT(RTC_IFM_AMONTH_POS) +#define RTC_IFM_AMONTH RTC_IFM_AMONTH_MSK + +#define RTC_IFM_ADTAE_POS 4U +#define RTC_IFM_ADTAE_MSK BIT(RTC_IFM_ADTAE_POS) +#define RTC_IFM_ADTAE RTC_IFM_ADTAE_MSK + +#define RTC_IFM_AWEEK_POS 3U +#define RTC_IFM_AWEEK_MSK BIT(RTC_IFM_AWEEK_POS) +#define RTC_IFM_AWEEK RTC_IFM_AWEEK_MSK + +#define RTC_IFM_AHOUR_POS 2U +#define RTC_IFM_AHOUR_MSK BIT(RTC_IFM_AHOUR_POS) +#define RTC_IFM_AHOUR RTC_IFM_AHOUR_MSK + +#define RTC_IFM_AMIN_POS 1U +#define RTC_IFM_AMIN_MSK BIT(RTC_IFM_AMIN_POS) +#define RTC_IFM_AMIN RTC_IFM_AMIN_MSK + +#define RTC_IFM_ASEC_POS 0U +#define RTC_IFM_ASEC_MSK BIT(RTC_IFM_ASEC_POS) +#define RTC_IFM_ASEC RTC_IFM_ASEC_MSK + +/****************** Bit definition for RTC_ICR register ************************/ + +#define RTC_ICR_WKTM_POS 16U +#define RTC_ICR_WKTM_MSK BIT(RTC_ICR_WKTM_POS) +#define RTC_ICR_WKTM RTC_ICR_WKTM_MSK + +#define RTC_ICR_F1HZ_POS 15U +#define RTC_ICR_F1HZ_MSK BIT(RTC_ICR_F1HZ_POS) +#define RTC_ICR_F1HZ RTC_ICR_F1HZ_MSK + +#define RTC_ICR_RYEAR_POS 14U +#define RTC_ICR_RYEAR_MSK BIT(RTC_ICR_RYEAR_POS) +#define RTC_ICR_RYEAR RTC_ICR_RYEAR_MSK + +#define RTC_ICR_RMON_POS 13U +#define RTC_ICR_RMON_MSK BIT(RTC_ICR_RMON_POS) +#define RTC_ICR_RMON RTC_ICR_RMON_MSK + +#define RTC_ICR_RDATE_POS 12U +#define RTC_ICR_RDATE_MSK BIT(RTC_ICR_RDATE_POS) +#define RTC_ICR_RDATE RTC_ICR_RDATE_MSK + +#define RTC_ICR_RWEEK_POS 11U +#define RTC_ICR_RWEEK_MSK BIT(RTC_ICR_RWEEK_POS) +#define RTC_ICR_RWEEK RTC_ICR_RWEEK_MSK + +#define RTC_ICR_RHOUR_POS 10U +#define RTC_ICR_RHOUR_MSK BIT(RTC_ICR_RHOUR_POS) +#define RTC_ICR_RHOUR RTC_ICR_RHOUR_MSK + +#define RTC_ICR_RMIN_POS 9U +#define RTC_ICR_RMIN_MSK BIT(RTC_ICR_RMIN_POS) +#define RTC_ICR_RMIN RTC_ICR_RMIN_MSK + +#define RTC_ICR_RSEC_POS 8U +#define RTC_ICR_RSEC_MSK BIT(RTC_ICR_RSEC_POS) +#define RTC_ICR_RSEC RTC_ICR_RSEC_MSK + +#define RTC_ICR_AMALL_POS 7U +#define RTC_ICR_AMALL_MSK BIT(RTC_ICR_AMALL_POS) +#define RTC_ICR_AMALL RTC_ICR_AMALL_MSK + +#define RTC_ICR_AYEAR_POS 6U +#define RTC_ICR_AYEAR_MSK BIT(RTC_ICR_AYEAR_POS) +#define RTC_ICR_AYEAR RTC_ICR_AYEAR_MSK + +#define RTC_ICR_AMONTH_POS 5U +#define RTC_ICR_AMONTH_MSK BIT(RTC_ICR_AMONTH_POS) +#define RTC_ICR_AMONTH RTC_ICR_AMONTH_MSK + +#define RTC_ICR_ADTAE_POS 4U +#define RTC_ICR_ADTAE_MSK BIT(RTC_ICR_ADTAE_POS) +#define RTC_ICR_ADTAE RTC_ICR_ADTAE_MSK + +#define RTC_ICR_AWEEK_POS 3U +#define RTC_ICR_AWEEK_MSK BIT(RTC_ICR_AWEEK_POS) +#define RTC_ICR_AWEEK RTC_ICR_AWEEK_MSK + +#define RTC_ICR_AHOUR_POS 2U +#define RTC_ICR_AHOUR_MSK BIT(RTC_ICR_AHOUR_POS) +#define RTC_ICR_AHOUR RTC_ICR_AHOUR_MSK + +#define RTC_ICR_AMIN_POS 1U +#define RTC_ICR_AMIN_MSK BIT(RTC_ICR_AMIN_POS) +#define RTC_ICR_AMIN RTC_ICR_AMIN_MSK + +#define RTC_ICR_ASEC_POS 0U +#define RTC_ICR_ASEC_MSK BIT(RTC_ICR_ASEC_POS) +#define RTC_ICR_ASEC RTC_ICR_ASEC_MSK + +/****************** Bit definition for RTC_STA register ************************/ + +#define RTC_STA_SYNDONE_POS 1U +#define RTC_STA_SYNDONE_MSK BIT(RTC_STA_SYNDONE_POS) +#define RTC_STA_SYNDONE RTC_STA_SYNDONE_MSK + +#define RTC_STA_EMPTY_POS 0U +#define RTC_STA_EMPTY_MSK BIT(RTC_STA_EMPTY_POS) +#define RTC_STA_EMPTY RTC_STA_EMPTY_MSK + +/****************** Bit definition for RTC_BKEN register ************************/ + +#define RTC_BKEN_BKEN_POS 0U +#define RTC_BKEN_BKEN_MSK BIT(RTC_BKEN_BKEN_POS) +#define RTC_BKEN_BKEN RTC_BKEN_BKEN_MSK + +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t WKUP; + __IO uint32_t TIME; + __IO uint32_t CAL; + __IO uint32_t CALIB; + uint32_t RESERVED14; + uint32_t RESERVED18; + uint32_t RESERVED1C; + __IO uint32_t ALTIME; + __IO uint32_t ALCAL; + __IO uint32_t ALEN; + __IO uint32_t TRIG; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + uint32_t RESERVED48; + uint32_t RESERVED4C; + __I uint32_t STA; + __IO uint32_t BKEN; +} RTC_TypeDef; + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_spi.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_spi.h new file mode 100644 index 00000000000..350c682546c --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_spi.h @@ -0,0 +1,598 @@ +/********************************************************************************** + * + * @file reg_spi.h + * @brief SPI Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __SPI_H__ +#define __SPI_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + +/****************** Bit definition for SPI_CON1 register ************************/ + +# define SPI_CON1_BIDEN_POS 15U +# define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) +# define SPI_CON1_BIDEN SPI_CON1_BIDEN_MSK + +# define SPI_CON1_BIDOEN_POS 14U +# define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) +# define SPI_CON1_BIDOEN SPI_CON1_BIDOEN_MSK + +# define SPI_CON1_CRCEN_POS 13U +# define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) +# define SPI_CON1_CRCEN SPI_CON1_CRCEN_MSK + +# define SPI_CON1_NXTCRC_POS 12U +# define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) +# define SPI_CON1_NXTCRC SPI_CON1_NXTCRC_MSK + +# define SPI_CON1_FLEN_POS 11U +# define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) +# define SPI_CON1_FLEN SPI_CON1_FLEN_MSK + +# define SPI_CON1_RXO_POS 10U +# define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) +# define SPI_CON1_RXO SPI_CON1_RXO_MSK + +# define SPI_CON1_SSEN_POS 9U +# define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) +# define SPI_CON1_SSEN SPI_CON1_SSEN_MSK + +# define SPI_CON1_SSOUT_POS 8U +# define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) +# define SPI_CON1_SSOUT SPI_CON1_SSOUT_MSK + +# define SPI_CON1_LSBFST_POS 7U +# define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) +# define SPI_CON1_LSBFST SPI_CON1_LSBFST_MSK + +# define SPI_CON1_SPIEN_POS 6U +# define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) +# define SPI_CON1_SPIEN SPI_CON1_SPIEN_MSK + +# define SPI_CON1_BAUD_POSS 3U +# define SPI_CON1_BAUD_POSE 5U +# define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS, SPI_CON1_BAUD_POSE) +# define SPI_CON1_BAUD SPI_CON1_BAUD_MSK + +# define SPI_CON1_MSTREN_POS 2U +# define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) +# define SPI_CON1_MSTREN SPI_CON1_MSTREN_MSK + +# define SPI_CON1_CPOL_POS 1U +# define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) +# define SPI_CON1_CPOL SPI_CON1_CPOL_MSK + +# define SPI_CON1_CPHA_POS 0U +# define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) +# define SPI_CON1_CPHA SPI_CON1_CPHA_MSK + +/****************** Bit definition for SPI_CON2 register ************************/ + +# define SPI_CON2_RXFTH_POSS 14U +# define SPI_CON2_RXFTH_POSE 15U +# define SPI_CON2_RXFTH_MSK BITS(SPI_CON2_RXFTH_POSS, SPI_CON2_RXFTH_POSE) +# define SPI_CON2_RXFTH SPI_CON2_RXFTH_MSK + +# define SPI_CON2_TXFTH_POSS 12U +# define SPI_CON2_TXFTH_POSE 13U +# define SPI_CON2_TXFTH_MSK BITS(SPI_CON2_TXFTH_POSS, SPI_CON2_TXFTH_POSE) +# define SPI_CON2_TXFTH SPI_CON2_TXFTH_MSK + +# define SPI_CON2_FRF_POS 4U +# define SPI_CON2_FRF_MSK BIT(SPI_CON2_FRF_POS) +# define SPI_CON2_FRF SPI_CON2_FRF_MSK + +# define SPI_CON2_NSSP_POS 3U +# define SPI_CON2_NSSP_MSK BIT(SPI_CON2_NSSP_POS) +# define SPI_CON2_NSSP SPI_CON2_NSSP_MSK + +# define SPI_CON2_NSSOE_POS 2U +# define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) +# define SPI_CON2_NSSOE SPI_CON2_NSSOE_MSK + +# define SPI_CON2_TXDMA_POS 1U +# define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) +# define SPI_CON2_TXDMA SPI_CON2_TXDMA_MSK + +# define SPI_CON2_RXDMA_POS 0U +# define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) +# define SPI_CON2_RXDMA SPI_CON2_RXDMA_MSK + +/****************** Bit definition for SPI_STAT register ************************/ + +# define SPI_STAT_RXFLV_POSS 24U +# define SPI_STAT_RXFLV_POSE 28U +# define SPI_STAT_RXFLV_MSK BITS(SPI_STAT_RXFLV_POSS, SPI_STAT_RXFLV_POSE) +# define SPI_STAT_RXFLV SPI_STAT_RXFLV_MSK + +# define SPI_STAT_TXFLV_POSS 16U +# define SPI_STAT_TXFLV_POSE 20U +# define SPI_STAT_TXFLV_MSK BITS(SPI_STAT_TXFLV_POSS, SPI_STAT_TXFLV_POSE) +# define SPI_STAT_TXFLV SPI_STAT_TXFLV_MSK + +# define SPI_STAT_BUSY_POS 15U +# define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) +# define SPI_STAT_BUSY SPI_STAT_BUSY_MSK + +# define SPI_STAT_CHSIDE_POS 14U +# define SPI_STAT_CHSIDE_MSK BIT(SPI_STAT_CHSIDE_POS) +# define SPI_STAT_CHSIDE SPI_STAT_CHSIDE_MSK + +# define SPI_STAT_RXTH_POS 12U +# define SPI_STAT_RXTH_MSK BIT(SPI_STAT_RXTH_POS) +# define SPI_STAT_RXTH SPI_STAT_RXTH_MSK + +# define SPI_STAT_RXUD_POS 11U +# define SPI_STAT_RXUD_MSK BIT(SPI_STAT_RXUD_POS) +# define SPI_STAT_RXUD SPI_STAT_RXUD_MSK + +# define SPI_STAT_RXOV_POS 10U +# define SPI_STAT_RXOV_MSK BIT(SPI_STAT_RXOV_POS) +# define SPI_STAT_RXOV SPI_STAT_RXOV_MSK + +# define SPI_STAT_RXF_POS 9U +# define SPI_STAT_RXF_MSK BIT(SPI_STAT_RXF_POS) +# define SPI_STAT_RXF SPI_STAT_RXF_MSK + +# define SPI_STAT_RXNE_POS 8U +# define SPI_STAT_RXNE_MSK BIT(SPI_STAT_RXNE_POS) +# define SPI_STAT_RXNE SPI_STAT_RXNE_MSK + +# define SPI_STAT_TXTH_POS 4U +# define SPI_STAT_TXTH_MSK BIT(SPI_STAT_TXTH_POS) +# define SPI_STAT_TXTH SPI_STAT_TXTH_MSK + +# define SPI_STAT_TXUD_POS 3U +# define SPI_STAT_TXUD_MSK BIT(SPI_STAT_TXUD_POS) +# define SPI_STAT_TXUD SPI_STAT_TXUD_MSK + +# define SPI_STAT_TXOV_POS 2U +# define SPI_STAT_TXOV_MSK BIT(SPI_STAT_TXOV_POS) +# define SPI_STAT_TXOV SPI_STAT_TXOV_MSK + +# define SPI_STAT_TXF_POS 1U +# define SPI_STAT_TXF_MSK BIT(SPI_STAT_TXF_POS) +# define SPI_STAT_TXF SPI_STAT_TXF_MSK + +# define SPI_STAT_TXE_POS 0U +# define SPI_STAT_TXE_MSK BIT(SPI_STAT_TXE_POS) +# define SPI_STAT_TXE SPI_STAT_TXE_MSK + +/****************** Bit definition for SPI_DATA register ************************/ + +# define SPI_DATA_DATA_POSS 0U +# define SPI_DATA_DATA_POSE 15U +# define SPI_DATA_DATA_MSK BITS(SPI_DATA_DATA_POSS, SPI_DATA_DATA_POSE) +# define SPI_DATA_DATA SPI_DATA_DATA_MSK + +/****************** Bit definition for SPI_CRCPOLY register ************************/ + +# define SPI_CRCPOLY_CRCPOLY_POSS 0U +# define SPI_CRCPOLY_CRCPOLY_POSE 15U +# define SPI_CRCPOLY_CRCPOLY_MSK BITS(SPI_CRCPOLY_CRCPOLY_POSS, SPI_CRCPOLY_CRCPOLY_POSE) +# define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_MSK + +/****************** Bit definition for SPI_RXCRC register ************************/ + +# define SPI_RXCRC_RXCRC_POSS 0U +# define SPI_RXCRC_RXCRC_POSE 15U +# define SPI_RXCRC_RXCRC_MSK BITS(SPI_RXCRC_RXCRC_POSS, SPI_RXCRC_RXCRC_POSE) +# define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_MSK + +/****************** Bit definition for SPI_TXCRC register ************************/ + +# define SPI_TXCRC_TXCRC_POSS 0U +# define SPI_TXCRC_TXCRC_POSE 15U +# define SPI_TXCRC_TXCRC_MSK BITS(SPI_TXCRC_TXCRC_POSS, SPI_TXCRC_TXCRC_POSE) +# define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_MSK + +/****************** Bit definition for SPI_I2SCFG register ************************/ + +# define SPI_I2SCFG_I2SMOD_POS 12U +# define SPI_I2SCFG_I2SMOD_MSK BIT(SPI_I2SCFG_I2SMOD_POS) +# define SPI_I2SCFG_I2SMOD SPI_I2SCFG_I2SMOD_MSK + +# define SPI_I2SCFG_I2SE_POS 11U +# define SPI_I2SCFG_I2SE_MSK BIT(SPI_I2SCFG_I2SE_POS) +# define SPI_I2SCFG_I2SE SPI_I2SCFG_I2SE_MSK + +# define SPI_I2SCFG_I2SCFG_POSS 8U +# define SPI_I2SCFG_I2SCFG_POSE 10U +# define SPI_I2SCFG_I2SCFG_MSK BITS(SPI_I2SCFG_I2SCFG_POSS, SPI_I2SCFG_I2SCFG_POSE) +# define SPI_I2SCFG_I2SCFG SPI_I2SCFG_I2SCFG_MSK + +# define SPI_I2SCFG_PCMSYNC_POS 7U +# define SPI_I2SCFG_PCMSYNC_MSK BIT(SPI_I2SCFG_PCMSYNC_POS) +# define SPI_I2SCFG_PCMSYNC SPI_I2SCFG_PCMSYNC_MSK + +# define SPI_I2SCFG_I2SSTD_POSS 4U +# define SPI_I2SCFG_I2SSTD_POSE 5U +# define SPI_I2SCFG_I2SSTD_MSK BITS(SPI_I2SCFG_I2SSTD_POSS, SPI_I2SCFG_I2SSTD_POSE) +# define SPI_I2SCFG_I2SSTD SPI_I2SCFG_I2SSTD_MSK + +# define SPI_I2SCFG_CKPOL_POS 3U +# define SPI_I2SCFG_CKPOL_MSK BIT(SPI_I2SCFG_CKPOL_POS) +# define SPI_I2SCFG_CKPOL SPI_I2SCFG_CKPOL_MSK + +# define SPI_I2SCFG_DATLEN_POSS 1U +# define SPI_I2SCFG_DATLEN_POSE 2U +# define SPI_I2SCFG_DATLEN_MSK BITS(SPI_I2SCFG_DATLEN_POSS, SPI_I2SCFG_DATLEN_POSE) +# define SPI_I2SCFG_DATLEN SPI_I2SCFG_DATLEN_MSK + +# define SPI_I2SCFG_CHLEN_POS 0U +# define SPI_I2SCFG_CHLEN_MSK BIT(SPI_I2SCFG_CHLEN_POS) +# define SPI_I2SCFG_CHLEN SPI_I2SCFG_CHLEN_MSK + +/****************** Bit definition for SPI_I2SPR register ************************/ + +# define SPI_I2SPR_EXTCKEN_POS 10U +# define SPI_I2SPR_EXTCKEN_MSK BIT(SPI_I2SPR_EXTCKEN_POS) +# define SPI_I2SPR_EXTCKEN SPI_I2SPR_EXTCKEN_MSK + +# define SPI_I2SPR_MCKOE_POS 9U +# define SPI_I2SPR_MCKOE_MSK BIT(SPI_I2SPR_MCKOE_POS) +# define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_MSK + +# define SPI_I2SPR_ODD_POS 8U +# define SPI_I2SPR_ODD_MSK BIT(SPI_I2SPR_ODD_POS) +# define SPI_I2SPR_ODD SPI_I2SPR_ODD_MSK + +# define SPI_I2SPR_I2SDIV_POSS 0U +# define SPI_I2SPR_I2SDIV_POSE 7U +# define SPI_I2SPR_I2SDIV_MSK BITS(SPI_I2SPR_I2SDIV_POSS, SPI_I2SPR_I2SDIV_POSE) +# define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_MSK + +/****************** Bit definition for SPI_IER register ************************/ + +# define SPI_IER_FRE_POS 18U +# define SPI_IER_FRE_MSK BIT(SPI_IER_FRE_POS) +# define SPI_IER_FRE SPI_IER_FRE_MSK + +# define SPI_IER_MODF_POS 17U +# define SPI_IER_MODF_MSK BIT(SPI_IER_MODF_POS) +# define SPI_IER_MODF SPI_IER_MODF_MSK + +# define SPI_IER_CRCERR_POS 16U +# define SPI_IER_CRCERR_MSK BIT(SPI_IER_CRCERR_POS) +# define SPI_IER_CRCERR SPI_IER_CRCERR_MSK + +# define SPI_IER_RXTH_POS 12U +# define SPI_IER_RXTH_MSK BIT(SPI_IER_RXTH_POS) +# define SPI_IER_RXTH SPI_IER_RXTH_MSK + +# define SPI_IER_RXUD_POS 11U +# define SPI_IER_RXUD_MSK BIT(SPI_IER_RXUD_POS) +# define SPI_IER_RXUD SPI_IER_RXUD_MSK + +# define SPI_IER_RXOV_POS 10U +# define SPI_IER_RXOV_MSK BIT(SPI_IER_RXOV_POS) +# define SPI_IER_RXOV SPI_IER_RXOV_MSK + +# define SPI_IER_RXF_POS 9U +# define SPI_IER_RXF_MSK BIT(SPI_IER_RXF_POS) +# define SPI_IER_RXF SPI_IER_RXF_MSK + +# define SPI_IER_RXNE_POS 8U +# define SPI_IER_RXNE_MSK BIT(SPI_IER_RXNE_POS) +# define SPI_IER_RXNE SPI_IER_RXNE_MSK + +# define SPI_IER_TXTH_POS 4U +# define SPI_IER_TXTH_MSK BIT(SPI_IER_TXTH_POS) +# define SPI_IER_TXTH SPI_IER_TXTH_MSK + +# define SPI_IER_TXUD_POS 3U +# define SPI_IER_TXUD_MSK BIT(SPI_IER_TXUD_POS) +# define SPI_IER_TXUD SPI_IER_TXUD_MSK + +# define SPI_IER_TXOV_POS 2U +# define SPI_IER_TXOV_MSK BIT(SPI_IER_TXOV_POS) +# define SPI_IER_TXOV SPI_IER_TXOV_MSK + +# define SPI_IER_TXE_POS 0U +# define SPI_IER_TXE_MSK BIT(SPI_IER_TXE_POS) +# define SPI_IER_TXE SPI_IER_TXE_MSK + +/****************** Bit definition for SPI_IDR register ************************/ + +# define SPI_IDR_FRE_POS 18U +# define SPI_IDR_FRE_MSK BIT(SPI_IDR_FRE_POS) +# define SPI_IDR_FRE SPI_IDR_FRE_MSK + +# define SPI_IDR_MODF_POS 17U +# define SPI_IDR_MODF_MSK BIT(SPI_IDR_MODF_POS) +# define SPI_IDR_MODF SPI_IDR_MODF_MSK + +# define SPI_IDR_CRCERR_POS 16U +# define SPI_IDR_CRCERR_MSK BIT(SPI_IDR_CRCERR_POS) +# define SPI_IDR_CRCERR SPI_IDR_CRCERR_MSK + +# define SPI_IDR_RXTH_POS 12U +# define SPI_IDR_RXTH_MSK BIT(SPI_IDR_RXTH_POS) +# define SPI_IDR_RXTH SPI_IDR_RXTH_MSK + +# define SPI_IDR_RXUD_POS 11U +# define SPI_IDR_RXUD_MSK BIT(SPI_IDR_RXUD_POS) +# define SPI_IDR_RXUD SPI_IDR_RXUD_MSK + +# define SPI_IDR_RXOV_POS 10U +# define SPI_IDR_RXOV_MSK BIT(SPI_IDR_RXOV_POS) +# define SPI_IDR_RXOV SPI_IDR_RXOV_MSK + +# define SPI_IDR_RXF_POS 9U +# define SPI_IDR_RXF_MSK BIT(SPI_IDR_RXF_POS) +# define SPI_IDR_RXF SPI_IDR_RXF_MSK + +# define SPI_IDR_RXNE_POS 8U +# define SPI_IDR_RXNE_MSK BIT(SPI_IDR_RXNE_POS) +# define SPI_IDR_RXNE SPI_IDR_RXNE_MSK + +# define SPI_IDR_TXTH_POS 4U +# define SPI_IDR_TXTH_MSK BIT(SPI_IDR_TXTH_POS) +# define SPI_IDR_TXTH SPI_IDR_TXTH_MSK + +# define SPI_IDR_TXUD_POS 3U +# define SPI_IDR_TXUD_MSK BIT(SPI_IDR_TXUD_POS) +# define SPI_IDR_TXUD SPI_IDR_TXUD_MSK + +# define SPI_IDR_TXOV_POS 2U +# define SPI_IDR_TXOV_MSK BIT(SPI_IDR_TXOV_POS) +# define SPI_IDR_TXOV SPI_IDR_TXOV_MSK + +# define SPI_IDR_TXE_POS 0U +# define SPI_IDR_TXE_MSK BIT(SPI_IDR_TXE_POS) +# define SPI_IDR_TXE SPI_IDR_TXE_MSK + +/****************** Bit definition for SPI_IVS register ************************/ + +# define SPI_IVS_FRE_POS 18U +# define SPI_IVS_FRE_MSK BIT(SPI_IVS_FRE_POS) +# define SPI_IVS_FRE SPI_IVS_FRE_MSK + +# define SPI_IVS_MODF_POS 17U +# define SPI_IVS_MODF_MSK BIT(SPI_IVS_MODF_POS) +# define SPI_IVS_MODF SPI_IVS_MODF_MSK + +# define SPI_IVS_CRCERR_POS 16U +# define SPI_IVS_CRCERR_MSK BIT(SPI_IVS_CRCERR_POS) +# define SPI_IVS_CRCERR SPI_IVS_CRCERR_MSK + +# define SPI_IVS_RXTH_POS 12U +# define SPI_IVS_RXTH_MSK BIT(SPI_IVS_RXTH_POS) +# define SPI_IVS_RXTH SPI_IVS_RXTH_MSK + +# define SPI_IVS_RXUD_POS 11U +# define SPI_IVS_RXUD_MSK BIT(SPI_IVS_RXUD_POS) +# define SPI_IVS_RXUD SPI_IVS_RXUD_MSK + +# define SPI_IVS_RXOV_POS 10U +# define SPI_IVS_RXOV_MSK BIT(SPI_IVS_RXOV_POS) +# define SPI_IVS_RXOV SPI_IVS_RXOV_MSK + +# define SPI_IVS_RXF_POS 9U +# define SPI_IVS_RXF_MSK BIT(SPI_IVS_RXF_POS) +# define SPI_IVS_RXF SPI_IVS_RXF_MSK + +# define SPI_IVS_RXNE_POS 8U +# define SPI_IVS_RXNE_MSK BIT(SPI_IVS_RXNE_POS) +# define SPI_IVS_RXNE SPI_IVS_RXNE_MSK + +# define SPI_IVS_TXTH_POS 4U +# define SPI_IVS_TXTH_MSK BIT(SPI_IVS_TXTH_POS) +# define SPI_IVS_TXTH SPI_IVS_TXTH_MSK + +# define SPI_IVS_TXUD_POS 3U +# define SPI_IVS_TXUD_MSK BIT(SPI_IVS_TXUD_POS) +# define SPI_IVS_TXUD SPI_IVS_TXUD_MSK + +# define SPI_IVS_TXOV_POS 2U +# define SPI_IVS_TXOV_MSK BIT(SPI_IVS_TXOV_POS) +# define SPI_IVS_TXOV SPI_IVS_TXOV_MSK + +# define SPI_IVS_TXE_POS 0U +# define SPI_IVS_TXE_MSK BIT(SPI_IVS_TXE_POS) +# define SPI_IVS_TXE SPI_IVS_TXE_MSK + +/****************** Bit definition for SPI_RIF register ************************/ + +# define SPI_RIF_FRE_POS 18U +# define SPI_RIF_FRE_MSK BIT(SPI_RIF_FRE_POS) +# define SPI_RIF_FRE SPI_RIF_FRE_MSK + +# define SPI_RIF_MODF_POS 17U +# define SPI_RIF_MODF_MSK BIT(SPI_RIF_MODF_POS) +# define SPI_RIF_MODF SPI_RIF_MODF_MSK + +# define SPI_RIF_CRCERR_POS 16U +# define SPI_RIF_CRCERR_MSK BIT(SPI_RIF_CRCERR_POS) +# define SPI_RIF_CRCERR SPI_RIF_CRCERR_MSK + +# define SPI_RIF_RXTH_POS 12U +# define SPI_RIF_RXTH_MSK BIT(SPI_RIF_RXTH_POS) +# define SPI_RIF_RXTH SPI_RIF_RXTH_MSK + +# define SPI_RIF_RXUD_POS 11U +# define SPI_RIF_RXUD_MSK BIT(SPI_RIF_RXUD_POS) +# define SPI_RIF_RXUD SPI_RIF_RXUD_MSK + +# define SPI_RIF_RXOV_POS 10U +# define SPI_RIF_RXOV_MSK BIT(SPI_RIF_RXOV_POS) +# define SPI_RIF_RXOV SPI_RIF_RXOV_MSK + +# define SPI_RIF_RXF_POS 9U +# define SPI_RIF_RXF_MSK BIT(SPI_RIF_RXF_POS) +# define SPI_RIF_RXF SPI_RIF_RXF_MSK + +# define SPI_RIF_RXNE_POS 8U +# define SPI_RIF_RXNE_MSK BIT(SPI_RIF_RXNE_POS) +# define SPI_RIF_RXNE SPI_RIF_RXNE_MSK + +# define SPI_RIF_TXTH_POS 4U +# define SPI_RIF_TXTH_MSK BIT(SPI_RIF_TXTH_POS) +# define SPI_RIF_TXTH SPI_RIF_TXTH_MSK + +# define SPI_RIF_TXUD_POS 3U +# define SPI_RIF_TXUD_MSK BIT(SPI_RIF_TXUD_POS) +# define SPI_RIF_TXUD SPI_RIF_TXUD_MSK + +# define SPI_RIF_TXOV_POS 2U +# define SPI_RIF_TXOV_MSK BIT(SPI_RIF_TXOV_POS) +# define SPI_RIF_TXOV SPI_RIF_TXOV_MSK + +# define SPI_RIF_TXE_POS 0U +# define SPI_RIF_TXE_MSK BIT(SPI_RIF_TXE_POS) +# define SPI_RIF_TXE SPI_RIF_TXE_MSK + +/****************** Bit definition for SPI_IFM register ************************/ + +# define SPI_IFM_FRE_POS 18U +# define SPI_IFM_FRE_MSK BIT(SPI_IFM_FRE_POS) +# define SPI_IFM_FRE SPI_IFM_FRE_MSK + +# define SPI_IFM_MODF_POS 17U +# define SPI_IFM_MODF_MSK BIT(SPI_IFM_MODF_POS) +# define SPI_IFM_MODF SPI_IFM_MODF_MSK + +# define SPI_IFM_CRCERR_POS 16U +# define SPI_IFM_CRCERR_MSK BIT(SPI_IFM_CRCERR_POS) +# define SPI_IFM_CRCERR SPI_IFM_CRCERR_MSK + +# define SPI_IFM_RXTH_POS 12U +# define SPI_IFM_RXTH_MSK BIT(SPI_IFM_RXTH_POS) +# define SPI_IFM_RXTH SPI_IFM_RXTH_MSK + +# define SPI_IFM_RXUD_POS 11U +# define SPI_IFM_RXUD_MSK BIT(SPI_IFM_RXUD_POS) +# define SPI_IFM_RXUD SPI_IFM_RXUD_MSK + +# define SPI_IFM_RXOV_POS 10U +# define SPI_IFM_RXOV_MSK BIT(SPI_IFM_RXOV_POS) +# define SPI_IFM_RXOV SPI_IFM_RXOV_MSK + +# define SPI_IFM_RXF_POS 9U +# define SPI_IFM_RXF_MSK BIT(SPI_IFM_RXF_POS) +# define SPI_IFM_RXF SPI_IFM_RXF_MSK + +# define SPI_IFM_RXNE_POS 8U +# define SPI_IFM_RXNE_MSK BIT(SPI_IFM_RXNE_POS) +# define SPI_IFM_RXNE SPI_IFM_RXNE_MSK + +# define SPI_IFM_TXTH_POS 4U +# define SPI_IFM_TXTH_MSK BIT(SPI_IFM_TXTH_POS) +# define SPI_IFM_TXTH SPI_IFM_TXTH_MSK + +# define SPI_IFM_TXUD_POS 3U +# define SPI_IFM_TXUD_MSK BIT(SPI_IFM_TXUD_POS) +# define SPI_IFM_TXUD SPI_IFM_TXUD_MSK + +# define SPI_IFM_TXOV_POS 2U +# define SPI_IFM_TXOV_MSK BIT(SPI_IFM_TXOV_POS) +# define SPI_IFM_TXOV SPI_IFM_TXOV_MSK + +# define SPI_IFM_TXE_POS 0U +# define SPI_IFM_TXE_MSK BIT(SPI_IFM_TXE_POS) +# define SPI_IFM_TXE SPI_IFM_TXE_MSK + +/****************** Bit definition for SPI_ICR register ************************/ + +# define SPI_ICR_FRE_POS 18U +# define SPI_ICR_FRE_MSK BIT(SPI_ICR_FRE_POS) +# define SPI_ICR_FRE SPI_ICR_FRE_MSK + +# define SPI_ICR_MODF_POS 17U +# define SPI_ICR_MODF_MSK BIT(SPI_ICR_MODF_POS) +# define SPI_ICR_MODF SPI_ICR_MODF_MSK + +# define SPI_ICR_CRCERR_POS 16U +# define SPI_ICR_CRCERR_MSK BIT(SPI_ICR_CRCERR_POS) +# define SPI_ICR_CRCERR SPI_ICR_CRCERR_MSK + +# define SPI_ICR_RXTH_POS 12U +# define SPI_ICR_RXTH_MSK BIT(SPI_ICR_RXTH_POS) +# define SPI_ICR_RXTH SPI_ICR_RXTH_MSK + +# define SPI_ICR_RXUD_POS 11U +# define SPI_ICR_RXUD_MSK BIT(SPI_ICR_RXUD_POS) +# define SPI_ICR_RXUD SPI_ICR_RXUD_MSK + +# define SPI_ICR_RXOV_POS 10U +# define SPI_ICR_RXOV_MSK BIT(SPI_ICR_RXOV_POS) +# define SPI_ICR_RXOV SPI_ICR_RXOV_MSK + +# define SPI_ICR_RXF_POS 9U +# define SPI_ICR_RXF_MSK BIT(SPI_ICR_RXF_POS) +# define SPI_ICR_RXF SPI_ICR_RXF_MSK + +# define SPI_ICR_RXNE_POS 8U +# define SPI_ICR_RXNE_MSK BIT(SPI_ICR_RXNE_POS) +# define SPI_ICR_RXNE SPI_ICR_RXNE_MSK + +# define SPI_ICR_TXTH_POS 4U +# define SPI_ICR_TXTH_MSK BIT(SPI_ICR_TXTH_POS) +# define SPI_ICR_TXTH SPI_ICR_TXTH_MSK + +# define SPI_ICR_TXUD_POS 3U +# define SPI_ICR_TXUD_MSK BIT(SPI_ICR_TXUD_POS) +# define SPI_ICR_TXUD SPI_ICR_TXUD_MSK + +# define SPI_ICR_TXOV_POS 2U +# define SPI_ICR_TXOV_MSK BIT(SPI_ICR_TXOV_POS) +# define SPI_ICR_TXOV SPI_ICR_TXOV_MSK + +# define SPI_ICR_TXE_POS 0U +# define SPI_ICR_TXE_MSK BIT(SPI_ICR_TXE_POS) +# define SPI_ICR_TXE SPI_ICR_TXE_MSK + +typedef struct +{ + __IO uint32_t CON1; // 0x000 + __IO uint32_t CON2; // 0x004 + __I uint32_t STAT; // 0x008 + __IO uint32_t DATA; // 0x00c + __IO uint32_t CRCPOLY; // 0x010 + __I uint32_t RXCRC; // 0x014 + __I uint32_t TXCRC; // 0x018 + __IO uint32_t I2SCFG; // 0x01c + __IO uint32_t I2SPR; // 0x020 + __O uint32_t IER; // 0x024 + __O uint32_t IDR; // 0x028 + __I uint32_t IVS; // 0x02c + __I uint32_t RIF; // 0x030 + __I uint32_t IFM; // 0x034 + __O uint32_t ICR; // 0x038 +} SPI_TypeDef, I2S_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_syscfg.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_syscfg.h new file mode 100644 index 00000000000..0ff1812308c --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_syscfg.h @@ -0,0 +1,646 @@ +/********************************************************************************** + * + * @file reg_syscfg.h + * @brief SYSCFG Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __SYSCFG_H__ +#define __SYSCFG_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + +/****************** Bit definition for SYSCFG_REMAP register ************************/ + +# define SYSCFG_REMAP_REALBASE_POSS 12U +# define SYSCFG_REMAP_REALBASE_POSE 16U +# define SYSCFG_REMAP_REALBASE_MSK BITS(SYSCFG_REMAP_REALBASE_POSS, SYSCFG_REMAP_REALBASE_POSE) +# define SYSCFG_REMAP_REALBASE SYSCFG_REMAP_REALBASE_MSK + +# define SYSCFG_REMAP_REALMOD_POSS 10U +# define SYSCFG_REMAP_REALMOD_POSE 11U +# define SYSCFG_REMAP_REALMOD_MSK BITS(SYSCFG_REMAP_REALMOD_POSS, SYSCFG_REMAP_REALMOD_POSE) +# define SYSCFG_REMAP_REALMOD SYSCFG_REMAP_REALMOD_MSK + +# define SYSCFG_REMAP_EFBASE_POSS 4U +# define SYSCFG_REMAP_EFBASE_POSE 8U +# define SYSCFG_REMAP_EFBASE_MSK BITS(SYSCFG_REMAP_EFBASE_POSS, SYSCFG_REMAP_EFBASE_POSE) +# define SYSCFG_REMAP_EFBASE SYSCFG_REMAP_EFBASE_MSK + +# define SYSCFG_REMAP_MEMMOD_POSS 2U +# define SYSCFG_REMAP_MEMMOD_POSE 3U +# define SYSCFG_REMAP_MEMMOD_MSK BITS(SYSCFG_REMAP_MEMMOD_POSS, SYSCFG_REMAP_MEMMOD_POSE) +# define SYSCFG_REMAP_MEMMOD SYSCFG_REMAP_MEMMOD_MSK + +# define SYSCFG_REMAP_REMAP_POS 0U +# define SYSCFG_REMAP_REMAP_MSK BIT(SYSCFG_REMAP_REMAP_POS) +# define SYSCFG_REMAP_REMAP SYSCFG_REMAP_REMAP_MSK + +/****************** Bit definition for SYSCFG_ENGEN register ************************/ + +# define SYSCFG_ENGEN_ENGEN_POSS 0U +# define SYSCFG_ENGEN_ENGEN_POSE 31U +# define SYSCFG_ENGEN_ENGEN_MSK BITS(SYSCFG_ENGEN_ENGEN_POSS, SYSCFG_ENGEN_ENGEN_POSE) +# define SYSCFG_ENGEN_ENGEN SYSCFG_ENGEN_ENGEN_MSK + +# define SYSCFG_ENGEN_ENGFLAG_POS 0U +# define SYSCFG_ENGEN_ENGFLAG_MSK BIT(SYSCFG_ENGEN_ENGFLAG_POS) +# define SYSCFG_ENGEN_ENGFLAG SYSCFG_ENGEN_ENGFLAG_MSK + +/****************** Bit definition for SYSCFG_PWR register ************************/ + +# define SYSCFG_PWR_LDOUSBSBY_POS 5U +# define SYSCFG_PWR_LDOUSBSBY_MSK BIT(SYSCFG_PWR_LDOUSBSBY_POS) +# define SYSCFG_PWR_LDOUSBSBY SYSCFG_PWR_LDOUSBSBY_MSK + +# define SYSCFG_PWR_LDOUSBEN_POS 4U +# define SYSCFG_PWR_LDOUSBEN_MSK BIT(SYSCFG_PWR_LDOUSBEN_POS) +# define SYSCFG_PWR_LDOUSBEN SYSCFG_PWR_LDOUSBEN_MSK + +# define SYSCFG_PWR_RESSRC_POS 1U +# define SYSCFG_PWR_RESSRC_MSK BIT(SYSCFG_PWR_RESSRC_POS) +# define SYSCFG_PWR_RESSRC SYSCFG_PWR_RESSRC_MSK + +# define SYSCFG_PWR_RESEN_POS 0U +# define SYSCFG_PWR_RESEN_MSK BIT(SYSCFG_PWR_RESEN_POS) +# define SYSCFG_PWR_RESEN SYSCFG_PWR_RESEN_MSK + +/****************** Bit definition for SYSCFG_IRSEL register ************************/ + +# define SYSCFG_IRSEL_PLR_POS 8U +# define SYSCFG_IRSEL_PLR_MSK BIT(SYSCFG_IRSEL_PLR_POS) +# define SYSCFG_IRSEL_PLR SYSCFG_IRSEL_PLR_MSK + +# define SYSCFG_IRSEL_SEL2_POSS 4U +# define SYSCFG_IRSEL_SEL2_POSE 7U +# define SYSCFG_IRSEL_SEL2_MSK BITS(SYSCFG_IRSEL_SEL2_POSS, SYSCFG_IRSEL_SEL2_POSE) +# define SYSCFG_IRSEL_SEL2 SYSCFG_IRSEL_SEL2_MSK + +# define SYSCFG_IRSEL_SEL1_POSS 0U +# define SYSCFG_IRSEL_SEL1_POSE 3U +# define SYSCFG_IRSEL_SEL1_MSK BITS(SYSCFG_IRSEL_SEL1_POSS, SYSCFG_IRSEL_SEL1_POSE) +# define SYSCFG_IRSEL_SEL1 SYSCFG_IRSEL_SEL1_MSK + +/****************** Bit definition for SYSCFG_SYSTRIM register ************************/ + +# define SYSCFG_SYSTRIM_USBLDOTRIM_POSS 16U +# define SYSCFG_SYSTRIM_USBLDOTRIM_POSE 18U +# define SYSCFG_SYSTRIM_USBLDOTRIM_MSK BITS(SYSCFG_SYSTRIM_USBLDOTRIM_POSS, SYSCFG_SYSTRIM_USBLDOTRIM_POSE) +# define SYSCFG_SYSTRIM_USBLDOTRIM SYSCFG_SYSTRIM_USBLDOTRIM_MSK + +# define SYSCFG_SYSTRIM_LVDTRIM_POSS 8U +# define SYSCFG_SYSTRIM_LVDTRIM_POSE 9U +# define SYSCFG_SYSTRIM_LVDTRIM_MSK BITS(SYSCFG_SYSTRIM_LVDTRIM_POSS, SYSCFG_SYSTRIM_LVDTRIM_POSE) +# define SYSCFG_SYSTRIM_LVDTRIM SYSCFG_SYSTRIM_LVDTRIM_MSK + +# define SYSCFG_SYSTRIM_BGTRIM_POSS 0U +# define SYSCFG_SYSTRIM_BGTRIM_POSE 3U +# define SYSCFG_SYSTRIM_BGTRIM_MSK BITS(SYSCFG_SYSTRIM_BGTRIM_POSS, SYSCFG_SYSTRIM_BGTRIM_POSE) +# define SYSCFG_SYSTRIM_BGTRIM SYSCFG_SYSTRIM_BGTRIM_MSK + +/****************** Bit definition for SYSCFG_CLKTRIM register ************************/ + +# define SYSCFG_CLKTRIM_PLLFNS_POSS 28U +# define SYSCFG_CLKTRIM_PLLFNS_POSE 29U +# define SYSCFG_CLKTRIM_PLLFNS_MSK BITS(SYSCFG_CLKTRIM_PLLFNS_POSS, SYSCFG_CLKTRIM_PLLFNS_POSE) +# define SYSCFG_CLKTRIM_PLLFNS SYSCFG_CLKTRIM_PLLFNS_MSK + +# define SYSCFG_CLKTRIM_HRC48TRIM_POSS 16U +# define SYSCFG_CLKTRIM_HRC48TRIM_POSE 24U +# define SYSCFG_CLKTRIM_HRC48TRIM_MSK BITS(SYSCFG_CLKTRIM_HRC48TRIM_POSS, SYSCFG_CLKTRIM_HRC48TRIM_POSE) +# define SYSCFG_CLKTRIM_HRC48TRIM SYSCFG_CLKTRIM_HRC48TRIM_MSK + +# define SYSCFG_CLKTRIM_LRCTRIM_POSS 8U +# define SYSCFG_CLKTRIM_LRCTRIM_POSE 14U +# define SYSCFG_CLKTRIM_LRCTRIM_MSK BITS(SYSCFG_CLKTRIM_LRCTRIM_POSS, SYSCFG_CLKTRIM_LRCTRIM_POSE) +# define SYSCFG_CLKTRIM_LRCTRIM SYSCFG_CLKTRIM_LRCTRIM_MSK + +# define SYSCFG_CLKTRIM_HRCTRIMM_POSS 0U +# define SYSCFG_CLKTRIM_HRCTRIM_POSE 7U +# define SYSCFG_CLKTRIM_HRCTRIM_MSK BITS(SYSCFG_CLKTRIM_HRCTRIMM_POSS, SYSCFG_CLKTRIM_HRCTRIM_POSE) +# define SYSCFG_CLKTRIM_HRCTRIM SYSCFG_CLKTRIM_HRCTRIM_MSK + +/****************** Bit definition for SYSCFG_OSCTRIM register ************************/ + +# define SYSCFG_OSCTRIM_LOSCRCNT_POSS 12U +# define SYSCFG_OSCTRIM_LOSCRCNT_POSE 13U +# define SYSCFG_OSCTRIM_LOSCRCNT_MSK BITS(SYSCFG_OSCTRIM_LOSCRCNT_POSS, SYSCFG_OSCTRIM_LOSCRCNT_POSE) +# define SYSCFG_OSCTRIM_LOSCRCNT SYSCFG_OSCTRIM_LOSCRCNT_MSK + +# define SYSCFG_OSCTRIM_LOSCCURSEL_POSS 8U +# define SYSCFG_OSCTRIM_LOSCCURSEL_POSE 10U +# define SYSCFG_OSCTRIM_LOSCCURSEL_MSK BITS(SYSCFG_OSCTRIM_LOSCCURSEL_POSS, SYSCFG_OSCTRIM_LOSCCURSEL_POSE) +# define SYSCFG_OSCTRIM_LOSCCURSEL SYSCFG_OSCTRIM_LOSCCURSEL_MSK + +# define SYSCFG_OSCTRIM_HOSCRCNT_POSS 4U +# define SYSCFG_OSCTRIM_HOSCRCNT_POSE 5U +# define SYSCFG_OSCTRIM_HOSCRCNT_MSK BITS(SYSCFG_OSCTRIM_HOSCRCNT_POSS, SYSCFG_OSCTRIM_HOSCRCNT_POSE) +# define SYSCFG_OSCTRIM_HOSCRCNT SYSCFG_OSCTRIM_HOSCRCNT_MSK + +# define SYSCFG_OSCTRIM_HOSCCURSEL_POSS 0U +# define SYSCFG_OSCTRIM_HOSCCURSEL_POSE 1U +# define SYSCFG_OSCTRIM_HOSCCURSEL_MSK BITS(SYSCFG_OSCTRIM_HOSCCURSEL_POSS, SYSCFG_OSCTRIM_HOSCCURSEL_POSE) +# define SYSCFG_OSCTRIM_HOSCCURSEL SYSCFG_OSCTRIM_HOSCCURSEL_MSK + +/****************** Bit definition for SYSCFG_IPTRIM register ************************/ + +# define SYSCFG_IPTRIM_CMP2TRIM_POSS 8U +# define SYSCFG_IPTRIM_CMP2TRIM_POSE 15U +# define SYSCFG_IPTRIM_CMP2TRIM_MSK BITS(SYSCFG_IPTRIM_CMP2TRIM_POSS, SYSCFG_IPTRIM_CMP2TRIM_POSE) +# define SYSCFG_IPTRIM_CMP2TRIM SYSCFG_IPTRIM_CMP2TRIM_MSK + +# define SYSCFG_IPTRIM_CMP1TRIM_POSS 0U +# define SYSCFG_IPTRIM_CMP1TRIM_POSE 7U +# define SYSCFG_IPTRIM_CMP1TRIM_MSK BITS(SYSCFG_IPTRIM_CMP1TRIM_POSS, SYSCFG_IPTRIM_CMP1TRIM_POSE) +# define SYSCFG_IPTRIM_CMP1TRIM SYSCFG_IPTRIM_CMP1TRIM_MSK + +/****************** Bit definition for SYSCFG_AHBIPEN register ************************/ + +# define SYSCFG_AHBIPEN_GPDEN_POS 19U +# define SYSCFG_AHBIPEN_GPDEN_MSK BIT(SYSCFG_AHBIPEN_GPDEN_POS) +# define SYSCFG_AHBIPEN_GPDEN SYSCFG_AHBIPEN_GPDEN_MSK + +# define SYSCFG_AHBIPEN_GPCEN_POS 18U +# define SYSCFG_AHBIPEN_GPCEN_MSK BIT(SYSCFG_AHBIPEN_GPCEN_POS) +# define SYSCFG_AHBIPEN_GPCEN SYSCFG_AHBIPEN_GPCEN_MSK + +# define SYSCFG_AHBIPEN_GPBEN_POS 17U +# define SYSCFG_AHBIPEN_GPBEN_MSK BIT(SYSCFG_AHBIPEN_GPBEN_POS) +# define SYSCFG_AHBIPEN_GPBEN SYSCFG_AHBIPEN_GPBEN_MSK + +# define SYSCFG_AHBIPEN_GPAEN_POS 16U +# define SYSCFG_AHBIPEN_GPAEN_MSK BIT(SYSCFG_AHBIPEN_GPAEN_POS) +# define SYSCFG_AHBIPEN_GPAEN SYSCFG_AHBIPEN_GPAEN_MSK + +# define SYSCFG_AHBIPEN_CALCEN_POS 15U +# define SYSCFG_AHBIPEN_CALCEN_MSK BIT(SYSCFG_AHBIPEN_CALCEN_POS) +# define SYSCFG_AHBIPEN_CALCEN SYSCFG_AHBIPEN_CALCEN_MSK + +# define SYSCFG_AHBIPEN_USBEN_POS 14U +# define SYSCFG_AHBIPEN_USBEN_MSK BIT(SYSCFG_AHBIPEN_USBEN_POS) +# define SYSCFG_AHBIPEN_USBEN SYSCFG_AHBIPEN_USBEN_MSK + +# define SYSCFG_AHBIPEN_AESEN_POS 13U +# define SYSCFG_AHBIPEN_AESEN_MSK BIT(SYSCFG_AHBIPEN_AESEN_POS) +# define SYSCFG_AHBIPEN_AESEN SYSCFG_AHBIPEN_AESEN_MSK + +# define SYSCFG_AHBIPEN_CRCEN_POS 12U +# define SYSCFG_AHBIPEN_CRCEN_MSK BIT(SYSCFG_AHBIPEN_CRCEN_POS) +# define SYSCFG_AHBIPEN_CRCEN SYSCFG_AHBIPEN_CRCEN_MSK + +# define SYSCFG_AHBIPEN_MSWDEN_POS 11U +# define SYSCFG_AHBIPEN_MSWDEN_MSK BIT(SYSCFG_AHBIPEN_MSWDEN_POS) +# define SYSCFG_AHBIPEN_MSWDEN SYSCFG_AHBIPEN_MSWDEN_MSK + +# define SYSCFG_AHBIPEN_CSUEN_POS 10U +# define SYSCFG_AHBIPEN_CSUEN_MSK BIT(SYSCFG_AHBIPEN_CSUEN_POS) +# define SYSCFG_AHBIPEN_CSUEN SYSCFG_AHBIPEN_CSUEN_MSK + +# define SYSCFG_AHBIPEN_KBCUEN_POS 7U +# define SYSCFG_AHBIPEN_KBCUEN_MSK BIT(SYSCFG_AHBIPEN_KBCUEN_POS) +# define SYSCFG_AHBIPEN_KBCUEN SYSCFG_AHBIPEN_KBCUEN_MSK + +# define SYSCFG_AHBIPEN_RTCEN_POS 6U +# define SYSCFG_AHBIPEN_RTCEN_MSK BIT(SYSCFG_AHBIPEN_RTCEN_POS) +# define SYSCFG_AHBIPEN_RTCEN SYSCFG_AHBIPEN_RTCEN_MSK + +# define SYSCFG_AHBIPEN_DMA1EN_POS 0U +# define SYSCFG_AHBIPEN_DMA1EN_MSK BIT(SYSCFG_AHBIPEN_DMA1EN_POS) +# define SYSCFG_AHBIPEN_DMA1EN SYSCFG_AHBIPEN_DMA1EN_MSK + +/****************** Bit definition for SYSCFG_APB1IPEN register ************************/ + +# define SYSCFG_APB1IPEN_I2C2EN_POS 22U +# define SYSCFG_APB1IPEN_I2C2EN_MSK BIT(SYSCFG_APB1IPEN_I2C2EN_POS) +# define SYSCFG_APB1IPEN_I2C2EN SYSCFG_APB1IPEN_I2C2EN_MSK + +# define SYSCFG_APB1IPEN_I2C1EN_POS 21U +# define SYSCFG_APB1IPEN_I2C1EN_MSK BIT(SYSCFG_APB1IPEN_I2C1EN_POS) +# define SYSCFG_APB1IPEN_I2C1EN SYSCFG_APB1IPEN_I2C1EN_MSK + +# define SYSCFG_APB1IPEN_UART4EN_POS 19U +# define SYSCFG_APB1IPEN_UART4EN_MSK BIT(SYSCFG_APB1IPEN_UART4EN_POS) +# define SYSCFG_APB1IPEN_UART4EN SYSCFG_APB1IPEN_UART4EN_MSK + +# define SYSCFG_APB1IPEN_UART3EN_POS 18U +# define SYSCFG_APB1IPEN_UART3EN_MSK BIT(SYSCFG_APB1IPEN_UART3EN_POS) +# define SYSCFG_APB1IPEN_UART3EN SYSCFG_APB1IPEN_UART3EN_MSK + +# define SYSCFG_APB1IPEN_UART2EN_POS 17U +# define SYSCFG_APB1IPEN_UART2EN_MSK BIT(SYSCFG_APB1IPEN_UART2EN_POS) +# define SYSCFG_APB1IPEN_UART2EN SYSCFG_APB1IPEN_UART2EN_MSK + +# define SYSCFG_APB1IPEN_SPI3EN_POS 15U +# define SYSCFG_APB1IPEN_SPI3EN_MSK BIT(SYSCFG_APB1IPEN_SPI3EN_POS) +# define SYSCFG_APB1IPEN_SPI3EN SYSCFG_APB1IPEN_SPI3EN_MSK + +# define SYSCFG_APB1IPEN_SPI2EN_POS 14U +# define SYSCFG_APB1IPEN_SPI2EN_MSK BIT(SYSCFG_APB1IPEN_SPI2EN_POS) +# define SYSCFG_APB1IPEN_SPI2EN SYSCFG_APB1IPEN_SPI2EN_MSK + +# define SYSCFG_APB1IPEN_IWDTEN_POS 12U +# define SYSCFG_APB1IPEN_IWDTEN_MSK BIT(SYSCFG_APB1IPEN_IWDTEN_POS) +# define SYSCFG_APB1IPEN_IWDTEN SYSCFG_APB1IPEN_IWDTEN_MSK + +# define SYSCFG_APB1IPEN_WWDTEN_POS 11U +# define SYSCFG_APB1IPEN_WWDTEN_MSK BIT(SYSCFG_APB1IPEN_WWDTEN_POS) +# define SYSCFG_APB1IPEN_WWDTEN SYSCFG_APB1IPEN_WWDTEN_MSK + +# define SYSCFG_APB1IPEN_BS16T1EN_POS 4U +# define SYSCFG_APB1IPEN_BS16T1EN_MSK BIT(SYSCFG_APB1IPEN_BS16T1EN_POS) +# define SYSCFG_APB1IPEN_BS16T1EN SYSCFG_APB1IPEN_BS16T1EN_MSK + +# define SYSCFG_APB1IPEN_GP16C4T3EN_POS 3U +# define SYSCFG_APB1IPEN_GP16C4T3EN_MSK BIT(SYSCFG_APB1IPEN_GP16C4T3EN_POS) +# define SYSCFG_APB1IPEN_GP16C4T3EN SYSCFG_APB1IPEN_GP16C4T3EN_MSK + +# define SYSCFG_APB1IPEN_GP16C4T2EN_POS 2U +# define SYSCFG_APB1IPEN_GP16C4T2EN_MSK BIT(SYSCFG_APB1IPEN_GP16C4T2EN_POS) +# define SYSCFG_APB1IPEN_GP16C4T2EN SYSCFG_APB1IPEN_GP16C4T2EN_MSK + +# define SYSCFG_APB1IPEN_GP16C4T1EN_POS 1U +# define SYSCFG_APB1IPEN_GP16C4T1EN_MSK BIT(SYSCFG_APB1IPEN_GP16C4T1EN_POS) +# define SYSCFG_APB1IPEN_GP16C4T1EN SYSCFG_APB1IPEN_GP16C4T1EN_MSK + +# define SYSCFG_APB1IPEN_GP32C4T1EN_POS 1U +# define SYSCFG_APB1IPEN_GP32C4T1EN_MSK BIT(SYSCFG_APB1IPEN_GP32C4T1EN_POS) +# define SYSCFG_APB1IPEN_GP32C4T1EN SYSCFG_APB1IPEN_GP32C4T1EN_MSK + +/****************** Bit definition for SYSCFG_APB2IPEN register ************************/ + +# define SYSCFG_APB2IPEN_CMPEN_POS 23U +# define SYSCFG_APB2IPEN_CMPEN_MSK BIT(SYSCFG_APB2IPEN_CMPEN_POS) +# define SYSCFG_APB2IPEN_CMPEN SYSCFG_APB2IPEN_CMPEN_MSK + +# define SYSCFG_APB2IPEN_GP16C2T4EN_POS 19U +# define SYSCFG_APB2IPEN_GP16C2T4EN_MSK BIT(SYSCFG_APB2IPEN_GP16C2T4EN_POS) +# define SYSCFG_APB2IPEN_GP16C2T4EN SYSCFG_APB2IPEN_GP16C2T4EN_MSK + +# define SYSCFG_APB2IPEN_GP16C2T3EN_POS 18U +# define SYSCFG_APB2IPEN_GP16C2T3EN_MSK BIT(SYSCFG_APB2IPEN_GP16C2T3EN_POS) +# define SYSCFG_APB2IPEN_GP16C2T3EN SYSCFG_APB2IPEN_GP16C2T3EN_MSK + +# define SYSCFG_APB2IPEN_GP16C2T2EN_POS 17U +# define SYSCFG_APB2IPEN_GP16C2T2EN_MSK BIT(SYSCFG_APB2IPEN_GP16C2T2EN_POS) +# define SYSCFG_APB2IPEN_GP16C2T2EN SYSCFG_APB2IPEN_GP16C2T2EN_MSK + +# define SYSCFG_APB2IPEN_GP16C2T1EN_POS 16U +# define SYSCFG_APB2IPEN_GP16C2T1EN_MSK BIT(SYSCFG_APB2IPEN_GP16C2T1EN_POS) +# define SYSCFG_APB2IPEN_GP16C2T1EN SYSCFG_APB2IPEN_GP16C2T1EN_MSK + +# define SYSCFG_APB2IPEN_UART1EN_POS 14U +# define SYSCFG_APB2IPEN_UART1EN_MSK BIT(SYSCFG_APB2IPEN_UART1EN_POS) +# define SYSCFG_APB2IPEN_UART1EN SYSCFG_APB2IPEN_UART1EN_MSK + +# define SYSCFG_APB2IPEN_SPI1EN_POS 12U +# define SYSCFG_APB2IPEN_SPI1EN_MSK BIT(SYSCFG_APB2IPEN_SPI1EN_POS) +# define SYSCFG_APB2IPEN_SPI1EN SYSCFG_APB2IPEN_SPI1EN_MSK + +# define SYSCFG_APB2IPEN_AD16C4T1EN_POS 11U +# define SYSCFG_APB2IPEN_AD16C4T1EN_MSK BIT(SYSCFG_APB2IPEN_AD16C4T1EN_POS) +# define SYSCFG_APB2IPEN_AD16C4T1EN SYSCFG_APB2IPEN_AD16C4T1EN_MSK + +# define SYSCFG_APB2IPEN_ADCEN_POS 9U +# define SYSCFG_APB2IPEN_ADCEN_MSK BIT(SYSCFG_APB2IPEN_ADCEN_POS) +# define SYSCFG_APB2IPEN_ADCEN SYSCFG_APB2IPEN_ADCEN_MSK + +/****************** Bit definition for SYSCFG_MEMMOD register ************************/ + +# define SYSCFG_MEMMOD_SMOD_POSS 8U +# define SYSCFG_MEMMOD_SMOD_POSE 15U +# define SYSCFG_MEMMOD_SMOD_MSK BITS(SYSCFG_MEMMOD_SMOD_POSS, SYSCFG_MEMMOD_SMOD_POSE) +# define SYSCFG_MEMMOD_SMOD SYSCFG_MEMMOD_SMOD_MSK + +# define SYSCFG_MEMMOD_FMOD_POSS 0U +# define SYSCFG_MEMMOD_FMOD_POSE 7U +# define SYSCFG_MEMMOD_FMOD_MSK BITS(SYSCFG_MEMMOD_FMOD_POSS, SYSCFG_MEMMOD_FMOD_POSE) +# define SYSCFG_MEMMOD_FMOD SYSCFG_MEMMOD_FMOD_MSK + +/****************** Bit definition for SYSCFG_ADCVREF register ************************/ + +# define SYSCFG_ADCVREF_ADCVREF_POSS 0U +# define SYSCFG_ADCVREF_ADCVREF_POSE 11U +# define SYSCFG_ADCVREF_ADCVREF_MSK BITS(SYSCFG_ADCVREF_ADCVREF_POSS, SYSCFG_ADCVREF_ADCVREF_POSE) +# define SYSCFG_ADCVREF_ADCVREF SYSCFG_ADCVREF_ADCVREF_MSK + +/****************** Bit definition for SYSCFG_ADCTEMP register ************************/ + +# define SYSCFG_ADCTEMP_ADCTEMPH_POSS 16U +# define SYSCFG_ADCTEMP_ADCTEMPH_POSE 27U +# define SYSCFG_ADCTEMP_ADCTEMPH_MSK BITS(SYSCFG_ADCTEMP_ADCTEMPH_POSS, SYSCFG_ADCTEMP_ADCTEMPH_POSE) +# define SYSCFG_ADCTEMP_ADCTEMPH SYSCFG_ADCTEMP_ADCTEMPH_MSK + +# define SYSCFG_ADCTEMP_ADCTEMPL_POSS 0U +# define SYSCFG_ADCTEMP_ADCTEMPL_POSE 11U +# define SYSCFG_ADCTEMP_ADCTEMPL_MSK BITS(SYSCFG_ADCTEMP_ADCTEMPL_POSS, SYSCFG_ADCTEMP_ADCTEMPL_POSE) +# define SYSCFG_ADCTEMP_ADCTEMPL SYSCFG_ADCTEMP_ADCTEMPL_MSK + +/****************** Bit definition for SYSCFG_SYSSET register ************************/ + +# define SYSCFG_SYSSET_SYS_IWDTEN_POSS 16U +# define SYSCFG_SYSSET_SYS_IWDTEN_POSE 23U +# define SYSCFG_SYSSET_SYS_IWDTEN_MSK BITS(SYSCFG_SYSSET_SYS_IWDTEN_POSS, SYSCFG_SYSSET_SYS_IWDTEN_POSE) +# define SYSCFG_SYSSET_SYS_IWDTEN SYSCFG_SYSSET_SYS_IWDTEN_MSK + +# define SYSCFG_SYSSET_SYS_BOREN_POSS 8U +# define SYSCFG_SYSSET_SYS_BOREN_POSE 15U +# define SYSCFG_SYSSET_SYS_BOREN_MSK BITS(SYSCFG_SYSSET_SYS_BOREN_POSS, SYSCFG_SYSSET_SYS_BOREN_POSE) +# define SYSCFG_SYSSET_SYS_BOREN SYSCFG_SYSSET_SYS_BOREN_MSK + +# define SYSCFG_SYSSET_SYS_BORLS_POSS 0U +# define SYSCFG_SYSSET_SYS_BORLS_POSE 2U +# define SYSCFG_SYSSET_SYS_BORLS_MSK BITS(SYSCFG_SYSSET_SYS_BORLS_POSS, SYSCFG_SYSSET_SYS_BORLS_POSE) +# define SYSCFG_SYSSET_SYS_BORLS SYSCFG_SYSSET_SYS_BORLS_MSK + +/****************** Bit definition for SYSCFG_CFG register ************************/ + +# define SYSCFG_CFG_DBGHEN_POSS 16U +# define SYSCFG_CFG_DBGHEN_POSE 31U +# define SYSCFG_CFG_DBGHEN_MSK BITS(SYSCFG_CFG_DBGHEN_POSS, SYSCFG_CFG_DBGHEN_POSE) +# define SYSCFG_CFG_DBGHEN SYSCFG_CFG_DBGHEN_MSK + +# define SYSCFG_CFG_LVDLCK_POS 14U +# define SYSCFG_CFG_LVDLCK_MSK BIT(SYSCFG_CFG_LVDLCK_POS) +# define SYSCFG_CFG_LVDLCK SYSCFG_CFG_LVDLCK_MSK + +# define SYSCFG_CFG_CSSLCK_POS 13U +# define SYSCFG_CFG_CSSLCK_MSK BIT(SYSCFG_CFG_CSSLCK_POS) +# define SYSCFG_CFG_CSSLCK SYSCFG_CFG_CSSLCK_MSK + +# define SYSCFG_CFG_CPULCK_POS 12U +# define SYSCFG_CFG_CPULCK_MSK BIT(SYSCFG_CFG_CPULCK_POS) +# define SYSCFG_CFG_CPULCK SYSCFG_CFG_CPULCK_MSK + +# define SYSCFG_CFG_VTESTSEL_POSS 8U +# define SYSCFG_CFG_VTESTSEL_POSE 11U +# define SYSCFG_CFG_VTESTSEL_MSK BITS(SYSCFG_CFG_VTESTSEL_POSS, SYSCFG_CFG_VTESTSEL_POSE) +# define SYSCFG_CFG_VTESTSEL SYSCFG_CFG_VTESTSEL_MSK + +# define SYSCFG_CFG_BKREADY_POS 0U +# define SYSCFG_CFG_BKREADY_MSK BIT(SYSCFG_CFG_BKREADY_POS) +# define SYSCFG_CFG_BKREADY SYSCFG_CFG_BKREADY_MSK + +/****************** Bit definition for SYSCFG_PWRCON register ************************/ + +# define SYSCFG_PWRCON_IWDTEN_POSS 15U +# define SYSCFG_PWRCON_IWDTEN_MSK BIT(SYSCFG_PWRCON_IWDTEN_POSS) +# define SYSCFG_PWRCON_IWDTEN SYSCFG_PWRCON_IWDTEN_MSK + +# define SYSCFG_PWRCON_BOREN_POSS 11U +# define SYSCFG_PWRCON_BOREN_MSK BIT(SYSCFG_PWRCON_BOREN_POSS) +# define SYSCFG_PWRCON_BOREN SYSCFG_PWRCON_BOREN_MSK + +# define SYSCFG_PWRCON_BORLS_POSS 8U +# define SYSCFG_PWRCON_BORLS_POSE 10U +# define SYSCFG_PWRCON_BORLS_MSK BITS(SYSCFG_PWRCON_BORLS_POSS, SYSCFG_PWRCON_BORLS_POSE) +# define SYSCFG_PWRCON_BORLS SYSCFG_PWRCON_BORLS_MSK + +# define SYSCFG_PWRCON_LVDEN_POS 4U +# define SYSCFG_PWRCON_LVDEN_MSK BIT(SYSCFG_PWRCON_LVDEN_POS) +# define SYSCFG_PWRCON_LVDEN SYSCFG_PWRCON_LVDEN_MSK + +# define SYSCFG_PWRCON_LVDLS_POSS 0U +# define SYSCFG_PWRCON_LVDLS_POSE 3U +# define SYSCFG_PWRCON_LVDLS_MSK BITS(SYSCFG_PWRCON_LVDLS_POSS, SYSCFG_PWRCON_LVDLS_POSE) +# define SYSCFG_PWRCON_LVDLS SYSCFG_PWRCON_LVDLS_MSK + +/****************** Bit definition for SYSCFG_WKTRIM register ************************/ + +# define SYSCFG_WKTRIM_LOSCRCNT_POSS 28U +# define SYSCFG_WKTRIM_LOSCRCNT_POSE 29U +# define SYSCFG_WKTRIM_LOSCRCNT_MSK BITS(SYSCFG_WKTRIM_LOSCRCNT_POSS, SYSCFG_WKTRIM_LOSCRCNT_POSE) +# define SYSCFG_WKTRIM_LOSCRCNT SYSCFG_WKTRIM_LOSCRCNT_MSK + +# define SYSCFG_WKTRIM_LOSCCURSEL_POSS 24U +# define SYSCFG_WKTRIM_LOSCCURSEL_POSE 26U +# define SYSCFG_WKTRIM_LOSCCURSEL_MSK BITS(SYSCFG_WKTRIM_LOSCCURSEL_POSS, SYSCFG_WKTRIM_LOSCCURSEL_POSE) +# define SYSCFG_WKTRIM_LOSCCURSEL SYSCFG_WKTRIM_LOSCCURSEL_MSK + +# define SYSCFG_WKTRIM_LDOCKVT_POSS 16U +# define SYSCFG_WKTRIM_LDOCKVT_POSE 18U +# define SYSCFG_WKTRIM_LDOCKVT_MSK BITS(SYSCFG_WKTRIM_LDOCKVT_POSS, SYSCFG_WKTRIM_LDOCKVT_POSE) +# define SYSCFG_WKTRIM_LDOCKVT SYSCFG_WKTRIM_LDOCKVT_MSK + +# define SYSCFG_WKTRIM_LVDTRIM_POSS 12U +# define SYSCFG_WKTRIM_LVDTRIM_POSE 13U +# define SYSCFG_WKTRIM_LVDTRIM_MSK BITS(SYSCFG_WKTRIM_LVDTRIM_POSS, SYSCFG_WKTRIM_LVDTRIM_POSE) +# define SYSCFG_WKTRIM_LVDTRIM SYSCFG_WKTRIM_LVDTRIM_MSK + +# define SYSCFG_WKTRIM_BGTRIM_POSS 8U +# define SYSCFG_WKTRIM_BGTRIM_POSE 11U +# define SYSCFG_WKTRIM_BGTRIM_MSK BITS(SYSCFG_WKTRIM_BGTRIM_POSS, SYSCFG_WKTRIM_BGTRIM_POSE) +# define SYSCFG_WKTRIM_BGTRIM SYSCFG_WKTRIM_BGTRIM_MSK + +# define SYSCFG_WKTRIM_LRCTRIM_POSS 0U +# define SYSCFG_WKTRIM_LRCTRIM_POSE 6U +# define SYSCFG_WKTRIM_LRCTRIM_MSK BITS(SYSCFG_WKTRIM_LRCTRIM_POSS, SYSCFG_WKTRIM_LRCTRIM_POSE) +# define SYSCFG_WKTRIM_LRCTRIM SYSCFG_WKTRIM_LRCTRIM_MSK + +/****************** Bit definition for SYSCFG_WKUP register ************************/ + +# define SYSCFG_WKUP_WKEG_POSS 16U +# define SYSCFG_WKUP_WKEG_POSE 31U +# define SYSCFG_WKUP_WKEG_MSK BITS(SYSCFG_WKUP_WKEG_POSS, SYSCFG_WKUP_WKEG_POSE) +# define SYSCFG_WKUP_WKEG SYSCFG_WKUP_WKEG_MSK + +# define SYSCFG_WKUP_WKEN_POSS 0U +# define SYSCFG_WKUP_WKEN_POSE 15U +# define SYSCFG_WKUP_WKEN_MSK BITS(SYSCFG_WKUP_WKEN_POSS, SYSCFG_WKUP_WKEN_POSE) +# define SYSCFG_WKUP_WKEN SYSCFG_WKUP_WKEN_MSK + +/****************** Bit definition for SYSCFG_WKSR register ************************/ + +# define SYSCFG_WKSR_WKCLR_POSS 31U +# define SYSCFG_WKSR_WKCLR_MSK BIT(SYSCFG_WKSR_WKCLR_POSS) +# define SYSCFG_WKSR_WKCLR SYSCFG_WKSR_WKCLR_MSK + +# define SYSCFG_WKSR_LPLS_POSS 28U +# define SYSCFG_WKSR_LPLS_POSE 29U +# define SYSCFG_WKSR_LPLS_MSK BITS(SYSCFG_WKSR_LPLS_POSS, SYSCFG_WKSR_LPLS_POSE) +# define SYSCFG_WKSR_LPLS SYSCFG_WKSR_LPLS_MSK + +# define SYSCFG_WKSR_FLAG_POSS 16U +# define SYSCFG_WKSR_FLAG_MSK BIT(SYSCFG_WKSR_FLAG_POSS) +# define SYSCFG_WKSR_FLAG SYSCFG_WKSR_FLAG_MSK + +# define SYSCFG_WKSR_FG_POSS 0U +# define SYSCFG_WKSR_FG_POSE 15U +# define SYSCFG_WKSR_FG_MSK BITS(SYSCFG_WKSR_FG_POSS, SYSCFG_WKSR_FG_POSE) +# define SYSCFG_WKSR_FG SYSCFG_WKSR_FG_MSK + +/****************** Bit definition for SYSCFG_BKREG0 register ************************/ + +# define SYSCFG_BKREG0_BKREG0_POSS 0U +# define SYSCFG_BKREG0_BKREG0_POSE 31U +# define SYSCFG_BKREG0_BKREG0_MSK BITS(SYSCFG_BKREG0_BKREG0_POSS, SYSCFG_BKREG0_BKREG0_POSE) +# define SYSCFG_BKREG0_BKREG0 SYSCFG_BKREG0_BKREG0_MSK + +/****************** Bit definition for SYSCFG_BKREG1 register ************************/ + +# define SYSCFG_BKREG1_BKREG1_POSS 0U +# define SYSCFG_BKREG1_BKREG1_POSE 31U +# define SYSCFG_BKREG1_BKREG1_MSK BITS(SYSCFG_BKREG1_BKREG1_POSS, SYSCFG_BKREG1_BKREG1_POSE) +# define SYSCFG_BKREG1_BKREG1 SYSCFG_BKREG1_BKREG1_MSK + +/****************** Bit definition for SYSCFG_BKREG2 register ************************/ + +# define SYSCFG_BKREG2_BKREG2_POSS 0U +# define SYSCFG_BKREG2_BKREG2_POSE 31U +# define SYSCFG_BKREG2_BKREG2_MSK BITS(SYSCFG_BKREG2_BKREG2_POSS, SYSCFG_BKREG2_BKREG2_POSE) +# define SYSCFG_BKREG2_BKREG2 SYSCFG_BKREG2_BKREG2_MSK + +/****************** Bit definition for SYSCFG_BKREG3 register ************************/ + +# define SYSCFG_BKREG3_BKREG3_POSS 0U +# define SYSCFG_BKREG3_BKREG3_POSE 31U +# define SYSCFG_BKREG3_BKREG3_MSK BITS(SYSCFG_BKREG3_BKREG3_POSS, SYSCFG_BKREG3_BKREG3_POSE) +# define SYSCFG_BKREG3_BKREG3 SYSCFG_BKREG3_BKREG3_MSK + +/****************** Bit definition for SYSCFG_OPBERR register ************************/ + +# define SYSCFG_OPBERR_opt64_err_POS 25U +# define SYSCFG_OPBERR_opt64_err_MSK BIT(SYSCFG_OPBERR_opt64_err_POS) +# define SYSCFG_OPBERR_opt64_err SYSCFG_OPBERR_opt64_err_MSK + +# define SYSCFG_OPBERR_opt60_err_POS 24U +# define SYSCFG_OPBERR_opt60_err_MSK BIT(SYSCFG_OPBERR_opt60_err_POS) +# define SYSCFG_OPBERR_opt60_err SYSCFG_OPBERR_opt60_err_MSK + +# define SYSCFG_OPBERR_opt5C_err_POS 23U +# define SYSCFG_OPBERR_opt5C_err_MSK BIT(SYSCFG_OPBERR_opt5C_err_POS) +# define SYSCFG_OPBERR_opt5C_err SYSCFG_OPBERR_opt5C_err_MSK + +# define SYSCFG_OPBERR_opt58_err_POS 22U +# define SYSCFG_OPBERR_opt58_err_MSK BIT(SYSCFG_OPBERR_opt58_err_POS) +# define SYSCFG_OPBERR_opt58_err SYSCFG_OPBERR_opt58_err_MSK + +# define SYSCFG_OPBERR_opt54_err_POS 21U +# define SYSCFG_OPBERR_opt54_err_MSK BIT(SYSCFG_OPBERR_opt54_err_POS) +# define SYSCFG_OPBERR_opt54_err SYSCFG_OPBERR_opt54_err_MSK + +# define SYSCFG_OPBERR_opt50_err_POS 20U +# define SYSCFG_OPBERR_opt50_err_MSK BIT(SYSCFG_OPBERR_opt50_err_POS) +# define SYSCFG_OPBERR_opt50_err SYSCFG_OPBERR_opt50_err_MSK + +# define SYSCFG_OPBERR_opt4C_err_POS 19U +# define SYSCFG_OPBERR_opt4C_err_MSK BIT(SYSCFG_OPBERR_opt4C_err_POS) +# define SYSCFG_OPBERR_opt4C_err SYSCFG_OPBERR_opt4C_err_MSK + +# define SYSCFG_OPBERR_opt48_err_POS 18U +# define SYSCFG_OPBERR_opt48_err_MSK BIT(SYSCFG_OPBERR_opt48_err_POS) +# define SYSCFG_OPBERR_opt48_err SYSCFG_OPBERR_opt48_err_MSK + +# define SYSCFG_OPBERR_opt44_err_POS 17U +# define SYSCFG_OPBERR_opt44_err_MSK BIT(SYSCFG_OPBERR_opt44_err_POS) +# define SYSCFG_OPBERR_opt44_err SYSCFG_OPBERR_opt44_err_MSK + +# define SYSCFG_OPBERR_opt40_err_POS 16U +# define SYSCFG_OPBERR_opt40_err_MSK BIT(SYSCFG_OPBERR_opt40_err_POS) +# define SYSCFG_OPBERR_opt40_err SYSCFG_OPBERR_opt40_err_MSK + +# define SYSCFG_OPBERR_opt3C_err_POS 15U +# define SYSCFG_OPBERR_opt3C_err_MSK BIT(SYSCFG_OPBERR_opt3C_err_POS) +# define SYSCFG_OPBERR_opt3C_err SYSCFG_OPBERR_opt3C_err_MSK + +# define SYSCFG_OPBERR_opt38_err_POS 14U +# define SYSCFG_OPBERR_opt38_err_MSK BIT(SYSCFG_OPBERR_opt38_err_POS) +# define SYSCFG_OPBERR_opt38_err SYSCFG_OPBERR_opt38_err_MSK + +# define SYSCFG_OPBERR_opt34_err_POS 13U +# define SYSCFG_OPBERR_opt34_err_MSK BIT(SYSCFG_OPBERR_opt34_err_POS) +# define SYSCFG_OPBERR_opt34_err SYSCFG_OPBERR_opt34_err_MSK + +# define SYSCFG_OPBERR_opt20_err_POS 8U +# define SYSCFG_OPBERR_opt20_err_MSK BIT(SYSCFG_OPBERR_opt20_err_POS) +# define SYSCFG_OPBERR_opt20_err SYSCFG_OPBERR_opt20_err_MSK + +# define SYSCFG_OPBERR_opt1C_err_POS 7U +# define SYSCFG_OPBERR_opt1C_err_MSK BIT(SYSCFG_OPBERR_opt1C_err_POS) +# define SYSCFG_OPBERR_opt1C_err SYSCFG_OPBERR_opt1C_err_MSK + +# define SYSCFG_OPBERR_opt18_err_POS 6U +# define SYSCFG_OPBERR_opt18_err_MSK BIT(SYSCFG_OPBERR_opt18_err_POS) +# define SYSCFG_OPBERR_opt18_err SYSCFG_OPBERR_opt18_err_MSK + +# define SYSCFG_OPBERR_opt14_err_POS 5U +# define SYSCFG_OPBERR_opt14_err_MSK BIT(SYSCFG_OPBERR_opt14_err_POS) +# define SYSCFG_OPBERR_opt14_err SYSCFG_OPBERR_opt14_err_MSK + +# define SYSCFG_OPBERR_opt10_err_POS 4U +# define SYSCFG_OPBERR_opt10_err_MSK BIT(SYSCFG_OPBERR_opt10_err_POS) +# define SYSCFG_OPBERR_opt10_err SYSCFG_OPBERR_opt10_err_MSK + +# define SYSCFG_OPBERR_opt0C_err_POS 3U +# define SYSCFG_OPBERR_opt0C_err_MSK BIT(SYSCFG_OPBERR_opt0C_err_POS) +# define SYSCFG_OPBERR_opt0C_err SYSCFG_OPBERR_opt0C_err_MSK + +# define SYSCFG_OPBERR_opt08_err_POS 2U +# define SYSCFG_OPBERR_opt08_err_MSK BIT(SYSCFG_OPBERR_opt08_err_POS) +# define SYSCFG_OPBERR_opt08_err SYSCFG_OPBERR_opt08_err_MSK + +# define SYSCFG_OPBERR_opt04_err_POS 1U +# define SYSCFG_OPBERR_opt04_err_MSK BIT(SYSCFG_OPBERR_opt04_err_POS) +# define SYSCFG_OPBERR_opt04_err SYSCFG_OPBERR_opt04_err_MSK + +typedef struct +{ + __IO uint32_t REMAP; // 0x000 + __IO uint32_t ENGEN; // 0x004 + __IO uint32_t PWR; // 0x008 + __IO uint32_t IRSEL; // 0x00c + __I uint32_t SYSTRIM; // 0x010 + __I uint32_t CLKTRIM; // 0x014 + __I uint32_t OSCTRIM; // 0x018 + __I uint32_t IPTRIM; // 0x01c + __I uint32_t AHBIPEN; // 0x020 + __I uint32_t APB1IPEN; // 0x024 + __I uint32_t APB2IPEN; // 0x028 + __I uint32_t MEMMOD; // 0x02c + __I uint32_t ADCVREF; // 0x030 + __I uint32_t ADCTEMP; // 0x034 + __I uint32_t SYSSET; // 0x038 + __IO uint32_t CFG; // 0x03c + __IO uint32_t PWRCON; // 0x040 + __IO uint32_t WKTRIM; // 0x044 + __IO uint32_t WKUP; // 0x048 + __IO uint32_t WKSR; // 0x04c + __IO uint32_t BKREG0; // 0x050 + __IO uint32_t BKREG1; // 0x054 + __IO uint32_t BKREG2; // 0x058 + __IO uint32_t BKREG3; // 0x05c + __IO uint32_t RESERVED0[36]; // 0x060-0x0ec + __I uint32_t OPBERR; // 0x0f0 +} SYSCFG_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_tick.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_tick.h new file mode 100644 index 00000000000..8c1c743baf0 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_tick.h @@ -0,0 +1,109 @@ +/********************************************************************************** + * + * @file reg_tick.h + * @brief TICK Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __TICK_H__ +#define __TICK_H__ + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* ////#pragma anon_unions */ + +/****************** Bit definition for SYST_CSR register ************************/ + +#define SYST_CSR_ENABLE_POS 0U +#define SYST_CSR_ENABLE_MSK BIT(SYST_CSR_ENABLE_POS) +#define SYST_CSR_ENABLE SYST_CSR_ENABLE_MSK + +#define SYST_CSR_TICKIE_POS 1U +#define SYST_CSR_TICKIE_MSK BIT(SYST_CSR_TICKIE_POS) +#define SYST_CSR_TICKIE SYST_CSR_TICKIE_MSK + +#define SYST_CSR_CLKSRC_POS 2U +#define SYST_CSR_CLKSRC_MSK BIT(SYST_CSR_CLKSRC_POS) +#define SYST_CSR_CLKSRC SYST_CSR_CLKSRC_MSK + +#define SYST_CSR_COUNT_POS 16U +#define SYST_CSR_COUNT_MSK BIT(SYST_CSR_COUNT_POS) +#define SYST_CSR_COUNT SYST_CSR_COUNT_MSK + +/****************** Bit definition for SYST_RVR register ************************/ + +#define SYST_RVR_RELOAD_POSS 0U +#define SYST_RVR_RELOAD_POSE 23U +#define SYST_RVR_RELOAD_MSK BITS(SYST_RVR_RELOAD_POSS,SYST_RVR_RELOAD_POSE) +#define SYST_RVR_RELOAD SYST_RVR_RELOAD_MSK + +/****************** Bit definition for SYST_CVR register ************************/ + +#define SYST_CVR_CURRENT_POSS 0U +#define SYST_CVR_CURRENT_POSE 23U +#define SYST_CVR_CURRENT_MSK BITS(SYST_CVR_CURRENT_POSS,SYST_CVR_CURRENT_POSE) +#define SYST_CVR_CURRENT SYST_CVR_CURRENT_MSK + +/* TICK Register */ +#define pTICK TICK + +/* TICK CSR Register(TICK_CSR) */ +#define CSR_COUNTFLAG(x) (x<<16) /* Indicates whether the counter has counted to 0 since the last read of this register + 0 timer has not counted to 0 + 1 timer has counted to 0 */ +#define CSR_CLKSOURCE(x) (x<<2) /* Indicates the SysTick clock source: + 0 SysTick uses the optional external reference clock + 1 SysTick uses the processor clock */ +#define CSR_TICKINT(x) (x<<1) /* Indicates whether counting to 0 causes the status of the SysTick exception to change to pending: + 0 count to 0 does not affect the SysTick exception status + 1 count to 0 changes the SysTick exception status to pending */ +#define CSR_ENABLE(x) (x<<0) /* /Indicates the enabled status of the SysTick counter: + 0 counter is disabled + 1 counter is operating */ + + +/* TICK RVR Register(TICK_RVR) */ +#define RVR_RELOAD(x) (x<<0) /* The value to load into the SYST_CVR register when the counter reaches 0 */ + + +/* TICK CVR Register(TICK_CVR) */ +#define CVR_CURRENT(x) (x<<0) /* Current counter value + This is the value of the counter at the time it is sampled */ + +typedef struct +{ + __IO uint32_t CSR; /* 0x10, Control and Status */ + __IO uint32_t RVR; /* 0x14, Reload Value */ + __IO uint32_t CVR; /* 0x18, Current Value */ +} SYST_TypeDef; + + +#else +/* */ +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_timer.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_timer.h new file mode 100644 index 00000000000..f690832578c --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_timer.h @@ -0,0 +1,901 @@ +/********************************************************************************** + * + * @file reg_timer.h + * @brief TIMER Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __TIMER_H__ +#define __TIMER_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + +/****************** Bit definition for TIMER_CON1 register ************************/ + +#define TIMER_CON1_DBGSEL_POS 15U +#define TIMER_CON1_DBGSEL_MSK BIT(TIMER_CON1_DBGSEL_POS) +#define TIMER_CON1_DBGSEL TIMER_CON1_DBGSEL_MSK + +#define TIMER_CON1_DFCKSEL_POSS 8U +#define TIMER_CON1_DFCKSEL_POSE 9U +#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS, TIMER_CON1_DFCKSEL_POSE) +#define TIMER_CON1_DFCKSEL TIMER_CON1_DFCKSEL_MSK + +#define TIMER_CON1_ARPEN_POS 7U +#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) +#define TIMER_CON1_ARPEN TIMER_CON1_ARPEN_MSK + +#define TIMER_CON1_CMSEL_POSS 5U +#define TIMER_CON1_CMSEL_POSE 6U +#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS, TIMER_CON1_CMSEL_POSE) +#define TIMER_CON1_CMSEL TIMER_CON1_CMSEL_MSK + +#define TIMER_CON1_DIRSEL_POS 4U +#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) +#define TIMER_CON1_DIRSEL TIMER_CON1_DIRSEL_MSK + +#define TIMER_CON1_SPMEN_POS 3U +#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) +#define TIMER_CON1_SPMEN TIMER_CON1_SPMEN_MSK + +#define TIMER_CON1_UERSEL_POS 2U +#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) +#define TIMER_CON1_UERSEL TIMER_CON1_UERSEL_MSK + +#define TIMER_CON1_DISUE_POS 1U +#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) +#define TIMER_CON1_DISUE TIMER_CON1_DISUE_MSK + +#define TIMER_CON1_CNTEN_POS 0U +#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) +#define TIMER_CON1_CNTEN TIMER_CON1_CNTEN_MSK + +/****************** Bit definition for TIMER_CON2 register ************************/ + +#define TIMER_CON2_OISS4_POS 14U +#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) +#define TIMER_CON2_OISS4 TIMER_CON2_OISS4_MSK + +#define TIMER_CON2_OISS3N_POS 13U +#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) +#define TIMER_CON2_OISS3N TIMER_CON2_OISS3N_MSK + +#define TIMER_CON2_OISS3_POS 12U +#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) +#define TIMER_CON2_OISS3 TIMER_CON2_OISS3_MSK + +#define TIMER_CON2_OISS2N_POS 11U +#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) +#define TIMER_CON2_OISS2N TIMER_CON2_OISS2N_MSK + +#define TIMER_CON2_OISS2_POS 10U +#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) +#define TIMER_CON2_OISS2 TIMER_CON2_OISS2_MSK + +#define TIMER_CON2_OISS1N_POS 9U +#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) +#define TIMER_CON2_OISS1N TIMER_CON2_OISS1N_MSK + +#define TIMER_CON2_OISS1_POS 8U +#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) +#define TIMER_CON2_OISS1 TIMER_CON2_OISS1_MSK + +#define TIMER_CON2_I1SEL_POS 7U +#define TIMER_CON2_I1SEL_MSK BIT(TIMER_CON2_I1SEL_POS) +#define TIMER_CON2_I1SEL TIMER_CON2_I1SEL_MSK + +#define TIMER_CON2_MMSEL_POSS 4U +#define TIMER_CON2_MMSEL_POSE 6U +#define TIMER_CON2_MMSEL_MSK BITS(TIMER_CON2_MMSEL_POSS, TIMER_CON2_MMSEL_POSE) +#define TIMER_CON2_MMSEL TIMER_CON2_MMSEL_MSK + +#define TIMER_CON2_CCDMASEL_POS 3U +#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) +#define TIMER_CON2_CCDMASEL TIMER_CON2_CCDMASEL_MSK + +#define TIMER_CON2_CCUSEL_POS 2U +#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) +#define TIMER_CON2_CCUSEL TIMER_CON2_CCUSEL_MSK + +#define TIMER_CON2_CCPCEN_POS 0U +#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) +#define TIMER_CON2_CCPCEN TIMER_CON2_CCPCEN_MSK + +/****************** Bit definition for TIMER_SMCON register ************************/ + +#define TIMER_SMCON_TSSEL2_POSS 20U +#define TIMER_SMCON_TSSEL2_POSE 21U +#define TIMER_SMCON_TSSEL2_MSK BITS(TIMER_SMCON_TSSEL2_POSS, TIMER_SMCON_TSSEL2_POSE) +#define TIMER_SMCON_TSSEL2 TIMER_SMCON_TSSEL2_MSK + +#define TIMER_SMCON_ETPOL_POS 15U +#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) +#define TIMER_SMCON_ETPOL TIMER_SMCON_ETPOL_MSK + +#define TIMER_SMCON_ECM2EN_POS 14U +#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) +#define TIMER_SMCON_ECM2EN TIMER_SMCON_ECM2EN_MSK + +#define TIMER_SMCON_ETPRES_POSS 12U +#define TIMER_SMCON_ETPRES_POSE 13U +#define TIMER_SMCON_ETPRES_MSK BITS(TIMER_SMCON_ETPRES_POSS, TIMER_SMCON_ETPRES_POSE) +#define TIMER_SMCON_ETPRES TIMER_SMCON_ETPRES_MSK + +#define TIMER_SMCON_ETFLT_POSS 8U +#define TIMER_SMCON_ETFLT_POSE 11U +#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS, TIMER_SMCON_ETFLT_POSE) +#define TIMER_SMCON_ETFLT TIMER_SMCON_ETFLT_MSK + +#define TIMER_SMCON_MSCFG_POS 7U +#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) +#define TIMER_SMCON_MSCFG TIMER_SMCON_MSCFG_MSK + +#define TIMER_SMCON_TSSEL1_POSS 4U +#define TIMER_SMCON_TSSEL1_POSE 6U +#define TIMER_SMCON_TSSEL1_MSK BITS(TIMER_SMCON_TSSEL1_POSS, TIMER_SMCON_TSSEL1_POSE) +#define TIMER_SMCON_TSSEL1 TIMER_SMCON_TSSEL1_MSK + +#define TIMER_SMCON_SMODS_POSS 0U +#define TIMER_SMCON_SMODS_POSE 2U +#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS, TIMER_SMCON_SMODS_POSE) +#define TIMER_SMCON_SMODS TIMER_SMCON_SMODS_MSK + +/****************** Bit definition for TIMER_IER register ************************/ + +#define TIMER_IER_CH4OV_POS 12U +#define TIMER_IER_CH4OV_MSK BIT(TIMER_IER_CH4OV_POS) +#define TIMER_IER_CH4OV TIMER_IER_CH4OV_MSK + +#define TIMER_IER_CH3OV_POS 11U +#define TIMER_IER_CH3OV_MSK BIT(TIMER_IER_CH3OV_POS) +#define TIMER_IER_CH3OV TIMER_IER_CH3OV_MSK + +#define TIMER_IER_CH2OV_POS 10U +#define TIMER_IER_CH2OV_MSK BIT(TIMER_IER_CH2OV_POS) +#define TIMER_IER_CH2OV TIMER_IER_CH2OV_MSK + +#define TIMER_IER_CH1OV_POS 9U +#define TIMER_IER_CH1OV_MSK BIT(TIMER_IER_CH1OV_POS) +#define TIMER_IER_CH1OV TIMER_IER_CH1OV_MSK + +#define TIMER_IER_BRK_POS 7U +#define TIMER_IER_BRK_MSK BIT(TIMER_IER_BRK_POS) +#define TIMER_IER_BRK TIMER_IER_BRK_MSK + +#define TIMER_IER_TRGI_POS 6U +#define TIMER_IER_TRGI_MSK BIT(TIMER_IER_TRGI_POS) +#define TIMER_IER_TRGI TIMER_IER_TRGI_MSK + +#define TIMER_IER_COM_POS 5U +#define TIMER_IER_COM_MSK BIT(TIMER_IER_COM_POS) +#define TIMER_IER_COM TIMER_IER_COM_MSK + +#define TIMER_IER_CH4_POS 4U +#define TIMER_IER_CH4_MSK BIT(TIMER_IER_CH4_POS) +#define TIMER_IER_CH4 TIMER_IER_CH4_MSK + +#define TIMER_IER_CH3_POS 3U +#define TIMER_IER_CH3_MSK BIT(TIMER_IER_CH3_POS) +#define TIMER_IER_CH3 TIMER_IER_CH3_MSK + +#define TIMER_IER_CH2_POS 2U +#define TIMER_IER_CH2_MSK BIT(TIMER_IER_CH2_POS) +#define TIMER_IER_CH2 TIMER_IER_CH2_MSK + +#define TIMER_IER_CH1_POS 1U +#define TIMER_IER_CH1_MSK BIT(TIMER_IER_CH1_POS) +#define TIMER_IER_CH1 TIMER_IER_CH1_MSK + +#define TIMER_IER_UPD_POS 0U +#define TIMER_IER_UPD_MSK BIT(TIMER_IER_UPD_POS) +#define TIMER_IER_UPD TIMER_IER_UPD_MSK + +/****************** Bit definition for TIMER_IDR register ************************/ + +#define TIMER_IDR_CH4OV_POS 12U +#define TIMER_IDR_CH4OV_MSK BIT(TIMER_IDR_CH4OV_POS) +#define TIMER_IDR_CH4OV TIMER_IDR_CH4OV_MSK + +#define TIMER_IDR_CH3OV_POS 11U +#define TIMER_IDR_CH3OV_MSK BIT(TIMER_IDR_CH3OV_POS) +#define TIMER_IDR_CH3OV TIMER_IDR_CH3OV_MSK + +#define TIMER_IDR_CH2OV_POS 10U +#define TIMER_IDR_CH2OV_MSK BIT(TIMER_IDR_CH2OV_POS) +#define TIMER_IDR_CH2OV TIMER_IDR_CH2OV_MSK + +#define TIMER_IDR_CH1OV_POS 9U +#define TIMER_IDR_CH1OV_MSK BIT(TIMER_IDR_CH1OV_POS) +#define TIMER_IDR_CH1OV TIMER_IDR_CH1OV_MSK + +#define TIMER_IDR_BRK_POS 7U +#define TIMER_IDR_BRK_MSK BIT(TIMER_IDR_BRK_POS) +#define TIMER_IDR_BRK TIMER_IDR_BRK_MSK + +#define TIMER_IDR_TRGI_POS 6U +#define TIMER_IDR_TRGI_MSK BIT(TIMER_IDR_TRGI_POS) +#define TIMER_IDR_TRGI TIMER_IDR_TRGI_MSK + +#define TIMER_IDR_COM_POS 5U +#define TIMER_IDR_COM_MSK BIT(TIMER_IDR_COM_POS) +#define TIMER_IDR_COM TIMER_IDR_COM_MSK + +#define TIMER_IDR_CH4_POS 4U +#define TIMER_IDR_CH4_MSK BIT(TIMER_IDR_CH4_POS) +#define TIMER_IDR_CH4 TIMER_IDR_CH4_MSK + +#define TIMER_IDR_CH3_POS 3U +#define TIMER_IDR_CH3_MSK BIT(TIMER_IDR_CH3_POS) +#define TIMER_IDR_CH3 TIMER_IDR_CH3_MSK + +#define TIMER_IDR_CH2_POS 2U +#define TIMER_IDR_CH2_MSK BIT(TIMER_IDR_CH2_POS) +#define TIMER_IDR_CH2 TIMER_IDR_CH2_MSK + +#define TIMER_IDR_CH1_POS 1U +#define TIMER_IDR_CH1_MSK BIT(TIMER_IDR_CH1_POS) +#define TIMER_IDR_CH1 TIMER_IDR_CH1_MSK + +#define TIMER_IDR_UPD_POS 0U +#define TIMER_IDR_UPD_MSK BIT(TIMER_IDR_UPD_POS) +#define TIMER_IDR_UPD TIMER_IDR_UPD_MSK + +/****************** Bit definition for TIMER_IVS register ************************/ + +#define TIMER_IVS_CH4OV_POS 12U +#define TIMER_IVS_CH4OV_MSK BIT(TIMER_IVS_CH4OV_POS) +#define TIMER_IVS_CH4OV TIMER_IVS_CH4OV_MSK + +#define TIMER_IVS_CH3OV_POS 11U +#define TIMER_IVS_CH3OV_MSK BIT(TIMER_IVS_CH3OV_POS) +#define TIMER_IVS_CH3OV TIMER_IVS_CH3OV_MSK + +#define TIMER_IVS_CH2OV_POS 10U +#define TIMER_IVS_CH2OV_MSK BIT(TIMER_IVS_CH2OV_POS) +#define TIMER_IVS_CH2OV TIMER_IVS_CH2OV_MSK + +#define TIMER_IVS_CH1OV_POS 9U +#define TIMER_IVS_CH1OV_MSK BIT(TIMER_IVS_CH1OV_POS) +#define TIMER_IVS_CH1OV TIMER_IVS_CH1OV_MSK + +#define TIMER_IVS_BRK_POS 7U +#define TIMER_IVS_BRK_MSK BIT(TIMER_IVS_BRK_POS) +#define TIMER_IVS_BRK TIMER_IVS_BRK_MSK + +#define TIMER_IVS_TRGI_POS 6U +#define TIMER_IVS_TRGI_MSK BIT(TIMER_IVS_TRGI_POS) +#define TIMER_IVS_TRGI TIMER_IVS_TRGI_MSK + +#define TIMER_IVS_COM_POS 5U +#define TIMER_IVS_COM_MSK BIT(TIMER_IVS_COM_POS) +#define TIMER_IVS_COM TIMER_IVS_COM_MSK + +#define TIMER_IVS_CH4_POS 4U +#define TIMER_IVS_CH4_MSK BIT(TIMER_IVS_CH4_POS) +#define TIMER_IVS_CH4 TIMER_IVS_CH4_MSK + +#define TIMER_IVS_CH3_POS 3U +#define TIMER_IVS_CH3_MSK BIT(TIMER_IVS_CH3_POS) +#define TIMER_IVS_CH3 TIMER_IVS_CH3_MSK + +#define TIMER_IVS_CH2_POS 2U +#define TIMER_IVS_CH2_MSK BIT(TIMER_IVS_CH2_POS) +#define TIMER_IVS_CH2 TIMER_IVS_CH2_MSK + +#define TIMER_IVS_CH1_POS 1U +#define TIMER_IVS_CH1_MSK BIT(TIMER_IVS_CH1_POS) +#define TIMER_IVS_CH1 TIMER_IVS_CH1_MSK + +#define TIMER_IVS_UPD_POS 0U +#define TIMER_IVS_UPD_MSK BIT(TIMER_IVS_UPD_POS) +#define TIMER_IVS_UPD TIMER_IVS_UPD_MSK + +/****************** Bit definition for TIMER_RIF register ************************/ + +#define TIMER_RIF_CH4OV_POS 12U +#define TIMER_RIF_CH4OV_MSK BIT(TIMER_RIF_CH4OV_POS) +#define TIMER_RIF_CH4OV TIMER_RIF_CH4OV_MSK + +#define TIMER_RIF_CH3OV_POS 11U +#define TIMER_RIF_CH3OV_MSK BIT(TIMER_RIF_CH3OV_POS) +#define TIMER_RIF_CH3OV TIMER_RIF_CH3OV_MSK + +#define TIMER_RIF_CH2OV_POS 10U +#define TIMER_RIF_CH2OV_MSK BIT(TIMER_RIF_CH2OV_POS) +#define TIMER_RIF_CH2OV TIMER_RIF_CH2OV_MSK + +#define TIMER_RIF_CH1OV_POS 9U +#define TIMER_RIF_CH1OV_MSK BIT(TIMER_RIF_CH1OV_POS) +#define TIMER_RIF_CH1OV TIMER_RIF_CH1OV_MSK + +#define TIMER_RIF_BRK_POS 7U +#define TIMER_RIF_BRK_MSK BIT(TIMER_RIF_BRK_POS) +#define TIMER_RIF_BRK TIMER_RIF_BRK_MSK + +#define TIMER_RIF_TRGI_POS 6U +#define TIMER_RIF_TRGI_MSK BIT(TIMER_RIF_TRGI_POS) +#define TIMER_RIF_TRGI TIMER_RIF_TRGI_MSK + +#define TIMER_RIF_COM_POS 5U +#define TIMER_RIF_COM_MSK BIT(TIMER_RIF_COM_POS) +#define TIMER_RIF_COM TIMER_RIF_COM_MSK + +#define TIMER_RIF_CH4_POS 4U +#define TIMER_RIF_CH4_MSK BIT(TIMER_RIF_CH4_POS) +#define TIMER_RIF_CH4 TIMER_RIF_CH4_MSK + +#define TIMER_RIF_CH3_POS 3U +#define TIMER_RIF_CH3_MSK BIT(TIMER_RIF_CH3_POS) +#define TIMER_RIF_CH3 TIMER_RIF_CH3_MSK + +#define TIMER_RIF_CH2_POS 2U +#define TIMER_RIF_CH2_MSK BIT(TIMER_RIF_CH2_POS) +#define TIMER_RIF_CH2 TIMER_RIF_CH2_MSK + +#define TIMER_RIF_CH1_POS 1U +#define TIMER_RIF_CH1_MSK BIT(TIMER_RIF_CH1_POS) +#define TIMER_RIF_CH1 TIMER_RIF_CH1_MSK + +#define TIMER_RIF_UPD_POS 0U +#define TIMER_RIF_UPD_MSK BIT(TIMER_RIF_UPD_POS) +#define TIMER_RIF_UPD TIMER_RIF_UPD_MSK + +/****************** Bit definition for TIMER_IFM register ************************/ + +#define TIMER_IFM_CH4OV_POS 12U +#define TIMER_IFM_CH4OV_MSK BIT(TIMER_IFM_CH4OV_POS) +#define TIMER_IFM_CH4OV TIMER_IFM_CH4OV_MSK + +#define TIMER_IFM_CH3OV_POS 11U +#define TIMER_IFM_CH3OV_MSK BIT(TIMER_IFM_CH3OV_POS) +#define TIMER_IFM_CH3OV TIMER_IFM_CH3OV_MSK + +#define TIMER_IFM_CH2OV_POS 10U +#define TIMER_IFM_CH2OV_MSK BIT(TIMER_IFM_CH2OV_POS) +#define TIMER_IFM_CH2OV TIMER_IFM_CH2OV_MSK + +#define TIMER_IFM_CH1OV_POS 9U +#define TIMER_IFM_CH1OV_MSK BIT(TIMER_IFM_CH1OV_POS) +#define TIMER_IFM_CH1OV TIMER_IFM_CH1OV_MSK + +#define TIMER_IFM_BRK_POS 7U +#define TIMER_IFM_BRK_MSK BIT(TIMER_IFM_BRK_POS) +#define TIMER_IFM_BRK TIMER_IFM_BRK_MSK + +#define TIMER_IFM_TRGI_POS 6U +#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) +#define TIMER_IFM_TRGI TIMER_IFM_TRGI_MSK + +#define TIMER_IFM_COM_POS 5U +#define TIMER_IFM_COM_MSK BIT(TIMER_IFM_COM_POS) +#define TIMER_IFM_COM TIMER_IFM_COM_MSK + +#define TIMER_IFM_CH4_POS 4U +#define TIMER_IFM_CH4_MSK BIT(TIMER_IFM_CH4_POS) +#define TIMER_IFM_CH4 TIMER_IFM_CH4_MSK + +#define TIMER_IFM_CH3_POS 3U +#define TIMER_IFM_CH3_MSK BIT(TIMER_IFM_CH3_POS) +#define TIMER_IFM_CH3 TIMER_IFM_CH3_MSK + +#define TIMER_IFM_CH2_POS 2U +#define TIMER_IFM_CH2_MSK BIT(TIMER_IFM_CH2_POS) +#define TIMER_IFM_CH2 TIMER_IFM_CH2_MSK + +#define TIMER_IFM_CH1_POS 1U +#define TIMER_IFM_CH1_MSK BIT(TIMER_IFM_CH1_POS) +#define TIMER_IFM_CH1 TIMER_IFM_CH1_MSK + +#define TIMER_IFM_UPD_POS 0U +#define TIMER_IFM_UPD_MSK BIT(TIMER_IFM_UPD_POS) +#define TIMER_IFM_UPD TIMER_IFM_UPD_MSK + +/****************** Bit definition for TIMER_ICR register ************************/ + +#define TIMER_ICR_CH4OV_POS 12U +#define TIMER_ICR_CH4OV_MSK BIT(TIMER_ICR_CH4OV_POS) +#define TIMER_ICR_CH4OV TIMER_ICR_CH4OV_MSK + +#define TIMER_ICR_CH3OV_POS 11U +#define TIMER_ICR_CH3OV_MSK BIT(TIMER_ICR_CH3OV_POS) +#define TIMER_ICR_CH3OV TIMER_ICR_CH3OV_MSK + +#define TIMER_ICR_CH2OV_POS 10U +#define TIMER_ICR_CH2OV_MSK BIT(TIMER_ICR_CH2OV_POS) +#define TIMER_ICR_CH2OV TIMER_ICR_CH2OV_MSK + +#define TIMER_ICR_CH1OV_POS 9U +#define TIMER_ICR_CH1OV_MSK BIT(TIMER_ICR_CH1OV_POS) +#define TIMER_ICR_CH1OV TIMER_ICR_CH1OV_MSK + +#define TIMER_ICR_BRK_POS 7U +#define TIMER_ICR_BRK_MSK BIT(TIMER_ICR_BRK_POS) +#define TIMER_ICR_BRK TIMER_ICR_BRK_MSK + +#define TIMER_ICR_TRGI_POS 6U +#define TIMER_ICR_TRGI_MSK BIT(TIMER_ICR_TRGI_POS) +#define TIMER_ICR_TRGI TIMER_ICR_TRGI_MSK + +#define TIMER_ICR_COM_POS 5U +#define TIMER_ICR_COM_MSK BIT(TIMER_ICR_COM_POS) +#define TIMER_ICR_COM TIMER_ICR_COM_MSK + +#define TIMER_ICR_CH4_POS 4U +#define TIMER_ICR_CH4_MSK BIT(TIMER_ICR_CH4_POS) +#define TIMER_ICR_CH4 TIMER_ICR_CH4_MSK + +#define TIMER_ICR_CH3_POS 3U +#define TIMER_ICR_CH3_MSK BIT(TIMER_ICR_CH3_POS) +#define TIMER_ICR_CH3 TIMER_ICR_CH3_MSK + +#define TIMER_ICR_CH2_POS 2U +#define TIMER_ICR_CH2_MSK BIT(TIMER_ICR_CH2_POS) +#define TIMER_ICR_CH2 TIMER_ICR_CH2_MSK + +#define TIMER_ICR_CH1_POS 1U +#define TIMER_ICR_CH1_MSK BIT(TIMER_ICR_CH1_POS) +#define TIMER_ICR_CH1 TIMER_ICR_CH1_MSK + +#define TIMER_ICR_UPD_POS 0U +#define TIMER_ICR_UPD_MSK BIT(TIMER_ICR_UPD_POS) +#define TIMER_ICR_UPD TIMER_ICR_UPD_MSK + +/****************** Bit definition for TIMER_SGE register ************************/ + +#define TIMER_SGE_SGBRK_POS 7U +#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) +#define TIMER_SGE_SGBRK TIMER_SGE_SGBRK_MSK + +#define TIMER_SGE_SGTRGI_POS 6U +#define TIMER_SGE_SGTRGI_MSK BIT(TIMER_SGE_SGTRGI_POS) +#define TIMER_SGE_SGTRGI TIMER_SGE_SGTRGI_MSK + +#define TIMER_SGE_SGCOM_POS 5U +#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) +#define TIMER_SGE_SGCOM TIMER_SGE_SGCOM_MSK + +#define TIMER_SGE_SGCH4_POS 4U +#define TIMER_SGE_SGCH4_MSK BIT(TIMER_SGE_SGCH4_POS) +#define TIMER_SGE_SGCH4 TIMER_SGE_SGCH4_MSK + +#define TIMER_SGE_SGCH3_POS 3U +#define TIMER_SGE_SGCH3_MSK BIT(TIMER_SGE_SGCH3_POS) +#define TIMER_SGE_SGCH3 TIMER_SGE_SGCH3_MSK + +#define TIMER_SGE_SGCH2_POS 2U +#define TIMER_SGE_SGCH2_MSK BIT(TIMER_SGE_SGCH2_POS) +#define TIMER_SGE_SGCH2 TIMER_SGE_SGCH2_MSK + +#define TIMER_SGE_SGCH1_POS 1U +#define TIMER_SGE_SGCH1_MSK BIT(TIMER_SGE_SGCH1_POS) +#define TIMER_SGE_SGCH1 TIMER_SGE_SGCH1_MSK + +#define TIMER_SGE_SGUPD_POS 0U +#define TIMER_SGE_SGUPD_MSK BIT(TIMER_SGE_SGUPD_POS) +#define TIMER_SGE_SGUPD TIMER_SGE_SGUPD_MSK + +/****************** Bit definition for TIMER_CHMR1_OUTPUT register ************************/ + +#define TIMER_CHMR1_OUTPUT_CH2OCLREN_POS 15U +#define TIMER_CHMR1_OUTPUT_CH2OCLREN_MSK BIT(TIMER_CHMR1_OUTPUT_CH2OCLREN_POS) +#define TIMER_CHMR1_OUTPUT_CH2OCLREN TIMER_CHMR1_OUTPUT_CH2OCLREN_MSK + +#define TIMER_CHMR1_OUTPUT_CH2MOD_POSS 12U +#define TIMER_CHMR1_OUTPUT_CH2MOD_POSE 14U +#define TIMER_CHMR1_OUTPUT_CH2MOD_MSK BITS(TIMER_CHMR1_OUTPUT_CH2MOD_POSS, TIMER_CHMR1_OUTPUT_CH2MOD_POSE) +#define TIMER_CHMR1_OUTPUT_CH2MOD TIMER_CHMR1_OUTPUT_CH2MOD_MSK + +#define TIMER_CHMR1_OUTPUT_CH2PEN_POS 11U +#define TIMER_CHMR1_OUTPUT_CH2PEN_MSK BIT(TIMER_CHMR1_OUTPUT_CH2PEN_POS) +#define TIMER_CHMR1_OUTPUT_CH2PEN TIMER_CHMR1_OUTPUT_CH2PEN_MSK + +#define TIMER_CHMR1_OUTPUT_CH2FEN_POS 10U +#define TIMER_CHMR1_OUTPUT_CH2FEN_MSK BIT(TIMER_CHMR1_OUTPUT_CH2FEN_POS) +#define TIMER_CHMR1_OUTPUT_CH2FEN TIMER_CHMR1_OUTPUT_CH2FEN_MSK + +#define TIMER_CHMR1_OUTPUT_CC2SSEL_POSS 8U +#define TIMER_CHMR1_OUTPUT_CC2SSEL_POSE 9U +#define TIMER_CHMR1_OUTPUT_CC2SSEL_MSK BITS(TIMER_CHMR1_OUTPUT_CC2SSEL_POSS, TIMER_CHMR1_OUTPUT_CC2SSEL_POSE) +#define TIMER_CHMR1_OUTPUT_CC2SSEL TIMER_CHMR1_OUTPUT_CC2SSEL_MSK + +#define TIMER_CHMR1_OUTPUT_CH1OCLREN_POS 7U +#define TIMER_CHMR1_OUTPUT_CH1OCLREN_MSK BIT(TIMER_CHMR1_OUTPUT_CH1OCLREN_POS) +#define TIMER_CHMR1_OUTPUT_CH1OCLREN TIMER_CHMR1_OUTPUT_CH1OCLREN_MSK + +#define TIMER_CHMR1_OUTPUT_CH1MOD_POSS 4U +#define TIMER_CHMR1_OUTPUT_CH1MOD_POSE 6U +#define TIMER_CHMR1_OUTPUT_CH1MOD_MSK BITS(TIMER_CHMR1_OUTPUT_CH1MOD_POSS, TIMER_CHMR1_OUTPUT_CH1MOD_POSE) +#define TIMER_CHMR1_OUTPUT_CH1MOD TIMER_CHMR1_OUTPUT_CH1MOD_MSK + +#define TIMER_CHMR1_OUTPUT_CH1PEN_POS 3U +#define TIMER_CHMR1_OUTPUT_CH1PEN_MSK BIT(TIMER_CHMR1_OUTPUT_CH1PEN_POS) +#define TIMER_CHMR1_OUTPUT_CH1PEN TIMER_CHMR1_OUTPUT_CH1PEN_MSK + +#define TIMER_CHMR1_OUTPUT_CH1FEN_POS 2U +#define TIMER_CHMR1_OUTPUT_CH1FEN_MSK BIT(TIMER_CHMR1_OUTPUT_CH1FEN_POS) +#define TIMER_CHMR1_OUTPUT_CH1FEN TIMER_CHMR1_OUTPUT_CH1FEN_MSK + +#define TIMER_CHMR1_OUTPUT_CC1SSEL_POSS 0U +#define TIMER_CHMR1_OUTPUT_CC1SSEL_POSE 1U +#define TIMER_CHMR1_OUTPUT_CC1SSEL_MSK BITS(TIMER_CHMR1_OUTPUT_CC1SSEL_POSS, TIMER_CHMR1_OUTPUT_CC1SSEL_POSE) +#define TIMER_CHMR1_OUTPUT_CC1SSEL TIMER_CHMR1_OUTPUT_CC1SSEL_MSK + +/****************** Bit definition for AD16C4T_CHMR1_INPUT register ************************/ + +#define TIMER_CHMR1_INPUT_I2FLT_POSS 12U +#define TIMER_CHMR1_INPUT_I2FLT_POSE 15U +#define TIMER_CHMR1_INPUT_I2FLT_MSK BITS(TIMER_CHMR1_INPUT_I2FLT_POSS,TIMER_CHMR1_INPUT_I2FLT_POSE) +#define TIMER_CHMR1_INPUT_I2FLT TIMER_CHMR1_INPUT_I2FLT_MSK + +#define TIMER_CHMR1_INPUT_I2PRES_POSS 10U +#define TIMER_CHMR1_INPUT_I2PRES_POSE 11U +#define TIMER_CHMR1_INPUT_I2PRES_MSK BITS(TIMER_CHMR1_INPUT_I2PRES_POSS,TIMER_CHMR1_INPUT_I2PRES_POSE) +#define TIMER_CHMR1_INPUT_I2PRES TIMER_CHMR1_INPUT_I2PRES_MSK + +#define TIMER_CHMR1_INPUT_CC2SSEL_POSS 8U +#define TIMER_CHMR1_INPUT_CC2SSEL_POSE 9U +#define TIMER_CHMR1_INPUT_CC2SSEL_MSK BITS(TIMER_CHMR1_INPUT_CC2SSEL_POSS,TIMER_CHMR1_INPUT_CC2SSEL_POSE) +#define TIMER_CHMR1_INPUT_CC2SSEL TIMER_CHMR1_INPUT_CC2SSEL_MSK + +#define TIMER_CHMR1_INPUT_I1FLT_POSS 4U +#define TIMER_CHMR1_INPUT_I1FLT_POSE 7U +#define TIMER_CHMR1_INPUT_I1FLT_MSK BITS(TIMER_CHMR1_INPUT_I1FLT_POSS,TIMER_CHMR1_INPUT_I1FLT_POSE) +#define TIMER_CHMR1_INPUT_I1FLT TIMER_CHMR1_INPUT_I1FLT_MSK + +#define TIMER_CHMR1_INPUT_I1PRES_POSS 2U +#define TIMER_CHMR1_INPUT_I1PRES_POSE 3U +#define TIMER_CHMR1_INPUT_I1PRES_MSK BITS(TIMER_CHMR1_INPUT_I1PRES_POSS,TIMER_CHMR1_INPUT_I1PRES_POSE) +#define TIMER_CHMR1_INPUT_I1PRES TIMER_CHMR1_INPUT_I1PRES_MSK + +#define TIMER_CHMR1_INPUT_CC1SSEL_POSS 0U +#define TIMER_CHMR1_INPUT_CC1SSEL_POSE 1U +#define TIMER_CHMR1_INPUT_CC1SSEL_MSK BITS(TIMER_CHMR1_INPUT_CC1SSEL_POSS,TIMER_CHMR1_INPUT_CC1SSEL_POSE) +#define TIMER_CHMR1_INPUT_CC1SSEL TIMER_CHMR1_INPUT_CC1SSEL_MSK + +/****************** Bit definition for TIMER_CHMR2_OUTPUT register ************************/ + +#define TIMER_CHMR2_OUTPUT_CH4OCLREN_POS 15U +#define TIMER_CHMR2_OUTPUT_CH4OCLREN_MSK BIT(TIMER_CHMR2_OUTPUT_CH4OCLREN_POS) +#define TIMER_CHMR2_OUTPUT_CH4OCLREN TIMER_CHMR2_OUTPUT_CH4OCLREN_MSK + +#define TIMER_CHMR2_OUTPUT_CH4MOD_POSS 12U +#define TIMER_CHMR2_OUTPUT_CH4MOD_POSE 14U +#define TIMER_CHMR2_OUTPUT_CH4MOD_MSK BITS(TIMER_CHMR2_OUTPUT_CH4MOD_POSS, TIMER_CHMR2_OUTPUT_CH4MOD_POSE) +#define TIMER_CHMR2_OUTPUT_CH4MOD TIMER_CHMR2_OUTPUT_CH4MOD_MSK + +#define TIMER_CHMR2_OUTPUT_CH4PEN_POS 11U +#define TIMER_CHMR2_OUTPUT_CH4PEN_MSK BIT(TIMER_CHMR2_OUTPUT_CH4PEN_POS) +#define TIMER_CHMR2_OUTPUT_CH4PEN TIMER_CHMR2_OUTPUT_CH4PEN_MSK + +#define TIMER_CHMR2_OUTPUT_CH4FEN_POS 10U +#define TIMER_CHMR2_OUTPUT_CH4FEN_MSK BIT(TIMER_CHMR2_OUTPUT_CH4FEN_POS) +#define TIMER_CHMR2_OUTPUT_CH4FEN TIMER_CHMR2_OUTPUT_CH4FEN_MSK + +#define TIMER_CHMR2_OUTPUT_CC4SSEL_POSS 8U +#define TIMER_CHMR2_OUTPUT_CC4SSEL_POSE 9U +#define TIMER_CHMR2_OUTPUT_CC4SSEL_MSK BITS(TIMER_CHMR2_OUTPUT_CC4SSEL_POSS, TIMER_CHMR2_OUTPUT_CC4SSEL_POSE) +#define TIMER_CHMR2_OUTPUT_CC4SSEL TIMER_CHMR2_OUTPUT_CC4SSEL_MSK + +#define TIMER_CHMR2_OUTPUT_CH3OCLREN_POS 7U +#define TIMER_CHMR2_OUTPUT_CH3OCLREN_MSK BIT(TIMER_CHMR2_OUTPUT_CH3OCLREN_POS) +#define TIMER_CHMR2_OUTPUT_CH3OCLREN TIMER_CHMR2_OUTPUT_CH3OCLREN_MSK + +#define TIMER_CHMR2_OUTPUT_CH3MOD_POSS 4U +#define TIMER_CHMR2_OUTPUT_CH3MOD_POSE 6U +#define TIMER_CHMR2_OUTPUT_CH3MOD_MSK BITS(TIMER_CHMR2_OUTPUT_CH3MOD_POSS, TIMER_CHMR2_OUTPUT_CH3MOD_POSE) +#define TIMER_CHMR2_OUTPUT_CH3MOD TIMER_CHMR2_OUTPUT_CH3MOD_MSK + +#define TIMER_CHMR2_OUTPUT_CH3PEN_POS 3U +#define TIMER_CHMR2_OUTPUT_CH3PEN_MSK BIT(TIMER_CHMR2_OUTPUT_CH3PEN_POS) +#define TIMER_CHMR2_OUTPUT_CH3PEN TIMER_CHMR2_OUTPUT_CH3PEN_MSK + +#define TIMER_CHMR2_OUTPUT_CH3FEN_POS 2U +#define TIMER_CHMR2_OUTPUT_CH3FEN_MSK BIT(TIMER_CHMR2_OUTPUT_CH3FEN_POS) +#define TIMER_CHMR2_OUTPUT_CH3FEN TIMER_CHMR2_OUTPUT_CH3FEN_MSK + +#define TIMER_CHMR2_OUTPUT_CC3SSEL_POSS 0U +#define TIMER_CHMR2_OUTPUT_CC3SSEL_POSE 1U +#define TIMER_CHMR2_OUTPUT_CC3SSEL_MSK BITS(TIMER_CHMR2_OUTPUT_CC3SSEL_POSS, TIMER_CHMR2_OUTPUT_CC3SSEL_POSE) +#define TIMER_CHMR2_OUTPUT_CC3SSEL TIMER_CHMR2_OUTPUT_CC3SSEL_MSK + +/****************** Bit definition for TIMER_CHMR2_INPUT register ************************/ + +#define TIMER_CHMR2_INPUT_I4FLT_POSS 12U +#define TIMER_CHMR2_INPUT_I4FLT_POSE 15U +#define TIMER_CHMR2_INPUT_I4FLT_MSK BITS(TIMER_CHMR2_INPUT_I4FLT_POSS, TIMER_CHMR2_INPUT_I4FLT_POSE) +#define TIMER_CHMR2_INPUT_I4FLT TIMER_CHMR2_INPUT_I4FLT_MSK + +#define TIMER_CHMR2_INPUT_I4PRES_POSS 10U +#define TIMER_CHMR2_INPUT_I4PRES_POSE 11U +#define TIMER_CHMR2_INPUT_I4PRES_MSK BITS(TIMER_CHMR2_INPUT_I4PRES_POSS, TIMER_CHMR2_INPUT_I4PRES_POSE) +#define TIMER_CHMR2_INPUT_I4PRES TIMER_CHMR2_INPUT_I4PRES_MSK + +#define TIMER_CHMR2_INPUT_CC4SSEL_POSS 8U +#define TIMER_CHMR2_INPUT_CC4SSEL_POSE 9U +#define TIMER_CHMR2_INPUT_CC4SSEL_MSK BITS(TIMER_CHMR2_INPUT_CC4SSEL_POSS, TIMER_CHMR2_INPUT_CC4SSEL_POSE) +#define TIMER_CHMR2_INPUT_CC4SSEL TIMER_CHMR2_INPUT_CC4SSEL_MSK + +#define TIMER_CHMR2_INPUT_I3FLT_POSS 4U +#define TIMER_CHMR2_INPUT_I3FLT_POSE 7U +#define TIMER_CHMR2_INPUT_I3FLT_MSK BITS(TIMER_CHMR2_INPUT_I3FLT_POSS, TIMER_CHMR2_INPUT_I3FLT_POSE) +#define TIMER_CHMR2_INPUT_I3FLT TIMER_CHMR2_INPUT_I3FLT_MSK + +#define TIMER_CHMR2_INPUT_I3PRES_POSS 2U +#define TIMER_CHMR2_INPUT_I3PRES_POSE 3U +#define TIMER_CHMR2_INPUT_I3PRES_MSK BITS(TIMER_CHMR2_INPUT_I3PRES_POSS, TIMER_CHMR2_INPUT_I3PRES_POSE) +#define TIMER_CHMR2_INPUT_I3PRES TIMER_CHMR2_INPUT_I3PRES_MSK + +#define TIMER_CHMR2_INPUT_CC3SSEL_POSS 0U +#define TIMER_CHMR2_INPUT_CC3SSEL_POSE 1U +#define TIMER_CHMR2_INPUT_CC3SSEL_MSK BITS(TIMER_CHMR2_INPUT_CC3SSEL_POSS, TIMER_CHMR2_INPUT_CC3SSEL_POSE) +#define TIMER_CHMR2_INPUT_CC3SSEL TIMER_CHMR2_INPUT_CC3SSEL_MSK + +/****************** Bit definition for TIMER_CCEP register ************************/ + +#define TIMER_CCEP_CC4NPOL_POS 15U +#define TIMER_CCEP_CC4NPOL_MSK BIT(TIMER_CCEP_CC4NPOL_POS) +#define TIMER_CCEP_CC4NPOL TIMER_CCEP_CC4NPOL_MSK + +#define TIMER_CCEP_CC4POL_POS 13U +#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) +#define TIMER_CCEP_CC4POL TIMER_CCEP_CC4POL_MSK + +#define TIMER_CCEP_CC4EN_POS 12U +#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) +#define TIMER_CCEP_CC4EN TIMER_CCEP_CC4EN_MSK + +#define TIMER_CCEP_CC3NPOL_POS 11U +#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) +#define TIMER_CCEP_CC3NPOL TIMER_CCEP_CC3NPOL_MSK + +#define TIMER_CCEP_CC3NEN_POS 10U +#define TIMER_CCEP_CC3NEN_MSK BIT(TIMER_CCEP_CC3NEN_POS) +#define TIMER_CCEP_CC3NEN TIMER_CCEP_CC3NEN_MSK + +#define TIMER_CCEP_CC3POL_POS 9U +#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) +#define TIMER_CCEP_CC3POL TIMER_CCEP_CC3POL_MSK + +#define TIMER_CCEP_CC3EN_POS 8U +#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) +#define TIMER_CCEP_CC3EN TIMER_CCEP_CC3EN_MSK + +#define TIMER_CCEP_CC2NPOL_POS 7U +#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) +#define TIMER_CCEP_CC2NPOL TIMER_CCEP_CC2NPOL_MSK + +#define TIMER_CCEP_CC2NEN_POS 6U +#define TIMER_CCEP_CC2NEN_MSK BIT(TIMER_CCEP_CC2NEN_POS) +#define TIMER_CCEP_CC2NEN TIMER_CCEP_CC2NEN_MSK + +#define TIMER_CCEP_CC2POL_POS 5U +#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) +#define TIMER_CCEP_CC2POL TIMER_CCEP_CC2POL_MSK + +#define TIMER_CCEP_CC2EN_POS 4U +#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) +#define TIMER_CCEP_CC2EN TIMER_CCEP_CC2EN_MSK + +#define TIMER_CCEP_CC1NPOL_POS 3U +#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) +#define TIMER_CCEP_CC1NPOL TIMER_CCEP_CC1NPOL_MSK + +#define TIMER_CCEP_CC1NEN_POS 2U +#define TIMER_CCEP_CC1NEN_MSK BIT(TIMER_CCEP_CC1NEN_POS) +#define TIMER_CCEP_CC1NEN TIMER_CCEP_CC1NEN_MSK + +#define TIMER_CCEP_CC1POL_POS 1U +#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) +#define TIMER_CCEP_CC1POL TIMER_CCEP_CC1POL_MSK + +#define TIMER_CCEP_CC1EN_POS 0U +#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) +#define TIMER_CCEP_CC1EN TIMER_CCEP_CC1EN_MSK + +/****************** Bit definition for TIMER_COUNT register ************************/ + +#define TIMER_COUNT_CNTV_POSS 0U +#define TIMER_COUNT_CNTV_POSE 31U +#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) +#define TIMER_COUNT_CNTV TIMER_COUNT_CNTV_MSK + +/****************** Bit definition for TIMER_PRES register ************************/ + +#define TIMER_PRES_PSCV_POSS 0U +#define TIMER_PRES_PSCV_POSE 15U +#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) +#define TIMER_PRES_PSCV TIMER_PRES_PSCV_MSK + +/****************** Bit definition for TIMER_AR register ************************/ + +#define TIMER_AR_ARV_POSS 0U +#define TIMER_AR_ARV_POSE 31U +#define TIMER_AR_ARV_MSK BITS(TIMER_AR_ARV_POSS, TIMER_AR_ARV_POSE) +#define TIMER_AR_ARV TIMER_AR_ARV_MSK + +/****************** Bit definition for TIMER_REPAR register ************************/ + +#define TIMER_REPAR_REPV_POSS 0U +#define TIMER_REPAR_REPV_POSE 7U +#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS, TIMER_REPAR_REPV_POSE) +#define TIMER_REPAR_REPV TIMER_REPAR_REPV_MSK + +/****************** Bit definition for TIMER_CCVAL1 register ************************/ + +#define TIMER_CCVAL1_CCRV1_POSS 0U +#define TIMER_CCVAL1_CCRV1_POSE 31U +#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS, TIMER_CCVAL1_CCRV1_POSE) +#define TIMER_CCVAL1_CCRV1 TIMER_CCVAL1_CCRV1_MSK + +/****************** Bit definition for TIMER_CCVAL2 register ************************/ + +#define TIMER_CCVAL2_CCRV2_POSS 0U +#define TIMER_CCVAL2_CCRV2_POSE 31U +#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS, TIMER_CCVAL2_CCRV2_POSE) +#define TIMER_CCVAL2_CCRV2 TIMER_CCVAL2_CCRV2_MSK + +/****************** Bit definition for TIMER_CCVAL3 register ************************/ + +#define TIMER_CCVAL3_CCRV3_POSS 0U +#define TIMER_CCVAL3_CCRV3_POSE 31U +#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS, TIMER_CCVAL3_CCRV3_POSE) +#define TIMER_CCVAL3_CCRV3 TIMER_CCVAL3_CCRV3_MSK + +/****************** Bit definition for TIMER_CCVAL4 register ************************/ + +#define TIMER_CCVAL4_CCRV4_POSS 0U +#define TIMER_CCVAL4_CCRV4_POSE 31U +#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS, TIMER_CCVAL4_CCRV4_POSE) +#define TIMER_CCVAL4_CCRV4 TIMER_CCVAL4_CCRV4_MSK + +/****************** Bit definition for TIMER_BDCFG register ************************/ +#define TIMER_BDCFG_GOEN_POS 15U +#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) +#define TIMER_BDCFG_GOEN TIMER_BDCFG_GOEN_MSK + +#define TIMER_BDCFG_AOEN_POS 14U +#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) +#define TIMER_BDCFG_AOEN TIMER_BDCFG_AOEN_MSK + +#define TIMER_BDCFG_BRKP_POS 13U +#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) +#define TIMER_BDCFG_BRKP TIMER_BDCFG_BRKP_MSK + +#define TIMER_BDCFG_BRKEN_POS 12U +#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) +#define TIMER_BDCFG_BRKEN TIMER_BDCFG_BRKEN_MSK + +#define TIMER_BDCFG_OFFSSR_POS 11U +#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) +#define TIMER_BDCFG_OFFSSR TIMER_BDCFG_OFFSSR_MSK + +#define TIMER_BDCFG_OFFSSI_POS 10U +#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) +#define TIMER_BDCFG_OFFSSI TIMER_BDCFG_OFFSSI_MSK + +#define TIMER_BDCFG_LOCKLVL_POSS 8U +#define TIMER_BDCFG_LOCKLVL_POSE 9U +#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS, TIMER_BDCFG_LOCKLVL_POSE) +#define TIMER_BDCFG_LOCKLVL TIMER_BDCFG_LOCKLVL_MSK + +#define TIMER_BDCFG_DT_POSS 0U +#define TIMER_BDCFG_DT_POSE 7U +#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS, TIMER_BDCFG_DT_POSE) +#define TIMER_BDCFG_DT TIMER_BDCFG_DT_MSK + +/****************** Bit definition for TIMER_DMAEN register ************************/ +#define TIMER_DMAEN_TRGI_POS 6U +#define TIMER_DMAEN_TRGI_MSK BIT(TIMER_DMAEN_TRGI_POS) +#define TIMER_DMAEN_TRGI TIMER_DMAEN_TRGI_MSK + +#define TIMER_DMAEN_COM_POS 5U +#define TIMER_DMAEN_COM_MSK BIT(TIMER_DMAEN_COM_POS) +#define TIMER_DMAEN_COM TIMER_DMAEN_COM_MSK + +#define TIMER_DMAEN_CH4_POS 4U +#define TIMER_DMAEN_CH4_MSK BIT(TIMER_DMAEN_CH4_POS) +#define TIMER_DMAEN_CH4 TIMER_DMAEN_CH4_MSK + +#define TIMER_DMAEN_CH3_POS 3U +#define TIMER_DMAEN_CH3_MSK BIT(TIMER_DMAEN_CH3_POS) +#define TIMER_DMAEN_CH3 TIMER_DMAEN_CH3_MSK + +#define TIMER_DMAEN_CH2_POS 2U +#define TIMER_DMAEN_CH2_MSK BIT(TIMER_DMAEN_CH2_POS) +#define TIMER_DMAEN_CH2 TIMER_DMAEN_CH2_MSK + +#define TIMER_DMAEN_CH1_POS 1U +#define TIMER_DMAEN_CH1_MSK BIT(TIMER_DMAEN_CH1_POS) +#define TIMER_DMAEN_CH1 TIMER_DMAEN_CH1_MSK + +#define TIMER_DMAEN_UPD_POS 0U +#define TIMER_DMAEN_UPD_MSK BIT(TIMER_DMAEN_UPD_POS) +#define TIMER_DMAEN_UPD TIMER_DMAEN_UPD_MSK + +/****************** Bit definition for TIMER_OPTR register ************************/ + +#define TIMER_OPTR_ETR_RMP_POSS 8U +#define TIMER_OPTR_ETR_RMP_POSE 9U +#define TIMER_OPTR_ETR_RMP_MSK BITS(TIMER_OPTR_ETR_RMP_POSS, TIMER_OPTR_ETR_RMP_POSE) +#define TIMER_OPTR_ETR_RMP TIMER_OPTR_ETR_RMP_MSK + +#define TIMER_OPTR_CH4_RMP_POSS 6U +#define TIMER_OPTR_CH4_RMP_POSE 7U +#define TIMER_OPTR_CH4_RMP_MSK BITS(TIMER_OPTR_CH4_RMP_POSS, TIMER_OPTR_CH4_RMP_POSE) +#define TIMER_OPTR_CH4_RMP TIMER_OPTR_CH4_RMP_MSK + +#define TIMER_OPTR_CH3_RMP_POSS 4U +#define TIMER_OPTR_CH3_RMP_POSE 5U +#define TIMER_OPTR_CH3_RMP_MSK BITS(TIMER_OPTR_CH3_RMP_POSS, TIMER_OPTR_CH3_RMP_POSE) +#define TIMER_OPTR_CH3_RMP TIMER_OPTR_CH3_RMP_MSK + +#define TIMER_OPTR_CH2_RMP_POSS 2U +#define TIMER_OPTR_CH2_RMP_POSE 3U +#define TIMER_OPTR_CH2_RMP_MSK BITS(TIMER_OPTR_CH2_RMP_POSS, TIMER_OPTR_CH2_RMP_POSE) +#define TIMER_OPTR_CH2_RMP TIMER_OPTR_CH2_RMP_MSK + +#define TIMER_OPTR_CH1_RMP_POSS 0U +#define TIMER_OPTR_CH1_RMP_POSE 1U +#define TIMER_OPTR_CH1_RMP_MSK BITS(TIMER_OPTR_CH1_RMP_POSS, TIMER_OPTR_CH1_RMP_POSE) +#define TIMER_OPTR_CH1_RMP TIMER_OPTR_CH1_RMP_MSK + +typedef struct +{ + __IO uint32_t CON1; // 0x000 + __IO uint32_t CON2; // 0x004 + __IO uint32_t SMCON; // 0x008 + __O uint32_t IER; // 0x00c + __O uint32_t IDR; // 0x010 + __I uint32_t IVS; // 0x014 + __I uint32_t RIF; // 0x018 + __I uint32_t IFM; // 0x01c + __O uint32_t ICR; // 0x020 + __O uint32_t SGE; // 0x024 + __IO uint32_t CHMR1; // 0x028 + __IO uint32_t CHMR2; // 0x02c + __IO uint32_t CCEP; // 0x030 + __IO uint32_t COUNT; // 0x034 + __IO uint32_t PRES; // 0x038 + __IO uint32_t AR; // 0x03c + __IO uint32_t REPAR; // 0x040 + __IO uint32_t CCVAL1; // 0x044 + __IO uint32_t CCVAL2; // 0x048 + __IO uint32_t CCVAL3; // 0x04c + __IO uint32_t CCVAL4; // 0x050 + __IO uint32_t BDCFG; // 0x054 + __IO uint32_t DMAEN; // 0x058 + __IO uint32_t OPTR; // 0x05c +} TIMER_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_uart.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_uart.h new file mode 100644 index 00000000000..d2a6176f8b7 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_uart.h @@ -0,0 +1,697 @@ +/********************************************************************************** + * + * @file reg_uart.h + * @brief UART Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 31 May 2021 AE Team Register rename + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __UART_H__ +#define __UART_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +//#pragma anon_unions + +/****************** Bit definition for UART_RXBUF register ************************/ + +# define UART_RXDATA_RXDATA_POSS 0U +# define UART_RXDATA_RXDATA_POSE 8U +# define UART_RXDATA_RXDATA_MSK BITS(UART_RXDATA_RXDATA_POSS, UART_RXDATA_RXDATA_POSE) +# define UART_RXDATA_RXDATA UART_RXDATA_RXDATA_MSK + +/****************** Bit definition for UART_TXBUF register ************************/ + +# define UART_TXDATA_TXDATA_POSS 0U +# define UART_TXDATA_TXDATA_POSE 8U +# define UART_TXDATA_TXDATA_MSK BITS(UART_TXDATA_TXDATA_POSS, UART_TXDATA_TXDATA_POSE) +# define UART_TXDATA_TXDATA UART_TXDATA_TXDATA_MSK + +/****************** Bit definition for UART_BRR register ************************/ + +# define UART_BRR_BRR_POSS 0U +# define UART_BRR_BRR_POSE 15U +# define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS, UART_BRR_BRR_POSE) +# define UART_BRR_BRR UART_BRR_BRR_MSK + +/****************** Bit definition for UART_LCON register ************************/ + +# define UART_LCON_TXEN_POS 15U +# define UART_LCON_TXEN_MSK BIT(UART_LCON_TXEN_POS) +# define UART_LCON_TXEN UART_LCON_TXEN_MSK + +# define UART_LCON_RXEN_POS 14U +# define UART_LCON_RXEN_MSK BIT(UART_LCON_RXEN_POS) +# define UART_LCON_RXEN UART_LCON_RXEN_MSK + +# define UART_LCON_DBCEN_POS 13U +# define UART_LCON_DBCEN_MSK BIT(UART_LCON_DBCEN_POS) +# define UART_LCON_DBCEN UART_LCON_DBCEN_MSK + +# define UART_LCON_BREAK_POS 10U +# define UART_LCON_BREAK_MSK BIT(UART_LCON_BREAK_POS) +# define UART_LCON_BREAK UART_LCON_BREAK_MSK + +# define UART_LCON_SWAP_POS 9U +# define UART_LCON_SWAP_MSK BIT(UART_LCON_SWAP_POS) +# define UART_LCON_SWAP UART_LCON_SWAP_MSK + +# define UART_LCON_TXINV_POS 8U +# define UART_LCON_TXINV_MSK BIT(UART_LCON_TXINV_POS) +# define UART_LCON_TXINV UART_LCON_TXINV_MSK + +# define UART_LCON_RXINV_POS 7U +# define UART_LCON_RXINV_MSK BIT(UART_LCON_RXINV_POS) +# define UART_LCON_RXINV UART_LCON_RXINV_MSK + +# define UART_LCON_DATAINV_POS 6U +# define UART_LCON_DATAINV_MSK BIT(UART_LCON_DATAINV_POS) +# define UART_LCON_DATAINV UART_LCON_DATAINV_MSK + +# define UART_LCON_MSB_POS 5U +# define UART_LCON_MSB_MSK BIT(UART_LCON_MSB_POS) +# define UART_LCON_MSB UART_LCON_MSB_MSK + +# define UART_LCON_PS_POS 4U +# define UART_LCON_PS_MSK BIT(UART_LCON_PS_POS) +# define UART_LCON_PS UART_LCON_PS_MSK + +# define UART_LCON_PE_POS 3U +# define UART_LCON_PE_MSK BIT(UART_LCON_PE_POS) +# define UART_LCON_PE UART_LCON_PE_MSK + +# define UART_LCON_STOP_POS 2U +# define UART_LCON_STOP_MSK BIT(UART_LCON_STOP_POS) +# define UART_LCON_STOP UART_LCON_STOP_MSK + +# define UART_LCON_DLS_POSS 0U +# define UART_LCON_DLS_POSE 1U +# define UART_LCON_DLS_MSK BITS(UART_LCON_DLS_POSS, UART_LCON_DLS_POSE) +# define UART_LCON_DLS UART_LCON_DLS_MSK + +/****************** Bit definition for UART_MCON register ************************/ + +# define UART_MCON_TXFLOAT_POS 16U +# define UART_MCON_TXFLOAT_MSK BIT(UART_MCON_TXFLOAT_POS) +# define UART_MCON_TXFLOAT UART_MCON_TXFLOAT_MSK + +# define UART_MCON_TXDMAEN_POS 15U +# define UART_MCON_TXDMAEN_MSK BIT(UART_MCON_TXDMAEN_POS) +# define UART_MCON_TXDMAEN UART_MCON_TXDMAEN_MSK + +# define UART_MCON_RXDMAEN_POS 14U +# define UART_MCON_RXDMAEN_MSK BIT(UART_MCON_RXDMAEN_POS) +# define UART_MCON_RXDMAEN UART_MCON_RXDMAEN_MSK + +# define UART_MCON_ABRREPT_POS 11U +# define UART_MCON_ABRREPT_MSK BIT(UART_MCON_ABRREPT_POS) +# define UART_MCON_ABRREPT UART_MCON_ABRREPT_MSK + +# define UART_MCON_ABRMOD_POSS 9U +# define UART_MCON_ABRMOD_POSE 10U +# define UART_MCON_ABRMOD_MSK BITS(UART_MCON_ABRMOD_POSS, UART_MCON_ABRMOD_POSE) +# define UART_MCON_ABRMOD UART_MCON_ABRMOD_MSK + +# define UART_MCON_ABREN_POS 8U +# define UART_MCON_ABREN_MSK BIT(UART_MCON_ABREN_POS) +# define UART_MCON_ABREN UART_MCON_ABREN_MSK + +# define UART_MCON_BKREQ_POS 5U +# define UART_MCON_BKREQ_MSK BIT(UART_MCON_BKREQ_POS) +# define UART_MCON_BKREQ UART_MCON_BKREQ_MSK + +# define UART_MCON_HDEN_POS 4U +# define UART_MCON_HDEN_MSK BIT(UART_MCON_HDEN_POS) +# define UART_MCON_HDEN UART_MCON_HDEN_MSK + +# define UART_MCON_IREN_POS 3U +# define UART_MCON_IREN_MSK BIT(UART_MCON_IREN_POS) +# define UART_MCON_IREN UART_MCON_IREN_MSK + +# define UART_MCON_AFCEN_POS 2U +# define UART_MCON_AFCEN_MSK BIT(UART_MCON_AFCEN_POS) +# define UART_MCON_AFCEN UART_MCON_AFCEN_MSK + +# define UART_MCON_RTSSET_POS 1U +# define UART_MCON_RTSSET_MSK BIT(UART_MCON_RTSSET_POS) +# define UART_MCON_RTSSET UART_MCON_RTSSET_MSK + +# define UART_MCON_LPBKEN_POS 0U +# define UART_MCON_LPBKEN_MSK BIT(UART_MCON_LPBKEN_POS) +# define UART_MCON_LPBKEN UART_MCON_LPBKEN_MSK + +/****************** Bit definition for UART_RS485 register ************************/ + +# define UART_RS485_DLY_POSS 16U +# define UART_RS485_DLY_POSE 23U +# define UART_RS485_DLY_MSK BITS(UART_RS485_DLY_POSS, UART_RS485_DLY_POSE) +# define UART_RS485_DLY UART_RS485_DLY_MSK + +# define UART_RS485_ADDR_POSS 8U +# define UART_RS485_ADDR_POSE 15U +# define UART_RS485_ADDR_MSK BITS(UART_RS485_ADDR_POSS, UART_RS485_ADDR_POSE) +# define UART_RS485_ADDR UART_RS485_ADDR_MSK + +# define UART_RS485_AADINV_POS 3U +# define UART_RS485_AADINV_MSK BIT(UART_RS485_AADINV_POS) +# define UART_RS485_AADINV UART_RS485_AADINV_MSK + +# define UART_RS485_AADACEN_POS 2U +# define UART_RS485_AADACEN_MSK BIT(UART_RS485_AADACEN_POS) +# define UART_RS485_AADACEN UART_RS485_AADACEN_MSK + +# define UART_RS485_AADNEN_POS 1U +# define UART_RS485_AADNEN_MSK BIT(UART_RS485_AADNEN_POS) +# define UART_RS485_AADNEN UART_RS485_AADNEN_MSK + +# define UART_RS485_AADEN_POS 0U +# define UART_RS485_AADEN_MSK BIT(UART_RS485_AADEN_POS) +# define UART_RS485_AADEN UART_RS485_AADEN_MSK + +/****************** Bit definition for UART_SCARD register ************************/ + +# define UART_SCARD_BLEN_POSS 24U +# define UART_SCARD_BLEN_POSE 31U +# define UART_SCARD_BLEN_MSK BITS(UART_SCARD_BLEN_POSS, UART_SCARD_BLEN_POSE) +# define UART_SCARD_BLEN UART_SCARD_BLEN_MSK + +# define UART_SCARD_GT_POSS 16U +# define UART_SCARD_GT_POSE 23U +# define UART_SCARD_GT_MSK BITS(UART_SCARD_GT_POSS, UART_SCARD_GT_POSE) +# define UART_SCARD_GT UART_SCARD_GT_MSK + +# define UART_SCARD_PSC_POSS 8U +# define UART_SCARD_PSC_POSE 15U +# define UART_SCARD_PSC_MSK BITS(UART_SCARD_PSC_POSS, UART_SCARD_PSC_POSE) +# define UART_SCARD_PSC UART_SCARD_PSC_MSK + +# define UART_SCARD_SCCNT_POSS 3U +# define UART_SCARD_SCCNT_POSE 5U +# define UART_SCARD_SCCNT_MSK BITS(UART_SCARD_SCCNT_POSS, UART_SCARD_SCCNT_POSE) +# define UART_SCARD_SCCNT UART_SCARD_SCCNT_MSK + +# define UART_SCARD_SCLKEN_POS 2U +# define UART_SCARD_SCLKEN_MSK BIT(UART_SCARD_SCLKEN_POS) +# define UART_SCARD_SCLKEN UART_SCARD_SCLKEN_MSK + +# define UART_SCARD_SCNACK_POS 1U +# define UART_SCARD_SCNACK_MSK BIT(UART_SCARD_SCNACK_POS) +# define UART_SCARD_SCNACK UART_SCARD_SCNACK_MSK + +# define UART_SCARD_SCEN_POS 0U +# define UART_SCARD_SCEN_MSK BIT(UART_SCARD_SCEN_POS) +# define UART_SCARD_SCEN UART_SCARD_SCEN_MSK + +/****************** Bit definition for UART_LIN register ************************/ + +# define UART_LIN_LINBKREQ_POS 2U +# define UART_LIN_LINBKREQ_MSK BIT(UART_LIN_LINBKREQ_POS) +# define UART_LIN_LINBKREQ UART_LIN_LINBKREQ_MSK + +# define UART_LIN_LINBDL_POS 1U +# define UART_LIN_LINBDL_MSK BIT(UART_LIN_LINBDL_POS) +# define UART_LIN_LINBDL UART_LIN_LINBDL_MSK + +# define UART_LIN_LINEN_POS 0U +# define UART_LIN_LINEN_MSK BIT(UART_LIN_LINEN_POS) +# define UART_LIN_LINEN UART_LIN_LINEN_MSK + +/****************** Bit definition for UART_RTOR register ************************/ + +# define UART_RTOR_RTOEN_POS 24U +# define UART_RTOR_RTOEN_MSK BIT(UART_RTOR_RTOEN_POS) +# define UART_RTOR_RTOEN UART_RTOR_RTOEN_MSK + +# define UART_RTOR_RTO_POSS 0U +# define UART_RTOR_RTO_POSE 23U +# define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS, UART_RTOR_RTO_POSE) +# define UART_RTOR_RTO UART_RTOR_RTO_MSK + +/****************** Bit definition for UART_STAT register ************************/ + +# define UART_STAT_TFOERR_POS 18U +# define UART_STAT_TFOERR_MSK BIT(UART_STAT_TFOERR_POS) +# define UART_STAT_TFOERR UART_STAT_TFOERR_MSK + +# define UART_STAT_TFEMPTY_POS 16U +# define UART_STAT_TFEMPTY_MSK BIT(UART_STAT_TFEMPTY_POS) +# define UART_STAT_TFEMPTY UART_STAT_TFEMPTY_MSK + +# define UART_STAT_TSBUSY_POS 14U +# define UART_STAT_TSBUSY_MSK BIT(UART_STAT_TSBUSY_POS) +# define UART_STAT_TSBUSY UART_STAT_TSBUSY_MSK + +# define UART_STAT_RFUERR_POS 13U +# define UART_STAT_RFUERR_MSK BIT(UART_STAT_RFUERR_POS) +# define UART_STAT_RFUERR UART_STAT_RFUERR_MSK + +# define UART_STAT_RFOERR_POS 12U +# define UART_STAT_RFOERR_MSK BIT(UART_STAT_RFOERR_POS) +# define UART_STAT_RFOERR UART_STAT_RFOERR_MSK + +# define UART_STAT_RFNEMPTY_POS 10U +# define UART_STAT_RFNEMPTY_MSK BIT(UART_STAT_RFNEMPTY_POS) +# define UART_STAT_RFNEMPTY UART_STAT_RFNEMPTY_MSK + +# define UART_STAT_RSBUSY_POS 8U +# define UART_STAT_RSBUSY_MSK BIT(UART_STAT_RSBUSY_POS) +# define UART_STAT_RSBUSY UART_STAT_RSBUSY_MSK + +# define UART_STAT_CTSSTA_POS 3U +# define UART_STAT_CTSSTA_MSK BIT(UART_STAT_CTSSTA_POS) +# define UART_STAT_CTSSTA UART_STAT_CTSSTA_MSK + +# define UART_STAT_BKERR_POS 2U +# define UART_STAT_BKERR_MSK BIT(UART_STAT_BKERR_POS) +# define UART_STAT_BKERR UART_STAT_BKERR_MSK + +# define UART_STAT_FERR_POS 1U +# define UART_STAT_FERR_MSK BIT(UART_STAT_FERR_POS) +# define UART_STAT_FERR UART_STAT_FERR_MSK + +# define UART_STAT_PERR_POS 0U +# define UART_STAT_PERR_MSK BIT(UART_STAT_PERR_POS) +# define UART_STAT_PERR UART_STAT_PERR_MSK + +/****************** Bit definition for UART_IER register ************************/ + +# define UART_IER_TFOERR_POS 18U +# define UART_IER_TFOERR_MSK BIT(UART_IER_TFOERR_POS) +# define UART_IER_TFOERR UART_IER_TFOERR_MSK + +# define UART_IER_TFEMPTY_POS 16U +# define UART_IER_TFEMPTY_MSK BIT(UART_IER_TFEMPTY_POS) +# define UART_IER_TFEMPTY UART_IER_TFEMPTY_MSK + +# define UART_IER_TBC_POS 14U +# define UART_IER_TBC_MSK BIT(UART_IER_TBC_POS) +# define UART_IER_TBC UART_IER_TBC_MSK + +# define UART_IER_RFUERR_POS 13U +# define UART_IER_RFUERR_MSK BIT(UART_IER_RFUERR_POS) +# define UART_IER_RFUERR UART_IER_RFUERR_MSK + +# define UART_IER_RFOERR_POS 12U +# define UART_IER_RFOERR_MSK BIT(UART_IER_RFOERR_POS) +# define UART_IER_RFOERR UART_IER_RFOERR_MSK + +# define UART_IER_RFNEMPTY_POS 10U +# define UART_IER_RFNEMPTY_MSK BIT(UART_IER_RFNEMPTY_POS) +# define UART_IER_RFNEMPTY UART_IER_RFNEMPTY_MSK + +# define UART_IER_NOISE_POS 8U +# define UART_IER_NOISE_MSK BIT(UART_IER_NOISE_POS) +# define UART_IER_NOISE UART_IER_NOISE_MSK + +# define UART_IER_EOB_POS 7U +# define UART_IER_EOB_MSK BIT(UART_IER_EOB_POS) +# define UART_IER_EOB UART_IER_EOB_MSK + +# define UART_IER_LINBK_POS 6U +# define UART_IER_LINBK_MSK BIT(UART_IER_LINBK_POS) +# define UART_IER_LINBK UART_IER_LINBK_MSK + +# define UART_IER_ADDRM_POS 5U +# define UART_IER_ADDRM_MSK BIT(UART_IER_ADDRM_POS) +# define UART_IER_ADDRM UART_IER_ADDRM_MSK + +# define UART_IER_RXTO_POS 4U +# define UART_IER_RXTO_MSK BIT(UART_IER_RXTO_POS) +# define UART_IER_RXTO UART_IER_RXTO_MSK + +# define UART_IER_DCTS_POS 3U +# define UART_IER_DCTS_MSK BIT(UART_IER_DCTS_POS) +# define UART_IER_DCTS UART_IER_DCTS_MSK + +# define UART_IER_ABTO_POS 2U +# define UART_IER_ABTO_MSK BIT(UART_IER_ABTO_POS) +# define UART_IER_ABTO UART_IER_ABTO_MSK + +# define UART_IER_ABEND_POS 1U +# define UART_IER_ABEND_MSK BIT(UART_IER_ABEND_POS) +# define UART_IER_ABEND UART_IER_ABEND_MSK + +# define UART_IER_RXBERR_POS 0U +# define UART_IER_RXBERR_MSK BIT(UART_IER_RXBERR_POS) +# define UART_IER_RXBERR UART_IER_RXBERR_MSK + +/****************** Bit definition for UART_IDR register ************************/ + +# define UART_IDR_TFOERR_POS 18U +# define UART_IDR_TFOERR_MSK BIT(UART_IDR_TFOERR_POS) +# define UART_IDR_TFOERR UART_IDR_TFOERR_MSK + +# define UART_IDR_TFEMPTY_POS 16U +# define UART_IDR_TFEMPTY_MSK BIT(UART_IDR_TFEMPTY_POS) +# define UART_IDR_TFEMPTY UART_IDR_TFEMPTY_MSK + +# define UART_IDR_TBC_POS 14U +# define UART_IDR_TBC_MSK BIT(UART_IDR_TBC_POS) +# define UART_IDR_TBC UART_IDR_TBC_MSK + +# define UART_IDR_RFUERR_POS 13U +# define UART_IDR_RFUERR_MSK BIT(UART_IDR_RFUERR_POS) +# define UART_IDR_RFUERR UART_IDR_RFUERR_MSK + +# define UART_IDR_RFOERR_POS 12U +# define UART_IDR_RFOERR_MSK BIT(UART_IDR_RFOERR_POS) +# define UART_IDR_RFOERR UART_IDR_RFOERR_MSK + +# define UART_IDR_RFNEMPTY_POS 10U +# define UART_IDR_RFNEMPTY_MSK BIT(UART_IDR_RFNEMPTY_POS) +# define UART_IDR_RFNEMPTY UART_IDR_RFNEMPTY_MSK + +# define UART_IDR_NOISE_POS 8U +# define UART_IDR_NOISE_MSK BIT(UART_IDR_NOISE_POS) +# define UART_IDR_NOISE UART_IDR_NOISE_MSK + +# define UART_IDR_EOB_POS 7U +# define UART_IDR_EOB_MSK BIT(UART_IDR_EOB_POS) +# define UART_IDR_EOB UART_IDR_EOB_MSK + +# define UART_IDR_LINBK_POS 6U +# define UART_IDR_LINBK_MSK BIT(UART_IDR_LINBK_POS) +# define UART_IDR_LINBK UART_IDR_LINBK_MSK + +# define UART_IDR_ADDRM_POS 5U +# define UART_IDR_ADDRM_MSK BIT(UART_IDR_ADDRM_POS) +# define UART_IDR_ADDRM UART_IDR_ADDRM_MSK + +# define UART_IDR_RXTO_POS 4U +# define UART_IDR_RXTO_MSK BIT(UART_IDR_RXTO_POS) +# define UART_IDR_RXTO UART_IDR_RXTO_MSK + +# define UART_IDR_DCTS_POS 3U +# define UART_IDR_DCTS_MSK BIT(UART_IDR_DCTS_POS) +# define UART_IDR_DCTS UART_IDR_DCTS_MSK + +# define UART_IDR_ABTO_POS 2U +# define UART_IDR_ABTO_MSK BIT(UART_IDR_ABTO_POS) +# define UART_IDR_ABTO UART_IDR_ABTO_MSK + +# define UART_IDR_ABEND_POS 1U +# define UART_IDR_ABEND_MSK BIT(UART_IDR_ABEND_POS) +# define UART_IDR_ABEND UART_IDR_ABEND_MSK + +# define UART_IDR_RXBERR_POS 0U +# define UART_IDR_RXBERR_MSK BIT(UART_IDR_RXBERR_POS) +# define UART_IDR_RXBERR UART_IDR_RXBERR_MSK + +/****************** Bit definition for UART_IVS register ************************/ + +# define UART_IVS_TFOERR_POS 18U +# define UART_IVS_TFOERR_MSK BIT(UART_IVS_TFOERR_POS) +# define UART_IVS_TFOERR UART_IVS_TFOERR_MSK + +# define UART_IVS_TFEMPTY_POS 16U +# define UART_IVS_TFEMPTY_MSK BIT(UART_IVS_TFEMPTY_POS) +# define UART_IVS_TFEMPTY UART_IVS_TFEMPTY_MSK + +# define UART_IVS_TBC_POS 14U +# define UART_IVS_TBC_MSK BIT(UART_IVS_TBC_POS) +# define UART_IVS_TBC UART_IVS_TBC_MSK + +# define UART_IVS_RFUERR_POS 13U +# define UART_IVS_RFUERR_MSK BIT(UART_IVS_RFUERR_POS) +# define UART_IVS_RFUERR UART_IVS_RFUERR_MSK + +# define UART_IVS_RFOERR_POS 12U +# define UART_IVS_RFOERR_MSK BIT(UART_IVS_RFOERR_POS) +# define UART_IVS_RFOERR UART_IVS_RFOERR_MSK + +# define UART_IVS_RFNEMPTY_POS 10U +# define UART_IVS_RFNEMPTY_MSK BIT(UART_IVS_RFNEMPTY_POS) +# define UART_IVS_RFNEMPTY UART_IVS_RFNEMPTY_MSK + +# define UART_IVS_NOISE_POS 8U +# define UART_IVS_NOISE_MSK BIT(UART_IVS_NOISE_POS) +# define UART_IVS_NOISE UART_IVS_NOISE_MSK + +# define UART_IVS_EOB_POS 7U +# define UART_IVS_EOB_MSK BIT(UART_IVS_EOB_POS) +# define UART_IVS_EOB UART_IVS_EOB_MSK + +# define UART_IVS_LINBK_POS 6U +# define UART_IVS_LINBK_MSK BIT(UART_IVS_LINBK_POS) +# define UART_IVS_LINBK UART_IVS_LINBK_MSK + +# define UART_IVS_ADDRM_POS 5U +# define UART_IVS_ADDRM_MSK BIT(UART_IVS_ADDRM_POS) +# define UART_IVS_ADDRM UART_IVS_ADDRM_MSK + +# define UART_IVS_RXTO_POS 4U +# define UART_IVS_RXTO_MSK BIT(UART_IVS_RXTO_POS) +# define UART_IVS_RXTO UART_IVS_RXTO_MSK + +# define UART_IVS_DCTS_POS 3U +# define UART_IVS_DCTS_MSK BIT(UART_IVS_DCTS_POS) +# define UART_IVS_DCTS UART_IVS_DCTS_MSK + +# define UART_IVS_ABTO_POS 2U +# define UART_IVS_ABTO_MSK BIT(UART_IVS_ABTO_POS) +# define UART_IVS_ABTO UART_IVS_ABTO_MSK + +# define UART_IVS_ABEND_POS 1U +# define UART_IVS_ABEND_MSK BIT(UART_IVS_ABEND_POS) +# define UART_IVS_ABEND UART_IVS_ABEND_MSK + +# define UART_IVS_RXBERR_POS 0U +# define UART_IVS_RXBERR_MSK BIT(UART_IVS_RXBERR_POS) +# define UART_IVS_RXBERR UART_IVS_RXBERR_MSK + +/****************** Bit definition for UART_RIF register ************************/ + +# define UART_RIF_TFOERR_POS 18U +# define UART_RIF_TFOERR_MSK BIT(UART_RIF_TFOERR_POS) +# define UART_RIF_TFOERR UART_RIF_TFOERR_MSK + +# define UART_RIF_TFEMPTY_POS 16U +# define UART_RIF_TFEMPTY_MSK BIT(UART_RIF_TFEMPTY_POS) +# define UART_RIF_TFEMPTY UART_RIF_TFEMPTY_MSK + +# define UART_RIF_TBC_POS 14U +# define UART_RIF_TBC_MSK BIT(UART_RIF_TBC_POS) +# define UART_RIF_TBC UART_RIF_TBC_MSK + +# define UART_RIF_RFUERR_POS 13U +# define UART_RIF_RFUERR_MSK BIT(UART_RIF_RFUERR_POS) +# define UART_RIF_RFUERR UART_RIF_RFUERR_MSK + +# define UART_RIF_RFOERR_POS 12U +# define UART_RIF_RFOERR_MSK BIT(UART_RIF_RFOERR_POS) +# define UART_RIF_RFOERR UART_RIF_RFOERR_MSK + +# define UART_RIF_RFNEMPTY_POS 10U +# define UART_RIF_RFNEMPTY_MSK BIT(UART_RIF_RFNEMPTY_POS) +# define UART_RIF_RFNEMPTY UART_RIF_RFNEMPTY_MSK + +# define UART_RIF_NOISE_POS 8U +# define UART_RIF_NOISE_MSK BIT(UART_RIF_NOISE_POS) +# define UART_RIF_NOISE UART_RIF_NOISE_MSK + +# define UART_RIF_EOB_POS 7U +# define UART_RIF_EOB_MSK BIT(UART_RIF_EOB_POS) +# define UART_RIF_EOB UART_RIF_EOB_MSK + +# define UART_RIF_LINBK_POS 6U +# define UART_RIF_LINBK_MSK BIT(UART_RIF_LINBK_POS) +# define UART_RIF_LINBK UART_RIF_LINBK_MSK + +# define UART_RIF_ADDRM_POS 5U +# define UART_RIF_ADDRM_MSK BIT(UART_RIF_ADDRM_POS) +# define UART_RIF_ADDRM UART_RIF_ADDRM_MSK + +# define UART_RIF_RXTO_POS 4U +# define UART_RIF_RXTO_MSK BIT(UART_RIF_RXTO_POS) +# define UART_RIF_RXTO UART_RIF_RXTO_MSK + +# define UART_RIF_DCTS_POS 3U +# define UART_RIF_DCTS_MSK BIT(UART_RIF_DCTS_POS) +# define UART_RIF_DCTS UART_RIF_DCTS_MSK + +# define UART_RIF_ABTO_POS 2U +# define UART_RIF_ABTO_MSK BIT(UART_RIF_ABTO_POS) +# define UART_RIF_ABTO UART_RIF_ABTO_MSK + +# define UART_RIF_ABEND_POS 1U +# define UART_RIF_ABEND_MSK BIT(UART_RIF_ABEND_POS) +# define UART_RIF_ABEND UART_RIF_ABEND_MSK + +# define UART_RIF_RXBERR_POS 0U +# define UART_RIF_RXBERR_MSK BIT(UART_RIF_RXBERR_POS) +# define UART_RIF_RXBERR UART_RIF_RXBERR_MSK +/****************** Bit definition for UART_IFM register ************************/ + +# define UART_IFM_TFOERR_POS 18U +# define UART_IFM_TFOERR_MSK BIT(UART_IFM_TFOERR_POS) +# define UART_IFM_TFOERR UART_IFM_TFOERR_MSK + +# define UART_IFM_TFEMPTY_POS 16U +# define UART_IFM_TFEMPTY_MSK BIT(UART_IFM_TFEMPTY_POS) +# define UART_IFM_TFEMPTY UART_IFM_TFEMPTY_MSK + +# define UART_IFM_TBC_POS 14U +# define UART_IFM_TBC_MSK BIT(UART_IFM_TBC_POS) +# define UART_IFM_TBC UART_IFM_TBC_MSK + +# define UART_IFM_RFUERR_POS 13U +# define UART_IFM_RFUERR_MSK BIT(UART_IFM_RFUERR_POS) +# define UART_IFM_RFUERR UART_IFM_RFUERR_MSK + +# define UART_IFM_RFOERR_POS 12U +# define UART_IFM_RFOERR_MSK BIT(UART_IFM_RFOERR_POS) +# define UART_IFM_RFOERR UART_IFM_RFOERR_MSK + +# define UART_IFM_RFNEMPTY_POS 10U +# define UART_IFM_RFNEMPTY_MSK BIT(UART_IFM_RFNEMPTY_POS) +# define UART_IFM_RFNEMPTY UART_IFM_RFNEMPTY_MSK + +# define UART_IFM_NOISE_POS 8U +# define UART_IFM_NOISE_MSK BIT(UART_IFM_NOISE_POS) +# define UART_IFM_NOISE UART_IFM_NOISE_MSK + +# define UART_IFM_EOB_POS 7U +# define UART_IFM_EOB_MSK BIT(UART_IFM_EOB_POS) +# define UART_IFM_EOB UART_IFM_EOB_MSK + +# define UART_IFM_LINBK_POS 6U +# define UART_IFM_LINBK_MSK BIT(UART_IFM_LINBK_POS) +# define UART_IFM_LINBK UART_IFM_LINBK_MSK + +# define UART_IFM_ADDRM_POS 5U +# define UART_IFM_ADDRM_MSK BIT(UART_IFM_ADDRM_POS) +# define UART_IFM_ADDRM UART_IFM_ADDRM_MSK + +# define UART_IFM_RXTO_POS 4U +# define UART_IFM_RXTO_MSK BIT(UART_IFM_RXTO_POS) +# define UART_IFM_RXTO UART_IFM_RXTO_MSK + +# define UART_IFM_DCTS_POS 3U +# define UART_IFM_DCTS_MSK BIT(UART_IFM_DCTS_POS) +# define UART_IFM_DCTS UART_IFM_DCTS_MSK + +# define UART_IFM_ABTO_POS 2U +# define UART_IFM_ABTO_MSK BIT(UART_IFM_ABTO_POS) +# define UART_IFM_ABTO UART_IFM_ABTO_MSK + +# define UART_IFM_ABEND_POS 1U +# define UART_IFM_ABEND_MSK BIT(UART_IFM_ABEND_POS) +# define UART_IFM_ABEND UART_IFM_ABEND_MSK + +# define UART_IFM_RXBERR_POS 0U +# define UART_IFM_RXBERR_MSK BIT(UART_IFM_RXBERR_POS) +# define UART_IFM_RXBERR UART_IFM_RXBERR_MSK + +/****************** Bit definition for UART_ICR register ************************/ + +# define UART_ICR_TFOERR_POS 18U +# define UART_ICR_TFOERR_MSK BIT(UART_ICR_TFOERR_POS) +# define UART_ICR_TFOERR UART_ICR_TFOERR_MSK + +# define UART_ICR_TFEMPTY_POS 16U +# define UART_ICR_TFEMPTY_MSK BIT(UART_ICR_TFEMPTY_POS) +# define UART_ICR_TFEMPTY UART_ICR_TFEMPTY_MSK + +# define UART_ICR_TBC_POS 14U +# define UART_ICR_TBC_MSK BIT(UART_ICR_TBC_POS) +# define UART_ICR_TBC UART_ICR_TBC_MSK + +# define UART_ICR_RFUERR_POS 13U +# define UART_ICR_RFUERR_MSK BIT(UART_ICR_RFUERR_POS) +# define UART_ICR_RFUERR UART_ICR_RFUERR_MSK + +# define UART_ICR_RFOERR_POS 12U +# define UART_ICR_RFOERR_MSK BIT(UART_ICR_RFOERR_POS) +# define UART_ICR_RFOERR UART_ICR_RFOERR_MSK + +# define UART_ICR_RFNEMPTY_POS 10U +# define UART_ICR_RFNEMPTY_MSK BIT(UART_ICR_RFNEMPTY_POS) +# define UART_ICR_RFNEMPTY UART_ICR_RFNEMPTY_MSK + +# define UART_ICR_NOISE_POS 8U +# define UART_ICR_NOISE_MSK BIT(UART_ICR_NOISE_POS) +# define UART_ICR_NOISE UART_ICR_NOISE_MSK + +# define UART_ICR_EOB_POS 7U +# define UART_ICR_EOB_MSK BIT(UART_ICR_EOB_POS) +# define UART_ICR_EOB UART_ICR_EOB_MSK + +# define UART_ICR_LINBK_POS 6U +# define UART_ICR_LINBK_MSK BIT(UART_ICR_LINBK_POS) +# define UART_ICR_LINBK UART_ICR_LINBK_MSK + +# define UART_ICR_ADDRM_POS 5U +# define UART_ICR_ADDRM_MSK BIT(UART_ICR_ADDRM_POS) +# define UART_ICR_ADDRM UART_ICR_ADDRM_MSK + +# define UART_ICR_RXTO_POS 4U +# define UART_ICR_RXTO_MSK BIT(UART_ICR_RXTO_POS) +# define UART_ICR_RXTO UART_ICR_RXTO_MSK + +# define UART_ICR_DCTS_POS 3U +# define UART_ICR_DCTS_MSK BIT(UART_ICR_DCTS_POS) +# define UART_ICR_DCTS UART_ICR_DCTS_MSK + +# define UART_ICR_ABTO_POS 2U +# define UART_ICR_ABTO_MSK BIT(UART_ICR_ABTO_POS) +# define UART_ICR_ABTO UART_ICR_ABTO_MSK + +# define UART_ICR_ABEND_POS 1U +# define UART_ICR_ABEND_MSK BIT(UART_ICR_ABEND_POS) +# define UART_ICR_ABEND UART_ICR_ABEND_MSK + +# define UART_ICR_RXBERR_POS 0U +# define UART_ICR_RXBERR_MSK BIT(UART_ICR_RXBERR_POS) +# define UART_ICR_RXBERR UART_ICR_RXBERR_MSK + +typedef struct +{ + __I uint32_t RXDATA; // 0x000 + __IO uint32_t TXDATA; // 0x004 + __IO uint32_t BRR; // 0x008 + __IO uint32_t LCON; // 0x00c + __IO uint32_t MCON; // 0x010 + __IO uint32_t RS485; // 0x014 + __IO uint32_t SCARD; // 0x018 + __IO uint32_t LIN; // 0x01c + __IO uint32_t RTOR; // 0x020 + __IO uint32_t RESERVED0; // 0x024 + __I uint32_t STAT; // 0x028 + __O uint32_t IER; // 0x02c + __O uint32_t IDR; // 0x030 + __I uint32_t IVS; // 0x034 + __I uint32_t RIF; // 0x038 + __I uint32_t IFM; // 0x03c + __O uint32_t ICR; // 0x040 +} UART_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_usb.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_usb.h new file mode 100644 index 00000000000..8f7baa3740a --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_usb.h @@ -0,0 +1,1211 @@ +/********************************************************************************** + * + * @file reg_usb.h + * @brief USB Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_USB_H__ +#define __REG_USB_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* //#pragma anon_unions */ + +/****************** Bit definition for USB_FADDR register ************************/ + +#define USB_FADDR_ADDR_POSS 0U +#define USB_FADDR_ADDR_POSE 6U +#define USB_FADDR_ADDR_MSK BITS(USB_FADDR_ADDR_POSS,USB_FADDR_ADDR_POSE) +#define USB_FADDR_ADDR USB_FADDR_ADDR_MSK + +/****************** Bit definition for USB_POWER register ************************/ + +/* device/host mode */ +#define USB_POWER_ISOUDT_POS 7U +#define USB_POWER_ISOUDT_MSK BIT(USB_POWER_ISOUDT_POS) +#define USB_POWER_ISOUDT USB_POWER_ISOUDT_MSK + +/* device mode */ +#define USB_POWER_RESET_POS 3U +#define USB_POWER_RESET_MSK BIT(USB_POWER_RESET_POS) +#define USB_POWER_RESET USB_POWER_RESET_MSK + +#define USB_POWER_RESUME_POS 2U +#define USB_POWER_RESUME_MSK BIT(USB_POWER_RESUME_POS) +#define USB_POWER_RESUME USB_POWER_RESUME_MSK + +#define USB_POWER_SUSPEND_POS 1U +#define USB_POWER_SUSPEND_MSK BIT(USB_POWER_SUSPEND_POS) +#define USB_POWER_SUSPEND USB_POWER_SUSPEND_MSK + +/* device mode */ +#define USB_POWER_SUSPENDEN_POS 0U +#define USB_POWER_SUSPENDEN_MSK BIT(USB_POWER_SUSPENDEN_POS) +#define USB_POWER_SUSPENDEN USB_POWER_SUSPENDEN_MSK + +/****************** Bit definition for USB_DPDMCON register ************************/ + +#define USB_DPDMCON_DPPUD_POSS 3U +#define USB_DPDMCON_DPPUD_POSE 4U +#define USB_DPDMCON_DPPUD_MSK BITS(USB_DPDMCON_DPPUD_POSS,USB_DPDMCON_DPPUD_POSE) +#define USB_DPDMCON_DPPUD USB_DPDMCON_DPPUD_MSK + +#define USB_DPDMCON_DMPUD_POSS 1U +#define USB_DPDMCON_DMPUD_POSE 2U +#define USB_DPDMCON_DMPUD_MSK BITS(USB_DPDMCON_DMPUD_POSS,USB_DPDMCON_DMPUD_POSE) +#define USB_DPDMCON_DMPUD USB_DPDMCON_DMPUD_MSK + +#define USB_DPDMCON_PHYPWREN_POS 0U +#define USB_DPDMCON_PHYPWREN_MSK BIT(USB_DPDMCON_PHYPWREN_POS) +#define USB_DPDMCON_PHYPWREN USB_DPDMCON_PHYPWREN_MSK + +/****************** Bit definition for USB_SWCID register ************************/ + +#define USB_SWCID_HOST_POS 1U +#define USB_SWCID_HOST_MSK BIT(USB_SWCID_HOST_POS) +#define USB_SWCID_HOST USB_SWCID_HOST_MSK + +#define USB_SWCID_CIDCTRL_POS 0U +#define USB_SWCID_CIDCTRL_MSK BIT(USB_SWCID_CIDCTRL_POS) +#define USB_SWCID_CIDCTRL USB_SWCID_CIDCTRL_MSK + +/****************** Bit definition for USB_SWVBUS register ************************/ + +#define USB_SWVBUS_VALTH_POS 3U +#define USB_SWVBUS_VALTH_MSK BIT(USB_SWVBUS_VALTH_POS) +#define USB_SWVBUS_VALTH USB_SWVBUS_VALTH_MSK + +#define USB_SWVBUS_SESVALTH_POS 2U +#define USB_SWVBUS_SESVALTH_MSK BIT(USB_SWVBUS_SESVALTH_POS) +#define USB_SWVBUS_SESVALTH USB_SWVBUS_SESVALTH_MSK + +#define USB_SWVBUS_SESENDTH_POS 1U +#define USB_SWVBUS_SESENDTH_MSK BIT(USB_SWVBUS_SESENDTH_POS) +#define USB_SWVBUS_SESENDTH USB_SWVBUS_SESENDTH_MSK + +#define USB_SWVBUS_SIGCTRL_POS 0U +#define USB_SWVBUS_SIGCTRL_MSK BIT(USB_SWVBUS_SIGCTRL_POS) +#define USB_SWVBUS_SIGCTRL USB_SWVBUS_SIGCTRL_MSK + +/****************** Bit definition for USB_TMODE register ************************/ + +#define USB_TMODE_PROTECT_POSS 2U +#define USB_TMODE_PROTECT_POSE 7U +#define USB_TMODE_PROTECT_MSK BITS(USB_TMODE_PROTECT_POSS,USB_TMODE_PROTECT_POSE) +#define USB_TMODE_PROTECT USB_TMODE_PROTECT_MSK + +#define USB_TMODE_MEMTST_EN_POS 1U +#define USB_TMODE_MEMTST_EN_MSK BIT(USB_TMODE_MEMTST_EN_POS) +#define USB_TMODE_MEMTST_EN USB_TMODE_MEMTST_EN_MSK + +#define USB_TMODE_ENABLE_POS 0U +#define USB_TMODE_ENABLE_MSK BIT(USB_TMODE_ENABLE_POS) +#define USB_TMODE_ENABLE USB_TMODE_ENABLE_MSK + +/****************** Bit definition for USB_FRAME1 register ************************/ + +#define USB_FRAME1_LOWFRAME_POSS 0U +#define USB_FRAME1_LOWFRAME_POSE 7U +#define USB_FRAME1_LOWFRAME_MSK BITS(USB_FRAME1_LOWFRAME_POSS,USB_FRAME1_LOWFRAME_POSE) +#define USB_FRAME1_LOWFRAME USB_FRAME1_LOWFRAME_MSK + +/****************** Bit definition for USB_FRAME2 register ************************/ + +#define USB_FRAME2_UPFRAME_POSS 0U +#define USB_FRAME2_UPFRAME_POSE 2U +#define USB_FRAME2_UPFRAME_MSK BITS(USB_FRAME2_UPFRAME_POSS,USB_FRAME2_UPFRAME_POSE) +#define USB_FRAME2_UPFRAME USB_FRAME2_UPFRAME_MSK + +/****************** Bit definition for USB_INDEX register ************************/ + +#define USB_INDEX_EPTIDX_POSS 0U +#define USB_INDEX_EPTIDX_POSE 3U +#define USB_INDEX_EPTIDX_MSK BITS(USB_INDEX_EPTIDX_POSS,USB_INDEX_EPTIDX_POSE) +#define USB_INDEX_EPTIDX USB_INDEX_EPTIDX_MSK + +/****************** Bit definition for USB_DEVCON register ************************/ + +#define USB_DEVCON_CID_POS 7U +#define USB_DEVCON_CID_MSK BIT(USB_DEVCON_CID_POS) +#define USB_DEVCON_CID USB_DEVCON_CID_MSK + +#define USB_DEVCON_FSDEV_POS 6U +#define USB_DEVCON_FSDEV_MSK BIT(USB_DEVCON_FSDEV_POS) +#define USB_DEVCON_FSDEV USB_DEVCON_FSDEV_MSK + +#define USB_DEVCON_LSDEV_POS 5U +#define USB_DEVCON_LSDEV_MSK BIT(USB_DEVCON_LSDEV_POS) +#define USB_DEVCON_LSDEV USB_DEVCON_LSDEV_MSK + +#define USB_DEVCON_HOST_POS 2U +#define USB_DEVCON_HOST_MSK BIT(USB_DEVCON_HOST_POS) +#define USB_DEVCON_HOST USB_DEVCON_HOST_MSK + +#define USB_DEVCON_HOSTREQ_POS 1U +#define USB_DEVCON_HOSTREQ_MSK BIT(USB_DEVCON_HOSTREQ_POS) +#define USB_DEVCON_HOSTREQ USB_DEVCON_HOSTREQ_MSK + +#define USB_DEVCON_SESSION_POS 0U +#define USB_DEVCON_SESSION_MSK BIT(USB_DEVCON_SESSION_POS) +#define USB_DEVCON_SESSION USB_DEVCON_SESSION_MSK + +/****************** Bit definition for USB_TXMAXP register ************************/ + +#define USB_TXMAXP_MAXSIZE_POSS 0U +#define USB_TXMAXP_MAXSIZE_POSE 7U +#define USB_TXMAXP_MAXSIZE_MSK BITS(USB_TXMAXP_MAXSIZE_POSS,USB_TXMAXP_MAXSIZE_POSE) +#define USB_TXMAXP_MAXSIZE USB_TXMAXP_MAXSIZE_MSK + +/****************** Bit definition for USB_CSR0L_TXCSRL register ************************/ + +/* Endpoint 0 */ +/* device mode */ +#define USB_CSR0L_SETENDC_POS 7U +#define USB_CSR0L_SETENDC_MSK BIT(USB_CSR0L_SETENDC_POS) +#define USB_CSR0L_SETENDC USB_CSR0L_SETENDC_MSK + +#define USB_CSR0L_RXRDYC_POS 6U +#define USB_CSR0L_RXRDYC_MSK BIT(USB_CSR0L_RXRDYC_POS) +#define USB_CSR0L_RXRDYC USB_CSR0L_RXRDYC_MSK + +#define USB_CSR0L_STALL_POS 5U +#define USB_CSR0L_STALL_MSK BIT(USB_CSR0L_STALL_POS) +#define USB_CSR0L_STALL USB_CSR0L_STALL_MSK + +#define USB_CSR0L_SETEND_POS 4U +#define USB_CSR0L_SETEND_MSK BIT(USB_CSR0L_SETEND_POS) +#define USB_CSR0L_SETEND USB_CSR0L_SETEND_MSK + +#define USB_CSR0L_DATAEND_POS 3U +#define USB_CSR0L_DATAEND_MSK BIT(USB_CSR0L_DATAEND_POS) +#define USB_CSR0L_DATAEND USB_CSR0L_DATAEND_MSK + +/* host mode */ +#define USB_CSR0L_NAKTO_POS 7U +#define USB_CSR0L_NAKTO_MSK BIT(USB_CSR0L_NAKTO_POS) +#define USB_CSR0L_NAKTO USB_CSR0L_NAKTO_MSK + +#define USB_CSR0L_STATUSPKT_POS 6U +#define USB_CSR0L_STATUSPKT_MSK BIT(USB_CSR0L_STATUSPKT_POS) +#define USB_CSR0L_STATUSPKT USB_CSR0L_STATUSPKT_MSK + +#define USB_CSR0L_REQPKT_POS 5U +#define USB_CSR0L_REQPKT_MSK BIT(USB_CSR0L_REQPKT_POS) +#define USB_CSR0L_REQPKT USB_CSR0L_REQPKT_MSK + +#define USB_CSR0L_ERROR_POS 4U +#define USB_CSR0L_ERROR_MSK BIT(USB_CSR0L_ERROR_POS) +#define USB_CSR0L_ERROR USB_CSR0L_ERROR_MSK + +#define USB_CSR0L_SETUPPKT_POS 3U +#define USB_CSR0L_SETUPPKT_MSK BIT(USB_CSR0L_SETUPPKT_POS) +#define USB_CSR0L_SETUPPKT USB_CSR0L_SETUPPKT_MSK + +/* device/host mode */ +#define USB_CSR0L_STALLED_POS 2U +#define USB_CSR0L_STALLED_MSK BIT(USB_CSR0L_STALLED_POS) +#define USB_CSR0L_STALLED USB_CSR0L_STALLED_MSK + +#define USB_CSR0L_TXRDY_POS 1U +#define USB_CSR0L_TXRDY_MSK BIT(USB_CSR0L_TXRDY_POS) +#define USB_CSR0L_TXRDY USB_CSR0L_TXRDY_MSK + +#define USB_CSR0L_RXRDY_POS 0U +#define USB_CSR0L_RXRDY_MSK BIT(USB_CSR0L_RXRDY_POS) +#define USB_CSR0L_RXRDY USB_CSR0L_RXRDY_MSK + +/* Endpoint 1-6 */ +/* host mode */ +#define USB_TXCSRL_NAKTO_POS 7U +#define USB_TXCSRL_NAKTO_MSK BIT(USB_TXCSRL_NAKTO_POS) +#define USB_TXCSRL_NAKTO USB_TXCSRL_NAKTO_MSK + +/* device/host mode */ +#define USB_TXCSRL_CLRDT_POS 6U +#define USB_TXCSRL_CLRDT_MSK BIT(USB_TXCSRL_CLRDT_POS) +#define USB_TXCSRL_CLRDT USB_TXCSRL_CLRDT_MSK + +#define USB_TXCSRL_STALLED_POS 5U +#define USB_TXCSRL_STALLED_MSK BIT(USB_TXCSRL_STALLED_POS) +#define USB_TXCSRL_STALLED USB_TXCSRL_STALLED_MSK + +/* device mode */ +#define USB_TXCSRL_STALL_POS 4U +#define USB_TXCSRL_STALL_MSK BIT(USB_TXCSRL_STALL_POS) +#define USB_TXCSRL_STALL USB_TXCSRL_STALL_MSK + +/* device/host mode */ +#define USB_TXCSRL_FLUSH_POS 3U +#define USB_TXCSRL_FLUSH_MSK BIT(USB_TXCSRL_FLUSH_POS) +#define USB_TXCSRL_FLUSH USB_TXCSRL_FLUSH_MSK + +/* device mode */ +#define USB_TXCSRL_UNDRUN_POS 2U +#define USB_TXCSRL_UNDRUN_MSK BIT(USB_TXCSRL_UNDRUN_POS) +#define USB_TXCSRL_UNDRUN USB_TXCSRL_UNDRUN_MSK + +/* host mode */ +#define USB_TXCSRL_ERROR_POS 2U +#define USB_TXCSRL_ERROR_MSK BIT(USB_TXCSRL_ERROR_POS) +#define USB_TXCSRL_ERROR USB_TXCSRL_ERROR_MSK + +/* device/host mode */ +#define USB_TXCSRL_FIFONE_POS 1U +#define USB_TXCSRL_FIFONE_MSK BIT(USB_TXCSRL_FIFONE_POS) +#define USB_TXCSRL_FIFONE USB_TXCSRL_FIFONE_MSK + +#define USB_TXCSRL_TXRDY_POS 0U +#define USB_TXCSRL_TXRDY_MSK BIT(USB_TXCSRL_TXRDY_POS) +#define USB_TXCSRL_TXRDY USB_TXCSRL_TXRDY_MSK + +/****************** Bit definition for USB_CSR0H_TXCSRH register ************************/ + +/* Endpoint 0 */ +/* device/host mode */ +#define USB_CSR0H_FLUSH_POS 0U +#define USB_CSR0H_FLUSH_MSK BIT(USB_CSR0H_FLUSH_POS) +#define USB_CSR0H_FLUSH USB_CSR0H_FLUSH_MSK + +/* For endpoint 1-6 */ +/* device/host mode */ +#define USB_TXCSRH_AUTOSET_POS 7U +#define USB_TXCSRH_AUTOSET_MSK BIT(USB_TXCSRH_AUTOSET_POS) +#define USB_TXCSRH_AUTOSET USB_TXCSRH_AUTOSET_MSK + +#define USB_TXCSRH_ISO_POS 6U +#define USB_TXCSRH_ISO_MSK BIT(USB_TXCSRH_ISO_POS) +#define USB_TXCSRH_ISO USB_TXCSRH_ISO_MSK + +#define USB_TXCSRH_MODE_POS 5U +#define USB_TXCSRH_MODE_MSK BIT(USB_TXCSRH_MODE_POS) +#define USB_TXCSRH_MODE USB_TXCSRH_MODE_MSK + +#define USB_TXCSRH_FDT_POS 3U +#define USB_TXCSRH_FDT_MSK BIT(USB_TXCSRH_FDT_POS) +#define USB_TXCSRH_FDT USB_TXCSRH_FDT_MSK + +/****************** Bit definition for USB_RXMAXP register ************************/ + +#define USB_RXMAXP_MAXSIZE_POSS 0U +#define USB_RXMAXP_MAXSIZE_POSE 7U +#define USB_RXMAXP_MAXSIZE_MSK BITS(USB_RXMAXP_MAXSIZE_POSS,USB_RXMAXP_MAXSIZE_POSE) +#define USB_RXMAXP_MAXSIZE USB_RXMAXP_MAXSIZE_MSK + +/****************** Bit definition for USB_RXCSRL register ************************/ + +/* device/host mode */ +#define USB_RXCSRL_CLRDT_POS 7U +#define USB_RXCSRL_CLRDT_MSK BIT(USB_RXCSRL_CLRDT_POS) +#define USB_RXCSRL_CLRDT USB_RXCSRL_CLRDT_MSK + +#define USB_RXCSRL_STALLED_POS 6U +#define USB_RXCSRL_STALLED_MSK BIT(USB_RXCSRL_STALLED_POS) +#define USB_RXCSRL_STALLED USB_RXCSRL_STALLED_MSK + +/* device mode */ +#define USB_RXCSRL_STALL_POS 5U +#define USB_RXCSRL_STALL_MSK BIT(USB_RXCSRL_STALL_POS) +#define USB_RXCSRL_STALL USB_RXCSRL_STALL_MSK + +/* host mode */ +#define USB_RXCSRL_REQPKT_POS 5U +#define USB_RXCSRL_REQPKT_MSK BIT(USB_RXCSRL_REQPKT_POS) +#define USB_RXCSRL_REQPKT USB_RXCSRL_REQPKT_MSK + +/* device/host mode */ +#define USB_RXCSRL_FLUSH_POS 4U +#define USB_RXCSRL_FLUSH_MSK BIT(USB_RXCSRL_FLUSH_POS) +#define USB_RXCSRL_FLUSH USB_RXCSRL_FLUSH_MSK + +/* device/host mode */ +#define USB_RXCSRL_DATAERR_POS 3U +#define USB_RXCSRL_DATAERR_MSK BIT(USB_RXCSRL_DATAERR_POS) +#define USB_RXCSRL_DATAERR USB_RXCSRL_DATAERR_MSK + +/* host mode */ +#define USB_RXCSRL_NAKTO_POS 3U +#define USB_RXCSRL_NAKTO_MSK BIT(USB_RXCSRL_NAKTO_POS) +#define USB_RXCSRL_NAKTO USB_RXCSRL_NAKTO_MSK + +/* device mode */ +#define USB_RXCSRL_OVERRUN_POS 2U +#define USB_RXCSRL_OVERRUN_MSK BIT(USB_RXCSRL_OVERRUN_POS) +#define USB_RXCSRL_OVERRUN USB_RXCSRL_OVERRUN_MSK + +/* host mode */ +#define USB_RXCSRL_ERROR_POS 2U +#define USB_RXCSRL_ERROR_MSK BIT(USB_RXCSRL_ERROR_POS) +#define USB_RXCSRL_ERROR USB_RXCSRL_ERROR_MSK + +/* device/host mode */ +#define USB_RXCSRL_FULL_POS 1U +#define USB_RXCSRL_FULL_MSK BIT(USB_RXCSRL_FULL_POS) +#define USB_RXCSRL_FULL USB_RXCSRL_FULL_MSK + +#define USB_RXCSRL_RXRDY_POS 0U +#define USB_RXCSRL_RXRDY_MSK BIT(USB_RXCSRL_RXRDY_POS) +#define USB_RXCSRL_RXRDY USB_RXCSRL_RXRDY_MSK + +/****************** Bit definition for USB_RXCSRH register ************************/ + +/* device/host mode */ +#define USB_RXCSRH_AUTOCLR_POS 7U +#define USB_RXCSRH_AUTOCLR_MSK BIT(USB_RXCSRH_AUTOCLR_POS) +#define USB_RXCSRH_AUTOCLR USB_RXCSRH_AUTOCLR_MSK + +/* device mode */ +#define USB_RXCSRH_ISO_POS 6U +#define USB_RXCSRH_ISO_MSK BIT(USB_RXCSRH_ISO_POS) +#define USB_RXCSRH_ISO USB_RXCSRH_ISO_MSK + +/* host mode */ +#define USB_RXCSRH_AUTOREQ_POS 6U +#define USB_RXCSRH_AUTOREQ_MSK BIT(USB_RXCSRH_AUTOREQ_POS) +#define USB_RXCSRH_AUTOREQ USB_RXCSRH_AUTOREQ_MSK + +/****************** Bit definition for USB_COUNT0_RX1 register ************************/ + +/* Endpoint 0 */ +#define USB_COUNT0_COUNT_POSS 0U +#define USB_COUNT0_COUNT_POSE 6U +#define USB_COUNT0_COUNT_MSK BITS(USB_COUNT0_COUNT_POSS,USB_COUNT0_COUNT_POSE) +#define USB_COUNT0_COUNT USB_COUNT0_COUNT_MSK + + +/*For endpoint 1-6 */ +#define USB_RX1_PKTLOW_POSS 0U +#define USB_RX1_PKTLOW_POSE 7U +#define USB_RX1_PKTLOW_MSK BITS(USB_RX1_PKTLOW_POSS,USB_RX1_PKTLOW_POSE) +#define USB_RX1_PKTLOW USB_RX1_PKTLOW_MSK + +/****************** Bit definition for USB_RXCOUNT2 register ************************/ + +#define USB_RXCOUNT2_PKTHIGH_POSS 0U +#define USB_RXCOUNT2_PKTHIGH_POSE 2U +#define USB_RXCOUNT2_PKTHIGH_MSK BITS(USB_RXCOUNT2_PKTHIGH_POSS,USB_RXCOUNT2_PKTHIGH_POSE) +#define USB_RXCOUNT2_PKTHIGH USB_RXCOUNT2_PKTHIGH_MSK + +/****************** Bit definition for USB_TXTYPE register ************************/ + +#define USB_TXTYPE_PROTOCOL_POSS 4U +#define USB_TXTYPE_PROTOCOL_POSE 5U +#define USB_TXTYPE_PROTOCOL_MSK BITS(USB_TXTYPE_PROTOCOL_POSS,USB_TXTYPE_PROTOCOL_POSE) +#define USB_TXTYPE_PROTOCOL USB_TXTYPE_PROTOCOL_MSK + +#define USB_TXTYPE_TEPN_POSS 0U +#define USB_TXTYPE_TEPN_POSE 3U +#define USB_TXTYPE_TEPN_MSK BITS(USB_TXTYPE_TEPN_POSS,USB_TXTYPE_TEPN_POSE) +#define USB_TXTYPE_TEPN USB_TXTYPE_TEPN_MSK + +/****************** Bit definition for USB_NAKLIMIT0_TXINTERVAL register ************************/ + +/* Endpoint 0 */ +#define USB_NAKLIMIT0_NAKLMT_POSS 0U +#define USB_NAKLIMIT0_NAKLMT_POSE 7U +#define USB_NAKLIMIT0_NAKLMT_MSK BITS(USB_NAKLIMIT0_NAKLMT_POSS,USB_NAKLIMIT0_NAKLMT_POSE) +#define USB_NAKLIMIT0_NAKLMT USB_NAKLIMIT0_NAKLMT_MSK + +/* For endpoint 1-6 */ +#define USB_TXINTERVAL_TXPOLL_POSS 0U +#define USB_TXINTERVAL_TXPOLL_POSE 7U +#define USB_TXINTERVAL_TXPOLL_MSK BITS(USB_TXINTERVAL_TXPOLL_POSS,USB_TXINTERVAL_TXPOLL_POSE) +#define USB_TXINTERVAL_TXPOLL USB_TXINTERVAL_TXPOLL_MSK + +#define USB_TXINTERVAL_NAKLMT_POSS 0U +#define USB_TXINTERVAL_NAKLMT_POSE 7U +#define USB_TXINTERVAL_NAKLMT_MSK BITS(USB_TXINTERVAL_NAKLMT_POSS,USB_TXINTERVAL_NAKLMT_POSE) +#define USB_TXINTERVAL_NAKLMT USB_TXINTERVAL_NAKLMT_POSS + +/****************** Bit definition for USB_RXTYPE register ************************/ + +#define USB_RXTYPE_PROTOCOL_POSS 4U +#define USB_RXTYPE_PROTOCOL_POSE 5U +#define USB_RXTYPE_PROTOCOL_MSK BITS(USB_RXTYPE_PROTOCOL_POSS,USB_RXTYPE_PROTOCOL_POSE) +#define USB_RXTYPE_PROTOCOL USB_RXTYPE_PROTOCOL_MSK + +#define USB_RXTYPE_TEPN_POSS 0U +#define USB_RXTYPE_TEPN_POSE 3U +#define USB_RXTYPE_TEPN_MSK BITS(USB_RXTYPE_TEPN_POSS,USB_RXTYPE_TEPN_POSE) +#define USB_RXTYPE_TEPN USB_RXTYPE_TEPN_MSK + +/****************** Bit definition for USB_RXINTERVAL register ************************/ + +#define USB_RXINTERVAL_RXPOLL_POSS 0U +#define USB_RXINTERVAL_RXPOLL_POSE 7U +#define USB_RXINTERVAL_RXPOLL_MSK BITS(USB_RXINTERVAL_RXPOLL_POSS,USB_RXINTERVAL_RXPOLL_POSE) +#define USB_RXINTERVAL_RXPOLL USB_RXINTERVAL_RXPOLL_MSK + +#define USB_RXINTERVAL_NAKLMT_POSS 0U +#define USB_RXINTERVAL_NAKLMT_POSE 7U +#define USB_RXINTERVAL_NAKLMT_MSK BITS(USB_RXINTERVAL_NAKLMT_POSS,USB_RXINTERVAL_NAKLMT_POSE) +#define USB_RXINTERVAL_NAKLMT USB_RXINTERVAL_NAKLMT_MSK + +/****************** Bit definition for USB_TXFIFO1 register ************************/ + +#define USB_TXFIFO1_ADDRL_POSS 0U +#define USB_TXFIFO1_ADDRL_POSE 7U +#define USB_TXFIFO1_ADDRL_MSK BITS(USB_TXFIFO1_ADDRL_POSS,USB_TXFIFO1_ADDRL_POSE) +#define USB_TXFIFO1_ADDRL USB_TXFIFO1_ADDRL_MSK + +/****************** Bit definition for USB_TXFIFO2 register ************************/ + +#define USB_TXFIFO2_MAXPKTSIZE_POSS 5U +#define USB_TXFIFO2_MAXPKTSIZE_POSE 7U +#define USB_TXFIFO2_MAXPKTSIZE_MSK BITS(USB_TXFIFO2_MAXPKTSIZE_POSS,USB_TXFIFO2_MAXPKTSIZE_POSE) +#define USB_TXFIFO2_MAXPKTSIZE USB_TXFIFO2_MAXPKTSIZE_MSK + +#define USB_TXFIFO2_DPB_POS 4U +#define USB_TXFIFO2_DPB_MSK BIT(USB_TXFIFO2_DPB_POS) +#define USB_TXFIFO2_DPB USB_TXFIFO2_DPB_MSK + +#define USB_TXFIFO2_ADDRH_POSS 0U +#define USB_TXFIFO2_ADDRH_POSE 3U +#define USB_TXFIFO2_ADDRH_MSK BITS(USB_TXFIFO2_ADDRH_POSS,USB_TXFIFO2_ADDRH_POSE) +#define USB_TXFIFO2_ADDRH USB_TXFIFO2_ADDRH_MSK + +/****************** Bit definition for USB_RXFIFO1 register ************************/ + +#define USB_RXFIFO1_ADDRL_POSS 0U +#define USB_RXFIFO1_ADDRL_POSE 7U +#define USB_RXFIFO1_ADDRL_MSK BITS(USB_RXFIFO1_ADDRL_POSS,USB_RXFIFO1_ADDRL_POSE) +#define USB_RXFIFO1_ADDRL USB_RXFIFO1_ADDRL_MSK + +/****************** Bit definition for USB_RXFIFO2 register ************************/ + +#define USB_RXFIFO2_MAXPKTSIZE_POSS 5U +#define USB_RXFIFO2_MAXPKTSIZE_POSE 7U +#define USB_RXFIFO2_MAXPKTSIZE_MSK BITS(USB_RXFIFO2_MAXPKTSIZE_POSS,USB_RXFIFO2_MAXPKTSIZE_POSE) +#define USB_RXFIFO2_MAXPKTSIZE USB_RXFIFO2_MAXPKTSIZE_MSK + +#define USB_RXFIFO2_DPB_POS 4U +#define USB_RXFIFO2_DPB_MSK BIT(USB_RXFIFO2_DPB_POS) +#define USB_RXFIFO2_DPB USB_RXFIFO2_DPB_MSK + +#define USB_RXFIFO2_ADDRH_POSS 0U +#define USB_RXFIFO2_ADDRH_POSE 3U +#define USB_RXFIFO2_ADDRH_MSK BITS(USB_RXFIFO2_ADDRH_POSS,USB_RXFIFO2_ADDRH_POSE) +#define USB_RXFIFO2_ADDRH USB_RXFIFO2_ADDRH_MSK + +/************* Bit definition for USB_EP0FIFO/USB_EPxFIFO register *****************/ + +#define USB_EP0FIFO_FIFO0_POSS 0U +#define USB_EP0FIFO_FIFO0_POSE 7U +#define USB_EP0FIFO_FIFO0_MSK BITS(USB_EP0FIFO_FIFO0_POSS,USB_EP0FIFO_FIFO0_POSE) +#define USB_EP0FIFO_FIFO0 USB_EP0FIFO_FIFO0_MSK + +#define USB_EP1FIFO_FIFO1_POSS 0U +#define USB_EP1FIFO_FIFO1_POSE 7U +#define USB_EP1FIFO_FIFO1_MSK BITS(USB_EP1FIFO_FIFO1_POSS,USB_EP1FIFO_FIFO1_POSE) +#define USB_EP1FIFO_FIFO1 USB_EP1FIFO_FIFO1_MSK + +#define USB_EP2FIFO_FIFO2_POSS 0U +#define USB_EP2FIFO_FIFO2_POSE 7U +#define USB_EP2FIFO_FIFO2_MSK BITS(USB_EP2FIFO_FIFO2_POSS,USB_EP2FIFO_FIFO2_POSE) +#define USB_EP2FIFO_FIFO2 USB_EP2FIFO_FIFO2_MSK + +#define USB_EP3FIFO_FIFO3_POSS 0U +#define USB_EP3FIFO_FIFO3_POSE 7U +#define USB_EP3FIFO_FIFO3_MSK BITS(USB_EP3FIFO_FIFO3_POSS,USB_EP3FIFO_FIFO3_POSE) +#define USB_EP3FIFO_FIFO3 USB_EP3FIFO_FIFO3_MSK + +#define USB_EP4FIFO_FIFO4_POSS 0U +#define USB_EP4FIFO_FIFO4_POSE 7U +#define USB_EP4FIFO_FIFO4_MSK BITS(USB_EP4FIFO_FIFO4_POSS,USB_EP4FIFO_FIFO4_POSE) +#define USB_EP4FIFO_FIFO4 USB_EP4FIFO_FIFO4_MSK + +#define USB_EP5FIFO_FIFO5_POSS 0U +#define USB_EP5FIFO_FIFO5_POSE 7U +#define USB_EP5FIFO_FIFO5_MSK BITS(USB_EP5FIFO_FIFO5_POSS,USB_EP5FIFO_FIFO5_POSE) +#define USB_EP5FIFO_FIFO5 USB_EP5FIFO_FIFO5_MSK + +#define USB_EP6FIFO_FIFO6_POSS 0U +#define USB_EP6FIFO_FIFO6_POSE 7U +#define USB_EP6FIFO_FIFO6_MSK BITS(USB_EP6FIFO_FIFO6_POSS,USB_EP6FIFO_FIFO6_POSE) +#define USB_EP6FIFO_FIFO6 USB_EP6FIFO_FIFO6_MSK + +#define USB_EPxFIFO_FIFOx_POSS 0U +#define USB_EPxFIFO_FIFOx_POSE 7U +#define USB_EPxFIFO_FIFOx_MSK BITS(USB_EPxFIFO_FIFOx_POSS,USB_EPxFIFO_FIFOx_POSE) +#define USB_EPxFIFO_FIFOx USB_EPxFIFO_FIFOx_MSK + +/****************** Bit definition for USB_TXIER register ************************/ + +#define USB_TXIER_EP6IE_POS 6U +#define USB_TXIER_EP6IE_MSK BIT(USB_TXIER_EP6IE_POS) +#define USB_TXIER_EP6IE USB_TXIER_EP6IE_MSK + +#define USB_TXIER_EP5IE_POS 5U +#define USB_TXIER_EP5IE_MSK BIT(USB_TXIER_EP5IE_POS) +#define USB_TXIER_EP5IE USB_TXIER_EP5IE_MSK + +#define USB_TXIER_EP4IE_POS 4U +#define USB_TXIER_EP4IE_MSK BIT(USB_TXIER_EP4IE_POS) +#define USB_TXIER_EP4IE USB_TXIER_EP4IE_MSK + +#define USB_TXIER_EP3IE_POS 3U +#define USB_TXIER_EP3IE_MSK BIT(USB_TXIER_EP3IE_POS) +#define USB_TXIER_EP3IE USB_TXIER_EP3IE_MSK + +#define USB_TXIER_EP2IE_POS 2U +#define USB_TXIER_EP2IE_MSK BIT(USB_TXIER_EP2IE_POS) +#define USB_TXIER_EP2IE USB_TXIER_EP2IE_MSK + +#define USB_TXIER_EP1IE_POS 1U +#define USB_TXIER_EP1IE_MSK BIT(USB_TXIER_EP1IE_POS) +#define USB_TXIER_EP1IE USB_TXIER_EP1IE_MSK + +#define USB_TXIER_EP0IE_POS 0U +#define USB_TXIER_EP0IE_MSK BIT(USB_TXIER_EP0IE_POS) +#define USB_TXIER_EP0IE USB_TXIER_EP0IE_MSK + +/****************** Bit definition for USB_RXIER register ************************/ + +#define USB_RXIER_EP6IE_POS 6U +#define USB_RXIER_EP6IE_MSK BIT(USB_RXIER_EP6IE_POS) +#define USB_RXIER_EP6IE USB_RXIER_EP6IE_MSK + +#define USB_RXIER_EP5IE_POS 5U +#define USB_RXIER_EP5IE_MSK BIT(USB_RXIER_EP5IE_POS) +#define USB_RXIER_EP5IE USB_RXIER_EP5IE_MSK + +#define USB_RXIER_EP4IE_POS 4U +#define USB_RXIER_EP4IE_MSK BIT(USB_RXIER_EP4IE_POS) +#define USB_RXIER_EP4IE USB_RXIER_EP4IE_MSK + +#define USB_RXIER_EP3IE_POS 3U +#define USB_RXIER_EP3IE_MSK BIT(USB_RXIER_EP3IE_POS) +#define USB_RXIER_EP3IE USB_RXIER_EP3IE_MSK + +#define USB_RXIER_EP2IE_POS 2U +#define USB_RXIER_EP2IE_MSK BIT(USB_RXIER_EP2IE_POS) +#define USB_RXIER_EP2IE USB_RXIER_EP2IE_MSK + +#define USB_RXIER_EP1IE_POS 1U +#define USB_RXIER_EP1IE_MSK BIT(USB_RXIER_EP1IE_POS) +#define USB_RXIER_EP1IE USB_RXIER_EP1IE_MSK + +/****************** Bit definition for USB_TXIDR register ************************/ + +#define USB_TXIDR_EP6ID_POS 6U +#define USB_TXIDR_EP6ID_MSK BIT(USB_TXIDR_EP6ID_POS) +#define USB_TXIDR_EP6ID USB_TXIDR_EP6ID_MSK + +#define USB_TXIDR_EP5ID_POS 5U +#define USB_TXIDR_EP5ID_MSK BIT(USB_TXIDR_EP5ID_POS) +#define USB_TXIDR_EP5ID USB_TXIDR_EP5ID_MSK + +#define USB_TXIDR_EP4ID_POS 4U +#define USB_TXIDR_EP4ID_MSK BIT(USB_TXIDR_EP4ID_POS) +#define USB_TXIDR_EP4ID USB_TXIDR_EP4ID_MSK + +#define USB_TXIDR_EP3ID_POS 3U +#define USB_TXIDR_EP3ID_MSK BIT(USB_TXIDR_EP3ID_POS) +#define USB_TXIDR_EP3ID USB_TXIDR_EP3ID_MSK + +#define USB_TXIDR_EP2ID_POS 2U +#define USB_TXIDR_EP2ID_MSK BIT(USB_TXIDR_EP2ID_POS) +#define USB_TXIDR_EP2ID USB_TXIDR_EP2ID_MSK + +#define USB_TXIDR_EP1ID_POS 1U +#define USB_TXIDR_EP1ID_MSK BIT(USB_TXIDR_EP1ID_POS) +#define USB_TXIDR_EP1ID USB_TXIDR_EP1ID_MSK + +#define USB_TXIDR_EP0ID_POS 0U +#define USB_TXIDR_EP0ID_MSK BIT(USB_TXIDR_EP0ID_POS) +#define USB_TXIDR_EP0ID USB_TXIDR_EP0ID_MSK + +/****************** Bit definition for USB_RXIDR register ************************/ + +#define USB_RXIDR_EP6ID_POS 6U +#define USB_RXIDR_EP6ID_MSK BIT(USB_RXIDR_EP6ID_POS) +#define USB_RXIDR_EP6ID USB_RXIDR_EP6ID_MSK + +#define USB_RXIDR_EP5ID_POS 5U +#define USB_RXIDR_EP5ID_MSK BIT(USB_RXIDR_EP5ID_POS) +#define USB_RXIDR_EP5ID USB_RXIDR_EP5ID_MSK + +#define USB_RXIDR_EP4ID_POS 4U +#define USB_RXIDR_EP4ID_MSK BIT(USB_RXIDR_EP4ID_POS) +#define USB_RXIDR_EP4ID USB_RXIDR_EP4ID_MSK + +#define USB_RXIDR_EP3ID_POS 3U +#define USB_RXIDR_EP3ID_MSK BIT(USB_RXIDR_EP3ID_POS) +#define USB_RXIDR_EP3ID USB_RXIDR_EP3ID_MSK + +#define USB_RXIDR_EP2ID_POS 2U +#define USB_RXIDR_EP2ID_MSK BIT(USB_RXIDR_EP2ID_POS) +#define USB_RXIDR_EP2ID USB_RXIDR_EP2ID_MSK + +#define USB_RXIDR_EP1ID_POS 1U +#define USB_RXIDR_EP1ID_MSK BIT(USB_RXIDR_EP1ID_POS) +#define USB_RXIDR_EP1ID USB_RXIDR_EP1ID_MSK + +/****************** Bit definition for USB_TXIVS register ************************/ + +#define USB_TXIVS_EP6IVS_POS 6U +#define USB_TXIVS_EP6IVS_MSK BIT(USB_TXIVS_EP6IVS_POS) +#define USB_TXIVS_EP6IVS USB_TXIVS_EP6IVS_MSK + +#define USB_TXIVS_EP5IVS_POS 5U +#define USB_TXIVS_EP5IVS_MSK BIT(USB_TXIVS_EP5IVS_POS) +#define USB_TXIVS_EP5IVS USB_TXIVS_EP5IVS_MSK + +#define USB_TXIVS_EP4IVS_POS 4U +#define USB_TXIVS_EP4IVS_MSK BIT(USB_TXIVS_EP4IVS_POS) +#define USB_TXIVS_EP4IVS USB_TXIVS_EP4IVS_MSK + +#define USB_TXIVS_EP3IVS_POS 3U +#define USB_TXIVS_EP3IVS_MSK BIT(USB_TXIVS_EP3IVS_POS) +#define USB_TXIVS_EP3IVS USB_TXIVS_EP3IVS_MSK + +#define USB_TXIVS_EP2IVS_POS 2U +#define USB_TXIVS_EP2IVS_MSK BIT(USB_TXIVS_EP2IVS_POS) +#define USB_TXIVS_EP2IVS USB_TXIVS_EP2IVS_MSK + +#define USB_TXIVS_EP1IVS_POS 1U +#define USB_TXIVS_EP1IVS_MSK BIT(USB_TXIVS_EP1IVS_POS) +#define USB_TXIVS_EP1IVS USB_TXIVS_EP1IVS_MSK + +#define USB_TXIVS_EP0IVS_POS 0U +#define USB_TXIVS_EP0IVS_MSK BIT(USB_TXIVS_EP0IVS_POS) +#define USB_TXIVS_EP0IVS USB_TXIVS_EP0IVS_MSK + +/****************** Bit definition for USB_RXIVS register ************************/ + +#define USB_RXIVS_EP6IVS_POS 6U +#define USB_RXIVS_EP6IVS_MSK BIT(USB_RXIVS_EP6IVS_POS) +#define USB_RXIVS_EP6IVS USB_RXIVS_EP6IVS_MSK + +#define USB_RXIVS_EP5IVS_POS 5U +#define USB_RXIVS_EP5IVS_MSK BIT(USB_RXIVS_EP5IVS_POS) +#define USB_RXIVS_EP5IVS USB_RXIVS_EP5IVS_MSK + +#define USB_RXIVS_EP4IVS_POS 4U +#define USB_RXIVS_EP4IVS_MSK BIT(USB_RXIVS_EP4IVS_POS) +#define USB_RXIVS_EP4IVS USB_RXIVS_EP4IVS_MSK + +#define USB_RXIVS_EP3IVS_POS 3U +#define USB_RXIVS_EP3IVS_MSK BIT(USB_RXIVS_EP3IVS_POS) +#define USB_RXIVS_EP3IVS USB_RXIVS_EP3IVS_MSK + +#define USB_RXIVS_EP2IVS_POS 2U +#define USB_RXIVS_EP2IVS_MSK BIT(USB_RXIVS_EP2IVS_POS) +#define USB_RXIVS_EP2IVS USB_RXIVS_EP2IVS_MSK + +#define USB_RXIVS_EP1IVS_POS 1U +#define USB_RXIVS_EP1IVS_MSK BIT(USB_RXIVS_EP1IVS_POS) +#define USB_RXIVS_EP1IVS USB_RXIVS_EP1IVS_MSK + +/****************** Bit definition for USB_TXRIF register ************************/ + +#define USB_TXRIF_EP6RIF_POS 6U +#define USB_TXRIF_EP6RIF_MSK BIT(USB_TXRIF_EP6RIF_POS) +#define USB_TXRIF_EP6RIF USB_TXRIF_EP6RIF_MSK + +#define USB_TXRIF_EP5RIF_POS 5U +#define USB_TXRIF_EP5RIF_MSK BIT(USB_TXRIF_EP5RIF_POS) +#define USB_TXRIF_EP5RIF USB_TXRIF_EP5RIF_MSK + +#define USB_TXRIF_EP4RIF_POS 4U +#define USB_TXRIF_EP4RIF_MSK BIT(USB_TXRIF_EP4RIF_POS) +#define USB_TXRIF_EP4RIF USB_TXRIF_EP4RIF_MSK + +#define USB_TXRIF_EP3RIF_POS 3U +#define USB_TXRIF_EP3RIF_MSK BIT(USB_TXRIF_EP3RIF_POS) +#define USB_TXRIF_EP3RIF USB_TXRIF_EP3RIF_MSK + +#define USB_TXRIF_EP2RIF_POS 2U +#define USB_TXRIF_EP2RIF_MSK BIT(USB_TXRIF_EP2RIF_POS) +#define USB_TXRIF_EP2RIF USB_TXRIF_EP2RIF_MSK + +#define USB_TXRIF_EP1RIF_POS 1U +#define USB_TXRIF_EP1RIF_MSK BIT(USB_TXRIF_EP1RIF_POS) +#define USB_TXRIF_EP1RIF USB_TXRIF_EP1RIF_MSK + +#define USB_TXRIF_EP0RIF_POS 0U +#define USB_TXRIF_EP0RIF_MSK BIT(USB_TXRIF_EP0RIF_POS) +#define USB_TXRIF_EP0RIF USB_TXRIF_EP0RIF_MSK + +/****************** Bit definition for USB_RXRIF register ************************/ + +#define USB_RXRIF_EP6RIF_POS 6U +#define USB_RXRIF_EP6RIF_MSK BIT(USB_RXRIF_EP6RIF_POS) +#define USB_RXRIF_EP6RIF USB_RXRIF_EP6RIF_MSK + +#define USB_RXRIF_EP5RIF_POS 5U +#define USB_RXRIF_EP5RIF_MSK BIT(USB_RXRIF_EP5RIF_POS) +#define USB_RXRIF_EP5RIF USB_RXRIF_EP5RIF_MSK + +#define USB_RXRIF_EP4RIF_POS 4U +#define USB_RXRIF_EP4RIF_MSK BIT(USB_RXRIF_EP4RIF_POS) +#define USB_RXRIF_EP4RIF USB_RXRIF_EP4RIF_MSK + +#define USB_RXRIF_EP3RIF_POS 3U +#define USB_RXRIF_EP3RIF_MSK BIT(USB_RXRIF_EP3RIF_POS) +#define USB_RXRIF_EP3RIF USB_RXRIF_EP3RIF_MSK + +#define USB_RXRIF_EP2RIF_POS 2U +#define USB_RXRIF_EP2RIF_MSK BIT(USB_RXRIF_EP2RIF_POS) +#define USB_RXRIF_EP2RIF USB_RXRIF_EP2RIF_MSK + +#define USB_RXRIF_EP1RIF_POS 1U +#define USB_RXRIF_EP1RIF_MSK BIT(USB_RXRIF_EP1RIF_POS) +#define USB_RXRIF_EP1RIF USB_RXRIF_EP1RIF_MSK + +/****************** Bit definition for USB_TXIFM register ************************/ + +#define USB_TXIFM_EP6IFM_POS 6U +#define USB_TXIFM_EP6IFM_MSK BIT(USB_TXIFM_EP6IFM_POS) +#define USB_TXIFM_EP6IFM USB_TXIFM_EP6IFM_MSK + +#define USB_TXIFM_EP5IFM_POS 5U +#define USB_TXIFM_EP5IFM_MSK BIT(USB_TXIFM_EP5IFM_POS) +#define USB_TXIFM_EP5IFM USB_TXIFM_EP5IFM_MSK + +#define USB_TXIFM_EP4IFM_POS 4U +#define USB_TXIFM_EP4IFM_MSK BIT(USB_TXIFM_EP4IFM_POS) +#define USB_TXIFM_EP4IFM USB_TXIFM_EP4IFM_MSK + +#define USB_TXIFM_EP3IFM_POS 3U +#define USB_TXIFM_EP3IFM_MSK BIT(USB_TXIFM_EP3IFM_POS) +#define USB_TXIFM_EP3IFM USB_TXIFM_EP3IFM_MSK + +#define USB_TXIFM_EP2IFM_POS 2U +#define USB_TXIFM_EP2IFM_MSK BIT(USB_TXIFM_EP2IFM_POS) +#define USB_TXIFM_EP2IFM USB_TXIFM_EP2IFM_MSK + +#define USB_TXIFM_EP1IFM_POS 1U +#define USB_TXIFM_EP1IFM_MSK BIT(USB_TXIFM_EP1IFM_POS) +#define USB_TXIFM_EP1IFM USB_TXIFM_EP1IFM_MSK + +#define USB_TXIFM_EP0IFM_POS 0U +#define USB_TXIFM_EP0IFM_MSK BIT(USB_TXIFM_EP0IFM_POS) +#define USB_TXIFM_EP0IFM USB_TXIFM_EP0IFM_MSK + +/****************** Bit definition for USB_RXIFM register ************************/ + +#define USB_RXIFM_EP6IFM_POS 6U +#define USB_RXIFM_EP6IFM_MSK BIT(USB_RXIFM_EP6IFM_POS) +#define USB_RXIFM_EP6IFM USB_RXIFM_EP6IFM_MSK + +#define USB_RXIFM_EP5IFM_POS 5U +#define USB_RXIFM_EP5IFM_MSK BIT(USB_RXIFM_EP5IFM_POS) +#define USB_RXIFM_EP5IFM USB_RXIFM_EP5IFM_MSK + +#define USB_RXIFM_EP4IFM_POS 4U +#define USB_RXIFM_EP4IFM_MSK BIT(USB_RXIFM_EP4IFM_POS) +#define USB_RXIFM_EP4IFM USB_RXIFM_EP4IFM_MSK + +#define USB_RXIFM_EP3IFM_POS 3U +#define USB_RXIFM_EP3IFM_MSK BIT(USB_RXIFM_EP3IFM_POS) +#define USB_RXIFM_EP3IFM USB_RXIFM_EP3IFM_MSK + +#define USB_RXIFM_EP2IFM_POS 2U +#define USB_RXIFM_EP2IFM_MSK BIT(USB_RXIFM_EP2IFM_POS) +#define USB_RXIFM_EP2IFM USB_RXIFM_EP2IFM_MSK + +#define USB_RXIFM_EP1IFM_POS 1U +#define USB_RXIFM_EP1IFM_MSK BIT(USB_RXIFM_EP1IFM_POS) +#define USB_RXIFM_EP1IFM USB_RXIFM_EP1IFM_MSK + +/****************** Bit definition for USB_TXICR register ************************/ + +#define USB_TXICR_EP6ICR_POS 6U +#define USB_TXICR_EP6ICR_MSK BIT(USB_TXICR_EP6ICR_POS) +#define USB_TXICR_EP6ICR USB_TXICR_EP6ICR_MSK + +#define USB_TXICR_EP5ICR_POS 5U +#define USB_TXICR_EP5ICR_MSK BIT(USB_TXICR_EP5ICR_POS) +#define USB_TXICR_EP5ICR USB_TXICR_EP5ICR_MSK + +#define USB_TXICR_EP4ICR_POS 4U +#define USB_TXICR_EP4ICR_MSK BIT(USB_TXICR_EP4ICR_POS) +#define USB_TXICR_EP4ICR USB_TXICR_EP4ICR_MSK + +#define USB_TXICR_EP3ICR_POS 3U +#define USB_TXICR_EP3ICR_MSK BIT(USB_TXICR_EP3ICR_POS) +#define USB_TXICR_EP3ICR USB_TXICR_EP3ICR_MSK + +#define USB_TXICR_EP2ICR_POS 2U +#define USB_TXICR_EP2ICR_MSK BIT(USB_TXICR_EP2ICR_POS) +#define USB_TXICR_EP2ICR USB_TXICR_EP2ICR_MSK + +#define USB_TXICR_EP1ICR_POS 1U +#define USB_TXICR_EP1ICR_MSK BIT(USB_TXICR_EP1ICR_POS) +#define USB_TXICR_EP1ICR USB_TXICR_EP1ICR_MSK + +#define USB_TXICR_EP0ICR_POS 0U +#define USB_TXICR_EP0ICR_MSK BIT(USB_TXICR_EP0ICR_POS) +#define USB_TXICR_EP0ICR USB_TXICR_EP0ICR_MSK + +/****************** Bit definition for USB_RXICR register ************************/ + +#define USB_RXICR_EP6ICR_POS 6U +#define USB_RXICR_EP6ICR_MSK BIT(USB_RXICR_EP6ICR_POS) +#define USB_RXICR_EP6ICR USB_RXICR_EP6ICR_MSK + +#define USB_RXICR_EP5ICR_POS 5U +#define USB_RXICR_EP5ICR_MSK BIT(USB_RXICR_EP5ICR_POS) +#define USB_RXICR_EP5ICR USB_RXICR_EP5ICR_MSK + +#define USB_RXICR_EP4ICR_POS 4U +#define USB_RXICR_EP4ICR_MSK BIT(USB_RXICR_EP4ICR_POS) +#define USB_RXICR_EP4ICR USB_RXICR_EP4ICR_MSK + +#define USB_RXICR_EP3ICR_POS 3U +#define USB_RXICR_EP3ICR_MSK BIT(USB_RXICR_EP3ICR_POS) +#define USB_RXICR_EP3ICR USB_RXICR_EP3ICR_MSK + +#define USB_RXICR_EP2ICR_POS 2U +#define USB_RXICR_EP2ICR_MSK BIT(USB_RXICR_EP2ICR_POS) +#define USB_RXICR_EP2ICR USB_RXICR_EP2ICR_MSK + +#define USB_RXICR_EP1ICR_POS 1U +#define USB_RXICR_EP1ICR_MSK BIT(USB_RXICR_EP1ICR_POS) +#define USB_RXICR_EP1ICR USB_RXICR_EP1ICR_MSK + +/****************** Bit definition for USB_IER register ************************/ + +/* device/host mode */ +#define USB_IER_SESREQIE_POS 6U +#define USB_IER_SESREQIE_MSK BIT(USB_IER_SESREQIE_POS) +#define USB_IER_SESREQIE USB_IER_SESREQIE_MSK + +#define USB_IER_DISCONIE_POS 5U +#define USB_IER_DISCONIE_MSK BIT(USB_IER_DISCONIE_POS) +#define USB_IER_DISCONIE USB_IER_DISCONIE_MSK + +/* host mode */ +#define USB_IER_CONIE_POS 4U +#define USB_IER_CONIE_MSK BIT(USB_IER_CONIE_POS) +#define USB_IER_CONIE USB_IER_CONIE_MSK + +/* device/host mode */ +#define USB_IER_SOFIE_POS 3U +#define USB_IER_SOFIE_MSK BIT(USB_IER_SOFIE_POS) +#define USB_IER_SOFIE USB_IER_SOFIE_MSK + +/* device mode */ +#define USB_IER_RESTIE_POS 2U +#define USB_IER_RESTIE_MSK BIT(USB_IER_RESTIE_POS) +#define USB_IER_RESTIE USB_IER_RESTIE_MSK + +/* host mode */ +#define USB_IER_BABIE_POS 2U +#define USB_IER_BABIE_MSK BIT(USB_IER_BABIE_POS) +#define USB_IER_BABIE USB_IER_BABIE_MSK + +/* device/host mode */ +#define USB_IER_RESIE_POS 1U +#define USB_IER_RESIE_MSK BIT(USB_IER_RESIE_POS) +#define USB_IER_RESIE USB_IER_RESIE_MSK + +#define USB_IER_SUSPDIE_POS 0U +#define USB_IER_SUSPDIE_MSK BIT(USB_IER_SUSPDIE_POS) +#define USB_IER_SUSPDIE USB_IER_SUSPDIE_MSK + +/****************** Bit definition for USB_IDR register ************************/ + +/* device/host mode */ +#define USB_IDR_SESREQID_POS 6U +#define USB_IDR_SESREQID_MSK BIT(USB_IDR_SESREQID_POS) +#define USB_IDR_SESREQID USB_IDR_SESREQID_MSK + +#define USB_IDR_DISCONID_POS 5U +#define USB_IDR_DISCONID_MSK BIT(USB_IDR_DISCONID_POS) +#define USB_IDR_DISCONID USB_IDR_DISCONID_MSK + +/* host mode */ +#define USB_IDR_CONID_POS 4U +#define USB_IDR_CONID_MSK BIT(USB_IDR_CONID_POS) +#define USB_IDR_CONID USB_IDR_CONID_MSK + +/* device/host mode */ +#define USB_IDR_SOFID_POS 3U +#define USB_IDR_SOFID_MSK BIT(USB_IDR_SOFID_POS) +#define USB_IDR_SOFID USB_IDR_SOFID_MSK + +/* device mode */ +#define USB_IDR_RESTID_POS 2U +#define USB_IDR_RESTID_MSK BIT(USB_IDR_RESTID_POS) +#define USB_IDR_RESTID USB_IDR_RESTID_MSK + +/* host mode */ +#define USB_IDR_BABID_POS 2U +#define USB_IDR_BABID_MSK BIT(USB_IDR_BABID_POS) +#define USB_IDR_BABID USB_IDR_BABID_MSK + +/* device/host mode */ +#define USB_IDR_RESID_POS 1U +#define USB_IDR_RESID_MSK BIT(USB_IDR_RESID_POS) +#define USB_IDR_RESID USB_IDR_RESID_MSK + +#define USB_IDR_SUSPDID_POS 0U +#define USB_IDR_SUSPDID_MSK BIT(USB_IDR_SUSPDID_POS) +#define USB_IDR_SUSPDID USB_IDR_SUSPDID_MSK + +/****************** Bit definition for USB_IVS register ************************/ + +/* device/host mode */ +#define USB_IVS_SESREQIVS_POS 6U +#define USB_IVS_SESREQIVS_MSK BIT(USB_IVS_SESREQIVS_POS) +#define USB_IVS_SESREQIVS USB_IVS_SESREQIVS_MSK + +#define USB_IVS_DISCONIVS_POS 5U +#define USB_IVS_DISCONIVS_MSK BIT(USB_IVS_DISCONIVS_POS) +#define USB_IVS_DISCONIVS USB_IVS_DISCONIVS_MSK + +/* host mode */ +#define USB_IVS_CONIVS_POS 4U +#define USB_IVS_CONIVS_MSK BIT(USB_IVS_CONIVS_POS) +#define USB_IVS_CONIVS USB_IVS_CONIVS_MSK + +/* device/host mode */ +#define USB_IVS_SOFIVS_POS 3U +#define USB_IVS_SOFIVS_MSK BIT(USB_IVS_SOFIVS_POS) +#define USB_IVS_SOFIVS USB_IVS_SOFIVS_MSK + +/* device mode */ +#define USB_IVS_RESTIVS_POS 2U +#define USB_IVS_RESTIVS_MSK BIT(USB_IVS_RESTIVS_POS) +#define USB_IVS_RESTIVS USB_IVS_RESTIVS_MSK + +/* host mode */ +#define USB_IVS_BABIVS_POS 2U +#define USB_IVS_BABIVS_MSK BIT(USB_IVS_BABIVS_POS) +#define USB_IVS_BABIVS USB_IVS_BABIVS_MSK + +/* device/host mode */ +#define USB_IVS_RESIVS_POS 1U +#define USB_IVS_RESIVS_MSK BIT(USB_IVS_RESIVS_POS) +#define USB_IVS_RESIVS USB_IVS_RESIVS_MSK + +#define USB_IVS_SUSPDIVS_POS 0U +#define USB_IVS_SUSPDIVS_MSK BIT(USB_IVS_SUSPDIVS_POS) +#define USB_IVS_SUSPDIVS USB_IVS_SUSPDIVS_MSK + +/****************** Bit definition for USB_RIF register ************************/ + +/* device/host mode */ +#define USB_RIF_SESREQRIF_POS 6U +#define USB_RIF_SESREQRIF_MSK BIT(USB_RIF_SESREQRIF_POS) +#define USB_RIF_SESREQRIF USB_RIF_SESREQRIF_MSK + +#define USB_RIF_DISCONRIF_POS 5U +#define USB_RIF_DISCONRIF_MSK BIT(USB_RIF_DISCONRIF_POS) +#define USB_RIF_DISCONRIF USB_RIF_DISCONRIF_MSK + +/* host mode */ +#define USB_RIF_CONRIF_POS 4U +#define USB_RIF_CONRIF_MSK BIT(USB_RIF_CONRIF_POS) +#define USB_RIF_CONRIF USB_RIF_CONRIF_MSK + +/* device/host mode */ +#define USB_RIF_SOFRIF_POS 3U +#define USB_RIF_SOFRIF_MSK BIT(USB_RIF_SOFRIF_POS) +#define USB_RIF_SOFRIF USB_RIF_SOFRIF_MSK + +/* device mode */ +#define USB_RIF_RESTRIF_POS 2U +#define USB_RIF_RESTRIF_MSK BIT(USB_RIF_RESTRIF_POS) +#define USB_RIF_RESTRIF USB_RIF_RESTRIF_MSK + +/* host mode */ +#define USB_RIF_BABRIF_POS 2U +#define USB_RIF_BABRIF_MSK BIT(USB_RIF_BABRIF_POS) +#define USB_RIF_BABRIF USB_RIF_BABRIF_MSK + +/* device/host mode */ +#define USB_RIF_RESRIF_POS 1U +#define USB_RIF_RESRIF_MSK BIT(USB_RIF_RESRIF_POS) +#define USB_RIF_RESRIF USB_RIF_RESRIF_MSK + +#define USB_RIF_SUSPDRIF_POS 0U +#define USB_RIF_SUSPDRIF_MSK BIT(USB_RIF_SUSPDRIF_POS) +#define USB_RIF_SUSPDRIF USB_RIF_SUSPDRIF_MSK + +/****************** Bit definition for USB_IFM register ************************/ + +/* device/host mode */ +#define USB_IFM_SESREQIFM_POS 6U +#define USB_IFM_SESREQIFM_MSK BIT(USB_IFM_SESREQIFM_POS) +#define USB_IFM_SESREQIFM USB_IFM_SESREQIFM_MSK + +#define USB_IFM_DISCONIFM_POS 5U +#define USB_IFM_DISCONIFM_MSK BIT(USB_IFM_DISCONIFM_POS) +#define USB_IFM_DISCONIFM USB_IFM_DISCONIFM_MSK + +/* host mode */ +#define USB_IFM_CONIFM_POS 4U +#define USB_IFM_CONIFM_MSK BIT(USB_IFM_CONIFM_POS) +#define USB_IFM_CONIFM USB_IFM_CONIFM_MSK + +/* device/host mode */ +#define USB_IFM_SOFIFM_POS 3U +#define USB_IFM_SOFIFM_MSK BIT(USB_IFM_SOFIFM_POS) +#define USB_IFM_SOFIFM USB_IFM_SOFIFM_MSK + +/* device mode */ +#define USB_IFM_RESTIFM_POS 2U +#define USB_IFM_RESTIFM_MSK BIT(USB_IFM_RESTIFM_POS) +#define USB_IFM_RESTIFM USB_IFM_RESTIFM_MSK + +/* host mode */ +#define USB_IFM_BABIFM_POS 2U +#define USB_IFM_BABIFM_MSK BIT(USB_IFM_BABIFM_POS) +#define USB_IFM_BABIFM USB_IFM_BABIFM_MSK + +/* device/host mode */ +#define USB_IFM_RESIFM_POS 1U +#define USB_IFM_RESIFM_MSK BIT(USB_IFM_RESIFM_POS) +#define USB_IFM_RESIFM USB_IFM_RESIFM_MSK + +#define USB_IFM_SUSPDIFM_POS 0U +#define USB_IFM_SUSPDIFM_MSK BIT(USB_IFM_SUSPDIFM_POS) +#define USB_IFM_SUSPDIFM USB_IFM_SUSPDIFM_MSK + +/****************** Bit definition for USB_ICR register ************************/ + +/* device/host mode */ +#define USB_ICR_SESREQICR_POS 6U +#define USB_ICR_SESREQICR_MSK BIT(USB_ICR_SESREQICR_POS) +#define USB_ICR_SESREQICR USB_ICR_SESREQICR_MSK + +#define USB_ICR_DISCONICR_POS 5U +#define USB_ICR_DISCONICR_MSK BIT(USB_ICR_DISCONICR_POS) +#define USB_ICR_DISCONICR USB_ICR_DISCONICR_MSK + +/* host mode */ +#define USB_ICR_CONICR_POS 4U +#define USB_ICR_CONICR_MSK BIT(USB_ICR_CONICR_POS) +#define USB_ICR_CONICR USB_ICR_CONICR_MSK + +/* device/host mode */ +#define USB_ICR_SOFICR_POS 3U +#define USB_ICR_SOFICR_MSK BIT(USB_ICR_SOFICR_POS) +#define USB_ICR_SOFICR USB_ICR_SOFICR_MSK + +/* device mode */ +#define USB_ICR_RESTICR_POS 2U +#define USB_ICR_RESTICR_MSK BIT(USB_ICR_RESTICR_POS) +#define USB_ICR_RESTICR USB_ICR_RESTICR_MSK + +/* host mode */ +#define USB_ICR_BABICR_POS 2U +#define USB_ICR_BABICR_MSK BIT(USB_ICR_BABICR_POS) +#define USB_ICR_BABICR USB_ICR_BABICR_MSK + +/* device/host mode */ +#define USB_ICR_RESICR_POS 1U +#define USB_ICR_RESICR_MSK BIT(USB_ICR_RESICR_POS) +#define USB_ICR_RESICR USB_ICR_RESICR_MSK + +#define USB_ICR_SUSPDICR_POS 0U +#define USB_ICR_SUSPDICR_MSK BIT(USB_ICR_SUSPDICR_POS) +#define USB_ICR_SUSPDICR USB_ICR_SUSPDICR_MSK + +typedef struct +{ + __IO uint8_t FADDR ; //0x0000 Function address register. + __IO uint8_t POWER ; //0x0001 Power management register. + __IO uint8_t DPDMCON ; //0x0002 DP DM Control register. + __IO uint8_t SWCID ; //0x0003 Softwave CID register. + __IO uint8_t SWVBUS ; //0x0004 Softwave VBUS register. + __IO uint8_t TMODE ; //0x0005 Test Mode register. + __IO uint8_t RES002[6] ; //0x0006~0x0B, Reserved + __IO uint8_t FRAME1 ; //0x000C, Frame number bits 0 to 7. + __IO uint8_t FRAME2 ; //0x000D, Frame number bits 8 to 10. + __IO uint8_t INDEX ; //0x000E, Index register for selecting the endp + __IO uint8_t DEVCON ; //0x000F, USB device control register. + __IO uint8_t TXMAXP ; //0x0010, Peripheral mode - Maximum packet size + __IO uint8_t CSR0L_TXCSRL ;//0x0011, Peripheral mode - Control Status regi + __IO uint8_t CSR0H_TXCSRH ;//0x0012, Peripheral mode - Control Status regi + __IO uint8_t RXMAXP ; //0x0013, Peripheral mode - Maximum packet size + __IO uint8_t RXCSRL ; //0x0014, Peripheral mode - Control Status regi + __IO uint8_t RXCSRH ; //0x0015, Peripheral mode - Control Status regi + __IO uint8_t COUNT0_RX1 ; //0x0016, Peripheral mode - Number of bytes in + __IO uint8_t RXCOUNT2 ; //0x0017, Peripheral mode - Number of bytes in + __IO uint8_t TXTYPE ; //0x0018, Peripheral mode - // + __IO uint8_t NAKLIMIT0_TXINTERVAL ; //0x0019, Peripheral mode - // + __IO uint8_t RXTYPE ; //0x001A, Peripheral mode - // + __IO uint8_t RXINTERVAL ; //0x001B, Peripheral mode - // + __IO uint8_t TXFIFO1 ; //0x001C, Tx Endpoint FIFO details + __IO uint8_t TXFIFO2 ; //0x001D, Tx Endpoint FIFO details + __IO uint8_t RXFIFO1 ; //0x001E, Rx Endpoint FIFO details + __IO uint8_t RXFIFO2 ; //0x001F, Rx Endpoint FIFO details + __IO uint8_t EP0FIFO ; //0x0020, FIFOs for Endpoints 0. + __IO uint8_t RES021[3] ; //0x0021~0x23, Reserved + __IO uint8_t EP1FIFO ; //0x0024, FIFOs for Endpoints 1. + __IO uint8_t RES025[3] ; //0x0025~0x27, Reserved + __IO uint8_t EP2FIFO ; //0x0028, FIFOs for Endpoints 2. + __IO uint8_t RES029[3] ; //0x0029~0x2B, Reserved + __IO uint8_t EP3FIFO ; //0x002C, FIFOs for Endpoints 3. + __IO uint8_t RES02D[3] ; //0x002D~0x2F, Reserved + __IO uint8_t EP4FIFO ; //0x0030, FIFOs for Endpoints 4. + __IO uint8_t RES031[3] ; //0x0031~0x33, Reserved + __IO uint8_t EP5FIFO ; //0x0034, FIFOs for Endpoints 5. + __IO uint8_t RES035[3] ; //0x0035~0x37, Reserved + __IO uint8_t EP6FIFO ; //0x0038, FIFOs for Endpoints 6. + __IO uint8_t RES039[71] ; //0x0039~0x7C, Reserved + __IO uint8_t TXIER ; //0x0080, TX Endpoint 0~6 Interrupt Enable + __IO uint8_t RES081 ; //0x0081, Reserved + __IO uint8_t RXIER ; //0x0082, RX Endpoint 0~6 Interrupt Enable + __IO uint8_t RES083 ; //0x0083, Reserved + __IO uint8_t TXIDR ; //0x0084, TX Endpoint 0~6 Interrupt Disable + __IO uint8_t RES085 ; //0x0085, Reserved + __IO uint8_t RXIDR ; //0x0086, RX Endpoint 0~6 Interrupt Disable + __IO uint8_t RES087 ; //0x0087, Reserved + __IO uint8_t TXIVS ; //0x0088, TX Endpoint 0~6 Interrupt Valid Status + __IO uint8_t RES089 ; //0x0089, Reserved + __IO uint8_t RXIVS ; //0x008A, RX Endpoint 0~6 Interrupt Valid Status + __IO uint8_t RES08B ; //0x008B, Reserved + __IO uint8_t TXRIF ; //0x008C, TX Endpoint 0~6 Raw Interrupt Flag Status + __IO uint8_t RES08D ; //0x008D, Reserved + __IO uint8_t RXRIF ; //0x008E, RX Endpoint 0~6 Raw Interrupt Flag Status + __IO uint8_t RES08F ; //0x008F, Reserved + __IO uint8_t TXIFM ; //0x0090, TX Endpoint 0~6 Interrupt Flag Masked Status + __IO uint8_t RES091 ; //0x0091, Reserved + __IO uint8_t RXIFM ; //0x0092, RX Endpoint 0~6 Interrupt Flag Masked Status + __IO uint8_t RES093 ; //0x0093, Reserved + __IO uint8_t TXICR ; //0x0094, TX Endpoint 0~6 Interrupt Clear Register + __IO uint8_t RES095 ; //0x0095, Reserved + __IO uint8_t RXICR ; //0x0096, RX Endpoint 0~6 Interrupt Clear Register + __IO uint8_t RES097[9] ; //0x0097~0x9C, Reserved + __O uint32_t IER ; //0x00A0, USB Interrupt Enable Register + __O uint32_t IDR ; //0x00A4, USB Interrupt Disable Register + __I uint32_t IVS ; //0x00A8, USB Interrupt Valid Register + __I uint32_t RIF ; //0x00AC, USB Raw Interrupt Flag Status Register + __I uint32_t IFM ; //0x00B0, USB Interrupt Flag Masked Status + __O uint32_t ICR ; //0x00B4, USB Interrupt Clear Register +} USB_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/FS026/reg_wwdt.h b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_wwdt.h new file mode 100644 index 00000000000..368091e7a4a --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/FS026/reg_wwdt.h @@ -0,0 +1,115 @@ +/********************************************************************************** + * + * @file reg_wwdt.h + * @brief WWDT Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __WWDT_H__ +#define __WWDT_H__ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/* Support for anonymous structures and unions. */ +////#pragma anon_unions + +/****************** Bit definition for WWDT_CON register ************************/ + +# define WWDT_CON_WDGA_POS 7U +# define WWDT_CON_WDGA_MSK BIT(WWDT_CON_WDGA_POS) +# define WWDT_CON_WDGA WWDT_CON_WDGA_MSK + +# define WWDT_CON_T_POSS 0U +# define WWDT_CON_T_POSE 6U +# define WWDT_CON_T_MSK BITS(WWDT_CON_T_POSS, WWDT_CON_T_POSE) +# define WWDT_CON_T WWDT_CON_T_MSK + +/****************** Bit definition for WWDT_CFG register ************************/ + +# define WWDT_CFG_WDGTB_POSS 7U +# define WWDT_CFG_WDGTB_POSE 8U +# define WWDT_CFG_WDGTB_MSK BITS(WWDT_CFG_WDGTB_POSS, WWDT_CFG_WDGTB_POSE) +# define WWDT_CFG_WDGTB WWDT_CFG_WDGTB_MSK + +# define WWDT_CFG_W_POSS 0U +# define WWDT_CFG_W_POSE 6U +# define WWDT_CFG_W_MSK BITS(WWDT_CFG_W_POSS, WWDT_CFG_W_POSE) +# define WWDT_CFG_W WWDT_CFG_W_MSK + +/****************** Bit definition for WWDT_IER register ************************/ + +# define WWDT_IER_EWI_POS 0U +# define WWDT_IER_EWI_MSK BIT(WWDT_IER_EWI_POS) +# define WWDT_IER_EWI WWDT_IER_EWI_MSK + +/****************** Bit definition for WWDT_IDR register ************************/ + +# define WWDT_IDR_EWI_POS 0U +# define WWDT_IDR_EWI_MSK BIT(WWDT_IDR_EWI_POS) +# define WWDT_IDR_EWI WWDT_IDR_EWI_MSK + +/****************** Bit definition for WWDT_IVS register ************************/ + +# define WWDT_IVS_EWI_POS 0U +# define WWDT_IVS_EWI_MSK BIT(WWDT_IVS_EWI_POS) +# define WWDT_IVS_EWI WWDT_IVS_EWI_MSK + +/****************** Bit definition for WWDT_RIF register ************************/ + +# define WWDT_RIF_EWI_POS 0U +# define WWDT_RIF_EWI_MSK BIT(WWDT_RIF_EWI_POS) +# define WWDT_RIF_EWI WWDT_RIF_EWI_MSK + +/****************** Bit definition for WWDT_IFM register ************************/ + +# define WWDT_IFM_EWI_POS 0U +# define WWDT_IFM_EWI_MSK BIT(WWDT_IFM_EWI_POS) +# define WWDT_IFM_EWI WWDT_IFM_EWI_MSK + +/****************** Bit definition for WWDT_ICR register ************************/ + +# define WWDT_ICR_EWI_POS 0U +# define WWDT_ICR_EWI_MSK BIT(WWDT_ICR_EWI_POS) +# define WWDT_ICR_EWI WWDT_ICR_EWI_MSK + +typedef struct +{ + __IO uint32_t CON; // 0x000 + __IO uint32_t CFG; // 0x004 + __O uint32_t IER; // 0x008 + __O uint32_t IDR; // 0x00c + __I uint32_t IVS; // 0x010 + __I uint32_t RIF; // 0x014 + __I uint32_t IFM; // 0x018 + __O uint32_t ICR; // 0x01c +} WWDT_TypeDef; + + +#endif diff --git a/os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.c b/os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.c new file mode 100644 index 00000000000..1a9cf0035a7 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.c @@ -0,0 +1,1658 @@ +/** + ********************************************************************************* + * + * @file ald_usb.c + * @brief USB module driver. + * + * @version V1.0 + * @date 25 Feb 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Feb 2022 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_usb.h" + +/** @addtogroup FS026_ALD + * @{ + */ + +/** @defgroup USB USB + * @brief USB module driver + * @{ + */ +#if 1//def ALD_USB +/** + * @defgroup USB_Public_Functions USB Public Function + * @{ + */ +/** @defgroup USB_Public_Functions_Group1 Base functions + * @brief Base functions + * @{ + */ + +/** + * @brief Gets the number of current frame. + * @retval Number of the frame. + */ +uint32_t ald_usb_frame_number_get(void) +{ + uint8_t framel = (uint8_t)USB->FRAME1; + uint8_t frameh = (uint8_t)USB->FRAME2; + return ((uint32_t)(framel & 0xFF) + ((uint32_t)(frameh & 0xFF) << 8)); +} + +/** + * @brief Request the session. + * @param start: true/false. + * @retval None + */ +void ald_usb_otg_session_request(bool start) +{ + if (start) + USB->DEVCON |= (uint8_t)ALD_USB_DEVCON_SESSION; + else + USB->DEVCON &= (uint8_t)(~(ALD_USB_DEVCON_SESSION)); + + return; +} + +/** + * @brief Gets the mode. + * @retval Mode + */ +uint32_t ald_usb_mode_get(void) +{ + return (USB->DEVCON & ((uint8_t)(ALD_USB_DEVCON_HOST | ALD_USB_DEVCON_SESSION))); +} + +/** + * @brief Start host require. + * @retval Mode + */ +uint32_t ald_usb_mode_host_req(void) +{ + USB->DEVCON |= (uint8_t)ALD_USB_DEVCON_HOSTREQ; + return 0; +} + +/** + * @brief Clear host require. + * @retval Mode + */ +uint32_t ald_usb_mode_host_req_clear(void) +{ + USB->DEVCON &= (uint8_t)(~ALD_USB_DEVCON_HOSTREQ); + return 0; +} + +/** + * @brief Enable/Disable the high mode. + * @param enable: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_high_speed_enable(bool enable) +{ + assert_param(enable == DISABLE); + + return; +} + +/** + * @brief Gets the speed of the device. + * @retval Type of the speed. + */ +uint32_t ald_usb_device_speed_get(void) +{ + return ALD_USB_FULL_SPEED; +} + +/** + * @brief Gets the number of the endpoint. + * @retval Number of the endpoint. + */ +uint32_t ald_usb_num_ep_get( void) +{ + return ALD_NUM_USB_EP; +} + +/** + * @brief Reset USB Control. + * @retval None + */ +void ald_usb_control_reset(void) +{ + //ALD_RCU_USB_RESET_ENABLE(); + + return; +} + +/** + * @brief Output USB clock, not support. + * @retval None + */ +void ald_usb_clock_output(void) +{ + return; +} + +/** + * @brief Starts eye diagram for high-speed host, not support. + * @param buf: Buffer for eye diagram. + * @param len: Length of the buffer. + * @retval Status, 0 means success, other values means failure. + */ +int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len) +{ + return 0; +} + +/** + * @brief Pull up or pull down USB dp line. + * @param pupd: USB_DPDM_FLOATING/USB_DPDM_PUSH_UP/USB_DPDM_PUSH_DOWN. + * @retval None + */ +void ald_usb_dppud_set(ald_dpdm_push_t pupd) +{ + USB->DPDMCON &= (uint8_t)(~USB_DPDMCON_DPPUD_MSK); + USB->DPDMCON |= (uint8_t)(pupd << USB_DPDMCON_DPPUD_POSS); + return; +} + +/** + * @brief Pull up or pull down USB dm line. + * @param pupd: USB_DPDM_FLOATING/USB_DPDM_PUSH_UP/USB_DPDM_PUSH_DOWN. + * @retval None + */ +void ald_usb_dmpud_set(ald_dpdm_push_t pupd) +{ + USB->DPDMCON &= (uint8_t)(~USB_DPDMCON_DMPUD_MSK); + USB->DPDMCON |= (uint8_t)(pupd << USB_DPDMCON_DMPUD_POSS); + return; +} + +/** + * @brief Switch usb mode by software. + * @param host: 0, indicates that software force to host + host: 1, indicates that software force to device. + * @retval None + */ +void ald_usb_swcid_host(uint8_t host) +{ + if (host) + USB->SWCID |= (uint8_t)(USB_SWCID_HOST_MSK); + else + USB->SWCID &= (uint8_t)(~USB_SWCID_HOST_MSK); + return; +} + +/** + * @brief Switch the control method of CID. + * @param cid: 0, indicates that use the hardware control + cid: 1, indicates that use the software control. + * @retval None + */ +void ald_usb_swcid_cidctrl(uint8_t cid) +{ + if (cid) + USB->SWCID |= (uint8_t)(ALD_USB_SWCID_CIDCTRL); + else + USB->SWCID &= (uint8_t)(~ALD_USB_SWCID_CIDCTRL); + return; +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group2 Device functions + * @brief Device functions + * @{ + */ + +/** + * @brief Gets the address. + * @retval Address. + */ +uint8_t ald_usb_dev_get_addr(void) +{ + return (USB->FADDR); +} + +/** + * @brief Sets the address. + * @param addr: The address which will be set. + * @retval None + */ +void ald_usb_dev_set_addr(uint8_t addr) +{ + USB->FADDR = addr; + return; +} + +/** + * @brief Enable connection. + * @retval None + */ +void ald_usb_dev_connect(void) +{ + USB->DPDMCON |= (uint8_t)(ALD_USB_DPDMCON_PHYPWREN); + return; +} + +/** + * @brief Disable connection. + * @retval None + */ +void ald_usb_dev_disconnect(void) +{ + USB->DPDMCON &= (uint8_t)(~(ALD_USB_DPDMCON_PHYPWREN)); + return; +} + +/** + * @brief Enable the devices suspend. + * @retval None + */ +void ald_usb_dev_suspend_enable(void) +{ + USB->POWER |= (uint8_t)USB_POWER_SUSPENDEN_MSK; + return; +} + +/** + * @brief Configure the endpoint in device mode. + * @param ep_idx: Index of the endpoint + * @param p_max: Size of the maximum package. + * @param flags: Flags of the endpoint. + * @retval None + */ +void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags) +{ + uint32_t tmp = 0U; + + USB->INDEX = (uint8_t)ep_idx; + + if (flags & ALD_USB_EP_DEV_IN) { + USB->TXMAXP = (uint8_t)(p_max); + if (flags & ALD_USB_EP_AUTO_SET) + tmp |= USB_TXCSRH_AUTOSET_MSK; + if ((flags & ALD_USB_EP_MODE_MASK) == ALD_USB_EP_MODE_ISOC) + tmp |= USB_TXCSRH_ISO_MSK; + + USB->CSR0H_TXCSRH |= (uint8_t)tmp; + USB->CSR0L_TXCSRL |= (uint8_t)USB_TXCSRL_CLRDT_MSK; + } + else { + USB->RXMAXP = (uint8_t)(p_max); + if (flags & ALD_USB_EP_AUTO_CLEAR) + tmp |= USB_RXCSRH_AUTOCLR_MSK; + if ((flags & ALD_USB_EP_MODE_MASK) == ALD_USB_EP_MODE_ISOC) + tmp |= USB_TXCSRH_ISO_MSK; + + USB->RXCSRH |= (uint8_t)tmp; + USB->RXCSRL |= (uint8_t)USB_RXCSRL_CLRDT_MSK; + } + + return; +} + +/** + * @brief Gets the parameters of the endpoint. + * @param ep_idx: Index of the endpoint + * @param p_max: Size of the maximum package. + * @param flags: Flags of the endpoint. + * @retval None + */ +void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags) +{ + uint32_t tmp; + + USB->INDEX = (uint8_t)ep_idx; + + if (*flags & ALD_USB_EP_DEV_IN) { + *flags = ALD_USB_EP_DEV_IN; + *p_max = (uint32_t)USB->TXMAXP; + tmp = (uint32_t)USB->CSR0H_TXCSRH; + if (tmp & USB_TXCSRH_AUTOSET_MSK) + *flags |= ALD_USB_EP_AUTO_SET; + if (tmp & USB_TXCSRH_ISO_MSK) + *flags |= ALD_USB_EP_MODE_ISOC; + else + *flags |= ALD_USB_EP_MODE_BULK; + } + else { + *flags = ALD_USB_EP_DEV_OUT; + *p_max = (uint32_t)USB->RXMAXP; + tmp = (uint32_t)USB->RXCSRH; + + if (tmp & USB_RXCSRH_AUTOCLR_MSK) + *flags |= ALD_USB_EP_AUTO_CLEAR; + if (tmp & USB_RXCSRH_ISO_MSK) + *flags |= ALD_USB_EP_MODE_ISOC; + else + *flags |= ALD_USB_EP_MODE_BULK; + } + return; +} +extern void printf_e(const char *fmt, ...); +/** + * @brief Acknowledge the data from host. + * @param ep_idx: Index of the endpoint + * @param last: true/false + * @retval None + */ +void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL |= (uint8_t)(USB_CSR0L_RXRDYC_MSK | (last ? USB_CSR0L_DATAEND_MSK : 0)); + else + USB->RXCSRL &= (uint8_t)(~USB_RXCSRL_RXRDY_MSK); + + return; +} + +/** + * @brief Stall the endpoint. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL |= (uint8_t)(USB_CSR0L_RXRDYC_MSK | USB_CSR0L_STALL_MSK); + else if (flags == ALD_USB_EP_DEV_IN) + USB->CSR0L_TXCSRL |= (uint8_t)USB_TXCSRL_STALL_MSK; + else + USB->RXCSRL |= (uint8_t)USB_RXCSRL_STALL_MSK; + + return; +} + +/** + * @brief Cancel the stall status. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL &= (uint8_t)(~USB_CSR0L_STALLED_MSK); + else if (flags == ALD_USB_EP_DEV_IN){ + USB->CSR0L_TXCSRL &= (uint8_t)(~(USB_TXCSRL_STALL_MSK | USB_TXCSRL_STALLED_MSK)); + USB->CSR0L_TXCSRL |= (uint8_t)USB_TXCSRL_CLRDT_MSK; + } + else{ + USB->RXCSRL &= (uint8_t)(~(USB_RXCSRL_STALL_MSK | USB_RXCSRL_STALLED_MSK)); + USB->RXCSRL |= (uint8_t)USB_RXCSRL_CLRDT_MSK; + } + + return; +} + +/** + * @brief Clear the status of the endpoint. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if (flags & ALD_USB_DEV_EP0_OUT_PKTRDY) + USB->CSR0L_TXCSRL |= (uint8_t)USB_CSR0L_RXRDYC_MSK; + if (flags & ALD_USB_DEV_EP0_SETUP_END) + USB->CSR0L_TXCSRL |= (uint8_t)USB_CSR0L_SETENDC_MSK; + if (flags & ALD_USB_DEV_EP0_SENT_STALL) + USB->CSR0L_TXCSRL &= (uint8_t)(~USB_CSR0L_STALLED_MSK); + } + else { + USB->CSR0L_TXCSRL &= (uint8_t)(~(flags & (ALD_USB_DEV_TX_SENT_STALL | ALD_USB_DEV_TX_UNDERRUN))); + USB->RXCSRL &= (uint8_t)(~((flags & (ALD_USB_DEV_RX_SENT_STALL | ALD_USB_DEV_RX_DATA_ERROR + | ALD_USB_DEV_RX_OVERRUN)) >> ALD_USB_RX_EPSTATUS_SHIFT)); + } + + return; +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group3 Host functions + * @brief Host functions + * @{ + */ +/** + * @brief Gets the device's address. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval Address + */ +uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + return (USB->FADDR); +} + +/** + * @brief Sets the device's address. + * @param ep_idx: Index of the endpoint. + * @param addr: The device's address. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + USB->FADDR = (uint8_t)addr; + + return; +} + +/** + * @brief Configure the endpoint in host mode. + * @param ep_idx: Index of the endpoint. + * @param p_max: Size of the maximum package. + * @param nak_val: Value of the nack. + * @param t_ep: Target endpoint. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags) +{ + uint32_t tmp = 0U; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + USB->NAKLIMIT0_TXINTERVAL = (uint8_t)nak_val; + + if (flags & ALD_USB_EP_SPEED_HIGH) + ; + else if (flags & ALD_USB_EP_SPEED_FULL) + ; + else + ; + } + else { + tmp = t_ep; + + if (flags & ALD_USB_EP_SPEED_HIGH) + ; + else if (flags & ALD_USB_EP_SPEED_FULL) + ; + else + ; + + switch (flags & ALD_USB_EP_MODE_MASK) { + case ALD_USB_EP_MODE_BULK: + tmp |= ALD_USB_TXTYPE1_PROTO_BULK; + break; + + case ALD_USB_EP_MODE_ISOC: + tmp |= ALD_USB_TXTYPE1_PROTO_ISOC; + break; + + case ALD_USB_EP_MODE_INT: + tmp |= ALD_USB_TXTYPE1_PROTO_INT; + break; + + case ALD_USB_EP_MODE_CTRL: + tmp |= ALD_USB_TXTYPE1_PROTO_CTRL; + break; + } + + if (flags & ALD_USB_EP_HOST_OUT) { + USB->TXTYPE = (uint8_t)tmp; + USB->NAKLIMIT0_TXINTERVAL = (uint8_t)nak_val; + USB->TXMAXP = (uint8_t)p_max; + + tmp = 0; + if (flags & ALD_USB_EP_AUTO_SET) + tmp = (uint8_t)ALD_USB_TXCSRH_AUTOSET; + USB->CSR0H_TXCSRH |= (uint8_t)tmp; + } + else { + USB->RXTYPE = (uint8_t)tmp; + USB->RXINTERVAL = (uint8_t)nak_val; + USB->RXMAXP = (uint8_t)p_max; + + tmp = 0; + if (flags & ALD_USB_EP_AUTO_CLEAR) + tmp |= (uint8_t)USB_RXCSRH_AUTOCLR_MSK; + if (flags & ALD_USB_EP_AUTO_REQUEST) + tmp |= (uint8_t)USB_RXCSRH_AUTOREQ_MSK; + + USB->RXCSRH |= (uint8_t)tmp; + } + } + + return; +} + +/** + * @brief Acknowledge the data in host mode. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_ep_data_ack(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL &= (uint8_t)(~(USB_CSR0L_RXRDY_MSK)); + else + USB->RXCSRL &= (uint8_t)(~(USB_RXCSRL_RXRDY_MSK)); + + return; +} + +/** + * @brief Toggle the data in host mode. + * The function is used to force the state of the data toggle in host mode. + * If the value passed in the bDataToggle parameter is false, then the data + * toggle is set to the DATA0 state, and if it is true it is set to the DATA1 + * state. + * @param ep_idx: Index of the endpoint. + * @param toggle: true/false. + * @param flags: can be USB_EP_HOST_IN or USB_EP_HOST_OUT. + * @retval None + */ +void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags) +{ + /* not supported by es32f0271. */ + return; +} + +/** + * @brief Clear the status of endpoint in host mode. + * @param ep_idx: Index of the endpoint. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + USB->CSR0L_TXCSRL &= (uint8_t)(~flags & 0xFF); + } + else { + USB->CSR0L_TXCSRL &= (uint8_t)(~flags & 0xFF); + USB->RXCSRL &= (uint8_t)(~(flags >> 16) & 0xFF); + } + + return; +} + +/** + * @brief Gets the HUB's address. + * @param ep_idx: Index of the endpoint. + * @param flags: Flags. + * @retval Address + */ +uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags) +{ + /* not supported by es32f0271. */ + return 0; +} + +/** + * @brief Sets the HUB's address. + * @param ep_idx: Index of the endpoint. + * @param addr: HUB's address which will be set. + * @param flags: Flags. + * @retval Address + */ +void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags) +{ + /* not supported by es32f0271. */ + return; +} + +/** + * @brief Disable power. + * @retval None + */ +void ald_usb_host_pwr_disable(void) +{ + USB->DPDMCON &= (uint8_t)(~(ALD_USB_DPDMCON_PHYPWREN)); + return; +} + +/** + * @brief Enable power. + * @retval None + */ +void ald_usb_host_pwr_enable(void) +{ + USB->DPDMCON |= (uint8_t)(ALD_USB_DPDMCON_PHYPWREN); + return; +} + +/** + * @brief Configure power in host mode. + * @param flags: Flags + * @retval None + */ +void ald_usb_host_pwr_config(uint32_t flags) +{ + return; +} + +/** + * @brief Disable the fault parameters of the power. + * @retval None + */ +void ald_usb_host_pwr_fault_disable(void) +{ + return; +} + +/** + * @brief Enable the fault parameters of the power. + * @retval None + */ +void ald_usb_host_pwr_fault_enable(void) +{ + return; +} + +/** + * @brief Request data IN(from device to host) + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_request_in(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL |= (uint8_t)USB_CSR0L_REQPKT_MSK; + else + USB->RXCSRL |= (uint8_t)USB_RXCSRL_REQPKT_MSK; + + return; +} + +/** + * @brief Clear the status of request IN. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_request_in_clear(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL &= (uint8_t)(~USB_CSR0L_REQPKT_MSK); + else + USB->RXCSRL &= (uint8_t)(~USB_RXCSRL_REQPKT_MSK); + + return; +} + +/** + * @brief Set the request for a status IN transaction. + * @retval None + */ +void ald_usb_host_request_status(void) +{ + USB->CSR0L_TXCSRL |= (uint8_t)(ALD_USB_CSR0L_REQPKT | ALD_USB_CSR0L_STATUSPKT); + + return; +} + +/** + * @brief Reset the USB's bus. + * @param start: true/false. + * @retval None + */ +void ald_usb_host_reset(bool start) +{ + if (start) + USB->POWER |= ALD_USB_POWER_RESET; + else + USB->POWER &= ~(ALD_USB_POWER_RESET); + + return; +} + +/** + * @brief Resume the devices. + * @param start: true/false. + * @retval None + */ +void ald_usb_host_resume(bool start) +{ + if (start) + USB->POWER |= (uint8_t)USB_POWER_RESUME_MSK; + else + USB->POWER &= (uint8_t)(~(ALD_USB_POWER_RESUME)); + + return; +} + +/** + * @brief Suspend the devices. + * @retval None + */ +void ald_usb_host_suspend(void) +{ + USB->POWER |= (uint8_t)USB_POWER_SUSPEND_MSK; + return; +} + +/** + * @brief Gets the device's speed. + * @retval Type of the speed. + */ +uint32_t ald_usb_host_speed_get(void) +{ + if (USB->DEVCON & ALD_USB_DEVCON_FSDEV) + return ALD_USB_FULL_SPEED; + + if (USB->DEVCON & ALD_USB_DEVCON_LSDEV) + return ALD_USB_LOW_SPEED; + + return ALD_USB_UNDEF_SPEED; +} + +/** + * @brief Sets the endpoint speed. + * @param ep_idx: Index of the endpoint. + * @param flags: Type of the speed. + * @retval None + */ +void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags) +{ + /* not support in F0271 */ + return; +} + +/** + * @brief Ping the endpoint. + * @param ep_idx: Index of the endpoint. + * @param enable: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable) +{ + /* not support in F0271 */ + return; +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group4 Endpoint functions + * @brief Endpoint functions + * @{ + */ +/** + * @brief Gets the size of the available data. + * @param ep_idx: Index of the endpoint + * @retval Size in bytes. + */ +uint32_t ald_usb_ep_data_avail(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if ((USB->CSR0L_TXCSRL & ALD_USB_CSR0L_RXRDY) == 0){ + return 0; + } + + return USB->COUNT0_RX1; + } + else { + if ((USB->RXCSRL & ALD_USB_CSR0L_RXRDY) == 0) + { + return 0; + } + + return (USB->COUNT0_RX1 + (((uint32_t)USB->RXCOUNT2) << 8)); + } +} + +/** + * @brief Gets the data from FIFO. + * @param ep_idx: Index of the endpoint + * @param data: Pointer to the buffer. + * @param size: Size of the data. + * @retval Status. + */ +int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size) +{ + uint32_t i, rx_fifo_addr; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if ((USB->CSR0L_TXCSRL & ALD_USB_CSR0L_RXRDY) == 0) { + *size = 0; + return -1; + } + i = USB->COUNT0_RX1; + } + else { + if ((USB->RXCSRL & ALD_USB_CSR0L_RXRDY) == 0) { + *size = 0; + return -1; + } + i = USB->COUNT0_RX1 + (((uint32_t)USB->RXCOUNT2) << 8); + } + + i = (i < *size) ? i : *size; + *size = i; + + rx_fifo_addr = (uint32_t)(&USB->EP0FIFO) + 4 * ep_idx; + + for (; i > 0; i--) + *data++ = *(volatile uint8_t *)(rx_fifo_addr); + + return 0; +} + +/** + * @brief Puts data to the FIFO. + * @param ep_idx: Index of the endpoint + * @param data: Pointer to the data. + * @param size: Size of the data. + * @retval Status. + */ +int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size) +{ + uint32_t tx_fifo_addr; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if (USB->CSR0L_TXCSRL & ALD_USB_CSR0L_TXRDY) + return -1; + } + else { + if (USB->CSR0L_TXCSRL & ALD_USB_TXCSRL_TXRDY) + return -1; + } + + tx_fifo_addr = (uint32_t)(&USB->EP0FIFO) + 4 * ep_idx; + + for (; size > 0; size--) + *(volatile uint8_t *)tx_fifo_addr = *data++; + + return 0; +} + +/** + * @brief Send data. + * @param ep_idx: Index of the endpoint + * @param tx_type: Type. + * @retval Status. + */ +int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type) +{ + uint32_t tmp; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if (USB->CSR0L_TXCSRL & ALD_USB_CSR0L_TXRDY) + return -1; + + tmp = tx_type & 0xFF; + } + else { + if (USB->CSR0L_TXCSRL & ALD_USB_TXCSRL_TXRDY) + return -1; + + tmp = (tx_type >> 8) & 0xff; + } + + USB->CSR0L_TXCSRL = tmp; + + return 0; +} + +/** + * @brief Clear the status of the toggle. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) + USB->CSR0L_TXCSRL |= (uint8_t)ALD_USB_TXCSRL_CLRDT; + else + USB->RXCSRL |= (uint8_t)ALD_USB_RXCSRL_CLRDT; + + return; +} + +/** + * @brief Sets the size of request data IN + * @param ep_idx: Index of the endpoint + * @param count: Size of request data IN. + * @retval None + */ +void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count) +{ + /* not support in f0271 */ + return; +} + +/** + * @brief Gets the status of the endpoint. + * @param ep_idx: Index of the endpoint + * @retval Status. + */ +uint32_t ald_usb_ep_status(uint32_t ep_idx) +{ + uint32_t status; + + USB->INDEX = (uint8_t)ep_idx; + + status = (ep_idx == ALD_USB_EP_0) ? (USB->CSR0L_TXCSRL): (USB->CSR0L_TXCSRL | (USB->RXCSRL << 16)); + + return status; +} + +/** + * @brief Configure the endpoint in DMA mode. + * @param ep_idx: Index of the endpoint + * @param flag: Flags. + * @param en: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, TypeFunc en) +{ + /* Not supported in F0271 */ + + return; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group5 FIFO functions + * @brief FIFO functions + * @{ + */ +/** + * @brief Gets the address of the FIFO. + * @param ep_idx: Index of the endpoint + * @retval Address + */ +uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx) +{ + /* Not supported in F0271 */ + + return 0; +} + +/** + * @brief Gets the parameters of the FIFO. + * @param ep_idx: Index of the endpoint + * @param addr: Address. + * @param size: Size of FIFO. + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags) +{ + USB->INDEX = ep_idx; + + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) { + *addr = ((uint32_t)USB->TXFIFO1 | ((uint32_t)USB->TXFIFO2 & 0x03)) << 3; + *size = ((USB->TXFIFO2 & ALD_USB_TXFIFO2_DPB) == 0x00) ? (USB->TXFIFO2 & ALD_USB_TXFIFO2_MAXPKTSIZE_1024) : (2 * (USB->TXFIFO2 & ALD_USB_TXFIFO2_MAXPKTSIZE_1024)); + } + else { + *addr = ((uint32_t)USB->RXFIFO1 | ((uint32_t)USB->RXFIFO2 & 0x03)) << 3; + *size = ((USB->RXFIFO2 & ALD_USB_RXFIFO2_DPB) == 0x00) ? (USB->RXFIFO2 & ALD_USB_RXFIFO2_MAXPKTSIZE_1024) : (2 * (USB->RXFIFO2 & ALD_USB_RXFIFO2_MAXPKTSIZE_1024)); + } + + return; +} + +/** + * @brief Sets the parameters of the FIFO. + * @param ep_idx: Index of the endpoint + * @param addr: Address. + * @param size: Size of FIFO, valid parameter has defined in usb_lowlayer_api.h. + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags) +{ + USB->INDEX = ep_idx; + + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) { + USB->TXFIFO1 = (uint8_t)((addr >> 3) & 0xFF); + USB->TXFIFO2 |= (uint8_t)(((addr >> 3) >> 8) & 0x0F); + + USB->TXFIFO2 |= (uint8_t)(size << USB_TXFIFO2_MAXPKTSIZE_POSS); + + USB->CSR0L_TXCSRL |= (uint8_t)ALD_USB_TXCSRL_FLUSH; + } + else { + USB->RXFIFO1 = (uint8_t)((addr >> 3) & 0xFF); + USB->RXFIFO2 |= (uint8_t)(((addr >> 3) >> 8) & 0x0F); + + USB->RXFIFO2 |= (uint8_t)(size << USB_RXFIFO2_MAXPKTSIZE_POSS); + + USB->RXCSRL |= (uint8_t)ALD_USB_RXCSRL_FLUSH; + } + + return; +} + +/** + * @brief Flush the FIFO + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = ep_idx; + + if (ep_idx == ALD_USB_EP_0) { + if ((USB->CSR0L_TXCSRL & (ALD_USB_CSR0L_RXRDY | ALD_USB_CSR0L_TXRDY)) != 0) + USB->CSR0H_TXCSRH |= ALD_USB_CSR0H_FLUSH; + } + else { + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) { + if (USB->CSR0L_TXCSRL & ALD_USB_TXCSRL_TXRDY) + USB->CSR0L_TXCSRL |= ALD_USB_TXCSRL_FLUSH; + } + else { + if (USB->RXCSRL & ALD_USB_RXCSRL_RXRDY) + USB->RXCSRL |= ALD_USB_RXCSRL_FLUSH; + } + } + return; +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group6 Interrupt functions + * @brief Interrupt functions + * @{ + */ +/** + * @brief Disable interrupt. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_disable(uint32_t flags) +{ + if (flags & ALD_USB_IDR_STATUS) + USB->IDR |= (uint8_t)(flags & ALD_USB_IDR_STATUS); + + return; +} + +/** + * @brief Enable interrupt. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_enable(uint32_t flags) +{ + if (flags & ALD_USB_IER_STATUS) + USB->IER |= (uint8_t)(flags & ALD_USB_IER_STATUS); + + return; +} + +/** + * @brief Gets the status of the interrupt. + * @retval Status. + */ +uint32_t ald_usb_int_status_get(void) +{ + uint32_t Status; + + Status = USB->IFM & 0x7F; + USB->ICR |= Status; + + return Status; +} + +/** + * @brief Disable interrupt of the endpoint. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_disable_ep(uint32_t flags) +{ + USB->TXIDR |= (uint8_t)(flags & (ALD_USB_INTEP_HOST_OUT | ALD_USB_INTEP_DEV_IN | ALD_USB_INTEP_0)); + USB->RXIDR |= (uint8_t)((flags & (ALD_USB_INTEP_HOST_IN | ALD_USB_INTEP_DEV_OUT)) >> ALD_USB_INTEP_RX_SHIFT); + return; +} + +/** + * @brief Enable interrupt of the endpoint. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_enable_ep(uint32_t flags) +{ + USB->TXIER |= (uint8_t)(flags & (ALD_USB_INTEP_HOST_OUT | ALD_USB_INTEP_DEV_IN | ALD_USB_INTEP_0)); + USB->RXIER |= (uint8_t)((flags & (ALD_USB_INTEP_HOST_IN | ALD_USB_INTEP_DEV_OUT)) >> ALD_USB_INTEP_RX_SHIFT); + return; +} + +/** + * @brief Gets the ststus of the endpoint interrupt. + * @retval Status. + */ +uint32_t ald_usb_int_status_ep_get(void) +{ + uint32_t status; + + status = USB->TXIFM; + status |= (USB->RXIFM << ALD_USB_INTEP_RX_SHIFT); + + USB->TXICR |= (uint8_t)(status & 0xFF); + USB->RXICR |= (uint8_t)((status >> ALD_USB_INTEP_RX_SHIFT) & 0xFF); + + return status; +} + +/** + * @brief Register USB's interrupt. + * @retval None + */ +void ald_usb_int_register(void) +{ + //ald_mcu_irq_config(USB_IRQn, 2, ENABLE); + NVIC_SetPriority(USB_IRQn, 3); + NVIC_EnableIRQ(USB_IRQn); + return; +} + +/** + * @brief Unregister USB's interrupt. + * @retval None + */ +void ald_usb_int_unregister(void) +{ + //ald_mcu_irq_config(USB_IRQn, 2, DISABLE); + NVIC_DisableIRQ(USB_IRQn); + return; +} + +/** + * @brief Get USB's interrupt number. + * @retval None + */ +uint32_t ald_usb_int_num_get(void) +{ + return USB_IRQn; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group7 DMA functions + * @brief DMA functions + * @{ + */ +#if defined(__ALD_MDA_H__) +/** + * @brief Configure DMA's channel. + * @param ch: Channel. + * @param addr: Address. + * @param count: Size of the data to be moved. + * @param ctrl: Parameters of the DMA's controler + * @retval None + */ +void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl) +{ + return; +} + +/** + * @brief Start multiple receive. + * @param ep_idx: Index of the endpoint + * @retval None + */ +void ald_usb_dma_mult_recv_start(uint32_t ep_idx) +{ + return; +} + +/** + * @brief Start DMA's machine. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_channel_start(uint8_t ch) +{ + return; +} + +/** + * @brief Stop DMA's machine. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_channel_stop(uint8_t ch) +{ + return; +} + +/** + * @brief Gets flags of the interrupt. + * @retval Flags of the interrupt. + */ +uint32_t ald_usb_dma_get_interrupt_flag(void) +{ + return; +} + +/** + * @brief Gets the status of the error. + * @param ch: Channel. + * @retval Status. + */ +uint32_t ald_usb_dma_get_channel_error(uint8_t ch) +{ + return 0; +} + +/** + * @brief Clear the status of the error. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_clear_channel_error(uint8_t ch) +{ + return; +} + +#endif +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group8 LPM functions + * @brief LPM functions + * @{ + */ +/** + * @brief Gets status of remote wakeup. + * @retval Status. + */ +uint32_t ald_usb_lpm_remote_wake_is_enable(void) +{ + return 1; +} + +/** + * @brief Gets the link status + * @retval Status + */ +uint32_t ald_usb_lpm_link_status_get(void) +{ + return 0; +} + +/** + * @brief Gets the index of the endpoint. + * @retval Index of the endpoint. + */ +uint32_t ald_usb_lpm_ep_get(void) +{ + return 0; +} + +/** + * @brief Gets the status of the interrupt. + * @retval Status. + */ +uint32_t ald_usb_lpm_int_status_get(void) +{ + return 0; +} + +/** + * @brief Disable the LPM interrupt. + * @retval None + */ +void ald_usb_lpm_int_disable(uint32_t ints) +{ + return; +} + +/** + * @brief Enable the LPM interrupt. + * @retval None + */ +void ald_usb_lpm_int_enable(uint32_t ints) +{ + return; +} + +/** + * @brief Transmit a LPM transaction in host mode. + * @param addr: Address. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx) +{ + return; +} + +/** + * @brief Configure the LPM parameters in host mode. + * @param resume_time: Resume time. + * @param config: Parameters + * @retval None + */ +void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config) +{ + return; +} + +/** + * @brief Initiate a RESUME from the L1 state in host mode. + * @retval None + */ +void ald_usb_host_lpm_resume(void) +{ + return; +} + +/** + * @brief Enable remote wakeup in device mode. + * @retval None + */ +void ald_usb_dev_lpm_remote_wake(void) +{ + return; +} + +/** + * @brief Enable remote wakeup in device mode. + * @retval None + */ +void ald_usb_dev_lpm_config(uint32_t config) +{ + return; +} + +/** + * @brief Enable LPM in device mode. + * @retval None + */ +void ald_usb_dev_lpm_enable(void) +{ + return; +} + +/** + * @brief Disable LPM in device mode. + * @retval None + */ +void ald_usb_dev_lpm_disable(void) +{ + return; +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group10 LPM functions + * @brief USB SWVBUS control + * @{ + */ +/** + * @brief Selet the control mode of VBUS. + * @param sigctl: 0, indicates that use the hardware control + * sigctl: 1, indicates that use the software control. + * @retval Status. + */ +void ald_usb_swvbus_sigctl_set(uint8_t sigctl) +{ + if (sigctl == 1) + { + USB->SWVBUS |= 0x01 << 0; + } + else + { + USB->SWVBUS &= ~(0x01 << 0); + } + return; +} + +/** + * @brief Selet the control mode of VBUS. + * @param None. + * @retval Status: 0, indicates that use the hardware control + * Status: 1, indicates that use the software control. + */ +uint8_t ald_usb_swvbus_sigctl_get(void) +{ + return (USB->SWVBUS & (0x01 << 0)); +} + +/** + * @brief Set session end threshold. + * @param thd: 0, indicates that lower than the session end threshold + * thd: 1, indicates that higher than the session end threshold. + * @retval Status. + */ +void ald_usb_swvbus_sesendth_set(uint8_t thd) +{ + if (thd == 1) + { + USB->SWVBUS |= 0x01 << 1; + } + else + { + USB->SWVBUS &= ~(0x01 << 1); + } + return; +} + +/** + * @brief Set session end threshold. + * @param None. + * @retval Status: 0, indicates that lower than the session end threshold + * Status: 1, indicates that higher than the session end threshold. + */ +uint8_t ald_usb_swvbus_sesendth_get(void) +{ + return (USB->SWVBUS & (0x01 << 1)); +} + +/** + * @brief Set session valid threshold. + * @param thd: 0, indicates that lower than the session valid threshold + thd: 1, indicates that higher than the session valid threshold. + * @retval Status. + */ +void ald_usb_swvbus_sesvalth_set(uint8_t thd) +{ + if (thd == 1) + { + USB->SWVBUS |= 0x01 << 2; + } + else + { + USB->SWVBUS &= ~(0x01 << 2); + } + return; +} + +/** + * @brief Set session valid threshold. + * @param None. + * @retval Status: 0, indicates that lower than the session valid threshold + Status: 1, indicates that higher than the session valid threshold. + */ +uint8_t ald_usb_swvbus_sesvalth_get(void) +{ + return (USB->SWVBUS & (0x01 << 2)); +} + +/** + * @brief Set VBUS valid threshold. + * @param thd: 0, indicates that lower than the vbus valid threshold + thd: 1, indicates that higher than the vbus valid threshold. + * @retval Status. + */ +void ald_usb_swvbus_valth_set(uint8_t thd) +{ + if (thd == 1) + { + USB->SWVBUS |= 0x01 << 3; + } + else + { + USB->SWVBUS &= ~(0x01 << 3); + } + return; +} + +/** + * @brief Set VBUS valid threshold. + * @param None. + * @retval Status: 0, indicates that lower than the vbus valid threshold + Status:thd: 1, indicates that higher than the vbus valid threshold. + */ +uint8_t ald_usb_swvbus_valth_get(void) +{ + return (USB->SWVBUS & (0x01 << 3)); +} + +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group11 components initialization functions + * @brief USB components initialization + * @{ + */ +/** + * @brief Initialize usb host components. + * @retval None + */ +void ald_usb_host_components_init(void) +{ + RCU->AHBRST |= 0x4000; + RCU->AHBRST &= 0xFFFFBFFF; + + /* Config EP0 */ + ald_usb_host_ep_config(ALD_USB_EP_0, 64, 0, 0, (ALD_USB_EP_MODE_CTRL | ALD_USB_EP_SPEED_FULL | ALD_USB_EP_HOST_OUT)); + + /* Clear interrupts */ + + + /* Enable PHY power */ + ald_usb_host_pwr_enable(); + /* clear hnp session */ + ald_usb_otg_session_request(false); + + /* set vbus control mode and threshold value */ + ald_usb_swvbus_sigctl_set(1); + ald_usb_swvbus_sesendth_set(1); + ald_usb_swvbus_sesvalth_set(1); + ald_usb_swvbus_valth_set(1); + /* Pull down DP and DM */ + ald_usb_dppud_set(ALD_USB_DPDM_PUSH_DOWN); + ald_usb_dmpud_set(ALD_USB_DPDM_PUSH_DOWN); + /* software control CID */ + ald_usb_swcid_cidctrl(1); + /* force to host mode */ + ald_usb_swcid_host(0); + /* start host request */ + ald_usb_mode_host_req(); + /* Start hnp */ + ald_usb_otg_session_request(true); + + /* Clear interrupts */ + ald_usb_int_status_get(); + /* Init interrupts */ + ald_usb_int_enable(ALD_USB_INTCTRL_SESSION | ALD_USB_INTCTRL_DISCONNECT | ALD_USB_INTCTRL_CONNECT | ALD_USB_INTCTRL_SOF | + ALD_USB_INTCTRL_BABBLE | ALD_USB_INTCTRL_RESUME); + ald_usb_int_enable_ep(ALD_USB_INTEP_ALL); + ald_usb_int_register(); + + return; +} + +/** + * @brief Initialize usb device components. + * @retval None + */ +void ald_usb_device_components_init(void) +{ + ald_usb_otg_session_request(true); + ald_usb_dppud_set(ALD_USB_DPDM_PUSH_UP); + /* software control CID */ + ald_usb_swcid_cidctrl(1); + /* force to dev mode */ + ald_usb_swcid_host(1); + ald_usb_dev_suspend_enable(); + + return; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_USB */ +/** + * @} + */ + +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.h b/os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.h new file mode 100644 index 00000000000..a845ad289e2 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.h @@ -0,0 +1,820 @@ +/** + ********************************************************************************* + * + * @file ald_usb.h + * @brief Header file of USB module driver. + * + * @version V1.0 + * @date 25 Feb. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Feb. 2022 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_USB_H__ +#define __ALD_USB_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include +#include "utils.h" + +/** @addtogroup ES32F0283_ALD + * @{ + */ + +/** @addtogroup USB + * @{ + */ + +/** @defgroup USB_Public_Macros USB Public Macros + * @{ + */ +/* Power */ +#define ALD_USB_POWER_RESET 0x00000008U +#define ALD_USB_POWER_RESUME 0x00000004U +#define ALD_USB_POWER_SUSPEND 0x00000002U +#define ALD_USB_POWER_ISOUDT 0x00000080U +#define ALD_USB_POWER_SUSPENDEN 0x00000001U + +/* DPDMCON */ +#define ALD_USB_DPDMCON_DPPUD 0x00000018U +#define ALD_USB_DPDMCON_DPPUD_FLOAT 0x00000000U +#define ALD_USB_DPDMCON_DPPUD_UP 0x00000008U +#define ALD_USB_DPDMCON_DPPUD_DOWN 0x00000010U +#define ALD_USB_DPDMCON_DMPUD 0x00000006U +#define ALD_USB_DPDMCON_DMPUD_FLOAT 0x00000000U +#define ALD_USB_DPDMCON_DMPUD_UP 0x00000002U +#define ALD_USB_DPDMCON_DMPUD_DOWN 0x00000004U +#define ALD_USB_DPDMCON_PHYPWREN 0x00000001U + +/* SWCID */ +#define ALD_USB_SWCID_HOST 0x00000002U +#define ALD_USB_SWCID_CIDCTRL 0x00000001U + +/* SWVBUS */ +#define ALD_USB_SWVBUS_VALTH 0x00000008U +#define ALD_USB_SWVBUS_SESVALTH 0x00000004U +#define ALD_USB_SWVBUS_SESENDTH 0x00000002U +#define ALD_USB_SWVBUS_SIGCTRL 0x00000001U + +/* SWTMODE */ +#define ALD_USB_SWTMODE_EN 0x00000001U + +/* DEVCON */ +#define ALD_USB_DEVCON_FSDEV 0x00000040U +#define ALD_USB_DEVCON_LSDEV 0x00000020U +#define ALD_USB_DEVCON_HOST 0x00000004U +#define ALD_USB_DEVCON_HOSTREQ 0x00000002U +#define ALD_USB_DEVCON_SESSION 0x00000001U + +/* CSR0L_TXCSRL */ +#define ALD_USB_CSR0L_NAKTO 0x00000080U +#define ALD_USB_CSR0L_STATUSPKT 0x00000040U +#define ALD_USB_CSR0L_REQPKT 0x00000020U +#define ALD_USB_CSR0L_ERROR 0x00000010U +#define ALD_USB_CSR0L_SETUPPKT 0x00000008U +#define ALD_USB_CSR0L_STALLED 0x00000004U +#define ALD_USB_CSR0L_TXRDY 0x00000002U +#define ALD_USB_CSR0L_RXRDY 0x00000001U + +#define ALD_USB_CSR0L_SETENDC 0x00000080U +#define ALD_USB_CSR0L_RXRDYC 0x00000040U +#define ALD_USB_CSR0L_STALL 0x00000020U +#define ALD_USB_CSR0L_SETEND 0x00000010U +#define ALD_USB_CSR0L_DATAEND 0x00000008U + +#define ALD_USB_TXCSRL_NAKTO 0x00000080U +#define ALD_USB_TXCSRL_CLRDT 0x00000040U +#define ALD_USB_TXCSRL_STALLED 0x00000020U +#define ALD_USB_TXCSRL_FLUSH 0x00000008U +#define ALD_USB_TXCSRL_ERROR 0x00000004U +#define ALD_USB_TXCSRL_FIFONE 0x00000002U +#define ALD_USB_TXCSRL_TXRDY 0x00000001U + +#define ALD_USB_TXCSRL_STALL 0x00000010U +#define ALD_USB_TXCSRL_UNDRUN 0x00000004U + +/* CSR0H_TXCSRH */ +#define ALD_USB_CSR0H_FLUSH 0x00000001U + +#define ALD_USB_TXCSRH_AUTOSET 0x00000080U +#define ALD_USB_TXCSRH_ISO 0x00000040U +#define ALD_USB_TXCSRH_MODE 0x00000020U +#define ALD_USB_TXCSRH_FDT 0x00000008U + +/* RXCSRL */ +#define ALD_USB_RXCSRL_CLRDT 0x00000080U +#define ALD_USB_RXCSRL_STALLED 0x00000040U +#define ALD_USB_RXCSRL_REQPKT 0x00000020U +#define ALD_USB_RXCSRL_FLUSH 0x00000010U +#define ALD_USB_RXCSRL_DATAERR_NAKTO 0x00000008U +#define ALD_USB_RXCSRL_ERROR 0x00000004U +#define ALD_USB_RXCSRL_FULL 0x00000002U +#define ALD_USB_RXCSRL_RXRDY 0x00000001U + +#define ALD_USB_RXCSRL_STALL 0x00000020U +#define ALD_USB_RXCSRL_DATAERR 0x00000008U +#define ALD_USB_RXCSRL_OVERRUN 0x00000004U + +/* RXCSRH */ +#define ALD_USB_RXCSRL_AUTOCLR 0x00000080U +#define ALD_USB_RXCSRL_AUTOREQ 0x00000040U + +#define ALD_USB_RXCSRL_ISO 0x00000040U + +/* TXTYPE */ +#define ALD_USB_TXTYPE_PROTOCOL 0x00000030U +#define ALD_USB_TXTYPE1_PROTOCOL_CTRL 0x00000000U +#define ALD_USB_TXTYPE_PROTOCOL_ISO 0x00000010U +#define ALD_USB_TXTYPE_PROTOCOL_BULK 0x00000020U +#define ALD_USB_TXTYPE_PROTOCOL_INT 0x00000030U +#define ALD_USB_TXTYPE_TEPN_1 0x00000001U +#define ALD_USB_TXTYPE_TEPN_2 0x00000002U +#define ALD_USB_TXTYPE_TEPN_3 0x00000003U +#define ALD_USB_TXTYPE_TEPN_4 0x00000004U +#define ALD_USB_TXTYPE_TEPN_5 0x00000005U +#define ALD_USB_TXTYPE_TEPN_6 0x00000006U + +/* RXTYPE */ +#define ALD_USB_RXTYPE_PROTOCOL_ISO 0x00000010U +#define ALD_USB_RXTYPE_PROTOCOL_BULK 0x00000020U +#define ALD_USB_RXTYPE_PROTOCOL_INT 0x00000030U +#define ALD_USB_RXTYPE_TEPN_1 0x00000001U +#define ALD_USB_RXTYPE_TEPN_2 0x00000002U +#define ALD_USB_RXTYPE_TEPN_3 0x00000003U +#define ALD_USB_RXTYPE_TEPN_4 0x00000004U +#define ALD_USB_RXTYPE_TEPN_5 0x00000005U +#define ALD_USB_RXTYPE_TEPN_6 0x00000006U + +/* TXFIFO2 */ +#define ALD_USB_TXFIFO2_MAXPKTSIZE_1024 0x000000E0U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_512 0x000000C0U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_256 0x000000A0U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_128 0x00000080U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_64 0x00000060U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_32 0x00000040U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_16 0x00000020U +#define ALD_USB_TXFIFO2_DPB 0x00000010U +#define ALD_USB_TXFIFO2_ADDRH 0x00000007U + +/* RXFIFO2 */ +#define ALD_USB_RXFIFO2_MAXPKTSIZE_1024 0x000000E0U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_512 0x000000C0U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_256 0x000000A0U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_128 0x00000080U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_64 0x00000060U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_32 0x00000040U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_16 0x00000020U +#define ALD_USB_RXFIFO2_DPB 0x00000010U + +/* TXIER */ +#define ALD_USB_TXIER_EP6IE 0x00000040U +#define ALD_USB_TXIER_EP5IE 0x00000020U +#define ALD_USB_TXIER_EP4IE 0x00000010U +#define ALD_USB_TXIER_EP3IE 0x00000008U +#define ALD_USB_TXIER_EP2IE 0x00000004U +#define ALD_USB_TXIER_EP1IE 0x00000002U +#define ALD_USB_TXIER_EP0IE 0x00000001U + +/* RXIER */ +#define ALD_USB_RXIER_EP6IE 0x00000040U +#define ALD_USB_RXIER_EP5IE 0x00000020U +#define ALD_USB_RXIER_EP4IE 0x00000010U +#define ALD_USB_RXIER_EP3IE 0x00000008U +#define ALD_USB_RXIER_EP2IE 0x00000004U +#define ALD_USB_RXIER_EP1IE 0x00000002U + +/* TXIDR */ +#define ALD_USB_TXIDR_EP6ID 0x00000040U +#define ALD_USB_TXIDR_EP5ID 0x00000020U +#define ALD_USB_TXIDR_EP4ID 0x00000010U +#define ALD_USB_TXIDR_EP3ID 0x00000008U +#define ALD_USB_TXIDR_EP2ID 0x00000004U +#define ALD_USB_TXIDR_EP1ID 0x00000002U +#define ALD_USB_TXIDR_EP0ID 0x00000001U + +/* RXIDR */ +#define ALD_USB_RXIDR_EP6ID 0x00000040U +#define ALD_USB_RXIDR_EP5ID 0x00000020U +#define ALD_USB_RXIDR_EP4ID 0x00000010U +#define ALD_USB_RXIDR_EP3ID 0x00000008U +#define ALD_USB_RXIDR_EP2ID 0x00000004U +#define ALD_USB_RXIDR_EP1ID 0x00000002U + +/* TXIVS */ +#define ALD_USB_TXIVS_EP6IVS 0x00000040U +#define ALD_USB_TXIVS_EP5IVS 0x00000020U +#define ALD_USB_TXIVS_EP4IVS 0x00000010U +#define ALD_USB_TXIVS_EP3IVS 0x00000008U +#define ALD_USB_TXIVS_EP2IVS 0x00000004U +#define ALD_USB_TXIVS_EP1IVS 0x00000002U +#define ALD_USB_TXIVS_EP0IVS 0x00000001U + +/* RXIVS */ +#define ALD_USB_RXIVS_EP6IVS 0x00000040U +#define ALD_USB_RXIVS_EP5IVS 0x00000020U +#define ALD_USB_RXIVS_EP4IVS 0x00000010U +#define ALD_USB_RXIVS_EP3IVS 0x00000008U +#define ALD_USB_RXIVS_EP2IVS 0x00000004U +#define ALD_USB_RXIVS_EP1IVS 0x00000002U + +/* TXRIF */ +#define ALD_USB_TXRIF_EP6RIF 0x00000040U +#define ALD_USB_TXRIF_EP5RIF 0x00000020U +#define ALD_USB_TXRIF_EP4RIF 0x00000010U +#define ALD_USB_TXRIF_EP3RIF 0x00000008U +#define ALD_USB_TXRIF_EP2RIF 0x00000004U +#define ALD_USB_TXRIF_EP1RIF 0x00000002U +#define ALD_USB_TXRIF_EP0RIF 0x00000001U + +/* RXRIF */ +#define ALD_USB_RXRIF_EP6RIF 0x00000040U +#define ALD_USB_RXRIF_EP5RIF 0x00000020U +#define ALD_USB_RXRIF_EP4RIF 0x00000010U +#define ALD_USB_RXRIF_EP3RIF 0x00000008U +#define ALD_USB_RXRIF_EP2RIF 0x00000004U +#define ALD_USB_RXRIF_EP1RIF 0x00000002U + +/* TXIFM */ +#define ALD_USB_TXIFM_EP6IFM 0x00000040U +#define ALD_USB_TXIFM_EP5IFM 0x00000020U +#define ALD_USB_TXIFM_EP4IFM 0x00000010U +#define ALD_USB_TXIFM_EP3IFM 0x00000008U +#define ALD_USB_TXIFM_EP2IFM 0x00000004U +#define ALD_USB_TXIFM_EP1IFM 0x00000002U +#define ALD_USB_TXIFM_EP0IFM 0x00000001U + +/* RXIFM */ +#define ALD_USB_RXIFM_EP6IFM 0x00000040U +#define ALD_USB_RXIFM_EP5IFM 0x00000020U +#define ALD_USB_RXIFM_EP4IFM 0x00000010U +#define ALD_USB_RXIFM_EP3IFM 0x00000008U +#define ALD_USB_RXIFM_EP2IFM 0x00000004U +#define ALD_USB_RXIFM_EP1IFM 0x00000002U + +/* TXICR */ +#define ALD_USB_TXICR_EP6ICR 0x00000040U +#define ALD_USB_TXICR_EP5ICR 0x00000020U +#define ALD_USB_TXICR_EP4ICR 0x00000010U +#define ALD_USB_TXICR_EP3ICR 0x00000008U +#define ALD_USB_TXICR_EP2ICR 0x00000004U +#define ALD_USB_TXICR_EP1ICR 0x00000002U +#define ALD_USB_TXICR_EP0ICR 0x00000001U + +/* RXICR */ +#define ALD_USB_RXICR_EP6ICR 0x00000040U +#define ALD_USB_RXICR_EP5ICR 0x00000020U +#define ALD_USB_RXICR_EP4ICR 0x00000010U +#define ALD_USB_RXICR_EP3ICR 0x00000008U +#define ALD_USB_RXICR_EP2ICR 0x00000004U +#define ALD_USB_RXICR_EP1ICR 0x00000002U + +/* IER */ +#define ALD_USB_IER_STATUS 0x000000FFU +#define ALD_USB_IER_SESREQIE 0x00000040U +#define ALD_USB_IER_DISCONIE 0x00000020U +#define ALD_USB_IER_CONIE 0x00000010U +#define ALD_USB_IER_SOFIE 0x00000008U +#define ALD_USB_IER_BABIE 0x00000004U +#define ALD_USB_IER_RESIE 0x00000002U + +/* IDR */ +#define ALD_USB_IDR_STATUS 0x000000FFU +#define ALD_USB_IDR_SESREQID 0x00000040U +#define ALD_USB_IDR_DISCONID 0x00000020U +#define ALD_USB_IDR_CONID 0x00000010U +#define ALD_USB_IDR_SOFID 0x00000008U +#define ALD_USB_IDR_BABID 0x00000004U +#define ALD_USB_IDR_RESID 0x00000002U + +/* IVS */ +#define ALD_USB_IVS_SESREQIVS 0x00000040U +#define ALD_USB_IVS_DISCONIVS 0x00000020U +#define ALD_USB_IVS_CONIVS 0x00000010U +#define ALD_USB_IVS_SOFIVS 0x00000008U +#define ALD_USB_IVS_BABIVS 0x00000004U +#define ALD_USB_IVS_RESIVS 0x00000002U + +/* RIF */ +#define ALD_USB_RIF_SESREQRIF 0x00000040U +#define ALD_USB_RIF_DISCONRIF 0x00000020U +#define ALD_USB_RIF_CONRIF 0x00000010U +#define ALD_USB_RIF_SOFRIF 0x00000008U +#define ALD_USB_RIF_BABRIF 0x00000004U +#define ALD_USB_RIF_RESRIF 0x00000002U + +/* IFM */ +#define ALD_USB_IFM_SESREQIFM 0x00000040U +#define ALD_USB_IFM_DISCONIFM 0x00000020U +#define ALD_USB_IFM_CONIFM 0x00000010U +#define ALD_USB_IFM_SOFIFM 0x00000008U +#define ALD_USB_IFM_BABIFM 0x00000004U +#define ALD_USB_IFM_RESIFM 0x00000002U + +/* ICR */ +#define ALD_USB_ICR_SESREQICR 0x00000040U +#define ALD_USB_ICR_DISCONICR 0x00000020U +#define ALD_USB_ICR_CONICR 0x00000010U +#define ALD_USB_ICR_SOFICR 0x00000008U +#define ALD_USB_ICR_BABICR 0x00000004U +#define ALD_USB_ICR_RESICR 0x00000002U + + +#define ALD_MAX_NAK_LIMIT 255U +#define ALD_DISABLE_NAK_LIMIT 0U + +#define ALD_USB_RX_EPSTATUS_SHIFT 16U +#define ALD_USB_INTEP_RX_SHIFT 16U + +#define ALD_MAX_PACKET_SIZE_EP0 64U + +#define ALD_USB_TXTYPE1_PROTO_M 0x00000030U +#define ALD_USB_TXTYPE1_PROTO_CTRL 0x00000000U +#define ALD_USB_TXTYPE1_PROTO_ISOC 0x00000010U +#define ALD_USB_TXTYPE1_PROTO_BULK 0x00000020U +#define ALD_USB_TXTYPE1_PROTO_INT 0x00000030U + +#define ALD_USB_FIFO_SZ_8 0x00000000U +#define ALD_USB_FIFO_SZ_16 0x00000001U +#define ALD_USB_FIFO_SZ_32 0x00000002U +#define ALD_USB_FIFO_SZ_64 0x00000003U +#define ALD_USB_FIFO_SZ_128 0x00000004U +#define ALD_USB_FIFO_SZ_256 0x00000005U +#define ALD_USB_FIFO_SZ_512 0x00000006U +#define ALD_USB_FIFO_SZ_1024 0x00000007U +#define ALD_USB_FIFO_SZ_2048 0x00000008U +#define ALD_USBFIFOSizeToBytes(x) (8 << (x)) + +#define ALD_USB_TRANS_OUT 0x00000102U +#define ALD_USB_TRANS_IN 0x00000102U +#define ALD_USB_TRANS_IN_LAST 0x0000010aU +#define ALD_USB_TRANS_SETUP 0x0000110aU +#define ALD_USB_TRANS_STATUS 0x00000142U + +#define ALD_USB_RX_EPSTATUS_SHIFT 16U +#define ALD_USB_INTEP_RX_SHIFT 16U + +#define ALD_USB_UNDEF_SPEED 0x80000000U +#define ALD_USB_HIGH_SPEED 0x00000002U +#define ALD_USB_FULL_SPEED 0x00000001U +#define ALD_USB_LOW_SPEED 0x00000000U + +#define ALD_USB_EP_AUTO_SET 0x00000001 +#define ALD_USB_EP_AUTO_REQUEST 0x00000002 +#define ALD_USB_EP_AUTO_CLEAR 0x00000004 +#define ALD_USB_EP_DUAL_BUFFERING 0x00000008 +#define ALD_USB_EP_DMA_MODE_0 0x00000008 +#define ALD_USB_EP_DMA_MODE_1 0x00000010 +#define ALD_USB_EP_DIS_NYET 0x00000020 + +#define ALD_USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define ALD_USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define ALD_USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define ALD_USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define ALD_USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define ALD_USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define ALD_USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define ALD_USB_EP_SPEED_HIGH 0x00004000 // High Speed +#define ALD_USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define ALD_USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define ALD_USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define ALD_USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +#define ALD_USB_INTCTRL_ALL 0x000003FFU +#define ALD_USB_INTCTRL_STATUS 0x000000FFU +#define ALD_USB_INTCTRL_VBUS_ERR 0x00000080U +#define ALD_USB_INTCTRL_SESSION 0x00000040U +#define ALD_USB_INTCTRL_SESSION_END 0x00000040U +#define ALD_USB_INTCTRL_DISCONNECT 0x00000020U +#define ALD_USB_INTCTRL_CONNECT 0x00000010U +#define ALD_USB_INTCTRL_SOF 0x00000008U +#define ALD_USB_INTCTRL_BABBLE 0x00000004U +#define ALD_USB_INTCTRL_RESET 0x00000004U +#define ALD_USB_INTCTRL_RESUME 0x00000002U +#define ALD_USB_INTCTRL_SUSPEND 0x00000001U +#define ALD_USB_INTCTRL_MODE_DETECT 0x00000200U +#define ALD_USB_INTCTRL_POWER_FAULT 0x00000100U + + +#define ALD_USB_INTEP_ALL 0xFFFFFFFFU +#define ALD_USB_INTEP_HOST_IN 0x001E0000U +#define ALD_USB_INTEP_HOST_IN_15 0x80000000U +#define ALD_USB_INTEP_HOST_IN_14 0x40000000U +#define ALD_USB_INTEP_HOST_IN_13 0x20000000U +#define ALD_USB_INTEP_HOST_IN_12 0x10000000U +#define ALD_USB_INTEP_HOST_IN_11 0x08000000U +#define ALD_USB_INTEP_HOST_IN_10 0x04000000U +#define ALD_USB_INTEP_HOST_IN_9 0x02000000U +#define ALD_USB_INTEP_HOST_IN_8 0x01000000U +#define ALD_USB_INTEP_HOST_IN_7 0x00800000U +#define ALD_USB_INTEP_HOST_IN_6 0x00400000U +#define ALD_USB_INTEP_HOST_IN_5 0x00200000U +#define ALD_USB_INTEP_HOST_IN_4 0x00100000U +#define ALD_USB_INTEP_HOST_IN_3 0x00080000U +#define ALD_USB_INTEP_HOST_IN_2 0x00040000U +#define ALD_USB_INTEP_HOST_IN_1 0x00020000U +#define ALD_USB_INTEP_DEV_OUT 0x001E0000U +#define ALD_USB_INTEP_DEV_OUT_15 0x80000000U +#define ALD_USB_INTEP_DEV_OUT_14 0x40000000U +#define ALD_USB_INTEP_DEV_OUT_13 0x20000000U +#define ALD_USB_INTEP_DEV_OUT_12 0x10000000U +#define ALD_USB_INTEP_DEV_OUT_11 0x08000000U +#define ALD_USB_INTEP_DEV_OUT_10 0x04000000U +#define ALD_USB_INTEP_DEV_OUT_9 0x02000000U +#define ALD_USB_INTEP_DEV_OUT_8 0x01000000U +#define ALD_USB_INTEP_DEV_OUT_7 0x00800000U +#define ALD_USB_INTEP_DEV_OUT_6 0x00400000U +#define ALD_USB_INTEP_DEV_OUT_5 0x00200000U +#define ALD_USB_INTEP_DEV_OUT_4 0x00100000U +#define ALD_USB_INTEP_DEV_OUT_3 0x00080000U +#define ALD_USB_INTEP_DEV_OUT_2 0x00040000U +#define ALD_USB_INTEP_DEV_OUT_1 0x00020000U +#define ALD_USB_INTEP_HOST_OUT 0x0000001EU +#define ALD_USB_INTEP_HOST_OUT_15 0x00008000U +#define ALD_USB_INTEP_HOST_OUT_14 0x00004000U +#define ALD_USB_INTEP_HOST_OUT_13 0x00002000U +#define ALD_USB_INTEP_HOST_OUT_12 0x00001000U +#define ALD_USB_INTEP_HOST_OUT_11 0x00000800U +#define ALD_USB_INTEP_HOST_OUT_10 0x00000400U +#define ALD_USB_INTEP_HOST_OUT_9 0x00000200U +#define ALD_USB_INTEP_HOST_OUT_8 0x00000100U +#define ALD_USB_INTEP_HOST_OUT_7 0x00000080U +#define ALD_USB_INTEP_HOST_OUT_6 0x00000040U +#define ALD_USB_INTEP_HOST_OUT_5 0x00000020U +#define ALD_USB_INTEP_HOST_OUT_4 0x00000010U +#define ALD_USB_INTEP_HOST_OUT_3 0x00000008U +#define ALD_USB_INTEP_HOST_OUT_2 0x00000004U +#define ALD_USB_INTEP_HOST_OUT_1 0x00000002U +#define ALD_USB_INTEP_DEV_IN 0x0000001EU +#define ALD_USB_INTEP_DEV_IN_15 0x00008000U +#define ALD_USB_INTEP_DEV_IN_14 0x00004000U +#define ALD_USB_INTEP_DEV_IN_13 0x00002000U +#define ALD_USB_INTEP_DEV_IN_12 0x00001000U +#define ALD_USB_INTEP_DEV_IN_11 0x00000800U +#define ALD_USB_INTEP_DEV_IN_10 0x00000400U +#define ALD_USB_INTEP_DEV_IN_9 0x00000200U +#define ALD_USB_INTEP_DEV_IN_8 0x00000100U +#define ALD_USB_INTEP_DEV_IN_7 0x00000080U +#define ALD_USB_INTEP_DEV_IN_6 0x00000040U +#define ALD_USB_INTEP_DEV_IN_5 0x00000020U +#define ALD_USB_INTEP_DEV_IN_4 0x00000010U +#define ALD_USB_INTEP_DEV_IN_3 0x00000008U +#define ALD_USB_INTEP_DEV_IN_2 0x00000004U +#define ALD_USB_INTEP_DEV_IN_1 0x00000002U +#define ALD_USB_INTEP_0 0x00000001U + + +#define ALD_USB_UNDEF_SPEED 0x80000000U +#define ALD_USB_HIGH_SPEED 0x00000002U +#define ALD_USB_FULL_SPEED 0x00000001U +#define ALD_USB_LOW_SPEED 0x00000000U + +#define ALD_USB_HOST_IN_STATUS 0x114F0000U +#define ALD_USB_HOST_IN_PID_ERROR 0x10000000U +#define ALD_USB_HOST_IN_NOT_COMP 0x01000000U +#define ALD_USB_HOST_IN_STALL 0x00400000U +#define ALD_USB_HOST_IN_DATA_ERROR 0x00080000U +#define ALD_USB_HOST_IN_NAK_TO 0x00080000U +#define ALD_USB_HOST_IN_ERROR 0x00040000U +#define ALD_USB_HOST_IN_FIFO_FULL 0x00020000U +#define ALD_USB_HOST_IN_PKTRDY 0x00010000U +#define ALD_USB_HOST_OUT_STATUS 0x000000A7U +#define ALD_USB_HOST_OUT_NAK_TO 0x00000080U +#define ALD_USB_HOST_OUT_NOT_COMP 0x00000080U +#define ALD_USB_HOST_OUT_STALL 0x00000020U +#define ALD_USB_HOST_OUT_ERROR 0x00000004U +#define ALD_USB_HOST_OUT_FIFO_NE 0x00000002U +#define ALD_USB_HOST_OUT_PKTPEND 0x00000001U +#define ALD_USB_HOST_EP0_NAK_TO 0x00000080U +#define ALD_USB_HOST_EP0_STATUS 0x00000040U +#define ALD_USB_HOST_EP0_ERROR 0x00000010U +#define ALD_USB_HOST_EP0_RX_STALL 0x00000004U +#define ALD_USB_HOST_EP0_RXPKTRDY 0x00000001U +#define ALD_USB_DEV_RX_PID_ERROR 0x01000000U +#define ALD_USB_DEV_RX_SENT_STALL 0x00400000U +#define ALD_USB_DEV_RX_DATA_ERROR 0x00080000U +#define ALD_USB_DEV_RX_OVERRUN 0x00040000U +#define ALD_USB_DEV_RX_FIFO_FULL 0x00020000U +#define ALD_USB_DEV_RX_PKT_RDY 0x00010000U +#define ALD_USB_DEV_TX_NOT_COMP 0x00000080U +#define ALD_USB_DEV_TX_SENT_STALL 0x00000020U +#define ALD_USB_DEV_TX_UNDERRUN 0x00000004U +#define ALD_USB_DEV_TX_FIFO_NE 0x00000002U +#define ALD_USB_DEV_TX_TXPKTRDY 0x00000001U +#define ALD_USB_DEV_EP0_SETUP_END 0x00000010U +#define ALD_USB_DEV_EP0_SENT_STALL 0x00000004U +#define ALD_USB_DEV_EP0_IN_PKTPEND 0x00000002U +#define ALD_USB_DEV_EP0_OUT_PKTRDY 0x00000001U + + +#define ALD_USB_EP_0 0x00000000U +#define ALD_USB_EP_1 0x00000001U +#define ALD_USB_EP_2 0x00000002U +#define ALD_USB_EP_3 0x00000003U +#define ALD_USB_EP_4 0x00000004U +#define ALD_USB_EP_5 0x00000005U +#define ALD_USB_EP_6 0x00000006U +#define ALD_USB_EP_7 0x00000007U +#define ALD_NUM_USB_EP 8U + +#define ALD_USB_FIFO_SZ_8 0x00000000U +#define ALD_USB_FIFO_SZ_16 0x00000001U +#define ALD_USB_FIFO_SZ_32 0x00000002U +#define ALD_USB_FIFO_SZ_64 0x00000003U +#define ALD_USB_FIFO_SZ_128 0x00000004U +#define ALD_USB_FIFO_SZ_256 0x00000005U +#define ALD_USB_FIFO_SZ_512 0x00000006U +#define ALD_USB_FIFO_SZ_1024 0x00000007U +#define ALD_USB_FIFO_SZ_2048 0x00000008U + +#define ALD_USB_TRANS_OUT 0x00000102U +#define ALD_USB_TRANS_IN 0x00000102U +#define ALD_USB_TRANS_IN_LAST 0x0000010aU +#define ALD_USB_TRANS_SETUP 0x0000110aU +#define ALD_USB_TRANS_STATUS 0x00000142U +#define ALD_USB_DMA_EP_CFG_TX 0x00000001U +#define ALD_USB_DMA_EP_CFG_RX_DEV 0x00000002U +#define ALD_USB_DMA_EP_CFG_RX_HOST 0x00000004U +#define ALD_USB_DMA_EP_TX_MSK 0x94U +#define ALD_USB_DMA_EP_RX_DEV_MSK 0xA8U +#define ALD_USB_DMA_EP_RX_HOST_MSK 0xE8U + +#define ALD_USB_INTLPM_ERROR 0x00000020U +#define ALD_USB_INTLPM_RESUME 0x00000010U +#define ALD_USB_INTLPM_INCOMPLETE 0x00000008U +#define ALD_USB_INTLPM_ACK 0x00000004U +#define ALD_USB_INTLPM_NYET 0x00000002U +#define ALD_USB_INTLPM_STALL 0x00000001U + + +#define ALD_USB_DEV_LPM_NAK 0x00000010U +#define ALD_USB_DEV_LPM_NONE 0x00000000U +#define ALD_USB_DEV_LPM_EN 0x0000000cU +#define ALD_USB_DEV_LPM_EXTONLY 0x00000004U + +#define ALD_USB_HOST_LPM_RMTWAKE 0x00000100U +#define ALD_USB_HOST_LPM_L1 0x00000001U + +#define ALD_USB_DEV_LPM_LS_RMTWAKE 0x00000100U +#define ALD_USB_DEV_LPM_LS_L1 0x00000001U + +#define ALD_USB_HOST_PWRFLT_LOW 0x00000010U +#define ALD_USB_HOST_PWRFLT_HIGH 0x00000030U +#define ALD_USB_HOST_PWRFLT_EP_NONE 0x00000000U +#define ALD_USB_HOST_PWRFLT_EP_TRI 0x00000140U +#define ALD_USB_HOST_PWRFLT_EP_LOW 0x00000240U +#define ALD_USB_HOST_PWRFLT_EP_HIGH 0x00000340U +#define ALD_USB_HOST_PWREN_MAN_LOW 0x00000000U +#define ALD_USB_HOST_PWREN_MAN_HIGH 0x00000001U +#define ALD_USB_HOST_PWREN_AUTOLOW 0x00000002U +#define ALD_USB_HOST_PWREN_AUTOHIGH 0x00000003U +#define ALD_USB_HOST_PWREN_FILTER 0x00010000U + + +/** + * @} + */ + + +/** + * @defgroup USB_Public_Types USB Public Types + * @{ + */ + +/** + * @brief USB DP/DM line push-up or push-down + */ +typedef enum { + ALD_USB_DPDM_FLOATING = 0x0U, /**< Floating */ + ALD_USB_DPDM_PUSH_UP = 0x1U, /**< Push-Up */ + ALD_USB_DPDM_PUSH_DOWN = 0x2U, /**< Push-Down */ +} ald_dpdm_push_t; + + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions + * @{ + */ + +/** @addtogroup USB_Public_Functions_Group1 + * @{ + */ +/* Base functions */ +extern uint32_t ald_usb_frame_number_get(void); +extern void ald_usb_otg_session_request(bool start); +extern uint32_t ald_usb_mode_get(void); +extern uint32_t ald_usb_mode_host_req(void); +extern uint32_t ald_usb_mode_host_req_clear(void); +extern void ald_usb_high_speed_enable(bool enable); +extern uint32_t ald_usb_device_speed_get(void); +extern uint32_t ald_usb_num_ep_get( void); +extern void ald_usb_control_reset(void); +void ald_usb_dppud_set(ald_dpdm_push_t pupd); +void ald_usb_dmpud_set(ald_dpdm_push_t pupd); +void ald_usb_swcid_cidctrl(uint8_t cid); +void ald_usb_swcid_host(uint8_t host); + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group2 + * @{ + */ +/* Device functions */ +extern uint8_t ald_usb_dev_get_addr(void); +extern void ald_usb_dev_set_addr(uint8_t addr); +extern void ald_usb_dev_connect(void); +extern void ald_usb_dev_disconnect(void); +extern void ald_usb_dev_suspend_enable(void); +extern void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags); +extern void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags); +extern void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last); +extern void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags); + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group3 + * @{ + */ +/* Host functions */ +extern uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags); +extern void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags); +extern void ald_usb_host_ep_data_ack(uint32_t ep_idx); +extern void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags); +extern void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags); +extern uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags); +extern void ald_usb_host_pwr_disable(void); +extern void ald_usb_host_pwr_enable(void); +extern void ald_usb_host_pwr_config(uint32_t flags); +extern void ald_usb_host_pwr_fault_disable(void); +extern void ald_usb_host_pwr_fault_enable(void); +extern void ald_usb_host_request_in(uint32_t ep_idx); +extern void ald_usb_host_request_in_clear(uint32_t ep_idx); +extern void ald_usb_host_request_status(void); +extern void ald_usb_host_reset(bool start); +extern void ald_usb_host_resume(bool start); +extern void ald_usb_host_suspend(void); +extern uint32_t ald_usb_host_speed_get(void); +extern void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group4 + * @{ + */ +/* Endpoint functions */ +extern uint32_t ald_usb_ep_data_avail(uint32_t ep_idx); +extern int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size); +extern int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size); +extern int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type); +extern void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count); +extern uint32_t ald_usb_ep_status(uint32_t ep_idx); +extern void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, TypeFunc en); + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group5 + * @{ + */ +/* FIFO functions */ +extern uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx); +extern void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags); +extern void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags); +extern void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group6 + * @{ + */ +/* Interrupt functions */ +extern void ald_usb_int_disable(uint32_t flags); +extern void ald_usb_int_enable(uint32_t flags); +extern uint32_t ald_usb_int_status_get(void); +extern void ald_usb_int_disable_ep(uint32_t flags); +extern void ald_usb_int_enable_ep(uint32_t flags); +extern uint32_t ald_usb_int_status_ep_get(void); +extern void ald_usb_int_register(void); +extern void ald_usb_int_unregister(void); +extern uint32_t ald_usb_int_num_get(void); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group7 + * @{ + */ +/* DMA functions */ +extern void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl); +extern void ald_usb_dma_mult_recv_start(uint32_t ep_idx); +extern void ald_usb_dma_channel_start(uint8_t ch); +extern void ald_usb_dma_channel_stop(uint8_t ch); +extern uint32_t ald_usb_dma_get_interrupt_flag(void); +extern uint32_t ald_usb_dma_get_channel_error(uint8_t ch); +extern void ald_usb_dma_clear_channel_error(uint8_t ch); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group8 + * @{ + */ +/* LPM functions */ +extern void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx); +extern void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config); +extern uint32_t ald_usb_lpm_remote_wake_is_enable(void); +extern void ald_usb_host_lpm_resume(void); +extern void ald_usb_dev_lpm_remote_wake(void); +extern void ald_usb_dev_lpm_config(uint32_t config); +extern void ald_usb_dev_lpm_enable(void); +extern void ald_usb_dev_lpm_disable(void); +extern uint32_t ald_usb_lpm_link_status_get(void); +extern uint32_t ald_usb_lpm_ep_get(void); +extern uint32_t ald_usb_lpm_int_status_get(void); +extern void ald_usb_lpm_int_disable(uint32_t ints); +extern void ald_usb_lpm_int_enable(uint32_t ints); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group9 + * @{ + */ +/* usb swvbus control functions */ +extern void ald_usb_swvbus_sigctl_set(uint8_t sigctl); +extern uint8_t ald_usb_swvbus_sigctl_get(void); +extern void ald_usb_swvbus_sesendth_set(uint8_t thd); +extern uint8_t ald_usb_swvbus_sesendth_get(void); +extern void ald_usb_swvbus_sesvalth_set(uint8_t thd); +extern uint8_t ald_usb_swvbus_valth_get(void); +extern void ald_usb_swvbus_valth_set(uint8_t thd); +extern uint8_t ald_usb_swvbus_valth_get(void); + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group10 + * @{ + */ +/* usb init functions */ +extern void ald_usb_host_components_init(void); +extern void ald_usb_device_components_init(void); + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALD_USB_H__ */ diff --git a/os/common/ext/CMSIS/ES32/FS026/ald/utils.c b/os/common/ext/CMSIS/ES32/FS026/ald/utils.c new file mode 100644 index 00000000000..9e500ffddde --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/ald/utils.c @@ -0,0 +1,436 @@ +/********************************************************************************** + * + * @file utils.c + * @brief utils C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "utils.h" +#include "cmsis_compiler.h" + +/** @defgroup ALD + * @brief Shanghai Eastsoft Microelectronics Cortex-M Chip Abstraction Layer Driver(ALD) + * @{ + */ + +/** @defgroup UTILS Utils + * @brief Utils module driver + * @{ + */ + +/** @defgroup ALD_Private_Constants Private Constants + * @brief ALD Private Constants + * @{ + */ + +/** + * @brief ALD version number + */ +#define __LIB_VERSION_MAIN (0x01) /**< [31:24] main version */ +#define __LIB_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ +#define __LIB_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ +#define __LIB_VERSION_RC (0x00) /**< [7:0] release candidate */ +#define __LIB_VERSION ((__LIB_VERSION_MAIN << 24) | \ + (__LIB_VERSION_SUB1 << 16) | \ + (__LIB_VERSION_SUB2 << 8 ) | \ + (__LIB_VERSION_RC)) +/** + * @} ALD_Private_Constants + */ + +/** @defgroup ALD_Private_Variables Private Variables + * @{ + */ +/** @brief lib_tick: Increase by one millisecond + */ +static __IO uint32_t lib_tick; +uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; +/** + * @} ALD_Private_Variables + */ + + +/** @defgroup ALD_Public_Functions Public Functions + * @{ + */ + +/** @defgroup ALD_Public_Functions_Group1 Initialization Function + * @brief Initialization functions + * + * @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms. + (++) Time base configuration function (__init_tick()) is called automatically + at the beginning of the program after reset by mcu_hal_init() or at + any time when clock is configured. + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if __delay_ms() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __WEAK + to make override possible in case of other implementations in user file. + (+) Configure the interval of Systick interrupt. + + @endverbatim + * @{ + */ + +/** + * @brief This function Configures time base source, NVIC and DMA. + * @note This function is called at the beginning of program after reset and before + * the clock configuration. + * @note The time base configuration is based on System clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation, Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval None + */ +void ald_init(void) +{ + __init_tick(TICK_INT_PRIORITY); + return; +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if __delay_ms() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __WEAK to be overwritten in case of other + * implementation in user file. + * @param prio: Tick interrupt priority. + * @retval None + */ +__WEAK void __init_tick(uint32_t prio) +{ + /* Configure the SysTick IRQ */ + SysTick_Config(SystemFrequency_SysClk / SYSTICK_INTERVAL_1MS); + + if (prio != 3) + + NVIC_SetPriority(SysTick_IRQn, prio); + + return; +} + +/** + * @brief Selects the interval of systick interrupt. + * @param value: The value of interval: + * @arg @ref SYSTICK_INTERVAL_1MS 1 millisecond + * @arg @ref SYSTICK_INTERVAL_10MS 10 milliseconds + * @arg @ref SYSTICK_INTERVAL_100MS 100 milliseconds + * @arg @ref SYSTICK_INTERVAL_1000MS 1 second + * @retval None + */ +void systick_interval_select(systick_interval_t value) +{ + assert_param(IS_SYSTICK_INTERVAL(value)); + + SysTick_Config(SystemFrequency_SysClk / value); + __systick_interval = value; + + if (TICK_INT_PRIORITY != 3) + NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); + + return; +} +/** + * @} ALD_Public_Functions_Group1 + */ + +/** @defgroup ALD_Public_Functions_Group2 Control functions + * @brief Control functions + * + * @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL version + (+) Waiting for flag + (+) Configure the interrupt + (+) Provide system tick value + (+) Get CPU ID + @endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "lib_tick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__WEAK void __inc_tick(void) +{ + ++lib_tick; +} + +/** + * @brief This function invoked by Systick ISR. + * @note This function is declared as __WEAK to be overwritten in case of + * other implementations in user file. + * @retval None + */ +__WEAK void systick_irq_cbk(void) +{ + /* do nothing */ + return; +} + + + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__WEAK uint32_t __get_tick(void) +{ + return lib_tick; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where lib_tick + * is incremented. + * @note This function is declared as __WEAK to be overwritten in case of other + * implementations in user file. + * @param delay: specifies the delay time length, in milliseconds. + * @retval None + */ +__WEAK void __delay_ms(__IO uint32_t delay) +{ + uint32_t tick, __delay; + + switch (__systick_interval) + { + case SYSTICK_INTERVAL_1MS: + __delay = delay; + break; + + case SYSTICK_INTERVAL_10MS: + __delay = delay / 10; + break; + + case SYSTICK_INTERVAL_100MS: + __delay = delay / 100; + break; + + case SYSTICK_INTERVAL_1000MS: + __delay = delay / 1000; + break; + + default: + __delay = delay; + break; + } + + tick = __get_tick(); + __delay = __delay == 0 ? 1 : __delay; + + while ((__get_tick() - tick) < __delay) + ; +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Once __suspend_tick() is called, the the SysTick interrupt + * will be disabled and so Tick increment is suspended. + * @note This function is declared as __WEAK to be overwritten + * in case of other implementations in user file. + * @retval None + */ +__WEAK void __suspend_tick(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation, SysTick timer is the source of + * time base. It is used to generate interrupts at regular time + * intervals. Once __resume_tick() is called, the the SysTick + * interrupt will be enabled and so Tick increment is resumed. + * @note This function is declared as __WEAK to be overwritten + * in case of other implementations in user file. + * @retval None + */ +__WEAK void __resume_tick(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief This method returns the HAL revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t get_lib_version(void) +{ + return __LIB_VERSION; +} + +/** + * @brief Waiting the specified bit in the register change to SET/RESET. + * @param reg: The register address. + * @param bit: The specified bit. + * @param status: The status for waiting. + * @param timeout: Timeout duration. + * @retval Status, see @ref hal_status_t. + */ +ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, FlagStatus status, uint32_t timeout) +{ + uint32_t tick = __get_tick(); + + assert_param(timeout > 0); + + if (status == SET) + { + while (!(IS_BIT_SET(*reg, bit))) + { + if (((__get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + else + { + while ((IS_BIT_SET(*reg, bit))) + { + if (((__get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief Configure interrupt. + * @param irq: Interrunpt type. + * @param prio: preempt priority(0-3). + * @param status: Status. + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void mcu_irq_config(IRQn_Type irq, uint8_t prio, TypeFunc status) +{ + assert_param(IS_FUNC_STATE(status)); + assert_param(IS_PRIO(prio)); + + if (status == ENABLE) + { + NVIC_SetPriority(irq, prio); + NVIC_EnableIRQ(irq); + NVIC_ClearPendingIRQ(irq); + + } + else + { + NVIC_DisableIRQ(irq); + } + + return; +} + +/** + * @brief Get the system tick. + * @retval The value of current tick. + */ +uint32_t mcu_get_tick(void) +{ + uint32_t load = SysTick->LOAD; + uint32_t val = SysTick->VAL; + + return (load - val); +} + +/** + * @brief Get the CPU ID. + * @retval CPU ID. + */ +uint32_t mcu_get_cpu_id(void) +{ + return SCB->CPUID; +} + +/** + * @brief clear_tick + * @retval none. + */ +void __clear_tick(void) +{ + lib_tick = 0; +} + +/** + * @} ALD_Public_Functions_Group2 + */ + +/** + * @} ALD_Public_Functions + */ + + +/** + * @} UTILS + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/ald/utils.h b/os/common/ext/CMSIS/ES32/FS026/ald/utils.h new file mode 100644 index 00000000000..fb08eabb57d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/ald/utils.h @@ -0,0 +1,180 @@ +/********************************************************************************** + * + * @file utils.h + * @brief header file of utils.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __UTILS_H__ +#define __UTILS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------*/ +#include +#include +#include +//#include +#include "fs026.h" + +/** @addtogroup + * @{ + */ + +/** @addtogroup UTILS UTILS + * @brief UTILS module driver + * @{ + */ + +/** @defgroup ALD_Public_Types Public Types + * @{ + */ + +/** + * @brief ALD Status structures definition + */ +typedef enum +{ + OK = 0x0, + Error = 0x1, + BUSY = 0x2, + TIMEOUT = 0x3, +} ald_status_t; + +/** + * @brief SysTick interval definition + */ +typedef enum +{ + SYSTICK_INTERVAL_1MS = 1000, + SYSTICK_INTERVAL_10MS = 100, + SYSTICK_INTERVAL_100MS = 10, + SYSTICK_INTERVAL_1000MS = 1, +} systick_interval_t; +/** + * @} ALD_Public_Types + */ + +/** @defgroup ALD_Public_Macros Public Macros + * @{ + */ +#define TICK_INT_PRIORITY 3 +#define ALD_MAX_DELAY 0xFFFFFFFF +#define UNUSED(x) ((void)(x)) +#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) +#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) +#define RESET_HANDLE_STATE(x) ((x)->state = 0) +#define __LOCK(x) \ + do { \ + if ((x)->lock == LOCK) { \ + return BUSY; \ + } \ + else { \ + (x)->lock = LOCK; \ + } \ + } while (0) + +#define __UNLOCK(x) \ + do { \ + (x)->lock = UNLOCK; \ + } while (0) + +/** + * @} + */ + +/** @defgroup ALD_Private_Macros Private Macros + * @{ + */ +#define IS_PRIO(x) ((x) < 4) +#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ + ((x) == SYSTICK_INTERVAL_10MS) || \ + ((x) == SYSTICK_INTERVAL_100MS) || \ + ((x) == SYSTICK_INTERVAL_1000MS)) +/** + * @}ALD_Private_Macros + */ + +/** @addtogroup ALD_Public_Functions + * @{ + */ + +/** @addtogroup ALD_Public_Functions_Group1 + * @{ + */ + +/* Initialization functions */ +void ald_init(void); +void __init_tick(uint32_t prio); +void systick_interval_select(systick_interval_t value); + +/** + * @} ALD_Public_Functions_Group1 + */ + +/** @addtogroup ALD_Public_Functions_Group2 + * @{ + */ +/* Peripheral Control functions */ +void __inc_tick(void); +void __delay_ms(__IO uint32_t delay); +uint32_t __get_tick(void); +void __suspend_tick(void); +void __resume_tick(void); +void systick_irq_cbk(void); +uint32_t get_lib_version(void); +ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, FlagStatus status, uint32_t timeout); +void mcu_irq_config(IRQn_Type irq, uint8_t prio, TypeFunc status); +uint32_t mcu_get_tick(void); +uint32_t mcu_get_cpu_id(void); +void __clear_tick(void); +/** + * @} ALD_Public_Functions_Group2 + */ + +/** + * @} ALD_Public_Functions + */ + +/** + * @} UTILS + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif +/******************* (C) COPYRIGHT Eastsoft Microelectronics END OF FILE****/ + diff --git a/os/common/ext/CMSIS/ES32/FS026/fs026.h b/os/common/ext/CMSIS/ES32/FS026/fs026.h new file mode 100644 index 00000000000..bd85a72f734 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/fs026.h @@ -0,0 +1,437 @@ +/********************************************************************************** + * + * @file es32fs026.h + * @brief REG Head File + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup fs026 + * @{ + */ + +#ifndef __FS026_H__ +#define __FS026_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief defines 'read only' 、'write only'、 'read / write' permissions. + */ +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief configuration of the cortex-M3 processor and core peripherals. + */ + +#define __MPU_PRESENT 0 /*!< cm0ikmcu does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< cm0ikmcu Supports 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** + * @} + */ + +/** @addtogroup peripherals_interrupt_number_definition + * @{ + */ + +typedef enum IRQn +{ + + /****** Processor Exceptions Numbers ******************************************************/ + + /*************** Cortex-M0 Processor Exceptions Numbers **************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + + /**************** ES32FS026 specific Exceptions Numbers **************************/ + WWDT_IRQn = 0, /* 0 | WWDT Interrupt */ + PVD_IRQn = 1, /* 1 | PVD Interrupt EXTI[20] */ + RTC_IRQn = 2, /* 2 | RTC Interrupt */ + WAKEUP_IRQn = 3, /* 3 | WAKEUP Interrupt EXTI[21] */ + RCU_CSU_IRQn = 4, /* 4 | Interrupt */ + EXTI_0to1_IRQn = 5, /* 5 | EXTI[1:0] Interrupt GPIOx[1:0] */ + EXTI_2to3_IRQn = 6, /* 6 | EXTI[3:2] Interrupt GPIOx[3:2] */ + EXTI_4to15_IRQn = 7, /* 7 | EXTI[15:4] Interrupt GPIOx[15:4] */ + SPI3_IRQn = 8, /* 8 | Interrupt */ + DMA1_CH0_IRQn = 9, /* 9 | DMA1_CH0 Interrupt */ + DMA1_CH12_IRQn = 10, /* 10 | DMA1_CH12 Interrupt */ + DMA1_CH345_IRQn = 11, /* 11 | DMA1_CH345 Interrupt */ + ADC_COMP_IRQn = 12, /* 12 | ADC/COMP0-3 Interrupt EXTI[19:16]) */ + AD16C4T1_IRQn = 13, /* 13 | AD16C4T1 Interrupt */ + BS16T1_IRQn = 14, /* 14 | BS16T1 Interrupt */ + GP32C4T1_IRQn = 15, /* 15 | GP32C4T1 Interrupt */ + GP16C4T1_IRQn = 16, /* 16 | GP16C4T1 Interrupt */ + GP16C4T2_IRQn = 17, /* 17 | GP16C4T2 Interrupt */ + GP16C4T3_IRQn = 18, /* 18 | GP16C4T3 Interrupt */ + GP16C2T1_IRQn = 19, /* 19 | GP16C2T1 Interrupt */ + GP16C2T2_IRQn = 20, /* 20 | GP16C2T2 Interrupt */ + GP16C2T3_IRQn = 21, /* 21 | GP16C2T3 Interrupt */ + GP16C2T4_IRQn = 22, /* 22 | GP16C2T4 Interrupt */ + I2C1_IRQn = 23, /* 23 | I2C1 Interrupt */ + I2C2_IRQn = 24, /* 24 | I2C2 Interrupt */ + SPI1_IRQn = 25, /* 25 | SPI1 Interrupt */ + I2S1_IRQn = 25, /* 25 | I2S1 Interrupt */ + SPI2_IRQn = 26, /* 26 | SPI2 Interrupt */ + UART1_IRQn = 27, /* 27 | UART1 Interrupt */ + UART2_IRQn = 28, /* 28 | UART2 Interrupt */ + UART3_AES_IRQn = 29, /* 29 | UART3_AES Interrupt */ + UART4_KBCU_IRQn = 30, /* 30 | SUART1/2 Interrupt */ + USB_IRQn = 31 /* 31 | USB Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +/* Includes-------------------------------------------------------------------------------*/ + +#include "core_cm0.h" +#include +#include +#include "system_fs026.h" +/** + * @brief these files declare Peripheral register bit_definition. + */ +#include "reg_gpio.h" +#include "reg_dma.h" +#include "reg_aes.h" +#include "reg_crc.h" +#include "reg_calc.h" +#include "reg_kbcu.h" +#include "reg_usb.h" +#include "reg_csu.h" +#include "reg_rtc.h" + +#include "reg_exti.h" +#include "reg_uart.h" +#include "reg_spi.h" +#include "reg_i2c.h" +#include "reg_timer.h" +#include "reg_wwdt.h" +#include "reg_iwdt.h" +#include "reg_adc.h" +#include "reg_cmp.h" + +#include "reg_rcu.h" +#include "reg_syscfg.h" +#include "reg_fc.h" +#include "reg_mswd.h" +#include "reg_tick.h" + +/******************************************************************************/ +/* Peripheral register */ +/******************************************************************************/ + +/* allow anonymous structures and anonymous enumeration */ +/* #pragma anon_unions */ + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ + +/********************* Base addresses *************************/ +#define FLASH_BASE (0x08000000UL) // EFLASH Main (128K Bytes) +#define FLASH_INFO_BASE (0x1FFFE000UL) // EFLASH Info ( 4K Bytes) - Boot Loader Memory +#define SRAM_BASE (0x20000000UL) +#define APB1_BASE (0x40000000UL) +#define APB2_BASE (0x40010000UL) +#define AHB1_BASE (0x40020000UL) +#define AHB2_BASE (0x48000000UL) +#define CM0IN_BASE (0xE0000000UL) + +/* Cortex簧-M0 internal Peripherals - CM0IN_BASE: 0xE0000000*/ +#define TICK_BASE (CM0IN_BASE + 0xE010) + +#define SRAM1_BASE (SRAM_BASE + 0x0000) // SRAM1 Memory ( 8K Bytes) +#define SRAM2_BASE (SRAM_BASE + 0x2000) // SRAM2 Memory ( 8K Bytes) +#define STACK_SIZE 0x00000400>>2 // Stack size (in Words) + +/***************** peripherals base addresses ********************/ +/* APB1 */ +#define GP32C4T1_BASE (APB1_BASE + 0x0000) +#define GP16C4T1_BASE (APB1_BASE + 0x0400) +#define GP16C4T2_BASE (APB1_BASE + 0x0800) +#define GP16C4T3_BASE (APB1_BASE + 0x0C00) +#define BS16T1_BASE (APB1_BASE + 0x1000) +#define WWDT_BASE (APB1_BASE + 0x2C00) +#define IWDT_BASE (APB1_BASE + 0x3000) +#define SPI2_BASE (APB1_BASE + 0x3800) +#define SPI3_BASE (APB1_BASE + 0x3C00) +#define UART2_BASE (APB1_BASE + 0x4400) +#define UART3_BASE (APB1_BASE + 0x4800) +#define UART4_BASE (APB1_BASE + 0x4C00) +#define I2C1_BASE (APB1_BASE + 0x5400) +#define I2C2_BASE (APB1_BASE + 0x5800) +/* APB2 */ +#define EXTI_BASE (APB2_BASE + 0x0400) +#define ADC_BASE (APB2_BASE + 0x2400) +#define AD16C4T1_BASE (APB2_BASE + 0x2C00) +#define SPI1_BASE (APB2_BASE + 0x3000) +#define I2S1_BASE (APB2_BASE + 0x3000) +#define UART1_BASE (APB2_BASE + 0x3800) +#define GP16C2T1_BASE (APB2_BASE + 0x4000) +#define GP16C2T2_BASE (APB2_BASE + 0x4400) +#define GP16C2T3_BASE (APB2_BASE + 0x4800) +#define GP16C2T4_BASE (APB2_BASE + 0x4C00) +#define DBGMCU_BASE (APB2_BASE + 0x5800) +#define CMP_BASE (APB2_BASE + 0x5C00) +/* AHB1 */ +#define DMA1_BASE (AHB1_BASE + 0x0000) +#define RCU_BASE (AHB1_BASE + 0x1000) +#define SYSCFG_BASE (AHB1_BASE + 0x1400) +#define OPT_BASE (AHB1_BASE + 0x14F0) +#define RTC_BASE (AHB1_BASE + 0x1800) +#define KBCU_BASE (AHB1_BASE + 0x1C00) +#define EFLASH_BASE (AHB1_BASE + 0x2000) +#define CSU_BASE (AHB1_BASE + 0x2800) +#define MSWD_BASE (AHB1_BASE + 0x2C00) +#define CRC_BASE (AHB1_BASE + 0x3000) +#define AES_BASE (AHB1_BASE + 0x3400) +#define USB_BASE (AHB1_BASE + 0x3800) +#define CALC_BASE (AHB1_BASE + 0x3C00) +/* AHB2 */ +#define GPIOA_BASE (AHB2_BASE + 0x0000) +#define GPIOB_BASE (AHB2_BASE + 0x0400) +#define GPIOC_BASE (AHB2_BASE + 0x0800) +#define GPIOD_BASE (AHB2_BASE + 0x0C00) +#define GPIOE_BASE (AHB2_BASE + 0x1000) +#define GPIOF_BASE (AHB2_BASE + 0x1400) +#define MBIST_BASE (AHB2_BASE + 0x3C00) + +/********************* Peripheral declaration *************************/ +#define TICK (( SYST_TypeDef *) TICK_BASE) +#define GPIOA (( GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB (( GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC (( GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD (( GPIO_TypeDef *) GPIOD_BASE) +#define MBIST (( MBIST_TypeDef *) MBIST_BASE) +#define DMA1 (( DMA_TypeDef *) DMA1_BASE) +#define RCU (( RCU_TypeDef *) RCU_BASE) +#define SYSCFG (( SYSCFG_TypeDef *) SYSCFG_BASE) +#define OPT (( OPT_TypeDef *) OPT_BASE) +#define RTC (( RTC_TypeDef *) RTC_BASE) +#define KBCU (( KBCU_TypeDef *) KBCU_BASE) +#define FC (( FC_TypeDef *) EFLASH_BASE) +#define CSU (( CSU_TypeDef *) CSU_BASE) +#define MSWD (( MSWD_TypeDef *) MSWD_BASE) +#define CRC (( CRC_TypeDef *) CRC_BASE) +#define AES (( AES_TypeDef *) AES_BASE) +#define USB (( USB_TypeDef *) USB_BASE) +#define USBH (( USB_TypeDef *) USB_BASE) +#define USBD (( USB_TypeDef *) USB_BASE) +#define CALC (( CALC_TypeDef *) CALC_BASE) +#define EXTI (( EXTI_TypeDef *) EXTI_BASE) +#define ADC (( ADC_TypeDef *) ADC_BASE) +#define AD16C4T1 (( TIMER_TypeDef *) AD16C4T1_BASE) +#define SPI1 (( SPI_TypeDef *) SPI1_BASE) +#define I2S1 (( I2S_TypeDef *) I2S1_BASE) +#define UART1 (( UART_TypeDef *) UART1_BASE) +#define GP16C2T1 (( TIMER_TypeDef *) GP16C2T1_BASE) +#define GP16C2T2 (( TIMER_TypeDef *) GP16C2T2_BASE) +#define GP16C2T3 (( TIMER_TypeDef *) GP16C2T3_BASE) +#define GP16C2T4 (( TIMER_TypeDef *) GP16C2T4_BASE) +#define CMP (( CMP_TypeDef *) CMP_BASE) +#define GP32C4T1 (( TIMER_TypeDef *) GP32C4T1_BASE) +#define GP16C4T1 (( TIMER_TypeDef *) GP16C4T1_BASE) +#define GP16C4T2 (( TIMER_TypeDef *) GP16C4T2_BASE) +#define GP16C4T3 (( TIMER_TypeDef *) GP16C4T3_BASE) +#define BS16T1 (( TIMER_TypeDef *) BS16T1_BASE) +#define WWDT (( WWDT_TypeDef *) WWDT_BASE) +#define IWDT (( IWDT_TypeDef *) IWDT_BASE) +#define SPI2 (( SPI_TypeDef *) SPI2_BASE) +#define SPI3 (( SPI_TypeDef *) SPI3_BASE) +#define UART2 (( UART_TypeDef *) UART2_BASE) +#define UART3 (( UART_TypeDef *) UART3_BASE) +#define UART4 (( UART_TypeDef *) UART4_BASE) +#define I2C1 (( I2C_TypeDef *) I2C1_BASE) +#define I2C2 (( I2C_TypeDef *) I2C2_BASE) + +/* Special stuff */ +#define MSG_INCR ( __IO uint8_t *) (DBGMCU_BASE + 0x50) +#define MSG_WR ( __IO uint32_t *) (DBGMCU_BASE + 0x54) +#define MSG_END ( __IO uint32_t *) (DBGMCU_BASE + 0x58) +#define MSG_INCR_S ( __IO uint32_t *) (DBGMCU_BASE + 0x5C) +#define MSG_INCR_X ( __IO uint32_t *) (DBGMCU_BASE + 0x60) +#define MSG_INCR_B ( __IO uint32_t *) (DBGMCU_BASE + 0x64) +#define MSG_PTR ( __IO uint8_t **) (DBGMCU_BASE + 0x68) +#define MSG_INCR_D ( __IO uint32_t *) (DBGMCU_BASE + 0x78) +#define INCR_ERR_CNT ( __IO uint32_t *) (DBGMCU_BASE + 0x6C) + +#define END_SIM *MSG_END +#define SIM_FAIL 0xFFFFAAAA +#define SIM_PASS 0xFFFF5555 +/******************************************************************************/ +/* macros */ +/******************************************************************************/ + +/** @addtogroup Public_macros + * @{ + */ +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#define __INLINE__ __inline +#else +#define __INLINE__ inline +#endif + +#define __isr__ + +#define UNUSED(x) ((void)(x)) + +#ifdef USE_ASSERT +#define assert_param(x) \ + do \ + { \ + if (!(x)) \ + { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ + } while (0) +#else +#define assert_param(x) +#endif + +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) + +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) &\ + (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) + +#define SET_BIT(REG, SETMASK) ((REG) |= (SETMASK)) + +#define CLEAR_BIT(REG, SETMASK) ((REG) &= ~(SETMASK)) + +#define READ_BIT(REG, SETMASK) ((REG) & (SETMASK)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +#define BYTE0(x) (uint8_t)(((x)>>0)&0xff) + +#define BYTE1(x) (uint8_t)(((x)>>8)&0xff) + +#define BYTE2(x) (uint8_t)(((x)>>16)&0xff) + +#define BYTE3(x) (uint8_t)(((x)>>24)&0xff) + +#define DATA16(d1,d0) (uint16_t)(((uint16_t)(d1)<<8)|(d0)) + +#define DATA32(d3,d2,d1,d0) (uint32_t)(((uint32_t)(d3)<<24)|((uint32_t)(d2)<<16)|((uint32_t)(d1)<<8)|(d0)) + +/** + * @} + */ + +/******************************************************************************/ +/* types */ +/******************************************************************************/ +/** @addtogroup Public_types + * @{ + */ +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} TypeFunc, FuncState; +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) + +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus, PinStatus; + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +typedef enum +{ + BIT_RESET = 0x0, + BIT_SET = 0x1, +} BitStatus; + +//typedef enum +//{ +// FALSE = 0x0, +// TRUE = 0x1, +//} TypeBool; + +#define FALSE 0 +#define TRUE 1 + +#define CPU_CLOCK (72000000) + +typedef enum +{ + UNLOCK = 0x0, + LOCK = 0x1, +} LockState; +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + +/** + * @} Public_types + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @} es32fs026 + */ + +/** + * @} CMSIS + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_adc.c b/os/common/ext/CMSIS/ES32/FS026/md/md_adc.c new file mode 100644 index 00000000000..62b5d702fc0 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_adc.c @@ -0,0 +1,346 @@ +/********************************************************************************** + * + * @file md_adc.c + * @brief md_adc C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 28 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_adc.h" +#include "md_syscfg.h" +#include +#include "md_fc.h" +#define ADC_DMA + +/** @addtogroup Micro_Driver + * @{ + */ + + +/** @defgroup ADC ADC + * @brief ADC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Private function prototypes ------------------------------------------------*/ + +void (*md_adc_nchs_sample[])(ADC_TypeDef *, uint32_t) = +{ + md_adc_set_normal_sequence_selection_1th, + md_adc_set_normal_sequence_selection_2th, + md_adc_set_normal_sequence_selection_3th, + md_adc_set_normal_sequence_selection_4th, + md_adc_set_normal_sequence_selection_5th, + md_adc_set_normal_sequence_selection_6th, + md_adc_set_normal_sequence_selection_7th, + md_adc_set_normal_sequence_selection_8th, + md_adc_set_normal_sequence_selection_9th, + md_adc_set_normal_sequence_selection_10th, + md_adc_set_normal_sequence_selection_11th, + md_adc_set_normal_sequence_selection_12th, + md_adc_set_normal_sequence_selection_13th, + md_adc_set_normal_sequence_selection_14th, + md_adc_set_normal_sequence_selection_15th, + md_adc_set_normal_sequence_selection_16th +}; + +void (*md_adc_ichs_sample[])(ADC_TypeDef *, uint32_t) = +{ + md_adc_set_inj_sequence_selection_1th, + md_adc_set_inj_sequence_selection_2th, + md_adc_set_inj_sequence_selection_3th, + md_adc_set_inj_sequence_selection_4th, +}; + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup ADC_PUB_FUNC ADC Public Functions + * @brief ADC Public Functions + * @{ + */ + +/** + * @brief ADC Initialization Function. + * @param ADC Instance. + * @param ADC_InitStruct. + * @retval None + */ +void md_adc_init(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruct) +{ + while (md_adc_is_enabled_calibration(ADCx)); + + md_adc_set_adc_clock_predivider(ADC, ADC_InitStruct->CKDIV); + + md_adc_enable_adcpower(ADCx); + + while (!md_adc_is_active_flag_adc_ready(ADCx)); + + while ((md_adc_get_start_inj(ADCx) == MD_ADC_CON_ISTART_START_INJECTED)); + + while ((md_adc_get_start_normal(ADCx) == MD_ADC_CON_NSTART_START_REGULAR)); + + md_adc_set_data_alignment(ADCx, ADC_InitStruct->ALIGN); + md_adc_set_resolution_selection(ADCx, ADC_InitStruct->RSEL); + md_adc_set_convsersion_mode(ADCx, ADC_InitStruct->Regular_CM); + +#ifdef ADC_DMA + md_adc_enable_dma_access(ADCx); +#else + md_adc_disable_dma_access(ADCx); +#endif + +} + +/** + * @brief ADC conversion Function. + * @param ADC Instance. + * @param ADC_InitStruct. + * @param sample_seq_channel + * @retval None + */ +void md_adc_sequence_conversion(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruct, uint32_t *sample_seq_channel) +{ + uint8_t i; + + if (ADC_InitStruct->Regular_Injected == MD_ADC_MODE_NCHS) + { + md_adc_set_normal_sequence_length(ADCx, ADC_InitStruct->Cnt); + + for (i = 0; i <= ADC_InitStruct->Cnt; i++) + md_adc_nchs_sample[i](ADCx, sample_seq_channel[i]); + +// md_adc_set_start_normal(ADCx, MD_ADC_CON_NSTART_START_REGULAR); + } + else + { + md_adc_set_inj_sequence_length(ADCx, ADC_InitStruct->Cnt); + + for (i = 0; i <= ADC_InitStruct->Cnt; i++) + md_adc_ichs_sample[i](ADCx, sample_seq_channel[i]); + +// md_adc_set_start_inj(ADCx, MD_ADC_CON_ISTART_START_INJECTED); + } + +} + +/** + * @brief ADC software calibration + * @param ADC Instance. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: calibration success + * - ERROR: calibration fail + */ +ErrorStatus md_adc_software_calibration(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruct) +{ + //ADC input APB clock 12MHz + uint8_t clkdiv; + uint16_t adc_data_1 = 0; + uint16_t adc_data_15 = 0; + + int16_t adc_offset = 0; + uint16_t adc_gain = 0; + + float temp_adc_offset = 0.0f; + + md_syscfg_set_vref_source(SYSCFG, MD_SYSCFG_PWR_VDDA); // VRES choose VDDA + md_syscfg_enable_vref(SYSCFG); + //ADC Setting + md_adc_set_convsersion_mode(ADC, MD_ADC_CFG_CM_SINGLE); // 1:Continuous + md_adc_set_resolution_selection(ADC, MD_ADC_CFG_RSEL_12BIT); // 12-bit resolution + md_adc_set_normal_sequence_selection_1th(ADC, MD_ADC_NCHS1_NS1_CH18); // channel number(16:Temperature) + md_adc_set_adc_clock_predivider(ADC, ADC_InitStruct->CKDIV); + + if (ADC_InitStruct->CKDIV == MD_ADC_SMPT1_CKDIV_DIV1) + clkdiv = 1; + else if (ADC_InitStruct->CKDIV == MD_ADC_SMPT1_CKDIV_DIV2) + clkdiv = 2; + else if (ADC_InitStruct->CKDIV == MD_ADC_SMPT1_CKDIV_DIV4) + clkdiv = 4; + else if (ADC_InitStruct->CKDIV == MD_ADC_SMPT1_CKDIV_DIV6) + clkdiv = 6; + else if (ADC_InitStruct->CKDIV == MD_ADC_SMPT1_CKDIV_DIV8) + clkdiv = 8; + + if ((SystemFrequency_APBClk / clkdiv) <= 12000000) + md_adc_set_sampletime_channel_18(ADCx, 0x40); //Sample Time Cycle + else + md_adc_set_sampletime_channel_18(ADCx, 0x80); //Sample Time Cycle + + //CLEAR CALCR + md_adc_set_gain_factor(ADCx, 1024); + md_adc_set_offset_factor(ADCx, 0); + + //ADC ENABLE + md_adc_enable_adcpower(ADCx); + + while (!md_adc_is_active_flag_adc_ready(ADCx)); + + // -------------------------------------------------------- + // 1/16 Sample + md_adc_set_vref_level(ADCx, MD_ADC_CCR_REFINTS_1DIV16); + md_adc_set_start_normal(ADCx, MD_ADC_CON_NSTART_START_REGULAR); + + while (md_adc_is_active_flag_normal_status(ADCx)); + + adc_data_1 = md_adc_get_normal_data(ADCx); + + // -------------------------------------------------------- + // 15/16 Sample + md_adc_set_vref_level(ADCx, MD_ADC_CCR_REFINTS_15DIV16); + md_adc_set_start_normal(ADCx, MD_ADC_CON_NSTART_START_REGULAR); + + while (md_adc_is_active_flag_normal_status(ADCx)); + + adc_data_15 = md_adc_get_normal_data(ADCx); + + // -------------------------------------------------------- + + + + temp_adc_offset = (float)((15 * adc_data_1) - adc_data_15) / 14; + + if (temp_adc_offset > 0) + { + adc_offset = (int16_t)(temp_adc_offset + 0.5); + } + else + { + adc_offset = (int16_t)(temp_adc_offset - 0.5); + } + + + + adc_gain = (uint16_t)((3584 * 1024) / (float)(adc_data_15 - adc_data_1) + 0.5); + + + + +// printf("adc_data_1:%d\r\n",adc_data_1); +// printf("adc_data_15:%d\r\n",adc_data_15); +// printf("adc_offset:%d\r\n",adc_offset); +// printf("adc_gain:%d\r\n",adc_gain); + + md_adc_set_gain_factor(ADCx, adc_gain); + md_adc_set_offset_factor(ADCx, adc_offset); + + // -------------------------------------------------------- + // Reset the used register to default + md_adc_set_convsersion_mode(ADCx, 0); + md_adc_set_resolution_selection(ADCx, MD_ADC_CFG_RSEL_6BIT); + md_adc_set_normal_sequence_selection_1th(ADCx, MD_ADC_NCHS1_NS1_CH0); + md_adc_set_adc_clock_predivider(ADCx, MD_ADC_SMPT1_CKDIV_DIV1); + md_adc_set_sampletime_channel_18(ADCx, 0); + md_adc_set_icr(ADCx, 0xFFFE); + + return SUCCESS; +} + +ErrorStatus md_adc_optionbyte_calibration(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruct) +{ + int8_t adc_offset = 0; + uint32_t adc_gain = 1024; + uint32_t cal_value = 0; + md_fc_read_info(ADC_CALIBRATION_ADDR, &cal_value); + + adc_gain = (cal_value & 0xFFF); + adc_offset = (cal_value >> 16) & 0xFF; + + //ADC ENABLE + md_adc_enable_adcpower(ADCx); + md_adc_set_gain_factor(ADCx, adc_gain); + md_adc_set_offset_factor(ADCx, adc_offset); + return SUCCESS; +} + +/** + * @brief Get ADC calibration Coefficient + * @param OCOMCOE. + * @param GCOMCOE. + * @retval None + */ +void md_adc_get_calibration(ADC_TypeDef *ADCx, uint8_t *OCOMCOE, uint16_t *GCOMCOE) +{ + *OCOMCOE = (uint8_t)md_adc_get_offset_factor(ADCx); + *GCOMCOE = (uint16_t)md_adc_get_gain_factor(ADCx); +} + +/** + * @brief Set ADC calibration Mode + * @param ADC Instance. + * @param ADC_InitStruct. + * @param + * @retval None + */ +ErrorStatus md_adc_calibration(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruct) +{ + uint32_t cal_value = 0; + md_fc_read_info(ADC_CALIBRATION_ADDR, &cal_value); + + + if (cal_value == 0xFFFFFFFF) + { + return md_adc_software_calibration(ADCx, ADC_InitStruct); + } + else + { + return md_adc_optionbyte_calibration(ADCx, ADC_InitStruct); + } + +} + +/** + * @brief Get the ADC data + * @param ADC Instance. + * @retval adc data + */ +uint16_t md_adc_get_data(ADC_TypeDef *ADCx) +{ + uint16_t adc_data; + + adc_data = md_adc_get_normal_data(ADCx); + + return adc_data; +} + + +/** + * @} ADC_PUB_FUNC ADC Public Functions + */ + +/** + * @} ADC + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_adc.h b/os/common/ext/CMSIS/ES32/FS026/md/md_adc.h new file mode 100644 index 00000000000..de8bbde4c3a --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_adc.h @@ -0,0 +1,5289 @@ +/********************************************************************************** + * + * @file md_adc.h + * @brief header file of md_adc.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 28 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_ADC_H__ +#define __MD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_ADC ADC + * @brief ADC micro driver + * @{ + */ + +/** @defgroup MD_ADC_Pubulic_Types ADC Pubulic Types + * @{ + */ + +/** + * @brief ADC Init structure. + */ +typedef struct +{ + uint8_t ALIGN; + uint32_t RSEL; + uint8_t Regular_Injected ; + uint16_t Regular_CM; + uint8_t Cnt; + uint8_t CKDIV; +} md_adc_initial; +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Macros ADC Public Macros + * @{ + */ + +#define MD_ADC_CON_ADCAL_CALIBRATION_COMPLETE (0x00000000U) +#define MD_ADC_CON_ADCAL_CALIBRATION (0x00000001U) + +#define MD_ADC_CON_ISTPC_NOSTOP_INJECTED (0x00000000U) +#define MD_ADC_CON_ISTPC_STOP_INJECTED (0x00000001U) + +#define MD_ADC_CON_NSTPC_NOSTOP_REGULAR (0x00000000U) +#define MD_ADC_CON_NSTPC_STOP_REGULAR (0x00000001U) + +#define MD_ADC_CON_ISTART_NOADC_INJECTED (0x00000000U) +#define MD_ADC_CON_ISTART_START_INJECTED (0x00000001U) + +#define MD_ADC_CON_NSTART_NOADC_REGULAR (0x00000000U) +#define MD_ADC_CON_NSTART_START_REGULAR (0x00000001U) + +#define MD_ADC_CON_ADCEN_DISABLE (0x00000000U) +#define MD_ADC_CON_ADCEN_ENABLE (0x00000001U) + + +#define MD_ADC_CFG_AWDCH_CH0 (0x00000000U) +#define MD_ADC_CFG_AWDCH_CH1 (0x00000001U) +#define MD_ADC_CFG_AWDCH_CH2 (0x00000002U) +#define MD_ADC_CFG_AWDCH_CH3 (0x00000003U) +#define MD_ADC_CFG_AWDCH_CH4 (0x00000004U) +#define MD_ADC_CFG_AWDCH_CH5 (0x00000005U) +#define MD_ADC_CFG_AWDCH_CH6 (0x00000006U) +#define MD_ADC_CFG_AWDCH_CH7 (0x00000007U) +#define MD_ADC_CFG_AWDCH_CH8 (0x00000008U) +#define MD_ADC_CFG_AWDCH_CH9 (0x00000009U) +#define MD_ADC_CFG_AWDCH_CH10 (0x0000000AU) +#define MD_ADC_CFG_AWDCH_CH11 (0x0000000BU) +#define MD_ADC_CFG_AWDCH_CH12 (0x0000000CU) +#define MD_ADC_CFG_AWDCH_CH13 (0x0000000DU) +#define MD_ADC_CFG_AWDCH_CH14 (0x0000000EU) +#define MD_ADC_CFG_AWDCH_CH15 (0x0000000FU) +#define MD_ADC_CFG_AWDCH_CH16 (0x00000010U) +#define MD_ADC_CFG_AWDCH_CH17 (0x00000011U) +#define MD_ADC_CFG_AWDCH_CH18 (0x00000012U) + +#define MD_ADC_CFG_AWDSGL_ALL_CH (0x00000000U) +#define MD_ADC_CFG_AWDSGL_SINGLE_CH (0x00000001U) + +#define MD_ADC_CFG_ETRGN_1CH (0x00000000U) +#define MD_ADC_CFG_ETRGN_2CH (0x00000001U) +#define MD_ADC_CFG_ETRGN_3CH (0x00000002U) +#define MD_ADC_CFG_ETRGN_4CH (0x00000003U) +#define MD_ADC_CFG_ETRGN_5CH (0x00000004U) +#define MD_ADC_CFG_ETRGN_6CH (0x00000005U) +#define MD_ADC_CFG_ETRGN_7CH (0x00000006U) +#define MD_ADC_CFG_ETRGN_8CH (0x00000007U) + +#define MD_ADC_CFG_CM_SINGLE (0x00000000U) +#define MD_ADC_CFG_CM_CONTINUOUS (0x00000001U) + +#define MD_ADC_CFG_OVRMOD_PRESERVED (0x00000000U) +#define MD_ADC_CFG_OVRMOD_OVERWRITTEN (0x00000001U) + +#define MD_ADC_CFG_NETS_DISABLE (0x00000000U) +#define MD_ADC_CFG_NETS_RISING (0x00000001U) +#define MD_ADC_CFG_NETS_FALLING (0x00000002U) +#define MD_ADC_CFG_NETS_BOTH (0x00000003U) + +#define MD_ADC_CFG_NEXTSEL_AD16C4T1_CH1 (0x00000000U) +#define MD_ADC_CFG_NEXTSEL_AD16C4T1_CH2 (0x00000001U) +#define MD_ADC_CFG_NEXTSEL_AD16C4T1_CH3 (0x00000002U) +#define MD_ADC_CFG_NEXTSEL_GP32C4T1_CH2 (0x00000003U) +#define MD_ADC_CFG_NEXTSEL_GP32C4T1_CH3 (0x00000004U) +#define MD_ADC_CFG_NEXTSEL_GP32C4T1_CH4 (0x00000005U) +#define MD_ADC_CFG_NEXTSEL_GP32C4T1_TRGOUT (0x00000006U) +#define MD_ADC_CFG_NEXTSEL_GP16C4T1_CH1 (0x00000007U) +#define MD_ADC_CFG_NEXTSEL_GP16C4T1_TRGOUT (0x00000008U) +#define MD_ADC_CFG_NEXTSEL_GP16C4T2_CH4 (0x00000009U) +#define MD_ADC_CFG_NEXTSEL_GP16C4T3_CH1 (0x0000000AU) +#define MD_ADC_CFG_NEXTSEL_GP16C4T3_CH2 (0x0000000BU) +#define MD_ADC_CFG_NEXTSEL_GP16C4T3_CH3 (0x0000000CU) +#define MD_ADC_CFG_NEXTSEL_BS16T1_TRGOUT (0x0000000DU) +#define MD_ADC_CFG_NEXTSEL_RTC (0x0000000EU) +#define MD_ADC_CFG_NEXTSEL_EXTI_TRG0 (0x0000000FU) + +#define MD_ADC_CFG_ALIGN_RIGHT (0x00000000U) +#define MD_ADC_CFG_ALIGN_LEFT (0x00000001U) + +#define MD_ADC_CFG_RSEL_6BIT (0x00000000U) +#define MD_ADC_CFG_RSEL_8BIT (0x00000001U) +#define MD_ADC_CFG_RSEL_10BIT (0x00000002U) +#define MD_ADC_CFG_RSEL_12BIT (0x00000003U) + +#define MD_ADC_SMPT1_CKDIV_DIV1 (0x00000000U) +#define MD_ADC_SMPT1_CKDIV_DIV2 (0x00000001U) +#define MD_ADC_SMPT1_CKDIV_DIV4 (0x00000002U) +#define MD_ADC_SMPT1_CKDIV_DIV6 (0x00000003U) +#define MD_ADC_SMPT1_CKDIV_DIV8 (0x00000004U) + +#define MD_ADC_NCHS1_NS4_CH0 (0x00000000U) +#define MD_ADC_NCHS1_NS4_CH1 (0x00000001U) +#define MD_ADC_NCHS1_NS4_CH2 (0x00000002U) +#define MD_ADC_NCHS1_NS4_CH3 (0x00000003U) +#define MD_ADC_NCHS1_NS4_CH4 (0x00000004U) +#define MD_ADC_NCHS1_NS4_CH5 (0x00000005U) +#define MD_ADC_NCHS1_NS4_CH6 (0x00000006U) +#define MD_ADC_NCHS1_NS4_CH7 (0x00000007U) +#define MD_ADC_NCHS1_NS4_CH8 (0x00000008U) +#define MD_ADC_NCHS1_NS4_CH9 (0x00000009U) +#define MD_ADC_NCHS1_NS4_CH10 (0x0000000AU) +#define MD_ADC_NCHS1_NS4_CH11 (0x0000000BU) +#define MD_ADC_NCHS1_NS4_CH12 (0x0000000CU) +#define MD_ADC_NCHS1_NS4_CH13 (0x0000000DU) +#define MD_ADC_NCHS1_NS4_CH14 (0x0000000EU) +#define MD_ADC_NCHS1_NS4_CH15 (0x0000000FU) +#define MD_ADC_NCHS1_NS4_CH16 (0x00000010U) +#define MD_ADC_NCHS1_NS4_CH17 (0x00000011U) +#define MD_ADC_NCHS1_NS4_CH18 (0x00000012U) + +#define MD_ADC_NCHS1_NS3_CH0 (0x00000000U) +#define MD_ADC_NCHS1_NS3_CH1 (0x00000001U) +#define MD_ADC_NCHS1_NS3_CH2 (0x00000002U) +#define MD_ADC_NCHS1_NS3_CH3 (0x00000003U) +#define MD_ADC_NCHS1_NS3_CH4 (0x00000004U) +#define MD_ADC_NCHS1_NS3_CH5 (0x00000005U) +#define MD_ADC_NCHS1_NS3_CH6 (0x00000006U) +#define MD_ADC_NCHS1_NS3_CH7 (0x00000007U) +#define MD_ADC_NCHS1_NS3_CH8 (0x00000008U) +#define MD_ADC_NCHS1_NS3_CH9 (0x00000009U) +#define MD_ADC_NCHS1_NS3_CH10 (0x0000000AU) +#define MD_ADC_NCHS1_NS3_CH11 (0x0000000BU) +#define MD_ADC_NCHS1_NS3_CH12 (0x0000000CU) +#define MD_ADC_NCHS1_NS3_CH13 (0x0000000DU) +#define MD_ADC_NCHS1_NS3_CH14 (0x0000000EU) +#define MD_ADC_NCHS1_NS3_CH15 (0x0000000FU) +#define MD_ADC_NCHS1_NS3_CH16 (0x00000010U) +#define MD_ADC_NCHS1_NS3_CH17 (0x00000011U) +#define MD_ADC_NCHS1_NS3_CH18 (0x00000012U) + +#define MD_ADC_NCHS1_NS2_CH0 (0x00000000U) +#define MD_ADC_NCHS1_NS2_CH1 (0x00000001U) +#define MD_ADC_NCHS1_NS2_CH2 (0x00000002U) +#define MD_ADC_NCHS1_NS2_CH3 (0x00000003U) +#define MD_ADC_NCHS1_NS2_CH4 (0x00000004U) +#define MD_ADC_NCHS1_NS2_CH5 (0x00000005U) +#define MD_ADC_NCHS1_NS2_CH6 (0x00000006U) +#define MD_ADC_NCHS1_NS2_CH7 (0x00000007U) +#define MD_ADC_NCHS1_NS2_CH8 (0x00000008U) +#define MD_ADC_NCHS1_NS2_CH9 (0x00000009U) +#define MD_ADC_NCHS1_NS2_CH10 (0x0000000AU) +#define MD_ADC_NCHS1_NS2_CH11 (0x0000000BU) +#define MD_ADC_NCHS1_NS2_CH12 (0x0000000CU) +#define MD_ADC_NCHS1_NS2_CH13 (0x0000000DU) +#define MD_ADC_NCHS1_NS2_CH14 (0x0000000EU) +#define MD_ADC_NCHS1_NS2_CH15 (0x0000000FU) +#define MD_ADC_NCHS1_NS2_CH16 (0x00000010U) +#define MD_ADC_NCHS1_NS2_CH17 (0x00000011U) +#define MD_ADC_NCHS1_NS2_CH18 (0x00000012U) + +#define MD_ADC_NCHS1_NS1_CH0 (0x00000000U) +#define MD_ADC_NCHS1_NS1_CH1 (0x00000001U) +#define MD_ADC_NCHS1_NS1_CH2 (0x00000002U) +#define MD_ADC_NCHS1_NS1_CH3 (0x00000003U) +#define MD_ADC_NCHS1_NS1_CH4 (0x00000004U) +#define MD_ADC_NCHS1_NS1_CH5 (0x00000005U) +#define MD_ADC_NCHS1_NS1_CH6 (0x00000006U) +#define MD_ADC_NCHS1_NS1_CH7 (0x00000007U) +#define MD_ADC_NCHS1_NS1_CH8 (0x00000008U) +#define MD_ADC_NCHS1_NS1_CH9 (0x00000009U) +#define MD_ADC_NCHS1_NS1_CH10 (0x0000000AU) +#define MD_ADC_NCHS1_NS1_CH11 (0x0000000BU) +#define MD_ADC_NCHS1_NS1_CH12 (0x0000000CU) +#define MD_ADC_NCHS1_NS1_CH13 (0x0000000DU) +#define MD_ADC_NCHS1_NS1_CH14 (0x0000000EU) +#define MD_ADC_NCHS1_NS1_CH15 (0x0000000FU) +#define MD_ADC_NCHS1_NS1_CH16 (0x00000010U) +#define MD_ADC_NCHS1_NS1_CH17 (0x00000011U) +#define MD_ADC_NCHS1_NS1_CH18 (0x00000012U) + +#define MD_ADC_NCHS1_NSL_1CON (0x00000000U) +#define MD_ADC_NCHS1_NSL_2CON (0x00000001U) +#define MD_ADC_NCHS1_NSL_3CON (0x00000002U) +#define MD_ADC_NCHS1_NSL_4CON (0x00000003U) +#define MD_ADC_NCHS1_NSL_5CON (0x00000004U) +#define MD_ADC_NCHS1_NSL_6CON (0x00000005U) +#define MD_ADC_NCHS1_NSL_7CON (0x00000006U) +#define MD_ADC_NCHS1_NSL_8CON (0x00000007U) +#define MD_ADC_NCHS1_NSL_9CON (0x00000008U) +#define MD_ADC_NCHS1_NSL_10CON (0x00000009U) +#define MD_ADC_NCHS1_NSL_11CON (0x0000000AU) +#define MD_ADC_NCHS1_NSL_12CON (0x0000000BU) +#define MD_ADC_NCHS1_NSL_13CON (0x0000000CU) +#define MD_ADC_NCHS1_NSL_14CON (0x0000000DU) +#define MD_ADC_NCHS1_NSL_15CON (0x0000000EU) +#define MD_ADC_NCHS1_NSL_16CON (0x0000000FU) + +#define MD_ADC_NCHS2_NS9_CH0 (0x00000000U) +#define MD_ADC_NCHS2_NS9_CH1 (0x00000001U) +#define MD_ADC_NCHS2_NS9_CH2 (0x00000002U) +#define MD_ADC_NCHS2_NS9_CH3 (0x00000003U) +#define MD_ADC_NCHS2_NS9_CH4 (0x00000004U) +#define MD_ADC_NCHS2_NS9_CH5 (0x00000005U) +#define MD_ADC_NCHS2_NS9_CH6 (0x00000006U) +#define MD_ADC_NCHS2_NS9_CH7 (0x00000007U) +#define MD_ADC_NCHS2_NS9_CH8 (0x00000008U) +#define MD_ADC_NCHS2_NS9_CH9 (0x00000009U) +#define MD_ADC_NCHS2_NS9_CH10 (0x0000000AU) +#define MD_ADC_NCHS2_NS9_CH11 (0x0000000BU) +#define MD_ADC_NCHS2_NS9_CH12 (0x0000000CU) +#define MD_ADC_NCHS2_NS9_CH13 (0x0000000DU) +#define MD_ADC_NCHS2_NS9_CH14 (0x0000000EU) +#define MD_ADC_NCHS2_NS9_CH15 (0x0000000FU) +#define MD_ADC_NCHS2_NS9_CH16 (0x00000010U) +#define MD_ADC_NCHS2_NS9_CH17 (0x00000011U) +#define MD_ADC_NCHS2_NS9_CH18 (0x00000012U) + +#define MD_ADC_NCHS2_NS8_CH0 (0x00000000U) +#define MD_ADC_NCHS2_NS8_CH1 (0x00000001U) +#define MD_ADC_NCHS2_NS8_CH2 (0x00000002U) +#define MD_ADC_NCHS2_NS8_CH3 (0x00000003U) +#define MD_ADC_NCHS2_NS8_CH4 (0x00000004U) +#define MD_ADC_NCHS2_NS8_CH5 (0x00000005U) +#define MD_ADC_NCHS2_NS8_CH6 (0x00000006U) +#define MD_ADC_NCHS2_NS8_CH7 (0x00000007U) +#define MD_ADC_NCHS2_NS8_CH8 (0x00000008U) +#define MD_ADC_NCHS2_NS8_CH9 (0x00000009U) +#define MD_ADC_NCHS2_NS8_CH10 (0x0000000AU) +#define MD_ADC_NCHS2_NS8_CH11 (0x0000000BU) +#define MD_ADC_NCHS2_NS8_CH12 (0x0000000CU) +#define MD_ADC_NCHS2_NS8_CH13 (0x0000000DU) +#define MD_ADC_NCHS2_NS8_CH14 (0x0000000EU) +#define MD_ADC_NCHS2_NS8_CH15 (0x0000000FU) +#define MD_ADC_NCHS2_NS8_CH16 (0x00000010U) +#define MD_ADC_NCHS2_NS8_CH17 (0x00000011U) +#define MD_ADC_NCHS2_NS8_CH18 (0x00000012U) + +#define MD_ADC_NCHS2_NS7_CH0 (0x00000000U) +#define MD_ADC_NCHS2_NS7_CH1 (0x00000001U) +#define MD_ADC_NCHS2_NS7_CH2 (0x00000002U) +#define MD_ADC_NCHS2_NS7_CH3 (0x00000003U) +#define MD_ADC_NCHS2_NS7_CH4 (0x00000004U) +#define MD_ADC_NCHS2_NS7_CH5 (0x00000005U) +#define MD_ADC_NCHS2_NS7_CH6 (0x00000006U) +#define MD_ADC_NCHS2_NS7_CH7 (0x00000007U) +#define MD_ADC_NCHS2_NS7_CH8 (0x00000008U) +#define MD_ADC_NCHS2_NS7_CH9 (0x00000009U) +#define MD_ADC_NCHS2_NS7_CH10 (0x0000000AU) +#define MD_ADC_NCHS2_NS7_CH11 (0x0000000BU) +#define MD_ADC_NCHS2_NS7_CH12 (0x0000000CU) +#define MD_ADC_NCHS2_NS7_CH13 (0x0000000DU) +#define MD_ADC_NCHS2_NS7_CH14 (0x0000000EU) +#define MD_ADC_NCHS2_NS7_CH15 (0x0000000FU) +#define MD_ADC_NCHS2_NS7_CH16 (0x00000010U) +#define MD_ADC_NCHS2_NS7_CH17 (0x00000011U) +#define MD_ADC_NCHS2_NS7_CH18 (0x00000012U) + +#define MD_ADC_NCHS2_NS6_CH0 (0x00000000U) +#define MD_ADC_NCHS2_NS6_CH1 (0x00000001U) +#define MD_ADC_NCHS2_NS6_CH2 (0x00000002U) +#define MD_ADC_NCHS2_NS6_CH3 (0x00000003U) +#define MD_ADC_NCHS2_NS6_CH4 (0x00000004U) +#define MD_ADC_NCHS2_NS6_CH5 (0x00000005U) +#define MD_ADC_NCHS2_NS6_CH6 (0x00000006U) +#define MD_ADC_NCHS2_NS6_CH7 (0x00000007U) +#define MD_ADC_NCHS2_NS6_CH8 (0x00000008U) +#define MD_ADC_NCHS2_NS6_CH9 (0x00000009U) +#define MD_ADC_NCHS2_NS6_CH10 (0x0000000AU) +#define MD_ADC_NCHS2_NS6_CH11 (0x0000000BU) +#define MD_ADC_NCHS2_NS6_CH12 (0x0000000CU) +#define MD_ADC_NCHS2_NS6_CH13 (0x0000000DU) +#define MD_ADC_NCHS2_NS6_CH14 (0x0000000EU) +#define MD_ADC_NCHS2_NS6_CH15 (0x0000000FU) +#define MD_ADC_NCHS2_NS6_CH16 (0x00000010U) +#define MD_ADC_NCHS2_NS6_CH17 (0x00000011U) +#define MD_ADC_NCHS2_NS6_CH18 (0x00000012U) + +#define MD_ADC_NCHS2_NS5_CH0 (0x00000000U) +#define MD_ADC_NCHS2_NS5_CH1 (0x00000001U) +#define MD_ADC_NCHS2_NS5_CH2 (0x00000002U) +#define MD_ADC_NCHS2_NS5_CH3 (0x00000003U) +#define MD_ADC_NCHS2_NS5_CH4 (0x00000004U) +#define MD_ADC_NCHS2_NS5_CH5 (0x00000005U) +#define MD_ADC_NCHS2_NS5_CH6 (0x00000006U) +#define MD_ADC_NCHS2_NS5_CH7 (0x00000007U) +#define MD_ADC_NCHS2_NS5_CH8 (0x00000008U) +#define MD_ADC_NCHS2_NS5_CH9 (0x00000009U) +#define MD_ADC_NCHS2_NS5_CH10 (0x0000000AU) +#define MD_ADC_NCHS2_NS5_CH11 (0x0000000BU) +#define MD_ADC_NCHS2_NS5_CH12 (0x0000000CU) +#define MD_ADC_NCHS2_NS5_CH13 (0x0000000DU) +#define MD_ADC_NCHS2_NS5_CH14 (0x0000000EU) +#define MD_ADC_NCHS2_NS5_CH15 (0x0000000FU) +#define MD_ADC_NCHS2_NS5_CH16 (0x00000010U) +#define MD_ADC_NCHS2_NS5_CH17 (0x00000011U) +#define MD_ADC_NCHS2_NS5_CH18 (0x00000012U) + +#define MD_ADC_NCHS3_NS14_CH0 (0x00000000U) +#define MD_ADC_NCHS3_NS14_CH1 (0x00000001U) +#define MD_ADC_NCHS3_NS14_CH2 (0x00000002U) +#define MD_ADC_NCHS3_NS14_CH3 (0x00000003U) +#define MD_ADC_NCHS3_NS14_CH4 (0x00000004U) +#define MD_ADC_NCHS3_NS14_CH5 (0x00000005U) +#define MD_ADC_NCHS3_NS14_CH6 (0x00000006U) +#define MD_ADC_NCHS3_NS14_CH7 (0x00000007U) +#define MD_ADC_NCHS3_NS14_CH8 (0x00000008U) +#define MD_ADC_NCHS3_NS14_CH9 (0x00000009U) +#define MD_ADC_NCHS3_NS14_CH10 (0x0000000AU) +#define MD_ADC_NCHS3_NS14_CH11 (0x0000000BU) +#define MD_ADC_NCHS3_NS14_CH12 (0x0000000CU) +#define MD_ADC_NCHS3_NS14_CH13 (0x0000000DU) +#define MD_ADC_NCHS3_NS14_CH14 (0x0000000EU) +#define MD_ADC_NCHS3_NS14_CH15 (0x0000000FU) +#define MD_ADC_NCHS3_NS14_CH16 (0x00000010U) +#define MD_ADC_NCHS3_NS14_CH17 (0x00000011U) +#define MD_ADC_NCHS3_NS14_CH18 (0x00000012U) + +#define MD_ADC_NCHS3_NS13_CH0 (0x00000000U) +#define MD_ADC_NCHS3_NS13_CH1 (0x00000001U) +#define MD_ADC_NCHS3_NS13_CH2 (0x00000002U) +#define MD_ADC_NCHS3_NS13_CH3 (0x00000003U) +#define MD_ADC_NCHS3_NS13_CH4 (0x00000004U) +#define MD_ADC_NCHS3_NS13_CH5 (0x00000005U) +#define MD_ADC_NCHS3_NS13_CH6 (0x00000006U) +#define MD_ADC_NCHS3_NS13_CH7 (0x00000007U) +#define MD_ADC_NCHS3_NS13_CH8 (0x00000008U) +#define MD_ADC_NCHS3_NS13_CH9 (0x00000009U) +#define MD_ADC_NCHS3_NS13_CH10 (0x0000000AU) +#define MD_ADC_NCHS3_NS13_CH11 (0x0000000BU) +#define MD_ADC_NCHS3_NS13_CH12 (0x0000000CU) +#define MD_ADC_NCHS3_NS13_CH13 (0x0000000DU) +#define MD_ADC_NCHS3_NS13_CH14 (0x0000000EU) +#define MD_ADC_NCHS3_NS13_CH15 (0x0000000FU) +#define MD_ADC_NCHS3_NS13_CH16 (0x00000010U) +#define MD_ADC_NCHS3_NS13_CH17 (0x00000011U) +#define MD_ADC_NCHS3_NS13_CH18 (0x00000012U) + +#define MD_ADC_NCHS3_NS12_CH0 (0x00000000U) +#define MD_ADC_NCHS3_NS12_CH1 (0x00000001U) +#define MD_ADC_NCHS3_NS12_CH2 (0x00000002U) +#define MD_ADC_NCHS3_NS12_CH3 (0x00000003U) +#define MD_ADC_NCHS3_NS12_CH4 (0x00000004U) +#define MD_ADC_NCHS3_NS12_CH5 (0x00000005U) +#define MD_ADC_NCHS3_NS12_CH6 (0x00000006U) +#define MD_ADC_NCHS3_NS12_CH7 (0x00000007U) +#define MD_ADC_NCHS3_NS12_CH8 (0x00000008U) +#define MD_ADC_NCHS3_NS12_CH9 (0x00000009U) +#define MD_ADC_NCHS3_NS12_CH10 (0x0000000AU) +#define MD_ADC_NCHS3_NS12_CH11 (0x0000000BU) +#define MD_ADC_NCHS3_NS12_CH12 (0x0000000CU) +#define MD_ADC_NCHS3_NS12_CH13 (0x0000000DU) +#define MD_ADC_NCHS3_NS12_CH14 (0x0000000EU) +#define MD_ADC_NCHS3_NS12_CH15 (0x0000000FU) +#define MD_ADC_NCHS3_NS12_CH16 (0x00000010U) +#define MD_ADC_NCHS3_NS12_CH17 (0x00000011U) +#define MD_ADC_NCHS3_NS12_CH18 (0x00000012U) + +#define MD_ADC_NCHS3_NS11_CH0 (0x00000000U) +#define MD_ADC_NCHS3_NS11_CH1 (0x00000001U) +#define MD_ADC_NCHS3_NS11_CH2 (0x00000002U) +#define MD_ADC_NCHS3_NS11_CH3 (0x00000003U) +#define MD_ADC_NCHS3_NS11_CH4 (0x00000004U) +#define MD_ADC_NCHS3_NS11_CH5 (0x00000005U) +#define MD_ADC_NCHS3_NS11_CH6 (0x00000006U) +#define MD_ADC_NCHS3_NS11_CH7 (0x00000007U) +#define MD_ADC_NCHS3_NS11_CH8 (0x00000008U) +#define MD_ADC_NCHS3_NS11_CH9 (0x00000009U) +#define MD_ADC_NCHS3_NS11_CH10 (0x0000000AU) +#define MD_ADC_NCHS3_NS11_CH11 (0x0000000BU) +#define MD_ADC_NCHS3_NS11_CH12 (0x0000000CU) +#define MD_ADC_NCHS3_NS11_CH13 (0x0000000DU) +#define MD_ADC_NCHS3_NS11_CH14 (0x0000000EU) +#define MD_ADC_NCHS3_NS11_CH15 (0x0000000FU) +#define MD_ADC_NCHS3_NS11_CH16 (0x00000010U) +#define MD_ADC_NCHS3_NS11_CH17 (0x00000011U) +#define MD_ADC_NCHS3_NS11_CH18 (0x00000012U) + +#define MD_ADC_NCHS3_NS10_CH0 (0x00000000U) +#define MD_ADC_NCHS3_NS10_CH1 (0x00000001U) +#define MD_ADC_NCHS3_NS10_CH2 (0x00000002U) +#define MD_ADC_NCHS3_NS10_CH3 (0x00000003U) +#define MD_ADC_NCHS3_NS10_CH4 (0x00000004U) +#define MD_ADC_NCHS3_NS10_CH5 (0x00000005U) +#define MD_ADC_NCHS3_NS10_CH6 (0x00000006U) +#define MD_ADC_NCHS3_NS10_CH7 (0x00000007U) +#define MD_ADC_NCHS3_NS10_CH8 (0x00000008U) +#define MD_ADC_NCHS3_NS10_CH9 (0x00000009U) +#define MD_ADC_NCHS3_NS10_CH10 (0x0000000AU) +#define MD_ADC_NCHS3_NS10_CH11 (0x0000000BU) +#define MD_ADC_NCHS3_NS10_CH12 (0x0000000CU) +#define MD_ADC_NCHS3_NS10_CH13 (0x0000000DU) +#define MD_ADC_NCHS3_NS10_CH14 (0x0000000EU) +#define MD_ADC_NCHS3_NS10_CH15 (0x0000000FU) +#define MD_ADC_NCHS3_NS10_CH16 (0x00000010U) +#define MD_ADC_NCHS3_NS10_CH17 (0x00000011U) +#define MD_ADC_NCHS3_NS10_CH18 (0x00000012U) + +#define MD_ADC_NCHS4_NS16_CH0 (0x00000000U) +#define MD_ADC_NCHS4_NS16_CH1 (0x00000001U) +#define MD_ADC_NCHS4_NS16_CH2 (0x00000002U) +#define MD_ADC_NCHS4_NS16_CH3 (0x00000003U) +#define MD_ADC_NCHS4_NS16_CH4 (0x00000004U) +#define MD_ADC_NCHS4_NS16_CH5 (0x00000005U) +#define MD_ADC_NCHS4_NS16_CH6 (0x00000006U) +#define MD_ADC_NCHS4_NS16_CH7 (0x00000007U) +#define MD_ADC_NCHS4_NS16_CH8 (0x00000008U) +#define MD_ADC_NCHS4_NS16_CH9 (0x00000009U) +#define MD_ADC_NCHS4_NS16_CH10 (0x0000000AU) +#define MD_ADC_NCHS4_NS16_CH11 (0x0000000BU) +#define MD_ADC_NCHS4_NS16_CH12 (0x0000000CU) +#define MD_ADC_NCHS4_NS16_CH13 (0x0000000DU) +#define MD_ADC_NCHS4_NS16_CH14 (0x0000000EU) +#define MD_ADC_NCHS4_NS16_CH15 (0x0000000FU) +#define MD_ADC_NCHS4_NS16_CH16 (0x00000010U) +#define MD_ADC_NCHS4_NS16_CH17 (0x00000011U) +#define MD_ADC_NCHS4_NS16_CH18 (0x00000012U) + +#define MD_ADC_NCHS4_NS15_CH0 (0x00000000U) +#define MD_ADC_NCHS4_NS15_CH1 (0x00000001U) +#define MD_ADC_NCHS4_NS15_CH2 (0x00000002U) +#define MD_ADC_NCHS4_NS15_CH3 (0x00000003U) +#define MD_ADC_NCHS4_NS15_CH4 (0x00000004U) +#define MD_ADC_NCHS4_NS15_CH5 (0x00000005U) +#define MD_ADC_NCHS4_NS15_CH6 (0x00000006U) +#define MD_ADC_NCHS4_NS15_CH7 (0x00000007U) +#define MD_ADC_NCHS4_NS15_CH8 (0x00000008U) +#define MD_ADC_NCHS4_NS15_CH9 (0x00000009U) +#define MD_ADC_NCHS4_NS15_CH10 (0x0000000AU) +#define MD_ADC_NCHS4_NS15_CH11 (0x0000000BU) +#define MD_ADC_NCHS4_NS15_CH12 (0x0000000CU) +#define MD_ADC_NCHS4_NS15_CH13 (0x0000000DU) +#define MD_ADC_NCHS4_NS15_CH14 (0x0000000EU) +#define MD_ADC_NCHS4_NS15_CH15 (0x0000000FU) +#define MD_ADC_NCHS4_NS15_CH16 (0x00000010U) +#define MD_ADC_NCHS4_NS15_CH17 (0x00000011U) +#define MD_ADC_NCHS4_NS15_CH18 (0x00000012U) + +#define MD_ADC_ICHS_IS4_CH0 (0x00000000U) +#define MD_ADC_ICHS_IS4_CH1 (0x00000001U) +#define MD_ADC_ICHS_IS4_CH2 (0x00000002U) +#define MD_ADC_ICHS_IS4_CH3 (0x00000003U) +#define MD_ADC_ICHS_IS4_CH4 (0x00000004U) +#define MD_ADC_ICHS_IS4_CH5 (0x00000005U) +#define MD_ADC_ICHS_IS4_CH6 (0x00000006U) +#define MD_ADC_ICHS_IS4_CH7 (0x00000007U) +#define MD_ADC_ICHS_IS4_CH8 (0x00000008U) +#define MD_ADC_ICHS_IS4_CH9 (0x00000009U) +#define MD_ADC_ICHS_IS4_CH10 (0x0000000AU) +#define MD_ADC_ICHS_IS4_CH11 (0x0000000BU) +#define MD_ADC_ICHS_IS4_CH12 (0x0000000CU) +#define MD_ADC_ICHS_IS4_CH13 (0x0000000DU) +#define MD_ADC_ICHS_IS4_CH14 (0x0000000EU) +#define MD_ADC_ICHS_IS4_CH15 (0x0000000FU) +#define MD_ADC_ICHS_IS4_CH16 (0x00000010U) +#define MD_ADC_ICHS_IS4_CH17 (0x00000011U) +#define MD_ADC_ICHS_IS4_CH18 (0x00000012U) + +#define MD_ADC_ICHS_IS3_CH0 (0x00000000U) +#define MD_ADC_ICHS_IS3_CH1 (0x00000001U) +#define MD_ADC_ICHS_IS3_CH2 (0x00000002U) +#define MD_ADC_ICHS_IS3_CH3 (0x00000003U) +#define MD_ADC_ICHS_IS3_CH4 (0x00000004U) +#define MD_ADC_ICHS_IS3_CH5 (0x00000005U) +#define MD_ADC_ICHS_IS3_CH6 (0x00000006U) +#define MD_ADC_ICHS_IS3_CH7 (0x00000007U) +#define MD_ADC_ICHS_IS3_CH8 (0x00000008U) +#define MD_ADC_ICHS_IS3_CH9 (0x00000009U) +#define MD_ADC_ICHS_IS3_CH10 (0x0000000AU) +#define MD_ADC_ICHS_IS3_CH11 (0x0000000BU) +#define MD_ADC_ICHS_IS3_CH12 (0x0000000CU) +#define MD_ADC_ICHS_IS3_CH13 (0x0000000DU) +#define MD_ADC_ICHS_IS3_CH14 (0x0000000EU) +#define MD_ADC_ICHS_IS3_CH15 (0x0000000FU) +#define MD_ADC_ICHS_IS3_CH16 (0x00000010U) +#define MD_ADC_ICHS_IS3_CH17 (0x00000011U) +#define MD_ADC_ICHS_IS3_CH18 (0x00000012U) + +#define MD_ADC_ICHS_IS2_CH0 (0x00000000U) +#define MD_ADC_ICHS_IS2_CH1 (0x00000001U) +#define MD_ADC_ICHS_IS2_CH2 (0x00000002U) +#define MD_ADC_ICHS_IS2_CH3 (0x00000003U) +#define MD_ADC_ICHS_IS2_CH4 (0x00000004U) +#define MD_ADC_ICHS_IS2_CH5 (0x00000005U) +#define MD_ADC_ICHS_IS2_CH6 (0x00000006U) +#define MD_ADC_ICHS_IS2_CH7 (0x00000007U) +#define MD_ADC_ICHS_IS2_CH8 (0x00000008U) +#define MD_ADC_ICHS_IS2_CH9 (0x00000009U) +#define MD_ADC_ICHS_IS2_CH10 (0x0000000AU) +#define MD_ADC_ICHS_IS2_CH11 (0x0000000BU) +#define MD_ADC_ICHS_IS2_CH12 (0x0000000CU) +#define MD_ADC_ICHS_IS2_CH13 (0x0000000DU) +#define MD_ADC_ICHS_IS2_CH14 (0x0000000EU) +#define MD_ADC_ICHS_IS2_CH15 (0x0000000FU) +#define MD_ADC_ICHS_IS2_CH16 (0x00000010U) +#define MD_ADC_ICHS_IS2_CH17 (0x00000011U) +#define MD_ADC_ICHS_IS2_CH18 (0x00000012U) + +#define MD_ADC_ICHS_IS1_CH0 (0x00000000U) +#define MD_ADC_ICHS_IS1_CH1 (0x00000001U) +#define MD_ADC_ICHS_IS1_CH2 (0x00000002U) +#define MD_ADC_ICHS_IS1_CH3 (0x00000003U) +#define MD_ADC_ICHS_IS1_CH4 (0x00000004U) +#define MD_ADC_ICHS_IS1_CH5 (0x00000005U) +#define MD_ADC_ICHS_IS1_CH6 (0x00000006U) +#define MD_ADC_ICHS_IS1_CH7 (0x00000007U) +#define MD_ADC_ICHS_IS1_CH8 (0x00000008U) +#define MD_ADC_ICHS_IS1_CH9 (0x00000009U) +#define MD_ADC_ICHS_IS1_CH10 (0x0000000AU) +#define MD_ADC_ICHS_IS1_CH11 (0x0000000BU) +#define MD_ADC_ICHS_IS1_CH12 (0x0000000CU) +#define MD_ADC_ICHS_IS1_CH13 (0x0000000DU) +#define MD_ADC_ICHS_IS1_CH14 (0x0000000EU) +#define MD_ADC_ICHS_IS1_CH15 (0x0000000FU) +#define MD_ADC_ICHS_IS1_CH16 (0x00000010U) +#define MD_ADC_ICHS_IS1_CH17 (0x00000011U) +#define MD_ADC_ICHS_IS1_CH18 (0x00000012U) + +#define MD_ADC_ICHS_IETS_DISABLE (0x00000000U) +#define MD_ADC_ICHS_IETS_RISING (0x00000001U) +#define MD_ADC_ICHS_IETS_FALLING (0x00000002U) +#define MD_ADC_ICHS_IETS_BOTH (0x00000003U) + +#define MD_ADC_ICHS_IEXTSEL_AD16C4T1_CH4 (0x00000000U) +#define MD_ADC_ICHS_IEXTSEL_AD16C4T1_TRGOUT (0x00000001U) +#define MD_ADC_ICHS_IEXTSEL_GP32C4T1_CH1 (0x00000002U) +#define MD_ADC_ICHS_IEXTSEL_GP32C4T1_TRGOUT (0x00000003U) +#define MD_ADC_ICHS_IEXTSEL_GP16C4T1_CH2 (0x00000004U) +#define MD_ADC_ICHS_IEXTSEL_GP16C4T1_CH3 (0x00000005U) +#define MD_ADC_ICHS_IEXTSEL_GP16C4T1_CH4 (0x00000006U) +#define MD_ADC_ICHS_IEXTSEL_GP16C4T2_CH1 (0x00000007U) +#define MD_ADC_ICHS_IEXTSEL_GP16C4T2_CH2 (0x00000008U) +#define MD_ADC_ICHS_IEXTSEL_GP16C4T2_CH3 (0x00000009U) +#define MD_ADC_ICHS_IEXTSEL_GP16C4T2_TRGOUT (0x0000000AU) +#define MD_ADC_ICHS_IEXTSEL_GP16C4T3_CH4 (0x0000000BU) +#define MD_ADC_ICHS_IEXTSEL_GP16C4T3_TRGOUT (0x0000000CU) +#define MD_ADC_ICHS_IEXTSEL_GP16C2T1_TRGOUT (0x0000000DU) +#define MD_ADC_ICHS_IEXTSEL_GP16C2T2_TRGOUT (0x0000000EU) +#define MD_ADC_ICHS_IEXTSEL_EXTI_TRG1 (0x0000000FU) + +#define MD_ADC_ICHS_ISL_1CON (0x00000000U) +#define MD_ADC_ICHS_ISL_2CON (0x00000001U) +#define MD_ADC_ICHS_ISL_3CON (0x00000002U) +#define MD_ADC_ICHS_ISL_4CON (0x00000003U) + +#define MD_ADC_OFF1_OFFCH_CH0 (0x00000000U) +#define MD_ADC_OFF1_OFFCH_CH1 (0x00000001U) +#define MD_ADC_OFF1_OFFCH_CH2 (0x00000002U) +#define MD_ADC_OFF1_OFFCH_CH3 (0x00000003U) +#define MD_ADC_OFF1_OFFCH_CH4 (0x00000004U) +#define MD_ADC_OFF1_OFFCH_CH5 (0x00000005U) +#define MD_ADC_OFF1_OFFCH_CH6 (0x00000006U) +#define MD_ADC_OFF1_OFFCH_CH7 (0x00000007U) +#define MD_ADC_OFF1_OFFCH_CH8 (0x00000008U) +#define MD_ADC_OFF1_OFFCH_CH9 (0x00000009U) +#define MD_ADC_OFF1_OFFCH_CH10 (0x0000000AU) +#define MD_ADC_OFF1_OFFCH_CH11 (0x0000000BU) +#define MD_ADC_OFF1_OFFCH_CH12 (0x0000000CU) +#define MD_ADC_OFF1_OFFCH_CH13 (0x0000000DU) +#define MD_ADC_OFF1_OFFCH_CH14 (0x0000000EU) +#define MD_ADC_OFF1_OFFCH_CH15 (0x0000000FU) +#define MD_ADC_OFF1_OFFCH_CH16 (0x00000010U) +#define MD_ADC_OFF1_OFFCH_CH17 (0x00000011U) +#define MD_ADC_OFF1_OFFCH_CH18 (0x00000012U) + +#define MD_ADC_OFF1_OFFPEN_NEGATIVE (0x00000000U) +#define MD_ADC_OFF1_OFFPEN_POSITIVE (0x00000001U) + +#define MD_ADC_OFF2_OFFCH_CH0 (0x00000000U) +#define MD_ADC_OFF2_OFFCH_CH1 (0x00000001U) +#define MD_ADC_OFF2_OFFCH_CH2 (0x00000002U) +#define MD_ADC_OFF2_OFFCH_CH3 (0x00000003U) +#define MD_ADC_OFF2_OFFCH_CH4 (0x00000004U) +#define MD_ADC_OFF2_OFFCH_CH5 (0x00000005U) +#define MD_ADC_OFF2_OFFCH_CH6 (0x00000006U) +#define MD_ADC_OFF2_OFFCH_CH7 (0x00000007U) +#define MD_ADC_OFF2_OFFCH_CH8 (0x00000008U) +#define MD_ADC_OFF2_OFFCH_CH9 (0x00000009U) +#define MD_ADC_OFF2_OFFCH_CH10 (0x0000000AU) +#define MD_ADC_OFF2_OFFCH_CH11 (0x0000000BU) +#define MD_ADC_OFF2_OFFCH_CH12 (0x0000000CU) +#define MD_ADC_OFF2_OFFCH_CH13 (0x0000000DU) +#define MD_ADC_OFF2_OFFCH_CH14 (0x0000000EU) +#define MD_ADC_OFF2_OFFCH_CH15 (0x0000000FU) +#define MD_ADC_OFF2_OFFCH_CH16 (0x00000010U) +#define MD_ADC_OFF2_OFFCH_CH17 (0x00000011U) +#define MD_ADC_OFF2_OFFCH_CH18 (0x00000012U) + +#define MD_ADC_OFF2_OFFPEN_NEGATIVE (0x00000000U) +#define MD_ADC_OFF2_OFFPEN_POSITIVE (0x00000001U) + +#define MD_ADC_OFF3_OFFCH_CH0 (0x00000000U) +#define MD_ADC_OFF3_OFFCH_CH1 (0x00000001U) +#define MD_ADC_OFF3_OFFCH_CH2 (0x00000002U) +#define MD_ADC_OFF3_OFFCH_CH3 (0x00000003U) +#define MD_ADC_OFF3_OFFCH_CH4 (0x00000004U) +#define MD_ADC_OFF3_OFFCH_CH5 (0x00000005U) +#define MD_ADC_OFF3_OFFCH_CH6 (0x00000006U) +#define MD_ADC_OFF3_OFFCH_CH7 (0x00000007U) +#define MD_ADC_OFF3_OFFCH_CH8 (0x00000008U) +#define MD_ADC_OFF3_OFFCH_CH9 (0x00000009U) +#define MD_ADC_OFF3_OFFCH_CH10 (0x0000000AU) +#define MD_ADC_OFF3_OFFCH_CH11 (0x0000000BU) +#define MD_ADC_OFF3_OFFCH_CH12 (0x0000000CU) +#define MD_ADC_OFF3_OFFCH_CH13 (0x0000000DU) +#define MD_ADC_OFF3_OFFCH_CH14 (0x0000000EU) +#define MD_ADC_OFF3_OFFCH_CH15 (0x0000000FU) +#define MD_ADC_OFF3_OFFCH_CH16 (0x00000010U) +#define MD_ADC_OFF3_OFFCH_CH17 (0x00000011U) +#define MD_ADC_OFF3_OFFCH_CH18 (0x00000012U) + +#define MD_ADC_OFF3_OFFPEN_NEGATIVE (0x00000000U) +#define MD_ADC_OFF3_OFFPEN_POSITIVE (0x00000001U) + +#define MD_ADC_OFF4_OFFCH_CH0 (0x00000000U) +#define MD_ADC_OFF4_OFFCH_CH1 (0x00000001U) +#define MD_ADC_OFF4_OFFCH_CH2 (0x00000002U) +#define MD_ADC_OFF4_OFFCH_CH3 (0x00000003U) +#define MD_ADC_OFF4_OFFCH_CH4 (0x00000004U) +#define MD_ADC_OFF4_OFFCH_CH5 (0x00000005U) +#define MD_ADC_OFF4_OFFCH_CH6 (0x00000006U) +#define MD_ADC_OFF4_OFFCH_CH7 (0x00000007U) +#define MD_ADC_OFF4_OFFCH_CH8 (0x00000008U) +#define MD_ADC_OFF4_OFFCH_CH9 (0x00000009U) +#define MD_ADC_OFF4_OFFCH_CH10 (0x0000000AU) +#define MD_ADC_OFF4_OFFCH_CH11 (0x0000000BU) +#define MD_ADC_OFF4_OFFCH_CH12 (0x0000000CU) +#define MD_ADC_OFF4_OFFCH_CH13 (0x0000000DU) +#define MD_ADC_OFF4_OFFCH_CH14 (0x0000000EU) +#define MD_ADC_OFF4_OFFCH_CH15 (0x0000000FU) +#define MD_ADC_OFF4_OFFCH_CH16 (0x00000010U) +#define MD_ADC_OFF4_OFFCH_CH17 (0x00000011U) +#define MD_ADC_OFF4_OFFCH_CH18 (0x00000012U) + +#define MD_ADC_OFF4_OFFPEN_NEGATIVE (0x00000000U) +#define MD_ADC_OFF4_OFFPEN_POSITIVE (0x00000001U) + +#define MD_ADC_CCR_REFINTS_4DIV16 (0x00000000U) +#define MD_ADC_CCR_REFINTS_8DIV16 (0x00000001U) +#define MD_ADC_CCR_REFINTS_12DIV16 (0x00000002U) +#define MD_ADC_CCR_REFINTS_16DIV16 (0x00000003U) +#define MD_ADC_CCR_REFINTS_1DIV16 (0x00000004U) +#define MD_ADC_CCR_REFINTS_15DIV16 (0x00000005U) + + +#define MD_ADC_MODE_NCHS 0x00000000U +#define MD_ADC_MODE_ICHS 0x00000001U + +#define MD_ADC_CHANNEL_0 0x0U +#define MD_ADC_CHANNEL_1 0x1U +#define MD_ADC_CHANNEL_2 0x2U +#define MD_ADC_CHANNEL_3 0x3U +#define MD_ADC_CHANNEL_4 0x4U +#define MD_ADC_CHANNEL_5 0x5U +#define MD_ADC_CHANNEL_6 0x6U +#define MD_ADC_CHANNEL_7 0x7U +#define MD_ADC_CHANNEL_8 0x8U +#define MD_ADC_CHANNEL_9 0x9U +#define MD_ADC_CHANNEL_10 0xAU +#define MD_ADC_CHANNEL_11 0xBU +#define MD_ADC_CHANNEL_12 0xCU +#define MD_ADC_CHANNEL_13 0xDU +#define MD_ADC_CHANNEL_14 0xEU +#define MD_ADC_CHANNEL_15 0xFU +#define MD_ADC_CHANNEL_16 0x10U +#define MD_ADC_CHANNEL_17 0x11U +#define MD_ADC_CHANNEL_18 0x12U + +//ADC calibration choose +#define MD_ADC_CALIBRATION 0x1U +#define MD_ADC_NONE_CALIBRATION 0x2U + +//ADC option byte address +#define ADC_CALIBRATION_ADDR 0x874 + +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions ADC Public Functions + * @{ + */ + +/** @defgroup MD_ADC_Public_Functions_Group2 IER + * @{ + */ + +/** + * @brief Set ADC_IER Register + * @param ADCx ADC Instance + * @param ier + */ +__STATIC_INLINE void md_adc_set_ier(ADC_TypeDef *ADCx, uint32_t ier) +{ + WRITE_REG(ADCx->IER, ier); +} + +/** + * @brief ADC Timeout Interrupt Enable. + * @note User can set this bit to enable timeout Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_it_timeout(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_TO); +} + +/** + * @brief Analog Watchdog Interrupt Enable. + * @note User can set this bit to enable Analog Watchdog Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_it_awd(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_AWDF); +} + +/** + * @brief End of Injected Sequence of Conversions Interrupt Enable. + * @note User can set this bit to enable End of Injected Sequence of Conversions Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_it_inj_sequence_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_ISE); +} + +/** + * @brief End of Injected Conversion Interrupt Enable. + * @note User can set this bit to enable End of Injected Conversion Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_it_inj_conversion_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_ICHE); +} + +/** + * @brief ADC Overrun Interrupt Enable. + * @note User can set this bit to enable ADC Overrun Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_it_overflow(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_OVR); +} + +/** + * @brief End of Regular Sequence of Conversions Interrupt Enable. + * @note User can set this bit to enable End of Regular Sequence of Conversions Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_it_normal_sequence_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_NSE); +} + +/** + * @brief End of Regular Conversion Interrupt Enable. + * @note User can set this bit to enable End of Regular Conversion Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_it_normal_conversion_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_NCHE); +} + +/** + * @brief End of Sampling Flag Interrupt Enable for Regular Conversions. + * @note User can set this bit to enable End of Sampling Flag Interrupt Enable for Regular Conversions Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_it_sample_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_SMPE); +} + +/** + * @brief ADC Ready Interrupt Enable. + * @note User can set this bit to enable ADC Ready Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_it_adc_ready(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_ARDY); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group3 IDR + * @{ + */ +/** + * @brief Set ADC_IDR Register + * @param ADCx ADC Instance + * @param ier + */ +__STATIC_INLINE void md_adc_set_idr(ADC_TypeDef *ADCx, uint32_t idr) +{ + WRITE_REG(ADCx->IDR, idr); +} + +/** + * @brief ADC Timeout Interrupt Disable. + * @note User can set this bit to Disable timeout Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_it_timeout(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_TO); +} + +/** + * @brief Analog Watchdog Interrupt Disable. + * @note User can set this bit to Disable Analog Watchdog Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_it_awd(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_AWDF); +} + +/** + * @brief End of Injected Sequence of Conversions Interrupt Disable. + * @note User can set this bit to Disable End of Injected Sequence of Conversions Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_it_inj_sequence_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_ISE); +} + +/** + * @brief End of Injected Conversion Interrupt Disable. + * @note User can set this bit to Disable End of Injected Conversion Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_it_inj_conversion_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_ICHE); +} + +/** + * @brief ADC Overrun Interrupt Disable. + * @note User can set this bit to Disable ADC Overrun Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_it_overflow(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_OVR); +} + +/** + * @brief End of Regular Sequence of Conversions Interrupt Disable. + * @note User can set this bit to Disable End of Regular Sequence of Conversions Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_it_normal_sequence_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_NSE); +} + +/** + * @brief End of Regular Conversion Interrupt Disable. + * @note User can set this bit to Disable End of Regular Conversion Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_it_normal_conversion_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_NCHE); +} + +/** + * @brief End of Sampling Flag Interrupt Disable for Regular Conversions. + * @note User can set this bit to Disable End of Sampling Flag Interrupt Disable for Regular Conversions function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_it_sample_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_SMPE); +} + +/** + * @brief ADC Ready Interrupt Disable. + * @note User can set this bit to Disable ADC Ready Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_it_adc_ready(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_ARDY); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group4 IVS + * @{ + */ +/** + * @brief Get ADC_IVS Register + * @param ADCx ADC Instance + * @param ier + */ +__STATIC_INLINE uint32_t md_adc_get_ivs(ADC_TypeDef *ADCx) +{ + return (uint32_t)READ_REG(ADCx->IVS); +} + +/** + * @brief Check if ADC Timeout Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_it_timeout(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_TO) == (ADC_IVS_TO)); +} + +/** + * @brief Check if ADC Analog Watchdog Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_it_awd(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_AWDF) == (ADC_IVS_AWDF)); +} + +/** + * @brief Check if ADC End of Injected Sequence of Conversions Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_it_inj_sequence_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_ISE) == (ADC_IVS_ISE)); +} + +/** + * @brief Check if ADC End of Injected Conversion Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_it_inj_conversion_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_ICHE) == (ADC_IVS_ICHE)); +} + +/** + * @brief Check if ADC ADC Overrun Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_it_overflow(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_OVR) == (ADC_IVS_OVR)); +} + +/** + * @brief Check if ADC ADC End of Regular Sequence of Conversions Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_it_normal_sequence_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_NSE) == (ADC_IVS_NSE)); +} + +/** + * @brief Check if ADC End of Regular Conversion Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_it_normal_conversion_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_NCHE) == (ADC_IVS_NCHE)); +} + +/** + * @brief Check if ADC End of Sampling Flag Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_it_sample_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_SMPE) == (ADC_IVS_SMPE)); +} + +/** + * @brief Check if ADC Ready Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_it_adc_ready(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_ARDY) == (ADC_IVS_ARDY)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group5 RIF + * @{ + */ + +/** + * @brief Get ADC_RIF Register + * @param ADCx ADC Instance + * @param ier + */ +__STATIC_INLINE uint32_t md_adc_get_rif(ADC_TypeDef *ADCx) +{ + return (uint32_t)READ_REG(ADCx->RIF); +} + +/** + * @brief Check Timeout Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_timeout(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_TO) == (ADC_RIF_TO)); +} + +/** + * @brief Check Analog Watchdog Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_awd(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_AWDF) == (ADC_RIF_AWDF)); +} + +/** + * @brief Check End of Injected Sequence of Conversions Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_inj_sequence_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_ISE) == (ADC_RIF_ISE)); +} + +/** + * @brief Check End of Injected Conversion Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_inj_conversion_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_ICHE) == (ADC_RIF_ICHE)); +} + +/** + * @brief Check ADC Overrun Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_overflow(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_OVR) == (ADC_RIF_OVR)); +} + +/** + * @brief Check End of Regular Sequence of Conversions Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_normal_sequence_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_NSE) == (ADC_RIF_NSE)); +} + +/** + * @brief Check End of Regular Conversion Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_normal_conversion_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_NCHE) == (ADC_RIF_NCHE)); +} + +/** + * @brief Check End of Sampling Flag Interrupt Flag Status for Regular Conversions. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_sample_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_SMPE) == (ADC_RIF_SMPE)); +} + +/** + * @brief Check ADC Ready Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_adc_ready(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_ARDY) == (ADC_RIF_ARDY)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group6 IFM + * @{ + */ +/** + * @brief Get ADC_IFM Register + * @param ADCx ADC Instance + * @param ier + */ +__STATIC_INLINE uint32_t md_adc_get_ifm(ADC_TypeDef *ADCx) +{ + return (uint32_t)READ_REG(ADCx->IFM); +} + +/** + * @brief Check Timeout Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_masked_it_timeout(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_TO) == (ADC_IFM_TO)); +} + +/** + * @brief Check Analog Watchdog Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_masked_it_awd(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_AWDF) == (ADC_IFM_AWDF)); +} + +/** + * @brief Check End of Injected Sequence of Conversions Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_masked_it_inj_sequence_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_ISE) == (ADC_IFM_ISE)); +} + +/** + * @brief Check End of Injected Conversion Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_masked_it_inj_conversion_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_ICHE) == (ADC_IFM_ICHE)); +} + +/** + * @brief Check ADC Overrun Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_masked_it_overflow(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_OVR) == (ADC_IFM_OVR)); +} + +/** + * @brief Check End of Regular Sequence of Conversions Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_masked_it_normal_sequence_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_NSE) == (ADC_IFM_NSE)); +} + +/** + * @brief Check End of Regular Conversion Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_masked_it_normal_conversion_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_NCHE) == (ADC_IFM_NCHE)); +} + +/** + * @brief Check End of Sampling Flag Interrupt Flag Masked Status for Regular Conversions. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_masked_it_sample_done(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_SMPE) == (ADC_IFM_SMPE)); +} + +/** + * @brief Check ADC Ready Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_masked_it_adc_ready(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_ARDY) == (ADC_IFM_ARDY)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group7 ICR + * @{ + */ +/** + * @brief Set ADC_ICR Register + * @param ADCx ADC Instance + * @param ier + */ +__STATIC_INLINE void md_adc_set_icr(ADC_TypeDef *ADCx, uint32_t icr) +{ + WRITE_REG(ADCx->ICR, icr); +} + +/** + * @brief ADC Timeout Interrupt Clear. + * @note User can set this bit to clear timeout interrupt status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_clear_it_timeout(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_TO); +} + +/** + * @brief ADC Analog Watchdog Interrupt Clear. + * @note User can set this bit to clear Analog Watchdog interrupt status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_clear_it_awd(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_AWDF); +} + +/** + * @brief ADC End of Injected Sequence of Conversions Interrupt Clear. + * @note User can set this bit to clear End of Injected Sequence of Conversions interrupt status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_clear_it_inj_sequence_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_ISE); +} + +/** + * @brief ADC End of Injected Conversion Interrupt Clear. + * @note User can set this bit to clear End of Injected Conversion interrupt status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_clear_it_inj_conversion_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_ICHE); +} + +/** + * @brief ADC Overrun Interrupt Clear. + * @note User can set this bit to clear Overrun interrupt status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_clear_it_overflow(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_OVR); +} + +/** + * @brief ADC End of Regular Sequence of Conversions Interrupt Clear. + * @note User can set this bit to clear End of Regular Sequence of Conversions interrupt status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_clear_it_normal_sequence_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_NSE); +} + +/** + * @brief ADC End of Regular Conversion Interrupt Clear. + * @note User can set this bit to clear End of Regular Conversion interrupt status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_clear_it_normal_conversion_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_NCHE); +} + +/** + * @brief ADC End of Sampling Flag Interrupt Clear for Regular Conversions. + * @note User can set this bit to clear End of Sampling Flag status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_clear_it_sample_done(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_SMPE); +} + +/** + * @brief ADC Ready Interrupt Clear. + * @note User can set this bit to clear Ready interrupt status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_clear_it_adc_ready(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_ARDY); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group8 CON + * @{ + */ +/** + * @brief Set ADC_CON Register + * @param ADCx ADC Instance + * @param ier + */ +__STATIC_INLINE void md_adc_set_con(ADC_TypeDef *ADCx, uint32_t con) +{ + WRITE_REG(ADCx->CON, con); +} + +/** + * @brief Get ADC_CON Register + * @param ADCx ADC Instance + */ +__STATIC_INLINE uint32_t md_adc_get_con(ADC_TypeDef *ADCx) +{ + return (uint32_t)READ_REG(ADCx->CON); +} + +/** + * @brief Set ADC calibration. + * @param ADCx ADC Instance + * @param adcal + @arg @ref MD_ADC_CON_ADCAL_CALIBRATION_COMPLETE + @arg @ref MD_ADC_CON_ADCAL_CALIBRATION + * @retval None + */ +__STATIC_INLINE void md_adc_enable_calibration(ADC_TypeDef *ADCx, uint32_t adcal) +{ + MODIFY_REG(ADCx->CON, ADC_CON_ADCAL, adcal << ADC_CON_ADCAL_POS); +} + +/** + * @brief Get ADC calibration. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CON_ADCAL_CALIBRATION_COMPLETE + @arg @ref MD_ADC_CON_ADCAL_CALIBRATION + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_calibration(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CON, ADC_CON_ADCAL)) == (ADC_CON_ADCAL)); +} + +/** + * @brief Set ADC stop of injected conversion command. + * @param ADCx ADC Instance + * @param istpc + @arg @ref MD_ADC_CON_ISTPC_NOSTOP_INJECTED + @arg @ref MD_ADC_CON_ISTPC_STOP_INJECTED + * @retval None + */ +__STATIC_INLINE void md_adc_set_stop_inj(ADC_TypeDef *ADCx, uint32_t istpc) +{ + MODIFY_REG(ADCx->CON, ADC_CON_ISTPC, istpc << ADC_CON_ISTPC_POS); +} + +/** + * @brief Get ADC stop of injected conversion command. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CON_ISTPC_NOSTOP_INJECTED + @arg @ref MD_ADC_CON_ISTPC_STOP_INJECTED + */ +__STATIC_INLINE uint32_t md_adc_get_stop_inj(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CON, ADC_CON_ISTPC)) >> ADC_CON_ISTPC_POS); +} + +/** + * @brief Set ADC stop of regular conversion command. + * @param ADCx ADC Instance + * @param nstpc + @arg @ref MD_ADC_CON_NSTPC_NOSTOP_REGULAR + @arg @ref MD_ADC_CON_NSTPC_STOP_REGULAR + * @retval None + */ +__STATIC_INLINE void md_adc_set_stop_normal(ADC_TypeDef *ADCx, uint32_t nstpc) +{ + MODIFY_REG(ADCx->CON, ADC_CON_NSTPC, nstpc << ADC_CON_NSTPC_POS); +} + +/** + * @brief Get ADC stop of regular conversion command. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CON_NSTPC_NOSTOP_REGULAR + @arg @ref MD_ADC_CON_NSTPC_STOP_REGULAR + */ +__STATIC_INLINE uint32_t md_adc_get_stop_normal(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CON, ADC_CON_NSTPC)) >> ADC_CON_NSTPC_POS); +} + +/** + * @brief Set ADC start of injected conversion. + * @param ADCx ADC Instance + * @param istart + @arg @ref MD_ADC_CON_ISTART_NOADC_INJECTED + @arg @ref MD_ADC_CON_ISTART_START_INJECTED + * @retval None + */ +__STATIC_INLINE void md_adc_set_start_inj(ADC_TypeDef *ADCx, uint32_t istart) +{ + MODIFY_REG(ADCx->CON, ADC_CON_ISTART, istart << ADC_CON_ISTART_POS); +} + +/** + * @brief Get ADC start of injected conversion. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CON_ISTART_NOADC_INJECTED + @arg @ref MD_ADC_CON_ISTART_START_INJECTED + */ +__STATIC_INLINE uint32_t md_adc_get_start_inj(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CON, ADC_CON_ISTART))); +} + +/** + * @brief Set ADC start of regular conversion. + * @param ADCx ADC Instance + * @param nstart + @arg @ref MD_ADC_CON_NSTART_NOADC_REGULAR + @arg @ref MD_ADC_CON_NSTART_START_REGULAR + * @retval None + */ +__STATIC_INLINE void md_adc_set_start_normal(ADC_TypeDef *ADCx, uint32_t nstart) +{ + MODIFY_REG(ADCx->CON, ADC_CON_NSTART, nstart << ADC_CON_NSTART_POS); +} + +/** + * @brief Get ADC start of regular conversion. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CON_NSTART_NOADC_REGULAR + @arg @ref MD_ADC_CON_NSTART_START_REGULAR + */ +__STATIC_INLINE uint32_t md_adc_get_start_normal(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CON, ADC_CON_NSTART)) >> ADC_CON_NSTART_POS); +} + +/** + * @brief Set ADC disable command. + * @param ADCx ADC Instance + * @param adcdis + @arg @ref MD_ADC_CON_ADCDIS_NODISABLE + @arg @ref MD_ADC_CON_ADCDIS_DISABLE + * @retval None + */ +__STATIC_INLINE void md_adc_disable_adcpower(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON, ADC_CON_ADCDIS); +} + +/** + * @brief Set ADC enable control. + * @param ADCx ADC Instance + * @param adcen + @arg @ref MD_ADC_CON_ADCEN_DISABLE + @arg @ref MD_ADC_CON_ADCEN_ENABLE + * @retval None + */ +__STATIC_INLINE void md_adc_enable_adcpower(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON, ADC_CON_ADCEN); +} + +/** + * @brief Get ADC enable control. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CON_ADCEN_DISABLE + @arg @ref MD_ADC_CON_ADCEN_ENABLE + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_adcpower(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CON, ADC_CON_ADCEN) == (ADC_CON_ADCEN)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group9 CFG + * @{ + */ +/** + * @brief Set ADC_CFG Register + * @param ADCx ADC Instance + * @param ier + */ +__STATIC_INLINE void md_adc_set_cfg(ADC_TypeDef *ADCx, uint32_t cfg) +{ + WRITE_REG(ADCx->CFG, cfg); +} + +/** + * @brief Get ADC_CFG Register + * @param ADCx ADC Instance + */ +__STATIC_INLINE uint32_t md_adc_get_cfg(ADC_TypeDef *ADCx) +{ + return (uint32_t)READ_REG(ADCx->CFG); +} + +/** + * @brief Set Analog watchdog channel selectione. + * @param ADCx ADC Instance + * @param awdch + @arg @ref MD_ADC_CFG_AWDCH_CH0 + @arg @ref MD_ADC_CFG_AWDCH_CH1 + @arg @ref MD_ADC_CFG_AWDCH_CH2 + @arg @ref MD_ADC_CFG_AWDCH_CH3 + @arg @ref MD_ADC_CFG_AWDCH_CH4 + @arg @ref MD_ADC_CFG_AWDCH_CH5 + @arg @ref MD_ADC_CFG_AWDCH_CH6 + @arg @ref MD_ADC_CFG_AWDCH_CH7 + @arg @ref MD_ADC_CFG_AWDCH_CH8 + @arg @ref MD_ADC_CFG_AWDCH_CH9 + @arg @ref MD_ADC_CFG_AWDCH_CH10 + @arg @ref MD_ADC_CFG_AWDCH_CH11 + @arg @ref MD_ADC_CFG_AWDCH_CH12 + @arg @ref MD_ADC_CFG_AWDCH_CH13 + @arg @ref MD_ADC_CFG_AWDCH_CH14 + @arg @ref MD_ADC_CFG_AWDCH_CH15 + @arg @ref MD_ADC_CFG_AWDCH_CH16 + @arg @ref MD_ADC_CFG_AWDCH_CH17 + @arg @ref MD_ADC_CFG_AWDCH_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_awd_monit_channel(ADC_TypeDef *ADCx, uint32_t awdch) +{ + MODIFY_REG(ADCx->CFG, ADC_CFG_AWDCH, awdch << ADC_CFG_AWDCH_POSS); +} + +/** + * @brief Get Analog watchdog channel selectione. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CFG_AWDCH_CH0 + @arg @ref MD_ADC_CFG_AWDCH_CH1 + @arg @ref MD_ADC_CFG_AWDCH_CH2 + @arg @ref MD_ADC_CFG_AWDCH_CH3 + @arg @ref MD_ADC_CFG_AWDCH_CH4 + @arg @ref MD_ADC_CFG_AWDCH_CH5 + @arg @ref MD_ADC_CFG_AWDCH_CH6 + @arg @ref MD_ADC_CFG_AWDCH_CH7 + @arg @ref MD_ADC_CFG_AWDCH_CH8 + @arg @ref MD_ADC_CFG_AWDCH_CH9 + @arg @ref MD_ADC_CFG_AWDCH_CH10 + @arg @ref MD_ADC_CFG_AWDCH_CH11 + @arg @ref MD_ADC_CFG_AWDCH_CH12 + @arg @ref MD_ADC_CFG_AWDCH_CH13 + @arg @ref MD_ADC_CFG_AWDCH_CH14 + @arg @ref MD_ADC_CFG_AWDCH_CH15 + @arg @ref MD_ADC_CFG_AWDCH_CH16 + @arg @ref MD_ADC_CFG_AWDCH_CH17 + @arg @ref MD_ADC_CFG_AWDCH_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_awd_monit_channel(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CFG, ADC_CFG_AWDCH)) >> ADC_CFG_AWDCH_POSS); +} + +/** + * @brief ADC Automatic injected group conversion Enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_inj_auto_convert(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CFG, ADC_CFG_IAUTO); +} + +/** + * @brief ADC Automatic injected group conversion Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_inj_auto_convert(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CFG, ADC_CFG_IAUTO); +} + +/** + * @brief Check if ADC Automatic injected group conversion is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_inj_auto_convert(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CFG, ADC_CFG_IAUTO) == (ADC_CFG_IAUTO)); +} + +/** + * @brief ADC Analog watchdog enable on injected channels. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_inj_awd(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CFG, ADC_CFG_IAWDEN); +} + +/** + * @brief ADC Analog watchdog disable on injected channels. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_inj_awd(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CFG, ADC_CFG_IAWDEN); +} + +/** + * @brief Check if ADC Analog watchdog enable on injected channels is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_inj_awd(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CFG, ADC_CFG_IAWDEN) == (ADC_CFG_IAWDEN)); +} + +/** + * @brief ADC Analog watchdog enable on regular channels. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_normal_awd(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CFG, ADC_CFG_NAWDEN); +} + +/** + * @brief ADC Analog watchdog disable on regular channels. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_normal_awd(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CFG, ADC_CFG_NAWDEN); +} + +/** + * @brief Check if ADC Analog watchdog enable on regular channels is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_normal_awd(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CFG, ADC_CFG_NAWDEN) == (ADC_CFG_NAWDEN)); +} + +/** + * @brief Set the watchdog on a single channel or on all channels. + * @param ADCx ADC Instance + * @param awdsgl + @arg @ref MD_ADC_CFG_AWDSGL_ALL_CH + @arg @ref MD_ADC_CFG_AWDSGL_SINGLE_CH + * @retval None + */ +__STATIC_INLINE void md_adc_set_awd_singlechannel(ADC_TypeDef *ADCx, uint32_t awdsgl) +{ + MODIFY_REG(ADCx->CFG, ADC_CFG_AWDSGL, awdsgl << ADC_CFG_AWDSGL_POS); +} + +/** + * @brief Get Enable the watchdog on a single channel or on all channels. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CFG_AWDSGL_ALL_CH + @arg @ref MD_ADC_CFG_AWDSGL_SINGLE_CH + */ +__STATIC_INLINE uint32_t md_adc_get_awd_singlechannel(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CFG, ADC_CFG_AWDSGL)) >> ADC_CFG_AWDSGL_POS); +} + +/** + * @brief Discontinuous mode on injected channels Enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_inj_discontinous(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CFG, ADC_CFG_ICHDCEN); +} + +/** + * @brief Discontinuous mode on injected channels Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_inj_discontinous(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CFG, ADC_CFG_ICHDCEN); +} + +/** + * @brief Check if Discontinuous mode on injected channels is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_inj_discontinous(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CFG, ADC_CFG_ICHDCEN) == (ADC_CFG_ICHDCEN)); +} + +/** + * @brief Set Discontinuous mode channel number. + * @param ADCx ADC Instance + * @param etrgn + @arg @ref MD_ADC_CFG_ETRGN_1CH + @arg @ref MD_ADC_CFG_ETRGN_2CH + @arg @ref MD_ADC_CFG_ETRGN_3CH + @arg @ref MD_ADC_CFG_ETRGN_4CH + @arg @ref MD_ADC_CFG_ETRGN_5CH + @arg @ref MD_ADC_CFG_ETRGN_6CH + @arg @ref MD_ADC_CFG_ETRGN_7CH + @arg @ref MD_ADC_CFG_ETRGN_8CH + * @retval None + */ +__STATIC_INLINE void md_adc_set_external_trigger_amount(ADC_TypeDef *ADCx, uint32_t etrgn) +{ + MODIFY_REG(ADCx->CFG, ADC_CFG_ETRGN, etrgn << ADC_CFG_ETRGN_POSS); +} + +/** + * @brief Get Discontinuous mode channel number. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CFG_ETRGN_1CH + @arg @ref MD_ADC_CFG_ETRGN_2CH + @arg @ref MD_ADC_CFG_ETRGN_3CH + @arg @ref MD_ADC_CFG_ETRGN_4CH + @arg @ref MD_ADC_CFG_ETRGN_5CH + @arg @ref MD_ADC_CFG_ETRGN_6CH + @arg @ref MD_ADC_CFG_ETRGN_7CH + @arg @ref MD_ADC_CFG_ETRGN_8CH + */ +__STATIC_INLINE uint32_t md_adc_get_external_trigger_amount(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CFG, ADC_CFG_ETRGN)) >> ADC_CFG_ETRGN_POSS); +} + +/** + * @brief Discontinuous mode for regular channels Enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_normal_discontinous(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CFG, ADC_CFG_NCHDCEN); +} + +/** + * @brief Discontinuous mode for regular channels Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_normal_discontinous(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CFG, ADC_CFG_NCHDCEN); +} + +/** + * @brief Check if Discontinuous mode for regular channels is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_normal_discontinous(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CFG, ADC_CFG_NCHDCEN) == (ADC_CFG_NCHDCEN)); +} + +/** + * @brief Auto Off Transition Mode Enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_auto_off_transition_mode(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CFG, ADC_CFG_AUTOFF); +} + +/** + * @brief Auto Off Transition Mode Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_auto_off_transition_mode(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CFG, ADC_CFG_AUTOFF); +} + +/** + * @brief Check if Auto Off Transition Mode is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_auto_off_transition_mode(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CFG, ADC_CFG_AUTOFF) == (ADC_CFG_AUTOFF)); +} + +/** + * @brief Delayed conversion mode Enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_auto_delay_mode(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CFG, ADC_CFG_AUTODLY); +} + +/** + * @brief Delayed conversion mode Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_auto_delay_mode(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CFG, ADC_CFG_AUTODLY); +} + +/** + * @brief Check if Delayed conversion mode is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_auto_delay_mode(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CFG, ADC_CFG_AUTODLY) == (ADC_CFG_AUTODLY)); +} + +/** + * @brief Set Single/continuous conversion mode for regular conversions. + * @param ADCx ADC Instance + * @param cm + @arg @ref MD_ADC_CFG_CM_SINGLE + @arg @ref MD_ADC_CFG_CM_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void md_adc_set_convsersion_mode(ADC_TypeDef *ADCx, uint32_t cm) +{ + MODIFY_REG(ADCx->CFG, ADC_CFG_CM, cm << ADC_CFG_CM_POS); +} + +/** + * @brief Get Single/continuous conversion mode for regular conversions. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CFG_CM_SINGLE + @arg @ref MD_ADC_CFG_CM_CONTINUOUS + */ +__STATIC_INLINE uint32_t md_adc_get_convsersion_mode(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CFG, ADC_CFG_CM)) >> ADC_CFG_CM_POS); +} + +/** + * @brief Set Overrun Mode. + * @param ADCx ADC Instance + * @param overmod + @arg @ref MD_ADC_CFG_OVRMOD_PRESERVED + @arg @ref MD_ADC_CFG_OVRMOD_OVERWRITTEN + * @retval None + */ +__STATIC_INLINE void md_adc_set_overflow_mode(ADC_TypeDef *ADCx, uint32_t overmod) +{ + MODIFY_REG(ADCx->CFG, ADC_CFG_OVRMOD, overmod << ADC_CFG_OVRMOD_POS); +} + +/** + * @brief Get Overrun Mode. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CFG_OVRMOD_PRESERVED + @arg @ref MD_ADC_CFG_OVRMOD_OVERWRITTEN + */ +__STATIC_INLINE uint32_t md_adc_get_overflow_mode(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CFG, ADC_CFG_OVRMOD)) >> ADC_CFG_OVRMOD_POS); +} + +/** + * @brief Set External trigger enable and polarity selection for regular channels. + * @param ADCx ADC Instance + * @param nets + @arg @ref MD_ADC_CFG_NETS_DISABLE + @arg @ref MD_ADC_CFG_NETS_RISING + @arg @ref MD_ADC_CFG_NETS_FALLING + @arg @ref MD_ADC_CFG_NETS_BOTH + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_external_trigger_mode(ADC_TypeDef *ADCx, uint32_t nets) +{ + MODIFY_REG(ADCx->CFG, ADC_CFG_NETS, nets << ADC_CFG_NETS_POSS); +} + +/** + * @brief Get External trigger enable and polarity selection for regular channels. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CFG_NETS_DISABLE + @arg @ref MD_ADC_CFG_NETS_RISING + @arg @ref MD_ADC_CFG_NETS_FALLING + @arg @ref MD_ADC_CFG_NETS_BOTH + */ +__STATIC_INLINE uint32_t md_adc_get_normal_external_trigger_mode(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CFG, ADC_CFG_NETS)) >> ADC_CFG_NETS_POSS); +} + +/** + * @brief Set External trigger selection for regular group. + * @param ADCx ADC Instance + * @param nextsel + @arg @ref MD_ADC_CFG_NEXTSEL_AD16C4T1_CH1 + @arg @ref MD_ADC_CFG_NEXTSEL_AD16C4T1_CH2 + @arg @ref MD_ADC_CFG_NEXTSEL_AD16C4T1_CH3 + @arg @ref MD_ADC_CFG_NEXTSEL_GP32C4T1_CH2 + @arg @ref MD_ADC_CFG_NEXTSEL_GP32C4T1_CH3 + @arg @ref MD_ADC_CFG_NEXTSEL_GP32C4T1_CH4 + @arg @ref MD_ADC_CFG_NEXTSEL_GP32C4T1_TRGOUT + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T1_CH1 + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T1_TRGOUT + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T2_CH4 + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T3_CH1 + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T3_CH2 + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T3_CH3 + @arg @ref MD_ADC_CFG_NEXTSEL_BS16T1_TRGOUT + @arg @ref MD_ADC_CFG_NEXTSEL_RTC + @arg @ref MD_ADC_CFG_NEXTSEL_EXTI_TRG0 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_external_trigger_source(ADC_TypeDef *ADCx, uint32_t nextsel) +{ + MODIFY_REG(ADCx->CFG, ADC_CFG_NEXTSEL, nextsel << ADC_CFG_NEXTSEL_POSS); +} + +/** + * @brief Get External trigger selection for regular group. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CFG_NEXTSEL_AD16C4T1_CH1 + @arg @ref MD_ADC_CFG_NEXTSEL_AD16C4T1_CH2 + @arg @ref MD_ADC_CFG_NEXTSEL_AD16C4T1_CH3 + @arg @ref MD_ADC_CFG_NEXTSEL_GP32C4T1_CH2 + @arg @ref MD_ADC_CFG_NEXTSEL_GP32C4T1_CH3 + @arg @ref MD_ADC_CFG_NEXTSEL_GP32C4T1_CH4 + @arg @ref MD_ADC_CFG_NEXTSEL_GP32C4T1_TRGOUT + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T1_CH1 + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T1_TRGOUT + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T2_CH4 + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T3_CH1 + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T3_CH2 + @arg @ref MD_ADC_CFG_NEXTSEL_GP16C4T3_CH3 + @arg @ref MD_ADC_CFG_NEXTSEL_BS16T1_TRGOUT + @arg @ref MD_ADC_CFG_NEXTSEL_RTC + @arg @ref MD_ADC_CFG_NEXTSEL_EXTI_TRG0 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_external_trigger_source(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CFG, ADC_CFG_NEXTSEL)) >> ADC_CFG_NEXTSEL_POSS); +} + +/** + * @brief Set Data alignment. + * @param ADCx ADC Instance + * @param align + @arg @ref MD_ADC_CFG_ALIGN_RIGHT + @arg @ref MD_ADC_CFG_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void md_adc_set_data_alignment(ADC_TypeDef *ADCx, uint32_t align) +{ + MODIFY_REG(ADCx->CFG, ADC_CFG_ALIGN, align << ADC_CFG_ALIGN_POS); +} + +/** + * @brief Get Data alignment. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CFG_ALIGN_RIGHT + @arg @ref MD_ADC_CFG_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t md_adc_get_data_alignment(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CFG, ADC_CFG_ALIGN)) >> ADC_CFG_ALIGN_POS); +} + +/** + * @brief Set Data resolution. + * @param ADCx ADC Instance + * @param rsel + @arg @ref MD_ADC_CFG_RSEL_6BIT + @arg @ref MD_ADC_CFG_RSEL_8BIT + @arg @ref MD_ADC_CFG_RSEL_10BIT + @arg @ref MD_ADC_CFG_RSEL_12BIT + * @retval None + */ +__STATIC_INLINE void md_adc_set_resolution_selection(ADC_TypeDef *ADCx, uint32_t rsel) +{ + MODIFY_REG(ADCx->CFG, ADC_CFG_RSEL, rsel << ADC_CFG_RSEL_POSS); +} + +/** + * @brief Get Data resolution. + * @param ADCx ADC Instance + * @retval None + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CFG_RSEL_6BIT + @arg @ref MD_ADC_CFG_RSEL_8BIT + @arg @ref MD_ADC_CFG_RSEL_10BIT + @arg @ref MD_ADC_CFG_RSEL_12BIT + */ +__STATIC_INLINE uint32_t md_adc_get_resolution_selection(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CFG, ADC_CFG_RSEL)) >> ADC_CFG_RSEL_POSS); +} + +/** + * @brief Direct memory access enable Enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_dma_access(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CFG, ADC_CFG_DMAEN); +} + +/** + * @brief Direct memory access enable Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_dma_access(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CFG, ADC_CFG_DMAEN); +} + +/** + * @brief Check if Direct memory access enable is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_dma_access(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CFG, ADC_CFG_DMAEN) == (ADC_CFG_DMAEN)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group10 SMPT1 + * @{ + */ +/** + * @brief Set ADC_SMPT1 Register + * @param ADCx ADC Instance + * @param ier + */ +__STATIC_INLINE void md_adc_set_smpt1(ADC_TypeDef *ADCx, uint32_t smpt1) +{ + WRITE_REG(ADCx->SMPT1, smpt1); +} + +/** + * @brief Get ADC_SMPT1 Register + * @param ADCx ADC Instance + */ +__STATIC_INLINE uint32_t md_adc_get_smpt1(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->SMPT1)); +} + +/** + * @brief Set Channel 2 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_2(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT1, ADC_SMPT1_CHT2, sample_time << ADC_SMPT1_CHT2_POSS); +} + +/** + * @brief Get Channel 2 sampling time. + * @param ADCx ADC Instance + * @retval Channel 2 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_2(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT1, ADC_SMPT1_CHT2) >> ADC_SMPT1_CHT2_POSS)); +} + +/** + * @brief Set Channel 1 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_1(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT1, ADC_SMPT1_CHT1, sample_time << ADC_SMPT1_CHT1_POSS); +} + +/** + * @brief Get Channel 0 sampling time. + * @param ADCx ADC Instance + * @retval Channel 0 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_1(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT1, ADC_SMPT1_CHT1) >> ADC_SMPT1_CHT1_POSS)); +} + +/** + * @brief Set Channel 0 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_0(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT1, ADC_SMPT1_CHT0, sample_time << ADC_SMPT1_CHT0_POSS); +} + +/** + * @brief Get Channel 0 sampling time. + * @param ADCx ADC Instance + * @retval Channel 0 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_0(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT1, ADC_SMPT1_CHT0) >> ADC_SMPT1_CHT0_POSS)); +} + +/** + * @brief Set ADC Converter Clock Division. + * @param ADCx ADC Instance + * @param ckdiv + @arg @ref MD_ADC_SMPT1_CKDIV_DIV1 + @arg @ref MD_ADC_SMPT1_CKDIV_DIV2 + @arg @ref MD_ADC_SMPT1_CKDIV_DIV4 + @arg @ref MD_ADC_SMPT1_CKDIV_DIV6 + @arg @ref MD_ADC_SMPT1_CKDIV_DIV8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_adc_clock_predivider(ADC_TypeDef *ADCx, uint32_t ckdiv) +{ + MODIFY_REG(ADCx->SMPT1, ADC_SMPT1_CKDIV, ckdiv << ADC_SMPT1_CKDIV_POSS); +} + +/** + * @brief Get ADC Converter Clock Division. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_SMPT1_CKDIV_DIV1 + @arg @ref MD_ADC_SMPT1_CKDIV_DIV2 + @arg @ref MD_ADC_SMPT1_CKDIV_DIV4 + @arg @ref MD_ADC_SMPT1_CKDIV_DIV6 + @arg @ref MD_ADC_SMPT1_CKDIV_DIV8 + */ +__STATIC_INLINE uint32_t md_adc_get_adc_clock_predivider(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT1, ADC_SMPT1_CKDIV)) >> ADC_SMPT1_CKDIV_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group11 SMPT2 + * @{ + */ +/** + * @brief Set ADC_SMPT2 Register + * @param ADCx ADC Instance + * @param smpt2 + * @retval None + */ +__STATIC_INLINE void md_adc_set_smpt2(ADC_TypeDef *ADCx, uint32_t smpt2) +{ + WRITE_REG(ADCx->SMPT2, smpt2); +} + +/** + * @brief Get ADC_SMPT2 Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_smpt2(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->SMPT2)); +} + +/** + * @brief Set Channel 6 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_6(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT2, ADC_SMPT2_CHT6, sample_time << ADC_SMPT2_CHT6_POSS); +} + +/** + * @brief Get Channel 6 sampling time. + * @param ADCx ADC Instance + * @retval Channel 6 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_6(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT2, ADC_SMPT2_CHT6) >> ADC_SMPT2_CHT6_POSS)); +} + +/** + * @brief Set Channel 6 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_5(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT2, ADC_SMPT2_CHT5, sample_time << ADC_SMPT2_CHT5_POSS); +} + +/** + * @brief Get Channel 5 sampling time. + * @param ADCx ADC Instance + * @retval Channel 5 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_5(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT2, ADC_SMPT2_CHT5) >> ADC_SMPT2_CHT5_POSS)); +} + +/** + * @brief Set Channel 4 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_4(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT2, ADC_SMPT2_CHT4, sample_time << ADC_SMPT2_CHT4_POSS); +} + +/** + * @brief Get Channel 4 sampling time. + * @param ADCx ADC Instance + * @retval Channel 6 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_4(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT2, ADC_SMPT2_CHT4) >> ADC_SMPT2_CHT4_POSS)); +} + +/** + * @brief Set Channel 3 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_3(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT2, ADC_SMPT2_CHT3, sample_time << ADC_SMPT2_CHT3_POSS); +} + +/** + * @brief Get Channel 3 sampling time. + * @param ADCx ADC Instance + * @retval Channel 6 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_3(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT2, ADC_SMPT2_CHT3) >> ADC_SMPT2_CHT3_POSS)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group12 SMPT3 + * @{ + */ +/** + * @brief Set ADC_SMPT3 Register + * @param ADCx ADC Instance + * @param smpt3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_smpt3(ADC_TypeDef *ADCx, uint32_t smpt3) +{ + WRITE_REG(ADCx->SMPT3, smpt3); +} + +/** + * @brief Get ADC_SMPT3 Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_smpt3(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->SMPT3)); +} + +/** + * @brief Set Channel 3 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_10(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT3, ADC_SMPT3_CHT10, sample_time << ADC_SMPT3_CHT10_POSS); +} + +/** + * @brief Get Channel 3 sampling time. + * @param ADCx ADC Instance + * @retval Channel 3 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_10(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT3, ADC_SMPT3_CHT10) >> ADC_SMPT3_CHT10_POSS)); +} + +/** + * @brief Set Channel 9 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_9(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT3, ADC_SMPT3_CHT9, sample_time << ADC_SMPT3_CHT9_POSS); +} + +/** + * @brief Get Channel 9 sampling time. + * @param ADCx ADC Instance + * @retval Channel 9 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_9(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT3, ADC_SMPT3_CHT9) >> ADC_SMPT3_CHT9_POSS)); +} + +/** + * @brief Set Channel 8 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_8(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT3, ADC_SMPT3_CHT8, sample_time << ADC_SMPT3_CHT8_POSS); +} + +/** + * @brief Get Channel 8 sampling time. + * @param ADCx ADC Instance + * @retval Channel 8 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_8(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT3, ADC_SMPT3_CHT8) >> ADC_SMPT3_CHT8_POSS)); +} + +/** + * @brief Set Channel 7 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_7(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT3, ADC_SMPT3_CHT7, sample_time << ADC_SMPT3_CHT7_POSS); +} + +/** + * @brief Get Channel 7 sampling time. + * @param ADCx ADC Instance + * @retval Channel 7 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_7(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT3, ADC_SMPT3_CHT7) >> ADC_SMPT3_CHT7_POSS)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group13 SMPT4 + * @{ + */ +/** + * @brief Set ADC_SMPT4 Register + * @param ADCx ADC Instance + * @param smpt4 + * @retval None + */ +__STATIC_INLINE void md_adc_set_smpt4(ADC_TypeDef *ADCx, uint32_t smpt4) +{ + WRITE_REG(ADCx->SMPT4, smpt4); +} + +/** + * @brief Get ADC_SMPT4 Register + * @param ADCx ADC Instance + */ +__STATIC_INLINE uint32_t md_adc_get_smpt4(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->SMPT4)); +} + +/** + * @brief Set Channel 14 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_14(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT4, ADC_SMPT4_CHT14, sample_time << ADC_SMPT4_CHT14_POSS); +} + +/** + * @brief Get Channel 14 sampling time. + * @param ADCx ADC Instance + * @retval Channel 14 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_14(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT4, ADC_SMPT4_CHT14) >> ADC_SMPT4_CHT14_POSS)); +} + +/** + * @brief Set Channel 13 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_13(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT4, ADC_SMPT4_CHT13, sample_time << ADC_SMPT4_CHT13_POSS); +} + +/** + * @brief Get Channel 13 sampling time. + * @param ADCx ADC Instance + * @retval Channel 13 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_13(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT4, ADC_SMPT4_CHT13) >> ADC_SMPT4_CHT13_POSS)); +} + +/** + * @brief Set Channel 12 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_12(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT4, ADC_SMPT4_CHT12, sample_time << ADC_SMPT4_CHT12_POSS); +} + +/** + * @brief Get Channel 12 sampling time. + * @param ADCx ADC Instance + * @retval Channel 12 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_12(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT4, ADC_SMPT4_CHT12) >> ADC_SMPT4_CHT12_POSS)); +} + +/** + * @brief Set Channel 11 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_11(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT4, ADC_SMPT4_CHT11, sample_time << ADC_SMPT4_CHT11_POSS); +} + +/** + * @brief Get Channel 11 sampling time. + * @param ADCx ADC Instance + * @retval Channel 11 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_11(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT4, ADC_SMPT4_CHT11) >> ADC_SMPT4_CHT11_POSS)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group14 SMPT5 + * @{ + */ +/** + * @brief Set ADC_SMPT5 Register + * @param ADCx ADC Instance + * @param smpt5 + * @retval None + */ +__STATIC_INLINE void md_adc_set_smpt5(ADC_TypeDef *ADCx, uint32_t smpt5) +{ + WRITE_REG(ADCx->SMPT5, smpt5); +} + +/** + * @brief Get ADC_SMPT5 Register + * @param ADCx ADC Instance + */ +__STATIC_INLINE uint32_t md_adc_get_smpt5(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->SMPT5)); +} + +/** + * @brief Set Channel 18 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_18(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT5, ADC_SMPT5_CHT18, sample_time << ADC_SMPT5_CHT18_POSS); +} + +/** + * @brief Get Channel 18 sampling time. + * @param ADCx ADC Instance + * @retval Channel 18 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_18(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT5, ADC_SMPT5_CHT18) >> ADC_SMPT5_CHT18_POSS)); +} + +/** + * @brief Set Channel 17 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_17(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT5, ADC_SMPT5_CHT17, sample_time << ADC_SMPT5_CHT17_POSS); +} + +/** + * @brief Get Channel 17 sampling time. + * @param ADCx ADC Instance + * @retval Channel 17 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_17(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT5, ADC_SMPT5_CHT17) >> ADC_SMPT5_CHT17_POSS)); +} + +/** + * @brief Set Channel 16 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_16(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT5, ADC_SMPT5_CHT16, sample_time << ADC_SMPT5_CHT16_POSS); +} + +/** + * @brief Get Channel 16 sampling time. + * @param ADCx ADC Instance + * @retval Channel 16 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_16(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT5, ADC_SMPT5_CHT16) >> ADC_SMPT5_CHT16_POSS)); +} + +/** + * @brief Set Channel 15 sampling time. + * @param ADCx ADC Instance + * @param sample_time + * @retval None + */ +__STATIC_INLINE void md_adc_set_sampletime_channel_15(ADC_TypeDef *ADCx, uint32_t sample_time) +{ + MODIFY_REG(ADCx->SMPT5, ADC_SMPT5_CHT15, sample_time << ADC_SMPT5_CHT15_POSS); +} + +/** + * @brief Get Channel 15 sampling time. + * @param ADCx ADC Instance + * @retval Channel 15 sampling time + */ +__STATIC_INLINE uint32_t md_adc_get_sampletime_channel_15(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->SMPT5, ADC_SMPT5_CHT15) >> ADC_SMPT5_CHT15_POSS)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group15 WDTH + * @{ + */ +/** + * @brief Set ADC_WDTH Register + * @param ADCx ADC Instance + * @param wdth + * @retval None + */ +__STATIC_INLINE void md_adc_set_wdth(ADC_TypeDef *ADCx, uint32_t wdth) +{ + WRITE_REG(ADCx->WDTH, wdth); +} + +/** + * @brief Get ADC_WDTH Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_wdth(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->WDTH)); +} + +/** + * @brief Set Analog watchdog higher threshold. + * @param ADCx ADC Instance + * @param ht + * @retval None + */ +__STATIC_INLINE void md_adc_set_awdg_high_threshold(ADC_TypeDef *ADCx, uint32_t ht) +{ + MODIFY_REG(ADCx->WDTH, ADC_WDTH_HT, ht << ADC_WDTH_HT_POSS); +} + +/** + * @brief Get Analog watchdog higher threshold. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_awdg_high_threshold(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->WDTH, ADC_WDTH_HT)) >> ADC_WDTH_HT_POSS); +} + +/** + * @brief Set Analog watchdog lower threshold. + * @param ADCx ADC Instance + * @param lt + * @retval None + */ +__STATIC_INLINE void md_adc_set_awdg_low_threshold(ADC_TypeDef *ADCx, uint32_t lt) +{ + MODIFY_REG(ADCx->WDTH, ADC_WDTH_LT, lt << ADC_WDTH_LT_POSS); +} + +/** + * @brief Get Analog watchdog lower threshold. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_awdg_low_threshold(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->WDTH, ADC_WDTH_LT)) >> ADC_WDTH_LT_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group16 NCHS1 + * @{ + */ +/** + * @brief Set ADC_NCHS1 Register + * @param ADCx ADC Instance + * @param nchs1 + * @retval None + */ +__STATIC_INLINE void md_adc_set_nchs1(ADC_TypeDef *ADCx, uint32_t nchs1) +{ + WRITE_REG(ADCx->NCHS1, nchs1); +} + +/** + * @brief Get ADC_NCHS1 Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_nchs1(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->NCHS1)); +} + +/** + * @brief Set 4th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns4 + @arg @ref MD_ADC_NCHS1_NS4_CH0 + @arg @ref MD_ADC_NCHS1_NS4_CH1 + @arg @ref MD_ADC_NCHS1_NS4_CH2 + @arg @ref MD_ADC_NCHS1_NS4_CH3 + @arg @ref MD_ADC_NCHS1_NS4_CH4 + @arg @ref MD_ADC_NCHS1_NS4_CH5 + @arg @ref MD_ADC_NCHS1_NS4_CH6 + @arg @ref MD_ADC_NCHS1_NS4_CH7 + @arg @ref MD_ADC_NCHS1_NS4_CH8 + @arg @ref MD_ADC_NCHS1_NS4_CH9 + @arg @ref MD_ADC_NCHS1_NS4_CH10 + @arg @ref MD_ADC_NCHS1_NS4_CH11 + @arg @ref MD_ADC_NCHS1_NS4_CH12 + @arg @ref MD_ADC_NCHS1_NS4_CH13 + @arg @ref MD_ADC_NCHS1_NS4_CH14 + @arg @ref MD_ADC_NCHS1_NS4_CH15 + @arg @ref MD_ADC_NCHS1_NS4_CH16 + @arg @ref MD_ADC_NCHS1_NS4_CH17 + @arg @ref MD_ADC_NCHS1_NS4_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_4th(ADC_TypeDef *ADCx, uint32_t ns4) +{ + MODIFY_REG(ADCx->NCHS1, ADC_NCHS1_NS4, ns4 << ADC_NCHS1_NS4_POSS); +} + +/** + * @brief Get 4th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS1_NS4_CH0 + @arg @ref MD_ADC_NCHS1_NS4_CH1 + @arg @ref MD_ADC_NCHS1_NS4_CH2 + @arg @ref MD_ADC_NCHS1_NS4_CH3 + @arg @ref MD_ADC_NCHS1_NS4_CH4 + @arg @ref MD_ADC_NCHS1_NS4_CH5 + @arg @ref MD_ADC_NCHS1_NS4_CH6 + @arg @ref MD_ADC_NCHS1_NS4_CH7 + @arg @ref MD_ADC_NCHS1_NS4_CH8 + @arg @ref MD_ADC_NCHS1_NS4_CH9 + @arg @ref MD_ADC_NCHS1_NS4_CH10 + @arg @ref MD_ADC_NCHS1_NS4_CH11 + @arg @ref MD_ADC_NCHS1_NS4_CH12 + @arg @ref MD_ADC_NCHS1_NS4_CH13 + @arg @ref MD_ADC_NCHS1_NS4_CH14 + @arg @ref MD_ADC_NCHS1_NS4_CH15 + @arg @ref MD_ADC_NCHS1_NS4_CH16 + @arg @ref MD_ADC_NCHS1_NS4_CH17 + @arg @ref MD_ADC_NCHS1_NS4_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_4th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS1, ADC_NCHS1_NS4)) >> ADC_NCHS1_NS4_POSS); +} + +/** + * @brief Set 3th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns3 + @arg @ref MD_ADC_NCHS1_NS3_CH0 + @arg @ref MD_ADC_NCHS1_NS3_CH1 + @arg @ref MD_ADC_NCHS1_NS3_CH2 + @arg @ref MD_ADC_NCHS1_NS3_CH3 + @arg @ref MD_ADC_NCHS1_NS3_CH4 + @arg @ref MD_ADC_NCHS1_NS3_CH5 + @arg @ref MD_ADC_NCHS1_NS3_CH6 + @arg @ref MD_ADC_NCHS1_NS3_CH7 + @arg @ref MD_ADC_NCHS1_NS3_CH8 + @arg @ref MD_ADC_NCHS1_NS3_CH9 + @arg @ref MD_ADC_NCHS1_NS3_CH10 + @arg @ref MD_ADC_NCHS1_NS3_CH11 + @arg @ref MD_ADC_NCHS1_NS3_CH12 + @arg @ref MD_ADC_NCHS1_NS3_CH13 + @arg @ref MD_ADC_NCHS1_NS3_CH14 + @arg @ref MD_ADC_NCHS1_NS3_CH15 + @arg @ref MD_ADC_NCHS1_NS3_CH16 + @arg @ref MD_ADC_NCHS1_NS3_CH17 + @arg @ref MD_ADC_NCHS1_NS3_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_3th(ADC_TypeDef *ADCx, uint32_t ns3) +{ + MODIFY_REG(ADCx->NCHS1, ADC_NCHS1_NS3, ns3 << ADC_NCHS1_NS3_POSS); +} + +/** + * @brief Get 3th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS1_NS3_CH0 + @arg @ref MD_ADC_NCHS1_NS3_CH1 + @arg @ref MD_ADC_NCHS1_NS3_CH2 + @arg @ref MD_ADC_NCHS1_NS3_CH3 + @arg @ref MD_ADC_NCHS1_NS3_CH4 + @arg @ref MD_ADC_NCHS1_NS3_CH5 + @arg @ref MD_ADC_NCHS1_NS3_CH6 + @arg @ref MD_ADC_NCHS1_NS3_CH7 + @arg @ref MD_ADC_NCHS1_NS3_CH8 + @arg @ref MD_ADC_NCHS1_NS3_CH9 + @arg @ref MD_ADC_NCHS1_NS3_CH10 + @arg @ref MD_ADC_NCHS1_NS3_CH11 + @arg @ref MD_ADC_NCHS1_NS3_CH12 + @arg @ref MD_ADC_NCHS1_NS3_CH13 + @arg @ref MD_ADC_NCHS1_NS3_CH14 + @arg @ref MD_ADC_NCHS1_NS3_CH15 + @arg @ref MD_ADC_NCHS1_NS3_CH16 + @arg @ref MD_ADC_NCHS1_NS3_CH17 + @arg @ref MD_ADC_NCHS1_NS3_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_3th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS1, ADC_NCHS1_NS3)) >> ADC_NCHS1_NS3_POSS); +} + +/** + * @brief Set 2th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns2 + @arg @ref MD_ADC_NCHS1_NS2_CH0 + @arg @ref MD_ADC_NCHS1_NS2_CH1 + @arg @ref MD_ADC_NCHS1_NS2_CH2 + @arg @ref MD_ADC_NCHS1_NS2_CH3 + @arg @ref MD_ADC_NCHS1_NS2_CH4 + @arg @ref MD_ADC_NCHS1_NS2_CH5 + @arg @ref MD_ADC_NCHS1_NS2_CH6 + @arg @ref MD_ADC_NCHS1_NS2_CH7 + @arg @ref MD_ADC_NCHS1_NS2_CH8 + @arg @ref MD_ADC_NCHS1_NS2_CH9 + @arg @ref MD_ADC_NCHS1_NS2_CH10 + @arg @ref MD_ADC_NCHS1_NS2_CH11 + @arg @ref MD_ADC_NCHS1_NS2_CH12 + @arg @ref MD_ADC_NCHS1_NS2_CH13 + @arg @ref MD_ADC_NCHS1_NS2_CH14 + @arg @ref MD_ADC_NCHS1_NS2_CH15 + @arg @ref MD_ADC_NCHS1_NS2_CH16 + @arg @ref MD_ADC_NCHS1_NS2_CH17 + @arg @ref MD_ADC_NCHS1_NS2_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_2th(ADC_TypeDef *ADCx, uint32_t ns2) +{ + MODIFY_REG(ADCx->NCHS1, ADC_NCHS1_NS2, ns2 << ADC_NCHS1_NS2_POSS); +} + +/** + * @brief Get 2th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS1_NS2_CH0 + @arg @ref MD_ADC_NCHS1_NS2_CH1 + @arg @ref MD_ADC_NCHS1_NS2_CH2 + @arg @ref MD_ADC_NCHS1_NS2_CH3 + @arg @ref MD_ADC_NCHS1_NS2_CH4 + @arg @ref MD_ADC_NCHS1_NS2_CH5 + @arg @ref MD_ADC_NCHS1_NS2_CH6 + @arg @ref MD_ADC_NCHS1_NS2_CH7 + @arg @ref MD_ADC_NCHS1_NS2_CH8 + @arg @ref MD_ADC_NCHS1_NS2_CH9 + @arg @ref MD_ADC_NCHS1_NS2_CH10 + @arg @ref MD_ADC_NCHS1_NS2_CH11 + @arg @ref MD_ADC_NCHS1_NS2_CH12 + @arg @ref MD_ADC_NCHS1_NS2_CH13 + @arg @ref MD_ADC_NCHS1_NS2_CH14 + @arg @ref MD_ADC_NCHS1_NS2_CH15 + @arg @ref MD_ADC_NCHS1_NS2_CH16 + @arg @ref MD_ADC_NCHS1_NS2_CH17 + @arg @ref MD_ADC_NCHS1_NS2_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_2th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS1, ADC_NCHS1_NS2)) >> ADC_NCHS1_NS2_POSS); +} + +/** + * @brief Set 1th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns1 + @arg @ref MD_ADC_NCHS1_NS1_CH0 + @arg @ref MD_ADC_NCHS1_NS1_CH1 + @arg @ref MD_ADC_NCHS1_NS1_CH2 + @arg @ref MD_ADC_NCHS1_NS1_CH3 + @arg @ref MD_ADC_NCHS1_NS1_CH4 + @arg @ref MD_ADC_NCHS1_NS1_CH5 + @arg @ref MD_ADC_NCHS1_NS1_CH6 + @arg @ref MD_ADC_NCHS1_NS1_CH7 + @arg @ref MD_ADC_NCHS1_NS1_CH8 + @arg @ref MD_ADC_NCHS1_NS1_CH9 + @arg @ref MD_ADC_NCHS1_NS1_CH10 + @arg @ref MD_ADC_NCHS1_NS1_CH11 + @arg @ref MD_ADC_NCHS1_NS1_CH12 + @arg @ref MD_ADC_NCHS1_NS1_CH13 + @arg @ref MD_ADC_NCHS1_NS1_CH14 + @arg @ref MD_ADC_NCHS1_NS1_CH15 + @arg @ref MD_ADC_NCHS1_NS1_CH16 + @arg @ref MD_ADC_NCHS1_NS1_CH17 + @arg @ref MD_ADC_NCHS1_NS1_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_1th(ADC_TypeDef *ADCx, uint32_t ns1) +{ + MODIFY_REG(ADCx->NCHS1, ADC_NCHS1_NS1, ns1 << ADC_NCHS1_NS1_POSS); +} + +/** + * @brief Get 1th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS1_NS1_CH0 + @arg @ref MD_ADC_NCHS1_NS1_CH1 + @arg @ref MD_ADC_NCHS1_NS1_CH2 + @arg @ref MD_ADC_NCHS1_NS1_CH3 + @arg @ref MD_ADC_NCHS1_NS1_CH4 + @arg @ref MD_ADC_NCHS1_NS1_CH5 + @arg @ref MD_ADC_NCHS1_NS1_CH6 + @arg @ref MD_ADC_NCHS1_NS1_CH7 + @arg @ref MD_ADC_NCHS1_NS1_CH8 + @arg @ref MD_ADC_NCHS1_NS1_CH9 + @arg @ref MD_ADC_NCHS1_NS1_CH10 + @arg @ref MD_ADC_NCHS1_NS1_CH11 + @arg @ref MD_ADC_NCHS1_NS1_CH12 + @arg @ref MD_ADC_NCHS1_NS1_CH13 + @arg @ref MD_ADC_NCHS1_NS1_CH14 + @arg @ref MD_ADC_NCHS1_NS1_CH15 + @arg @ref MD_ADC_NCHS1_NS1_CH16 + @arg @ref MD_ADC_NCHS1_NS1_CH17 + @arg @ref MD_ADC_NCHS1_NS1_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_1th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS1, ADC_NCHS1_NS1)) >> ADC_NCHS1_NS1_POSS); +} + +/** + * @brief Set Regular channel sequence length. + * @param ADCx ADC Instance + * @param nsl + @arg @ref MD_ADC_NCHS1_NSL_1CON + @arg @ref MD_ADC_NCHS1_NSL_2CON + @arg @ref MD_ADC_NCHS1_NSL_3CON + @arg @ref MD_ADC_NCHS1_NSL_4CON + @arg @ref MD_ADC_NCHS1_NSL_5CON + @arg @ref MD_ADC_NCHS1_NSL_6CON + @arg @ref MD_ADC_NCHS1_NSL_7CON + @arg @ref MD_ADC_NCHS1_NSL_8CON + @arg @ref MD_ADC_NCHS1_NSL_9CON + @arg @ref MD_ADC_NCHS1_NSL_10CON + @arg @ref MD_ADC_NCHS1_NSL_11CON + @arg @ref MD_ADC_NCHS1_NSL_12CON + @arg @ref MD_ADC_NCHS1_NSL_13CON + @arg @ref MD_ADC_NCHS1_NSL_14CON + @arg @ref MD_ADC_NCHS1_NSL_15CON + @arg @ref MD_ADC_NCHS1_NSL_16CON + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_length(ADC_TypeDef *ADCx, uint32_t nsl) +{ + MODIFY_REG(ADCx->NCHS1, ADC_NCHS1_NSL, nsl << ADC_NCHS1_NSL_POSS); +} + +/** + * @brief Get Regular channel sequence length. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS1_NSL_1CON + @arg @ref MD_ADC_NCHS1_NSL_2CON + @arg @ref MD_ADC_NCHS1_NSL_3CON + @arg @ref MD_ADC_NCHS1_NSL_4CON + @arg @ref MD_ADC_NCHS1_NSL_5CON + @arg @ref MD_ADC_NCHS1_NSL_6CON + @arg @ref MD_ADC_NCHS1_NSL_7CON + @arg @ref MD_ADC_NCHS1_NSL_8CON + @arg @ref MD_ADC_NCHS1_NSL_9CON + @arg @ref MD_ADC_NCHS1_NSL_10CON + @arg @ref MD_ADC_NCHS1_NSL_11CON + @arg @ref MD_ADC_NCHS1_NSL_12CON + @arg @ref MD_ADC_NCHS1_NSL_13CON + @arg @ref MD_ADC_NCHS1_NSL_14CON + @arg @ref MD_ADC_NCHS1_NSL_15CON + @arg @ref MD_ADC_NCHS1_NSL_16CON + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_length(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS1, ADC_NCHS1_NSL)) >> ADC_NCHS1_NSL_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group17 NCHS2 + * @{ + */ +/** + * @brief Set ADC_NCHS2 Register + * @param ADCx ADC Instance + * @param nchs2 + * @retval None + */ +__STATIC_INLINE void md_adc_set_nchs2(ADC_TypeDef *ADCx, uint32_t nchs2) +{ + WRITE_REG(ADCx->NCHS2, nchs2); +} + +/** + * @brief Get ADC_NCHS2 Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_nchs2(ADC_TypeDef *ADCx) +{ + return (uint32_t)READ_REG(ADCx->NCHS2); +} + +/** + * @brief Set 9th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns9 + @arg @ref MD_ADC_NCHS2_NS9_CH0 + @arg @ref MD_ADC_NCHS2_NS9_CH1 + @arg @ref MD_ADC_NCHS2_NS9_CH2 + @arg @ref MD_ADC_NCHS2_NS9_CH3 + @arg @ref MD_ADC_NCHS2_NS9_CH4 + @arg @ref MD_ADC_NCHS2_NS9_CH5 + @arg @ref MD_ADC_NCHS2_NS9_CH6 + @arg @ref MD_ADC_NCHS2_NS9_CH7 + @arg @ref MD_ADC_NCHS2_NS9_CH8 + @arg @ref MD_ADC_NCHS2_NS9_CH9 + @arg @ref MD_ADC_NCHS2_NS9_CH10 + @arg @ref MD_ADC_NCHS2_NS9_CH11 + @arg @ref MD_ADC_NCHS2_NS9_CH12 + @arg @ref MD_ADC_NCHS2_NS9_CH13 + @arg @ref MD_ADC_NCHS2_NS9_CH14 + @arg @ref MD_ADC_NCHS2_NS9_CH15 + @arg @ref MD_ADC_NCHS2_NS9_CH16 + @arg @ref MD_ADC_NCHS2_NS9_CH17 + @arg @ref MD_ADC_NCHS2_NS9_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_9th(ADC_TypeDef *ADCx, uint32_t ns9) +{ + MODIFY_REG(ADCx->NCHS2, ADC_NCHS2_NS9, ns9 << ADC_NCHS2_NS9_POSS); +} + +/** + * @brief Get 9th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS2_NS9_CH0 + @arg @ref MD_ADC_NCHS2_NS9_CH1 + @arg @ref MD_ADC_NCHS2_NS9_CH2 + @arg @ref MD_ADC_NCHS2_NS9_CH3 + @arg @ref MD_ADC_NCHS2_NS9_CH4 + @arg @ref MD_ADC_NCHS2_NS9_CH5 + @arg @ref MD_ADC_NCHS2_NS9_CH6 + @arg @ref MD_ADC_NCHS2_NS9_CH7 + @arg @ref MD_ADC_NCHS2_NS9_CH8 + @arg @ref MD_ADC_NCHS2_NS9_CH9 + @arg @ref MD_ADC_NCHS2_NS9_CH10 + @arg @ref MD_ADC_NCHS2_NS9_CH11 + @arg @ref MD_ADC_NCHS2_NS9_CH12 + @arg @ref MD_ADC_NCHS2_NS9_CH13 + @arg @ref MD_ADC_NCHS2_NS9_CH14 + @arg @ref MD_ADC_NCHS2_NS9_CH15 + @arg @ref MD_ADC_NCHS2_NS9_CH16 + @arg @ref MD_ADC_NCHS2_NS9_CH17 + @arg @ref MD_ADC_NCHS2_NS9_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_9th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS2, ADC_NCHS2_NS9)) >> ADC_NCHS2_NS9_POSS); +} + +/** + * @brief Set 8th conversion in regular sequence. + * @param ADCx ADC Instance + @arg @ref MD_ADC_NCHS2_NS8_CH0 + @arg @ref MD_ADC_NCHS2_NS8_CH1 + @arg @ref MD_ADC_NCHS2_NS8_CH2 + @arg @ref MD_ADC_NCHS2_NS8_CH3 + @arg @ref MD_ADC_NCHS2_NS8_CH4 + @arg @ref MD_ADC_NCHS2_NS8_CH5 + @arg @ref MD_ADC_NCHS2_NS8_CH6 + @arg @ref MD_ADC_NCHS2_NS8_CH7 + @arg @ref MD_ADC_NCHS2_NS8_CH8 + @arg @ref MD_ADC_NCHS2_NS8_CH9 + @arg @ref MD_ADC_NCHS2_NS8_CH10 + @arg @ref MD_ADC_NCHS2_NS8_CH11 + @arg @ref MD_ADC_NCHS2_NS8_CH12 + @arg @ref MD_ADC_NCHS2_NS8_CH13 + @arg @ref MD_ADC_NCHS2_NS8_CH14 + @arg @ref MD_ADC_NCHS2_NS8_CH15 + @arg @ref MD_ADC_NCHS2_NS8_CH16 + @arg @ref MD_ADC_NCHS2_NS8_CH17 + @arg @ref MD_ADC_NCHS2_NS8_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_8th(ADC_TypeDef *ADCx, uint32_t ns8) +{ + MODIFY_REG(ADCx->NCHS2, ADC_NCHS2_NS8, ns8 << ADC_NCHS2_NS8_POSS); +} + +/** + * @brief Get 8th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS2_NS8_CH0 + @arg @ref MD_ADC_NCHS2_NS8_CH1 + @arg @ref MD_ADC_NCHS2_NS8_CH2 + @arg @ref MD_ADC_NCHS2_NS8_CH3 + @arg @ref MD_ADC_NCHS2_NS8_CH4 + @arg @ref MD_ADC_NCHS2_NS8_CH5 + @arg @ref MD_ADC_NCHS2_NS8_CH6 + @arg @ref MD_ADC_NCHS2_NS8_CH7 + @arg @ref MD_ADC_NCHS2_NS8_CH8 + @arg @ref MD_ADC_NCHS2_NS8_CH9 + @arg @ref MD_ADC_NCHS2_NS8_CH10 + @arg @ref MD_ADC_NCHS2_NS8_CH11 + @arg @ref MD_ADC_NCHS2_NS8_CH12 + @arg @ref MD_ADC_NCHS2_NS8_CH13 + @arg @ref MD_ADC_NCHS2_NS8_CH14 + @arg @ref MD_ADC_NCHS2_NS8_CH15 + @arg @ref MD_ADC_NCHS2_NS8_CH16 + @arg @ref MD_ADC_NCHS2_NS8_CH17 + @arg @ref MD_ADC_NCHS2_NS8_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_8th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS2, ADC_NCHS2_NS8)) >> ADC_NCHS2_NS8_POSS); +} + +/** + * @brief Set 7th conversion in regular sequence. + * @param ADCx ADC Instance + @arg @ref MD_ADC_NCHS2_NS7_CH0 + @arg @ref MD_ADC_NCHS2_NS7_CH1 + @arg @ref MD_ADC_NCHS2_NS7_CH2 + @arg @ref MD_ADC_NCHS2_NS7_CH3 + @arg @ref MD_ADC_NCHS2_NS7_CH4 + @arg @ref MD_ADC_NCHS2_NS7_CH5 + @arg @ref MD_ADC_NCHS2_NS7_CH6 + @arg @ref MD_ADC_NCHS2_NS7_CH7 + @arg @ref MD_ADC_NCHS2_NS7_CH8 + @arg @ref MD_ADC_NCHS2_NS7_CH9 + @arg @ref MD_ADC_NCHS2_NS7_CH10 + @arg @ref MD_ADC_NCHS2_NS7_CH11 + @arg @ref MD_ADC_NCHS2_NS7_CH12 + @arg @ref MD_ADC_NCHS2_NS7_CH13 + @arg @ref MD_ADC_NCHS2_NS7_CH14 + @arg @ref MD_ADC_NCHS2_NS7_CH15 + @arg @ref MD_ADC_NCHS2_NS7_CH16 + @arg @ref MD_ADC_NCHS2_NS7_CH17 + @arg @ref MD_ADC_NCHS2_NS7_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_7th(ADC_TypeDef *ADCx, uint32_t ns7) +{ + MODIFY_REG(ADCx->NCHS2, ADC_NCHS2_NS7, ns7 << ADC_NCHS2_NS7_POSS); +} + +/** + * @brief Get 7th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS2_NS7_CH0 + @arg @ref MD_ADC_NCHS2_NS7_CH1 + @arg @ref MD_ADC_NCHS2_NS7_CH2 + @arg @ref MD_ADC_NCHS2_NS7_CH3 + @arg @ref MD_ADC_NCHS2_NS7_CH4 + @arg @ref MD_ADC_NCHS2_NS7_CH5 + @arg @ref MD_ADC_NCHS2_NS7_CH6 + @arg @ref MD_ADC_NCHS2_NS7_CH7 + @arg @ref MD_ADC_NCHS2_NS7_CH8 + @arg @ref MD_ADC_NCHS2_NS7_CH9 + @arg @ref MD_ADC_NCHS2_NS7_CH10 + @arg @ref MD_ADC_NCHS2_NS7_CH11 + @arg @ref MD_ADC_NCHS2_NS7_CH12 + @arg @ref MD_ADC_NCHS2_NS7_CH13 + @arg @ref MD_ADC_NCHS2_NS7_CH14 + @arg @ref MD_ADC_NCHS2_NS7_CH15 + @arg @ref MD_ADC_NCHS2_NS7_CH16 + @arg @ref MD_ADC_NCHS2_NS7_CH17 + @arg @ref MD_ADC_NCHS2_NS7_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_7th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS2, ADC_NCHS2_NS7)) >> ADC_NCHS2_NS7_POSS); +} + +/** + * @brief Set 6th conversion in regular sequence. + * @param ADCx ADC Instance + @arg @ref MD_ADC_NCHS2_NS6_CH0 + @arg @ref MD_ADC_NCHS2_NS6_CH1 + @arg @ref MD_ADC_NCHS2_NS6_CH2 + @arg @ref MD_ADC_NCHS2_NS6_CH3 + @arg @ref MD_ADC_NCHS2_NS6_CH4 + @arg @ref MD_ADC_NCHS2_NS6_CH5 + @arg @ref MD_ADC_NCHS2_NS6_CH6 + @arg @ref MD_ADC_NCHS2_NS6_CH7 + @arg @ref MD_ADC_NCHS2_NS6_CH8 + @arg @ref MD_ADC_NCHS2_NS6_CH9 + @arg @ref MD_ADC_NCHS2_NS6_CH10 + @arg @ref MD_ADC_NCHS2_NS6_CH11 + @arg @ref MD_ADC_NCHS2_NS6_CH12 + @arg @ref MD_ADC_NCHS2_NS6_CH13 + @arg @ref MD_ADC_NCHS2_NS6_CH14 + @arg @ref MD_ADC_NCHS2_NS6_CH15 + @arg @ref MD_ADC_NCHS2_NS6_CH16 + @arg @ref MD_ADC_NCHS2_NS6_CH17 + @arg @ref MD_ADC_NCHS2_NS6_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_6th(ADC_TypeDef *ADCx, uint32_t ns6) +{ + MODIFY_REG(ADCx->NCHS2, ADC_NCHS2_NS6, ns6 << ADC_NCHS2_NS6_POSS); +} + +/** + * @brief Get 6th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS2_NS6_CH0 + @arg @ref MD_ADC_NCHS2_NS6_CH1 + @arg @ref MD_ADC_NCHS2_NS6_CH2 + @arg @ref MD_ADC_NCHS2_NS6_CH3 + @arg @ref MD_ADC_NCHS2_NS6_CH4 + @arg @ref MD_ADC_NCHS2_NS6_CH5 + @arg @ref MD_ADC_NCHS2_NS6_CH6 + @arg @ref MD_ADC_NCHS2_NS6_CH7 + @arg @ref MD_ADC_NCHS2_NS6_CH8 + @arg @ref MD_ADC_NCHS2_NS6_CH9 + @arg @ref MD_ADC_NCHS2_NS6_CH10 + @arg @ref MD_ADC_NCHS2_NS6_CH11 + @arg @ref MD_ADC_NCHS2_NS6_CH12 + @arg @ref MD_ADC_NCHS2_NS6_CH13 + @arg @ref MD_ADC_NCHS2_NS6_CH14 + @arg @ref MD_ADC_NCHS2_NS6_CH15 + @arg @ref MD_ADC_NCHS2_NS6_CH16 + @arg @ref MD_ADC_NCHS2_NS6_CH17 + @arg @ref MD_ADC_NCHS2_NS6_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_6th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS2, ADC_NCHS2_NS6)) >> ADC_NCHS2_NS6_POSS); +} + +/** + * @brief Set 5th conversion in regular sequence. + * @param ADCx ADC Instance + @arg @ref MD_ADC_NCHS2_NS5_CH0 + @arg @ref MD_ADC_NCHS2_NS5_CH1 + @arg @ref MD_ADC_NCHS2_NS5_CH2 + @arg @ref MD_ADC_NCHS2_NS5_CH3 + @arg @ref MD_ADC_NCHS2_NS5_CH4 + @arg @ref MD_ADC_NCHS2_NS5_CH5 + @arg @ref MD_ADC_NCHS2_NS5_CH6 + @arg @ref MD_ADC_NCHS2_NS5_CH7 + @arg @ref MD_ADC_NCHS2_NS5_CH8 + @arg @ref MD_ADC_NCHS2_NS5_CH9 + @arg @ref MD_ADC_NCHS2_NS5_CH10 + @arg @ref MD_ADC_NCHS2_NS5_CH11 + @arg @ref MD_ADC_NCHS2_NS5_CH12 + @arg @ref MD_ADC_NCHS2_NS5_CH13 + @arg @ref MD_ADC_NCHS2_NS5_CH14 + @arg @ref MD_ADC_NCHS2_NS5_CH15 + @arg @ref MD_ADC_NCHS2_NS5_CH16 + @arg @ref MD_ADC_NCHS2_NS5_CH17 + @arg @ref MD_ADC_NCHS2_NS5_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_5th(ADC_TypeDef *ADCx, uint32_t ns5) +{ + MODIFY_REG(ADCx->NCHS2, ADC_NCHS2_NS5, ns5 << ADC_NCHS2_NS5_POSS); +} + +/** + * @brief Get 5th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS2_NS5_CH0 + @arg @ref MD_ADC_NCHS2_NS5_CH1 + @arg @ref MD_ADC_NCHS2_NS5_CH2 + @arg @ref MD_ADC_NCHS2_NS5_CH3 + @arg @ref MD_ADC_NCHS2_NS5_CH4 + @arg @ref MD_ADC_NCHS2_NS5_CH5 + @arg @ref MD_ADC_NCHS2_NS5_CH6 + @arg @ref MD_ADC_NCHS2_NS5_CH7 + @arg @ref MD_ADC_NCHS2_NS5_CH8 + @arg @ref MD_ADC_NCHS2_NS5_CH9 + @arg @ref MD_ADC_NCHS2_NS5_CH10 + @arg @ref MD_ADC_NCHS2_NS5_CH11 + @arg @ref MD_ADC_NCHS2_NS5_CH12 + @arg @ref MD_ADC_NCHS2_NS5_CH13 + @arg @ref MD_ADC_NCHS2_NS5_CH14 + @arg @ref MD_ADC_NCHS2_NS5_CH15 + @arg @ref MD_ADC_NCHS2_NS5_CH16 + @arg @ref MD_ADC_NCHS2_NS5_CH17 + @arg @ref MD_ADC_NCHS2_NS5_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_5th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS2, ADC_NCHS2_NS5)) >> ADC_NCHS2_NS5_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group18 NCHS3 + * @{ + */ +/** + * @brief Set ADC_NCHS3 Register + * @param ADCx ADC Instance + * @param nchs3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_nchs3(ADC_TypeDef *ADCx, uint32_t nchs3) +{ + WRITE_REG(ADCx->NCHS3, nchs3); +} + +/** + * @brief Get ADC_NCHS3 Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_nchs3(ADC_TypeDef *ADCx) +{ + return (uint32_t)READ_REG(ADCx->NCHS3); +} + +/** + * @brief Set 14th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns14 + @arg @ref MD_ADC_NCHS3_NS14_CH0 + @arg @ref MD_ADC_NCHS3_NS14_CH1 + @arg @ref MD_ADC_NCHS3_NS14_CH2 + @arg @ref MD_ADC_NCHS3_NS14_CH3 + @arg @ref MD_ADC_NCHS3_NS14_CH4 + @arg @ref MD_ADC_NCHS3_NS14_CH5 + @arg @ref MD_ADC_NCHS3_NS14_CH6 + @arg @ref MD_ADC_NCHS3_NS14_CH7 + @arg @ref MD_ADC_NCHS3_NS14_CH8 + @arg @ref MD_ADC_NCHS3_NS14_CH9 + @arg @ref MD_ADC_NCHS3_NS14_CH10 + @arg @ref MD_ADC_NCHS3_NS14_CH11 + @arg @ref MD_ADC_NCHS3_NS14_CH12 + @arg @ref MD_ADC_NCHS3_NS14_CH13 + @arg @ref MD_ADC_NCHS3_NS14_CH14 + @arg @ref MD_ADC_NCHS3_NS14_CH15 + @arg @ref MD_ADC_NCHS3_NS14_CH16 + @arg @ref MD_ADC_NCHS3_NS14_CH17 + @arg @ref MD_ADC_NCHS3_NS14_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_14th(ADC_TypeDef *ADCx, uint32_t ns14) +{ + MODIFY_REG(ADCx->NCHS3, ADC_NCHS3_NS14, ns14 << ADC_NCHS3_NS14_POSS); +} + +/** + * @brief Get 14th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS3_NS14_CH0 + @arg @ref MD_ADC_NCHS3_NS14_CH1 + @arg @ref MD_ADC_NCHS3_NS14_CH2 + @arg @ref MD_ADC_NCHS3_NS14_CH3 + @arg @ref MD_ADC_NCHS3_NS14_CH4 + @arg @ref MD_ADC_NCHS3_NS14_CH5 + @arg @ref MD_ADC_NCHS3_NS14_CH6 + @arg @ref MD_ADC_NCHS3_NS14_CH7 + @arg @ref MD_ADC_NCHS3_NS14_CH8 + @arg @ref MD_ADC_NCHS3_NS14_CH9 + @arg @ref MD_ADC_NCHS3_NS14_CH10 + @arg @ref MD_ADC_NCHS3_NS14_CH11 + @arg @ref MD_ADC_NCHS3_NS14_CH12 + @arg @ref MD_ADC_NCHS3_NS14_CH13 + @arg @ref MD_ADC_NCHS3_NS14_CH14 + @arg @ref MD_ADC_NCHS3_NS14_CH15 + @arg @ref MD_ADC_NCHS3_NS14_CH16 + @arg @ref MD_ADC_NCHS3_NS14_CH17 + @arg @ref MD_ADC_NCHS3_NS14_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_14th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS3, ADC_NCHS3_NS14)) >> ADC_NCHS3_NS14_POSS); +} + +/** + * @brief Set 13th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns13 + @arg @ref MD_ADC_NCHS3_NS13_CH0 + @arg @ref MD_ADC_NCHS3_NS13_CH1 + @arg @ref MD_ADC_NCHS3_NS13_CH2 + @arg @ref MD_ADC_NCHS3_NS13_CH3 + @arg @ref MD_ADC_NCHS3_NS13_CH4 + @arg @ref MD_ADC_NCHS3_NS13_CH5 + @arg @ref MD_ADC_NCHS3_NS13_CH6 + @arg @ref MD_ADC_NCHS3_NS13_CH7 + @arg @ref MD_ADC_NCHS3_NS13_CH8 + @arg @ref MD_ADC_NCHS3_NS13_CH9 + @arg @ref MD_ADC_NCHS3_NS13_CH10 + @arg @ref MD_ADC_NCHS3_NS13_CH11 + @arg @ref MD_ADC_NCHS3_NS13_CH12 + @arg @ref MD_ADC_NCHS3_NS13_CH13 + @arg @ref MD_ADC_NCHS3_NS13_CH14 + @arg @ref MD_ADC_NCHS3_NS13_CH15 + @arg @ref MD_ADC_NCHS3_NS13_CH16 + @arg @ref MD_ADC_NCHS3_NS13_CH17 + @arg @ref MD_ADC_NCHS3_NS13_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_13th(ADC_TypeDef *ADCx, uint32_t ns13) +{ + MODIFY_REG(ADCx->NCHS3, ADC_NCHS3_NS13, ns13 << ADC_NCHS3_NS13_POSS); +} + +/** + * @brief Get 13th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS3_NS13_CH0 + @arg @ref MD_ADC_NCHS3_NS13_CH1 + @arg @ref MD_ADC_NCHS3_NS13_CH2 + @arg @ref MD_ADC_NCHS3_NS13_CH3 + @arg @ref MD_ADC_NCHS3_NS13_CH4 + @arg @ref MD_ADC_NCHS3_NS13_CH5 + @arg @ref MD_ADC_NCHS3_NS13_CH6 + @arg @ref MD_ADC_NCHS3_NS13_CH7 + @arg @ref MD_ADC_NCHS3_NS13_CH8 + @arg @ref MD_ADC_NCHS3_NS13_CH9 + @arg @ref MD_ADC_NCHS3_NS13_CH10 + @arg @ref MD_ADC_NCHS3_NS13_CH11 + @arg @ref MD_ADC_NCHS3_NS13_CH12 + @arg @ref MD_ADC_NCHS3_NS13_CH13 + @arg @ref MD_ADC_NCHS3_NS13_CH14 + @arg @ref MD_ADC_NCHS3_NS13_CH15 + @arg @ref MD_ADC_NCHS3_NS13_CH16 + @arg @ref MD_ADC_NCHS3_NS13_CH17 + @arg @ref MD_ADC_NCHS3_NS13_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_13th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS3, ADC_NCHS3_NS13)) >> ADC_NCHS3_NS13_POSS); +} + +/** + * @brief Set 12th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns12 + @arg @ref MD_ADC_NCHS3_NS12_CH0 + @arg @ref MD_ADC_NCHS3_NS12_CH1 + @arg @ref MD_ADC_NCHS3_NS12_CH2 + @arg @ref MD_ADC_NCHS3_NS12_CH3 + @arg @ref MD_ADC_NCHS3_NS12_CH4 + @arg @ref MD_ADC_NCHS3_NS12_CH5 + @arg @ref MD_ADC_NCHS3_NS12_CH6 + @arg @ref MD_ADC_NCHS3_NS12_CH7 + @arg @ref MD_ADC_NCHS3_NS12_CH8 + @arg @ref MD_ADC_NCHS3_NS12_CH9 + @arg @ref MD_ADC_NCHS3_NS12_CH10 + @arg @ref MD_ADC_NCHS3_NS12_CH11 + @arg @ref MD_ADC_NCHS3_NS12_CH12 + @arg @ref MD_ADC_NCHS3_NS12_CH13 + @arg @ref MD_ADC_NCHS3_NS12_CH14 + @arg @ref MD_ADC_NCHS3_NS12_CH15 + @arg @ref MD_ADC_NCHS3_NS12_CH16 + @arg @ref MD_ADC_NCHS3_NS12_CH17 + @arg @ref MD_ADC_NCHS3_NS12_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_12th(ADC_TypeDef *ADCx, uint32_t ns12) +{ + MODIFY_REG(ADCx->NCHS3, ADC_NCHS3_NS12, ns12 << ADC_NCHS3_NS12_POSS); +} + +/** + * @brief Get 12th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS3_NS12_CH0 + @arg @ref MD_ADC_NCHS3_NS12_CH1 + @arg @ref MD_ADC_NCHS3_NS12_CH2 + @arg @ref MD_ADC_NCHS3_NS12_CH3 + @arg @ref MD_ADC_NCHS3_NS12_CH4 + @arg @ref MD_ADC_NCHS3_NS12_CH5 + @arg @ref MD_ADC_NCHS3_NS12_CH6 + @arg @ref MD_ADC_NCHS3_NS12_CH7 + @arg @ref MD_ADC_NCHS3_NS12_CH8 + @arg @ref MD_ADC_NCHS3_NS12_CH9 + @arg @ref MD_ADC_NCHS3_NS12_CH10 + @arg @ref MD_ADC_NCHS3_NS12_CH11 + @arg @ref MD_ADC_NCHS3_NS12_CH12 + @arg @ref MD_ADC_NCHS3_NS12_CH13 + @arg @ref MD_ADC_NCHS3_NS12_CH14 + @arg @ref MD_ADC_NCHS3_NS12_CH15 + @arg @ref MD_ADC_NCHS3_NS12_CH16 + @arg @ref MD_ADC_NCHS3_NS12_CH17 + @arg @ref MD_ADC_NCHS3_NS12_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_12th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS3, ADC_NCHS3_NS12)) >> ADC_NCHS3_NS12_POSS); +} + +/** + * @brief Set 11th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns11 + @arg @ref MD_ADC_NCHS3_NS11_CH0 + @arg @ref MD_ADC_NCHS3_NS11_CH1 + @arg @ref MD_ADC_NCHS3_NS11_CH2 + @arg @ref MD_ADC_NCHS3_NS11_CH3 + @arg @ref MD_ADC_NCHS3_NS11_CH4 + @arg @ref MD_ADC_NCHS3_NS11_CH5 + @arg @ref MD_ADC_NCHS3_NS11_CH6 + @arg @ref MD_ADC_NCHS3_NS11_CH7 + @arg @ref MD_ADC_NCHS3_NS11_CH8 + @arg @ref MD_ADC_NCHS3_NS11_CH9 + @arg @ref MD_ADC_NCHS3_NS11_CH10 + @arg @ref MD_ADC_NCHS3_NS11_CH11 + @arg @ref MD_ADC_NCHS3_NS11_CH12 + @arg @ref MD_ADC_NCHS3_NS11_CH13 + @arg @ref MD_ADC_NCHS3_NS11_CH14 + @arg @ref MD_ADC_NCHS3_NS11_CH15 + @arg @ref MD_ADC_NCHS3_NS11_CH16 + @arg @ref MD_ADC_NCHS3_NS11_CH17 + @arg @ref MD_ADC_NCHS3_NS11_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_11th(ADC_TypeDef *ADCx, uint32_t ns11) +{ + MODIFY_REG(ADCx->NCHS3, ADC_NCHS3_NS11, ns11 << ADC_NCHS3_NS11_POSS); +} + +/** + * @brief Get 11th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS3_NS11_CH0 + @arg @ref MD_ADC_NCHS3_NS11_CH1 + @arg @ref MD_ADC_NCHS3_NS11_CH2 + @arg @ref MD_ADC_NCHS3_NS11_CH3 + @arg @ref MD_ADC_NCHS3_NS11_CH4 + @arg @ref MD_ADC_NCHS3_NS11_CH5 + @arg @ref MD_ADC_NCHS3_NS11_CH6 + @arg @ref MD_ADC_NCHS3_NS11_CH7 + @arg @ref MD_ADC_NCHS3_NS11_CH8 + @arg @ref MD_ADC_NCHS3_NS11_CH9 + @arg @ref MD_ADC_NCHS3_NS11_CH10 + @arg @ref MD_ADC_NCHS3_NS11_CH11 + @arg @ref MD_ADC_NCHS3_NS11_CH12 + @arg @ref MD_ADC_NCHS3_NS11_CH13 + @arg @ref MD_ADC_NCHS3_NS11_CH14 + @arg @ref MD_ADC_NCHS3_NS11_CH15 + @arg @ref MD_ADC_NCHS3_NS11_CH16 + @arg @ref MD_ADC_NCHS3_NS11_CH17 + @arg @ref MD_ADC_NCHS3_NS11_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_11th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS3, ADC_NCHS3_NS11)) >> ADC_NCHS3_NS11_POSS); +} + +/** + * @brief Set 10th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns10 + @arg @ref MD_ADC_NCHS3_NS10_CH0 + @arg @ref MD_ADC_NCHS3_NS10_CH1 + @arg @ref MD_ADC_NCHS3_NS10_CH2 + @arg @ref MD_ADC_NCHS3_NS10_CH3 + @arg @ref MD_ADC_NCHS3_NS10_CH4 + @arg @ref MD_ADC_NCHS3_NS10_CH5 + @arg @ref MD_ADC_NCHS3_NS10_CH6 + @arg @ref MD_ADC_NCHS3_NS10_CH7 + @arg @ref MD_ADC_NCHS3_NS10_CH8 + @arg @ref MD_ADC_NCHS3_NS10_CH9 + @arg @ref MD_ADC_NCHS3_NS10_CH10 + @arg @ref MD_ADC_NCHS3_NS10_CH11 + @arg @ref MD_ADC_NCHS3_NS10_CH12 + @arg @ref MD_ADC_NCHS3_NS10_CH13 + @arg @ref MD_ADC_NCHS3_NS10_CH14 + @arg @ref MD_ADC_NCHS3_NS10_CH15 + @arg @ref MD_ADC_NCHS3_NS10_CH16 + @arg @ref MD_ADC_NCHS3_NS10_CH17 + @arg @ref MD_ADC_NCHS3_NS10_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_10th(ADC_TypeDef *ADCx, uint32_t ns10) +{ + MODIFY_REG(ADCx->NCHS3, ADC_NCHS3_NS10, ns10 << ADC_NCHS3_NS10_POSS); +} + +/** + * @brief Get 10th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS3_NS10_CH0 + @arg @ref MD_ADC_NCHS3_NS10_CH1 + @arg @ref MD_ADC_NCHS3_NS10_CH2 + @arg @ref MD_ADC_NCHS3_NS10_CH3 + @arg @ref MD_ADC_NCHS3_NS10_CH4 + @arg @ref MD_ADC_NCHS3_NS10_CH5 + @arg @ref MD_ADC_NCHS3_NS10_CH6 + @arg @ref MD_ADC_NCHS3_NS10_CH7 + @arg @ref MD_ADC_NCHS3_NS10_CH8 + @arg @ref MD_ADC_NCHS3_NS10_CH9 + @arg @ref MD_ADC_NCHS3_NS10_CH10 + @arg @ref MD_ADC_NCHS3_NS10_CH11 + @arg @ref MD_ADC_NCHS3_NS10_CH12 + @arg @ref MD_ADC_NCHS3_NS10_CH13 + @arg @ref MD_ADC_NCHS3_NS10_CH14 + @arg @ref MD_ADC_NCHS3_NS10_CH15 + @arg @ref MD_ADC_NCHS3_NS10_CH16 + @arg @ref MD_ADC_NCHS3_NS10_CH17 + @arg @ref MD_ADC_NCHS3_NS10_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_10th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS3, ADC_NCHS3_NS10)) >> ADC_NCHS3_NS10_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group19 NCHS4 + * @{ + */ +/** + * @brief Set ADC_NCHS4 Register + * @param ADCx ADC Instance + * @param nchs4 + * @retval None + */ +__STATIC_INLINE void md_adc_set_nchs4(ADC_TypeDef *ADCx, uint32_t nchs4) +{ + WRITE_REG(ADCx->NCHS4, nchs4); +} + +/** + * @brief Get ADC_NCHS4 Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_nchs4(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->NCHS4)); +} + +/** + * @brief Set 16th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns15 + @arg @ref MD_ADC_NCHS4_NS16_CH0 + @arg @ref MD_ADC_NCHS4_NS16_CH1 + @arg @ref MD_ADC_NCHS4_NS16_CH2 + @arg @ref MD_ADC_NCHS4_NS16_CH3 + @arg @ref MD_ADC_NCHS4_NS16_CH4 + @arg @ref MD_ADC_NCHS4_NS16_CH5 + @arg @ref MD_ADC_NCHS4_NS16_CH6 + @arg @ref MD_ADC_NCHS4_NS16_CH7 + @arg @ref MD_ADC_NCHS4_NS16_CH8 + @arg @ref MD_ADC_NCHS4_NS16_CH9 + @arg @ref MD_ADC_NCHS4_NS16_CH10 + @arg @ref MD_ADC_NCHS4_NS16_CH11 + @arg @ref MD_ADC_NCHS4_NS16_CH12 + @arg @ref MD_ADC_NCHS4_NS16_CH13 + @arg @ref MD_ADC_NCHS4_NS16_CH14 + @arg @ref MD_ADC_NCHS4_NS16_CH15 + @arg @ref MD_ADC_NCHS4_NS16_CH16 + @arg @ref MD_ADC_NCHS4_NS16_CH17 + @arg @ref MD_ADC_NCHS4_NS16_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_16th(ADC_TypeDef *ADCx, uint32_t ns16) +{ + MODIFY_REG(ADCx->NCHS4, ADC_NCHS4_NS16, ns16 << ADC_NCHS4_NS16_POSS); +} + +/** + * @brief Get 16th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS4_NS16_CH0 + @arg @ref MD_ADC_NCHS4_NS16_CH1 + @arg @ref MD_ADC_NCHS4_NS16_CH2 + @arg @ref MD_ADC_NCHS4_NS16_CH3 + @arg @ref MD_ADC_NCHS4_NS16_CH4 + @arg @ref MD_ADC_NCHS4_NS16_CH5 + @arg @ref MD_ADC_NCHS4_NS16_CH6 + @arg @ref MD_ADC_NCHS4_NS16_CH7 + @arg @ref MD_ADC_NCHS4_NS16_CH8 + @arg @ref MD_ADC_NCHS4_NS16_CH9 + @arg @ref MD_ADC_NCHS4_NS16_CH10 + @arg @ref MD_ADC_NCHS4_NS16_CH11 + @arg @ref MD_ADC_NCHS4_NS16_CH12 + @arg @ref MD_ADC_NCHS4_NS16_CH13 + @arg @ref MD_ADC_NCHS4_NS16_CH14 + @arg @ref MD_ADC_NCHS4_NS16_CH15 + @arg @ref MD_ADC_NCHS4_NS16_CH16 + @arg @ref MD_ADC_NCHS4_NS16_CH17 + @arg @ref MD_ADC_NCHS4_NS16_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_16th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS4, ADC_NCHS4_NS16)) >> ADC_NCHS4_NS16_POSS); +} + +/** + * @brief Set 15th conversion in regular sequence. + * @param ADCx ADC Instance + * @param ns15 + @arg @ref MD_ADC_NCHS4_NS15_CH0 + @arg @ref MD_ADC_NCHS4_NS15_CH1 + @arg @ref MD_ADC_NCHS4_NS15_CH2 + @arg @ref MD_ADC_NCHS4_NS15_CH3 + @arg @ref MD_ADC_NCHS4_NS15_CH4 + @arg @ref MD_ADC_NCHS4_NS15_CH5 + @arg @ref MD_ADC_NCHS4_NS15_CH6 + @arg @ref MD_ADC_NCHS4_NS15_CH7 + @arg @ref MD_ADC_NCHS4_NS15_CH8 + @arg @ref MD_ADC_NCHS4_NS15_CH9 + @arg @ref MD_ADC_NCHS4_NS15_CH10 + @arg @ref MD_ADC_NCHS4_NS15_CH11 + @arg @ref MD_ADC_NCHS4_NS15_CH12 + @arg @ref MD_ADC_NCHS4_NS15_CH13 + @arg @ref MD_ADC_NCHS4_NS15_CH14 + @arg @ref MD_ADC_NCHS4_NS15_CH15 + @arg @ref MD_ADC_NCHS4_NS15_CH16 + @arg @ref MD_ADC_NCHS4_NS15_CH17 + @arg @ref MD_ADC_NCHS4_NS15_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_sequence_selection_15th(ADC_TypeDef *ADCx, uint32_t ns15) +{ + MODIFY_REG(ADCx->NCHS4, ADC_NCHS4_NS15, ns15 << ADC_NCHS4_NS15_POSS); +} + +/** + * @brief Get 15th conversion in regular sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_NCHS4_NS15_CH0 + @arg @ref MD_ADC_NCHS4_NS15_CH1 + @arg @ref MD_ADC_NCHS4_NS15_CH2 + @arg @ref MD_ADC_NCHS4_NS15_CH3 + @arg @ref MD_ADC_NCHS4_NS15_CH4 + @arg @ref MD_ADC_NCHS4_NS15_CH5 + @arg @ref MD_ADC_NCHS4_NS15_CH6 + @arg @ref MD_ADC_NCHS4_NS15_CH7 + @arg @ref MD_ADC_NCHS4_NS15_CH8 + @arg @ref MD_ADC_NCHS4_NS15_CH9 + @arg @ref MD_ADC_NCHS4_NS15_CH10 + @arg @ref MD_ADC_NCHS4_NS15_CH11 + @arg @ref MD_ADC_NCHS4_NS15_CH12 + @arg @ref MD_ADC_NCHS4_NS15_CH13 + @arg @ref MD_ADC_NCHS4_NS15_CH14 + @arg @ref MD_ADC_NCHS4_NS15_CH15 + @arg @ref MD_ADC_NCHS4_NS15_CH16 + @arg @ref MD_ADC_NCHS4_NS15_CH17 + @arg @ref MD_ADC_NCHS4_NS15_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_normal_sequence_selection_15th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHS4, ADC_NCHS4_NS15)) >> ADC_NCHS4_NS15_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group20 NCHDR + * @{ + */ +/** + * @brief Get Regular data converted. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_normal_data(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->NCHDR, ADC_NCHDR_VAL))); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group21 ICHS + * @{ + */ +/** + * @brief Set ADC_ICHS Register + * @param ADCx ADC Instance + * @param ichs + * @retval None + */ +__STATIC_INLINE void md_adc_set_ichs(ADC_TypeDef *ADCx, uint32_t ichs) +{ + WRITE_REG(ADCx->ICHS, ichs); +} + +/** + * @brief Get ADC_ICHS Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_ichs(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->ICHS)); +} + +/** + * @brief Set 4th conversion in the injected sequence. + * @param ADCx ADC Instance + * @param is4 + @arg @ref MD_ADC_ICHS_IS4_CH0 + @arg @ref MD_ADC_ICHS_IS4_CH1 + @arg @ref MD_ADC_ICHS_IS4_CH2 + @arg @ref MD_ADC_ICHS_IS4_CH3 + @arg @ref MD_ADC_ICHS_IS4_CH4 + @arg @ref MD_ADC_ICHS_IS4_CH5 + @arg @ref MD_ADC_ICHS_IS4_CH6 + @arg @ref MD_ADC_ICHS_IS4_CH7 + @arg @ref MD_ADC_ICHS_IS4_CH8 + @arg @ref MD_ADC_ICHS_IS4_CH9 + @arg @ref MD_ADC_ICHS_IS4_CH10 + @arg @ref MD_ADC_ICHS_IS4_CH11 + @arg @ref MD_ADC_ICHS_IS4_CH12 + @arg @ref MD_ADC_ICHS_IS4_CH13 + @arg @ref MD_ADC_ICHS_IS4_CH14 + @arg @ref MD_ADC_ICHS_IS4_CH15 + @arg @ref MD_ADC_ICHS_IS4_CH16 + @arg @ref MD_ADC_ICHS_IS4_CH17 + @arg @ref MD_ADC_ICHS_IS4_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_inj_sequence_selection_4th(ADC_TypeDef *ADCx, uint32_t is4) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_IS4, is4 << ADC_ICHS_IS4_POSS); +} + +/** + * @brief Get 4th conversion in the injected sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_ICHS_IS4_CH0 + @arg @ref MD_ADC_ICHS_IS4_CH1 + @arg @ref MD_ADC_ICHS_IS4_CH2 + @arg @ref MD_ADC_ICHS_IS4_CH3 + @arg @ref MD_ADC_ICHS_IS4_CH4 + @arg @ref MD_ADC_ICHS_IS4_CH5 + @arg @ref MD_ADC_ICHS_IS4_CH6 + @arg @ref MD_ADC_ICHS_IS4_CH7 + @arg @ref MD_ADC_ICHS_IS4_CH8 + @arg @ref MD_ADC_ICHS_IS4_CH9 + @arg @ref MD_ADC_ICHS_IS4_CH10 + @arg @ref MD_ADC_ICHS_IS4_CH11 + @arg @ref MD_ADC_ICHS_IS4_CH12 + @arg @ref MD_ADC_ICHS_IS4_CH13 + @arg @ref MD_ADC_ICHS_IS4_CH14 + @arg @ref MD_ADC_ICHS_IS4_CH15 + @arg @ref MD_ADC_ICHS_IS4_CH16 + @arg @ref MD_ADC_ICHS_IS4_CH17 + @arg @ref MD_ADC_ICHS_IS4_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_inj_sequence_selection_4th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->ICHS, ADC_ICHS_IS4)) >> ADC_ICHS_IS4_POSS); +} + +/** + * @brief Set 3th conversion in the injected sequence. + * @param ADCx ADC Instance + * @param is3 + @arg @ref MD_ADC_ICHS_IS3_CH0 + @arg @ref MD_ADC_ICHS_IS3_CH1 + @arg @ref MD_ADC_ICHS_IS3_CH2 + @arg @ref MD_ADC_ICHS_IS3_CH3 + @arg @ref MD_ADC_ICHS_IS3_CH4 + @arg @ref MD_ADC_ICHS_IS3_CH5 + @arg @ref MD_ADC_ICHS_IS3_CH6 + @arg @ref MD_ADC_ICHS_IS3_CH7 + @arg @ref MD_ADC_ICHS_IS3_CH8 + @arg @ref MD_ADC_ICHS_IS3_CH9 + @arg @ref MD_ADC_ICHS_IS3_CH10 + @arg @ref MD_ADC_ICHS_IS3_CH11 + @arg @ref MD_ADC_ICHS_IS3_CH12 + @arg @ref MD_ADC_ICHS_IS3_CH13 + @arg @ref MD_ADC_ICHS_IS3_CH14 + @arg @ref MD_ADC_ICHS_IS3_CH15 + @arg @ref MD_ADC_ICHS_IS3_CH16 + @arg @ref MD_ADC_ICHS_IS3_CH17 + @arg @ref MD_ADC_ICHS_IS3_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_inj_sequence_selection_3th(ADC_TypeDef *ADCx, uint32_t is3) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_IS3, is3 << ADC_ICHS_IS3_POSS); +} + +/** + * @brief Get 3th conversion in the injected sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_ICHS_IS3_CH0 + @arg @ref MD_ADC_ICHS_IS3_CH1 + @arg @ref MD_ADC_ICHS_IS3_CH2 + @arg @ref MD_ADC_ICHS_IS3_CH3 + @arg @ref MD_ADC_ICHS_IS3_CH4 + @arg @ref MD_ADC_ICHS_IS3_CH5 + @arg @ref MD_ADC_ICHS_IS3_CH6 + @arg @ref MD_ADC_ICHS_IS3_CH7 + @arg @ref MD_ADC_ICHS_IS3_CH8 + @arg @ref MD_ADC_ICHS_IS3_CH9 + @arg @ref MD_ADC_ICHS_IS3_CH10 + @arg @ref MD_ADC_ICHS_IS3_CH11 + @arg @ref MD_ADC_ICHS_IS3_CH12 + @arg @ref MD_ADC_ICHS_IS3_CH13 + @arg @ref MD_ADC_ICHS_IS3_CH14 + @arg @ref MD_ADC_ICHS_IS3_CH15 + @arg @ref MD_ADC_ICHS_IS3_CH16 + @arg @ref MD_ADC_ICHS_IS3_CH17 + @arg @ref MD_ADC_ICHS_IS3_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_inj_sequence_selection_3th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->ICHS, ADC_ICHS_IS3)) >> ADC_ICHS_IS3_POSS); +} + +/** + * @brief Set 2th conversion in the injected sequence. + * @param ADCx ADC Instance + * @param is2 + @arg @ref MD_ADC_ICHS_IS2_CH0 + @arg @ref MD_ADC_ICHS_IS2_CH1 + @arg @ref MD_ADC_ICHS_IS2_CH2 + @arg @ref MD_ADC_ICHS_IS2_CH3 + @arg @ref MD_ADC_ICHS_IS2_CH4 + @arg @ref MD_ADC_ICHS_IS2_CH5 + @arg @ref MD_ADC_ICHS_IS2_CH6 + @arg @ref MD_ADC_ICHS_IS2_CH7 + @arg @ref MD_ADC_ICHS_IS2_CH8 + @arg @ref MD_ADC_ICHS_IS2_CH9 + @arg @ref MD_ADC_ICHS_IS2_CH10 + @arg @ref MD_ADC_ICHS_IS2_CH11 + @arg @ref MD_ADC_ICHS_IS2_CH12 + @arg @ref MD_ADC_ICHS_IS2_CH13 + @arg @ref MD_ADC_ICHS_IS2_CH14 + @arg @ref MD_ADC_ICHS_IS2_CH15 + @arg @ref MD_ADC_ICHS_IS2_CH16 + @arg @ref MD_ADC_ICHS_IS2_CH17 + @arg @ref MD_ADC_ICHS_IS2_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_inj_sequence_selection_2th(ADC_TypeDef *ADCx, uint32_t is2) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_IS2, is2 << ADC_ICHS_IS2_POSS); +} + +/** + * @brief Get 2th conversion in the injected sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_ICHS_IS2_CH0 + @arg @ref MD_ADC_ICHS_IS2_CH1 + @arg @ref MD_ADC_ICHS_IS2_CH2 + @arg @ref MD_ADC_ICHS_IS2_CH3 + @arg @ref MD_ADC_ICHS_IS2_CH4 + @arg @ref MD_ADC_ICHS_IS2_CH5 + @arg @ref MD_ADC_ICHS_IS2_CH6 + @arg @ref MD_ADC_ICHS_IS2_CH7 + @arg @ref MD_ADC_ICHS_IS2_CH8 + @arg @ref MD_ADC_ICHS_IS2_CH9 + @arg @ref MD_ADC_ICHS_IS2_CH10 + @arg @ref MD_ADC_ICHS_IS2_CH11 + @arg @ref MD_ADC_ICHS_IS2_CH12 + @arg @ref MD_ADC_ICHS_IS2_CH13 + @arg @ref MD_ADC_ICHS_IS2_CH14 + @arg @ref MD_ADC_ICHS_IS2_CH15 + @arg @ref MD_ADC_ICHS_IS2_CH16 + @arg @ref MD_ADC_ICHS_IS2_CH17 + @arg @ref MD_ADC_ICHS_IS2_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_inj_sequence_selection_2th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->ICHS, ADC_ICHS_IS2)) >> ADC_ICHS_IS2_POSS); +} + +/** + * @brief Set 1th conversion in the injected sequence. + * @param ADCx ADC Instance + * @param is1 + @arg @ref MD_ADC_ICHS_IS1_CH0 + @arg @ref MD_ADC_ICHS_IS1_CH1 + @arg @ref MD_ADC_ICHS_IS1_CH2 + @arg @ref MD_ADC_ICHS_IS1_CH3 + @arg @ref MD_ADC_ICHS_IS1_CH4 + @arg @ref MD_ADC_ICHS_IS1_CH5 + @arg @ref MD_ADC_ICHS_IS1_CH6 + @arg @ref MD_ADC_ICHS_IS1_CH7 + @arg @ref MD_ADC_ICHS_IS1_CH8 + @arg @ref MD_ADC_ICHS_IS1_CH9 + @arg @ref MD_ADC_ICHS_IS1_CH10 + @arg @ref MD_ADC_ICHS_IS1_CH11 + @arg @ref MD_ADC_ICHS_IS1_CH12 + @arg @ref MD_ADC_ICHS_IS1_CH13 + @arg @ref MD_ADC_ICHS_IS1_CH14 + @arg @ref MD_ADC_ICHS_IS1_CH15 + @arg @ref MD_ADC_ICHS_IS1_CH16 + @arg @ref MD_ADC_ICHS_IS1_CH17 + @arg @ref MD_ADC_ICHS_IS1_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_inj_sequence_selection_1th(ADC_TypeDef *ADCx, uint32_t is1) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_IS1, is1 << ADC_ICHS_IS1_POSS); +} + +/** + * @brief Get 1th conversion in the injected sequence. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_ICHS_IS1_CH0 + @arg @ref MD_ADC_ICHS_IS1_CH1 + @arg @ref MD_ADC_ICHS_IS1_CH2 + @arg @ref MD_ADC_ICHS_IS1_CH3 + @arg @ref MD_ADC_ICHS_IS1_CH4 + @arg @ref MD_ADC_ICHS_IS1_CH5 + @arg @ref MD_ADC_ICHS_IS1_CH6 + @arg @ref MD_ADC_ICHS_IS1_CH7 + @arg @ref MD_ADC_ICHS_IS1_CH8 + @arg @ref MD_ADC_ICHS_IS1_CH9 + @arg @ref MD_ADC_ICHS_IS1_CH10 + @arg @ref MD_ADC_ICHS_IS1_CH11 + @arg @ref MD_ADC_ICHS_IS1_CH12 + @arg @ref MD_ADC_ICHS_IS1_CH13 + @arg @ref MD_ADC_ICHS_IS1_CH14 + @arg @ref MD_ADC_ICHS_IS1_CH15 + @arg @ref MD_ADC_ICHS_IS1_CH16 + @arg @ref MD_ADC_ICHS_IS1_CH17 + @arg @ref MD_ADC_ICHS_IS1_CH18 + */ +__STATIC_INLINE uint32_t md_adc_get_inj_sequence_selection_1th(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->ICHS, ADC_ICHS_IS1)) >> ADC_ICHS_IS1_POSS); +} + +/** + * @brief Set External Trigger Enable and Polarity Selection for injected channels. + * @param ADCx ADC Instance + * @param iets + @arg @ref MD_ADC_ICHS_IETS_DISABLE + @arg @ref MD_ADC_ICHS_IETS_RISING + @arg @ref MD_ADC_ICHS_IETS_FALLING + @arg @ref MD_ADC_ICHS_IETS_BOTH + * @retval None + */ +__STATIC_INLINE void md_adc_set_inj_external_trigger_mode(ADC_TypeDef *ADCx, uint32_t iets) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_IETS, iets << ADC_ICHS_IETS_POSS); +} + +/** + * @brief Get External Trigger Enable and Polarity Selection for injected channels. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_ICHS_IETS_DISABLE + @arg @ref MD_ADC_ICHS_IETS_RISING + @arg @ref MD_ADC_ICHS_IETS_FALLING + @arg @ref MD_ADC_ICHS_IETS_BOTH + */ +__STATIC_INLINE uint32_t md_adc_get_inj_external_trigger_mode(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->ICHS, ADC_ICHS_IETS)) >> ADC_ICHS_IETS_POSS); +} + +/** + * @brief Set External Trigger Selection for injected group. + * @param ADCx ADC Instance + * @param iextsel + @arg @ref MD_ADC_ICHS_IEXTSEL_AD16C4T1_CH4 + @arg @ref MD_ADC_ICHS_IEXTSEL_AD16C4T1_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_GP32C4T1_CH1 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP32C4T1_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T1_CH2 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T1_CH3 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T1_CH4 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T2_CH1 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T2_CH2 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T2_CH3 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T2_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T3_CH4 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T3_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C2T1_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C2T2_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_EXTI_TRG1 + * @retval None + */ +__STATIC_INLINE void md_adc_set_inj_external_trigger_source(ADC_TypeDef *ADCx, uint32_t iextsel) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_IEXTSEL, iextsel << ADC_ICHS_IEXTSEL_POSS); +} + +/** + * @brief Get External Trigger Selection for injected group. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_ICHS_IEXTSEL_AD16C4T1_CH4 + @arg @ref MD_ADC_ICHS_IEXTSEL_AD16C4T1_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_GP32C4T1_CH1 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP32C4T1_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T1_CH2 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T1_CH3 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T1_CH4 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T2_CH1 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T2_CH2 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T2_CH3 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T2_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T3_CH4 + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C4T3_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C2T1_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_GP16C2T2_TRGOUT + @arg @ref MD_ADC_ICHS_IEXTSEL_EXTI_TRG1 + */ +__STATIC_INLINE uint32_t md_adc_get_inj_external_trigger_source(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->ICHS, ADC_ICHS_IEXTSEL)) >> ADC_ICHS_IEXTSEL_POSS); +} + +/** + * @brief Set Injected channel sequence length. + * @param ADCx ADC Instance + * @param isl + @arg @ref MD_ADC_ICHS_ISL_1CON + @arg @ref MD_ADC_ICHS_ISL_2CON + @arg @ref MD_ADC_ICHS_ISL_3CON + @arg @ref MD_ADC_ICHS_ISL_4CON + * @retval None + */ +__STATIC_INLINE void md_adc_set_inj_sequence_length(ADC_TypeDef *ADCx, uint32_t isl) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_ISL, isl << ADC_ICHS_ISL_POSS); +} + +/** + * @brief Get Injected channel sequence length. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_ICHS_ISL_1CON + @arg @ref MD_ADC_ICHS_ISL_2CON + @arg @ref MD_ADC_ICHS_ISL_3CON + @arg @ref MD_ADC_ICHS_ISL_4CON + */ +__STATIC_INLINE uint32_t md_adc_get_inj_sequence_length(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->ICHS, ADC_ICHS_ISL)) >> ADC_ICHS_ISL_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group22 OFF1 + * @{ + */ +/** + * @brief Set ADC_OFF1 Register + * @param ADCx ADC Instance + * @param off1 + * @retval None + */ +__STATIC_INLINE void md_adc_set_off1(ADC_TypeDef *ADCx, uint32_t off1) +{ + WRITE_REG(ADCx->OFF1, off1); +} + +/** + * @brief Get ADC_OFF1 Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_off1(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->OFF1)); +} + +/** + * @brief Offset enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_offset_compensation_1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->OFF1, ADC_OFF1_OFFEN); +} + +/** + * @brief Offset Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_offset_compensation_1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->OFF1, ADC_OFF1_OFFEN); +} + +/** + * @brief Check if Offset is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_disableb_offset_compensation_1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->OFF1, ADC_OFF1_OFFEN) == (ADC_OFF1_OFFEN)); +} + +/** + * @brief Set Channel selection for the data offset. + * @param ADCx ADC Instance + * @param offch + @arg @ref MD_ADC_OFF1_OFFCH_CH0 + @arg @ref MD_ADC_OFF1_OFFCH_CH1 + @arg @ref MD_ADC_OFF1_OFFCH_CH2 + @arg @ref MD_ADC_OFF1_OFFCH_CH3 + @arg @ref MD_ADC_OFF1_OFFCH_CH4 + @arg @ref MD_ADC_OFF1_OFFCH_CH5 + @arg @ref MD_ADC_OFF1_OFFCH_CH6 + @arg @ref MD_ADC_OFF1_OFFCH_CH7 + @arg @ref MD_ADC_OFF1_OFFCH_CH8 + @arg @ref MD_ADC_OFF1_OFFCH_CH9 + @arg @ref MD_ADC_OFF1_OFFCH_CH10 + @arg @ref MD_ADC_OFF1_OFFCH_CH11 + @arg @ref MD_ADC_OFF1_OFFCH_CH12 + @arg @ref MD_ADC_OFF1_OFFCH_CH13 + @arg @ref MD_ADC_OFF1_OFFCH_CH14 + @arg @ref MD_ADC_OFF1_OFFCH_CH15 + @arg @ref MD_ADC_OFF1_OFFCH_CH16 + @arg @ref MD_ADC_OFF1_OFFCH_CH17 + @arg @ref MD_ADC_OFF1_OFFCH_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_enable_compensation_channel_selection_1(ADC_TypeDef *ADCx, uint32_t offch) +{ + MODIFY_REG(ADCx->OFF1, ADC_OFF1_OFFCH, offch << ADC_OFF1_OFFCH_POSS); +} + +/** + * @brief Get Channel selection for the data offset. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_OFF1_OFFCH_CH0 + @arg @ref MD_ADC_OFF1_OFFCH_CH1 + @arg @ref MD_ADC_OFF1_OFFCH_CH2 + @arg @ref MD_ADC_OFF1_OFFCH_CH3 + @arg @ref MD_ADC_OFF1_OFFCH_CH4 + @arg @ref MD_ADC_OFF1_OFFCH_CH5 + @arg @ref MD_ADC_OFF1_OFFCH_CH6 + @arg @ref MD_ADC_OFF1_OFFCH_CH7 + @arg @ref MD_ADC_OFF1_OFFCH_CH8 + @arg @ref MD_ADC_OFF1_OFFCH_CH9 + @arg @ref MD_ADC_OFF1_OFFCH_CH10 + @arg @ref MD_ADC_OFF1_OFFCH_CH11 + @arg @ref MD_ADC_OFF1_OFFCH_CH12 + @arg @ref MD_ADC_OFF1_OFFCH_CH13 + @arg @ref MD_ADC_OFF1_OFFCH_CH14 + @arg @ref MD_ADC_OFF1_OFFCH_CH15 + @arg @ref MD_ADC_OFF1_OFFCH_CH16 + @arg @ref MD_ADC_OFF1_OFFCH_CH17 + @arg @ref MD_ADC_OFF1_OFFCH_CH18 + */ +__STATIC_INLINE uint32_t md_adc_disable_compensation_channel_selection_1(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->OFF1, ADC_OFF1_OFFCH) >> ADC_OFF1_OFFCH_POSS); +} + +/** + * @brief Saturation enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_compensation_saturation_1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->OFF1, ADC_OFF1_SATEN); +} + +/** + * @brief Saturation Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_compensation_saturation_1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->OFF1, ADC_OFF1_SATEN); +} + +/** + * @brief Check if Saturation is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_disabled_compensation_saturation_1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->OFF1, ADC_OFF1_SATEN) == (ADC_OFF1_SATEN)); +} + +/** + * @brief Set Positive offset. + * @param ADCx ADC Instance + * @param offpen + @arg @ref MD_ADC_OFF1_OFFPEN_NEGATIVE + @arg @ref MD_ADC_OFF1_OFFPEN_POSITIVE + * @retval None + */ +__STATIC_INLINE void md_adc_set_compensation_polarity_1(ADC_TypeDef *ADCx, uint32_t offpen) +{ + MODIFY_REG(ADCx->OFF1, ADC_OFF1_OFFPEN, offpen << ADC_OFF1_OFFPEN_POS); +} + +/** + * @brief Get Positive offset. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_OFF1_OFFPEN_NEGATIVE + @arg @ref MD_ADC_OFF1_OFFPEN_POSITIVE + */ +__STATIC_INLINE uint32_t md_adc_get_compensation_polarity_1(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->OFF1, ADC_OFF1_OFFPEN)) >> ADC_OFF1_OFFPEN_POS); +} + +/** + * @brief Set Data offset y for the channel programmed into bits OFFCH[4:0]. + * @param ADCx ADC Instance + * @param off + * @retval None + */ +__STATIC_INLINE void md_adc_set_compensation_value_1(ADC_TypeDef *ADCx, uint32_t off) +{ + MODIFY_REG(ADCx->OFF1, ADC_OFF1_OFF, off << ADC_OFF1_OFF_POSS); +} + +/** + * @brief Get Data offset y for the channel programmed into bits OFFCH[4:0]. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_compensation_value_1(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->OFF1, ADC_OFF1_OFF)) >> ADC_OFF1_OFF_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group23 OFF2 + * @{ + */ +/** + * @brief Set ADC_OFF2 Register + * @param ADCx ADC Instance + * @param off2 + * @retval None + */ +__STATIC_INLINE void md_adc_set_off2(ADC_TypeDef *ADCx, uint32_t off2) +{ + WRITE_REG(ADCx->OFF2, off2); +} + +/** + * @brief Get ADC_OFF2 Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_off2(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->OFF2)); +} + +/** + * @brief Offset enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_offset_compensation_2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->OFF2, ADC_OFF2_OFFEN); +} + +/** + * @brief Offset Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_offset_compensation_2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->OFF2, ADC_OFF2_OFFEN); +} + +/** + * @brief Check if Offset is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_disableb_offset_compensation_2(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->OFF2, ADC_OFF2_OFFEN) == (ADC_OFF2_OFFEN)); +} + +/** + * @brief Set Channel selection for the data offset. + * @param ADCx ADC Instance + * @param offch + @arg @ref MD_ADC_OFF2_OFFCH_CH0 + @arg @ref MD_ADC_OFF2_OFFCH_CH1 + @arg @ref MD_ADC_OFF2_OFFCH_CH2 + @arg @ref MD_ADC_OFF2_OFFCH_CH3 + @arg @ref MD_ADC_OFF2_OFFCH_CH4 + @arg @ref MD_ADC_OFF2_OFFCH_CH5 + @arg @ref MD_ADC_OFF2_OFFCH_CH6 + @arg @ref MD_ADC_OFF2_OFFCH_CH7 + @arg @ref MD_ADC_OFF2_OFFCH_CH8 + @arg @ref MD_ADC_OFF2_OFFCH_CH9 + @arg @ref MD_ADC_OFF2_OFFCH_CH10 + @arg @ref MD_ADC_OFF2_OFFCH_CH11 + @arg @ref MD_ADC_OFF2_OFFCH_CH12 + @arg @ref MD_ADC_OFF2_OFFCH_CH13 + @arg @ref MD_ADC_OFF2_OFFCH_CH14 + @arg @ref MD_ADC_OFF2_OFFCH_CH15 + @arg @ref MD_ADC_OFF2_OFFCH_CH16 + @arg @ref MD_ADC_OFF2_OFFCH_CH17 + @arg @ref MD_ADC_OFF2_OFFCH_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_enable_compensation_channel_selection_2(ADC_TypeDef *ADCx, uint32_t offch) +{ + MODIFY_REG(ADCx->OFF2, ADC_OFF2_OFFCH, offch << ADC_OFF2_OFFCH_POSS); +} + +/** + * @brief Get Channel selection for the data offset. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_OFF2_OFFCH_CH0 + @arg @ref MD_ADC_OFF2_OFFCH_CH1 + @arg @ref MD_ADC_OFF2_OFFCH_CH2 + @arg @ref MD_ADC_OFF2_OFFCH_CH3 + @arg @ref MD_ADC_OFF2_OFFCH_CH4 + @arg @ref MD_ADC_OFF2_OFFCH_CH5 + @arg @ref MD_ADC_OFF2_OFFCH_CH6 + @arg @ref MD_ADC_OFF2_OFFCH_CH7 + @arg @ref MD_ADC_OFF2_OFFCH_CH8 + @arg @ref MD_ADC_OFF2_OFFCH_CH9 + @arg @ref MD_ADC_OFF2_OFFCH_CH10 + @arg @ref MD_ADC_OFF2_OFFCH_CH11 + @arg @ref MD_ADC_OFF2_OFFCH_CH12 + @arg @ref MD_ADC_OFF2_OFFCH_CH13 + @arg @ref MD_ADC_OFF2_OFFCH_CH14 + @arg @ref MD_ADC_OFF2_OFFCH_CH15 + @arg @ref MD_ADC_OFF2_OFFCH_CH16 + @arg @ref MD_ADC_OFF2_OFFCH_CH17 + @arg @ref MD_ADC_OFF2_OFFCH_CH18 + */ +__STATIC_INLINE uint32_t md_adc_disable_compensation_channel_selection_2(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->OFF2, ADC_OFF2_OFFCH) >> ADC_OFF2_OFFCH_POSS); +} + +/** + * @brief Saturation enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_compensation_saturation_2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->OFF2, ADC_OFF2_SATEN); +} + +/** + * @brief Saturation Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_compensation_saturation_2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->OFF2, ADC_OFF2_SATEN); +} + +/** + * @brief Check if Saturation is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_disabled_compensation_saturation_2(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->OFF2, ADC_OFF2_SATEN) == (ADC_OFF2_SATEN)); +} + +/** + * @brief Set Positive offset. + * @param ADCx ADC Instance + * @param offpen + @arg @ref MD_ADC_OFF2_OFFPEN_NEGATIVE + @arg @ref MD_ADC_OFF2_OFFPEN_POSITIVE + * @retval None + */ +__STATIC_INLINE void md_adc_set_compensation_polarity_2(ADC_TypeDef *ADCx, uint32_t offpen) +{ + MODIFY_REG(ADCx->OFF2, ADC_OFF2_OFFPEN, offpen << ADC_OFF2_OFFPEN_POS); +} + +/** + * @brief Get Positive offset. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_OFF2_OFFPEN_NEGATIVE + @arg @ref MD_ADC_OFF2_OFFPEN_POSITIVE + */ +__STATIC_INLINE uint32_t md_adc_get_compensation_polarity_2(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->OFF2, ADC_OFF2_OFFPEN)) >> ADC_OFF2_OFFPEN_POS); +} + +/** + * @brief Set Data offset y for the channel programmed into bits OFFCH[4:0]. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_compensation_value_2(ADC_TypeDef *ADCx, uint32_t off) +{ + MODIFY_REG(ADCx->OFF2, ADC_OFF2_OFF, off << ADC_OFF2_OFF_POSS); +} + +/** + * @brief Get Data offset y for the channel programmed into bits OFFCH[4:0]. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_compensation_value_2(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->OFF2, ADC_OFF2_OFF)) >> ADC_OFF2_OFF_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group24 OFF3 + * @{ + */ +/** + * @brief Set ADC_OFF3 Register + * @param ADCx ADC Instance + * @param off3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_off3(ADC_TypeDef *ADCx, uint32_t off3) +{ + WRITE_REG(ADCx->OFF3, off3); +} + +/** + * @brief Get ADC_OFF3 Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_off3(ADC_TypeDef *ADCx) +{ + return (uint32_t)READ_REG(ADCx->OFF3); +} + +/** + * @brief Offset enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_offset_compensation_3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->OFF3, ADC_OFF3_OFFEN); +} + +/** + * @brief Offset Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_offset_compensation_3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->OFF3, ADC_OFF3_OFFEN); +} + +/** + * @brief Check if Offset is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_disableb_offset_compensation_3(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->OFF3, ADC_OFF3_OFFEN) == (ADC_OFF3_OFFEN)); +} + +/** + * @brief Set Channel selection for the data offset. + * @param ADCx ADC Instance + * @param offch + @arg @ref MD_ADC_OFF3_OFFCH_CH0 + @arg @ref MD_ADC_OFF3_OFFCH_CH1 + @arg @ref MD_ADC_OFF3_OFFCH_CH2 + @arg @ref MD_ADC_OFF3_OFFCH_CH3 + @arg @ref MD_ADC_OFF3_OFFCH_CH4 + @arg @ref MD_ADC_OFF3_OFFCH_CH5 + @arg @ref MD_ADC_OFF3_OFFCH_CH6 + @arg @ref MD_ADC_OFF3_OFFCH_CH7 + @arg @ref MD_ADC_OFF3_OFFCH_CH8 + @arg @ref MD_ADC_OFF3_OFFCH_CH9 + @arg @ref MD_ADC_OFF3_OFFCH_CH10 + @arg @ref MD_ADC_OFF3_OFFCH_CH11 + @arg @ref MD_ADC_OFF3_OFFCH_CH12 + @arg @ref MD_ADC_OFF3_OFFCH_CH13 + @arg @ref MD_ADC_OFF3_OFFCH_CH14 + @arg @ref MD_ADC_OFF3_OFFCH_CH15 + @arg @ref MD_ADC_OFF3_OFFCH_CH16 + @arg @ref MD_ADC_OFF3_OFFCH_CH17 + @arg @ref MD_ADC_OFF3_OFFCH_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_enable_compensation_channel_selection_3(ADC_TypeDef *ADCx, uint32_t offch) +{ + MODIFY_REG(ADCx->OFF3, ADC_OFF3_OFFCH, offch << ADC_OFF3_OFFCH_POSS); +} + +/** + * @brief Get Channel selection for the data offset. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_OFF3_OFFCH_CH0 + @arg @ref MD_ADC_OFF3_OFFCH_CH1 + @arg @ref MD_ADC_OFF3_OFFCH_CH2 + @arg @ref MD_ADC_OFF3_OFFCH_CH3 + @arg @ref MD_ADC_OFF3_OFFCH_CH4 + @arg @ref MD_ADC_OFF3_OFFCH_CH5 + @arg @ref MD_ADC_OFF3_OFFCH_CH6 + @arg @ref MD_ADC_OFF3_OFFCH_CH7 + @arg @ref MD_ADC_OFF3_OFFCH_CH8 + @arg @ref MD_ADC_OFF3_OFFCH_CH9 + @arg @ref MD_ADC_OFF3_OFFCH_CH10 + @arg @ref MD_ADC_OFF3_OFFCH_CH11 + @arg @ref MD_ADC_OFF3_OFFCH_CH12 + @arg @ref MD_ADC_OFF3_OFFCH_CH13 + @arg @ref MD_ADC_OFF3_OFFCH_CH14 + @arg @ref MD_ADC_OFF3_OFFCH_CH15 + @arg @ref MD_ADC_OFF3_OFFCH_CH16 + @arg @ref MD_ADC_OFF3_OFFCH_CH17 + @arg @ref MD_ADC_OFF3_OFFCH_CH18 + */ +__STATIC_INLINE uint32_t md_adc_disable_compensation_channel_selection_3(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->OFF3, ADC_OFF3_OFFCH) >> ADC_OFF3_OFFCH_POSS); +} + +/** + * @brief Saturation enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_compensation_saturation_3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->OFF3, ADC_OFF3_SATEN); +} + +/** + * @brief Saturation Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_compensation_saturation_3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->OFF3, ADC_OFF3_SATEN); +} + +/** + * @brief Check if Saturation is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_disabled_compensation_saturation_3(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->OFF3, ADC_OFF3_SATEN) == (ADC_OFF3_SATEN)); +} + +/** + * @brief Set Positive offset. + * @param ADCx ADC Instance + * @param offpen + @arg @ref MD_ADC_OFF3_OFFPEN_NEGATIVE + @arg @ref MD_ADC_OFF3_OFFPEN_POSITIVE + * @retval None + */ +__STATIC_INLINE void md_adc_set_compensation_polarity_3(ADC_TypeDef *ADCx, uint32_t offpen) +{ + MODIFY_REG(ADCx->OFF3, ADC_OFF3_OFFPEN, offpen << ADC_OFF3_OFFPEN_POS); +} + +/** + * @brief Get Positive offset. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_OFF3_OFFPEN_NEGATIVE + @arg @ref MD_ADC_OFF3_OFFPEN_POSITIVE + */ +__STATIC_INLINE uint32_t md_adc_get_compensation_polarity_3(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->OFF3, ADC_OFF3_OFFPEN)) >> ADC_OFF3_OFFPEN_POS); +} + +/** + * @brief Set Data offset y for the channel programmed into bits OFFCH[4:0]. + * @param ADCx ADC Instance + * @param off + * @retval None + */ +__STATIC_INLINE void md_adc_set_compensation_value_3(ADC_TypeDef *ADCx, uint32_t off) +{ + MODIFY_REG(ADCx->OFF3, ADC_OFF3_OFF, off << ADC_OFF3_OFF_POSS); +} + +/** + * @brief Get Data offset y for the channel programmed into bits OFFCH[4:0]. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_compensation_value_3(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->OFF3, ADC_OFF3_OFF)) >> ADC_OFF3_OFF_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group25 OFF4 + * @{ + */ +/** + * @brief Set ADC_OFF4 Register + * @param ADCx ADC Instance + * @param off4 + * @retval None + */ +__STATIC_INLINE void md_adc_set_off4(ADC_TypeDef *ADCx, uint32_t off4) +{ + WRITE_REG(ADCx->OFF4, off4); +} + +/** + * @brief Get ADC_OFF4 Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_off4(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->OFF4)); +} + +/** + * @brief Offset enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_offset_compensation_4(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->OFF4, ADC_OFF4_OFFEN); +} + +/** + * @brief Offset Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_offset_compensation_4(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->OFF4, ADC_OFF4_OFFEN); +} + +/** + * @brief Check if Offset is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_disableb_offset_compensation_4(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->OFF4, ADC_OFF4_OFFEN) == (ADC_OFF4_OFFEN)); +} + +/** + * @brief Set Channel selection for the data offset. + * @param ADCx ADC Instance + * @param offch + @arg @ref MD_ADC_OFF4_OFFCH_CH0 + @arg @ref MD_ADC_OFF4_OFFCH_CH1 + @arg @ref MD_ADC_OFF4_OFFCH_CH2 + @arg @ref MD_ADC_OFF4_OFFCH_CH3 + @arg @ref MD_ADC_OFF4_OFFCH_CH4 + @arg @ref MD_ADC_OFF4_OFFCH_CH5 + @arg @ref MD_ADC_OFF4_OFFCH_CH6 + @arg @ref MD_ADC_OFF4_OFFCH_CH7 + @arg @ref MD_ADC_OFF4_OFFCH_CH8 + @arg @ref MD_ADC_OFF4_OFFCH_CH9 + @arg @ref MD_ADC_OFF4_OFFCH_CH10 + @arg @ref MD_ADC_OFF4_OFFCH_CH11 + @arg @ref MD_ADC_OFF4_OFFCH_CH12 + @arg @ref MD_ADC_OFF4_OFFCH_CH13 + @arg @ref MD_ADC_OFF4_OFFCH_CH14 + @arg @ref MD_ADC_OFF4_OFFCH_CH15 + @arg @ref MD_ADC_OFF4_OFFCH_CH16 + @arg @ref MD_ADC_OFF4_OFFCH_CH17 + @arg @ref MD_ADC_OFF4_OFFCH_CH18 + * @retval None + */ +__STATIC_INLINE void md_adc_enable_compensation_channel_selection_4(ADC_TypeDef *ADCx, uint32_t offch) +{ + MODIFY_REG(ADCx->OFF4, ADC_OFF4_OFFCH, offch << ADC_OFF4_OFFCH_POSS); +} + +/** + * @brief Get Channel selection for the data offset. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_OFF4_OFFCH_CH0 + @arg @ref MD_ADC_OFF4_OFFCH_CH1 + @arg @ref MD_ADC_OFF4_OFFCH_CH2 + @arg @ref MD_ADC_OFF4_OFFCH_CH3 + @arg @ref MD_ADC_OFF4_OFFCH_CH4 + @arg @ref MD_ADC_OFF4_OFFCH_CH5 + @arg @ref MD_ADC_OFF4_OFFCH_CH6 + @arg @ref MD_ADC_OFF4_OFFCH_CH7 + @arg @ref MD_ADC_OFF4_OFFCH_CH8 + @arg @ref MD_ADC_OFF4_OFFCH_CH9 + @arg @ref MD_ADC_OFF4_OFFCH_CH10 + @arg @ref MD_ADC_OFF4_OFFCH_CH11 + @arg @ref MD_ADC_OFF4_OFFCH_CH12 + @arg @ref MD_ADC_OFF4_OFFCH_CH13 + @arg @ref MD_ADC_OFF4_OFFCH_CH14 + @arg @ref MD_ADC_OFF4_OFFCH_CH15 + @arg @ref MD_ADC_OFF4_OFFCH_CH16 + @arg @ref MD_ADC_OFF4_OFFCH_CH17 + @arg @ref MD_ADC_OFF4_OFFCH_CH18 + */ +__STATIC_INLINE uint32_t md_adc_disable_compensation_channel_selection_4(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->OFF4, ADC_OFF4_OFFCH) >> ADC_OFF4_OFFCH_POSS); +} + +/** + * @brief Saturation enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_compensation_saturation_4(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->OFF4, ADC_OFF4_SATEN); +} + +/** + * @brief Saturation Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_compensation_saturation_4(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->OFF4, ADC_OFF4_SATEN); +} + +/** + * @brief Check if Saturation is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_disabled_compensation_saturation_4(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->OFF4, ADC_OFF4_SATEN) == (ADC_OFF4_SATEN)); +} + +/** + * @brief Set Positive offset. + * @param ADCx ADC Instance + * @param offpen + @arg @ref MD_ADC_OFF3_OFFPEN_NEGATIVE + @arg @ref MD_ADC_OFF3_OFFPEN_POSITIVE + * @retval None + */ +__STATIC_INLINE void md_adc_set_compensation_polarity_4(ADC_TypeDef *ADCx, uint32_t offpen) +{ + MODIFY_REG(ADCx->OFF4, ADC_OFF4_OFFPEN, offpen); +} + +/** + * @brief Get Positive offset. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_OFF3_OFFPEN_NEGATIVE + @arg @ref MD_ADC_OFF3_OFFPEN_POSITIVE + */ +__STATIC_INLINE uint32_t md_adc_get_compensation_polarity_4(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->OFF4, ADC_OFF4_OFFPEN))); +} + +/** + * @brief Set Data offset y for the channel programmed into bits OFFCH[4:0]. + * @param ADCx ADC Instance + * @param off + * @retval None + */ +__STATIC_INLINE void md_adc_set_compensation_value_4(ADC_TypeDef *ADCx, uint32_t off) +{ + MODIFY_REG(ADCx->OFF4, ADC_OFF4_OFF, off << ADC_OFF4_OFF_POSS); +} + +/** + * @brief Get Data offset y for the channel programmed into bits OFFCH[4:0]. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_compensation_value_4(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->OFF4, ADC_OFF4_OFF)) >> ADC_OFF4_OFF_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group26 ICHDR1 + * @{ + */ +/** + * @brief Get Injected data. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_inj_data_1(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->ICHDR1, ADC_ICHDR1_VAL)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group27 ICHDR2 + * @{ + */ +/** + * @brief Get Injected data. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_inj_data_2(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->ICHDR2, ADC_ICHDR2_VAL)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group28 ICHDR3 + * @{ + */ +/** + * @brief Get Injected data. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_inj_data_3(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->ICHDR3, ADC_ICHDR3_VAL)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group29 ICHDR4 + * @{ + */ +/** + * @brief Get Injected data. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_inj_data_4(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->ICHDR4, ADC_ICHDR4_VAL)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group30 CALCR + * @{ + */ +/** + * @brief Set ADC_CALCR Register + * @param ADCx ADC Instance + * @param calcr + * @retval None + */ +__STATIC_INLINE void md_adc_set_calcr(ADC_TypeDef *ADCx, uint32_t calcr) +{ + WRITE_REG(ADCx->CALCR, calcr); +} + +/** + * @brief Get ADC_CALCR Register + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_calcr(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADCx->CALCR)); +} + +/** + * @brief Set Offset Compensation Coefficient. + * @param ADCx ADC Instance + * @param ocomcoe + * @retval None + */ +__STATIC_INLINE void md_adc_set_offset_factor(ADC_TypeDef *ADCx, uint32_t ocomcoe) +{ + MODIFY_REG(ADCx->CALCR, ADC_CALCR_OCOMCOE, ocomcoe << ADC_CALCR_OCOMCOE_POSS); +} + +/** + * @brief Get Offset Compensation Coefficient. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_offset_factor(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CALCR, ADC_CALCR_OCOMCOE)) >> ADC_CALCR_OCOMCOE_POSS); +} + +/** + * @brief Set Gain Compensation Coefficient. + * @param ADCx ADC Instance + * @param gcomcoe + * @retval None + */ +__STATIC_INLINE void md_adc_set_gain_factor(ADC_TypeDef *ADCx, uint32_t gcomcoe) +{ + MODIFY_REG(ADCx->CALCR, ADC_CALCR_GCOMCOE, gcomcoe << ADC_CALCR_GCOMCOE_POSS); +} + +/** + * @brief Get Gain Compensation Coefficient. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_get_gain_factor(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CALCR, ADC_CALCR_GCOMCOE)) >> ADC_CALCR_GCOMCOE_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group31 CCR + * @{ + */ +/** + * @brief Set Internal reference voltage scaling output selection. + * @param ADCx ADC Instance + * @param refints + @arg @ref MD_ADC_CCR_REFINTS_4DIV16 + @arg @ref MD_ADC_CCR_REFINTS_8DIV16 + @arg @ref MD_ADC_CCR_REFINTS_12DIV16 + @arg @ref MD_ADC_CCR_REFINTS_16DIV16 + @arg @ref MD_ADC_CCR_REFINTS_1DIV16 + @arg @ref MD_ADC_CCR_REFINTS_15DIV16 + * @retval None + */ +__STATIC_INLINE void md_adc_set_vref_level(ADC_TypeDef *ADCx, uint32_t refints) +{ + MODIFY_REG(ADCx->CCR, ADC_CCR_REFINTS, refints << ADC_CCR_REFINTS_POSS); +} + +/** + * @brief Get Internal reference voltage scaling output selection. + * @param ADCx ADC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_ADC_CCR_REFINTS_4DIV16 + @arg @ref MD_ADC_CCR_REFINTS_8DIV16 + @arg @ref MD_ADC_CCR_REFINTS_12DIV16 + @arg @ref MD_ADC_CCR_REFINTS_16DIV16 + @arg @ref MD_ADC_CCR_REFINTS_1DIV16 + @arg @ref MD_ADC_CCR_REFINTS_15DIV16 + */ +__STATIC_INLINE uint32_t md_adc_get_vref_level(ADC_TypeDef *ADCx) +{ + return (uint32_t)((READ_BIT(ADCx->CCR, ADC_CCR_REFINTS)) >> ADC_CCR_REFINTS_POSS); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group32 SR + * @{ + */ +/** + * @brief Get Injected data. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_normal_status(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->SR, ADC_SR_NDRE)) == (ADC_SR_NDRE)); +} +/** + * @} + */ + +/** @defgroup MD_ADC_Public_Functions_Group1 Initialization + * @{ + */ +void md_adc_init(ADC_TypeDef *, md_adc_initial *); +void md_adc_sequence_conversion(ADC_TypeDef *, md_adc_initial *, uint32_t *); + +ErrorStatus md_adc_calibration(ADC_TypeDef *, md_adc_initial *); +void md_adc_get_calibration(ADC_TypeDef *, uint8_t *, uint16_t *); +uint16_t md_adc_get_data(ADC_TypeDef *); + +ErrorStatus md_adc_software_calibration(ADC_TypeDef *ADCx, md_adc_initial *); +ErrorStatus md_adc_optionbyte_calibration(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruct); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_aes.h b/os/common/ext/CMSIS/ES32/FS026/md/md_aes.h new file mode 100644 index 00000000000..06ac51260cc --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_aes.h @@ -0,0 +1,829 @@ +/********************************************************************************** + * + * @file md_aes.h + * @brief header file of md_aes.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 28 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_AES_H__ +#define __MD_AES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_AES AES + * @brief AES micro driver + * @{ + */ + +/** @defgroup MD_AES_Pubulic_Types AES Pubulic Types + * @{ + */ + +/** + * @brief MD_AES_INIT AES init structure + * @ + */ +typedef struct +{ + volatile uint8_t aes_ctrl_bl; + volatile uint8_t aes_ctrl_mode; + volatile uint32_t aes_key[4]; + volatile uint32_t aes_iv[4]; + volatile uint32_t aes_din[4]; + volatile uint32_t aes_dout[4]; +} md_aes_init_typedef; +/** + * @} + */ + +/** @defgroup MD_AES_Public_Macros AES Public Macros + * @{ + */ + +#define MD_AES_CON_READY_BUSY (0) /*!< This allow user to read AES Encryption/Decryption Ready Status. */ +#define MD_AES_CON_READY_READY (1) /*!< This allow user to read AES Encryption/Decryption Ready Status. */ + +#define MD_AES_CON_OT_DEPTH_0 (0) /*!< This allow user to read AES DIO data depth status (X=0). */ +#define MD_AES_CON_OT_DEPTH_1 (1) /*!< This allow user to read AES DIO data depth status (X=1). */ +#define MD_AES_CON_OT_DEPTH_2 (2) /*!< This allow user to read AES DIO data depth status (X=2). */ +#define MD_AES_CON_OT_DEPTH_3 (3) /*!< This allow user to read AES DIO data depth status (X=3). */ + +#define MD_AES_CON_IT_DEPTH_0 (0) /*!< This allow user to read AES DIO data depth status (X=0). */ +#define MD_AES_CON_IT_DEPTH_1 (1) /*!< This allow user to read AES DIO data depth status (X=1). */ +#define MD_AES_CON_IT_DEPTH_2 (2) /*!< This allow user to read AES DIO data depth status (X=2). */ +#define MD_AES_CON_IT_DEPTH_3 (3) /*!< This allow user to read AES DIO data depth status (X=3). */ + +#define MD_AES_CON_DMA_EN_INPUT_ENABLE ((1 << 0)) /*!< This allow user to set AES DMA Function Enable. 0:AES input DMA disable */ +#define MD_AES_CON_DMA_EN_INPUT_DISABLE ((0 << 0)) /*!< This allow user to set AES DMA Function Enable. 1:AES input DMA enable */ + +#define MD_AES_CON_DMA_EN_OUTPUT_ENABLE ((1 << 1)) /*!< This allow user to set AES DMA Function Enable. 0:AES output DMA disable */ +#define MD_AES_CON_DMA_EN_OUTPUT_DISABLE ((0 << 1)) /*!< This allow user to set AES DMA Function Enable. 1:AES outut DMA enable */ + +#define MD_AES_CON_BL_CBC (0) /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 000:CBC */ +#define MD_AES_CON_BL_CFB (1) /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 001:CFB */ +#define MD_AES_CON_BL_OFB (2) /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 010:OFB */ +#define MD_AES_CON_BL_CTR (3) /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 011:CTR */ +#define MD_AES_CON_BL_ECB (4) /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 100:ECB */ +#define MD_AES_CON_BL_GCM (5) /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 101:GCM */ + +#define MD_AES_CON_MODE_ENCRYPT (0) /*!< This allow user to set AES Mode Control. 0:Encryption Mode */ +#define MD_AES_CON_MODE_DECRYPT (1) /*!< This allow user to set AES Mode Control. 1:Decryption Mode */ + +#define MD_AES_CON_START 1 /*!< This allow user to set AES Start. AES function will start after this bit is set to 1. */ + +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions AES Public Functions + * @{ + */ + +/** @defgroup MD_AES_Public_Functions_Group2 CON + * @{ + */ + +/** + * @brief AES Control Register + * @param AES Instance + * @param value + * @retval None. + */ +__STATIC_INLINE void md_aes_set_control(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->CON, value); +} + +/** + * @brief AES Control Register + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_aes_get_control(AES_TypeDef *aes) +{ + return (uint32_t)(READ_REG(aes->CON)); +} + +/** + * @brief AES Encryption / Decryption Ready Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_READY_BUSY + * @arg @ref MD_AES_CON_READY_READY + */ +__STATIC_INLINE uint32_t md_aes_get_ready(AES_TypeDef *aes) +{ + return (uint32_t)(READ_BIT(aes->CON, AES_CON_READY) >> AES_CON_READY_POS); +} + +/** + * @brief AES DMA Output Status + * @param AES Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_aes_is_enabled_output_dma(AES_TypeDef *aes) +{ + return (READ_BIT(aes->CON, AES_CON_OT_DMA_ST) == (AES_CON_OT_DMA_ST)); +} + +/** + * @brief AES DMA Intput Status + * @param AES Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_aes_is_enabled_input_dma(AES_TypeDef *aes, uint32_t value) +{ + return (READ_BIT(aes->CON, AES_CON_IT_DMA_ST) == (AES_CON_IT_DMA_ST)); +} + +/** + * @brief AES DIO data depth status (X=0,1,2,3) + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_OT_DEPTH_0 + * @arg @ref MD_AES_CON_OT_DEPTH_1 + * @arg @ref MD_AES_CON_OT_DEPTH_2 + * @arg @ref MD_AES_CON_OT_DEPTH_3 + */ +__STATIC_INLINE uint32_t md_aes_get_output_data_depth(AES_TypeDef *aes) +{ + return (uint32_t)(READ_BIT(aes->CON, AES_CON_OT_DEPTH) >> AES_CON_OT_DEPTH_POSS); +} + +/** + * @brief AES DIO data depth status (X=0,1,2,3) + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_IT_DEPTH_0 + * @arg @ref MD_AES_CON_IT_DEPTH_1 + * @arg @ref MD_AES_CON_IT_DEPTH_2 + * @arg @ref MD_AES_CON_IT_DEPTH_3 + */ +__STATIC_INLINE uint32_t md_aes_get_input_data_depth(AES_TypeDef *aes) +{ + return (uint32_t)(READ_BIT(aes->CON, AES_CON_IT_DEPTH) >> AES_CON_IT_DEPTH_POSS); +} + +/** + * @brief AES Re-initial + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_trigger_initial(AES_TypeDef *aes) +{ + SET_BIT(aes->CON, AES_CON_RE_INIT); +} + +/** + * @brief AES DMA Function Enable + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE + * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE + * @retval None. + */ +__STATIC_INLINE void md_aes_set_dma_en(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_DMA_EN, value << AES_CON_DMA_EN_POSS); +} + +/** + * @brief AES DMA Function Enable + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE + * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE + */ +__STATIC_INLINE uint32_t md_aes_get_dma_en(AES_TypeDef *aes) +{ + return (uint32_t)(READ_BIT(aes->CON, AES_CON_DMA_EN) >> AES_CON_DMA_EN_POSS); +} + +/** + * @brief Block Cipher Encryption / Decryption Mode + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_BL_CBC + * @arg @ref MD_AES_CON_BL_CFB + * @arg @ref MD_AES_CON_BL_OFB + * @arg @ref MD_AES_CON_BL_CTR + * @arg @ref MD_AES_CON_BL_ECB + * @arg @ref MD_AES_CON_BL_GCM + * @retval None. + */ +__STATIC_INLINE void md_aes_set_block_mode(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_BL, value << AES_CON_BL_POSS); +} + +/** + * @brief Block Cipher Encryption / Decryption Mode + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_BL_CBC + * @arg @ref MD_AES_CON_BL_CFB + * @arg @ref MD_AES_CON_BL_OFB + * @arg @ref MD_AES_CON_BL_CTR + * @arg @ref MD_AES_CON_BL_ECB + * @arg @ref MD_AES_CON_BL_GCM + */ +__STATIC_INLINE uint32_t md_aes_get_block_mode(AES_TypeDef *aes) +{ + return (uint32_t)(READ_BIT(aes->CON, AES_CON_BL) >> AES_CON_BL_POSS); +} + +/** + * @brief AES Mode Control + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_MODE_ENCRYPT + * @arg @ref MD_AES_CON_MODE_DECRYPT + * @retval None. + */ +__STATIC_INLINE void md_aes_set_direction(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_MODE, value << AES_CON_MODE_POS); +} + +/** + * @brief AES Mode Control + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_MODE_ENCRYPT + * @arg @ref MD_AES_CON_MODE_DECRYPT + */ +__STATIC_INLINE uint32_t md_aes_get_direction(AES_TypeDef *aes) +{ + return (uint32_t)(READ_BIT(aes->CON, AES_CON_MODE) >> AES_CON_MODE_POS); +} + +/** + * @brief AES Start + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_trigger_start(AES_TypeDef *aes) +{ + SET_BIT(aes->CON, AES_CON_START); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group3 IER + * @{ + */ +/** + * @brief AES Interrupt Enable Register + * @param AES Instance + * @param value + * @retval None. + */ +__STATIC_INLINE void md_aes_set_ier(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IER, value); +} + +/** + * @brief AES Decryption Interrupt Enable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_enable_it_dec(AES_TypeDef *aes) +{ + SET_BIT(aes->IER, AES_IER_DEC); +} + +/** + * @brief AES Encryption Interrupt Enable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_enable_it_enc(AES_TypeDef *aes) +{ + SET_BIT(aes->IER, AES_IER_ENC); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group4 IDR + * @{ + */ +/** + * @brief AES Interrupt Disable Register + * @param AES Instance + * @param value + * @retval None. + */ +__STATIC_INLINE void md_aes_set_idr(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IDR, value); +} + +/** + * @brief AES Decryption Interrupt Disable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_disable_it_dec(AES_TypeDef *aes) +{ + SET_BIT(aes->IDR, AES_IDR_DEC); +} + +/** + * @brief AES Encryption Interrupt Disable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_disable_it_enc(AES_TypeDef *aes) +{ + SET_BIT(aes->IDR, AES_IDR_DEC); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group5 IVS + * @{ + */ +/** + * @brief AES Interrupt Valid Status Register + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_aes_get_ivs(AES_TypeDef *aes) +{ + return (uint32_t)(READ_REG(aes->IVS)); +} + +/** + * @brief AES Decryption Interrupt Valid Status + * @param AES Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE bool md_aes_is_enabled_it_dec(AES_TypeDef *aes) +{ + return (READ_BIT(aes->IVS, AES_IVS_DEC) == (AES_IVS_DEC)); +} + +/** + * @brief AES Encryption Interrupt Valid Status + * @param AES Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE bool md_aes_is_enabled_it_enc(AES_TypeDef *aes) +{ + return (READ_BIT(aes->IVS, AES_IVS_ENC) == (AES_IVS_ENC)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group6 RIF + * @{ + */ +/** + * @brief AES Raw Interrupt Flag Status + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_aes_get_rif(AES_TypeDef *aes) +{ + return (uint32_t)(READ_REG(aes->RIF)); +} + +/** + * @brief AES Encryption Raw Interrupt Flag Status + * @param AES Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE bool md_aes_is_active_it_dec(AES_TypeDef *aes) +{ + return (READ_BIT(aes->RIF, AES_RIF_DEC) == (AES_RIF_DEC)); +} + +/** + * @brief AES Encryption Raw Interrupt Flag Status + * @param AES Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE bool md_aes_is_active_it_enc(AES_TypeDef *aes) +{ + return (READ_BIT(aes->RIF, AES_RIF_ENC) == (AES_RIF_ENC)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group7 IFM + * @{ + */ +/** + * @brief AES Interrupt Flag Mask Status Register + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_aes_get_ifm(AES_TypeDef *aes) +{ + return (uint32_t)(READ_REG(aes->IFM)); +} + +/** + * @brief AES Interrupt Flag Mask Status Register + * @param AES Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE bool md_aes_is_masked_it_dec(AES_TypeDef *aes) +{ + return (READ_BIT(aes->IFM, AES_IFM_DEC) == (AES_IFM_DEC)); +} + +/** + * @brief AES Interrupt Flag Mask Status Register + * @param AES Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE bool md_aes_is_masked_it_enc(AES_TypeDef *aes) +{ + return (READ_BIT(aes->IFM, AES_IFM_ENC) == (AES_IFM_ENC)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group8 ICR + * @{ + */ +/** + * @brief AES Interrupt Clear Register + * @param AES Instance + * @param value + * @retval None. + */ +__STATIC_INLINE void md_aes_set_icr(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->ICR, value); +} + +/** + * @brief AES Decryption Interrupt Clear + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_clear_it_dec(AES_TypeDef *aes) +{ + SET_BIT(aes->ICR, AES_ICR_DEC); +} + +/** + * @brief AES Encryption Interrupt Clear + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_clear_it_enc(AES_TypeDef *aes) +{ + SET_BIT(aes->ICR, AES_ICR_ENC); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group9 DIO + * @{ + */ +/** + * @brief AES 128-bit Input / Ouput Data Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_data(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->DIO, value); +} + +/** + * @brief AES 128-bit Input / Ouput Data Register + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ + +__STATIC_INLINE uint32_t md_aes_get_data(AES_TypeDef *aes) +{ + return (uint32_t)(READ_REG(aes->DIO)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group10 KEY0 + * @{ + */ +/** + * @brief AES 128-bit Keyword Register 0 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key0(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY0, value); +} + +/** + * @brief AES 128-bit Keyword Register 0 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key0(AES_TypeDef *aes) +{ + return (uint32_t)(READ_REG(aes->KEY0)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group11 KEY1 + * @{ + */ +/** + * @brief AES 128-bit Keyword Register 1 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key1(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY1, value); +} + +/** + * @brief AES 128-bit Keyword Register 1 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key1(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY1)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group12 KEY2 + * @{ + */ +/** + * @brief AES 128-bit Keyword Register 2 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key2(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY2, value); +} + +/** + * @brief AES 128-bit Keyword Register 2 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key2(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY2)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group13 KEY3 + * @{ + */ +/** + * @brief AES 128-bit Keyword Register 3 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key3(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY3, value); +} + +/** + * @brief AES 128-bit Keyword Register 3 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key3(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY3)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group14 IV0 + * @{ + */ +/** + * @brief AES 128-bit Initial Vector Register 0 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_initial_vector0(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV0, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 0 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_initial_vector0(AES_TypeDef *aes) +{ + return (uint32_t)(READ_REG(aes->IV0)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group15 IV1 + * @{ + */ +/** + * @brief AES 128-bit Initial Vector Register 1 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_initial_vector1(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV1, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 1 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_initial_vector1(AES_TypeDef *aes) +{ + return (uint32_t)(READ_REG(aes->IV1)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group16 IV2 + * @{ + */ +/** + * @brief AES 128-bit Initial Vector Register 2 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_initial_vector2(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV2, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 2 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_initial_vector2(AES_TypeDef *aes) +{ + return (uint32_t)(READ_REG(aes->IV2)); +} +/** + * @} + */ + +/** @defgroup MD_AES_Public_Functions_Group17 IV3 + * @{ + */ +/** + * @brief AES 128-bit Initial Vector Register 3 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_initial_vector3(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV3, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 3 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_initial_vector3(AES_TypeDef *aes) +{ + return (uint32_t)(READ_REG(aes->IV3)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_calc.h b/os/common/ext/CMSIS/ES32/FS026/md/md_calc.h new file mode 100644 index 00000000000..5d13b9794c4 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_calc.h @@ -0,0 +1,364 @@ +/********************************************************************************** + * + * @file md_calc.h + * @brief header file of md_calc.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 24 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_CALC_H__ +#define __MD_CALC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_CALC CALC + * @brief CALC micro driver + * @{ + */ + +/** @defgroup MD_CALC_Public_Macros CALC Public Macros + * @{ + */ + +#define MD_CALC_TRM_DIVDR (0x00000000UL) +#define MD_CALC_TRM_DIVSR (0x00000001UL) + +#define MD_CALC_SIGN_USIGN (0x00000000UL) +#define MD_CALC_SIGN_SIGN (0x00000001UL) + +#define MD_CALC_DZ_NONZERO (0x00000000UL) +#define MD_CALC_DZ_ZERO (0x00000001UL) + +#define MD_CALC_BUSY_DONE (0x00000000UL) +#define MD_CALC_BUSY_ONGOING (0x00000001UL) + +/** + * @} + */ + +/** @defgroup MD_CALC_Public_Functions CALC Public Functions + * @{ + */ + +/** @defgroup MD_CALC_Public_Functions_Group2 DIVDR + * @{ + */ +/** + * @brief Set CALC_DIVDR Register + * @note This register is given the dividend of divider before calculation starting + * @param calc CALC Instance + * @param divdr + @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_calc_set_dividend(CALC_TypeDef *calc, uint32_t divdr) +{ + WRITE_REG(calc->DIVDR, divdr); +} + +/** + * @brief Get CALC_DIVDR Register + * @note This register is given the dividend of divider before calculation starting + * @param calc CALC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_calc_get_dividend(CALC_TypeDef *calc) +{ + return (uint32_t)(READ_REG(calc->DIVDR)); +} +/** + * @} + */ + +/** @defgroup MD_CALC_Public_Functions_Group3 DIVSR + * @{ + */ +/** + * @brief Set CALC_DIVSR Register + * @note This register is given the divisor of divider before calculation starts + * @param calc CALC Instance + * @param divsr + @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_calc_set_divisor(CALC_TypeDef *calc, uint32_t divsr) +{ + WRITE_REG(calc->DIVSR, divsr); +} + +/** + * @brief Get CALC_DIVSR Register + * @note This register is given the divisor of divider before calculation starts + * @param calc CALC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_calc_get_divisor(CALC_TypeDef *calc) +{ + return (uint32_t)(READ_REG(calc->DIVSR)); +} +/** + * @} + */ + +/** @defgroup MD_CALC_Public_Functions_Group4 DIVQR + * @{ + */ +/** + * @brief Get CALC_DIVQR Register + * @note This register holds the quotient result of divider after calculation complete + * @param calc CALC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_calc_get_quotient(CALC_TypeDef *calc) +{ + return (uint32_t)(READ_REG(calc->DIVQR)); +} +/** + * @} + */ + +/** @defgroup MD_CALC_Public_Functions_Group5 DIVRR + * @{ + */ +/** + * @brief Get CALC_DIVRR Register + * @note This register holds the remainder result of divider after calculation complete + * @param calc CALC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_calc_get_remainder(CALC_TypeDef *calc) +{ + return (uint32_t)(READ_REG(calc->DIVRR)); +} +/** + * @} + */ + +/** @defgroup MD_CALC_Public_Functions_Group6 DIVCON + * @{ + */ +/** + * @brief Set CALC_DIVCON Register + * @note Division Operation Control Register + * @param calc CALC Instance + * @param divcon + * @retval None + */ +__STATIC_INLINE void md_calc_set_control(CALC_TypeDef *calc, uint32_t divcon) +{ + WRITE_REG(calc->DIVCON, divcon); +} + +/** + * @brief Get CALC_DIVCON Register + * @note Division Operation Control Register + * @param calc CALC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_calc_get_control(CALC_TypeDef *calc) +{ + return (uint32_t)(READ_REG(calc->DIVCON)); +} + +/** + * @brief Set Division operation trigger mode selection + * @param calc CALC Instance + * @param trm trigger mode + @arg @ref MD_CALC_TRM_DIVDR + @arg @ref MD_CALC_TRM_DIVSR + * @retval None + */ +__STATIC_INLINE void md_calc_set_trigger_mode(CALC_TypeDef *calc, uint32_t trm) +{ + MODIFY_REG(calc->DIVCON, CALC_DIVCON_TRM, trm << CALC_DIVCON_TRM_POS); +} + +/** + * @brief Get Division operation trigger mode selection + * @param calc CALC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_CALC_TRM_DIVDR + @arg @ref MD_CALC_TRM_DIVSR + */ +__STATIC_INLINE uint32_t md_calc_get_trigger_mode(CALC_TypeDef *calc) +{ + return (uint32_t)(READ_BIT(calc->DIVCON, CALC_DIVCON_TRM) >> CALC_DIVCON_TRM_POS); +} + +/** + * @brief Set Division operation symbol selection + * @param calc CALC Instance + * @param sign Division operation + @arg @ref MD_CALC_SIGN_USIGN + @arg @ref MD_CALC_SIGN_SIGN + * @retval None + */ +__STATIC_INLINE void md_calc_set_operation_mode(CALC_TypeDef *calc, uint32_t sign) +{ + MODIFY_REG(calc->DIVCON, CALC_DIVCON_SIGN, sign << CALC_DIVCON_SIGN_POS); +} + +/** + * @brief Get Division operation symbol selection + * @param calc CALC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_CALC_SIGN_USIGN + @arg @ref MD_CALC_SIGN_SIGN + */ +__STATIC_INLINE uint32_t md_calc_get_operation_mode(CALC_TypeDef *calc) +{ + return (uint32_t)(READ_BIT(calc->DIVCON, CALC_DIVCON_SIGN) >> CALC_DIVCON_SIGN_POS); +} +/** + * @} + */ + +/** @defgroup MD_CALC_Public_Functions_Group7 RDCND + * @{ + */ +/** + * @brief Set CALC_RDCND Register + * @param calc CALC Instance + * @param rdcnd Number of square roots + * @retval None + */ +__STATIC_INLINE void md_calc_set_radicand(CALC_TypeDef *calc, uint32_t rdcnd) +{ + WRITE_REG(calc->RDCND, rdcnd); +} + +/** + * @brief Get CALC_RDCND Register + * @param calc CALC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_calc_get_radicand(CALC_TypeDef *calc) +{ + return (uint32_t)(READ_REG(calc->RDCND)); +} +/** + * @} + */ + +/** @defgroup MD_CALC_Public_Functions_Group8 SQRTRES + * @{ + */ +/** + * @brief Get CALC_SQRTRES RESULT + * @note Get Square root operation result value + * @param calc CALC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_calc_get_square_root(CALC_TypeDef *calc) +{ + return (uint32_t)(READ_REG(calc->SQRTRES)); +} +/** + * @} + */ + +/** @defgroup MD_CALC_Public_Functions_Group9 STAT + * @{ + */ +/** + * @brief Get CALC_STAT Register + * @note CALC operation status register + * @param calc CALC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_calc_get_status(CALC_TypeDef *calc) +{ + return (uint32_t)(READ_REG(calc->STAT)); +} + +/** + * @brief Get CALC_STAT DZ + * @note Divide by zero warning + * @param calc CALC Instance + * @retval The retval can be one of the following values: + * @arg MD_CALC_DZ_NONZERO + * @arg MD_CALC_DZ_NONZERO + */ +__STATIC_INLINE uint8_t md_calc_is_active_flag_divisor_zero(CALC_TypeDef *calc) +{ + return (READ_BIT(calc->STAT, CALC_STAT_DZ) == (CALC_STAT_DZ)); +} + +/** + * @brief Get CALC_STAT BUSY + * @note Operation status bit + * @param calc CALC Instance + * @retval The retval can be one of the following values: + * @arg MD_CALC_BUSY_DONE + * @arg MD_CALC_BUSY_ONGOING + */ +__STATIC_INLINE uint8_t md_calc_is_active_flag_busy(CALC_TypeDef *calc) +{ + return (READ_BIT(calc->STAT, CALC_STAT_BUSY) == (CALC_STAT_BUSY)); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_cmp.h b/os/common/ext/CMSIS/ES32/FS026/md/md_cmp.h new file mode 100644 index 00000000000..a37f7f7d9ca --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_cmp.h @@ -0,0 +1,765 @@ +/********************************************************************************** + * + * @file md_cmp.h + * @brief header file of md_cmp.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 24 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_CMP_H__ +#define __MD_CMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_CMP CMP + * @brief CMP micro driver + * @{ + */ + + +/** @defgroup MD_CMP_Public_Macros CMP Public Macros + * @{ + */ +#define MD_CMP_CFG1_LOCK_READ_WRITE (0x00000000UL) /*!< @brief CMP_CFG1[31:0] bits can be read and written normally */ +#define MD_CMP_CFG1_LOCK_ONLY_READ (0x00000001UL) /*!< @brief The CMP_CFG1[31:0] bits are for read operations only. */ + +#define MD_CMP_CFG1_VALUE_OUTPUT_LOW_LEVEL (0x00000000UL) /*!< @brief CMP output is low level. */ +#define MD_CMP_CFG1_VALUE_OUTPUT_HIGH_LEVEL (0x00000001UL) /*!< @brief CMP output is high level. */ + +#define MD_CMP_CFG1_BLANKSEL_CLOSE (0x00000000UL) /*!< @brief 00000:Close */ +#define MD_CMP_CFG1_BLANKSEL_AD16C4T1_OC4 (0x00000001UL) /*!< @brief xxxx1:AD16C4T1_OC4 */ +#define MD_CMP_CFG1_BLANKSEL_GP32C4T1_OC4 (0x00000002UL) /*!< @brief xxx1x:GP32C4T1_OC4 */ +#define MD_CMP_CFG1_BLANKSEL_GP16C4T1_OC4 (0x00000004UL) /*!< @brief xx1xx:GP16C4T1_OC4 */ +#define MD_CMP_CFG1_BLANKSEL_GP16C4T2_OC4 (0x00000008UL) /*!< @brief x1xxx:GP16C4T2_OC4 */ +#define MD_CMP_CFG1_BLANKSEL_GP16C2T1_OC2 (0x00000010UL) /*!< @brief 1xxxx:GP16C2T1_OC2 */ + +#define MD_CMP_CFG1_POLARITY_NO_INVERTED (0x00000000UL) /*!< @brief The output is not inverted.*/ +#define MD_CMP_CFG1_POLARITY_INVERTED (0x00000001UL) /*!< @brief The output is inverted. */ + +#define MD_CMP_CFG1_OUTSEL_NO (0x00000000UL) /*!< @brief 000:NO */ +#define MD_CMP_CFG1_OUTSEL_AD16C4T1_BKIN (0x00000001UL) /*!< @brief 001:AD16C4T1_BKIN */ +#define MD_CMP_CFG1_OUTSEL_GP16C2T1_BKIN (0x00000002UL) /*!< @brief 010:GP16C4T1_BKIN */ +#define MD_CMP_CFG1_OUTSEL_GP16C2T2_BKIN (0x00000003UL) /*!< @brief 011:GP16C4T2_BKIN */ +#define MD_CMP_CFG1_OUTSEL_GP16C2T3_BKIN (0x00000004UL) /*!< @brief 100:GP16C4T3_BKIN */ +#define MD_CMP_CFG1_OUTSEL_GP16C2T4_BKIN (0x00000005UL) /*!< @brief 101:GP16C4T4_BKIN */ + +#define MD_CMP_CFG1_INNSEL_1DIV4_Vres (0x00000000UL) /*!< @brief 000:1/4 Vres */ +#define MD_CMP_CFG1_INNSEL_1DIV2_Vres (0x00000001UL) /*!< @brief 001:1/2 Vres */ +#define MD_CMP_CFG1_INNSEL_3DIV4_Vres (0x00000002UL) /*!< @brief 010:3/4 Vres */ +#define MD_CMP_CFG1_INNSEL_Vres (0x00000003UL) /*!< @brief 011:Vres_src */ +#define MD_CMP_CFG1_INNSEL_PA04 (0x00000004UL) /*!< @brief 100:PA04 */ +#define MD_CMP_CFG1_INNSEL_PA05 (0x00000005UL) /*!< @brief 101:PA05 */ +#define MD_CMP_CFG1_INNSEL_PA00 (0x00000006UL) /*!< @brief 110:PA00 */ + +#define MD_CMP_CFG2_LOCK_READ_WRITE (0x00000000UL) /*!< @brief CMP_CFG2[31:0] bits can be read and written normally */ +#define MD_CMP_CFG2_LOCK_ONLY_READ (0x00000001UL) /*!< @brief The CMP_CFG2[31:0] bits are for read operations only. */ + +#define MD_CMP_CFG2_VALUE_OUTPUT_LOW_LEVEL (0x00000000UL) /*!< @brief CMP output is low level. */ +#define MD_CMP_CFG2_VALUE_OUTPUT_HIGH_LEVEL (0x00000001UL) /*!< @brief CMP output is high level. */ + +#define MD_CMP_CFG2_BLANKSEL_CLOSE (0x00000000UL) /*!< @brief 00000:Close */ +#define MD_CMP_CFG2_BLANKSEL_AD16C4T1_OC4 (0x00000001UL) /*!< @brief xxxx1:AD16C4T1_OC4 */ +#define MD_CMP_CFG2_BLANKSEL_GP32C4T1_OC4 (0x00000002UL) /*!< @brief xxx1x:GP32C4T1_OC4 */ +#define MD_CMP_CFG2_BLANKSEL_GP16C4T1_OC4 (0x00000004UL) /*!< @brief xx1xx:GP16C4T1_OC4 */ +#define MD_CMP_CFG2_BLANKSEL_GP16C4T2_OC4 (0x00000008UL) /*!< @brief x1xxx:GP16C4T2_OC4 */ +#define MD_CMP_CFG2_BLANKSEL_GP16C2T1_OC2 (0x00000010UL) /*!< @brief 1xxxx:GP16C2T1_OC2 */ + +#define MD_CMP_CFG2_POLARITY_NO_INVERTED (0x00000000UL) /*!< @brief The output is not inverted.*/ +#define MD_CMP_CFG2_POLARITY_INVERTED (0x00000001UL) /*!< @brief The output is inverted. */ + +#define MD_CMP_CFG2_OUTSEL_NO (0x00000000UL) /*!< @brief 000:NO */ +#define MD_CMP_CFG2_OUTSEL_AD16C4T1_BKIN (0x00000001UL) /*!< @brief 001:AD16C4T1_BKIN */ +#define MD_CMP_CFG2_OUTSEL_GP16C2T1_BKIN (0x00000002UL) /*!< @brief 010:GP16C4T1_BKIN */ +#define MD_CMP_CFG2_OUTSEL_GP16C2T2_BKIN (0x00000003UL) /*!< @brief 011:GP16C4T2_BKIN */ +#define MD_CMP_CFG2_OUTSEL_GP16C2T3_BKIN (0x00000004UL) /*!< @brief 100:GP16C4T3_BKIN */ +#define MD_CMP_CFG2_OUTSEL_GP16C2T4_BKIN (0x00000005UL) /*!< @brief 101:GP16C4T4_BKIN */ + +#define MD_CMP_CFG2_INNSEL_1DIV4_Vres (0x00000000UL) /*!< @brief 000:1/4 Vres */ +#define MD_CMP_CFG2_INNSEL_1DIV2_Vres (0x00000001UL) /*!< @brief 001:1/2 Vres */ +#define MD_CMP_CFG2_INNSEL_3DIV4_Vres (0x00000002UL) /*!< @brief 010:3/4 Vres */ +#define MD_CMP_CFG2_INNSEL_Vres (0x00000003UL) /*!< @brief 011:Vres_src */ +#define MD_CMP_CFG2_INNSEL_PA04 (0x00000004UL) /*!< @brief 100:PA04 */ +#define MD_CMP_CFG2_INNSEL_PA05 (0x00000005UL) /*!< @brief 101:PA05 */ +#define MD_CMP_CFG2_INNSEL_PA02 (0x00000006UL) /*!< @brief 110:PA02 */ + +/** + * @} + */ + +/** @defgroup MD_CMP_Public_Functions CMP Public Functions + * @{ + */ + +/** @defgroup MD_CMP_Public_Functions_Group2 CFG1 + * @{ + */ +/** + * @brief Set CMP control register (CMP_CFG1) + * @param cmp CMP Instance + * @param value The value write in CMP_CFG1 + * @retval None + */ +__STATIC_INLINE void md_cmp_set_cfg1(CMP_TypeDef *cmp, uint32_t value) +{ + WRITE_REG(cmp->CFG1, value); +} + +/** + * @brief Get CMP control register (CMP_CFG1) + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_get_cfg1(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_REG(cmp->CFG1)); +} + +/** + * @brief Comparator 1 locked W/R + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp1_enable_lock(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_LOCK); +} + +/** + * @brief Get Comparator 1 locked + * @param cmp CMP Instance + * @retval The retval can be a value of the value: + @arg @ref MD_CMP_CFG1_LOCK_READ_WRITE + @arg @ref MD_CMP_CFG1_LOCK_ONLY_READ + */ +__STATIC_INLINE uint32_t md_cmp1_is_enabled_lock(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_LOCK) == (CMP_CFG1_LOCK)); +} + +/** + * @brief Get Comparator 1 output + * @param cmp CMP Instance + * @retval The retval can be a value of the value: + @arg @ref MD_CMP_CFG1_VALUE_OUTPUT_LOW_LEVEL + @arg @ref MD_CMP_CFG1_VALUE_OUTPUT_HIGH_LEVEL + */ +__STATIC_INLINE uint32_t md_cmp1_get_output_level(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->CFG1, CMP_CFG1_VALUE) >> CMP_CFG1_VALUE_POS); +} + +/** + * @brief Set Comparator 1 masking function + * @param cmp CMP Instance + * @param blanksel This parameter can be one of the following values: + * @arg MD_CMP_CFG1_BLANKSEL_CLOSE + * @arg MD_CMP_CFG1_BLANKSEL_AD16C4T1_OC4 + * @arg MD_CMP_CFG1_BLANKSEL_GP32C4T1_OC4 + * @arg MD_CMP_CFG1_BLANKSEL_GP16C4T1_OC4 + * @arg MD_CMP_CFG1_BLANKSEL_GP16C4T2_OC4 + * @arg MD_CMP_CFG1_BLANKSEL_GP16C2T1_OC2 + * @retval None + */ +__STATIC_INLINE void md_cmp1_set_blanking_source(CMP_TypeDef *cmp, uint32_t blanksel) +{ + MODIFY_REG(cmp->CFG1, CMP_CFG1_BLANKSEL, blanksel << CMP_CFG1_BLANKSEL_POSS); +} + +/** + * @brief Return Comparator 1 masking function + * @param cmp CMP Instance + * @retval The retval can be a value of the value: + * @arg MD_CMP_CFG1_BLANKSEL_CLOSE + * @arg MD_CMP_CFG1_BLANKSEL_AD16C4T1_OC4 + * @arg MD_CMP_CFG1_BLANKSEL_GP32C4T1_OC4 + * @arg MD_CMP_CFG1_BLANKSEL_GP16C4T1_OC4 + * @arg MD_CMP_CFG1_BLANKSEL_GP16C4T2_OC4 + * @arg MD_CMP_CFG1_BLANKSEL_GP16C2T1_OC2 + */ +__STATIC_INLINE uint32_t md_cmp1_get_blanking_source(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->CFG1, CMP_CFG1_BLANKSEL) >> CMP_CFG1_BLANKSEL_POSS); +} + +/** + * @brief Enable Comparator 1 filter function + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp1_enable_filter(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_FILT); +} +/** + * @brief Disable Comparator 1 filter function + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp1_disable_filter(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_FILT); +} + +/** + * @brief Check if Comparator 1 filter function select is enable + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp1_is_enabled_filter(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_FILT) == (CMP_CFG1_FILT)); +} + +/** + * @brief Enable Comparator 1 hysteresis function + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp1_enable_hysteresis(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_HYST); +} +/** + * @brief Disable Comparator 1 hysteresis function + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp1_disable_hysteresis(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_HYST); +} + +/** + * @brief Check if Comparator 1 hysteresis function + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp1_is_enabled_hysteresis(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_HYST) == (CMP_CFG1_HYST)); +} + +/** + * @brief Enable Comparator 1 output polarity + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp1_enable_polarity(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_POLARITY); +} + +/** + * @brief Disable Comparator 1 output polarity + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp1_disable_polarity(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_POLARITY); +} + +/** + * @brief Check if Comparator 1 output polarity + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp1_is_enabled_polarity(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_POLARITY) == (CMP_CFG1_POLARITY)); +} + +/** + * @brief Set Comparator 1 output trigger selection + * @param cmp CMP Instance + * @param outsel + * @param outsel This parameter can be one of the following values: + * @arg MD_CMP_OUTSEL_NO + * @arg MD_CMP_CFG1_OUTSEL_AD16C4T1_BKIN + * @arg MD_CMP_CFG1_OUTSEL_GP16C4T1_BKIN + * @arg MD_CMP_CFG1_OUTSEL_GP16C4T2_BKIN + * @arg MD_CMP_CFG1_OUTSEL_GP16C4T3_BKIN + * @arg MD_CMP_CFG1_OUTSEL_GP16C4T4_BKIN + * @retval None + */ +__STATIC_INLINE void md_cmp1_set_output_trigger_select(CMP_TypeDef *cmp, uint32_t outsel) +{ + MODIFY_REG(cmp->CFG1, CMP_CFG1_OUTSEL, outsel << CMP_CFG1_OUTSEL_POSS); +} + +/** + * @brief Return Comparator 1 output trigger selection + * @param cmp CMP Instance + * @retval The retval can be a value of the value: + * @arg MD_CMP_OUTSEL_NO + * @arg MD_CMP_CFG1_OUTSEL_AD16C4T1_BKIN + * @arg MD_CMP_CFG1_OUTSEL_GP16C4T1_BKIN + * @arg MD_CMP_CFG1_OUTSEL_GP16C4T2_BKIN + * @arg MD_CMP_CFG1_OUTSEL_GP16C4T3_BKIN + * @arg MD_CMP_CFG1_OUTSEL_GP16C4T4_BKIN + */ +__STATIC_INLINE uint32_t md_cmp1_get_output_trigger_select(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->CFG1, CMP_CFG1_OUTSEL) >> CMP_CFG1_OUTSEL_POSS); +} + +/** + * @brief Set Comparator 1 negative input selection + * @param cmp CMP Instance + * @param innsel This parameter can be one of the following values: + * @arg MD_CMP_CFG1_INNSEL_1DIV4_Vres + * @arg MD_CMP_CFG1_INNSEL_1DIV2_Vres + * @arg MD_CMP_CFG1_INNSEL_3DIV4_Vres + * @arg MD_CMP_CFG1_INNSEL_Vres + * @arg MD_CMP_CFG1_INNSEL_PA04 + * @arg MD_CMP_CFG1_INNSEL_PA05 + * @arg MD_CMP_CFG1_INNSEL_PA00 + * @retval None + */ +__STATIC_INLINE void md_cmp1_set_input_negative_select(CMP_TypeDef *cmp, uint32_t innsel) +{ + MODIFY_REG(cmp->CFG1, CMP_CFG1_INNSEL, innsel << CMP_CFG1_INNSEL_POSS); +} + +/** + * @brief Return Comparator 1 negative input selection + * @param cmp CMP Instance + * @retval The retval can be a value of the value: + * @arg MD_CMP_CFG1_INNSEL_1DIV4_Vres + * @arg MD_CMP_CFG1_INNSEL_1DIV2_Vres + * @arg MD_CMP_CFG1_INNSEL_3DIV4_Vres + * @arg MD_CMP_CFG1_INNSEL_Vres + * @arg MD_CMP_CFG1_INNSEL_PA04 + * @arg MD_CMP_CFG1_INNSEL_PA05 + * @arg MD_CMP_CFG1_INNSEL_PA00 + */ +__STATIC_INLINE uint32_t md_cmp1_get_input_negative_select(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->CFG1, CMP_CFG1_INNSEL) >> CMP_CFG1_INNSEL_POSS); +} + +/** + * @brief Enable Comparator 1 switch + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp1_enable(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_EN); +} +/** + * @brief Disable Comparator 1 switch + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp1_disable(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_EN); +} + +/** + * @brief Get Comparator 1 switch + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp1_is_enabled(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_EN) == (CMP_CFG1_EN)); +} +/** + * @} + */ + +/** @defgroup MD_CMP_Public_Functions_Group3 CFG2 + * @{ + */ +/** + * @brief Set CMP control register (CMP_CFG2) + * @param cmp CMP Instance + * @param value The value write in CMP_CFG2 + * @retval None + */ +__STATIC_INLINE void md_cmp_set_cfg2(CMP_TypeDef *cmp, uint32_t value) +{ + WRITE_REG(cmp->CFG2, value); +} + +/** + * @brief Get CMP control register (CMP_CFG1) + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_get_cfg2(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_REG(cmp->CFG2)); +} + +/** + * @brief Comparator 2 locked W/R + * @param cmp CMP Instance + * @param lock + @arg @ref MD_CMP_CFG2_LOCK_READ_WRITE + @arg @ref MD_CMP_CFG2_LOCK_ONLY_READ + * @retval None + */ +__STATIC_INLINE void md_cmp2_enable_lock(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG2_LOCK); +} + +/** + * @brief Get Comparator 2 locked + * @param cmp CMP Instance + * @retval The retval can be a value of the value: + @arg @ref MD_CMP_CFG2_LOCK_READ_WRITE + @arg @ref MD_CMP_CFG2_LOCK_ONLY_READ + */ +__STATIC_INLINE uint32_t md_cmp2_is_enabled_lock(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_LOCK) == (CMP_CFG2_LOCK)); +} + +/** + * @brief Get Comparator 2 output + * @param cmp CMP Instance + * @retval The retval can be a value of the value: + @arg @ref MD_CMP_CFG2_VALUE_OUTPUT_LOW_LEVEL + @arg @ref MD_CMP_CFG2_VALUE_OUTPUT_HIGH_LEVEL + */ +__STATIC_INLINE uint32_t md_cmp2_get_output_level(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->CFG2, CMP_CFG2_VALUE) >> CMP_CFG2_VALUE_POS); +} + +/** + * @brief Set Comparator 2 masking function + * @param cmp CMP Instance + * @param blanksel This parameter can be one of the following values: + * @arg MD_CMP_CFG2_BLANKSEL_CLOSE + * @arg MD_CMP_CFG2_BLANKSEL_AD16C4T1_OC4 + * @arg MD_CMP_CFG2_BLANKSEL_GP32C4T1_OC4 + * @arg MD_CMP_CFG2_BLANKSEL_GP16C4T1_OC4 + * @arg MD_CMP_CFG2_BLANKSEL_GP16C4T2_OC4 + * @arg MD_CMP_CFG2_BLANKSEL_GP16C2T1_OC2 + * @retval None + */ +__STATIC_INLINE void md_cmp2_set_blanking_source(CMP_TypeDef *cmp, uint32_t blanksel) +{ + MODIFY_REG(cmp->CFG2, CMP_CFG2_BLANKSEL, blanksel << CMP_CFG2_BLANKSEL_POSS); +} + +/** + * @brief Return Comparator 2 masking function + * @param cmp CMP Instance + * @retval None + * @arg MD_CMP_CFG2_BLANKSEL_CLOSE + * @arg MD_CMP_CFG2_BLANKSEL_AD16C4T1_OC4 + * @arg MD_CMP_CFG2_BLANKSEL_GP32C4T1_OC4 + * @arg MD_CMP_CFG2_BLANKSEL_GP16C4T1_OC4 + * @arg MD_CMP_CFG2_BLANKSEL_GP16C4T2_OC4 + * @arg MD_CMP_CFG2_BLANKSEL_GP16C2T1_OC2 + */ +__STATIC_INLINE uint32_t md_cmp2_get_blanking_source(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->CFG2, CMP_CFG2_BLANKSEL) >> CMP_CFG2_BLANKSEL_POSS); +} + +/** + * @brief Enable Comparator 2 filter function + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp2_enable_filter(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_FILT); +} +/** + * @brief Disable Comparator 2 filter function + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp2_disable_filter(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_FILT); +} + +/** + * @brief Check if Comparator 2 filter function select is enable + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp2_is_enabled_filter(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_FILT) == (CMP_CFG2_FILT)); +} + +/** + * @brief Enable Comparator 2 hysteresis function + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp2_enable_hysteresis(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_HYST); +} +/** + * @brief Disable Comparator 2 hysteresis function + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp2_disable_hysteresis(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_HYST); +} + +/** + * @brief Check if Comparator 2 hysteresis function + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp2_is_enabled_hysteresis(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_HYST) == (CMP_CFG2_HYST)); +} + +/** + * @brief Enable Comparator 2 output polarity + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp2_enable_polarity(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_POLARITY); +} + +/** + * @brief Disable Comparator 2 output polarity + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp2_disable_polarity(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_POLARITY); +} + +/** + * @brief Check if Comparator 2 output polarity + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp2_is_enabled_polarity(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_POLARITY) == (CMP_CFG2_POLARITY)); +} + +/** + * @brief Set Comparator 2 output trigger selection + * @param cmp CMP Instance + * @param outsel This parameter can be one of the following values: + * @arg MD_CMP_CFG2_OUTSEL_NO + * @arg MD_CMP_CFG2_OUTSEL_AD16C4T1_BKIN + * @arg MD_CMP_CFG2_OUTSEL_GP16C4T1_BKIN + * @arg MD_CMP_CFG2_OUTSEL_GP16C4T2_BKIN + * @arg MD_CMP_CFG2_OUTSEL_GP16C4T3_BKIN + * @arg MD_CMP_CFG2_OUTSEL_GP16C4T4_BKIN + * @retval None + */ +__STATIC_INLINE void md_cmp2_set_output_trigger_select(CMP_TypeDef *cmp, uint32_t outsel) +{ + MODIFY_REG(cmp->CFG2, CMP_CFG2_OUTSEL, outsel << CMP_CFG2_OUTSEL_POSS); +} + +/** + * @brief Return Comparator 2 output trigger selection + * @param cmp CMP Instance + * @retval The retval can be one of the following values: + * @arg MD_CMP_CFG2_OUTSEL_NO + * @arg MD_CMP_CFG2_OUTSEL_AD16C4T1_BKIN + * @arg MD_CMP_CFG2_OUTSEL_GP16C4T1_BKIN + * @arg MD_CMP_CFG2_OUTSEL_GP16C4T2_BKIN + * @arg MD_CMP_CFG2_OUTSEL_GP16C4T3_BKIN + * @arg MD_CMP_CFG2_OUTSEL_GP16C4T4_BKIN + */ +__STATIC_INLINE uint32_t md_cmp2_get_output_trigger_select(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->CFG2, CMP_CFG2_OUTSEL) >> CMP_CFG2_OUTSEL_POSS); +} + +/** + * @brief Enable Comparator 2 window output mode + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_window_out(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_WINOUT); +} +/** + * @brief Disable Comparator 2 window output mode + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_window_out(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_WINOUT); +} + +/** + * @brief Get Comparator 2 window output mode + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp_is_enabled_window_out(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_WINOUT) == (CMP_CFG2_WINOUT)); +} + +/** + * @brief Enable Comparator 2 window monitor mode + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_window_mode(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_WINMODE); +} +/** + * @brief Disable Comparator 2 window monitor mode + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_window_mode(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_WINMODE); +} + +/** + * @brief Get Comparator 2 window monitor mode + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp_is_enabled_window_mode(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_WINMODE) == (CMP_CFG2_WINMODE)); +} + +/** + * @brief Set Comparator 2 negative input selection + * @param cmp CMP Instance + * @param blanksel This parameter can be one of the following values: + * @arg MD_CMP_CFG2_INNSEL_1DIV4_Vres + * @arg MD_CMP_CFG2_INNSEL_1DIV2_Vres + * @arg MD_CMP_CFG2_INNSEL_3DIV4_Vres + * @arg MD_CMP_CFG2_INNSEL_Vres + * @arg MD_CMP_CFG2_INNSEL_PA04 + * @arg MD_CMP_CFG2_INNSEL_PA05 + * @arg MD_CMP_CFG2_INNSEL_PA02 + * @retval None + */ +__STATIC_INLINE void md_cmp2_set_input_negative_select(CMP_TypeDef *cmp, uint32_t innsel) +{ + MODIFY_REG(cmp->CFG2, CMP_CFG2_INNSEL, innsel << CMP_CFG2_INNSEL_POSS); +} + +/** + * @brief Return Comparator 2 negative input selection + * @param cmp CMP Instance + * @retval The retval can be one of the following values: + * @arg MD_CMP_CFG2_INNSEL_1DIV4_Vres + * @arg MD_CMP_CFG2_INNSEL_1DIV2_Vres + * @arg MD_CMP_CFG2_INNSEL_3DIV4_Vres + * @arg MD_CMP_CFG2_INNSEL_Vres + * @arg MD_CMP_CFG2_INNSEL_PA04 + * @arg MD_CMP_CFG2_INNSEL_PA05 + * @arg MD_CMP_CFG2_INNSEL_PA02 + */ +__STATIC_INLINE uint32_t md_cmp2_get_input_negative_select(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->CFG2, CMP_CFG2_INNSEL) >> CMP_CFG2_INNSEL_POSS); +} + +/** + * @brief Enable Comparator 2 switch + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp2_enable(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_EN); +} +/** + * @brief Disable Comparator 2 switch + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp2_disable(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_EN); +} + +/** + * @brief Get Comparator 2 switch + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp2_is_enabled(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_EN) == (CMP_CFG2_EN)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_crc.c b/os/common/ext/CMSIS/ES32/FS026/md/md_crc.c new file mode 100644 index 00000000000..29ae5b7bde4 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_crc.c @@ -0,0 +1,107 @@ +/********************************************************************************** + * + * @file md_crc.c + * @brief md_crc C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "system_fs026.h" +#include "md_crc.h" +#include "md_rcu.h" + +/** @addtogroup Micro_Driver + * @{ + */ + + +/** @defgroup CRC CRC + * @brief CRC micro driver + * @{ + */ + + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/** @defgroup MD_CRC_Private_Macros CRC Private Macros + * @{ + */ + + +/** + * @} MD_CRC_Private_Macros + */ + +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_CRC_Public_Functions CRC Public Functions + * @{ + */ + +/** + * @brief De-initialize CRC registers (Registers restored to their default values). + * @param crc CRC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: CRC registers are de-initialized + * - ERROR: CRC registers are not de-initialized + */ +ErrorStatus md_crc_deinit(CRC_TypeDef *crc) +{ + ErrorStatus status = SUCCESS; + + if (crc == CRC) + { + /* Force CRC reset */ + md_rcu_enable_crc_reset(RCU); + + /* Release CRC reset */ + md_rcu_disable_crc_reset(RCU); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @} MD_RCU_Public_Functions + */ + +/** + * @} RCU + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_crc.h b/os/common/ext/CMSIS/ES32/FS026/md/md_crc.h new file mode 100644 index 00000000000..ee53a9d0a0d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_crc.h @@ -0,0 +1,602 @@ +/********************************************************************************** + * + * @file md_crc.h + * @brief header file of md_crc.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 24 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_CRC_H__ +#define __MD_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_CRC CRC + * @brief CRC micro driver + * @{ + */ + +/** @defgroup MD_CRC_Pubulic_Types CRC Pubulic Types + * @{ + */ + +/** + * @brief CRC init structure + */ +typedef struct +{ + uint32_t xorout; + uint32_t refout; + uint32_t refin; + uint32_t byte; + uint32_t mode; + uint32_t req; + uint32_t ds; + uint32_t rst; +} md_crc_init_typedef; +/** + * @} + */ + +/** @defgroup MD_CRC_Public_Macros CRC Public Macros + * @{ + */ +#define MD_CRC_CON_MSB_ON (1) /*!< User can set this bit to change the 'byte' order of input data. */ +#define MD_CRC_CON_MSB_OFF (0) /*!< User can set this bit to change the 'byte' order of input data. */ + +#define MD_CRC_CON_SIZE_POLY32 (0) /*!< This allow user to select polynomial size. */ +#define MD_CRC_CON_SIZE_POLY16 (1) /*!< This allow user to select polynomial size. */ +#define MD_CRC_CON_SIZE_POLY8 (2) /*!< This allow user to select polynomial size. */ + +#define MD_CRC_CON_MODE_COMP_DISABLE (0) /*!< This allow user to check CRC result. */ +#define MD_CRC_CON_MODE_COMP_ZERO (1) /*!< This allow user to check CRC result. */ +#define MD_CRC_CON_MODE_COMP_ENABLE (2) /*!< This allow user to check CRC result. */ + +#define MD_CRC_CON_RESET 1 /*!< User can set this bit to reset CRC function. */ +/** + * @} + */ + +/** @defgroup MD_CRC_Public_Functions CRC Public Functions + * @{ + */ + +/** @defgroup MD_CRC_Public_Functions_Group2 INIT + * @{ + */ +/** + * @brief This register is used to write the CRC initial data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_initial_data(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->INIT, value); +} + +/** + * @brief This register is used to read the CRC initial data. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_initial_data(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_REG(crc->INIT)); +} +/** + * @} + */ + +/** @defgroup MD_CRC_Public_Functions_Group3 POLY + * @{ + */ +/** + * @brief This register is used to write the coefficient of the CRC polynomial. Default coefficient is for CRC32. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_polynomial_coef(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->POLY, value); +} + +/** + * @brief This register is used to read the coefficient of the CRC polynomial. Default coefficient is for CRC32. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_polynomial_coef(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_REG(crc->POLY)); +} +/** + * @} + */ + +/** @defgroup MD_CRC_Public_Functions_Group4 DATA + * @{ + */ +/** + * @brief This register is used to write word CRC input data. CRC will start to calculate result after this register is written. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_input_data32(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->DATA, value); +} + +/** + * @brief This register is used to read word CRC input data. CRC will start to calculate result after this register is written. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_input_data32(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_REG(crc->DATA)); +} + +/** + * @brief This register is used to write half word CRC input data. CRC will start to calculate result after this register is written. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000 + * @arg Maximum 0xFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_input_data16(CRC_TypeDef *crc, uint16_t value) +{ + //In order to write after conversion + WRITE_REG(*(uint16_t *) & (crc->DATA), value); +} + +/** + * @brief This register is used to read half word CRC input data. CRC will start to calculate result after this register is written. + * @param CRC Instance + * @retval value 0x0000 ~ 0xffff. + */ +__STATIC_INLINE uint16_t md_crc_get_input_data16(CRC_TypeDef *crc) +{ + return (uint16_t)(READ_REG(crc->DATA)); +} + +/** + * @brief This register is used to write byte CRC input data. CRC will start to calculate result after this register is written. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00 + * @arg Maximum 0xFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_input_data8(CRC_TypeDef *crc, uint8_t value) +{ + //In order to write after conversion + WRITE_REG(*(uint8_t *) & (crc->DATA), value); +} + +/** + * @brief This register is used to read byte CRC input data. CRC will start to calculate result after this register is written. + * @param CRC Instance + * @retval value 0x00 ~ 0xff. + */ +__STATIC_INLINE uint8_t md_crc_get_input_data8(CRC_TypeDef *crc) +{ + return (uint8_t)(READ_REG(crc->DATA)); +} +/** + * @} + */ + +/** @defgroup MD_CRC_Public_Functions_Group5 COMP + * @{ + */ +/** + * @brief This register is used to compare with the CRC output data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_compare_data(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->COMP, value); +} + +/** + * @brief This register is used to compare with the CRC output data. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_compare_data(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_REG(crc->COMP)); +} +/** + * @} + */ + +/** @defgroup MD_CRC_Public_Functions_Group6 REMA + * @{ + */ +/** + * @brief This register is used to set a parameter to do exclusive OR with CRC output data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_remainder_data(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->REMA, value); +} + +/** + * @brief This register is used to set a parameter to do exclusive OR with CRC output data. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_remainder_data(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_REG(crc->REMA)); +} +/** + * @} + */ + +/** @defgroup MD_CRC_Public_Functions_Group7 CON + * @{ + */ +/** + * @brief This register is used to set a parameter. + * @param CRC Instance + * @param value + * @retval None. + */ +__STATIC_INLINE void md_crc_set_control(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->CON, value); +} + +/** + * @brief This register is used to get a parameter. + * @param CRC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_crc_get_control(CRC_TypeDef *crc) +{ + return (uint32_t)READ_REG(READ_REG(crc->CON)); +} + +/** + * @brief This function allow user to enable DMA function enable. + * @param CRC Instance + * @retval None. + */ +__STATIC_INLINE void md_crc_enable_dma(CRC_TypeDef *crc) +{ + SET_BIT(crc->CON, CRC_CON_DMA); +} + +/** + * @brief This function allow user to enable DMA function disable. + * @param CRC Instance + * @retval None. + */ +__STATIC_INLINE void md_crc_disable_dma(CRC_TypeDef *crc) +{ + CLEAR_BIT(crc->CON, CRC_CON_DMA); +} + +/** + * @brief This function allow user to enable DMA function. + * @param CRC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_crc_is_enabled_dma(CRC_TypeDef *crc) +{ + return (READ_BIT(crc->CON, CRC_CON_DMA) == (CRC_CON_DMA)); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_MSB_ON + * @arg @ref MD_CRC_CON_MSB_OFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_input_data_msb(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_MSB, value << CRC_CON_MSB_POS); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_CRC_CON_MSB_ON + * @arg @ref MD_CRC_CON_MSB_OFF + */ +__STATIC_INLINE uint32_t md_crc_get_input_data_msb(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_BIT(crc->CON, CRC_CON_MSB) >> CRC_CON_MSB_POS); +} + +/** + * @brief This function allow user to reverse the order of CRC output data enable. + * @param CRC Instance + * @retval None. + */ +__STATIC_INLINE void md_crc_enable_output_data_reverse(CRC_TypeDef *crc) +{ + SET_BIT(crc->CON, CRC_CON_REOUT); +} + +/** + * @brief This function allow user to reverse the order of CRC output data disable. + * @param CRC Instance + * @retval None. + */ +__STATIC_INLINE void md_crc_disable_output_data_reverse(CRC_TypeDef *crc) +{ + CLEAR_BIT(crc->CON, CRC_CON_REOUT); +} + +/** + * @brief This function allow user to reverse the order of CRC output data. + * @param CRC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_crc_is_enabled_output_data_reverse(CRC_TypeDef *crc) +{ + return (READ_BIT(crc->CON, CRC_CON_REOUT) == (CRC_CON_REOUT)); +} + +/** + * @brief This function allow user to reverse the order of CRC input data enable. + * @param CRC Instance + * @retval None. + */ +__STATIC_INLINE void md_crc_enable_input_data_reverse(CRC_TypeDef *crc) +{ + SET_BIT(crc->CON, CRC_CON_REIN); +} + +/** + * @brief This function allow user to reverse the order of CRC input data disable. + * @param CRC Instance + * @retval None. + */ +__STATIC_INLINE void md_crc_disable_input_data_reverse(CRC_TypeDef *crc) +{ + CLEAR_BIT(crc->CON, CRC_CON_REIN); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_crc_is_enabled_input_data_reverse(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_REIN) == (CRC_CON_REIN))); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_SIZE_POLY32 + * @arg @ref MD_CRC_CON_SIZE_POLY16 + * @arg @ref MD_CRC_CON_SIZE_POLY8 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_polynomial_size(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_SIZE, value << CRC_CON_SIZE_POSS); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_CRC_CON_SIZE_POLY32 + * @arg @ref MD_CRC_CON_SIZE_POLY16 + * @arg @ref MD_CRC_CON_SIZE_POLY8 + */ +__STATIC_INLINE uint32_t md_crc_get_polynomial_size(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_BIT(crc->CON, CRC_CON_SIZE) >> CRC_CON_SIZE_POSS); +} + +/** + * @brief This function allow user to check CRC result. If CRC result is not correct, the status “FAIL” in CRC_STA will be set to 1. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_MODE_COMP_DISABLE + * @arg @ref MD_CRC_CON_MODE_COMP_ZERO + * @arg @ref MD_CRC_CON_MODE_COMP_ENABLE + * @retval None. + */ +__STATIC_INLINE void md_crc_set_compare_mode(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_MODE, value << CRC_CON_MODE_POSS); +} + +/** + * @brief This function allow user to check CRC result. If CRC result is not correct, the status “FAIL” in CRC_STA will be set to 1. + * @param CRC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_CRC_CON_MODE_COMP_DISABLE + * @arg @ref MD_CRC_CON_MODE_COMP_ZERO + * @arg @ref MD_CRC_CON_MODE_COMP_ENABLE + */ +__STATIC_INLINE uint32_t md_crc_get_compare_mode(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_BIT(crc->CON, CRC_CON_MODE) >> CRC_CON_MODE_POSS); +} + +/** + * @brief User can set this bit to reset CRC function. This bit will be cleared by itself. + * @param CRC Instance + * @retval None. + */ +__STATIC_INLINE void md_crc_trigger_reset(CRC_TypeDef *crc) +{ + SET_BIT(crc->CON, CRC_CON_RESET); +} +/** + * @} + */ + +/** @defgroup MD_CRC_Public_Functions_Group8 DOUT + * @{ + */ +/** + * @brief This register is used to show the CRC calculation result. + * @param CRC Instance + * @retval value: 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_output_data(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_REG(crc->DOUT)); +} +/** + * @} + */ + +/** @defgroup MD_CRC_Public_Functions_Group9 DOUT_XOR + * @{ + */ +/** + * @brief This register is used to show the CRC calculation exculsive OR result. + * @param CRC Instance + * @retval value: 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_output_data_xor(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_REG(crc->DOUT_XOR)); +} +/** + * @} + */ + +/** @defgroup MD_CRC_Public_Functions_Group10 STAT + * @{ + */ +/** + * @brief This register is used to show the CRC calculation exculsive OR result. + * @param CRC Instance + * @retval value: 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_status(CRC_TypeDef *crc) +{ + return (uint32_t)(READ_REG(crc->STAT)); +} + +/** + * @brief This bit is set when CRC result is not correct. + * @param CRC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_crc_is_active_flag_compare_fail(CRC_TypeDef *crc) +{ + return (READ_BIT(crc->STAT, CRC_STAT_FAIL) == (CRC_STAT_FAIL)); +} + +/** + * @brief This bit is cleaned after an CRC calculation. + * @param CRC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_crc_is_active_flag_empty(CRC_TypeDef *crc) +{ + return (READ_BIT(crc->STAT, CRC_STAT_EMPTY) == (CRC_STAT_EMPTY)); +} + +/** + * @brief This bit is set when CRC module is calculating result. + * @param CRC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_crc_is_active_flag_busy(CRC_TypeDef *crc) +{ + return (READ_BIT(crc->STAT, CRC_STAT_BUSY) == (CRC_STAT_BUSY)); +} + +/** + * @brief This bit is set when CRC module is calculating result. + * @param CRC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_crc_is_active_flag_done(CRC_TypeDef *crc) +{ + return (READ_BIT(crc->STAT, CRC_STAT_DONE) == (CRC_STAT_DONE)); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_csu.c b/os/common/ext/CMSIS/ES32/FS026/md/md_csu.c new file mode 100644 index 00000000000..3beeae0da2f --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_csu.c @@ -0,0 +1,115 @@ +/********************************************************************************** + * + * @file md_csu.c + * @brief md_csu C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 25 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "system_fs026.h" +#include "md_csu.h" +#include "md_rcu.h" +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup CSU CSU + * @brief CSU micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ + +/** @defgroup CSU_PUB_FUNC CSU Public Functions + * @brief CSU Public Functions + * @{ + */ + +/** + * @brief CSU Initialization + * @param csu CSU Instance + * @param CSU Init Structure + * @retval None + */ +void md_csu_init(CSU_TypeDef *csu, md_csu_init_typedef *CSU_InitStruct) +{ + md_csu_set_trim_source(csu, CSU_InitStruct->TrimSel); + md_csu_set_sync_polarity(csu, CSU_InitStruct->PolSel); + md_csu_set_sync_source(csu, CSU_InitStruct->SyncSrc); + md_csu_set_sync_source_div(csu, CSU_InitStruct->SyncDiv); +} + +/** + * @brief Set CSU Count tolerance and Counter reload value + * @param csu CSU Instance + * @param CSU_InitStruct + * @param clksrc Clock Source + @arg @ref CSU_CLKSRC_GPIO + @arg @ref CSU_CLKSRC_LOSC + @arg @ref CSU_CLKSRC_USB_SOF + * @retval None + */ +void md_csu_set(CSU_TypeDef *csu, md_csu_init_typedef *CSU_InitStruct, uint16_t clksrc) +{ + uint8_t cntth, div; + uint16_t reload, fsync; + + div = 1 << (CSU_InitStruct->SyncDiv >> CSU_CFG_SYNCDIV_POSS); + + fsync = clksrc / div; + + reload = ((__HRC48 / fsync) - 1); + cntth = (__HRC48 / fsync / 5 / 100 / 2); + + md_csu_set_trim_counter_tolerance(csu, cntth); + md_csu_set_trim_counter_reload(csu, reload); + + md_csu_enable_trim_counter(csu); + md_csu_enable_trim_auto(csu); +} + + +/** + * @} CSU_PUB_FUNC CSU Public Functions + */ + +/** + * @} CSU + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_csu.h b/os/common/ext/CMSIS/ES32/FS026/md/md_csu.h new file mode 100644 index 00000000000..66112b3cf96 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_csu.h @@ -0,0 +1,968 @@ +/********************************************************************************** + * + * @file md_csu.h + * @brief header file of md_csu.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 25 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_CSU_H__ +#define __MD_CSU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "fs026.h" + + +/** @addtogroup Micro_Driver + * @{ + */ + + +/** @defgroup MD_CSU CSU + * @brief CSU micro driver + * @{ + */ + +/** @defgroup MD_CSU_Pubulic_Types CSU Pubulic Types + * @{ + */ + +/** + * @brief CSU Init structure + */ +typedef struct +{ + uint32_t TrimSel; /*!< Trim Value Selection.*/ + uint32_t PolSel; /*!< Synchronous clock polarity selection.*/ + uint32_t SyncSrc; /*!< Synchronous clock source selection.*/ + uint32_t SyncDiv; /*!< Synchronous clock source pre-divider.*/ +} md_csu_init_typedef; + +typedef struct +{ + uint32_t CntTh; /*!< Count tolerance.*/ + uint32_t Reload; /*!< Counter reload value.*/ +} md_csu_set_typedef; +/** + * @} + */ + +/** @defgroup MD_CSU_Public_Macros CSU Public Macros + * @{ + */ + +#define MD_CSU_CFG_TRIMSEL_OPTIONBYTE (0U) +#define MD_CSU_CFG_TRIMSEL_CUSTOM (1U) + +#define MD_CSU_CFG_POLSEL_RISING (0U) +#define MD_CSU_CFG_POLSEL_FALLING (1U) + +#define MD_CSU_CFG_SYNCSRC_GPIO (0U) +#define MD_CSU_CFG_SYNCSRC_LOSC (1U) +#define MD_CSU_CFG_SYNCSRC_USB (2U) +#define MD_CSU_CFG_SYNCSRC_SW (3U) + +#define MD_CSU_CFG_SYNCDIV_DIV1 (0U) +#define MD_CSU_CFG_SYNCDIV_DIV2 (1U) +#define MD_CSU_CFG_SYNCDIV_DIV4 (2U) +#define MD_CSU_CFG_SYNCDIV_DIV8 (3U) +#define MD_CSU_CFG_SYNCDIV_DIV16 (4U) +#define MD_CSU_CFG_SYNCDIV_DIV32 (5U) +#define MD_CSU_CFG_SYNCDIV_DIV64 (6U) +#define MD_CSU_CFG_SYNCDIV_DIV128 (7U) + +#define CSU_CLKSRC_GPIO 1000 // GPIO Input 1kHz Frequency (User defined) +#define CSU_CLKSRC_LOSC __LOSC // LOSC 32.768kHz Divide by 32 +#define CSU_CLKSRC_USB_SOF 1000 // Get USB SOF Package every 1 ms +#define FSYNC CSU_CLKSRC_USB_SOF // Clock Source Selection (User defined) +#define MD_CSU_CFG_RELOAD ((__HRC48/FSYNC)-1) // (Ftarget/Fsync)-1 +#define MD_CSU_CFG_CNTTH (__HRC48/FSYNC/5/100/2) // (Ftarget/Fsync)*SETP[%]/100%/2 +/** + * @} + */ + + +/** @defgroup MD_CSU_Public_Functions CSU Public Functions + * @{ + */ + +/** @defgroup MD_CSU_Public_Functions_Group2 CON + * @{ + */ +/** + * @brief Set CSU_CON Register + * @param csu CSU Instance + * @param con + * @retval None + */ +__STATIC_INLINE void md_csu_set_con(CSU_TypeDef *csu, uint32_t con) +{ + WRITE_REG(csu->CON, con); +} + +/** + * @brief Get CSU_CON Register + * @param csu CSU Instance + * @retval Read all CSU_CON Register + */ +__STATIC_INLINE uint32_t md_csu_get_con(CSU_TypeDef *csu) +{ + return (uint32_t) READ_REG(csu->CON); +} + +/** + * @brief Set CSU Trim Value. + * @param csu CSU Instance. + * @param trim + * @retval None + */ +__STATIC_INLINE void md_csu_set_hrc48trim(CSU_TypeDef *csu, uint32_t trim) +{ + MODIFY_REG(csu->CON, CSU_CON_TRIM, trim << CSU_CON_TRIM_POSS); +} + +/** + * @brief Get CSU Trim Value. + * @param csu CSU Instance. + * @retval Read HRC48 Trim value + */ +__STATIC_INLINE uint32_t md_csu_get_hrc48trim(CSU_TypeDef *csu) +{ + return (uint32_t)((READ_BIT(csu->CON, CSU_CON_TRIM)) >> CSU_CON_TRIM_POSS); +} + +/** + * @brief CSU Software synchronization clock generation. + * @param csu CSU Instance + * @retval None + */ +__STATIC_INLINE void md_csu_trigger_sync_software(CSU_TypeDef *csu) +{ + SET_BIT(csu->CON, CSU_CON_SYNCGEN); +} + +/** + * @brief CSU Automatic calibration switch enable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_enable_trim_auto(CSU_TypeDef *csu) +{ + SET_BIT(csu->CON, CSU_CON_AUTOEN); +} + +/** + * @brief CSU Automatic calibration switch disable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_disable_trim_auto(CSU_TypeDef *csu) +{ + CLEAR_BIT(csu->CON, CSU_CON_AUTOEN); +} + +/** + * @brief Check if CSU Automatic calibration switch is enabled. + * @param csu CSU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : trim auto enable + * @arg 0x0 : trim auto disable + */ +__STATIC_INLINE uint32_t md_csu_is_enabled_trim_auto(CSU_TypeDef *csu) +{ + return (uint32_t)(READ_BIT(csu->CON, CSU_CON_AUTOEN) == (CSU_CON_AUTOEN)); +} + +/** + * @brief CSU Counter switch enable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_enable_trim_counter(CSU_TypeDef *csu) +{ + SET_BIT(csu->CON, CSU_CON_CNTEN); +} + +/** + * @brief CSU Counter switch disable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_disable_trim_counter(CSU_TypeDef *csu) +{ + CLEAR_BIT(csu->CON, CSU_CON_CNTEN); +} + +/** + * @brief Check if CSU Counter switch is enabled. + * @param csu CSU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : trim counter enable + * @arg 0x0 : trim counter disable + */ +__STATIC_INLINE uint32_t md_csu_is_enabled_trim_counter(CSU_TypeDef *csu) +{ + return (uint32_t)(READ_BIT(csu->CON, CSU_CON_CNTEN) == (CSU_CON_CNTEN)); +} +/** + * @} + */ + +/** @defgroup MD_CSU_Public_Functions_Group3 CFG + * @{ + */ +/** + * @brief Set CSU_CFG Register + * @param csu CSU Instance + * @param cfg + * @retval None + */ +__STATIC_INLINE void md_csu_set_cfg(CSU_TypeDef *csu, uint32_t cfg) +{ + WRITE_REG(csu->CFG, cfg); +} + +/** + * @brief Get CSU_CFG Register + * @param csu CSU Instance + * @retval Read all CSU_CFG Register + */ +__STATIC_INLINE uint32_t md_csu_get_cfg(CSU_TypeDef *csu) +{ + return (uint32_t) READ_REG(csu->CFG); +} + +/** + * @brief Set CSU Trim Value Selection. + * @param csu CSU Instance. + * @param trimsel + @arg @ref MD_CSU_CFG_TRIMSEL_OPTIONBYTE + @arg @ref MD_CSU_CFG_TRIMSEL_CUSTOM + * @retval None + */ +__STATIC_INLINE void md_csu_set_trim_source(CSU_TypeDef *csu, uint32_t trimsel) +{ + MODIFY_REG(csu->CFG, CSU_CFG_TRIMSEL, trimsel << CSU_CFG_TRIMSEL_POS); +} + +/** + * @brief Get CSU Trim Value Selection. + * @param csu CSU Instance. + * @retval The retval can be one of the following values: + @arg @ref MD_CSU_CFG_TRIMSEL_OPTIONBYTE + @arg @ref MD_CSU_CFG_TRIMSEL_CUSTOM + */ +__STATIC_INLINE uint32_t md_csu_get_trim_source(CSU_TypeDef *csu) +{ + return (uint32_t)(READ_BIT(csu->CFG, CSU_CFG_TRIMSEL) >> CSU_CFG_TRIMSEL_POS); +} + +/** + * @brief Set CSU Synchronous clock polarity selection. + * @param csu CSU Instance. + * @param polsel + @arg @ref MD_CSU_CFG_POLSEL_RISING + @arg @ref MD_CSU_CFG_POLSEL_FALLING + * @retval None + */ +__STATIC_INLINE void md_csu_set_sync_polarity(CSU_TypeDef *csu, uint32_t polsel) +{ + MODIFY_REG(csu->CFG, CSU_CFG_POLSEL, polsel << CSU_CFG_POLSEL_POS); +} + +/** + * @brief Get CSU Synchronous clock polarity selection. + * @param csu CSU Instance. + * @retval The retval can be one of the following values: + @arg @ref MD_CSU_CFG_POLSEL_RISING + @arg @ref MD_CSU_CFG_POLSEL_FALLING + */ +__STATIC_INLINE uint32_t md_csu_get_sync_polarity(CSU_TypeDef *csu) +{ + return (uint32_t)(READ_BIT(csu->CFG, CSU_CFG_POLSEL) >> CSU_CFG_POLSEL_POS); +} + +/** + * @brief Set CSU Synchronous clock source selection. + * @param csu CSU Instance. + * @param syncsrc + @arg @ref MD_CSU_CFG_SYNCSRC_GPIO + @arg @ref MD_CSU_CFG_SYNCSRC_LOSC + @arg @ref MD_CSU_CFG_SYNCSRC_USB + @arg @ref MD_CSU_CFG_SYNCSRC_SW + * @retval None + */ +__STATIC_INLINE void md_csu_set_sync_source(CSU_TypeDef *csu, uint32_t syncsrc) +{ + MODIFY_REG(csu->CFG, CSU_CFG_SYNCSRC, syncsrc << CSU_CFG_SYNCSRC_POSS); +} + +/** + * @brief Get CSU Synchronous clock source selection. + * @param csu CSU Instance. + * @retval The retval can be one of the following values: + @arg @ref MD_CSU_CFG_SYNCSRC_GPIO + @arg @ref MD_CSU_CFG_SYNCSRC_LOSC + @arg @ref MD_CSU_CFG_SYNCSRC_USB + @arg @ref MD_CSU_CFG_SYNCSRC_SW + */ +__STATIC_INLINE uint32_t md_csu_get_sync_source(CSU_TypeDef *csu) +{ + return (uint32_t)(READ_BIT(csu->CFG, CSU_CFG_SYNCSRC) >> CSU_CFG_SYNCSRC_POSS); +} + +/** + * @brief Set CSU Synchronous clock source pre-divider. + * @param csu CSU Instance. + * @param syncdiv + @arg @ref MD_CSU_CFG_SYNCDIV_DIV1 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV2 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV4 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV8 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV16 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV32 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV64 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV128 + * @retval None + */ +__STATIC_INLINE void md_csu_set_sync_source_div(CSU_TypeDef *csu, uint32_t syncdiv) +{ + MODIFY_REG(csu->CFG, CSU_CFG_SYNCDIV, syncdiv << CSU_CFG_SYNCDIV_POSS); +} + +/** + * @brief Get CSU Synchronous clock source pre-divider. + * @param csu CSU Instance. + * @retval The retval can be one of the following values: + @arg @ref MD_CSU_CFG_SYNCDIV_DIV1 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV2 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV4 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV8 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV16 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV32 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV64 + @arg @ref MD_CSU_CFG_SYNCDIV_DIV128 + */ +__STATIC_INLINE uint32_t md_csu_get_sync_source_div(CSU_TypeDef *csu) +{ + return (uint32_t)(READ_BIT(csu->CFG, CSU_CFG_SYNCDIV) >> CSU_CFG_SYNCDIV_POSS); +} + +/** + * @brief Set CSU Count tolerance. + * @param csu CSU Instance. + * @param cntth + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_csu_set_trim_counter_tolerance(CSU_TypeDef *csu, uint32_t cntth) +{ + MODIFY_REG(csu->CFG, CSU_CFG_CNTTH, cntth << CSU_CFG_CNTTH_POSS); +} + +/** + * @brief Get CSU Count tolerance. + * @param csu CSU Instance. + * @retval Read Count tolerance + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_csu_get_trim_counter_tolerance(CSU_TypeDef *csu) +{ + return (uint32_t)((READ_BIT(csu->CFG, CSU_CFG_CNTTH)) >> CSU_CFG_CNTTH_POSS); +} + +/** + * @brief Set CSU Counter reload value. + * @param csu CSU Instance. + * @param reload + * @arg Max Value 0xFFFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_csu_set_trim_counter_reload(CSU_TypeDef *csu, uint32_t reload) +{ + MODIFY_REG(csu->CFG, CSU_CFG_RELOAD, reload << CSU_CFG_RELOAD_POSS); +} + +/** + * @brief Get CSU Counter reload value. + * @param csu CSU Instance. + * @retval Read Counter reload value + * @arg Max Value 0xFFFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_csu_get_trim_counter_reload(CSU_TypeDef *csu) +{ + return (uint32_t)((READ_BIT(csu->CFG, CSU_CFG_RELOAD)) >> CSU_CFG_RELOAD_POSS); +} +/** + * @} + */ + +/** @defgroup MD_CSU_Public_Functions_Group4 STAT + * @{ + */ +/** + * @brief Get CSU_STAT Register + * @param csu CSU Instance + * @retval Read all CSC_STAT Register + */ +__STATIC_INLINE uint32_t md_csu_get_stat(CSU_TypeDef *csu) +{ + return (uint32_t) READ_REG(csu->STAT); +} + +/** + * @brief Get CSU Option Byte value. + * @param csu CSU Instance. + * @retval Read Option Byte trim value + */ +__STATIC_INLINE uint32_t md_csu_get_option_hrc48trim(CSU_TypeDef *csu) +{ + return (uint32_t)((READ_BIT(csu->STAT, CSU_STAT_OPT_TRIM)) >> CSU_STAT_OPT_TRIM_POSS); +} + +/** + * @brief Get CSU Counter direction. + * @param csu CSU Instance + * @retval Read Counter direction + * @arg 0x1 : Countdown + * @arg 0x0 : Countup + */ +__STATIC_INLINE uint32_t md_csu_get_trim_counter_direction(CSU_TypeDef *csu) +{ + return (uint32_t)((READ_BIT(csu->STAT, CSU_STAT_CNTDIR)) >> CSU_STAT_CNTDIR_POS); +} + +/** + * @brief Get CSU Count value record. + * @param csu CSU Instance. + * @retval Read Count value record + */ +__STATIC_INLINE uint32_t md_csu_get_trim_counter_capture(CSU_TypeDef *csu) +{ + return (uint32_t)((READ_BIT(csu->STAT, CSU_STAT_CNTCAP)) >> CSU_STAT_CNTCAP_POSS); +} +/** + * @} + */ + +/** @defgroup MD_CSU_Public_Functions_Group5 IER + * @{ + */ +/** + * @brief Set CSU_IER Register + * @param csu CSU Instance + * @param ier + */ +__STATIC_INLINE void md_csu_set_ier(CSU_TypeDef *csu, uint32_t ier) +{ + WRITE_REG(csu->IER, ier); +} + +/** + * @brief Ideal synchronous interrupt function Enable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_enable_it_trim_match(CSU_TypeDef *csu) +{ + SET_BIT(csu->IER, CSU_IER_FHIT); +} + +/** + * @brief Calibration value error interrupt function Enable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_enable_it_trim_error(CSU_TypeDef *csu) +{ + SET_BIT(csu->IER, CSU_IER_TRIMERR); +} + +/** + * @brief Clock synchronization abnormal interrupt function Enable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_enable_it_trim_fault(CSU_TypeDef *csu) +{ + SET_BIT(csu->IER, CSU_IER_FFAULT); +} + +/** + * @brief Clock synchronization error interrupt function Enable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_enable_it_counter_error(CSU_TypeDef *csu) +{ + SET_BIT(csu->IER, CSU_IER_FERROR); +} + +/** + * @brief Clock synchronization warning interrupt function Enable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_enable_it_counter_warning(CSU_TypeDef *csu) +{ + SET_BIT(csu->IER, CSU_IER_FWARN); +} + +/** + * @brief Clock synchronization match interrupt function Enable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_enable_it_counter_match(CSU_TypeDef *csu) +{ + SET_BIT(csu->IER, CSU_IER_FMATCH); +} +/** + * @} + */ + +/** @defgroup MD_CSU_Public_Functions_Group6 IDR + * @{ + */ +/** + * @brief Set CSU_IDR Register + * @param csu CSU Instance + * @param idr + */ +__STATIC_INLINE void md_csu_set_idr(CSU_TypeDef *csu, uint32_t idr) +{ + WRITE_REG(csu->IDR, idr); +} + +/** + * @brief Ideal synchronous interrupt function Disable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_disable_it_trim_match(CSU_TypeDef *csu) +{ + SET_BIT(csu->IDR, CSU_IDR_FHIT); +} + +/** + * @brief Calibration value error interrupt function Disable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_disable_it_trim_error(CSU_TypeDef *csu) +{ + SET_BIT(csu->IDR, CSU_IDR_TRIMERR); +} + +/** + * @brief Clock synchronization abnormal interrupt function Disable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_disable_it_trim_fault(CSU_TypeDef *csu) +{ + SET_BIT(csu->IDR, CSU_IDR_FFAULT); +} + +/** + * @brief Clock synchronization error interrupt function Disable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_disable_it_counter_error(CSU_TypeDef *csu) +{ + SET_BIT(csu->IDR, CSU_IDR_FERROR); +} + +/** + * @brief Clock synchronization warning interrupt function Disable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_disable_it_counter_warning(CSU_TypeDef *csu) +{ + SET_BIT(csu->IDR, CSU_IDR_FWARN); +} + +/** + * @brief Clock synchronization match interrupt function Disable. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_disable_it_counter_match(CSU_TypeDef *csu) +{ + SET_BIT(csu->IDR, CSU_IDR_FMATCH); +} +/** + * @} + */ + +/** @defgroup MD_CSU_Public_Functions_Group7 IVS + * @{ + */ +/** + * @brief Get CSU_IVS Register + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_csu_get_ivs(CSU_TypeDef *csu) +{ + return (uint32_t) READ_REG(csu->IVS); +} + +/** + * @brief Check if Ideal synchronous interrupt is enabled. + * @param csu CSU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : trim match + * @arg 0x0 : trim mismatch + */ +__STATIC_INLINE uint32_t md_csu_is_enabled_it_trim_match(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IVS, CSU_IVS_FHIT) == (CSU_IVS_FHIT)); +} + +/** + * @brief Check if Calibration value error interrupt is enabled. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_enabled_it_trim_error(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IVS, CSU_IVS_TRIMERR) == (CSU_IVS_TRIMERR)); +} + +/** + * @brief Check if Clock synchronization abnormal interrupt is enabled. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_enabled_it_trim_fault(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IVS, CSU_IVS_FFAULT) == (CSU_IVS_FFAULT)); +} + +/** + * @brief Check if Clock synchronization error interrupt is enabled. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_enabled_it_counter_error(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IVS, CSU_IVS_FERROR) == (CSU_IVS_FERROR)); +} + +/** + * @brief Check if Clock synchronization warning interrupt is enabled. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_enabled_it_counter_warning(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IVS, CSU_IVS_FWARN) == (CSU_IVS_FWARN)); +} + +/** + * @brief Check if Clock synchronization match interrupt is enabled. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_enabled_it_counter_match(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IVS, CSU_IVS_FMATCH) == (CSU_IVS_FMATCH)); +} +/** + * @} + */ + +/** @defgroup MD_CSU_Public_Functions_Group8 RIF + * @{ + */ +/** + * @brief Set CSU_RIF Register + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_csu_get_rif(CSU_TypeDef *csu) +{ + return (uint32_t) READ_REG(csu->RIF); +} + +/** + * @brief Get Ideal synchronous interrupt flag. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_active_flag_trim_match(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->RIF, CSU_RIF_FHIT) == (CSU_RIF_FHIT)); +} + +/** + * @brief Get Calibration value error interrupt flag. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_active_flag_trim_error(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->RIF, CSU_RIF_TRIMERR) == (CSU_RIF_TRIMERR)); +} + +/** + * @brief Get Clock synchronization abnormal interrupt flag. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_active_flag_trim_fault(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->RIF, CSU_RIF_FFAULT) == (CSU_RIF_FFAULT)); +} + +/** + * @brief Get Clock synchronization error interrupt flag. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_active_flag_counter_error(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->RIF, CSU_RIF_FERROR) == (CSU_RIF_FERROR)); +} + +/** + * @brief Get Clock synchronization warning interrupt flag. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_active_flag_counter_warning(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->RIF, CSU_RIF_FWARN) == (CSU_RIF_FWARN)); +} + +/** + * @brief Get Clock synchronization match interrupt flag. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_active_flag_counter_match(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->RIF, CSU_RIF_FMATCH) == (CSU_RIF_FMATCH)); +} +/** + * @} + */ + +/** @defgroup MD_CSU_Public_Functions_Group9 IFM + * @{ + */ +/** + * @brief Set CSU_IFM Register + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_csu_get_ifm(CSU_TypeDef *csu) +{ + return (uint32_t) READ_REG(csu->IFM); +} + +/** + * @brief Get Ideal synchronous interrupt flag masked. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_masked_it_trim_match(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IFM, CSU_IFM_FHIT) == (CSU_IFM_FHIT)); +} + +/** + * @brief Get Calibration value error interrupt flag masked. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_masked_it_trim_error(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IFM, CSU_IFM_TRIMERR) == (CSU_IFM_TRIMERR)); +} + +/** + * @brief Get Clock synchronization abnormal interrupt flag masked. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_masked_it_trim_fault(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IFM, CSU_IFM_FFAULT) == (CSU_IFM_FFAULT)); +} + +/** + * @brief Get Clock synchronization error interrupt flag masked. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_masked_it_counter_error(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IFM, CSU_IFM_FERROR) == (CSU_IFM_FERROR)); +} + +/** + * @brief Get Clock synchronization warning interrupt flag masked. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_masked_it_counter_warning(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IFM, CSU_IFM_FWARN) == (CSU_IFM_FWARN)); +} + +/** + * @brief Get Clock synchronization match interrupt flag masked. + * @param csu CSU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_csu_is_masked_it_counter_match(CSU_TypeDef *csu) +{ + return (READ_BIT(csu->IFM, CSU_IFM_FMATCH) == (CSU_IFM_FMATCH)); +} +/** + * @} + */ + +/** @defgroup MD_CSU_Public_Functions_Group10 ICR + * @{ + */ +/** + * @brief Set CSU_ICR Register + * @param csu CSU Instance + * @param icr + * @retval None. + */ +__STATIC_INLINE void md_csu_set_icr(CSU_TypeDef *csu, uint32_t icr) +{ + WRITE_REG(csu->ICR, icr); +} + +/** + * @brief Ideal synchronous interrupt function flag clear. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_clear_it_trim_match(CSU_TypeDef *csu) +{ + SET_BIT(csu->ICR, CSU_ICR_FHIT); +} + +/** + * @brief Calibration value error interrupt function flag clear. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_clear_it_trim_error(CSU_TypeDef *csu) +{ + SET_BIT(csu->ICR, CSU_ICR_TRIMERR); +} + +/** + * @brief Clock synchronization abnormal interrupt function flag clear. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_clear_it_trim_fault(CSU_TypeDef *csu) +{ + SET_BIT(csu->ICR, CSU_ICR_FFAULT); +} + +/** + * @brief Clock synchronization error interrupt function flag clear. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_clear_it_counter_error(CSU_TypeDef *csu) +{ + SET_BIT(csu->ICR, CSU_ICR_FERROR); +} + +/** + * @brief Clock synchronization warning interrupt function flag clear. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_clear_it_counter_warning(CSU_TypeDef *csu) +{ + SET_BIT(csu->ICR, CSU_ICR_FWARN); +} + +/** + * @brief Clock synchronization match interrupt function flag clear. + * @param csu CSU Instance + * @retval None. + */ +__STATIC_INLINE void md_csu_clear_it_counter_match(CSU_TypeDef *csu) +{ + SET_BIT(csu->ICR, CSU_ICR_FMATCH); +} +/** + * @} + */ + +/** @defgroup MD_CSU_Public_Functions_Group1 Initialization + * @{ + */ +void md_csu_init(CSU_TypeDef *csu, md_csu_init_typedef *CSU_InitStruct); +void md_csu_set(CSU_TypeDef *csu, md_csu_init_typedef *CSU_InitStruct, uint16_t); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_dma.c b/os/common/ext/CMSIS/ES32/FS026/md/md_dma.c new file mode 100644 index 00000000000..f975cce8e15 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_dma.c @@ -0,0 +1,163 @@ +/********************************************************************************** + * + * @file md_dma.c + * @brief md_dma C file + * + * @date 26 Apr 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Apr 2022 AE Team the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + + +/* Includes -------------------------------------------------------------------*/ +#include "md_syscfg.h" +#include "md_dma.h" +#include +#include +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Private function prototypes ------------------------------------------------*/ +/* Public functions -----------------------------------------------------------*/ + + + + +void md_dma_init(DMA_TypeDef *DMAx, md_dma_init_typedef DMAx_init) +{ + if (DMAx_init.type == MD_DMA_PRIMARY) + { + md_dma_enable_primary_mode(DMAx, DMAx_init.channal); + md_dma_set_primary_channel_source_data_end_address(DMAx, DMAx_init.channal, DMAx_init.source_data_end_address); + md_dma_set_primary_channel_destination_data_end_address(DMAx, DMAx_init.channal, DMAx_init.destination_data_end_address); + md_dma_set_primary_channel_cycle_mode(DMAx, DMAx_init.channal, DMAx_init.cycle_mode); + + if ((DMAx_init.transfer_number - 1) > 0) + { + md_dma_set_primary_channel_transfer_number(DMAx, DMAx_init.channal, DMAx_init.transfer_number - 1); + } + else + { + md_dma_set_primary_channel_transfer_number(DMAx, DMAx_init.channal, 0); + } + + md_dma_set_primary_channel_r_power(DMAx, DMAx_init.channal, DMAx_init.r_power); + md_dma_set_primary_channel_source_address_size(DMAx, DMAx_init.channal, DMAx_init.source_address_size); + md_dma_set_primary_channel_source_address_incremental(DMAx, DMAx_init.channal, DMAx_init.source_address_incremental); + md_dma_set_primary_channel_destination_address_size(DMAx, DMAx_init.channal, DMAx_init.destination_address_size); + md_dma_set_primary_channel_destination_address_incremental(DMAx, DMAx_init.channal, DMAx_init.destination_address_incremental); + } + else if (DMAx_init.type == MD_DMA_ALTERNATE) + { + md_dma_enable_alternate_mode(DMAx, DMAx_init.channal); + md_dma_set_alternate_channel_source_data_end_address(DMAx, DMAx_init.channal, DMAx_init.source_data_end_address); + md_dma_set_alternate_channel_destination_data_end_address(DMAx, DMAx_init.channal, DMAx_init.destination_data_end_address); + md_dma_set_alternate_channel_cycle_mode(DMAx, DMAx_init.channal, DMAx_init.cycle_mode); + + if ((DMAx_init.transfer_number - 1) > 0) + { + md_dma_set_alternate_channel_transfer_number(DMAx, DMAx_init.channal, DMAx_init.transfer_number - 1); + } + else + { + md_dma_set_alternate_channel_transfer_number(DMAx, DMAx_init.channal, 0); + } + + md_dma_set_alternate_channel_r_power(DMAx, DMAx_init.channal, DMAx_init.r_power); + md_dma_set_alternate_channel_source_address_size(DMAx, DMAx_init.channal, DMAx_init.source_address_size); + md_dma_set_alternate_channel_source_address_incremental(DMAx, DMAx_init.channal, DMAx_init.source_address_incremental); + md_dma_set_alternate_channel_destination_address_size(DMAx, DMAx_init.channal, DMAx_init.destination_address_size); + md_dma_set_alternate_channel_destination_address_incremental(DMAx, DMAx_init.channal, DMAx_init.destination_address_incremental); + } + + + if (DMAx_init.disable_auto_software_enable_channel == 0) + md_dma_enable_channel(DMAx, DMAx_init.channal); +} + +/** + * @brief md_dma_set_channel_data_start_address_and_length + * @param len: + number of arrays + * @param size: + MD_DMA_CHANNEL_SIZE_BYTE + MD_DMA_CHANNEL_SIZE_HALF_WORD + MD_DMA_CHANNEL_SIZE_WORD + * @retval None + */ + +uint32_t md_dma_set_channel_data_start_address_and_length(uint32_t addr, uint32_t len, uint32_t size) +{ + return (uint32_t)addr + ((len - 1) * (1 << size)); +} + +/** + * @brief md_dma_set_primary_channel_destination_data_start_address_and_length + * @param ch: + MD_DMA_CHANNEL0 + MD_DMA_CHANNEL1 + MD_DMA_CHANNEL2 + MD_DMA_CHANNEL3 + MD_DMA_CHANNEL4 + MD_DMA_CHANNEL5 + * @param len: + number of arrays + * @param size: + MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_BYTE + MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_HALF_WORD + MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_WORD + * @retval None + */ + +void md_dma_set_primary_channel_destination_data_start_address_and_length(DMA_TypeDef *DMAx, uint32_t ch, uint32_t addr, uint32_t len, uint32_t size) +{ + md_dma_set_primary_channel_destination_data_end_address(DMAx, ch, (uint32_t)addr + ((len - 1) * (1 << size))); +} + + +/** + * @brief md_dma_set_primary_channel_source_data_start_address_and_length + * @param ch: + MD_DMA_CHANNEL0 + MD_DMA_CHANNEL1 + MD_DMA_CHANNEL2 + MD_DMA_CHANNEL3 + MD_DMA_CHANNEL4 + MD_DMA_CHANNEL5 + * @param len: + number of arrays + * @param size: + MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_BYTE + MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_HALF_WORD + MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_WORD + * @retval None + */ + +void md_dma_set_primary_channel_source_data_start_address_and_length(DMA_TypeDef *DMAx, uint32_t ch, uint32_t addr, uint32_t len, uint32_t size) +{ + md_dma_set_primary_channel_source_data_end_address(DMAx, ch, (uint32_t)addr + ((len - 1) * (1 << size))); +} + + diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_dma.h b/os/common/ext/CMSIS/ES32/FS026/md/md_dma.h new file mode 100644 index 00000000000..acd64e5635a --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_dma.h @@ -0,0 +1,2035 @@ +/********************************************************************************** + * + * @file md_dma.h + * @brief header file of md_dma.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 25 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_DMA_H__ +#define __MD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" +#include "reg_dma.h" +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (DMA1) + +/** @defgroup DMA DMA + * @brief DMA micro driver + * @{ + */ + +/** @defgroup MD_DMA_Pubulic_Types GPIO Pubulic Types + * @{ + */ + +/** + * @brief MD DMA Init Structure definition + */ +typedef struct +{ + uint32_t type; /** DMA channal set type + @ref MD_DMA_PRIMARY + @ref MD_DMA_ALTERNATE + */ + + uint32_t channal; /** DMA channel macros define + @ref MD_DMA_CHANNEL0 + @ref MD_DMA_CHANNEL1 + @ref MD_DMA_CHANNEL2 + @ref MD_DMA_CHANNEL3 + @ref MD_DMA_CHANNEL4 + @ref MD_DMA_CHANNEL5 + */ + uint32_t cycle_mode; /** DMA cycle_mode + @ref MD_DMA_CHANNEL_CFG_MODE_STOP + @ref MD_DMA_CHANNEL_CFG_MODE_BASIC + @ref MD_DMA_CHANNEL_CFG_MODE_AUTO + @ref MD_DMA_CHANNEL_CFG_MODE_PING_PONG + @ref MD_DMA_CHANNEL_CFG_MODE_MEMORY_PRIMARY + @ref MD_DMA_CHANNEL_CFG_MODE_MEMORY_ALTERNATE + @ref MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_PRIMARY + @ref MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_ALTERNATE + */ + uint32_t r_power; /** DMA r_power + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1 + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_2 + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_4 + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_8 + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_16 + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_32 + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_64 + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_128 + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_256 + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_512 + @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1024 + */ + uint32_t source_address_size; /** DMA source_address_size + @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_BYTE + @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_HALF_WORD + @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_WORD + */ + uint32_t source_address_incremental; /** DMA source_address_incremental + @ref MD_DMA_CHANNEL_CFG_SRCINC_BYTE + @ref MD_DMA_CHANNEL_CFG_SRCINC_HALF_WORD + @ref MD_DMA_CHANNEL_CFG_SRCINC_WORD + @ref MD_DMA_CHANNEL_CFG_SRCINC_NO_INC + */ + uint32_t destination_address_size; /** DMA source_address_size + @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_BYTE + @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_HALF_WORD + @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_WORD + */ + uint32_t destination_address_incremental; /** DMA source_address_incremental + @ref MD_DMA_CHANNEL_CFG_DSTINC_BYTE + @ref MD_DMA_CHANNEL_CFG_DSTINC_HALF_WORD + @ref MD_DMA_CHANNEL_CFG_DSTINC_WORD + @ref MD_DMA_CHANNEL_CFG_DSTINC_NO_INC + */ + uint32_t transfer_number; /** DMA transfer_number + @Note counting from 1.For example, if I want to send 5 pieces of information, just fill in 5. + */ + uint32_t source_data_end_address; /** DMA source_data_end_address + @ref md_dma_set_channel_data_start_address_and_length + */ + uint32_t destination_data_end_address; /** DMA destination_data_end_address + @ref md_dma_set_channel_data_start_address_and_length + */ + bool disable_auto_software_enable_channel;/** disable software enable channel in DMA_init()*/ +} md_dma_init_typedef; + +typedef union +{ + struct + { + uint32_t cycle_mode: 3; + uint32_t next_useburst: 1; + uint32_t transfer_number: 10; + uint32_t r_power : 4; + uint32_t reserved0: 3; + uint32_t reserved1: 3; + uint32_t source_address_size: 2; + uint32_t source_address_incremental: 2; + uint32_t destination_address_size: 2; + uint32_t destination_address_incremental: 2; + } md_dma_config_typedef; + uint32_t word; +} md_dma_control_typedef; + +typedef struct +{ + uint32_t source_data_end_address; //0x00 Pointer to the end address of the source data + uint32_t destination_data_end_address; //0x04 Pointer to the end address of the destination data + md_dma_control_typedef control; //0x08 Control data configuration + uint32_t reserved; //0x0C RESERVED +} md_dma_channel_config_typedef; +/** + * @} + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_DMA_Public_Constants DMA Public Constants + * @{ + */ + +/* DMA SELCON Index */ +#define MD_DMA_SELCON_INDEX(DMAx, CH) (*((uint32_t *)&DMAx->CH0_SELCON + CH)) + +/* DMA PRI_SRC_DATA_END_PTR Index */ +#define MD_DMA_PRI_SRC_DATA_END_INDEX(DMAx, CH) (*((uint32_t *)&DMAx->PRI_CH00_SRC_DATA_END_PTR + (CH * 4))) + +/* DMA PRI_DST_DATA_END_PTR Index */ +#define MD_DMA_PRI_DST_DATA_END_INDEX(DMAx, CH) (*((uint32_t *)&DMAx->PRI_CH00_DST_DATA_END_PTR + (CH * 4))) + +/* DMA PRI_CHANNEL_CFG Index */ +#define MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, CH) (*((uint32_t *)&DMAx->PRI_CH00_CHANNEL_CFG + (CH * 4))) + +/* DMA ALT_SRC_DATA_END_PTR Index */ +#define MD_DMA_ALT_SRC_DATA_END_INDEX(DMAx, CH) (*((uint32_t *)&DMAx->ALT_CH00_SRC_DATA_END_PTR + (CH * 4))) + +/* DMA ALT_DST_DATA_END_PTR Index */ +#define MD_DMA_ALT_DST_DATA_END_INDEX(DMAx, CH) (*((uint32_t *)&DMAx->ALT_CH00_DST_DATA_END_PTR + (CH * 4))) + +/* DMA ALT_CHANNEL_CFG Index */ +#define MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, CH) (*((uint32_t *)&DMAx->ALT_CH00_CHANNEL_CFG + (CH * 4))) + + +/* DMA channel macros define */ +#define MD_DMA_CHANNEL0 0 +#define MD_DMA_CHANNEL1 1 +#define MD_DMA_CHANNEL2 2 +#define MD_DMA_CHANNEL3 3 +#define MD_DMA_CHANNEL4 4 +#define MD_DMA_CHANNEL5 5 + +/* DMA channel set macros define */ +//#define MD_DMA_CHANNEL0_SET (1 << 0) +//#define MD_DMA_CHANNEL1_SET (1 << 1) +//#define MD_DMA_CHANNEL2_SET (1 << 2) +//#define MD_DMA_CHANNEL3_SET (1 << 3) +//#define MD_DMA_CHANNEL4_SET (1 << 4) +//#define MD_DMA_CHANNEL5_SET (1 << 5) + +/* DMA peripheral request select macros define */ +#define MD_DMA_PRS_UART1_TX 0 +#define MD_DMA_PRS_UART2_TX 1 +#define MD_DMA_PRS_UART3_TX 2 +#define MD_DMA_PRS_UART4_TX 3 +#define MD_DMA_PRS_SPI1_TX 5 +#define MD_DMA_PRS_I2S1_TX 5 +#define MD_DMA_PRS_SPI2_TX 6 +#define MD_DMA_PRS_I2C1_TX 7 +#define MD_DMA_PRS_I2C2_TX 8 +#define MD_DMA_PRS_AES_IN 9 +#define MD_DMA_PRS_CRC 11 +#define MD_DMA_PRS_SPI3_TX 12 +#define MD_DMA_PRS_UART1_RX 15 +#define MD_DMA_PRS_UART2_RX 16 +#define MD_DMA_PRS_UART3_RX 17 +#define MD_DMA_PRS_UART4_RX 18 +#define MD_DMA_PRS_SPI1_RX 20 +#define MD_DMA_PRS_I2S1_RX 20 +#define MD_DMA_PRS_SPI2_RX 21 +#define MD_DMA_PRS_I2C1_RX 22 +#define MD_DMA_PRS_I2C2_RX 23 +#define MD_DMA_PRS_AES_OUT 24 +#define MD_DMA_PRS_ADC 25 +#define MD_DMA_PRS_SPI3_RX 29 +#define MD_DMA_PRS_KBCU 31 +#define MD_DMA_PRS_BS16T1_UP 32 +#define MD_DMA_PRS_AD16C4T1_CH1 33 +#define MD_DMA_PRS_AD16C4T1_CH2 34 +#define MD_DMA_PRS_AD16C4T1_CH3 35 +#define MD_DMA_PRS_AD16C4T1_CH4 36 +#define MD_DMA_PRS_AD16C4T1_UP 37 +#define MD_DMA_PRS_AD16C4T1_TRIG 38 +#define MD_DMA_PRS_AD16C4T1_COM 39 +#define MD_DMA_PRS_GP32C4T1_CH1 40 +#define MD_DMA_PRS_GP32C4T1_CH2 41 +#define MD_DMA_PRS_GP32C4T1_CH3 42 +#define MD_DMA_PRS_GP32C4T1_CH4 43 +#define MD_DMA_PRS_GP32C4T1_UP 44 +#define MD_DMA_PRS_GP32C4T1_TRIG 45 +#define MD_DMA_PRS_GP16C4T1_CH1 46 +#define MD_DMA_PRS_GP16C4T1_CH2 47 +#define MD_DMA_PRS_GP16C4T1_CH3 48 +#define MD_DMA_PRS_GP16C4T1_CH4 49 +#define MD_DMA_PRS_GP16C4T1_UP 50 +#define MD_DMA_PRS_GP16C4T1_TRIG 51 +#define MD_DMA_PRS_GP16C4T2_CH1 52 +#define MD_DMA_PRS_GP16C4T2_CH2 53 +#define MD_DMA_PRS_GP16C4T2_CH3 54 +#define MD_DMA_PRS_GP16C4T2_CH4 55 +#define MD_DMA_PRS_GP16C4T2_UP 56 +#define MD_DMA_PRS_GP16C4T2_TRIG 57 +#define MD_DMA_PRS_GP16C4T3_CH1 58 +#define MD_DMA_PRS_GP16C4T3_CH2 59 +#define MD_DMA_PRS_GP16C4T3_CH3 60 +#define MD_DMA_PRS_GP16C4T3_CH4 61 +#define MD_DMA_PRS_GP16C4T3_UP 62 +#define MD_DMA_PRS_GP16C4T3_TRIG 63 +#define MD_DMA_PRS_GP16C2T1_CH1 64 +#define MD_DMA_PRS_GP16C2T1_CH2 65 +#define MD_DMA_PRS_GP16C2T1_UP 66 +#define MD_DMA_PRS_GP16C2T1_TRIG 67 +#define MD_DMA_PRS_GP16C2T1_COM 68 +#define MD_DMA_PRS_GP16C2T2_CH1 70 +#define MD_DMA_PRS_GP16C2T2_CH2 71 +#define MD_DMA_PRS_GP16C2T2_UP 72 +#define MD_DMA_PRS_GP16C2T2_TRIG 73 +#define MD_DMA_PRS_GP16C2T2_COM 74 +#define MD_DMA_PRS_GP16C2T3_CH1 76 +#define MD_DMA_PRS_GP16C2T3_CH2 77 +#define MD_DMA_PRS_GP16C2T3_UP 78 +#define MD_DMA_PRS_GP16C2T3_TRIG 79 +#define MD_DMA_PRS_GP16C2T3_COM 80 +#define MD_DMA_PRS_GP16C2T4_CH1 82 +#define MD_DMA_PRS_GP16C2T4_CH2 83 +#define MD_DMA_PRS_GP16C2T4_UP 84 +#define MD_DMA_PRS_GP16C2T4_TRIG 85 +#define MD_DMA_PRS_GP16C2T4_COM 86 +#define MD_DMA_PRS_MEMORY 127 + +/* DMA destination address increment size*/ +#define MD_DMA_CHANNEL_CFG_DSTINC_BYTE (0U) +#define MD_DMA_CHANNEL_CFG_DSTINC_HALF_WORD (1U) +#define MD_DMA_CHANNEL_CFG_DSTINC_WORD (2U) +#define MD_DMA_CHANNEL_CFG_DSTINC_NO_INC (3U) + +/* DMA destination data size */ +#define MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_BYTE (0 ) +#define MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_HALF_WORD (1 ) +#define MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_WORD (2 ) + +/* DMA source address increment size*/ +#define MD_DMA_CHANNEL_CFG_SRCINC_BYTE (0 ) +#define MD_DMA_CHANNEL_CFG_SRCINC_HALF_WORD (1 ) +#define MD_DMA_CHANNEL_CFG_SRCINC_WORD (2 ) +#define MD_DMA_CHANNEL_CFG_SRCINC_NO_INC (3 ) + +/* DMA source data size */ +#define MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_BYTE (0 ) +#define MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_HALF_WORD (1 ) +#define MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_WORD (2 ) + +/* Number of times the DMA transfer every arbitration */ +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1 (0 ) +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_2 (1 ) +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_4 (2 ) +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_8 (3 ) +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_16 (4 ) +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_32 (5 ) +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_64 (6 ) +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_128 (7 ) +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_256 (8 ) +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_512 (9 ) +#define MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1024 (10) + +/* DMA mode */ +#define MD_DMA_CHANNEL_CFG_MODE_STOP (0 ) +#define MD_DMA_CHANNEL_CFG_MODE_BASIC (1 ) +#define MD_DMA_CHANNEL_CFG_MODE_AUTO (2 ) +#define MD_DMA_CHANNEL_CFG_MODE_PING_PONG (3 ) +#define MD_DMA_CHANNEL_CFG_MODE_MEMORY_PRIMARY (4 ) +#define MD_DMA_CHANNEL_CFG_MODE_MEMORY_ALTERNATE (5 ) +#define MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_PRIMARY (6 ) +#define MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_ALTERNATE (7 ) + +/* DMA type */ +#define MD_DMA_PRIMARY (0) +#define MD_DMA_ALTERNATE (1) + +/* DMA size */ +#define MD_DMA_CHANNEL_SIZE_BYTE (0) +#define MD_DMA_CHANNEL_SIZE_HALF_WORD (1) +#define MD_DMA_CHANNEL_SIZE_WORD (2) + + +/** + * @} MD_DMA_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_DMA_Public_Macros DMA Public Macros + * @{ + */ + +/** + * @brief GET DMA STATUS register value. + * @param DMAx DMA instance + * @retval DMA STATUS register value. + */ + +__STATIC_INLINE uint32_t md_dma_get_status(DMA_TypeDef *DMAx) +{ + return (uint32_t)(READ_REG(DMAx->STATUS)); +} + +/** + * @brief GET DMA number of channel. + * @param DMAx DMA instance + * @retval DMA available channel 0~12. + */ + +__STATIC_INLINE uint32_t md_dma_get_available_channel_number(DMA_TypeDef *DMAx) +{ + return (uint32_t)(READ_BIT(DMAx->STATUS, DMA_STATUS_CHNLS_MINUS1) >> DMA_STATUS_CHNLS_MINUS1_POSS); +} + +/** + * @brief GET DMA status. + * @param DMAx DMA instance + * @retval The current state of the state machine. + */ + +__STATIC_INLINE uint32_t md_dma_get_current_status(DMA_TypeDef *DMAx) +{ + return (uint32_t)(READ_BIT(DMAx->STATUS, DMA_STATUS_STATUS) >> DMA_STATUS_STATUS_POSS); +} + +/** + * @brief Indicates whether the DMAx is enabled. + * @param DMAx DMA instance + * @retval DMA master enable register value; State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_is_enabled(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->STATUS, DMA_STATUS_MASTER_ENABLE) == (DMA_STATUS_MASTER_ENABLE)); +} + +/** + * @brief DMA CFG setup. + * @param DMAx DMA instance + * @param value DMA configuration + * @retval None + */ + +__STATIC_INLINE void md_dma_set_configuration(DMA_TypeDef *DMAx, uint32_t value) +{ + WRITE_REG(DMAx->CFG, value); +} + +/** + * @brief DMA channel protect setup. + * @param DMAx DMA instance + * @param CHProtect Channel protect setup + * @retval None + */ + +__STATIC_INLINE void md_dma_set_channel_hport_control(DMA_TypeDef *DMAx, uint32_t CHProtect) +{ + MODIFY_REG(DMAx->CFG, DMA_CFG_CHNL_PROT_CTRL, (CHProtect << DMA_CFG_CHNL_PROT_CTRL_POSS)); +} + +/** + * @brief DMA enable. + * @param DMAx DMA instance + * @retval None + */ + +__STATIC_INLINE void md_dma_enable_master(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE); +} + +/** + * @brief DMA disable. + * @param DMAx DMA instance + * @retval None + */ + +__STATIC_INLINE void md_dma_disable_master(DMA_TypeDef *DMAx) +{ + CLEAR_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE); +} + +/** + * @brief GET DMA channel request status. + * @param DMAx DMA instance + * @retval Wait on request state + */ + +__STATIC_INLINE uint32_t md_dma_get_channel_wait_on_request(DMA_TypeDef *DMAx) +{ + return (uint32_t)(READ_BIT(DMAx->CHWAITSTATUS, DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS)); +} + +/** + * @brief DMA CHSWREQ setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_enable_soft_request(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHSWREQ, (1 << channel)); +} + +/** + * @brief DMA CHUSEBURSTSET setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_enable_burst_request(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHUSEBURSTSET, (1 << channel)); +} + +/** + * @brief GET DMA CHUSEBURSTSET register value. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA CHUSEBURSTSET register value; State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_is_enabled_burst_request(DMA_TypeDef *DMAx, uint32_t channel) +{ + return (READ_BIT(DMAx->CHUSEBURSTSET, (1 << channel)) == (1 << channel)); +} + +/** + * @brief DMA CHUSEBURSTCLR setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_disable_burst_request(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << channel)); +} + +/** + * @brief DMA CHREQMASKSET setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_disable_request(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHREQMASKSET, (1 << channel)); +} + +/** + * @brief GET DMA CHREQMASKSET register value. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA CHREQMASKSET register value; State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_is_enabled_request(DMA_TypeDef *DMAx, uint32_t channel) +{ + return ((READ_BIT(DMAx->CHREQMASKSET, (1 << channel)) != (1 << channel))); +} + +/** + * @brief DMA CHREQMASKCLR setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_enable_request(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHREQMASKCLR, (1 << channel)); +} + +/** + * @brief DMA CHENSET setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_enable_channel(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHENSET, (1 << channel)); +} + +/** + * @brief GET DMA CHENSET register value. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA CHENSET register value; State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_is_enabled_channel(DMA_TypeDef *DMAx, uint32_t channel) +{ + return (READ_BIT(DMAx->CHENSET, (1 << channel)) == (1 << channel)); +} + +/** + * @brief DMA CHENCLR setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_disable_channel(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHENCLR, (1 << channel)); +} + +/** + * @brief DMA CHPRIALTSET setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_enable_alternate_mode(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHPRIALTSET, (1 << channel)); +} + +/** + * @brief GET DMA CHPRIALTSET register value. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA CHPRIALTSET register value; State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_is_enabled_alternate_mode(DMA_TypeDef *DMAx, uint32_t channel) +{ + return (READ_BIT(DMAx->CHPRIALTSET, (1 << channel)) == (1 << channel)); +} + +/** + * @brief DMA CHPRIALTCLR setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_enable_primary_mode(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); +} + +/** + * @brief DMA CHPRSET setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_set_channel_priority(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHPRSET, (1 << channel)); +} + +/** + * @brief GET DMA CHPRSET register value. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA CHPRSET register value. State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_get_channel_priority(DMA_TypeDef *DMAx, uint32_t channel) +{ + return (READ_BIT(DMAx->CHPRSET, (1 << channel))); +} + +/** + * @brief DMA CHPRCLR setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_set_channel_priority_default(DMA_TypeDef *DMAx, uint32_t channel) +{ + WRITE_REG(DMAx->CHPRCLR, (1 << channel)); +} + +/** + * @brief DMA IER setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_enable_it_channel_done(DMA_TypeDef *DMAx, uint32_t channel) +{ + SET_BIT(DMAx->IER, (1 << channel)); +} + +/** + * @brief DMA IDR setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_disable_it_channel_done(DMA_TypeDef *DMAx, uint32_t channel) +{ + SET_BIT(DMAx->IDR, (1 << channel)); +} + +/** + * @brief GET DMA IVS register value. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA IVS register value. State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_is_enabled_it_channel_done(DMA_TypeDef *DMAx, uint32_t channel) +{ + return (READ_BIT(DMAx->IVS, (1 << channel)) == (1 << channel)); +} + +/** + * @brief GET DMA RIF register value. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA RIF register value. State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_is_active_flag_channel_done(DMA_TypeDef *DMAx, uint32_t channel) +{ + return (READ_BIT(DMAx->RIF, (1 << channel)) == (1 << channel)); +} + +/** + * @brief GET DMA IFM register value. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA IFM register value. State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_is_masked_it_channel_done(DMA_TypeDef *DMAx, uint32_t channel) +{ + return (READ_BIT(DMAx->IFM, (1 << channel)) == (1 << channel)); +} + +/** + * @brief DMA ICR setup. + * @param DMAx DMA instance + * @param channel The channel can be one of the following values: + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_clear_it_channel_done(DMA_TypeDef *DMAx, uint32_t channel) +{ + SET_BIT(DMAx->ICR, (1 << channel)); +} + +/** + * @brief DMA CH_SELCON setup. + * @param DMAx DMA instance + * @param value MISGSEL + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_set_request_peripherals(DMA_TypeDef *DMAx, uint32_t ch, uint32_t value) +{ + WRITE_REG(MD_DMA_SELCON_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA CH_SELCON register value. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMAx->CH_SELCON[ch].MISGSEL register value. + */ + +__STATIC_INLINE uint32_t md_dma_get_request_peripherals(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_REG(MD_DMA_SELCON_INDEX(DMAx, ch))); +} + +/** + * @brief DMA PRI_CH_CHANNEL_CFG.scr setup. + * @param DMAx DMA instance + * @param value PRI_CH_CHANNEL_CFG.scr + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_set_primary_channel_source_data_end_address(DMA_TypeDef *DMAx, uint32_t ch, uint32_t value) +{ + while (READ_REG(MD_DMA_PRI_SRC_DATA_END_INDEX(DMAx, ch) != value)) + WRITE_REG(MD_DMA_PRI_SRC_DATA_END_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA DMA PRI_CH_CHANNEL_CFG.scr register value. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA PRI_CH_CHANNEL_CFG.scr register value. + */ + +__STATIC_INLINE uint32_t md_dma_get_primary_channel_source_data_end_address(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_REG(MD_DMA_PRI_SRC_DATA_END_INDEX(DMAx, ch))); +} + +/** + * @brief DMA PRI_CH_CHANNEL_CFG.dst setup. + * @param DMAx DMA instance + * @param value PRI_CH_CHANNEL_CFG.dst + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_set_primary_channel_destination_data_end_address(DMA_TypeDef *DMAx, uint32_t ch, uint32_t value) +{ + while (READ_REG(MD_DMA_PRI_DST_DATA_END_INDEX(DMAx, ch) != value)) + WRITE_REG(MD_DMA_PRI_DST_DATA_END_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA PRI_CH_CHANNEL_CFG.dst register value. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA PRI_CH_CHANNEL_CFG.dst register value. + */ + +__STATIC_INLINE uint32_t md_dma_get_primary_channel_destination_data_end_address(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(MD_DMA_PRI_DST_DATA_END_INDEX(DMAx, ch)); +} +/** + * @brief DMA PRI_CH_CHANNEL_CFG.cfg.word setup. + * @param DMAx DMA instance + * @param value PRI_CH_CHANNEL_CFG.cfg.word + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_set_primary_channel_channel_configuration(DMA_TypeDef *DMAx, uint32_t ch, uint32_t value) +{ + while (READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch) != value)) + WRITE_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA PRI_CH_CHANNEL_CFG.cfg.word register value. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA PRI_CH_CHANNEL_CFG.cfg.word register value. + */ + +__STATIC_INLINE uint32_t md_dma_get_primary_channel_channel_configuration(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch))); +} + +/** + * @brief DMA channel destination increment size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param DstInc channel destination increment size. + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_NO_INC + * @retval None + */ + +__STATIC_INLINE void md_dma_set_primary_channel_destination_address_incremental(DMA_TypeDef *DMAx, uint32_t ch, uint32_t DstInc) +{ + uint32_t value; +// value = READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch) & ~(CHANNEL_CFG_DST_INC); + value = CLEAR_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_DST_INC); + value |= DstInc << CHANNEL_CFG_DST_INC_POSS; + + while (READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA channel destination increment size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_NO_INC + */ + +__STATIC_INLINE uint32_t md_dma_get_primary_channel_destination_address_incremental(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_DST_INC)) >> CHANNEL_CFG_DST_INC_POSS; +} + +/** + * @brief DMA channel destination data size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param DstSize channel destination data size. + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_WORD + * @retval None + */ + +__STATIC_INLINE void md_dma_set_primary_channel_destination_address_size(DMA_TypeDef *DMAx, uint32_t ch, uint32_t DstSize) +{ + uint32_t value; +// value = READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_DST_SIZE); + value = CLEAR_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_DST_SIZE); + value |= DstSize << CHANNEL_CFG_DST_SIZE_POSS; + + while (READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA channel destination data size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_WORD + */ + +__STATIC_INLINE uint32_t md_dma_get_primary_channel_destination_address_size(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_DST_SIZE)) >> CHANNEL_CFG_DST_SIZE_POSS; +} + +/** + * @brief DMA channel source increment size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param SrcInc channel source increment size. + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_NO_INC + * @retval None + */ + +__STATIC_INLINE void md_dma_set_primary_channel_source_address_incremental(DMA_TypeDef *DMAx, uint32_t ch, uint32_t SrcInc) +{ + uint32_t value; +// value = READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_SRC_INC); + value = CLEAR_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_SRC_INC); + value |= SrcInc << CHANNEL_CFG_SRC_INC_POSS; + + while (READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA channel source increment size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_NO_INC + */ + +__STATIC_INLINE uint32_t md_dma_get_primary_channel_source_address_incremental(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_SRC_INC)) >> CHANNEL_CFG_SRC_INC_POSS; +} + +/** + * @brief DMA channel source data size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param SrcSize channel source data size. + @arg @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_WORD + * @retval None + */ + +__STATIC_INLINE void md_dma_set_primary_channel_source_address_size(DMA_TypeDef *DMAx, uint32_t ch, uint32_t SrcSize) +{ + uint32_t value; +// value = READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_SRC_SIZE); + value = CLEAR_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_SRC_SIZE); + value |= SrcSize << CHANNEL_CFG_SRC_SIZE_POSS; + + while (READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA channel source data size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_WORD + */ + +__STATIC_INLINE uint32_t md_dma_get_primary_channel_source_address_size(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_SRC_SIZE)) >> CHANNEL_CFG_SRC_SIZE_POSS; +} + +/** + * @brief Number of times the DMA channel 0 transfer Before the controller re-arbitrates. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param times Number of times the DMA channel transfer Before the controller re-arbitrates. + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_2 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_4 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_8 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_16 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_32 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_64 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_128 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_256 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_512 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1024 + * @retval None + */ + +__STATIC_INLINE void md_dma_set_primary_channel_r_power(DMA_TypeDef *DMAx, uint32_t ch, uint32_t times) +{ + uint32_t value; +// value = READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_R_POWER); + value = CLEAR_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_R_POWER); + value |= times << CHANNEL_CFG_R_POWER_POSS; + + while (READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET Number of times the DMA channel transfer Before the controller re-arbitrates. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_2 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_4 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_8 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_16 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_32 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_64 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_128 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_256 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_512 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1024 + */ + +__STATIC_INLINE uint32_t md_dma_get_primary_channel_r_power(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_R_POWER)) >> CHANNEL_CFG_R_POWER_POSS; +} + +/** + * @brief Number of times the DMA channel transfer. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param times Number of times the DMA channel transfer. + * @arg Max Value 1023 + * @arg Min Value 0 + * @retval None + */ + +__STATIC_INLINE void md_dma_set_primary_channel_transfer_number(DMA_TypeDef *DMAx, uint32_t ch, uint32_t times) +{ + uint32_t value; +// value = READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_N_MINUS_1); + value = CLEAR_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_N_MINUS_1); + value |= times << CHANNEL_CFG_N_MINUS_1_POSS; + + while (READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET Number of times the DMA channel transfer. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval Number of times the DMA channel transfer. + * @arg Max Value 1023 + * @arg Min Value 0 + */ + +__STATIC_INLINE uint32_t md_dma_get_primary_channel_transfer_number(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_N_MINUS_1) >> CHANNEL_CFG_N_MINUS_1_POSS); +} + +/** + * @brief DMA channel set CHNL_USEBURST_SET[C] enable. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_enable_primary_channel_next_burst_request(DMA_TypeDef *DMAx, uint32_t ch) +{ + uint32_t value; +// value = READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_NEXT_USEBURST); + value = CLEAR_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_NEXT_USEBURST); + value |= 1 << CHANNEL_CFG_NEXT_USEBURST_POS; + + while (READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief DMA channel set CHNL_USEBURST_SET[C] disable. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_disable_primary_channel_next_burst_request(DMA_TypeDef *DMAx, uint32_t ch) +{ + uint32_t value; +// value = READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_NEXT_USEBURST); + value = CLEAR_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_NEXT_USEBURST); + value &= ~(1 << CHANNEL_CFG_NEXT_USEBURST_POS); + + while (READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief Indicates whether the DMA channel set CHNL_USEBURST_SET[C] is enabled. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_is_enabled_primary_channel_next_burst_request(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (READ_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_NEXT_USEBURST) == (CHANNEL_CFG_NEXT_USEBURST)); +} + +/** + * @brief DMA channel mode setup. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param mode DMA channel mode. + @arg @ref MD_DMA_CHANNEL_CFG_MODE_STOP + @arg @ref MD_DMA_CHANNEL_CFG_MODE_BASIC + @arg @ref MD_DMA_CHANNEL_CFG_MODE_AUTO + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PING_PONG + @arg @ref MD_DMA_CHANNEL_CFG_MODE_MEMORY_PRIMARY + @arg @ref MD_DMA_CHANNEL_CFG_MODE_MEMORY_ALTERNATE + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_PRIMARY + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_ALTERNATE + * @retval None + */ + +__STATIC_INLINE void md_dma_set_primary_channel_cycle_mode(DMA_TypeDef *DMAx, uint32_t ch, uint32_t mode) +{ + uint32_t value; +// value = READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_CYCLE_CTRL); + value = CLEAR_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_CYCLE_CTRL); + value |= mode << CHANNEL_CFG_CYCLE_CTRL_POSS; + + while (READ_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA channel mode. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_MODE_STOP + @arg @ref MD_DMA_CHANNEL_CFG_MODE_BASIC + @arg @ref MD_DMA_CHANNEL_CFG_MODE_AUTO + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PING_PONG + @arg @ref MD_DMA_CHANNEL_CFG_MODE_MEMORY_PRIMARY + @arg @ref MD_DMA_CHANNEL_CFG_MODE_MEMORY_ALTERNATE + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_PRIMARY + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_ALTERNATE + */ + +__STATIC_INLINE uint32_t md_dma_get_primary_channel_cycle_mode(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_PRI_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_CYCLE_CTRL)) >> CHANNEL_CFG_CYCLE_CTRL_POSS; +} + + +/** + * @brief DMA ALT_CH_CHANNEL_CFG.scr setup. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param value ALT_CH_CHANNEL_CFG.scr + * @retval None + */ + +__STATIC_INLINE void md_dma_set_alternate_channel_source_data_end_address(DMA_TypeDef *DMAx, uint32_t ch, uint32_t value) +{ + while (READ_REG(MD_DMA_ALT_SRC_DATA_END_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_SRC_DATA_END_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA DMA ALT_CH_CHANNEL_CFG.scr register value. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA DMA ALT_CH_CHANNEL_CFG.scr register value. + */ + +__STATIC_INLINE uint32_t md_dma_get_alternate_channel_source_data_end_address(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_REG(MD_DMA_ALT_SRC_DATA_END_INDEX(DMAx, ch))); +} + +/** + * @brief DMA ALT_CH_CHANNEL_CFG.dst setup. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param value ALT_CH_CHANNEL_CFG.dst + * @retval None + */ + +__STATIC_INLINE void md_dma_set_alternate_channel_destination_data_end_address(DMA_TypeDef *DMAx, uint32_t ch, uint32_t value) +{ + while (READ_REG(MD_DMA_ALT_DST_DATA_END_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_DST_DATA_END_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA ALT_CH_CHANNEL_CFG.dst register value. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA ALT_CH_CHANNEL_CFG.dst register value. + */ + +__STATIC_INLINE uint32_t md_dma_get_alternate_channel_destination_data_end_address(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_REG(MD_DMA_ALT_DST_DATA_END_INDEX(DMAx, ch))); +} + +/** + * @brief DMA ALT_CH_CHANNEL_CFG.cfg.word setup. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param value ALT_CH_CHANNEL_CFG.cfg.word + * @retval None + */ + +__STATIC_INLINE void md_dma_set_alternate_channel_channel_configuration(DMA_TypeDef *DMAx, uint32_t ch, uint32_t value) +{ + while (READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA ALT_CH_CHANNEL_CFG.cfg.word register value. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval DMA ALT_CH_CHANNEL_CFG.cfg.word register value. + */ + +__STATIC_INLINE uint32_t md_dma_get_alternate_channel_channel_configuration(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch))); +} + +/** + * @brief DMA channel destination increment size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param DstInc channel destination increment size. + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_NO_INC + * @retval None + */ + +__STATIC_INLINE void md_dma_set_alternate_channel_destination_address_incremental(DMA_TypeDef *DMAx, uint32_t ch, uint32_t DstInc) +{ + uint32_t value; +// value = READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_DST_INC); + value = CLEAR_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_DST_INC); + value |= DstInc << CHANNEL_CFG_DST_INC_POSS; + + while (READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA channel destination increment size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTINC_NO_INC + */ + +__STATIC_INLINE uint32_t md_dma_get_alternate_channel_destination_address_incremental(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_DST_INC)) >> CHANNEL_CFG_DST_INC_POSS; +} + +/** + * @brief DMA channel destination data size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param DstSize channel destination data size. + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_WORD + * @retval None + */ + +__STATIC_INLINE void md_dma_set_alternate_channel_destination_address_size(DMA_TypeDef *DMAx, uint32_t ch, uint32_t DstSize) +{ + uint32_t value; +// value = READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_DST_SIZE); + value = CLEAR_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_DST_SIZE); + value |= DstSize << CHANNEL_CFG_DST_SIZE_POSS; + + while (READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA channel destination data size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_DSTDATA_SIZE_WORD + */ + +__STATIC_INLINE uint32_t md_dma_get_alternate_channel_destination_address_size(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_DST_SIZE)) >> CHANNEL_CFG_DST_SIZE_POSS; +} + +/** + * @brief DMA channel source increment size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param SrcInc channel source increment size. + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_NO_INC + * @retval None + */ + +__STATIC_INLINE void md_dma_set_alternate_channel_source_address_incremental(DMA_TypeDef *DMAx, uint32_t ch, uint32_t SrcInc) +{ + uint32_t value; +// value = READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_SRC_INC); + value = CLEAR_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_SRC_INC); + value |= SrcInc << CHANNEL_CFG_SRC_INC_POSS; + + while (READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA channel source increment size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCINC_NO_INC + */ + +__STATIC_INLINE uint32_t md_dma_get_alternate_channel_source_address_incremental(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_SRC_INC)) >> CHANNEL_CFG_SRC_INC_POSS; +} + +/** + * @brief DMA channel source data size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param SrcSize channel source data size. + @arg @ref MD_DMA_CHANNEL_SRCDATA_SIZE_BYTE + @arg @ref MD_DMA_CHANNEL_SRCDATA_SIZE_HALF_WORD + @arg @ref MD_DMA_CHANNEL_SRCDATA_SIZE_WORD + * @retval None + */ + +__STATIC_INLINE void md_dma_set_alternate_channel_source_address_size(DMA_TypeDef *DMAx, uint32_t ch, uint32_t SrcSize) +{ + uint32_t value; +// value = READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_SRC_SIZE); + value = CLEAR_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_SRC_SIZE); + value |= SrcSize << CHANNEL_CFG_SRC_SIZE_POSS; + + while (READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA channel source data size. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_BYTE + @arg @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_HALF_WORD + @arg @ref MD_DMA_CHANNEL_CFG_SRCDATA_SIZE_WORD + */ + +__STATIC_INLINE uint32_t md_dma_get_alternate_channel_source_address_size(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_SRC_SIZE)) >> CHANNEL_CFG_SRC_SIZE_POSS; +} + +/** + * @brief Number of times the DMA channel 0 transfer Before the controller re-arbitrates. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param times Number of times the DMA channel transfer Before the controller re-arbitrates. + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_2 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_4 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_8 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_16 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_32 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_64 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_128 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_256 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_512 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1024 + * @retval None + */ + +__STATIC_INLINE void md_dma_set_alternate_channel_r_power(DMA_TypeDef *DMAx, uint32_t ch, uint32_t times) +{ + uint32_t value; +// value = READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_R_POWER); + value = CLEAR_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_R_POWER); + value |= times << CHANNEL_CFG_R_POWER_POSS; + + while (READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET Number of times the DMA channel transfer Before the controller re-arbitrates. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_2 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_4 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_8 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_16 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_32 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_64 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_128 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_256 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_512 + @arg @ref MD_DMA_CHANNEL_CFG_RPOWER_SIZE_1024 + */ + +__STATIC_INLINE uint32_t md_dma_get_alternate_channel_r_power(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_R_POWER)) >> CHANNEL_CFG_R_POWER_POSS; +} + +/** + * @brief Number of times the DMA channel transfer. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param Number of times the DMA channel transfer. + * @arg Max Value 1023 + * @arg Min Value 0 + * @retval None + */ + +__STATIC_INLINE void md_dma_set_alternate_channel_transfer_number(DMA_TypeDef *DMAx, uint32_t ch, uint32_t times) +{ + uint32_t value; +// value = READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_N_MINUS_1); + value = CLEAR_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_N_MINUS_1); + value |= times << CHANNEL_CFG_N_MINUS_1_POSS; + + while (READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET Number of times the DMA channel transfer. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval Number of times the DMA channel transfer. + * @arg Max Value 1023 + * @arg Min Value 0 + */ + +__STATIC_INLINE uint32_t md_dma_get_alternate_channel_transfer_number(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_N_MINUS_1) >> CHANNEL_CFG_N_MINUS_1_POSS); +} + +/** + * @brief DMA channel set CHNL_USEBURST_SET[C] enable. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_enable_alternate_channel_next_burst_request(DMA_TypeDef *DMAx, uint32_t ch) +{ + uint32_t value; +// value = READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_NEXT_USEBURST); + value = CLEAR_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_NEXT_USEBURST); + value |= 1 << CHANNEL_CFG_NEXT_USEBURST_POS; + + while (READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief DMA channel set CHNL_USEBURST_SET[C] disable. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval None + */ + +__STATIC_INLINE void md_dma_disable_alternate_channel_next_burst_request(DMA_TypeDef *DMAx, uint32_t ch) +{ + uint32_t value; +// value = READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_NEXT_USEBURST); + value = CLEAR_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_NEXT_USEBURST); + value &= ~(1 << CHANNEL_CFG_NEXT_USEBURST_POS); + + while (READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief Indicates whether the DMA channel set CHNL_USEBURST_SET[C] is enabled. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_dma_is_enabled_alternate_channel_next_burst_request(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (READ_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_NEXT_USEBURST) == (CHANNEL_CFG_NEXT_USEBURST)); +} + +/** + * @brief DMA channel mode setup. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @param mode DMA channel mode. + @arg @ref MD_DMA_CHANNEL_CFG_MODE_STOP + @arg @ref MD_DMA_CHANNEL_CFG_MODE_BASIC + @arg @ref MD_DMA_CHANNEL_CFG_MODE_AUTO + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PING_PONG + @arg @ref MD_DMA_CHANNEL_CFG_MODE_MEMORY_ALTMARY + @arg @ref MD_DMA_CHANNEL_CFG_MODE_MEMORY_ALTERNATE + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_ALTMARY + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_ALTERNATE + * @retval None + */ + +__STATIC_INLINE void md_dma_set_alternate_channel_cycle_mode(DMA_TypeDef *DMAx, uint32_t ch, uint32_t mode) +{ + uint32_t value; +// value = READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) & ~(CHANNEL_CFG_CYCLE_CTRL); + value = CLEAR_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_CYCLE_CTRL); + value |= mode << CHANNEL_CFG_CYCLE_CTRL_POSS; + + while (READ_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch)) != value) + WRITE_REG(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), value); +} + +/** + * @brief GET DMA channel mode. + * @param DMAx DMA instance + * @param ch Channel select + @arg @ref MD_DMA_CHANNEL0 + @arg @ref MD_DMA_CHANNEL1 + @arg @ref MD_DMA_CHANNEL2 + @arg @ref MD_DMA_CHANNEL3 + @arg @ref MD_DMA_CHANNEL4 + @arg @ref MD_DMA_CHANNEL5 + * @retval The retval can be one of the following values: + @arg @ref MD_DMA_CHANNEL_CFG_MODE_STOP + @arg @ref MD_DMA_CHANNEL_CFG_MODE_BASIC + @arg @ref MD_DMA_CHANNEL_CFG_MODE_AUTO + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PING_PONG + @arg @ref MD_DMA_CHANNEL_CFG_MODE_MEMORY_ALTMARY + @arg @ref MD_DMA_CHANNEL_CFG_MODE_MEMORY_ALTERNATE + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_ALTMARY + @arg @ref MD_DMA_CHANNEL_CFG_MODE_PERIPHERAL_ALTERNATE + */ + +__STATIC_INLINE uint32_t md_dma_get_alternate_channel_cycle_mode(DMA_TypeDef *DMAx, uint32_t ch) +{ + return (uint32_t)(READ_BIT(MD_DMA_ALT_CHANNEL_CFG_INDEX(DMAx, ch), CHANNEL_CFG_CYCLE_CTRL)) >> CHANNEL_CFG_CYCLE_CTRL_POSS; +} + + +/** + * @} MD_DMA_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_DMA_Public_Functions DMA Public Functions + * @{ + */ + +/** @defgroup MD_DMA_Basic_Configuration Basic Configuration + * @{ + */ + +/** + * @} MD_DMA_Basic_Configuration + */ + + +/** + * @} MD_DMA_Public_Functions + */ +void md_dma_set_primary_channel_destination_data_start_address_and_length(DMA_TypeDef *DMAx, uint32_t ch, uint32_t addr, uint32_t len, uint32_t size); +void md_dma_set_primary_channel_source_data_start_address_and_length(DMA_TypeDef *DMAx, uint32_t ch, uint32_t addr, uint32_t len, uint32_t size); +uint32_t md_dma_set_channel_data_start_address_and_length(uint32_t addr, uint32_t len, uint32_t size); +void md_dma_init(DMA_TypeDef *DMAx, md_dma_init_typedef DMAx_init); +#endif + +/** + * @} DMA + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_exti.h b/os/common/ext/CMSIS/ES32/FS026/md/md_exti.h new file mode 100644 index 00000000000..ab0c706e4d5 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_exti.h @@ -0,0 +1,1699 @@ +/********************************************************************************** + * + * @file md_exti.h + * @brief header file of md_exti.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 14 Dec 2021 Ginger Modify function instructions + * 21 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_EXTI_H__ +#define __MD_EXTI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_EXTI EXTI + * @brief EXTI micro driver + * @{ + */ + + +/** @defgroup MD_EXTI_Public_Macros EXTI Public Macros + * @{ + */ + +#define MD_EXTI_PORT_GPIOA (0x00000000UL) /*!< @brief Select GPIOA for EXTIx */ +#define MD_EXTI_PORT_GPIOB (0x00000001UL) /*!< @brief Select GPIOB for EXTIx */ +#define MD_EXTI_PORT_GPIOC (0x00000002UL) /*!< @brief Select GPIOC for EXTIx */ +#define MD_EXTI_PORT_GPIOD (0x00000003UL) /*!< @brief Select GPIOD for EXTIx */ + +#define MD_EXTI_GPIO0 (1<<0) /*!< @brief Select GPIO0 for EXTIx */ +#define MD_EXTI_GPIO1 (1<<1) /*!< @brief Select GPIO1 for EXTIx */ +#define MD_EXTI_GPIO2 (1<<2) /*!< @brief Select GPIO2 for EXTIx */ +#define MD_EXTI_GPIO3 (1<<3) /*!< @brief Select GPIO3 for EXTIx */ +#define MD_EXTI_GPIO4 (1<<4) /*!< @brief Select GPIO4 for EXTIx */ +#define MD_EXTI_GPIO5 (1<<5) /*!< @brief Select GPIO5 for EXTIx */ +#define MD_EXTI_GPIO6 (1<<6) /*!< @brief Select GPIO6 for EXTIx */ +#define MD_EXTI_GPIO7 (1<<7) /*!< @brief Select GPIO7 for EXTIx */ +#define MD_EXTI_GPIO8 (1<<8) /*!< @brief Select GPIO0 for EXTIx */ +#define MD_EXTI_GPIO9 (1<<9) /*!< @brief Select GPIO1 for EXTIx */ +#define MD_EXTI_GPIO10 (1<<10) /*!< @brief Select GPIO2 for EXTIx */ +#define MD_EXTI_GPIO11 (1<<11) /*!< @brief Select GPIO3 for EXTIx */ +#define MD_EXTI_GPIO12 (1<<12) /*!< @brief Select GPIO4 for EXTIx */ +#define MD_EXTI_GPIO13 (1<<13) /*!< @brief Select GPIO5 for EXTIx */ +#define MD_EXTI_GPIO14 (1<<14) /*!< @brief Select GPIO6 for EXTIx */ +#define MD_EXTI_GPIO15 (1<<15) /*!< @brief Select GPIO7 for EXTIx */ + +#define MD_EXTI_PIN_GPIO0 (0) /*!< @brief Select GPIO0 for EXTIx */ +#define MD_EXTI_PIN_GPIO1 (4) /*!< @brief Select GPIO1 for EXTIx */ +#define MD_EXTI_PIN_GPIO2 (8) /*!< @brief Select GPIO2 for EXTIx */ +#define MD_EXTI_PIN_GPIO3 (12) /*!< @brief Select GPIO3 for EXTIx */ +#define MD_EXTI_PIN_GPIO4 (16) /*!< @brief Select GPIO4 for EXTIx */ +#define MD_EXTI_PIN_GPIO5 (20) /*!< @brief Select GPIO5 for EXTIx */ +#define MD_EXTI_PIN_GPIO6 (24) /*!< @brief Select GPIO6 for EXTIx */ +#define MD_EXTI_PIN_GPIO7 (28) /*!< @brief Select GPIO7 for EXTIx */ + +#define MD_EXTI_PIN_GPIO8 (0) /*!< @brief Select GPIO8 for EXTIx */ +#define MD_EXTI_PIN_GPIO9 (4) /*!< @brief Select GPIO9 for EXTIx */ +#define MD_EXTI_PIN_GPIO10 (8) /*!< @brief Select GPIO10 for EXTIx */ +#define MD_EXTI_PIN_GPIO11 (12) /*!< @brief Select GPIO11 for EXTIx */ +#define MD_EXTI_PIN_GPIO12 (16) /*!< @brief Select GPIO12 for EXTIx */ +#define MD_EXTI_PIN_GPIO13 (20) /*!< @brief Select GPIO13 for EXTIx */ +#define MD_EXTI_PIN_GPIO14 (24) /*!< @brief Select GPIO14 for EXTIx */ +#define MD_EXTI_PIN_GPIO15 (28) /*!< @brief Select GPIO15 for EXTIx */ + +#define MD_EXTI_GPIOA0 (0 << MD_EXTI_PIN_GPIO0) +#define MD_EXTI_GPIOA1 (0 << MD_EXTI_PIN_GPIO1) +#define MD_EXTI_GPIOA2 (0 << MD_EXTI_PIN_GPIO2) +#define MD_EXTI_GPIOA3 (0 << MD_EXTI_PIN_GPIO3) +#define MD_EXTI_GPIOA4 (0 << MD_EXTI_PIN_GPIO4) +#define MD_EXTI_GPIOA5 (0 << MD_EXTI_PIN_GPIO5) +#define MD_EXTI_GPIOA6 (0 << MD_EXTI_PIN_GPIO6) +#define MD_EXTI_GPIOA7 (0 << MD_EXTI_PIN_GPIO7) +#define MD_EXTI_GPIOA8 (0 << MD_EXTI_PIN_GPIO8) +#define MD_EXTI_GPIOA9 (0 << MD_EXTI_PIN_GPIO9) +#define MD_EXTI_GPIOA10 (0 << MD_EXTI_PIN_GPIO10) +#define MD_EXTI_GPIOA11 (0 << MD_EXTI_PIN_GPIO11) +#define MD_EXTI_GPIOA12 (0 << MD_EXTI_PIN_GPIO12) +#define MD_EXTI_GPIOA13 (0 << MD_EXTI_PIN_GPIO13) +#define MD_EXTI_GPIOA14 (0 << MD_EXTI_PIN_GPIO14) +#define MD_EXTI_GPIOA15 (0 << MD_EXTI_PIN_GPIO15) + +#define MD_EXTI_GPIOB0 (1 << MD_EXTI_PIN_GPIO0) +#define MD_EXTI_GPIOB1 (1 << MD_EXTI_PIN_GPIO1) +#define MD_EXTI_GPIOB2 (1 << MD_EXTI_PIN_GPIO2) +#define MD_EXTI_GPIOB3 (1 << MD_EXTI_PIN_GPIO3) +#define MD_EXTI_GPIOB4 (1 << MD_EXTI_PIN_GPIO4) +#define MD_EXTI_GPIOB5 (1 << MD_EXTI_PIN_GPIO5) +#define MD_EXTI_GPIOB6 (1 << MD_EXTI_PIN_GPIO6) +#define MD_EXTI_GPIOB7 (1 << MD_EXTI_PIN_GPIO7) +#define MD_EXTI_GPIOB8 (1 << MD_EXTI_PIN_GPIO8) +#define MD_EXTI_GPIOB9 (1 << MD_EXTI_PIN_GPIO9) +#define MD_EXTI_GPIOB10 (1 << MD_EXTI_PIN_GPIO10) +#define MD_EXTI_GPIOB11 (1 << MD_EXTI_PIN_GPIO11) +#define MD_EXTI_GPIOB12 (1 << MD_EXTI_PIN_GPIO12) +#define MD_EXTI_GPIOB13 (1 << MD_EXTI_PIN_GPIO13) +#define MD_EXTI_GPIOB14 (1 << MD_EXTI_PIN_GPIO14) +#define MD_EXTI_GPIOB15 (1 << MD_EXTI_PIN_GPIO15) + +#define MD_EXTI_GPIOC0 (2 << MD_EXTI_PIN_GPIO0) +#define MD_EXTI_GPIOC1 (2 << MD_EXTI_PIN_GPIO1) +#define MD_EXTI_GPIOC2 (2 << MD_EXTI_PIN_GPIO2) +#define MD_EXTI_GPIOC3 (2 << MD_EXTI_PIN_GPIO3) +#define MD_EXTI_GPIOC4 (2 << MD_EXTI_PIN_GPIO4) +#define MD_EXTI_GPIOC5 (2 << MD_EXTI_PIN_GPIO5) +#define MD_EXTI_GPIOC6 (2 << MD_EXTI_PIN_GPIO6) +#define MD_EXTI_GPIOC7 (2 << MD_EXTI_PIN_GPIO7) +#define MD_EXTI_GPIOC8 (2 << MD_EXTI_PIN_GPIO8) +#define MD_EXTI_GPIOC9 (2 << MD_EXTI_PIN_GPIO9) +#define MD_EXTI_GPIOC10 (2 << MD_EXTI_PIN_GPIO10) +#define MD_EXTI_GPIOC11 (2 << MD_EXTI_PIN_GPIO11) +#define MD_EXTI_GPIOC12 (2 << MD_EXTI_PIN_GPIO12) +#define MD_EXTI_GPIOC13 (2 << MD_EXTI_PIN_GPIO13) +#define MD_EXTI_GPIOC14 (2 << MD_EXTI_PIN_GPIO14) +#define MD_EXTI_GPIOC15 (2 << MD_EXTI_PIN_GPIO15) + +#define MD_EXTI_GPIOD0 (3 << MD_EXTI_PIN_GPIO0) +#define MD_EXTI_GPIOD1 (3 << MD_EXTI_PIN_GPIO1) +#define MD_EXTI_GPIOD2 (3 << MD_EXTI_PIN_GPIO2) +#define MD_EXTI_GPIOD3 (3 << MD_EXTI_PIN_GPIO3) +#define MD_EXTI_GPIOD4 (3 << MD_EXTI_PIN_GPIO4) +#define MD_EXTI_GPIOD5 (3 << MD_EXTI_PIN_GPIO5) +#define MD_EXTI_GPIOD6 (3 << MD_EXTI_PIN_GPIO6) +#define MD_EXTI_GPIOD7 (3 << MD_EXTI_PIN_GPIO7) +#define MD_EXTI_GPIOD8 (3 << MD_EXTI_PIN_GPIO8) +#define MD_EXTI_GPIOD9 (3 << MD_EXTI_PIN_GPIO9) +#define MD_EXTI_GPIOD10 (3 << MD_EXTI_PIN_GPIO10) +#define MD_EXTI_GPIOD11 (3 << MD_EXTI_PIN_GPIO11) +#define MD_EXTI_GPIOD12 (3 << MD_EXTI_PIN_GPIO12) +#define MD_EXTI_GPIOD13 (3 << MD_EXTI_PIN_GPIO13) +#define MD_EXTI_GPIOD14 (3 << MD_EXTI_PIN_GPIO14) +#define MD_EXTI_GPIOD15 (3 << MD_EXTI_PIN_GPIO15) + +#define MD_EXTI_EVENT_GPIO0 (1<<0) /*!< @brief Select GPIO0 for EXTIx */ +#define MD_EXTI_EVENT_GPIO1 (1<<1) /*!< @brief Select GPIO1 for EXTIx */ +#define MD_EXTI_EVENT_GPIO2 (1<<2) /*!< @brief Select GPIO2 for EXTIx */ +#define MD_EXTI_EVENT_GPIO3 (1<<3) /*!< @brief Select GPIO3 for EXTIx */ +#define MD_EXTI_EVENT_GPIO4 (1<<4) /*!< @brief Select GPIO4 for EXTIx */ +#define MD_EXTI_EVENT_GPIO5 (1<<5) /*!< @brief Select GPIO5 for EXTIx */ +#define MD_EXTI_EVENT_GPIO6 (1<<6) /*!< @brief Select GPIO6 for EXTIx */ +#define MD_EXTI_EVENT_GPIO7 (1<<7) /*!< @brief Select GPIO7 for EXTIx */ +#define MD_EXTI_EVENT_GPIO8 (1<<8) /*!< @brief Select GPIO8 for EXTIx */ +#define MD_EXTI_EVENT_GPIO9 (1<<9) /*!< @brief Select GPIO9 for EXTIx */ +#define MD_EXTI_EVENT_GPIO10 (1<<10) /*!< @brief Select GPIO10 for EXTIx */ +#define MD_EXTI_EVENT_GPIO11 (1<<11) /*!< @brief Select GPIO11 for EXTIx */ +#define MD_EXTI_EVENT_GPIO12 (1<<12) /*!< @brief Select GPIO12 for EXTIx */ +#define MD_EXTI_EVENT_GPIO13 (1<<13) /*!< @brief Select GPIO13 for EXTIx */ +#define MD_EXTI_EVENT_GPIO14 (1<<14) /*!< @brief Select GPIO14 for EXTIx */ +#define MD_EXTI_EVENT_GPIO15 (1<<15) /*!< @brief Select GPIO15 for EXTIx */ +#define MD_EXTI_EVENT_CMP1 (1<<16) /*!< @brief Select CMP1 for EXTIx */ +#define MD_EXTI_EVENT_CMP2 (1<<17) /*!< @brief Select CMP2 for EXTIx */ +#define MD_EXTI_EVENT_LVD (1<<20) /*!< @brief Select LVD for EXTIx */ +#define MD_EXTI_EVENT_WAKEUP (1<<21) /*!< @brief Select WAKEUP for EXTIx */ + +#define MD_EXTI_DEBOUNCECOUNT_IMMEDIATELY 0U +#define MD_EXTI_DEBOUNCECOUNT_2_TIMES 1U +#define MD_EXTI_DEBOUNCECOUNT_3_TIMES 2U +#define MD_EXTI_DEBOUNCECOUNT_4_TIMES 3U +#define MD_EXTI_DEBOUNCECOUNT_5_TIMES 4U +#define MD_EXTI_DEBOUNCECOUNT_6_TIMES 5U +#define MD_EXTI_DEBOUNCECOUNT_7_TIMES 6U +#define MD_EXTI_DEBOUNCECOUNT_8_TIMES 7U + +/** +* @} +*/ + +/** @defgroup MD_EXTI_Public_Functions EXTI Public Functions + * @{ + */ + +/** @defgroup MD_EXTI_Public_Functions_Group2 IER + * @{ + */ + +/** + * @brief Enable interrupt on line + * @param exti EXTI Instance + * @param value The value write in EXTI->IER + * @retval None + */ +__STATIC_INLINE void md_exti_set_ier(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->IER, value); +} + +/** + * @brief Enable Wake Up interrupt + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_it_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_WAKEUP); +} + +/** + * @brief Enable Low Power Detector (LVD) interrupt. + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_it_low_power_detector(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_LVD); +} + +/** + * @brief Enable Comparator2 (CMP2) interrupt. + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_it_comparator2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_CMP2); +} + +/** + * @brief Enable Comparator1 (CMP1) interrupt. + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_it_comparator1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_CMP1); +} + +/** + * @brief Enable GPIOy interrupt. + * @param exti EXTI Instance + * @param gpioy(gpio0~gpio15) The value write in EXTI->IER + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + * @retval None + */ +__STATIC_INLINE void md_exti_enable_it_gpio_pin(EXTI_TypeDef *exti, uint32_t gpioy) +{ + SET_BIT(exti->IER, gpioy); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group3 IDR + * @{ + */ +/** + * @brief Disable interrupt on line + * @param exti EXTI Instance + * @param value The value write in EXTI->IDR + * @retval None + */ +__STATIC_INLINE void md_exti_set_idr(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->IDR, value); +} + +/** + * @brief Disable Wake Up interrupt + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_it_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_WAKEUP); +} + +/** + * @brief Disable Low Power Detector (LVD) interrupt. + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_it_low_power_detector(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_LVD); +} + +/** + * @brief Disable Comparator2 (CMP2) interrupt. + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_it_comparator2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_CMP2); +} + +/** + * @brief Disable Comparator1 (CMP1) interrupt. + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_it_comparator1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_CMP1); +} + +/** + * @brief Disable GPIOy interrupt. + * @param exti EXTI Instance + * @param gpioy(gpio0~gpio15) The value write in EXTI->IDR + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + * @retval None + */ +__STATIC_INLINE void md_exti_disable_it_gpio_pin(EXTI_TypeDef *exti, uint32_t gpioy) +{ + SET_BIT(exti->IDR, gpioy); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group4 IVS + * @{ + */ +/** + * @brief Interrupt Valid Status on line + * @param exti EXTI Instance + * @retval EXTI->IVS value + */ +__STATIC_INLINE uint32_t md_exti_get_ivs(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->IVS)); +} + +/** + * @brief Wake Up interrupt enabled state. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_it_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_WAKEUP) == (EXTI_IVS_WAKEUP)); +} + +/** + * @brief Low Power Detector (LVD) interrupt enable state. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_it_low_power_detector(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_LVD) == (EXTI_IVS_LVD)); +} + +/** + * @brief Comparator2 (CMP2) interrupt enable state. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_it_comparator2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_CMP2) == (EXTI_IVS_CMP2)); +} + +/** + * @brief Comparator1 (CMP1) interrupt enable state. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_it_comparator1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_CMP1) == (EXTI_IVS_CMP1)); +} + +/** + * @brief GPIOy interrupt. (y=0...15) Interrupt enable state. + * @param exti EXTI Instance + * @param gpioy(gpio0~gpio15) The value Read in EXTI->IVS + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_it_gpio_pin(EXTI_TypeDef *exti, uint32_t gpioy) +{ + return (READ_BIT(exti->IVS, gpioy) == gpioy); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group5 RIF + * @{ + */ +/** + * @brief Check if Raw interrupt flag Status on line is actived + * @param exti EXTI Instance + * @retval EXTI->RIF value + */ +__STATIC_INLINE uint32_t md_exti_get_rif(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->RIF)); +} + +/** + * @brief Wake Up interrupts the original state. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_active_it_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RIF, EXTI_RIF_WAKEUP) == (EXTI_RIF_WAKEUP)); +} + +/** + * @brief Low Power Detector (LVD) interrupts the original state. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_active_it_low_power_detector(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RIF, EXTI_RIF_LVD) == (EXTI_RIF_LVD)); +} + +/** + * @brief Comparator2 (CMP2) interrupts the original state. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_active_it_comparator2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RIF, EXTI_RIF_CMP2) == (EXTI_RIF_CMP2)); +} + +/** + * @brief Comparator1 (CMP1) interrupts the original state. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_active_it_comparator1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RIF, EXTI_RIF_CMP1) == (EXTI_RIF_CMP1)); +} + +/** + * @brief GPIOy interrupt. (y=0...15) Interrupt the original state. + * @param exti EXTI Instance + * @param gpioy(gpio0~gpio15) The value Read in EXTI->IVS + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_active_it_gpio_pin(EXTI_TypeDef *exti, uint32_t gpioy) +{ + return (READ_BIT(exti->RIF, gpioy) == gpioy); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group6 IFM + * @{ + */ +/** + * @brief Check if Interrupt Flag Masked Status on line is actived + * @param exti EXTI Instance + * @retval EXTI->IFM value + */ +__STATIC_INLINE uint32_t md_exti_get_ifm(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->IFM)); +} + +/** + * @brief Wake Up interrupt mask status. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_masked_it_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IFM, EXTI_IFM_WAKEUP) == (EXTI_IFM_WAKEUP)); +} + +/** + * @brief Low Power Detector (LVD) interrupt mask status. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_masked_it_low_power_detector(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IFM, EXTI_IFM_LVD) == (EXTI_IFM_LVD)); +} + +/** + * @brief Comparator2 (CMP2) interrupt mask status. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_masked_it_comparator2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IFM, EXTI_IFM_CMP2) == (EXTI_IFM_CMP2)); +} + +/** + * @brief Comparator1 (CMP1) interrupt mask status. + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_masked_it_comparator1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IFM, EXTI_IFM_CMP1) == (EXTI_IFM_CMP1)); +} + +/** + * @brief GPIOy interrupt. (y=0...15) Interrupt mask status. + * @param exti EXTI Instance + * @param gpioy(gpio0~gpio15) The value Read in EXTI->IFM + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_masked_it_gpio_pin(EXTI_TypeDef *exti, uint32_t gpioy) +{ + return (READ_BIT(exti->IFM, gpioy) == gpioy); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group7 ICR + * @{ + */ +/** + * @brief Interrupt Clear on line + * @param exti EXTI Instance + * @param value The value write in EXTI->ICR + * @retval None + */ +__STATIC_INLINE void md_exti_set_icr(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ICR, value); +} + +/** + * @brief Clear the Wake Up interrupt. + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_it_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_WAKEUP); +} + +/** + * @brief Clear the Low Power Detector (LVD) interrupt. + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_it_low_power_detector(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_LVD); +} + +/** + * @brief Clear the Comparator2 (CMP2) interrupt. + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_it_comparator2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_CMP2); +} + +/** + * @brief Clear the Comparator1 (CMP1) interrupt. + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_it_comparator1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_CMP1); +} + +/** + * @brief Clear the GPIOy interrupt. (y=0...15). + * @param exti EXTI Instance + * @param gpioy(gpio0~gpio15) The value write in EXTI->ICR + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + * @retval None + */ +__STATIC_INLINE void md_exti_clear_it_gpio_pin(EXTI_TypeDef *exti, uint32_t gpioy) +{ + SET_BIT(exti->ICR, gpioy); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group8 RTS + * @{ + */ +/** + * @brief Set rising trigger event configuration bit of line + * @param exti EXTI Instance + * @param value The value write in EXTI->RTS + * @retval None + */ +__STATIC_INLINE void md_exti_set_rts(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->RTS, value); +} + +/** + * @brief Get rising trigger event configuration bit of line + * @param exti EXTI Instance + * @retval EXTI->RTS value + */ +__STATIC_INLINE uint32_t md_exti_get_rts(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->RTS)); +} + +/** + * @brief Enable RTSy: Rising edge trigger event configuration. (y=0...21). + * @param exti EXTI Instance + * @param rtsy The value write in EXTI->RTS + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rising_edge_trigger(EXTI_TypeDef *exti, uint32_t rtsy) +{ + SET_BIT(exti->RTS, rtsy); +} + +/** + * @brief Disable RTSy: Rising edge trigger event configuration. (y=0...21). + * @param exti EXTI Instance + * @param rtsy The value write in EXTI->RTS + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rising_edge_trigger(EXTI_TypeDef *exti, uint32_t rtsy) +{ + CLEAR_BIT(exti->RTS, rtsy); +} + +/** + * @brief Is enabled RTSy: Rising edge trigger event configuration. (y=0...21). + * @param exti EXTI Instance + * @param rtsy The value write in EXTI->RTS + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_rising_edge_trigger(EXTI_TypeDef *exti, uint32_t rtsy) +{ + return ((READ_BIT(exti->RTS, rtsy) == (rtsy))); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group9 FTS + * @{ + */ +/** + * @brief Set falling trigger event configuration bit of line + * @param exti EXTI Instance + * @param value The value write in EXTI->FTS + * @retval None + */ +__STATIC_INLINE void md_exti_set_fts(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->FTS, value); +} + +/** + * @brief Get falling trigger event configuration bit of line + * @param exti EXTI Instance + * @retval EXTI->FTS Value + */ +__STATIC_INLINE uint32_t md_exti_get_fts(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->FTS)); +} + +/** + * @brief Enable FTSy: Falling edge trigger event configuration. (y=0...21). + * @param exti EXTI Instance + * @param ftsy The value write in EXTI->FTS + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval None + */ +__STATIC_INLINE void md_exti_enable_falling_edge_trigger(EXTI_TypeDef *exti, uint32_t ftsy) +{ + SET_BIT(exti->FTS, ftsy); +} + +/** + * @brief Disable FTSy: Falling edge trigger event configuration. (y=0...21). + * @param exti EXTI Instance + * @param ftsy The value write in EXTI->RTS + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval None + */ +__STATIC_INLINE void md_exti_disable_falling_edge_trigger(EXTI_TypeDef *exti, uint32_t ftsy) +{ + CLEAR_BIT(exti->FTS, ftsy); +} + +/** + * @brief Is enabled FTSy: Falling edge trigger event configuration. (y=0...21). + * @param exti EXTI Instance + * @param ftsy The value write in EXTI->RTS + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_falling_edge_trigger(EXTI_TypeDef *exti, uint32_t ftsy) +{ + return ((READ_BIT(exti->FTS, ftsy) == (ftsy))); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group10 SWI + * @{ + */ +/** + * @brief Set software interrupt on line + * @param exti EXTI Instance + * @param value The value write in EXTI->SWI + * @retval None + */ +__STATIC_INLINE void md_exti_set_swi(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->SWI, value); +} + +/** + * @brief Get software interrupt on line + * @param exti EXTI Instance + * @retval EXTI->SWI Value + */ +__STATIC_INLINE uint32_t md_exti_get_swi(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->SWI)); +} + +/** + * @brief Enable SWIy: Software interruption. (y=0...21). + * @param exti EXTI Instance + * @param swiy The value write in EXTI->SWI + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval None + */ +__STATIC_INLINE void md_exti_enable_software_interrupt(EXTI_TypeDef *exti, uint32_t swiy) +{ + SET_BIT(exti->SWI, swiy); +} + +/** + * @brief Disable SWIy: Software interruption. (y=0...21). + * @param exti EXTI Instance + * @param swiy The value write in EXTI->SWI + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval None + */ +__STATIC_INLINE void md_exti_disable_software_interrupt(EXTI_TypeDef *exti, uint32_t swiy) +{ + CLEAR_BIT(exti->SWI, swiy); +} + +/** + * @brief Is enabled SWIy: Software interruption. (y=0...21). + * @param exti EXTI Instance + * @param swiy The value write in EXTI->SWI + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_software_interrupt(EXTI_TypeDef *exti, uint32_t swiy) +{ + return ((READ_BIT(exti->SWI, swiy) == (swiy))); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group11 ADTE1 + * @{ + */ +/** + * @brief Set ADC trigger on line + * @param exti EXTI Instance + * @param value The value write in EXTI->ADTE1 + * @retval None + */ +__STATIC_INLINE void md_exti_set_adte1(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ADTE1, value); +} + +/** + * @brief Get ADC trigger on line + * @param exti EXTI Instance + * @retval EXTI->ADTE1 Value + */ +__STATIC_INLINE uint32_t md_exti_get_adte1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->ADTE1)); +} + +/** + * @brief enable ADTEy: ADC trigger is enabled. (y=0...17). + * @param exti EXTI Instance + * @param adtey The value write in EXTI->ADTE1 + @arg @ref (MD_EXTI_EVENT_GPIO0 | MD_EXTI_EVENT_GPIO1 | MD_EXTI_EVENT_GPIO2 | MD_EXTI_EVENT_GPIO3 | + MD_EXTI_EVENT_GPIO4 | MD_EXTI_EVENT_GPIO5 | MD_EXTI_EVENT_GPIO6 | MD_EXTI_EVENT_GPIO7 | + MD_EXTI_EVENT_GPIO8 | MD_EXTI_EVENT_GPIO9 | MD_EXTI_EVENT_GPIO10 | MD_EXTI_EVENT_GPIO11 | + MD_EXTI_EVENT_GPIO12 | MD_EXTI_EVENT_GPIO13 | MD_EXTI_EVENT_GPIO14 | MD_EXTI_EVENT_GPIO15 | + MD_EXTI_EVENT_CMP1 | MD_EXTI_EVENT_CMP2) + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adc_trigger_source_1(EXTI_TypeDef *exti, uint32_t adtey) +{ + SET_BIT(exti->ADTE1, adtey); +} + +/** + * @brief disable ADTEy: ADC trigger is disabled. (y=0...17). + * @param exti EXTI Instance + * @param adtey The value write in EXTI->ADTE1 + @arg @ref (MD_EXTI_EVENT_GPIO0 | MD_EXTI_EVENT_GPIO1 | MD_EXTI_EVENT_GPIO2 | MD_EXTI_EVENT_GPIO3 | + MD_EXTI_EVENT_GPIO4 | MD_EXTI_EVENT_GPIO5 | MD_EXTI_EVENT_GPIO6 | MD_EXTI_EVENT_GPIO7 | + MD_EXTI_EVENT_GPIO8 | MD_EXTI_EVENT_GPIO9 | MD_EXTI_EVENT_GPIO10 | MD_EXTI_EVENT_GPIO11 | + MD_EXTI_EVENT_GPIO12 | MD_EXTI_EVENT_GPIO13 | MD_EXTI_EVENT_GPIO14 | MD_EXTI_EVENT_GPIO15 | + MD_EXTI_EVENT_CMP1 | MD_EXTI_EVENT_CMP2) + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adc_trigger_source_1(EXTI_TypeDef *exti, uint32_t adtey) +{ + CLEAR_BIT(exti->ADTE1, adtey); +} + +/** + * @brief Get ADTEy: ADC trigger is enabled. (y=0...17). + * @param exti EXTI Instance + * @retval adc trigger source + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_adc_trigger_source_1(EXTI_TypeDef *exti, uint32_t adtey) +{ + return (uint32_t)((bool)(READ_BIT(exti->ADTE1, adtey))); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group12 ADTE2 + * @{ + */ +/** + * @brief Set ADC trigger on line + * @param exti EXTI Instance + * @param value The value write in EXTI->ADTE2 + * @retval None + */ +__STATIC_INLINE void md_exti_set_adte2(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ADTE2, value); +} + +/** + * @brief Get ADC trigger on line + * @param exti EXTI Instance + * @retval EXTI->ADTE2 Value + */ +__STATIC_INLINE uint32_t md_exti_get_adte2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->ADTE2)); +} + +/** + * @brief Enable ADTEy: ADC trigger is enabled. (y=0...17). + * @param exti EXTI Instance + * @param adtey The value write in EXTI->ADTE1 + @arg @ref (MD_EXTI_EVENT_GPIO0 | MD_EXTI_EVENT_GPIO1 | MD_EXTI_EVENT_GPIO2 | MD_EXTI_EVENT_GPIO3 | + MD_EXTI_EVENT_GPIO4 | MD_EXTI_EVENT_GPIO5 | MD_EXTI_EVENT_GPIO6 | MD_EXTI_EVENT_GPIO7 | + MD_EXTI_EVENT_GPIO8 | MD_EXTI_EVENT_GPIO9 | MD_EXTI_EVENT_GPIO10 | MD_EXTI_EVENT_GPIO11 | + MD_EXTI_EVENT_GPIO12 | MD_EXTI_EVENT_GPIO13 | MD_EXTI_EVENT_GPIO14 | MD_EXTI_EVENT_GPIO15 | + MD_EXTI_EVENT_CMP1 | MD_EXTI_EVENT_CMP2) + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adc_trigger_source_2(EXTI_TypeDef *exti, uint32_t adtey) +{ + SET_BIT(exti->ADTE2, adtey); +} + +/** + * @brief Disable ADTEy: ADC trigger is disabled. (y=0...17). + * @param exti EXTI Instance + * @param adtey The value write in EXTI->ADTE1 + @arg @ref (MD_EXTI_EVENT_GPIO0 | MD_EXTI_EVENT_GPIO1 | MD_EXTI_EVENT_GPIO2 | MD_EXTI_EVENT_GPIO3 | + MD_EXTI_EVENT_GPIO4 | MD_EXTI_EVENT_GPIO5 | MD_EXTI_EVENT_GPIO6 | MD_EXTI_EVENT_GPIO7 | + MD_EXTI_EVENT_GPIO8 | MD_EXTI_EVENT_GPIO9 | MD_EXTI_EVENT_GPIO10 | MD_EXTI_EVENT_GPIO11 | + MD_EXTI_EVENT_GPIO12 | MD_EXTI_EVENT_GPIO13 | MD_EXTI_EVENT_GPIO14 | MD_EXTI_EVENT_GPIO15 | + MD_EXTI_EVENT_CMP1 | MD_EXTI_EVENT_CMP2) + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adc_trigger_source_2(EXTI_TypeDef *exti, uint32_t adtey) +{ + CLEAR_BIT(exti->ADTE2, adtey); +} + +/** + * @brief Get ADTEy: ADC trigger is enabled. (y=0...17). + * @param exti EXTI Instance + * @retval adc trigger source + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_adc_trigger_source_2(EXTI_TypeDef *exti, uint32_t adtey) +{ + return (uint32_t)((bool)(READ_BIT(exti->ADTE2, adtey))); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group13 DB + * @{ + */ +/** + * @brief Set debounce enable bit of line + * @param exti EXTI Instance + * @param value The value write in EXTI->DB + * @retval None + */ +__STATIC_INLINE void md_exti_set_db(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->DB, value); +} + +/** + * @brief Get debounce enable bit of line + * @param exti EXTI Instance + * @retval EXTI->DB Value + */ +__STATIC_INLINE uint32_t md_exti_get_db(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->DB)); +} + +/** + * @brief Enable DBENy: Bounce elimination function switch. (y=0...21). + * @param exti EXTI Instance + * @param dbeny The value write in EXTI->DB + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval None + */ +__STATIC_INLINE void md_exti_enable_debounce(EXTI_TypeDef *exti, uint32_t dbeny) +{ + SET_BIT(exti->DB, dbeny); +} + +/** + * @brief disable DBENy: Bounce elimination function switch. (y=0...21). + * @param exti EXTI Instance + * @param dbeny The value write in EXTI->DB + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval None + */ +__STATIC_INLINE void md_exti_disable_debounce(EXTI_TypeDef *exti, uint32_t dbeny) +{ + CLEAR_BIT(exti->DB, dbeny); +} + +/** + * @brief Enabled DBENy: Bounce elimination function switch. (y=0...21). + * @param exti EXTI Instance + * @param dbeny The value write in EXTI->DB + @arg @ref MD_EXTI_EVENT_GPIO0 + @arg @ref MD_EXTI_EVENT_GPIO1 + @arg @ref MD_EXTI_EVENT_GPIO2 + @arg @ref MD_EXTI_EVENT_GPIO3 + @arg @ref MD_EXTI_EVENT_GPIO4 + @arg @ref MD_EXTI_EVENT_GPIO5 + @arg @ref MD_EXTI_EVENT_GPIO6 + @arg @ref MD_EXTI_EVENT_GPIO7 + @arg @ref MD_EXTI_EVENT_GPIO8 + @arg @ref MD_EXTI_EVENT_GPIO9 + @arg @ref MD_EXTI_EVENT_GPIO10 + @arg @ref MD_EXTI_EVENT_GPIO11 + @arg @ref MD_EXTI_EVENT_GPIO12 + @arg @ref MD_EXTI_EVENT_GPIO13 + @arg @ref MD_EXTI_EVENT_GPIO14 + @arg @ref MD_EXTI_EVENT_GPIO15 + @arg @ref MD_EXTI_EVENT_CMP1 + @arg @ref MD_EXTI_EVENT_CMP2 + @arg @ref MD_EXTI_EVENT_LVD + @arg @ref MD_EXTI_EVENT_WAKEUP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enabled_debounce(EXTI_TypeDef *exti, uint32_t dbeny) +{ + return ((READ_BIT(exti->DB, dbeny) == (dbeny))); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group14 DBC + * @{ + */ +/** + * @brief Set Sampling Rate Control Register + * @param exti EXTI Instance + * @param value The value write in EXTI->DBC + * @retval None + */ +__STATIC_INLINE void md_exti_set_dbc(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->DBC, value); +} + +/** + * @brief Get Sampling Rate Control Register + * @param exti EXTI Instance + * @retval EXTI->DBC Value + */ +__STATIC_INLINE uint32_t md_exti_get_dbc(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->DBC)); +} + +/** + * @brief Set Bounce elimination prescaler + * @param exti EXTI Instance + * @param value The value write in EXTI->DBC + * @retval None + */ +__STATIC_INLINE void md_exti_set_debounce_prescaler(EXTI_TypeDef *exti, uint32_t value) +{ + MODIFY_REG(exti->DBC, EXTI_DBC_DBPRE_MSK, value << EXTI_DBC_DBPRE_POSS); +} + +/** + * @brief Get Bounce elimination prescaler + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_debounce_prescaler(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->DBC, EXTI_DBC_DBPRE_MSK) >> EXTI_DBC_DBPRE_POSS); +} + +/** + * @brief Set Bounce elimination counter + * @param exti EXTI Instance + * @param dbcnt The value write in EXTI->DBC + @arg @ref MD_EXTI_DEBOUNCECOUNT_IMMEDIATELY + @arg @ref MD_EXTI_DEBOUNCECOUNT_2_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_3_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_4_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_5_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_6_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_7_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_8_TIMES + * @retval None + */ +__STATIC_INLINE void md_exti_set_debounce_count(EXTI_TypeDef *exti, uint32_t dbcnt) +{ + MODIFY_REG(exti->DBC, EXTI_DBC_DBCNT_MSK, dbcnt << EXTI_DBC_DBCNT_POSS); +} + +/** + * @brief Get Bounce elimination counter + * @param exti EXTI Instance + * @retval The retval can be one of the following values: + @arg @ref MD_EXTI_DEBOUNCECOUNT_IMMEDIATELY + @arg @ref MD_EXTI_DEBOUNCECOUNT_2_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_3_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_4_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_5_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_6_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_7_TIMES + @arg @ref MD_EXTI_DEBOUNCECOUNT_8_TIMES + */ +__STATIC_INLINE uint32_t md_exti_get_debounce_count(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->DBC, EXTI_DBC_DBCNT_MSK) >> EXTI_DBC_DBCNT_POSS); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group15 ICFG1 + * @{ + */ +/** + * @brief Set EXTI interrupt configuration register 1 + * @param exti EXTI Instance + * @param value The value write in EXTI->ICFG1 + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ICFG1, value); +} + +/** + * @brief Get EXTI interrupt configuration register 1 + * @param exti EXTI Instance + * @retval EXTI->ICFG1 Value + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->ICFG1)); +} + +/** + * @brief Set EXTI interrupt configuration register 1 + * @param exti EXTI Instance + * @param extiy The value write in EXTI->ICFG1 + @arg @ref MD_EXTI_GPIOA0 | MD_EXTI_GPIOA1 | MD_EXTI_GPIOA2 | MD_EXTI_GPIOA3 | + MD_EXTI_GPIOA4 | MD_EXTI_GPIOA5 | MD_EXTI_GPIOA6 | MD_EXTI_GPIOA7) + + @arg @ref MD_EXTI_GPIOB0 | MD_EXTI_GPIOB1 | MD_EXTI_GPIOB2 | MD_EXTI_GPIOB3 | + MD_EXTI_GPIOB4 | MD_EXTI_GPIOB5 | MD_EXTI_GPIOB6 | MD_EXTI_GPIOB7) + + @arg @ref MD_EXTI_GPIOC0 | MD_EXTI_GPIOC1 | MD_EXTI_GPIOC2 | MD_EXTI_GPIOC3 | + MD_EXTI_GPIOC4 | MD_EXTI_GPIOC5 | MD_EXTI_GPIOC6 | MD_EXTI_GPIOC7) + + @arg @ref MD_EXTI_GPIOD0 | MD_EXTI_GPIOD1 | MD_EXTI_GPIOD2 | MD_EXTI_GPIOD3 | + MD_EXTI_GPIOD4 | MD_EXTI_GPIOD5 | MD_EXTI_GPIOD6 | MD_EXTI_GPIOD7) + * @retval None + */ +__STATIC_INLINE void md_exti_set_interrupt_pin_0_7(EXTI_TypeDef *exti, uint32_t extiy) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_EXTIy, extiy); +} + +/** + * @brief Get EXTI interrupt configuration register 1 + * @param exti EXTI Instance + * @retval The retval can be one of the following values: + @arg @ref MD_EXTI_GPIOA0 + @arg @ref MD_EXTI_GPIOA1 + @arg @ref MD_EXTI_GPIOA2 + @arg @ref MD_EXTI_GPIOA3 + @arg @ref MD_EXTI_GPIOA4 + @arg @ref MD_EXTI_GPIOA5 + @arg @ref MD_EXTI_GPIOA6 + @arg @ref MD_EXTI_GPIOA7 + + @arg @ref MD_EXTI_GPIOB0 + @arg @ref MD_EXTI_GPIOB1 + @arg @ref MD_EXTI_GPIOB2 + @arg @ref MD_EXTI_GPIOB3 + @arg @ref MD_EXTI_GPIOB4 + @arg @ref MD_EXTI_GPIOB5 + @arg @ref MD_EXTI_GPIOB6 + @arg @ref MD_EXTI_GPIOB7 + + @arg @ref MD_EXTI_GPIOC0 + @arg @ref MD_EXTI_GPIOC1 + @arg @ref MD_EXTI_GPIOC2 + @arg @ref MD_EXTI_GPIOC3 + @arg @ref MD_EXTI_GPIOC4 + @arg @ref MD_EXTI_GPIOC5 + @arg @ref MD_EXTI_GPIOC6 + @arg @ref MD_EXTI_GPIOC7 + + @arg @ref MD_EXTI_GPIOD0 + @arg @ref MD_EXTI_GPIOD1 + @arg @ref MD_EXTI_GPIOD2 + @arg @ref MD_EXTI_GPIOD3 + @arg @ref MD_EXTI_GPIOD4 + @arg @ref MD_EXTI_GPIOD5 + @arg @ref MD_EXTI_GPIOD6 + @arg @ref MD_EXTI_GPIOD7 + */ +__STATIC_INLINE uint32_t md_exti_get_interrupt_pin_0_7(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_EXTIy)); +} +/** + * @} + */ + +/** @defgroup MD_EXTI_Public_Functions_Group16 ICFG2 + * @{ + */ +/** + * @brief Set EXTI interrupt configuration register 2 + * @param exti EXTI Instance + * @param value The value write in EXTI->ICFG2 + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ICFG2, value); +} + +/** + * @brief Get EXTI interrupt configuration register 2 + * @param exti EXTI Instance + * @retval EXTI->ICFG2 Value + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->ICFG2)); +} + +/** + * @brief Set EXTI interrupt configuration register 2 + * @param exti EXTI Instance + * @param extiy The value write in EXTI->ICFG1 + @arg @ref MD_EXTI_GPIOA8 | MD_EXTI_GPIOA9 | MD_EXTI_GPIOA10 | MD_EXTI_GPIOA11 | + MD_EXTI_GPIOA12 | MD_EXTI_GPIOA13 | MD_EXTI_GPIOA14 | MD_EXTI_GPIOA15) + + @arg @ref MD_EXTI_GPIOB8 | MD_EXTI_GPIOB9 | MD_EXTI_GPIOB10 | MD_EXTI_GPIOB11 | + MD_EXTI_GPIOB12 | MD_EXTI_GPIOB13 | MD_EXTI_GPIOB14 | MD_EXTI_GPIOB15) + + @arg @ref MD_EXTI_GPIOC8 | MD_EXTI_GPIOC9 | MD_EXTI_GPIOC10 | MD_EXTI_GPIOC11 | + MD_EXTI_GPIOC12 | MD_EXTI_GPIOC13 | MD_EXTI_GPIOC14 | MD_EXTI_GPIOC15) + + @arg @ref MD_EXTI_GPIOD8 | MD_EXTI_GPIOD9 | MD_EXTI_GPIOD10 | MD_EXTI_GPIOD11 | + MD_EXTI_GPIOD12 | MD_EXTI_GPIOD13 | MD_EXTI_GPIOD14 | MD_EXTI_GPIOD15) + * @retval None + */ +__STATIC_INLINE void md_exti_set_interrupt_pin_8_15(EXTI_TypeDef *exti, uint32_t extiy) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_EXTIy, extiy); +} + +/** + * @brief Get EXTI interrupt configuration register 2 + * @param exti EXTI Instance + * @retval None + @arg @ref MD_EXTI_GPIOA8 + @arg @ref MD_EXTI_GPIOA9 + @arg @ref MD_EXTI_GPIOA10 + @arg @ref MD_EXTI_GPIOA11 + @arg @ref MD_EXTI_GPIOA12 + @arg @ref MD_EXTI_GPIOA13 + @arg @ref MD_EXTI_GPIOA14 + @arg @ref MD_EXTI_GPIOA15 + + @arg @ref MD_EXTI_GPIOB8 + @arg @ref MD_EXTI_GPIOB9 + @arg @ref MD_EXTI_GPIOB10 + @arg @ref MD_EXTI_GPIOB11 + @arg @ref MD_EXTI_GPIOB12 + @arg @ref MD_EXTI_GPIOB13 + @arg @ref MD_EXTI_GPIOB14 + @arg @ref MD_EXTI_GPIOB15 + + @arg @ref MD_EXTI_GPIOC8 + @arg @ref MD_EXTI_GPIOC9 + @arg @ref MD_EXTI_GPIOC10 + @arg @ref MD_EXTI_GPIOC11 + @arg @ref MD_EXTI_GPIOC12 + @arg @ref MD_EXTI_GPIOC13 + @arg @ref MD_EXTI_GPIOC14 + @arg @ref MD_EXTI_GPIOC15 + + @arg @ref MD_EXTI_GPIOD8 + @arg @ref MD_EXTI_GPIOD9 + @arg @ref MD_EXTI_GPIOD10 + @arg @ref MD_EXTI_GPIOD11 + @arg @ref MD_EXTI_GPIOD12 + @arg @ref MD_EXTI_GPIOD13 + @arg @ref MD_EXTI_GPIOD14 + @arg @ref MD_EXTI_GPIOD15 + */ +__STATIC_INLINE uint32_t md_exti_get_interrupt_pin_8_15(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_EXTIy)); +} +/** + * @} + */ + +///** +// * @brief Set EXTI interrupt configuration register 2 +// * @param exti EXTI Instance +// * @param port The value write in EXTI->ICFG1 +// @arg @ref MD_EXTI_PORT_GPIOA +// @arg @ref MD_EXTI_PORT_GPIOB +// @arg @ref MD_EXTI_PORT_GPIOC +// @arg @ref MD_EXTI_PORT_GPIOD +// * @param extiy The value write in EXTI->ICFG1 +// @arg @ref MD_EXTI_GPIO0 +// @arg @ref MD_EXTI_GPIO1 +// @arg @ref MD_EXTI_GPIO2 +// @arg @ref MD_EXTI_GPIO3 +// @arg @ref MD_EXTI_GPIO4 +// @arg @ref MD_EXTI_GPIO5 +// @arg @ref MD_EXTI_GPIO6 +// @arg @ref MD_EXTI_GPIO7 +// @arg @ref MD_EXTI_GPIO8 +// @arg @ref MD_EXTI_GPIO9 +// @arg @ref MD_EXTI_GPIO10 +// @arg @ref MD_EXTI_GPIO11 +// @arg @ref MD_EXTI_GPIO12 +// @arg @ref MD_EXTI_GPIO13 +// @arg @ref MD_EXTI_GPIO14 +// @arg @ref MD_EXTI_GPIO15 +// * @retval None +// */ +//__STATIC_INLINE void md_exti_set_interrupt_source(EXTI_TypeDef *exti, uint32_t port, uint32_t extiy) +//{ +// if((extiy >> 8) == 0) +// MODIFY_REG(exti->ICFG1, EXTI_ICFG1_EXTIy, port << extiy); +// else +// MODIFY_REG(exti->ICFG2, EXTI_ICFG2_EXTIy, port << extiy); +//} + +///** +// * @brief Get EXTI interrupt configuration register 2 +// * @param exti EXTI Instance +// * @retval None +// @arg @ref MD_EXTI_GPIOA8 +// @arg @ref MD_EXTI_GPIOA9 +// @arg @ref MD_EXTI_GPIOA10 +// @arg @ref MD_EXTI_GPIOA11 +// @arg @ref MD_EXTI_GPIOA12 +// @arg @ref MD_EXTI_GPIOA13 +// @arg @ref MD_EXTI_GPIOA14 +// @arg @ref MD_EXTI_GPIOA15 + +// @arg @ref MD_EXTI_GPIOB8 +// @arg @ref MD_EXTI_GPIOB9 +// @arg @ref MD_EXTI_GPIOB10 +// @arg @ref MD_EXTI_GPIOB11 +// @arg @ref MD_EXTI_GPIOB12 +// @arg @ref MD_EXTI_GPIOB13 +// @arg @ref MD_EXTI_GPIOB14 +// @arg @ref MD_EXTI_GPIOB15 + +// @arg @ref MD_EXTI_GPIOC8 +// @arg @ref MD_EXTI_GPIOC9 +// @arg @ref MD_EXTI_GPIOC10 +// @arg @ref MD_EXTI_GPIOC11 +// @arg @ref MD_EXTI_GPIOC12 +// @arg @ref MD_EXTI_GPIOC13 +// @arg @ref MD_EXTI_GPIOC14 +// @arg @ref MD_EXTI_GPIOC15 + +// @arg @ref MD_EXTI_GPIOD8 +// @arg @ref MD_EXTI_GPIOD9 +// @arg @ref MD_EXTI_GPIOD10 +// @arg @ref MD_EXTI_GPIOD11 +// @arg @ref MD_EXTI_GPIOD12 +// @arg @ref MD_EXTI_GPIOD13 +// @arg @ref MD_EXTI_GPIOD14 +// @arg @ref MD_EXTI_GPIOD15 +// */ +//__STATIC_INLINE uint32_t md_exti_get_interrupt_source(EXTI_TypeDef *exti, uint32_t extiy) +//{ +// if((extiy>>8) == 0) +// return (uint32_t)(READ_BIT(exti->ICFG1, extiy)); +// else +// return (uint32_t)(READ_BIT(exti->ICFG2, extiy)); +//} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif +#endif + + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_fc.c b/os/common/ext/CMSIS/ES32/FS026/md/md_fc.c new file mode 100644 index 00000000000..a84144b37c6 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_fc.c @@ -0,0 +1,642 @@ +/********************************************************************************** + * + * @file md_fc.c + * @brief md_fc C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 25 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_syscfg.h" +#include "md_fc.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (FC) + +/** @defgroup FC FC + * @brief FC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Private constants ----------------------------------------------------------*/ +/** @defgroup MD_FC_Private_Constants FC Private Constants + * @{ + */ + +#define REMAPDATA_BASE (( uint32_t)0x00000000) /* FLASH Main (128K Bytes) */ +#define REMAPINFO_BASE (( uint32_t)0x00000000) /* FLASH Info ( 4K Bytes) */ + +/** + * @} MD_FC_Private_Constants + */ + +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Functions FC Public Functions + * @{ + */ + +/** + * @brief FC unlock. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: FC unlock done + * - ERROR: FC unlock fail + */ +ErrorStatus md_fc_unlock(void) +{ + ErrorStatus status = ERROR; + + /* Unlock EF*/ + if (!md_fc_is_active_flag_flash_unlock(FC)) + { + md_fc_set_flash_unlock(FC, MD_FC_PC_EF_UL_KEY1); + md_fc_set_flash_unlock(FC, MD_FC_PC_EF_UL_KEY2); + + if (!md_fc_is_active_flag_flash_unlock(FC)) + return status; + } + + status = SUCCESS; + return status; +} + +/** + * @brief FC lock. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: FC lock done + * - ERROR: FC lock fail + */ +ErrorStatus md_fc_lock(void) +{ + ErrorStatus status = ERROR; + + /* Unlock EF*/ + if (md_fc_is_active_flag_flash_unlock(FC)) + { + md_fc_set_flash_unlock(FC, MD_FC_PC_EF_UL_LOCK); + + if (md_fc_is_active_flag_flash_unlock(FC)) + return status; + } + + status = SUCCESS; + return status; +} + +/** + * @brief FC main erase. + * @note To prevent unexpected code branch, the main erase function must specify a dedicated main erase ID + * @param MEraseID Key for main erase, must be 0xA5A5AA55 + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Main flash erased + * - ERROR: Main erase ID mismatch + */ +ErrorStatus md_fc_main_erase(uint32_t MEraseID) +{ + ErrorStatus status = ERROR; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return status; + + /* Check the ID */ + if (MEraseID != MD_FC_PC_EF_MERASEID) + return status; + + md_fc_set_pa(FC, 0x0); + /* Write MERASE to CMD*/ + md_fc_set_flash_command(FC, MD_FC_CMD_FULL_ERASE); + + status = SUCCESS; + return status; +} + +/** + * @brief FC Sector Erase + * @note To prevent unexpected code branch, the page erase function must specify the complement start address + * @param pSErasePara Pointer to structure md_fc_ControlTypeDef + * @retval An ErrorStatus enumeration value. + * - SUCCESS: Specified page address erased + * - ERROR: Complement of start address mismatch + */ +ErrorStatus md_fc_sector_erase(md_fc_ControlTypeDef *pSErasePara) +{ + ErrorStatus status = ERROR; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return status; + + /* Check the start address and complement of start address*/ + if (pSErasePara->SAddr & pSErasePara->SAddrC) + return status; + + /* Write sector address to PA*/ + md_fc_disable_info_region(FC); + md_fc_set_program_address(FC, pSErasePara->SAddr); + /* Write SERASE to CMD*/ + md_fc_set_flash_command(FC, MD_FC_CMD_SECTOR_ERASE); + + status = SUCCESS; + return status; +} + +/** + * @brief FC Page Erase + * @note To prevent unexpected code branch, the page erase function must specify the complement start address + * @param pSErasePara Pointer to structure md_fc_ControlTypeDef + * @retval An ErrorStatus enumeration value. + * - SUCCESS: Specified page address erased + * - ERROR: Complement of start address mismatch + */ +ErrorStatus md_fc_page_erase(md_fc_ControlTypeDef *pSErasePara) +{ + ErrorStatus status = ERROR; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return status; + + /* Check the start address and complement of start address*/ + if (pSErasePara->SAddr & pSErasePara->SAddrC) + return status; + + md_fc_disable_info_region(FC); + /* Write sector address to PA*/ + md_fc_set_program_address(FC, pSErasePara->SAddr); + /* Write SERASE to CMD*/ + md_fc_set_flash_command(FC, MD_FC_CMD_PAGE_ERASE); + + status = SUCCESS; + return status; +} + +/** + * @brief FC Info. Page Erase + * @note To prevent unexpected code branch, the page erase function must specify the complement start address + * @param pSErasePara Pointer to structure md_fc_ControlTypeDef + * @retval An ErrorStatus enumeration value. + * - SUCCESS: Specified page address erased + * - ERROR: Complement of start address mismatch + */ +ErrorStatus md_fc_info_page_erase(md_fc_ControlTypeDef *pSErasePara) +{ + ErrorStatus status = ERROR; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return status; + + /* Check the start address and complement of start address*/ + if (pSErasePara->SAddr & pSErasePara->SAddrC) + return status; + + md_fc_enable_info_region(FC); + /* Write sector address to PA*/ + md_fc_set_program_address(FC, pSErasePara->SAddr); + /* Write SERASE to CMD*/ + md_fc_set_flash_command(FC, MD_FC_CMD_PAGE_ERASE); + + md_fc_disable_info_region(FC); + + status = SUCCESS; + return status; +} + +/** + * @brief FC Page Program + * @note To prevent unexpected code branch, the page program function must specify the complement start address + * @param pProgramPara Pointer to structure md_fc_ControlTypeDef + * @retval An ErrorStatus enumeration value. + * - SUCCESS: Data in data buffer programed to specified page address + * - ERROR: Complement of start address mismatch + */ +ErrorStatus md_fc_program(md_fc_ControlTypeDef *pProgramPara) +{ + ErrorStatus status = ERROR; + uint16_t BCnt; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return status; + + md_fc_set_program_counter(FC, pProgramPara->BCnt); + md_fc_set_program_address(FC, pProgramPara->SAddr); + BCnt = pProgramPara->BCnt; + BCnt = (BCnt + 3) >> 2; + + while (BCnt--) + { + /* Check the start address and complement of start address*/ + if (pProgramPara->SAddr & pProgramPara->SAddrC) + { + return status; + } + + /* Write lower 32bit program data to PLD*/ + md_fc_set_program_data(FC, *pProgramPara->pU32Buf++); + + /* Write PROGRAM to CMD*/ + md_fc_set_flash_command(FC, MD_FC_CMD_PROG_EFLASH); + } + + status = SUCCESS; + return status; +} + +/** + * @brief FC Info. Page Program + * @note To prevent unexpected code branch, the page program function must specify the complement start address + * @param pProgramPara Pointer to structure md_fc_ControlTypeDef + * @retval An ErrorStatus enumeration value. + * - SUCCESS: Data in data buffer programed to specified page address + * - ERROR: Complement of start address mismatch + */ +ErrorStatus md_fc_info_program(md_fc_ControlTypeDef *pProgramPara) +{ + ErrorStatus status = ERROR; + uint16_t BCnt; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return status; + + md_fc_enable_info_region(FC); + md_fc_set_program_counter(FC, pProgramPara->BCnt); + md_fc_set_program_address(FC, pProgramPara->SAddr); + BCnt = pProgramPara->BCnt; + BCnt = (BCnt + 3) >> 2; + + while (BCnt--) + { + /* Check the start address and complement of start address*/ + if (pProgramPara->SAddr & pProgramPara->SAddrC) + { + return status; + } + + /* Write lower 32bit program data to PLD*/ + md_fc_set_program_data(FC, *pProgramPara->pU32Buf++); + + /* Write PROGRAM to CMD*/ + md_fc_set_flash_command(FC, MD_FC_CMD_PROG_EFLASH); + } + + md_fc_disable_info_region(FC); + + status = SUCCESS; + return status; +} + +/** + * @brief FC Page Read + * @param pReadPara Pointer to structure md_fc_ControlTypeDef + * @retval Always return SUCCESS + * - Data in specified page address read to data buffer + */ +ErrorStatus md_fc_read(md_fc_ControlTypeDef *pReadPara) +{ + ErrorStatus status = SUCCESS; + uint32_t *EFAddr; + uint16_t BCnt; + + if (md_syscfg_get_memory_mapping_real(SYSCFG) == MD_SYSCFG_MEMMOD_MAIN) /* Reamp from Main */ + EFAddr = (uint32_t *)(REMAPDATA_BASE + pReadPara->SAddr); + else + EFAddr = (uint32_t *)(FLASH_BASE + pReadPara->SAddr); + + BCnt = pReadPara->BCnt; + BCnt = (BCnt + 3) >> 2; + + while (BCnt--) + *pReadPara->pU32Buf++ = *EFAddr++; + + return status; +} + +/** + * @brief FC Update UCRP Protect + * @param pUpdateBit Pointer to structure md_fc_UpdProtTypeDdef + * @retval An ErrorStatus enumeration value: + * - SUCCESS: protect set success + * - ERROR: The status is locked + */ +ErrorStatus md_fc_update_ucrp(md_fc_UpdProtTypeDef *pUpdateBit) +{ + ErrorStatus status = SUCCESS; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return ERROR; + + md_fc_set_protect0(FC, pUpdateBit->UpdateL); + md_fc_set_protect1(FC, pUpdateBit->UpdateH); + md_fc_set_flash_command(FC, MD_FC_CMD_UCRP_PROTECT); + + return status; +} + +/** + * @brief FC Update Read Protect + * @param parameter can be one of the following values: + * @arg @ref Level0 0xaaaaaaaa + * @arg @ref Level1 0xbbbbbbbb + * @arg @ref Level2 0xcccccccc + * @retval An ErrorStatus enumeration value: + * - SUCCESS: protect set success + * - ERROR: The status is locked + */ +ErrorStatus md_fc_update_rp(uint32_t level) +{ + ErrorStatus status = SUCCESS; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return ERROR; + + md_fc_set_protect0(FC, level); + md_fc_set_flash_command(FC, MD_FC_CMD_RP_PROTECT); + + return status; +} + +/** + * @brief FC Update Write Protect + * @param pUpdateBit Pointer to structure md_fc_UpdProtTypeDdef + * @retval An ErrorStatus enumeration value: + * - SUCCESS: protect set success + * - ERROR: The status is locked + */ +ErrorStatus md_fc_update_wp(md_fc_UpdProtTypeDef *pUpdateBit) +{ + ErrorStatus status = SUCCESS; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return ERROR; + + md_fc_set_protect0(FC, pUpdateBit->UpdateL); + md_fc_set_protect1(FC, pUpdateBit->UpdateH); + md_fc_set_flash_command(FC, MD_FC_CMD_WP_PROTECT); + + return status; +} + +/** + * @brief FC Clear UCRP Protect + * @param + * @retval An ErrorStatus enumeration value: + * - SUCCESS: protect clear success + * - ERROR: The status is locked + */ +ErrorStatus md_fc_clear_ucrp(void) +{ + ErrorStatus status = SUCCESS; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return ERROR; + + /* Write sector address to PA*/ + md_fc_enable_info_region(FC); + md_fc_set_program_address(FC, MD_FC_PC_EF_IPAGESZ * 0); + /* Write SERASE to CMD*/ + md_fc_set_flash_command(FC, MD_FC_CMD_PAGE_ERASE); + md_fc_disable_info_region(FC); + + return status; +} + +/** + * @brief FC Clear WP Protect + * @param + * @retval An ErrorStatus enumeration value: + * - SUCCESS: protect clear success + * - ERROR: The status is locked + */ +ErrorStatus md_fc_clear_wp(void) +{ + ErrorStatus status = SUCCESS; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return ERROR; + + /* Write sector address to PA*/ + md_fc_enable_info_region(FC); + md_fc_set_program_address(FC, MD_FC_PC_EF_IPAGESZ * 2); + /* Write SERASE to CMD*/ + md_fc_set_flash_command(FC, MD_FC_CMD_PAGE_ERASE); + md_fc_disable_info_region(FC); + + return status; +} + +/** + * @brief FC Clear User Option (Info. Page 2) + * @param + * @retval An ErrorStatus enumeration value: + * - SUCCESS: protect clear success + * - ERROR: The status is locked + */ +ErrorStatus md_fc_clear_user_option(void) +{ + ErrorStatus status = SUCCESS; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return ERROR; + + /* Write sector address to PA*/ + md_fc_enable_info_region(FC); + md_fc_set_program_address(FC, MD_FC_PC_EF_IPAGESZ * 2); + /* Write SERASE to CMD*/ + md_fc_set_flash_command(FC, MD_FC_CMD_PAGE_ERASE); + md_fc_disable_info_region(FC); + + return status; +} + +/** + * @brief FC Reload Option Byte + * @note Write fixed value 0xE to trigger the option byte reload. + After option byte is reloaded, the system reset will be triggered. + * @param None + * @retval None + */ +ErrorStatus md_fc_option_byte_reload() +{ + ErrorStatus status = SUCCESS; + + /* Check the status not lock */ + if (!md_fc_is_active_flag_flash_unlock(FC)) + return ERROR; + + md_fc_set_option_byte_reload(FC, MD_FC_OPRLD_0XE); + + return status; +} + +/** + * @brief FC Read Info. page + * @param None + * @retval Always return SUCCESS + * - Data in specified page address read to data buffer + */ +ErrorStatus md_fc_read_info(uint32_t info_addr, uint32_t *info) +{ + ErrorStatus status = SUCCESS; + uint32_t *EFAddr; + + if (md_fc_is_enabled_flash_prefetch(FC)) + { + md_fc_disable_flash_prefetch(FC); + EFAddr = (uint32_t *)(FLASH_INFO_BASE + info_addr); + *info = *EFAddr; + md_fc_enable_flash_prefetch(FC); + } + else + { + EFAddr = (uint32_t *)(FLASH_INFO_BASE + info_addr); + *info = *EFAddr; + } + + return status; +} + +/** + * @brief FC read chipid (Address 0x08A0) + * @param pReadPara Pointer to structure md_fc_ControlTypeDef + * @retval Always return SUCCESS + * - Data in specified page address read to data buffer + */ +ErrorStatus md_fc_read_chipid(uint32_t *CHIPID) +{ + ErrorStatus status = SUCCESS; + uint32_t *EFAddr; + + if (md_fc_is_enabled_flash_prefetch(FC)) + { + md_fc_disable_flash_prefetch(FC); + EFAddr = (uint32_t *)(FLASH_INFO_BASE + CHIP_ID); + *CHIPID = *EFAddr; + md_fc_enable_flash_prefetch(FC); + } + else + { + EFAddr = (uint32_t *)(FLASH_INFO_BASE + CHIP_ID); + *CHIPID = *EFAddr; + } + + return status; +} + +/** + * @brief FC read unique id (Address 0x08A4/0x08A8/0x08AC/0x08B0) + * @param pReadPara Pointer to structure md_fc_ControlTypeDef + * @retval Always return SUCCESS + * - Data in specified page address read to data buffer + */ +ErrorStatus md_fc_read_uid(uint32_t *UID0, uint32_t *UID1, uint32_t *UID2, uint32_t *UID3) +{ + ErrorStatus status = SUCCESS; + uint32_t *EFAddr; + + if (md_fc_is_enabled_flash_prefetch(FC)) + { + md_fc_disable_flash_prefetch(FC); + EFAddr = (uint32_t *)(FLASH_INFO_BASE + U_ID); + *UID0 = *EFAddr++; + *UID1 = *EFAddr++; + *UID2 = *EFAddr++; + *UID3 = *EFAddr; + md_fc_enable_flash_prefetch(FC); + } + else + { + EFAddr = (uint32_t *)(FLASH_INFO_BASE + U_ID); + *UID0 = *EFAddr++; + *UID1 = *EFAddr++; + *UID2 = *EFAddr++; + *UID3 = *EFAddr; + } + + return status; +} + +void md_fc_protect_bit(uint8_t page, uint32_t *UPH, uint32_t *UPL) +{ + if (page < 128) + { + *UPL &= (~(1 << (page / 4))); + *UPH &= 0xFFFFFFFF; + } + else + { + *UPL &= 0xFFFFFFFF; + *UPH &= (~(1 << ((page - 128) / 4))); + } +} + +void md_fc_protect_bit_s(uint8_t sector, uint32_t *UPH, uint32_t *UPL) +{ + if (sector < 32) + { + *UPL &= (~(1 << sector)); + *UPH &= 0xFFFFFFFF; + } + else + { + *UPL &= 0xFFFFFFFF; + *UPH &= (~(1 << (sector - 32))); + } +} + +/** + * @} MD_FC_Public_Functions + */ + +/** + * @} FC + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_fc.h b/os/common/ext/CMSIS/ES32/FS026/md/md_fc.h new file mode 100644 index 00000000000..13bbd670215 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_fc.h @@ -0,0 +1,893 @@ +/********************************************************************************** + * + * @file md_fc.h + * @brief header file of md_fc.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 25 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_FC_H__ +#define __MD_FC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_FC FC + * @brief FC micro driver + * @{ + */ + +/** @defgroup MD_FC_Pubulic_Types FC Pubulic Types + * @{ + */ + +/** + * @brief MD FC Parameter Structure definition + */ +typedef struct +{ + uint32_t SAddr; /*!< Specifies the FC sector address to be erased. + This parameter should be aligned with 0x400*/ + + uint32_t SAddrC; /*!< Specifies the complement of FC sector address to be erased. + This parameter should be the complement of FC page address*/ + + uint16_t BCnt; /*!< Specifies the control byte count. + For program, this parameter should be aligned with 8 and smaller than 0x400 + For read, this parameter should be aligned with 4*/ + + uint32_t *pU32Buf; /*!< Specifies the uint32_t data buffer to program. + This parameter should be the pointer to uint32_t*/ + +} md_fc_ControlTypeDef; + +/** + * @brief MD FC Update Protect Level Structure definition + */ +typedef struct +{ + uint32_t UpdateL; /*!< Specifies the protect sector bit mapping low byte (sector 31~0) (0=protect, 1=unprotect). + This parameter can be any value between 0~65535*/ + + uint32_t UpdateH; /*!< Specifies the protect sector bit mapping high byte (sector 63~32) (0=protect, 1=unprotect). + This parameter can be any value between 0~65535*/ + +} md_fc_UpdProtTypeDef; + +/** + * @} + */ + +/** @defgroup MD_FC_Public_Macros FC Public Macros + * @{ + */ + +#define CHIP_ID 0x08A0 +#define U_ID 0x08A4 + +#define Level0 0xaaaaaaaa +#define Level1 0xbbbbbbbb +#define Level2 0xcccccccc + +#define MD_FC_PC_EF_MPAGESZ (0x00000200UL) /** @brief Select main page size */ +#define MD_FC_PC_EF_IPAGESZ (0x00000200UL) /** @brief Select information page size */ +#define MD_FC_PC_EF_MERASEID (0xA5A5AA55UL) /** @brief Select main erase ID */ + +#define MD_FC_PC_EF_UL_LOCK (0x00000000UL) /** @brief EF Lock Key */ +#define MD_FC_PC_EF_UL_KEY1 (0x00112233UL) /** @brief EF Unlock Key1 */ +#define MD_FC_PC_EF_UL_KEY2 (0x55667788UL) /** @brief EF Unlock Key2 */ + +#define MD_FC_CMD_PROG_EFLASH (0xF0) /** @brief Program EFlash */ +#define MD_FC_CMD_PAGE_ERASE (0xF1) /** @brief Page Erase */ +#define MD_FC_CMD_SECTOR_ERASE (0xF2) /** @brief Sector Erase */ +#define MD_FC_CMD_FULL_ERASE (0xF3) /** @brief Full Erase */ +#define MD_FC_CMD_UCRP_PROTECT (0xF5) /** @brief UCRP Protect */ +#define MD_FC_CMD_RP_PROTECT (0xF6) /** @brief RP Protect */ +#define MD_FC_CMD_WP_PROTECT (0xF7) /** @brief WP Protect */ + +#define MD_FC_PC_SREMAP_MAIN (0x00) /** @brief Main Flash memory mapped at 0x0000 0000 */ +#define MD_FC_PC_SREMAP_BOOTROM (0x01) /** @brief Bootrom mapped at 0x0000 0000 */ +#define MD_FC_PC_SREMAP_SRAM (0x02) /** @brief SRAM mapped at 0x0000 0000 */ + +#define MD_FC_OPRLD_0XE (0xE ) /** @brief Fill in the fixed value 0xE to trigger configuration word reload */ + +#define MD_FC_WAIT_LESS_THAN_24MHz (0x0 ) /** @brief System frequency<24Mhz. */ +#define MD_FC_WAIT_BETWEEN_24MHz_AND_48Mhz (0x1 ) /** @brief System frequency>24Mhz and system frequency<=48Mhz. */ +#define MD_FC_WAIT_BETWEEN_48MHz_AND_72Mhz (0x2 ) /** @brief System frequency>48Mhz and system frequency<=72Mhz. */ +#define MD_FC_WAIT_MORE_THAN_72Mhz (0x3 ) /** @brief System frequency>72Mhz. */ + +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions FC Public Functions + * @{ + */ + +/** @defgroup MD_FC_Public_Functions_Group2 CMD + * @{ + */ +/** + * @brief Set FC CMD Flash Command + * @param fc FC Instance + * @param cmd Flash command + @arg @ref MD_FC_CMD_PROG_EFLASH(0xF0) : Program EFlash + @arg @ref MD_FC_CMD_PAGE_ERASE(0xF1) : Page Erase + @arg @ref MD_FC_CMD_SECTOR_ERASE(0xF2) : Sector Erase + @arg @ref MD_FC_CMD_FULL_ERASE(0xF3) : Full Erase + @arg @ref MD_FC_CMD_UCRP_PROTECT(0xF5) : UCRP Protect + @arg @ref MD_FC_CMD_RP_PROTECT(0xF6) : RP Protect + @arg @ref MD_FC_CMD_WP_PROTECTE(0xF7) : WP Protect + * @retval None + */ +__STATIC_INLINE void md_fc_set_flash_command(FC_TypeDef *fc, uint32_t Cmd) +{ + MODIFY_REG(fc->CMD, FC_CMD_CMD, Cmd); +} + +/** + * @brief Get FC CMD Flash Command + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_FC_CMD_PROG_EFLASH(0xF0) : Program EFlash + * @arg @ref MD_FC_CMD_PAGE_ERASE(0xF1) : Page Erase + * @arg @ref MD_FC_CMD_SECTOR_ERASE(0xF2) : Sector Erase + * @arg @ref MD_FC_CMD_FULL_ERASE(0xF3) : Full Erase + * @arg @ref MD_FC_CMD_UCRP_PROTECT(0xF5) : UCRP Protect + * @arg @ref MD_FC_CMD_RP_PROTECT(0xF6) : RP Protect + * @arg @ref MD_FC_CMD_WP_PROTECTE(0xF7) : WP Protect + */ +__STATIC_INLINE uint32_t md_fc_get_flash_command(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->CMD, FC_CMD_CMD)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group3 PA + * @{ + */ +/** + * @brief Set FC PA + * @param fc FC Instance + * @param pa Flash programming address + * @retval None + */ +__STATIC_INLINE void md_fc_set_pa(FC_TypeDef *fc, uint32_t pa) +{ + WRITE_REG(fc->PA, pa); +} + +/** + * @brief Get FC PA + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_fc_get_pa(FC_TypeDef *fc) +{ + return (uint32_t)(READ_REG(fc->PA)); +} + +/** + * @brief Set FC Program Counter + * @note Provide maximum 128 times continuous program without modify progeam address + * @param fc FC Instance + * @param pcnt Programming byte,pcnt > 0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_program_counter(FC_TypeDef *fc, uint32_t pcnt) +{ + MODIFY_REG(fc->PA, FC_PA_PCNT, ((((pcnt + 3) >> 2) - 1) << FC_PA_PCNT_POSS)); +} + +/** + * @brief Get FC Program Counter + * @note Provide maximum 128 times continuous program + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7f + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_program_counter(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->PA, FC_PA_PCNT) >> FC_PA_PCNT_POSS); +} + +/** + * @brief Enable FC Information Block + * @note User can program/erase Info. Block page 7 when Flash protect is disable + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE void md_fc_enable_info_region(FC_TypeDef *fc) +{ + SET_BIT(fc->PA, FC_PA_IFREN); +} + +/** + * @brief Disable FC Information Block + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE void md_fc_disable_info_region(FC_TypeDef *fc) +{ + CLEAR_BIT(fc->PA, FC_PA_IFREN); +} + +/** + * @brief Is FC Information Block Enabled + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint32_t md_fc_is_enabled_info_region(FC_TypeDef *fc) +{ + return (READ_BIT(fc->PA, FC_PA_IFREN) == (FC_PA_IFREN)); +} + +/** + * @brief Set FC Program/Erase Address + * @note Program : PROG_ADDR[12: 2] is word addressaddress + * @note Page Erase : PROG_ADDR[16: 9] is page address, and PROG_ADDR[8:0] don't care + * @note Sector Erase : PROG_ADDR[16:11] is sector address, and PROG_ADDR[10:0] don't care + * @note Macro Erase : PROG_ADDR[16: 0] don't care + * @param fc FC Instance + * @param PAddr Program/erase address + * @retval None + */ +__STATIC_INLINE void md_fc_set_program_address(FC_TypeDef *fc, uint32_t PAddr) +{ + MODIFY_REG(fc->PA, FC_PA_PA, PAddr); +} + +/** + * @brief Get FC Program/Erase Address + * @note Program : PROG_ADDR[12: 2] is word addressaddress + * @note Page Erase : PROG_ADDR[16: 9] is page address, and PROG_ADDR[8:0] don't care + * @note Sector Erase : PROG_ADDR[16:11] is sector address, and PROG_ADDR[10:0] don't care + * @note Macro Erase : PROG_ADDR[16: 0] don't care + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_fc_get_program_address(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->PA, FC_PA_PA)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group4 PLD + * @{ + */ +/** + * @brief Set FC Program Low Data + * @note Eflash supports 32 bits data program, this register provides Low 32 bits data + * @param fc FC Instance + * @param pld Flash programming data lower 32 bits + * @retval None + */ +__STATIC_INLINE void md_fc_set_program_data(FC_TypeDef *fc, uint32_t pld) +{ + MODIFY_REG(fc->PLD, FC_PLD_PLD, pld); +} + +/** + * @brief Get FC Program Low Data + * @note Eflash supports 32 bits data program, this register provides Low 32 bits data + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_program_data(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->PLD, FC_PLD_PLD)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group5 CTL + * @{ + */ +/** + * @brief Set FC CON + * @param fc FC Instance + * @param ctl Flash control register + * @retval None + */ +__STATIC_INLINE void md_fc_set_ctl(FC_TypeDef *fc, uint32_t ctl) +{ + WRITE_REG(fc->CTL, ctl); +} + +/** + * @brief Get FC CON + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_fc_get_ctl(FC_TypeDef *fc) +{ + return (uint32_t)(READ_REG(fc->CTL)); +} + +/** + * @brief Enable FC Control Sleep + * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE void md_fc_enable_flash_stop_mode(FC_TypeDef *fc) +{ + SET_BIT(fc->CTL, FC_CTL_FCSLEEP); +} + +/** + * @brief Disable FC Control Sleep + * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE void md_fc_disable_flash_stop_mode(FC_TypeDef *fc) +{ + CLEAR_BIT(fc->CTL, FC_CTL_FCSLEEP); +} + +/** + * @brief Is FC Control Sleep Enabled + * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. + * @param fc FC Instance + * @retval The retval can be one of the following values: + * 0x0:Disable Flash sleep mask function + * 0x1:Enable Flash sleep mask function + */ +__STATIC_INLINE uint8_t md_fc_is_enabled_flash_stop_mode(FC_TypeDef *fc) +{ + return (READ_BIT(fc->CTL, FC_CTL_FCSLEEP) == (FC_CTL_FCSLEEP)); +} + +/** + * @brief Enable FC Control PreFetch + * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE void md_fc_enable_flash_prefetch(FC_TypeDef *fc) +{ + SET_BIT(fc->CTL, FC_CTL_PFEN); +} + +/** + * @brief Disable FC Control PreFetch + * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE void md_fc_disable_flash_prefetch(FC_TypeDef *fc) +{ + CLEAR_BIT(fc->CTL, FC_CTL_PFEN); +} + +/** + * @brief Is FC Control PreFetch Enabled + * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read + * @param fc FC Instance + * @retval The retval can be one of the following values: + * 0x0:Disable pre-fetch function + * 0x1:Enable pre-fetch function + */ +__STATIC_INLINE uint8_t md_fc_is_enabled_flash_prefetch(FC_TypeDef *fc) +{ + return (READ_BIT(fc->CTL, FC_CTL_PFEN) == (FC_CTL_PFEN)); +} + +/** + * @brief Set FC Control Configuration word load key + * @note Fill in the fixed value 0xE to trigger the configuration word reload + * @param fc FC Instance + * @param oprld Configuration word load key + * @arg @ref MD_FC_OPRLD_0XE + * @retval None + */ +__STATIC_INLINE void md_fc_set_option_byte_reload(FC_TypeDef *fc, uint32_t oprld) +{ + MODIFY_REG(fc->CTL, FC_CTL_OPRLD, oprld << FC_CTL_OPRLD_POSS); +} + +/** + * @brief Set FC Control Wait Cycle + * @param fc FC Instance + * @param Wait Flash read wait cycle + @arg @ref MD_FC_WAIT_LESS_THAN_24MHz + @arg @ref MD_FC_WAIT_BETWEEN_24MHz_AND_48Mhz + @arg @ref MD_FC_WAIT_BETWEEN_48MHz_AND_72Mhz + @arg @ref MD_FC_WAIT_MORE_THAN_72Mhz + * @retval None + */ +__STATIC_INLINE void md_fc_set_read_latency(FC_TypeDef *fc, uint32_t Wait) +{ + MODIFY_REG(fc->CTL, FC_CTL_WAIT, Wait << FC_CTL_WAIT_POSS); +} + +/** + * @brief Get FC Control Wait Cycle + * @param fc FC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_FC_WAIT_LESS_THAN_24MHz + @arg @ref MD_FC_WAIT_BETWEEN_24MHz_AND_48Mhz + @arg @ref MD_FC_WAIT_BETWEEN_48MHz_AND_72Mhz + @arg @ref MD_FC_WAIT_MORE_THAN_72Mhz + */ +__STATIC_INLINE uint32_t md_fc_get_read_latency(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->CTL, FC_CTL_WAIT) >> FC_CTL_WAIT_POSS); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group6 STAT + * @{ + */ +/** + * @brief Get FC STAT + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_sta(FC_TypeDef *fc) +{ + return (uint32_t)(READ_REG(fc->STAT)); +} + +/** + * @brief Get FC Option Byte reload times + * @note This bit is set when Option Byte Data is valid + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_option_byte_reload_times(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->STAT, FC_STA_OPRLDLOOP) >> FC_STA_OPRLDLOOP_POSS); +} + +/** + * @brief Set Protection area read status + * @param fc FC Instance + * @retval none + */ +__STATIC_INLINE void md_fc_clear_flag_protect_area_read(FC_TypeDef *fc) +{ + SET_BIT(fc->STAT, FC_STA_PRTAREARD); +} + +/** + * @brief Get Protection area read status + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Value 0x1 : An illegal action occurred in the program area to read the data in the protected area + * @arg Value 0x0 : The protected area has not been read + */ +__STATIC_INLINE uint32_t md_fc_is_active_flag_protect_area_read(FC_TypeDef *fc) +{ + return (READ_BIT(fc->STAT, FC_STA_PRTAREARD) == (FC_STA_PRTAREARD)); +} + +/** + * @brief Set Protected area operating status + * @param fc FC Instance + * @retval none + */ +__STATIC_INLINE void md_fc_clear_flag_protect_area_write(FC_TypeDef *fc) +{ + SET_BIT(fc->STAT, FC_STA_PRTAREAWR); +} + +/** + * @brief Get FC Protected area operating status + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Value 0x1 : An illegal action in the operation protection zone of the program area has occurred + * @arg Value 0x0 : The protected area has not been operated by Program/Erase + */ +__STATIC_INLINE uint32_t md_fc_is_active_flag_protect_area_write(FC_TypeDef *fc) +{ + return (READ_BIT(fc->STAT, FC_STA_PRTAREAWR) == (FC_STA_PRTAREAWR)); +} + +/** + * @brief Get FC_CMD register protection status + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Value 0x1 : FC_CMD register is unlocked + * @arg Value 0x0 : FC_CMD register lock + */ +__STATIC_INLINE uint32_t md_fc_is_active_flag_flash_unlock(FC_TypeDef *fc) +{ + return (READ_BIT(fc->STAT, FC_STA_CMDULK) == (FC_STA_CMDULK)); +} + +/** + * @brief Get Flash Controller Busy Status + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Value 0x1 : Flash controller busy + * @arg Value 0x0 : Flash controller idle + */ +__STATIC_INLINE uint32_t md_fc_is_active_flag_flash_busy(FC_TypeDef *fc) +{ + return (READ_BIT(fc->STAT, FC_STA_FCBUSY) == (FC_STA_FCBUSY)); +} + +/** + * @brief Get Program area write protection (WP) protection status + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Value 0x1 : Protection function is not turned on + * @arg Value 0x0 : Protection function is on + */ +__STATIC_INLINE uint32_t md_fc_is_active_flag_wp_disable(FC_TypeDef *fc) +{ + return (READ_BIT(fc->STAT, FC_STA_WPDIS) == (FC_STA_WPDIS)); +} + +/** + * @brief Get Program area read protection (RP) protection status + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Value 0x2 : Read protection level is Lv2 + * @arg Value 0x1 : Read protection level is Lv1 + * @arg Value 0x0 : Read protection level is Lv0 + */ +__STATIC_INLINE uint32_t md_fc_get_rp_level(FC_TypeDef *fc) +{ + return (READ_BIT(fc->STAT, FC_STA_RPLV) >> FC_STA_RPLV_POSS); +} + +/** + * @brief Get Program area user code readout protection (UCRP) protection status + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Value 0x1 : Protection function is not turned on + * @arg Value 0x0 : Protection function is on + */ +__STATIC_INLINE uint32_t md_fc_is_active_flag_ucrp_disable(FC_TypeDef *fc) +{ + return (READ_BIT(fc->STAT, FC_STA_UCRPDIS) == (FC_STA_UCRPDIS)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group7 UPL + * @{ + */ +/** + * @brief Set FC Protect Update Low Data + * @note Update main block Protect setting 0 + * @param fc FC Instance + * @param upl Update protection setting low 32 bits + * @retval None + */ +__STATIC_INLINE void md_fc_set_protect0(FC_TypeDef *fc, uint32_t upl) +{ + MODIFY_REG(fc->UPL, FC_UPL_UPL, upl); +} + +/** + * @brief Get FC Protect Update Low Data + * @note Update main block Protect setting 0 + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_fc_get_protect0(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->UPL, FC_UPL_UPL)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group8 UPH + * @{ + */ +/** + * @brief Set FC Protect Update High Data + * @note Update main block Protect setting 1 + * @param fc FC Instance + * @param uph Update protection setting High 32 bits + * @retval None + */ +__STATIC_INLINE void md_fc_set_protect1(FC_TypeDef *fc, uint32_t uph) +{ + MODIFY_REG(fc->UPH, FC_UPH_UPH, uph); +} + +/** + * @brief Get FC Protect Update High Data + * @note Update main block Protect setting 1 + * @param fc FC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_fc_get_protect1(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->UPH, FC_UPH_UPH)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group9 UL + * @{ + */ +/** + * @brief Set FC Flash control unlock key + * @note 0x00112233 / 0x55667788 + * @param fc FC Instance + * @param ul Flash control unlock key + @arg @ref MD_FC_PC_EF_UL_LOCK + @arg @ref MD_FC_PC_EF_UL_KEY1 + @arg @ref MD_FC_PC_EF_UL_KEY2 + * @retval None + */ +__STATIC_INLINE void md_fc_set_flash_unlock(FC_TypeDef *fc, uint32_t ul) +{ + MODIFY_REG(fc->UL, FC_UL_UL, ul); +} + +/** + * @brief Get FC Flash control unlock key + * @note 0x00112233 / 0x55667788 + * @param fc FC Instance + * @retval The retval can be one of the following values: + @arg @ref MD_FC_PC_EF_UL_LOCK + @arg @ref MD_FC_PC_EF_UL_KEY1 + @arg @ref MD_FC_PC_EF_UL_KEY2 + */ +__STATIC_INLINE uint32_t md_fc_get_flash_unlock(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->UL, FC_UL_UL)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group10 UCRPL + * @{ + */ +/** + * @brief Get Flash configuration word user code read protection setting low 32 bits + * @note Program area Sector 31 ~ Sector 0 user code readout protection settings + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_ucrp0(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->UCRPL, FC_UCRPL_UCRPL)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group11 UCRPH + * @{ + */ +/** + * @brief Get Flash configuration word user code read protection setting high 32 bits + * @note Program area Sector 63 ~ Sector 32 user code readout protection settings + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_ucrp1(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->UCRPH, FC_UCRPH_UCRPH)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group12 RP + * @{ + */ +/** + * @brief Get Flash configuration word read protection setting + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg 0xAAAAAAAA: Lv0 + * @arg 0xCCCCCCCC: Lv2 + * @arg else: Lv1 + */ +__STATIC_INLINE uint32_t md_fc_get_rp(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->RP, FC_RP_RP)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group13 WPL + * @{ + */ +/** + * @brief Get Flash memory configuration word write protection setting low 32 bits + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_wp0(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->WPL, FC_WPL_WPL)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group14 WPH + * @{ + */ +/** + * @brief Get Flash memory configuration word write protection setting high 32 bits + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_wp1(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->WPH, FC_WPH_WPH)); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group15 REMAP + * @{ + */ +/** + * @brief Get FC REMAP + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_remap(FC_TypeDef *fc) +{ + return (uint32_t)(READ_REG(fc->REMAP)); +} + +/** + * @brief Get FC Hardware Remap Option + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @arg Value 0xa5 skip bootroom + */ +__STATIC_INLINE uint8_t md_fc_get_option_bootrom_bypass(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->REMAP, FC_REMAP_BOOTBYP) >> FC_REMAP_BOOTBYP_POSS); +} + +/** + * @brief Get FC Software Remap Option + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_FC_PC_SREMAP_MAIN(0x0) : Main Flash memory mapped at 0x0000 0000 + * @arg @ref MD_FC_PC_SREMAP_BOOTROM(0x1) : Bootrom mapped at 0x0000 0000 + * @arg @ref MD_FC_PC_SREMAP_SRAM(0x2) : SRAM mapped at 0x0000 0000 + * @arg Else : Reserved + */ +__STATIC_INLINE uint8_t md_fc_get_option_memory_mapping(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->REMAP, FC_REMAP_SELECT) >> FC_REMAP_SELECT_POSS); +} + +/** + * @brief Get FC Software Remap Base Address Settng Data + * @note If set 0x1, it means second 4k Byte, If set 0x2, it means third 4k Byte, and so on + * @note This value is invalid if the value in SREMAP field is 0x3 + * @param fc FC Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x1f + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_fc_get_option_flash_remap_base(FC_TypeDef *fc) +{ + return (uint32_t)(READ_BIT(fc->REMAP, FC_REMAP_SEFBASE) >> FC_REMAP_SEFBASE_POSS); +} +/** + * @} + */ + +/** @defgroup MD_FC_Public_Functions_Group1 Initialization + * @{ + */ +ErrorStatus md_fc_unlock(void); +ErrorStatus md_fc_lock(void); +ErrorStatus md_fc_main_erase(uint32_t MEraseID); +ErrorStatus md_fc_sector_erase(md_fc_ControlTypeDef *pSErasePara); +ErrorStatus md_fc_page_erase(md_fc_ControlTypeDef *pSErasePara); +ErrorStatus md_fc_info_page_erase(md_fc_ControlTypeDef *pSErasePara); +ErrorStatus md_fc_program(md_fc_ControlTypeDef *pProgramPara); +ErrorStatus md_fc_info_program(md_fc_ControlTypeDef *pProgramPara); +ErrorStatus md_fc_read(md_fc_ControlTypeDef *pReadPara); +ErrorStatus md_fc_update_ucrp(md_fc_UpdProtTypeDef *pUpdateBit); +ErrorStatus md_fc_update_rp(uint32_t); +ErrorStatus md_fc_update_wp(md_fc_UpdProtTypeDef *pUpdateBit); +ErrorStatus md_fc_clear_ucrp(void); +ErrorStatus md_fc_clear_wp(void); +ErrorStatus md_fc_clear_user_option(void); +ErrorStatus md_fc_option_byte_reload(void); +ErrorStatus md_fc_read_info(uint32_t info_addr, uint32_t *info); +ErrorStatus md_fc_read_chipid(uint32_t *); +ErrorStatus md_fc_read_uid(uint32_t *, uint32_t *, uint32_t *, uint32_t *); +void md_fc_protect_bit(uint8_t, uint32_t *, uint32_t *); +void md_fc_protect_bit_s(uint8_t, uint32_t *, uint32_t *); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ + diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_gpio.c b/os/common/ext/CMSIS/ES32/FS026/md/md_gpio.c new file mode 100644 index 00000000000..79d1dca466d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_gpio.c @@ -0,0 +1,219 @@ +/********************************************************************************** + * + * @file md_rcu.c + * @brief md_rcu C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 21 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_gpio.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) + +/** @defgroup GPIO GPIO + * @brief GPIO micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/** @defgroup MD_GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_MD_GPIO_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__ == GPIOA) \ + || (__INSTANCE__ == GPIOB) \ + || (__INSTANCE__ == GPIOC) \ + || (__INSTANCE__ == GPIOD)) + +#define IS_MD_GPIO_PIN(__VALUE__) (((__VALUE__) == MD_GPIO_PIN_0) \ + || ((__VALUE__) == MD_GPIO_PIN_1) \ + || ((__VALUE__) == MD_GPIO_PIN_2) \ + || ((__VALUE__) == MD_GPIO_PIN_3) \ + || ((__VALUE__) == MD_GPIO_PIN_4) \ + || ((__VALUE__) == MD_GPIO_PIN_5) \ + || ((__VALUE__) == MD_GPIO_PIN_6) \ + || ((__VALUE__) == MD_GPIO_PIN_7) \ + || ((__VALUE__) == MD_GPIO_PIN_8) \ + || ((__VALUE__) == MD_GPIO_PIN_9) \ + || ((__VALUE__) == MD_GPIO_PIN_10) \ + || ((__VALUE__) == MD_GPIO_PIN_11) \ + || ((__VALUE__) == MD_GPIO_PIN_12) \ + || ((__VALUE__) == MD_GPIO_PIN_13) \ + || ((__VALUE__) == MD_GPIO_PIN_14) \ + || ((__VALUE__) == MD_GPIO_PIN_15)) \ + +#define IS_MD_GPIO_MODE(__VALUE__) (((__VALUE__) == MD_GPIO_MODE_INPUT) \ + || ((__VALUE__) == MD_GPIO_MODE_OUTPUT) \ + || ((__VALUE__) == MD_GPIO_MODE_FUNCTION) \ + || ((__VALUE__) == MD_GPIO_MODE_ANALOG)) + +#define IS_MD_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == MD_GPIO_OUTPUT_PUSHPULL) \ + || ((__VALUE__) == MD_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_MD_GPIO_PULL(__VALUE__) (((__VALUE__) == MD_GPIO_PULL_FLOATING) \ + || ((__VALUE__) == MD_GPIO_PULL_UP) \ + || ((__VALUE__) == MD_GPIO_PULL_DOWN)) + +#define IS_MD_GPIO_DS(__VALUE__) (((__VALUE__) == MD_GPIO_DRIVING_8MA) \ + || ((__VALUE__) == MD_GPIO_DRIVING_16MA)) + +#define IS_MD_GPIO_FUNCTION(__VALUE__) (((__VALUE__) == MD_GPIO_AF0) \ + || ((__VALUE__) == MD_GPIO_AF1) \ + || ((__VALUE__) == MD_GPIO_AF2) \ + || ((__VALUE__) == MD_GPIO_AF3) \ + || ((__VALUE__) == MD_GPIO_AF4) \ + || ((__VALUE__) == MD_GPIO_AF5) \ + || ((__VALUE__) == MD_GPIO_AF6) \ + || ((__VALUE__) == MD_GPIO_AF7)) + +#define IS_MD_GPIO_IST(__VALUE__) (((__VALUE__) == MD_GPIO_IST_TTL) \ + || ((__VALUE__) == MD_GPIO_IST_CMOS)) + +/** + * @} MD_GPIO_Private_Macros + */ + +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @addtogroup MD_GPIO_PF_Init GPIO Public Init Functions + * @{ + */ + +/** + * @brief De-initialize the GPIO registers to their default reset values. + * @param GPIOx GPIO Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: GPIO registers are not de-initialized + */ +ErrorStatus md_gpio_deinit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_MD_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force reset of GPIO clock */ + if (GPIOx == GPIOA) + { + md_rcu_enable_gpioa_reset(RCU); + md_rcu_disable_gpioa_reset(RCU); + } + else if (GPIOx == GPIOB) + { + md_rcu_enable_gpiob_reset(RCU); + md_rcu_disable_gpiob_reset(RCU); + } + else if (GPIOx == GPIOC) + { + md_rcu_enable_gpioc_reset(RCU); + md_rcu_disable_gpioc_reset(RCU); + } + else /* if(GPIOx==GPIOD) */ + { + md_rcu_enable_gpiod_reset(RCU); + md_rcu_disable_gpiod_reset(RCU); + } + + status = SUCCESS; + + return status; +} + +/** + * @brief Initialize the GPIO registers according to the specified parameters in GPIO_InitStruct. + * @note As some bits in GPIO configuration registers can only be written when the GPIO is disabled (GPIO_CR1_SPE bit =0), + * GPIO IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param GPIOx GPIO Instance + * @param GPIO_InitStruct pointer to a @ref md_gpio_inittypedef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus md_gpio_init(GPIO_TypeDef *GPIOx, md_gpio_inittypedef *GPIO_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the GPIO Instance GPIOx*/ + assert_param(IS_MD_GPIO_ALL_INSTANCE(GPIOx)); + + /* Check the GPIO parameters from GPIO_InitStruct*/ + assert_param(IS_MD_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_MD_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_MD_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + assert_param(IS_MD_GPIO_PULL(GPIO_InitStruct->Pull)); + assert_param(IS_MD_GPIO_DS(GPIO_InitStruct->OutDrive)); + assert_param(IS_MD_GPIO_FUNCTION(GPIO_InitStruct->Function)); + + if (POSITION_VAL(GPIO_InitStruct->Pin) <= 7) + { + md_gpio_set_pin_function0_7(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Function); + } + else + { + md_gpio_set_pin_function8_15(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Function); + } + + md_gpio_set_pin_output_type(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + md_gpio_set_pin_pull(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Pull); + md_gpio_set_pin_outputdriving(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutDrive); + md_gpio_set_pin_mode(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Mode); + + status = SUCCESS; + + return status; +} + +/** + * @} MD_GPIO_PF_Init + */ + +/** + * @} MD_GPIO_Public_Functions + */ + +/** + * @} GPIO + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_gpio.h b/os/common/ext/CMSIS/ES32/FS026/md/md_gpio.h new file mode 100644 index 00000000000..873e6bd5a37 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_gpio.h @@ -0,0 +1,1093 @@ +/********************************************************************************** + * + * @file md_gpio.h + * @brief header file of md_gpio.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 21 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_GPIO_H__ +#define __MD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_GPIO GPIO + * @brief GPIO micro driver + * @{ + */ + +/** @defgroup MD_GPIO_Pubulic_Types GPIO Pubulic Types + * @{ + */ + +/** + * @brief MD GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref MD_GPIO_PC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_mode().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_OT. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_output_type().*/ + + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_pull().*/ + + uint32_t OutDrive; /*!< Specifies the output driving current for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_DS. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_get_ds().*/ + + uint32_t Function; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_FUNCTION. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_function0_7() and md_gpio_set_function8_15().*/ +} md_gpio_inittypedef; + +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Macros GPIO Public Macros + * @{ + */ + +/** + * @brief MD_GPIO_PIN Pin + */ +#define MD_GPIO_PIN_0 (0x0001U) /*!< Select pin 0 */ +#define MD_GPIO_PIN_1 (0x0002U) /*!< Select pin 1 */ +#define MD_GPIO_PIN_2 (0x0004U) /*!< Select pin 2 */ +#define MD_GPIO_PIN_3 (0x0008U) /*!< Select pin 3 */ +#define MD_GPIO_PIN_4 (0x0010U) /*!< Select pin 4 */ +#define MD_GPIO_PIN_5 (0x0020U) /*!< Select pin 5 */ +#define MD_GPIO_PIN_6 (0x0040U) /*!< Select pin 6 */ +#define MD_GPIO_PIN_7 (0x0080U) /*!< Select pin 7 */ +#define MD_GPIO_PIN_8 (0x0100U) /*!< Select pin 8 */ +#define MD_GPIO_PIN_9 (0x0200U) /*!< Select pin 9 */ +#define MD_GPIO_PIN_10 (0x0400U) /*!< Select pin 10 */ +#define MD_GPIO_PIN_11 (0x0800U) /*!< Select pin 11 */ +#define MD_GPIO_PIN_12 (0x1000U) /*!< Select pin 12 */ +#define MD_GPIO_PIN_13 (0x2000U) /*!< Select pin 13 */ +#define MD_GPIO_PIN_14 (0x4000U) /*!< Select pin 14 */ +#define MD_GPIO_PIN_15 (0x8000U) /*!< Select pin 15 */ +#define MD_GPIO_PIN_ALL (0xFFFFU) /*!< Select all pins */ + +/** + * @brief MD_GPIO_LCK Lock + */ +#define MD_GPIO_UNLOCK (0x00000000UL) /** @brief Select input mode */ +#define MD_GPIO_LOCK (0X00000001UL) /** @brief Select output mode */ + + +/** + * @brief MD_GPIO_MODE Mode + */ +#define MD_GPIO_MODE_INPUT (0x00000000UL) /** @brief Select input mode */ +#define MD_GPIO_MODE_OUTPUT (0X00000001UL) /** @brief Select output mode */ +#define MD_GPIO_MODE_FUNCTION (0X00000002UL) /** @brief Select function mode */ +#define MD_GPIO_MODE_ANALOG (0x00000003UL) /** @brief Select analog mode */ + +/** + * @brief MD_GPIO_OT Output Type + */ +#define MD_GPIO_OUTPUT_PUSHPULL (0x00000000U) /** @brief Select push-pull as output type */ +#define MD_GPIO_OUTPUT_OPENDRAIN (0x00000001U) /** @brief Select open-drain as output type */ + +/** + * @brief MD_GPIO_PULL FLOATING/ Pull Up / Pull Down + */ +#define MD_GPIO_PULL_FLOATING (0x00000000UL) /** @brief Select I/O no pull */ +#define MD_GPIO_PULL_UP (0x00000001UL) /** @brief Select I/O pull up */ +#define MD_GPIO_PULL_DOWN (0x00000002UL) /** @brief Select I/O pull down */ + +/** + * @brief MD_GPIO_DS Output driving/sinking current + */ +#define MD_GPIO_DRIVING_16MA (0x00000001U) /** @brief Select I/O 16mA driving/sinking current */ +#define MD_GPIO_DRIVING_8MA (0x00000000U) /** @brief Select I/O 8mA driving/sinking current */ + +/** + * @brief MD_GPIO_FUNCTION Alternate Function + */ +#define MD_GPIO_AF0 (0x00000000UL) /** @brief Select alternate function 0 */ +#define MD_GPIO_AF1 (0x00000001UL) /** @brief Select alternate function 1 */ +#define MD_GPIO_AF2 (0x00000002UL) /** @brief Select alternate function 2 */ +#define MD_GPIO_AF3 (0x00000003UL) /** @brief Select alternate function 3 */ +#define MD_GPIO_AF4 (0x00000004UL) /** @brief Select alternate function 4 */ +#define MD_GPIO_AF5 (0x00000005UL) /** @brief Select alternate function 5 */ +#define MD_GPIO_AF6 (0x00000006UL) /** @brief Select alternate function 6 */ +#define MD_GPIO_AF7 (0x00000007UL) /** @brief Select alternate function 7 */ +#define MD_GPIO_AF8 (0x00000008UL) /** @brief Select alternate function 8 */ +#define MD_GPIO_AF9 (0x00000009UL) /** @brief Select alternate function 9 */ + +/** + * @brief MD_GPIO_FILTER Input Filter + */ +#define MD_GPIO_FILTER_BYPASS (0x00000000UL) /** @brief Select bypass */ +#define MD_GPIO_FILTER_GLITCH (0x00000001UL) /** @brief Select glitch free for 20ns plus */ + +/** + * @brief MD_GPIO_IST Input Type + */ +#define MD_GPIO_IST_TTL (0x00000000UL) /** @brief Select TTL IO Level */ +#define MD_GPIO_IST_CMOS (0x00000001UL) /** @brief Select CMOS IO Level */ + +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @defgroup MD_GPIO_Public_Functions_Group2 ID + * @{ + */ +/** + * @brief Return full input data register value for a dedicated port. + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t md_gpio_get_inputport(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ID)); +} + +/** + * @brief Return input pin data. + * @param GPIOx GPIO Port + * @param pin each pin of the port + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Input pin data value of port + * @arg @ref 0 0r 1 + */ + +__STATIC_INLINE uint32_t md_gpio_get_inputpinset(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + return (READ_BIT(GPIOx->ID, pin) == pin); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group3 OD + * @{ + */ +/** + * @brief Write output data register for the port. + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_outputport(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->OD, PortValue); +} + +/** + * @brief Read output data register for the port. + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t md_gpio_get_outputport(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->OD)); +} + +/** + * @brief Set output pin data. + * @param GPIOx GPIO Port + * @param pin each pin of the port + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_outputpinset(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->OD, pin); +} + +/** + * @brief Return output pin data. + * @param GPIOx GPIO Port + * @param pin each pin of the port + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Input pin data value of port + * @arg @ref 0 0r 1 + */ +__STATIC_INLINE uint32_t md_gpio_get_outputpinset(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + return (READ_BIT(GPIOx->OD, pin) == pin); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group4 BSBR + * @{ + */ +/** + * @brief Set several pins to high level on dedicated gpio port. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_high(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSBR, PinMask); +} + +/** + * @brief Reset several pins to low level on dedicated gpio port. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_low(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSBR, (PinMask << 16)); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group5 LCK + * @{ + */ +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note LOCK key write sequence: + * WR GPIOx_LCK = (~LCK[15:0]<<16) + LCK[15:0] + * WR GPIOx_LCK = (~LCK[15:0]<<16) + LCK[15:0] + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @param PinLock This parameter can be one of the following values: + * @arg @ref MD_GPIO_UNLOCK + * @arg @ref MD_GPIO_LOCK + * @retval None + */ +__STATIC_INLINE void md_gpio_set_lockpin(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t PinLock) +{ + WRITE_REG(GPIOx->LCK, ((~(GPIOx->LCK | PinLock << (POSITION_VAL(Pin))) << 16) | (GPIOx->LCK | PinLock << (POSITION_VAL(Pin))))); + WRITE_REG(GPIOx->LCK, ((~(GPIOx->LCK | PinLock << (POSITION_VAL(Pin))) << 16) | (GPIOx->LCK | PinLock << (POSITION_VAL(Pin))))); +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_gpio_get_lockpin(GPIO_TypeDef *GPIOx, uint32_t PinLock) +{ + return ((READ_BIT(GPIOx->LCK, PinLock) == (PinLock))); +} + +/** + * @brief Get Lock key is enabled + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_gpio_is_enabled_anylockpin(GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCK, GPIO_LCK_LCKK) == (GPIO_LCK_LCKK))); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group6 MOD + * @{ + */ +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, output mode, Alternate function mode, or Analog mode. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref MD_GPIO_MODE_INPUT + * @arg @ref MD_GPIO_MODE_OUTPUT + * @arg @ref MD_GPIO_MODE_FUNCTION + * @arg @ref MD_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_mode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MOD, (GPIO_MOD_MOD0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, output mode, Alternate function mode, or Analog mode. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_MODE_INPUT + * @arg @ref MD_GPIO_MODE_OUTPUT + * @arg @ref MD_GPIO_MODE_FUNCTION + * @arg @ref MD_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t md_gpio_get_pin_mode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MOD, (GPIO_MOD_MOD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group7 PUD + * @{ + */ +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref MD_GPIO_PULL_FLOATING + * @arg @ref MD_GPIO_PULL_UP + * @arg @ref MD_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_pull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUD, (GPIO_PUD_PUD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_PULL_FLOATING + * @arg @ref MD_GPIO_PULL_UP + * @arg @ref MD_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t md_gpio_get_pin_pull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUD, (GPIO_PUD_PUD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group8 OT + * @{ + */ +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @param GPIOx GPIO Port + * @param Pin This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param OutputType This parameter can be one of the following values: + * @arg @ref MD_GPIO_OUTPUT_PUSHPULL + * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_output_type(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OT, (GPIO_OT_OT0 << (POSITION_VAL(Pin))), (OutputType << (POSITION_VAL(Pin)))); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_OUTPUT_PUSHPULL + * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t md_gpio_get_pin_output_type(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)((READ_BIT(GPIOx->OT, (GPIO_OT_OT0 << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))) & (0x1U)); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group9 DS + * @{ + */ +/** + * @brief Configure gpio output driving/sinking current a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Odrv This parameter can be one of the following values: + * @arg @ref MD_GPIO_DRIVING_8MA + * @arg @ref MD_GPIO_DRIVING_16MA + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_outputdriving(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Odrv) +{ + MODIFY_REG(GPIOx->DS, (GPIO_DS_DS0 << (POSITION_VAL(Pin))), (Odrv << (POSITION_VAL(Pin)))); +} + +/** + * @brief Return gpio output driving/sinking current a dedicated pin on a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_DRIVING_8MA + * @arg @ref MD_GPIO_DRIVING_16MA + */ +__STATIC_INLINE uint32_t md_gpio_get_pin_outputdriving(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->DS, (GPIO_DS_DS0 << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group10 FIR + * @{ + */ +/** + * @brief Enable input filter register for the port. + * @note These bits are written by software to configure + * the input signal over thought a glitch filter. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_enable_pin_filter(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + SET_BIT(GPIOx->FIR, Pin); +} + + +/** + * @brief Disable input filter register for the port. + * @note These bits are written by software to configure + * the input signal over thought a glitch filter. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_disable_pin_filter(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + CLEAR_BIT(GPIOx->FIR, Pin); +} + +/** + * @brief Check if input filter register for the port is enabled. + * @note These bits are written by software to configure + * the input signal over thought a glitch filter. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE uint32_t md_gpio_is_enabled_pin_filter(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + + return ((READ_BIT(GPIOx->FIR, Pin) == (Pin))); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group11 IST + * @{ + */ +/** + * @brief Set gpio Input Schmitt Trigger for GPIO_FIR register. + * @param GPIOx GPIO Port + * @param Pin_Ist This parameter sets the required pin Input Schmitt Trigger + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pinist(GPIO_TypeDef *GPIOx, uint32_t Pin_Ist) +{ + WRITE_REG(GPIOx->IST, Pin_Ist); +} + +/** + * @brief Get gpio Input Schmitt Trigger for GPIO_OT register. + * @param GPIOx GPIO Port + * @retval Return the Input Schmitt Trigger of each pin + */ +__STATIC_INLINE uint32_t md_gpio_get_pinist(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)READ_REG(GPIOx->IST); +} + +/** + * @brief Configure GPIOx port Input Schmitt Trigger Register. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Iolev This parameter can be one of the following values: + * @arg @ref MD_GPIO_IST_TTL + * @arg @ref MD_GPIO_IST_CMOS + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_type(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Iolev) +{ + MODIFY_REG(GPIOx->IST, (GPIO_IST_IST0 << (POSITION_VAL(Pin))), (Iolev << (POSITION_VAL(Pin)))); +} + +/** + * @brief Return GPIOx port Input Schmitt Trigger Register + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval The retval can be one of the following values: + * @arg @ref MD_GPIO_IST_TTL + * @arg @ref MD_GPIO_IST_CMOS + */ +__STATIC_INLINE uint32_t md_gpio_get_pin_type(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->IST, (GPIO_IST_IST0 << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group12 AFL + * @{ + */ +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from FUNCTION0 to FUNCTION7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @param Function This parameter can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_function0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Function) +{ + MODIFY_REG(GPIOx->AFL, (GPIO_AFL_AF0 << (POSITION_VAL(Pin) * 4U)), (Function << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + */ +__STATIC_INLINE uint32_t md_gpio_get_pin_function0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFL, (GPIO_AFL_AF0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group13 AFH + * @{ + */ +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from FUNCTION0 to FUNCTION7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Function This parameter can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_function8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Function) +{ + MODIFY_REG(GPIOx->AFH, (GPIO_AFH_AF8 << (POSITION_VAL(Pin >> 8U) * 4U)), (Function << (POSITION_VAL(Pin >> 8U) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + */ +__STATIC_INLINE uint32_t md_gpio_get_pin_function8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFH, (GPIO_AFH_AF8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +} +/** + * @} + */ + +/** @defgroup MD_GPIO_Public_Functions_Group1 Initialization + * @{ + */ +ErrorStatus md_gpio_deinit(GPIO_TypeDef *GPIOx); +ErrorStatus md_gpio_init(GPIO_TypeDef *GPIOx, md_gpio_inittypedef *GPIO_InitStruct); +void md_gpio_struct_init(md_gpio_inittypedef *GPIO_InitStruct); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c b/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c new file mode 100644 index 00000000000..1250d912af9 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c @@ -0,0 +1,353 @@ +/********************************************************************************** + * + * @file md_i2c.c + * @brief md_i2c C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_i2c.h" +#include "md_rcu.h" +#include +#include "stdint.h" +/** @addtogroup Micro_Driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/** + * @brief This function is used when I2C uses DMA to import data into TXDATA. + It is necessary to reset the I2C after first clearing the data in TXDATA after receiving the NACK signal. + * Note: When using this function, you need to wait for the stop signal and the stop flag in the RIF will be automatically cleared after use. + * @param hperh: Pointer to a ald_i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +void md_i2c_clear_txbuff(I2C_TypeDef *I2Cx) +{ + while (!md_i2c_is_active_it_nack(I2Cx)); + + md_i2c_clear_it_nack(I2Cx); + + while (!md_i2c_is_active_it_stop(I2Cx)); + + md_i2c_clear_it_stop(I2Cx); + md_i2c_disable_pe(I2Cx); +} + +/** + * @brief De-initialize the I2C registers to their default reset values. + * @param I2Cx I2C Instance. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are de-initialized + * - ERROR: I2C registers are not de-initialized + */ +ErrorStatus md_i2c_deinit(I2C_TypeDef *I2Cx) +{ + ErrorStatus status = SUCCESS; + + if (I2Cx == I2C1) + { + /* Enable reset of I2C clock */ + md_rcu_enable_i2c1(RCU); + + /* Disable reset of I2C clock */ + md_rcu_disable_i2c1(RCU); + } + else if (I2Cx == I2C2) + { + /* Enable reset of I2C clock */ + md_rcu_enable_i2c2_reset(RCU); + + /* Disable reset of I2C clock */ + md_rcu_disable_i2c2_reset(RCU); + } + else + { + status = ERROR; + } + + return status; +} + + +/** + * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. + * @note The parameters in md_i2c_init should be expected values. Otherwise, ERROR result will be returned. + * @param I2Cx I2C Instance + * @param I2C_InitStruct pointer to a @ref md_i2c_inittypedef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus md_i2c_init(I2C_TypeDef *I2Cx, md_i2c_inittypedef *I2C_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_MD_I2C_ALL_INSTANCE(I2Cx)); + + /* Check the I2C parameters from I2C_InitStruct */ + assert_param(IS_MD_I2C_TIMING(I2C_InitStruct->Timing)); + assert_param(IS_MD_I2C_ADDRSIZE(I2C_InitStruct->AddrSize)); + assert_param(IS_MD_I2C_ADDRESS1(I2C_InitStruct->Address1)); + assert_param(IS_MD_I2C_DUALADDRESSMODE(I2C_InitStruct->DualAddressMode)); + assert_param(IS_MD_I2C_ADDRESS2(I2C_InitStruct->Address2)); + assert_param(IS_MD_I2C_ADDRESS2MASKS(I2C_InitStruct->Address2Masks)); + /* Check the PLL clock, if not corrt, modify it */ + + md_i2c_disable_pe(I2Cx); + md_i2c_set_clock_prescaler(I2Cx, ((I2C_InitStruct->Timing) >> 28) & 0xF); + md_i2c_set_data_setup_time(I2Cx, ((I2C_InitStruct->Timing) >> 20) & 0xF); + md_i2c_set_data_hold_time(I2Cx, ((I2C_InitStruct->Timing) >> 16) & 0xF); + md_i2c_set_clock_high_period(I2Cx, ((I2C_InitStruct->Timing) >> 8) & 0xFF); + md_i2c_set_clock_low_period(I2Cx, ((I2C_InitStruct->Timing)) & 0xFF); + + md_i2c_enable_pe(I2Cx); + + md_i2c_disable_own1_addr(I2Cx); + md_i2c_set_own1_addr(I2Cx, I2C_InitStruct->Address1); + + if (I2C_InitStruct->AddrSize == MD_I2C_OA1MODE_10BIT) + { + md_i2c_enable_own1_10_bit_addr(I2Cx); + } + else if (I2C_InitStruct->AddrSize == MD_I2C_OA1MODE_7BIT) + { + md_i2c_enable_own1_7_bit_addr(I2Cx); + } + + md_i2c_enable_own1_addr(I2Cx); + + if (I2C_InitStruct->DualAddressMode == MD_I2C_OA2_ENABLE) + { + md_i2c_disable_own2_addr(I2Cx); + md_i2c_set_own2_mask_addr(I2Cx, I2C_InitStruct->Address2Masks); + md_i2c_set_own2_addr(I2Cx, I2C_InitStruct->Address2); + md_i2c_enable_own2_addr(I2Cx); + } + + status = SUCCESS; + + return status; +} + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be transmitted + * @param Enable/Disable 10-bit addressing mode + * @param Device(slave) address + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_master_send(I2C_TypeDef *I2Cx, uint32_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *txbuf) +{ + uint32_t Nbyte_bak = 0; + md_i2c_master_setting(I2Cx, Nbyte, addr10, DevAddr, MD_I2C_WRITE); + + Nbyte_bak = Nbyte; + + while (Nbyte > 0) + { + while (!(md_i2c_is_active_flag_txe(I2Cx))); + + md_i2c_set_tx_reg_data(I2Cx, *txbuf++); + + Nbyte--; + + if (Nbyte_bak - Nbyte >= 65535) + { + while (!md_i2c_is_active_flag_tcr(I2Cx)); + + md_i2c_clear_it_tcr(I2Cx); + Nbyte_bak = Nbyte; + + if (Nbyte <= 65535) + { + md_i2c_handler_transfer(I2Cx, DevAddr, addr10, Nbyte, MD_I2C_MODE_AUTOEND, MD_I2C_REQUEST_NOSTARTSTOP); + } + else + { + md_i2c_handler_transfer(I2Cx, DevAddr, addr10, 0xFFFF, MD_I2C_MODE_RELOAD | MD_I2C_MODE_AUTOEND, MD_I2C_REQUEST_NOSTARTSTOP); + } + } + } + +} + +/** + * @brief Transmits/Receive in master mode setting. + * @param I2Cx I2C Instance + * @param The number of bytes to be transmitted,When the number of receive exceeds 255, the reload function needs to be enabled + * @param Enable/Disable 10-bit addressing mode + * @param Device(slave) address + * @param The pointer to a data buffer + * @param Master is write mode or read mode + @arg @ref MD_I2C_WRITE + @arg @ref MD_I2C_READ + * @retval None + */ +void md_i2c_master_setting(I2C_TypeDef *I2Cx, uint32_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t WriteRead) +{ + /* Config Device(slave) address */ + if (addr10 == MD_I2C_ADDRESSINGMODE_7BIT) + { + md_i2c_enable_addr_7_bit(I2Cx); + } + else if (addr10 == MD_I2C_ADDRESSINGMODE_10BIT) + { + md_i2c_enable_addr_10_bit(I2Cx); + } + + md_i2c_set_slave_addr(I2Cx, DevAddr); + + if (WriteRead == MD_I2C_WRITE) + { + if (Nbyte > 65535) + md_i2c_set_transmit_length(I2Cx, 0xFFFF); + else + md_i2c_set_transmit_length(I2Cx, Nbyte); + + md_i2c_enable_master_write(I2Cx); + + if (Nbyte > 65535) + md_i2c_enable_reload(I2Cx); + else + md_i2c_disable_reload(I2Cx); + } + else + { + if (Nbyte > 255) + md_i2c_set_transmit_length(I2Cx, 0xFF); + else + md_i2c_set_transmit_length(I2Cx, Nbyte); + + md_i2c_enable_master_read(I2Cx); + + if (Nbyte > 255) + md_i2c_enable_reload(I2Cx); + else + md_i2c_disable_reload(I2Cx); + } + + /* When NBYTES is matched, the communication will be automatically stop */ + md_i2c_enable_auto_end(I2Cx); + /* Start the I2C communication */ + md_i2c_set_start(I2Cx); +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be received,When the number of receive exceeds 255, the reload function needs to be enabled + * @param Enable/Disable 10-bit addressing mode + * @param Device(slave) address + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_master_receive(I2C_TypeDef *I2Cx, uint32_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *rxbuf) +{ + uint32_t Nbyte_bak = Nbyte; + md_i2c_master_setting(I2Cx, Nbyte, addr10, DevAddr, MD_I2C_READ); + + while (Nbyte > 0) + { + /* Wait Rx FIFO non-empty */ + while (!(md_i2c_is_active_flag_rxne(I2Cx))); + + *rxbuf++ = md_i2c_get_rx_reg_data(I2Cx); + Nbyte--; + + if (Nbyte_bak - Nbyte >= 255) + { + while (!md_i2c_is_active_flag_tcr(I2Cx)); + + md_i2c_clear_it_tcr(I2Cx); + Nbyte_bak = Nbyte; + + if (Nbyte <= 255) + { + md_i2c_handler_transfer(I2Cx, DevAddr, addr10, Nbyte, MD_I2C_MODE_AUTOEND, MD_I2C_REQUEST_NOSTARTSTOP); + } + else + { + md_i2c_handler_transfer(I2Cx, DevAddr, addr10, 0xFFFF, MD_I2C_MODE_RELOAD | MD_I2C_MODE_AUTOEND, MD_I2C_REQUEST_NOSTARTSTOP); + } + } + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be transmitted, not for NBYTES + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_slave_send(I2C_TypeDef *I2Cx, uint32_t Num, uint8_t *txbuf) +{ + + while (!(md_i2c_is_active_flag_busy(I2Cx))); + + while (Num > 0) + { + while (!(md_i2c_is_active_flag_txe(I2Cx))); + + md_i2c_set_tx_reg_data(I2Cx, *txbuf++); + Num--; + } +} + +/** + * @brief Receives in slave mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be transmitted, not for NBYTES + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_slave_receive(I2C_TypeDef *I2Cx, uint32_t Num, uint8_t *rxbuf) +{ + + while (!(md_i2c_is_active_flag_busy(I2Cx))); + + printf("I2C1->STAT:%x\r\n", I2C1->STAT); + + while (Num > 0) + { + while (!(md_i2c_is_active_flag_rxne(I2Cx))); + + *rxbuf++ = md_i2c_get_rx_reg_data(I2Cx); + Num--; + } +} + +/** + * @} Micro_Driver + */ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.h b/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.h new file mode 100644 index 00000000000..461929bbf68 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.h @@ -0,0 +1,3107 @@ +/********************************************************************************** + * + * @file md_i2c.h + * @brief header file of md_i2c.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 21 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_I2C_H__ +#define __MD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_I2C I2C + * @brief I2C micro driver + * @{ + */ + +/** @defgroup MD_I2C_Pubulic_Types I2C Pubulic Types + * @{ + */ + +/** + * @brief I2C Init structure. + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter can be a value of @ref CLK100kHz8M + @ref CLK400kHz8M + @ref CLK500kHz8M + @ref CLK10kHz16M + @ref CLK100kHz16M + @ref CLK400kHz16M + @ref CLK1000kHz16M + @ref CLK10kHz48M + @ref CLK100kHz48M + @ref CLK400kHz48M + @ref CLK1000kHz48M */ + + uint32_t Address1; /*!< Specifies the first device address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddrSize; /*!< Specifies the device address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref MD_I2C_OA1MODE_7BIT + @ref MD_I2C_OA1MODE_10BIT */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. */ + + uint32_t Address2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t Address2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref MD_I2C_ADDR2_NOMASK + @ref MD_I2C_ADDR2_MASK01 + @ref MD_I2C_ADDR2_MASK02 + @ref MD_I2C_ADDR2_MASK03 + @ref MD_I2C_ADDR2_MASK04 + @ref MD_I2C_ADDR2_MASK05 + @ref MD_I2C_ADDR2_MASK06 + @ref MD_I2C_ADDR2_MASK07 */ +} md_i2c_inittypedef; +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Macros I2C Public Macros + * @{ + */ + +/* I2C_CON1 macros define*/ + +#define MD_I2C_DNF_DISABLE (0x00000000U) +#define MD_I2C_DNF_1T (0x00000001U) +#define MD_I2C_DNF_2T (0x00000002U) +#define MD_I2C_DNF_3T (0x00000003U) +#define MD_I2C_DNF_4T (0x00000004U) +#define MD_I2C_DNF_5T (0x00000005U) +#define MD_I2C_DNF_6T (0x00000006U) +#define MD_I2C_DNF_7T (0x00000007U) +#define MD_I2C_DNF_8T (0x00000008U) +#define MD_I2C_DNF_9T (0x00000009U) +#define MD_I2C_DNF_10T (0x0000000AU) +#define MD_I2C_DNF_11T (0x0000000BU) +#define MD_I2C_DNF_12T (0x0000000CU) +#define MD_I2C_DNF_13T (0x0000000DU) +#define MD_I2C_DNF_14T (0x0000000EU) +#define MD_I2C_DNF_15T (0x0000000FU) + +/* I2C_CON2 macros define*/ +#define MD_I2C_ACK_UPD_NO_UPDATE (0x00000000U) +#define MD_I2C_ACK_UPD_UPDATE (0x00000001U) + +#define MD_I2C_ACK (0x00000000U) +#define MD_I2C_NACK (0x00000001U) + +#define MD_I2C_STOP_NO (0x00000000U) +#define MD_I2C_STOP_GENERATION (0x00000001U) + +#define MD_I2C_START_NO (0x00000000U) +#define MD_I2C_START_GENERATION (0x00000001U) + +#define MD_I2C_ADDRESSINGMODE_7BIT (0x00000000U) +#define MD_I2C_ADDRESSINGMODE_10BIT (0x00000001U) + +/* I2C_ADDR1 macros define*/ + +#define MD_I2C_OA1MODE_7BIT (0x00000000U) +#define MD_I2C_OA1MODE_10BIT (0x00000001U) + +/* I2C_ADDR2 macros define*/ +#define MD_I2C_OA2_DISABLE (0x00000000U) +#define MD_I2C_OA2_ENABLE (0x00000001U) + +#define MD_I2C_ADDR2_NOMASK (0x00U) +#define MD_I2C_ADDR2_MASK01 (0x01U) +#define MD_I2C_ADDR2_MASK02 (0x02U) +#define MD_I2C_ADDR2_MASK03 (0x03U) +#define MD_I2C_ADDR2_MASK04 (0x04U) +#define MD_I2C_ADDR2_MASK05 (0x05U) +#define MD_I2C_ADDR2_MASK06 (0x06U) +#define MD_I2C_ADDR2_MASK07 (0x07U) + +/* I2C_TIMINGR macros define*/ +/* presc scldel sdadel sclh scll */ +#define CLK10kHz8M (0x1<<28) |(0x4<<20) |(0x2<<16) |(0xC3<<8) |(0xC7) /*!< APB = 8MHz; CLK = 10kHz */ +#define CLK100kHz8M (0x1<<28) |(0x4<<20) |(0x2<<16) |(0xF<<8) |(0x13) /*!< APB = 8MHz; CLK = 100kHz */ +#define CLK400kHz8M (0x0<<28) |(0x3<<20) |(0x1<<16) |(0x3<<8) |(0x9) /*!< APB = 8MHz; CLK = 400kHz */ +#define CLK500kHz8M (0x0<<28) |(0x1<<20) |(0x0<<16) |(0x3<<8) |(0x6) /*!< APB = 8MHz; CLK = 500kHz */ +#define CLK10kHz16M (0x3<<28) |(0x4<<20) |(0x2<<16) |(0xC3<<8) |(0xC7) /*!< APB = 16MHz; CLK = 10kHz */ +#define CLK100kHz16M (0x3<<28) |(0xF<<20) |(0x2<<16) |(0xF<<8) |(0x13) /*!< APB = 16MHz; CLK = 100kHz */ +#define CLK400kHz16M (0x1<<28) |(0x3<<20) |(0x2<<16) |(0x3<<8) |(0x9) /*!< APB = 16MHz; CLK = 400kHz */ +#define CLK1000kHz16M (0x0<<28) |(0x2<<20) |(0x0<<16) |(0x2<<8) |(0x4) /*!< APB = 16MHz; CLK = 1000kHz */ +#define CLK10kHz48M (0xBU<<28) |(0x4<<20) |(0x2<<16) |(0xC3<<8) |(0xC7) /*!< APB = 48MHz; CLK = 10kHz */ +#define CLK100kHz48M (0xBU<<28) |(0x4<<20) |(0x2<<16) |(0xF<<8) |(0x13) /*!< APB = 48MHz; CLK = 100kHz */ +#define CLK400kHz48M (0x5<<28) |(0x3<<20) |(0x3<<16) |(0x3<<8) |(0x9) /*!< APB = 48MHz; CLK = 400kHz */ +#define CLK1000kHz48M (0x5<<28) |(0x1<<20) |(0x0<<16) |(0x1<<8) |(0x3) /*!< APB = 48MHz; CLK = 1000kHz */ +#define CLK10kHz72M (0xFU<<28) |(0x4<<20) |(0x2<<16) |(0xDB<<8) |(0xE1) /*!< APB = 72MHz; CLK = 10kHz */ +#define CLK100kHz72M (0x8U<<28) |(0x6<<20) |(0x3<<16) |(0x23<<8) |(0x24) /*!< APB = 72MHz; CLK = 100kHz */ +#define CLK400kHz72M (0x8U<<28) |(0x3<<20) |(0x3<<16) |(0x3<<8) |(0x7) /*!< APB = 72MHz; CLK = 400kHz */ +#define CLK1000kHz72M (0x0U<<28) |(0x1<<20) |(0x0<<16) |(0x2<<8) |(0x4) /*!< APB = 72MHz; CLK = 1000kHz */ + +#define MD_I2C_MODE_NONE ((uint8_t)0x00U) /*!< None */ +#define MD_I2C_MODE_MASTER ((uint8_t)0x10U) /*!< Master */ +#define MD_I2C_MODE_SLAVE ((uint8_t)0x20U) /*!< Slave */ +#define MD_I2C_MODE_MEM ((uint8_t)0x40U) /*!< Mem */ + +#define MD_I2C_MODE_RELOAD (I2C_CON2_RELOAD) +#define MD_I2C_MODE_AUTOEND (I2C_CON2_AUTOEND) +#define MD_I2C_MODE_SOFTEND (0x0U) +#define MD_I2C_MODE_SMBUS_RELOAD MD_I2C_MODE_RELOAD +#define MD_I2C_MODE_SMBUS_AUTOEND_NO_PEC MD_I2C_MODE_AUTOEND +#define MD_I2C_MODE_SMBUS_SOFTEND_NO_PEC MD_I2C_MODE_SOFTEND +#define MD_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(MD_I2C_MODE_AUTOEND | I2C_CON2_PECBYTE) +#define MD_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(MD_I2C_MODE_SOFTEND | I2C_CON2_PECBYTE) + +#define MD_I2C_REQUEST_NOSTARTSTOP (0x0U) +#define MD_I2C_REQUEST_STOP I2C_CON2_STOP +#define MD_I2C_REQUEST_START_READ (uint32_t)(I2C_CON2_START|I2C_CON2_RD_WRN) +#define MD_I2C_REQUEST_START_WRITE (uint32_t)(I2C_CON2_START) +#define MD_I2C_REQUEST_RESTART_7BIT_READ (uint32_t)(I2C_CON2_START|I2C_CON2_RD_WRN) +#define MD_I2C_REQUEST_RESTART_7BIT_WRITE (uint32_t)(I2C_CON2_START) +#define MD_I2C_REQUEST_RESTART_10BIT_READ (uint32_t)(I2C_CON2_START|I2C_CON2_HEAD10R|I2C_CON2_RD_WRN); +#define MD_I2C_REQUEST_RESTART_10BIT_WRITE (uint32_t)(I2C_CON2_START); + +#define MD_I2C_ADDRESS_SIZE_7BIT 0 +#define MD_I2C_ADDRESS_SIZE_10BIT 1 + + +/* I2C_MASTER_WriteRead macros define*/ +#define MD_I2C_WRITE 0 +#define MD_I2C_READ 1 +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions I2C Public Functions + * @{ + */ + +/** @defgroup MD_I2C_Public_Functions_Group2 CON1 + * @{ + */ +/** + * @brief I2C Set CON1 + * @note These bits must be configured when the I2C is disabled (PE = 0) except TXDMAEN and RXDMAEN. + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con1(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->CON1, Reg_Value); +} + +/** + * @brief I2C Get CON1 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_con1(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->CON1)); +} + +/** + * @brief Set I2C number of bytes + * @note The number of bytes to be transmitted/received is programmed there. + * This field is don't care in slave mode with SBC=0. + * Changing these bits when the START bit is set is not allowed. + * @param I2Cx I2C Instance + * @param nbytes number of bytes + * @arg Max Value 0xFFFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_transmit_length(I2C_TypeDef *I2Cx, uint32_t nbytes) +{ + nbytes &= 0xffff; //mask bit31~bit16 + + if (nbytes >= 0xff) + { + MODIFY_REG(I2Cx->CON1, I2C_CON1_NBYTES, ((nbytes) >> 8) << I2C_CON1_NBYTES_POSS); + } + + nbytes &= 0xff; //mask bit31~bit8 + MODIFY_REG(I2Cx->CON2, I2C_CON2_NBYTES, nbytes << I2C_CON2_NBYTES_POSS); +} + +/** + * @brief Get I2C number of bytes + * @note The number of bytes to be transmitted/received is programmed there. + * This field is don't care in slave mode with SBC=0. + * Changing these bits when the START bit is set is not allowed. + * @param I2Cx I2C Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFFFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_transmit_length(I2C_TypeDef *I2Cx) +{ + uint32_t high_nbytes = ((READ_BIT(I2Cx->CON1, I2C_CON1_NBYTES) >> I2C_CON1_NBYTES_POSS) & 0Xff); + uint32_t low_nbytes = ((READ_BIT(I2Cx->CON2, I2C_CON2_NBYTES) >> I2C_CON2_NBYTES_POSS) & 0xff); + + return (uint32_t)((high_nbytes << 8) | (low_nbytes)); +} + +/** + * @brief I2C PEC Enable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_smbus_pec(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_PECEN); +} + +/** + * @brief I2C PEC Disable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_smbus_pec(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_PECEN); +} + +/** + * @brief Indicate if I2C PEC is enabled + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to '0' + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_smbus_pec(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_PECEN) == (I2C_CON1_PECEN)); +} + +/** + * @brief I2C Alert Enable + * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_smbus_alert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_ALERTEN); +} + +/** + * @brief I2C Alert Disable + * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_smbus_alert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_ALERTEN); +} + +/** + * @brief Indicate if I2C PEC is enabled + * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_smbus_alert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_ALERTEN) == (I2C_CON1_ALERTEN)); +} + +/** + * @brief I2C SMBus Device Default address Enable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_smbus_slave_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SMBDEN); +} + +/** + * @brief I2C SMBus Device Default address Disable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_smbus_slave_addr(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SMBDEN); +} + +/** + * @brief Indicate if I2C SMBus Device Default address is enabled + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_smbus_slave_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_SMBDEN) == (I2C_CON1_SMBDEN)); +} + +/** + * @brief I2C SMBus Host address Enable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_smbus_host_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SMBHEN); +} + +/** + * @brief I2C SMBus Host address Disable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_smbus_host_addr(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SMBHEN); +} + +/** + * @brief Indicate if I2C SMBus Host address is enabled + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_smbus_host_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_SMBHEN) == (I2C_CON1_SMBHEN)); +} + +/** + * @brief I2C general call Enable + * @note This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_general_call(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_GCEN); +} + +/** + * @brief I2C general call Disable + * @note This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_general_call(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_GCEN); +} + +/** + * @brief Indicate if I2C general call is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_general_call(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_GCEN) == (I2C_CON1_GCEN)); +} + +/** + * @brief I2C clock stretching Disable + * @note Clock stretching disables. This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_scl_nostretch(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH); +} + +/** + * @brief I2C clock stretching Enable + * @note Clock stretching enables.This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_scl_nostretch(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH); +} + +/** + * @brief Indicate if I2C clock nostretching is enabled + * @note This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_scl_nostretch(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH) == (I2C_CON1_NOSTRETCH)); +} + +/** + * @brief I2C slave byte control Enable + * @note This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_slave_byte_control(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SBC); +} + +/** + * @brief I2C slave byte control Disable + * @note This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_slave_byte_control(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SBC); +} + +/** + * @brief Indicate if I2C slave byte control is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_slave_byte_control(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_SBC) == (I2C_CON1_SBC)); +} + +/** + * @brief I2C DMA receiver requests Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_dma_receive(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN); +} + +/** + * @brief I2C DMA receiver requests Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_dma_receive(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN); +} + +/** + * @brief Indicate if I2C DMA receiver requests is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_dma_receive(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN) == (I2C_CON1_RXDMAEN)); +} + +/** + * @brief I2C DMA transmitter requests Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_dma_transmit(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN); +} + +/** + * @brief I2C DMA transmitter requests Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_dma_transmit(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN); +} + +/** + * @brief Indicate if I2C DMA transmitter requests is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_dma_transmit(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN) == (I2C_CON1_TXDMAEN)); +} + +/** + * @brief Set I2C digital noise filter + * @note If the analog filter is also enabled,the digital filter is added to the analog filter. + * This filter can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param filter_capability digital noise filter capability + * @arg @ref MD_I2C_DNF_DISABLE + * @arg @ref MD_I2C_DNF_1T + * @reg @ref MD_I2C_DNF_2T + * @reg @ref MD_I2C_DNF_3T + * @reg @ref MD_I2C_DNF_4T + * @reg @ref MD_I2C_DNF_5T + * @reg @ref MD_I2C_DNF_6T + * @reg @ref MD_I2C_DNF_7T + * @reg @ref MD_I2C_DNF_8T + * @reg @ref MD_I2C_DNF_9T + * @reg @ref MD_I2C_DNF_10T + * @reg @ref MD_I2C_DNF_11T + * @reg @ref MD_I2C_DNF_12T + * @reg @ref MD_I2C_DNF_13T + * @reg @ref MD_I2C_DNF_14T + * @reg @ref MD_I2C_DNF_15T + * @retval None + */ +__STATIC_INLINE void md_i2c_set_digit_filter(I2C_TypeDef *I2Cx, uint32_t filter_capability) +{ + MODIFY_REG(I2Cx->CON1, I2C_CON1_DNF, filter_capability << I2C_CON1_DNF_POSS); +} + +/** + * @brief Get I2C digital noise filter + * @note If the analog filter is also enabled,the digital filter is added to the analog filter. + * This filter can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_I2C_DNF_DISABLE + * @arg @ref MD_I2C_DNF_1T + * @reg @ref MD_I2C_DNF_2T + * @reg @ref MD_I2C_DNF_3T + * @reg @ref MD_I2C_DNF_4T + * @reg @ref MD_I2C_DNF_5T + * @reg @ref MD_I2C_DNF_6T + * @reg @ref MD_I2C_DNF_7T + * @reg @ref MD_I2C_DNF_8T + * @reg @ref MD_I2C_DNF_9T + * @reg @ref MD_I2C_DNF_10T + * @reg @ref MD_I2C_DNF_11T + * @reg @ref MD_I2C_DNF_12T + * @reg @ref MD_I2C_DNF_13T + * @reg @ref MD_I2C_DNF_14T + * @reg @ref MD_I2C_DNF_15T + */ +__STATIC_INLINE uint32_t md_i2c_get_digit_filter(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_DNF) >> I2C_CON1_DNF_POSS); +} + +/** + * @brief I2C Peripheral Enable + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_pe(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_PE); +} + +/** + * @brief I2C Peripheral Disable + * @note When PE = 0, the I2C SCL and SDA lines are released.Internal state machines and status bits are put back to their reset value.When cleared,PE must be kept low for at least 3 APB clock cycles + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_pe(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_PE); +} + +/** + * @brief Indicate if Peripheral is enabled + * @note When PE = 0, the I2C SCL and SDA lines are released.Internal state machines and status bits are put back to their reset value.When cleared,PE must be kept low for at least 3 APB clock cycles + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_pe(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_PE) == (I2C_CON1_PE)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group3 CON2 + * @{ + */ +/** + * @brief I2C Set CON2 + * @note None + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->CON2, Reg_Value); +} + +/** + * @brief I2C Get CON2 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_con2(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->CON2)); +} + +/** + * @brief Enable I2C Packet error checking byte + * @note This bit is enable by software, and cleared by hardware when the PEC is transferred, + * or when a STOP condition or an Address matched is received, also when PE=0. + * Writing 0 to this bit has no effet. This bit has no effect when RELOAD is set, + * and when SBC is 0 in the slave mode. + * If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * @param I2Cx I2C Instance + * @retval None + + */ +__STATIC_INLINE void md_i2c_enable_pec_byte(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_PECBYTE); +} + +/** + * @brief Check if the I2C Packet error checking byte is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_pec_byte(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_PECBYTE) == (I2C_CON2_PECBYTE)); +} + +/** + * @brief Enable I2C auto end function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_auto_end(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_AUTOEND); +} + +/** + * @brief Disable I2C auto end function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_auto_end(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_AUTOEND); +} + +/** + * @brief Check if I2C auto end function is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_auto_end(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_AUTOEND) == (I2C_CON2_AUTOEND)); +} + +/** + * @brief Enable I2C reload fuctions. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_reload(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_RELOAD); +} + +/** + * @brief Disable I2C reload fuctions. + * @param I2Cx I2C Instance. + * @retval None + + */ +__STATIC_INLINE void md_i2c_disable_reload(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_RELOAD); +} + +/** + * @brief Check if I2C reload fuctions is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_reload(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_RELOAD) == (I2C_CON2_RELOAD)); +} + +/** + * @brief Set I2C send NACK. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_nack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_NACK); +} + +/** + * @brief Get I2C NACK bit state(slave mode) + * @note NACK=1: will generate NACK + * NACK=0: will generate ACK + * @param I2Cx I2C Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_I2C_ACK + * @arg @ref MD_I2C_NACK + */ +__STATIC_INLINE uint32_t md_i2c_get_nack(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON2, I2C_CON2_NACK) >> I2C_CON2_NACK_POS); +} + +/** + * @brief Set I2C Stop generation(master mode) + * @note Writing 0 to this bit has no effect. + * @param I2Cx I2C Instance + * @retval None + + */ +__STATIC_INLINE void md_i2c_set_stop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_STOP); +} + +/** + * @brief Get I2C state of STOP bit(master mode) + * @note Writing 0 to this bit has no effect. + * @param I2Cx I2C Instance + * @retval The retval can be one of the following values: + * @arg MD_I2C_STOP_NO + * @arg MD_I2C_STOP_GENERATION + */ +__STATIC_INLINE uint32_t md_i2c_get_stop(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON2, I2C_CON2_STOP) >> I2C_CON2_STOP_POS); +} + +/** + * @brief Set I2C Start generation + * @note Writing 0 to this bit has no effect.The START bit can be set even if the bus is BUSY or I2C is in slave mode. + * In 10-bit addressing mode, if a NACK is received on the first part of the address, + * the START bit is not cleared by hardware and the master will resend the address sequence. + * @param I2Cx I2C Instance + * @retval None + + */ +__STATIC_INLINE void md_i2c_set_start(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_START); +} + +/** + * @brief Get I2C state of START bit + * @note None + * @param I2Cx I2C Instance + * @retval The retval can be one of the following values: + * @arg MD_I2C_START_NO + * @arg MD_I2C_START_GENERATION + */ +__STATIC_INLINE uint32_t md_i2c_get_start(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON2, I2C_CON2_START) >> I2C_CON2_START_POS); +} + +/** + * @brief Enable i2c send 10-bit standard address header. + * @param I2Cx I2C Instance. + * @retval None + frome M950 + */ +__STATIC_INLINE void md_i2c_enable_standard_10_bit_header(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_HEAD10R); +} + +/** + * @brief Disable i2c send 10-bit standard address header. + * @param I2Cx I2C Instance. + * @retval None + + */ +__STATIC_INLINE void md_i2c_disable_standard_10_bit_header(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_HEAD10R); +} + +/** + * @brief Check if i2c send 10-bit standard address header is enabled or disable. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_standard_10_bit_header(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_HEAD10R) == (I2C_CON2_HEAD10R)); +} + +/** + * @brief Enable 10-bit address mode. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_addr_10_bit(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_ADD10); +} + +/** + * @brief Enable 7-bit address mode. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_addr_7_bit(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_ADD10); +} + +/** + * @brief Check if is enabled 10-bit address mode. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_addr_10_bit(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_ADD10) == (I2C_CON2_ADD10)); +} + +/** + * @brief Check if is enabled 7-bit address mode. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_addr_7_bit(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_ADD10) != (I2C_CON2_ADD10)); +} + +/** + * @brief Enable i2c master read. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_master_read(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_RD_WRN); +} + +/** + * @brief Enable i2c master write. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_master_write(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_RD_WRN); +} + +/** + * @brief Check if is enabled master read. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_master_read(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_RD_WRN) == (I2C_CON2_RD_WRN)); +} + +/** + * @brief Check if is enabled master write. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_master_write(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_RD_WRN) != (I2C_CON2_RD_WRN)); +} + +/** + * @brief Set I2C slave address(master mode) + * @note Changing these bits when the START bit is set is not allowed + * For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @param slave_addr I2C slave address + * @arg Max Value 7-bit: 0xFE / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_slave_addr(I2C_TypeDef *I2Cx, uint32_t addr) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_SADD, (addr << I2C_CON2_SADD_POSS)); +} + +/** + * @brief Get I2C slave address(master mode) + * @note Changing these bits when the START bit is set is not allowed + * For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @retval I2C slave address + * @arg Max Value 7-bit: 0xFE / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_slave_addr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON2, I2C_CON2_SADD)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group4 ADDR1 + * @{ + */ +/** + * @brief Set I2C ADDR1 + * @note These bits can be written only when OA1EN=0 except OA1EN. + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr1(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->ADDR1, Reg_Value); +} + +/** + * @brief Get I2C ADDR1 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_addr1(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->ADDR1)); +} + +/** + * @brief I2C address register 1 Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_own1_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN); +} + +/** + * @brief I2C address register 1 Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_own1_addr(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN); +} + +/** + * @brief Indicate if address register 1 is enabled + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_own1_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN) == (I2C_ADDR1_OA1EN)); +} + + + +/** + * @brief Enable i2c own1 10_bit address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_own1_10_bit_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE); +} + +/** + * @brief Enable i2c own1 7_bit address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_own1_7_bit_addr(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE); +} + +/** + * @brief Check if is enabled i2c own1 10_bit address. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_own1_10_bit_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE) == (I2C_ADDR1_OA1MODE)); +} + +/** + * @brief Check if is enabled i2c own1 7_bit address. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_own1_7_bit_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE) != (I2C_ADDR1_OA1MODE)); +} + +/** + * @brief Set I2C address1 + * @note For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @param own_addr I2C own address1 + * @arg Max Value 7-bit: 0xFE / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_own1_addr(I2C_TypeDef *I2Cx, uint32_t own_addr) +{ + MODIFY_REG(I2Cx->ADDR1, I2C_ADDR1_OA1, own_addr); +} + +/** + * @brief Get I2C address1 + * @note For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @retval I2C own address1 + * @arg Max Value 7-bit: 0xFE / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_own1_addr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group5 ADDR2 + * @{ + */ +/** + * @brief Set I2C ADDR2 + * @note These bits can be written only when OA2EN=0 except OA2EN. + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr2(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->ADDR2, Reg_Value); +} + +/** + * @brief Get I2C ADDR2 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_addr2(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->ADDR2)); +} + +/** + * @brief I2C own address register 2 Enable + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_own2_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN); +} + +/** + * @brief I2C own address register 2 Disable + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_own2_addr(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN); +} + +/** + * @brief Indicate if address register 2 is enabled + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_own2_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN) == (I2C_ADDR2_OA2EN)); +} + +/** + * @brief Set I2C own address2 mask + * @note These bits can be written only when OA2EN=0. + * As soon as OA2MSK is not equal to 0,the reserved I2C addresses(0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + * @param I2Cx I2C Instance + * @param oa2_mask I2C own address2 mask + * @arg @ref MD_I2C_ADDR2_NOMASK + * @arg @ref MD_I2C_ADDR2_MASK01 + * @arg @ref MD_I2C_ADDR2_MASK02 + * @arg @ref MD_I2C_ADDR2_MASK03 + * @arg @ref MD_I2C_ADDR2_MASK04 + * @arg @ref MD_I2C_ADDR2_MASK05 + * @arg @ref MD_I2C_ADDR2_MASK06 + * @arg @ref MD_I2C_ADDR2_MASK07 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_own2_mask_addr(I2C_TypeDef *I2Cx, uint32_t oa2_mask) +{ + MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2MSK, oa2_mask << I2C_ADDR2_OA2MSK_POSS); +} + +/** + * @brief Get I2C address2 mask + * @note None + * As soon as OA2MSK is not equal to 0,the reserved I2C addresses(0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + * @param I2Cx I2C Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_I2C_ADDR2_NOMASK + * @arg @ref MD_I2C_ADDR2_MASK01 + * @arg @ref MD_I2C_ADDR2_MASK02 + * @arg @ref MD_I2C_ADDR2_MASK03 + * @arg @ref MD_I2C_ADDR2_MASK04 + * @arg @ref MD_I2C_ADDR2_MASK05 + * @arg @ref MD_I2C_ADDR2_MASK06 + * @arg @ref MD_I2C_ADDR2_MASK07 + */ +__STATIC_INLINE uint32_t md_i2c_get_own2_mask_addr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2MSK) >> I2C_ADDR2_OA2MSK_POSS); +} + +/** + * @brief Set I2C own address2 + * @note These bits can be written only when OA2EN=0. + * @param I2Cx I2C Instance + * @param own_addr I2C own address2 + * @arg Max Value 0x7F + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_own2_addr(I2C_TypeDef *I2Cx, uint32_t own_addr) +{ + MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2, own_addr << I2C_ADDR2_OA2_POSS); +} + +/** + * @brief Get I2C own address2 + * @note None + * @param I2Cx I2C Instance + * @retval I2C own address2 + * @arg Max Value 0x7F + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_own2_addr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2) >> I2C_ADDR2_OA2_POSS); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group6 TIMINGR + * @{ + */ +/** + * @brief Set I2C TIMINGR + * @note These bits must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->TIMINGR, Reg_Value); +} + +/** + * @brief Get I2C TIMINGR + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->TIMINGR)); +} + +/** + * @brief Set I2C Timing prescaler + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param timing_prescaler + * @arg Max Value 0xF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_clock_prescaler(I2C_TypeDef *I2Cx, uint32_t timing_prescaler) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_PRESC, timing_prescaler << I2C_TIMINGR_PRESC_POSS); +} + +/** + * @brief Get I2C Timing prescaler + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval timing_prescaler + * @arg Max Value 0xF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_clock_prescaler(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_POSS); +} + +/** + * @brief Set I2C date setup time + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param data_setup_time + * @arg Max Value 0xF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_data_setup_time(I2C_TypeDef *I2Cx, uint32_t data_setup_time) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL, data_setup_time << I2C_TIMINGR_SCLDEL_POSS); +} + +/** + * @brief Get I2C date setup time + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval data_setup_time + * @arg Max Value 0xF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_data_setup_time(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_POSS); +} + +/** + * @brief Set I2C date hold time + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param data_hold_time + * @arg Max Value 0xF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_data_hold_time(I2C_TypeDef *I2Cx, uint32_t data_hold_time) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL, data_hold_time << I2C_TIMINGR_SDADEL_POSS); +} + +/** + * @brief Get I2C date hold time + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval data_hold_time + * @arg Max Value 0xF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_data_hold_time(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_POSS); +} + +/** + * @brief Set I2C Clock high period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param SCL_hperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_clock_high_period(I2C_TypeDef *I2Cx, uint32_t SCL_hperiod) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLH, SCL_hperiod << I2C_TIMINGR_SCLH_POSS); +} + +/** + * @brief Get I2C Clock high period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval SCL_hperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_clock_high_period(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_POSS); +} + +/** + * @brief Set I2C Clock low period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param SCL_lperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_clock_low_period(I2C_TypeDef *I2Cx, uint32_t SCL_lperiod) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLL, SCL_lperiod << I2C_TIMINGR_SCLL_POSS); +} + +/** + * @brief Get I2C Clock low period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval SCL_lperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_clock_low_period(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group7 TIMEOUTR + * @{ + */ +/** + * @brief Set I2C TIMEOUTR + * @note These bits can be written only when TEXTEN=0 and TIMEOUTEN=0 except TEXTEN and TIMEOUTEN. + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timeoutr(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->TIMEOUTR, Reg_Value); +} + +/** + * @brief Get I2C TIMEOUTR + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_timeoutr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->TIMEOUTR)); +} + +/** + * @brief I2C Extended clock timeout Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_texten(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN); +} + +/** + * @brief I2C Extended clock timeout Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_texten(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN); +} + +/** + * @brief Indicate if I2C Extended clock timeout is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_texten(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN) == (I2C_TIMEOUTR_TEXTEN)); +} + +/** + * @brief Set I2C Bus timeout B + * @note These bits can be written only when TEXTEN = 0 + * @param I2Cx I2C Instance + * @param timeoutb Bus timeout B + * @arg Max Value 0xFFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_bus_timeout_b(I2C_TypeDef *I2Cx, uint32_t timeoutb) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB, timeoutb << I2C_TIMEOUTR_TIMEOUTB_POSS); +} + +/** + * @brief Get I2C Bus timeout B + * @note These bits can be written only when TEXTEN = 0 + * @param I2Cx I2C Instance + * @retval Bus timeout B + * @arg Max Value 0xFFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_bus_timeout_b(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_POSS); +} + +/** + * @brief I2C clock timeout Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_timeouten(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN); +} + +/** + * @brief I2C clock timeout Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_timeouten(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN); +} + +/** + * @brief Indicate if I2C clock timeout is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_timeouten(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN) == (I2C_TIMEOUTR_TIMEOUTEN)); +} + + + +/** + * @brief Enable i2c idle state timeout detect function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_idle_timeout(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE); +} + +/** + * @brief Enable i2c idle state timeout detect function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_scl_low_timeout(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE); +} + + +/** + * @brief Check if is enabled i2c idle state timeout detect function + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_idle_timeout(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE) == (I2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Set I2C Bus timeout A + * @note These bits can be written only when TIMOUTEN = 0 + * @param I2Cx I2C Instance + * @param timeouta Bus timeout A + * @arg Max Value 0xFFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_bus_timeout_a(I2C_TypeDef *I2Cx, uint32_t timeouta) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA, timeouta); +} + +/** + * @brief Get I2C Bus timeout A + * @note These bits can be written only when TIMOUTEN = 0 + * @param I2Cx I2C Instance + * @retval Bus timeout A + * @arg Max Value 0xFFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_bus_timeout_a(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group8 STAT + * @{ + */ +/** + * @brief Get I2C STAT + * @note All bits are read-only + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_stat(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->STAT)); +} + +/** + * @brief Get address match code(slave mode) + * @note These bits are updated with the received address when an address match event occurs(ADDR=1). + * @param I2Cx I2C Instance + * @retval 7-bit received address value + */ +__STATIC_INLINE uint32_t md_i2c_get_addr_match(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_ADDCODE) >> (I2C_STAT_ADDCODE_POSS)); +} + + +/** + * @brief Get slave module write. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_write(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_DIR) != (I2C_STAT_DIR)); +} + + +/** + * @brief Get slave module read. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_read(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_DIR) == (I2C_STAT_DIR)); +} + + +/** + * @brief Indicate if I2C busy flag is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_busy(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_BUSY) == (I2C_STAT_BUSY)); +} + +/** + * @brief Indicate if I2C transfer complete reload flag (TCR) is active + * @note This bit is cleared by hardware when PE = 0. + * This flag is only for master mode,or for slave mode when the SBC bit is set + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_tcr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_TCR) == (I2C_STAT_TCR)); +} + +/** + * @brief Indicate if I2C transfer complete flag (TC) is active + * @note This bit is cleared by hardware when PE = 0. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_tc(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_TC) == (I2C_STAT_TC)); +} + +/** + * @brief Indicate if I2C Rx buffer underflow flag (RXUD) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_rxud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_RXUD) == (I2C_STAT_RXUD)); +} + +/** + * @brief Indicate if I2C Rx buffer overflow flag (RXOV) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_rxov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_RXOV) == (I2C_STAT_RXOV)); +} + +/** + * @brief Indicate if I2C Rx buffer not empty flag (RXNE) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_rxne(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_RXNE) == (I2C_STAT_RXNE)); +} + + +/** + * @brief Indicate if I2C Tx buffer underflow flag (TXUD) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_txud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_TXUD) == (I2C_STAT_TXUD)); +} + +/** + * @brief Indicate if I2C Tx buffer overflow flag (TXOV) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_txov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_TXOV) == (I2C_STAT_TXOV)); +} + +/** + * @brief Indicate if I2C Tx buffer empty flag (TXE) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_txe(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_TXE) == (I2C_STAT_TXE)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group9 PECR + * @{ + */ +/** + * @brief Get packet error checking register + * @note None + * @param I2Cx I2C Instance + * @retval 8-bit pec value + */ +__STATIC_INLINE uint32_t md_i2c_get_rx_reg_pec(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group10 RXDATA + * @{ + */ +/** + * @brief Get receive data + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_i2c_get_rx_reg_data(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->RXDATA)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group11 TXDATA + * @{ + */ +/** + * @brief 8-bit transmit data + * @note These bits can be written only when TXE = 1. + * @param I2Cx I2C Instance + * @param txdata Transmit Data + * @arg Max value 0xFF + * @arg Min value 0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_tx_reg_data(I2C_TypeDef *I2Cx, uint32_t txdata) +{ + MODIFY_REG(I2Cx->TXDATA, I2C_TXDATA_TXDATA, txdata); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group12 IER + * @{ + */ +/** + * @brief Set I2C IER + * @note None + * @param I2Cx I2C Instance + * @param ier + * @retval None + */ +__STATIC_INLINE void md_i2c_set_ier(I2C_TypeDef *I2Cx, uint32_t ier) +{ + WRITE_REG(I2Cx->IER, ier); +} + +/** + * @brief Enable SMBus alert interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_alert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ALERT); +} + +/** + * @brief Enable timeout interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_tout(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TOUT); +} + +/** + * @brief Enable PEC error interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_pece(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_PECE); +} + +/** + * @brief Enable arbitration loss interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_arlo(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ARLO); +} + +/** + * @brief Enable bus error interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_berr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_BERR); +} + +/** + * @brief Enable stop detection interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_stop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_STOP); +} + +/** + * @brief Enable NACK receiver interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_nack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_NACK); +} + +/** + * @brief Enable address matched interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ADDR); +} + +/** + * @brief Enable transfer complete and reload interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_tcr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TCR); +} + +/** + * @brief Enable transfer complete interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_tc(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TC); +} + + +/** + * @brief Enable receive buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_rxud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXUD); +} + +/** + * @brief Enable receive buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_rxov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXOV); +} + +/** + * @brief Enable receive buffer not empty interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_rxne(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXNE); +} + +/** + * @brief Enable transmit buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_txud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXUD); +} + +/** + * @brief Enable transmit buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_txov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXOV); +} + +/** + * @brief Enable transmit buffer empty interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_txe(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXE); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group13 IDR + * @{ + */ +/** + * @brief Set I2C IDR + * @note None + * @param I2Cx I2C Instance + * @param idr + * @retval None + */ +__STATIC_INLINE void md_i2c_set_idr(I2C_TypeDef *I2Cx, uint32_t idr) +{ + WRITE_REG(I2Cx->IDR, idr); +} + +/** + * @brief Disable SMBus alert interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_alert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_ALERT); +} + +/** + * @brief Disable timeout interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_tout(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TOUT); +} + +/** + * @brief Disable PEC error interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_pece(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_PECE); +} + +/** + * @brief Disable arbitration loss interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_arlo(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_ARLO); +} + +/** + * @brief Disable bus error interrupt. + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_berr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_BERR); +} + +/** + * @brief Disable stop detection interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_stop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_STOP); +} + +/** + * @brief Disable NACK receiver interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_nack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_NACK); +} + +/** + * @brief Disable address matched interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_ADDR); +} + +/** + * @brief Disable transfer complete and reload interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_tcr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TCR); +} + +/** + * @brief Disable transfer complete interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_tc(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TC); +} + +/** + * @brief Disable receive buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_rxud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_RXUD); +} + +/** + * @brief Disable receive buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_rxov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_RXOV); +} + +/** + * @brief Disable receive buffer not empty interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_rxne(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_RXNE); +} + +/** + * @brief Disable transmit buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_txud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TXUD); +} + +/** + * @brief Disable transmit buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_txov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TXOV); +} + +/** + * @brief Disable transmit buffer empty interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_txe(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TXE); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group14 IVS + * @{ + */ +/** + * @brief Get I2C IVS + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_ivs(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->IVS)); +} + +/** + * @brief Check if SMBus alert interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_alert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ALERT) == (I2C_IVS_ALERT)); +} + +/** + * @brief Check if timeout interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_tout(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TOUT) == (I2C_IVS_TOUT)); +} + +/** + * @brief Check if PEC error interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_pece(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_PECE) == (I2C_IVS_PECE)); +} + +/** + * @brief Check if arbitration loss interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_arlo(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ARLO) == (I2C_IVS_ARLO)); +} + +/** + * @brief Check if bus error interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_berr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_BERR) == (I2C_IVS_BERR)); +} + +/** + * @brief Check if stop detection interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_stop(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_STOP) == (I2C_IVS_STOP)); +} + +/** + * @brief Check if NACK receiver interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_nack(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_NACK) == (I2C_IVS_NACK)); +} + +/** + * @brief Check if address matched interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ADDR) == (I2C_IVS_ADDR)); +} + +/** + * @brief Check if transfer complete and reload interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_tcr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TCR) == (I2C_IVS_TCR)); +} + +/** + * @brief Check if transfer complete interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_tc(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TC) == (I2C_IVS_TC)); +} + +/** + * @brief Check if receive buffer underrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_rxud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXUD) == (I2C_IVS_RXUD)); +} + +/** + * @brief Check if receive buffer ovrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_rxov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXOV) == (I2C_IVS_RXOV)); +} + +/** + * @brief Check if receive buffer not empty interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_rxne(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXNE) == (I2C_IVS_RXNE)); +} + +/** + * @brief Check if transmit buffer underrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_txud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXUD) == (I2C_IVS_TXUD)); +} + +/** + * @brief Check if transmit buffer ovrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_txov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXOV) == (I2C_IVS_TXOV)); +} + +/** + * @brief Check if transmit buffer empty interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_it_txe(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXE) == (I2C_IVS_TXE)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group15 RIF + * @{ + */ +/** + * @brief Get I2C RIF + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_rif(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->RIF)); +} + +/** + * @brief Get SMBus alert raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_alert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ALERT) == (I2C_RIF_ALERT)); +} + +/** + * @brief Get timeout raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_tout(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TOUT) == (I2C_RIF_TOUT)); +} + +/** + * @brief Get PEC error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_pece(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_PECE) == (I2C_RIF_PECE)); +} + +/** + * @brief Get arbitration loss raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_arlo(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ARLO) == (I2C_RIF_ARLO)); +} + +/** + * @brief Get bus error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_berr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_BERR) == (I2C_RIF_BERR)); +} + +/** + * @brief Get stop detection raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_stop(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_STOP) == (I2C_RIF_STOP)); +} + +/** + * @brief Get NACK receiver raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_nack(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_NACK) == (I2C_RIF_NACK)); +} + +/** + * @brief Get address matched raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ADDR) == (I2C_RIF_ADDR)); +} + +/** + * @brief Get transfer complete and reload raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_tcr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TCR) == (I2C_RIF_TCR)); +} + +/** + * @brief Get transfer complete raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_tc(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TC) == (I2C_RIF_TC)); +} + +/** + * @brief Get receive buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_rxud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXUD) == (I2C_RIF_RXUD)); +} + +/** + * @brief Get receive buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_rxov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXOV) == (I2C_RIF_RXOV)); +} + + + +/** + * @brief Get receive buffer not empty raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_rxne(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXNE) == (I2C_RIF_RXNE)); +} + +/** + * @brief Get transmit buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_txud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXUD) == (I2C_RIF_TXUD)); +} + +/** + * @brief Get transmit buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_txov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXOV) == (I2C_RIF_TXOV)); +} + +/** + * @brief Get transmit buffer empty raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_it_txe(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXE) == (I2C_RIF_TXE)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group16 IFM + * @{ + */ +/** + * @brief Get I2C IFM + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_ifm(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_REG(I2Cx->IFM)); +} + +/** + * @brief Get SMBus alert interrupt flag massked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_alert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ALERT) == (I2C_IFM_ALERT)); +} + +/** + * @brief Get timeout interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_tout(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TOUT) == (I2C_IFM_TOUT)); +} + +/** + * @brief Get PEC error interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_pece(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_PECE) == (I2C_IFM_PECE)); +} + +/** + * @brief Get arbitration loss interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_arlo(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ARLO) == (I2C_IFM_ARLO)); +} + +/** + * @brief Get bus error interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_berr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_BERR) == (I2C_IFM_BERR)); +} + +/** + * @brief Get stop detection interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_stop(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_STOP) == (I2C_IFM_STOP)); +} + +/** + * @brief Get NACK receiver interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_nack(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_NACK) == (I2C_IFM_NACK)); +} + +/** + * @brief Get address matched interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ADDR) == (I2C_IFM_ADDR)); +} + +/** + * @brief Get transfer complete and reload interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_tcr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TCR) == (I2C_IFM_TCR)); +} + +/** + * @brief Get transfer complete interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_tc(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TC) == (I2C_IFM_TC)); +} + +/** + * @brief Get receive buffer underrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_rxud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXUD) == (I2C_IFM_RXUD)); +} + +/** + * @brief Get receive buffer ovrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_rxov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXOV) == (I2C_IFM_RXOV)); +} + +/** + * @brief Get receive buffer not empty interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_rxne(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXNE) == (I2C_IFM_RXNE)); +} + +/** + * @brief Get transmit buffer underrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_txud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXUD) == (I2C_IFM_TXUD)); +} + +/** + * @brief Get transmit buffer ovrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_txov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXOV) == (I2C_IFM_TXOV)); +} + +/** + * @brief Get transmit buffer empty interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_masked_it_txe(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXE) == (I2C_IFM_TXE)); +} +/** + * @} + */ + +/** @defgroup MD_I2C_Public_Functions_Group17 ICR + * @{ + */ +/** + * @brief Set I2C ICR + * @note None + * @param I2Cx I2C Instance + * @param icr + * @retval None + */ +__STATIC_INLINE void md_i2c_set_icr(I2C_TypeDef *I2Cx, uint32_t icr) +{ + WRITE_REG(I2Cx->ICR, icr); +} + +/** + * @brief Clear SMBus alert raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_alert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERT); +} + +/** + * @brief Clear timeout raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_tout(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TOUT); +} + +/** + * @brief Clear PEC error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_pece(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECE); +} + +/** + * @brief Clear arbitration loss raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_arlo(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLO); +} + +/** + * @brief Clear bus error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_berr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERR); +} + +/** + * @brief Clear stop detection raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_stop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOP); +} + +/** + * @brief Clear NACK receiver raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_nack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACK); +} + +/** + * @brief Clear address matched raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDR); +} + +/** + * @brief Clear transfer complete and reload raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_tcr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TCR); +} + +/** + * @brief Clear transfer complete raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_tc(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TC); +} + +/** + * @brief Clear receive buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_rxud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXUD); +} + +/** + * @brief Clear receive buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_rxov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXOV); +} + +/** + * @brief Clear receive buffer not empty raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_rxne(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXNE); +} + +/** + * @brief Clear transmit buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_txud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXUD); +} + +/** + * @brief Clear transmit buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_txov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXOV); +} + +/** + * @brief Clear transmit buffer empty raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_it_txe(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXE); +} +/** + * @} + */ + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param I2Cx I2C Instance. + * @param slave_address Specifies the slave address to be programmed. + * @param address_size This parameter can be one of the following values: + * @arg @ref MD_I2C_ADDRESS_SIZE_7BIT + * @arg @ref MD_I2C_ADDRESS_SIZE_10BIT + * @param transfer_size Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=65535. + * @param mode This parameter can be one of the following values: + * @arg @ref MD_I2C_MODE_RELOAD + * @arg @ref MD_I2C_MODE_AUTOEND + * @arg @ref MD_I2C_MODE_SOFTEND + * @arg @ref MD_I2C_MODE_SMBUS_RELOAD + * @arg @ref MD_I2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref MD_I2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref MD_I2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref MD_I2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param request This parameter can be one of the following values: + * @arg @ref MD_I2C_REQUEST_NOSTARTSTOP + * @arg @ref MD_I2C_REQUEST_STOP + * @arg @ref MD_I2C_REQUEST_START_READ + * @arg @ref MD_I2C_REQUEST_START_WRITE + * @arg @ref MD_I2C_REQUEST_RESTART_7BIT_READ + * @arg @ref MD_I2C_REQUEST_RESTART_7BIT_WRITE + * @arg @ref MD_I2C_REQUEST_RESTART_10BIT_READ + * @arg @ref MD_I2C_REQUEST_RESTART_10BIT_WRITE + * @retval None + */ +__STATIC_INLINE void md_i2c_handler_transfer(I2C_TypeDef *I2Cx, uint32_t slave_address, uint32_t address_size, uint32_t transfer_size, uint32_t mode, uint32_t request) +{ + if (request & I2C_CON2_RD_WRN) + { + MODIFY_REG(I2Cx->CON2, + I2C_CON2_PECBYTE | I2C_CON2_AUTOEND | I2C_CON2_RELOAD | I2C_CON2_NBYTES | I2C_CON2_NACK | I2C_CON2_STOP | I2C_CON2_START | I2C_CON2_HEAD10R | I2C_CON2_ADD10 | I2C_CON2_RD_WRN | I2C_CON2_SADD, + mode | (transfer_size & 0xFF) << I2C_CON2_NBYTES_POSS | request | slave_address | address_size << I2C_CON2_ADD10_POS); + } + else + { + MODIFY_REG(I2Cx->CON1, + I2C_CON1_NBYTES, + ((transfer_size & 0xFF00) >> 2) << I2C_CON1_NBYTES_POSS); + MODIFY_REG(I2Cx->CON2, + I2C_CON2_PECBYTE | I2C_CON2_AUTOEND | I2C_CON2_RELOAD | I2C_CON2_NBYTES | I2C_CON2_NACK | I2C_CON2_STOP | I2C_CON2_START | I2C_CON2_HEAD10R | I2C_CON2_ADD10 | I2C_CON2_RD_WRN | I2C_CON2_SADD, + mode | (transfer_size & 0xFF) << I2C_CON2_NBYTES_POSS | request | slave_address | address_size << I2C_CON2_ADD10_POS); + } +} + +/** @defgroup MD_I2C_Public_Functions_Group1 Initialization + * @{ + */ +//ErrorStatus md_i2c_deinit(I2C_TypeDef *I2Cx); +ErrorStatus md_i2c_init(I2C_TypeDef *I2Cx, md_i2c_inittypedef *I2C_InitStruct); +void md_i2c_struct_init(md_i2c_inittypedef *I2C_InitStruct); +void md_i2c_master_send(I2C_TypeDef *I2Cx, uint32_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *txbuf); +void md_i2c_master_receive(I2C_TypeDef *I2Cx, uint32_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *rxbuf); +void md_i2c_slave_send(I2C_TypeDef *I2Cx, uint32_t Num, uint8_t *txbuf); +void md_i2c_slave_receive(I2C_TypeDef *I2Cx, uint32_t Num, uint8_t *rxbuf); +void md_i2c_master_setting(I2C_TypeDef *I2Cx, uint32_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t WriteRead); +void md_i2c_clear_txbuff(I2C_TypeDef *I2Cx); +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup MD_I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_MD_I2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__ == I2C1) \ + || (__INSTANCE__ == I2C2)) + +#define IS_MD_I2C_TIMING(__VALUE__) ((__VALUE__ == CLK10kHz8M) \ + || (__VALUE__ == CLK100kHz8M) \ + || (__VALUE__ == CLK400kHz8M) \ + || (__VALUE__ == CLK500kHz8M) \ + || (__VALUE__ == CLK10kHz16M) \ + || (__VALUE__ == CLK100kHz16M) \ + || (__VALUE__ == CLK400kHz16M) \ + || (__VALUE__ == CLK1000kHz16M) \ + || (__VALUE__ == CLK10kHz48M) \ + || (__VALUE__ == CLK100kHz48M) \ + || (__VALUE__ == CLK400kHz48M) \ + || (__VALUE__ == CLK1000kHz48M)) + +#define IS_MD_I2C_ADDRSIZE(__VALUE__) ((__VALUE__ == MD_I2C_ADDRESSINGMODE_7BIT) \ + || (__VALUE__ == MD_I2C_ADDRESSINGMODE_10BIT)) + +#define IS_MD_I2C_ADDRESS1(__VALUE__) (__VALUE__ <= 0x000003FFU) +#define IS_MD_I2C_ADDRESS2(__VALUE__) (__VALUE__ <= (uint16_t)0x00FFU) + +#define IS_MD_I2C_DUALADDRESSMODE(__VALUE__) ((__VALUE__ == MD_I2C_OA2_DISABLE) \ + || (__VALUE__ == MD_I2C_OA2_ENABLE)) +#define IS_MD_I2C_ADDRESS2MASKS(__VALUE__) ((__VALUE__ == MD_I2C_ADDR2_NOMASK) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK01) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK02) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK03) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK04) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK05) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK06) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK07)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_iwdt.h b/os/common/ext/CMSIS/ES32/FS026/md/md_iwdt.h new file mode 100644 index 00000000000..3c4ec582453 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_iwdt.h @@ -0,0 +1,272 @@ +/********************************************************************************** + * + * @file md_iwdt.h + * @brief header file of md_iwdt.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 24 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_IWDT_H +#define __MD_IWDT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_IWDT IWDT + * @brief IWDT micro driver + * @{ + */ + +/** @defgroup MD_IWDT_Public_Macros IWDT Public Macros + * @{ + */ + +/** + * @brief MD_IWDT_Key IWDT Key + */ +#define IWDT_KEY_RELOAD 0x0000AAAAU /*!< IWDT Reload Counter Enable */ +#define IWDT_KEY_ENABLE 0x0000CCCCU /*!< IWDT Peripheral Enable */ +#define IWDT_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDT KR Write Access Enable */ + +/** + * @brief MD_IWDT_Prescaler IWDT Prescaler + */ +#define IWDT_PRESCALER_4 0x00000000U /*!< Divider by 4 */ +#define IWDT_PRESCALER_8 0x00000001U /*!< Divider by 8 */ +#define IWDT_PRESCALER_16 0x00000002U /*!< Divider by 16 */ +#define IWDT_PRESCALER_32 0x00000003U /*!< Divider by 32 */ +#define IWDT_PRESCALER_64 0x00000004U /*!< Divider by 64 */ +#define IWDT_PRESCALER_128 0x00000005U /*!< Divider by 128 */ +#define IWDT_PRESCALER_256 0x00000006U /*!< Divider by 256 */ +/** + * @} + */ + +/** @defgroup MD_IWDT_Public_Functions IWDT Public Functions + * @{ + */ + +/** @defgroup MD_IWDT_Public_Functions_Group2 BKKR + * @{ + */ + +/** + * @brief Start the Independent Watchdog + * @note if the hardware watchdog option is selected + * @param IWDTx IWDT Instance + * @retval None + */ +__STATIC_INLINE void md_iwdt_set_start(IWDT_TypeDef *IWDTx) +{ + WRITE_REG(IWDT->BKKR, IWDT_KEY_ENABLE); +} + +/** + * @brief Reload the Independent Watchdog + * @note if the hardware watchdog option is selected + * @param IWDTx IWDT Instance + * @retval None + */ +__STATIC_INLINE void md_iwdt_set_reload_counter(IWDT_TypeDef *IWDTx) +{ + WRITE_REG(IWDT->BKKR, IWDT_KEY_RELOAD); +} + +/** + * @brief Enable write access the Independent Watchdog + * @note if the hardware watchdog option is selected + * @param IWDTx IWDT Instance + * @retval None + */ +__STATIC_INLINE void md_iwdt_set_enable_write_access(IWDT_TypeDef *IWDTx) +{ + WRITE_REG(IWDT->BKKR, IWDT_KEY_WR_ACCESS_ENABLE); +} + +/** + * @} + */ + +/** @defgroup MD_IWDT_Public_Functions_Group3 BKPR + * @{ + */ + +/** + * @brief Select the prescaler of the IWDT + * @param IWDTx IWDT Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref IWDT_PRESCALER_4 + * @arg @ref IWDT_PRESCALER_8 + * @arg @ref IWDT_PRESCALER_16 + * @arg @ref IWDT_PRESCALER_32 + * @arg @ref IWDT_PRESCALER_64 + * @arg @ref IWDT_PRESCALER_128 + * @arg @ref IWDT_PRESCALER_256 + * @retval None + */ +__STATIC_INLINE void md_iwdt_set_prescaler(IWDT_TypeDef *IWDTx, uint32_t Prescaler) +{ + WRITE_REG(IWDTx->BKPR, Prescaler); +} + +/** + * @brief Get the selected prescaler of the IWDT + * @param IWDTx IWDT Instance + * @retval Returned value can be one of the following values: + * @arg @ref IWDT_PRESCALER_4 + * @arg @ref IWDT_PRESCALER_8 + * @arg @ref IWDT_PRESCALER_16 + * @arg @ref IWDT_PRESCALER_32 + * @arg @ref IWDT_PRESCALER_64 + * @arg @ref IWDT_PRESCALER_128 + * @arg @ref IWDT_PRESCALER_256 + */ +__STATIC_INLINE uint32_t md_iwdt_get_prescaler(IWDT_TypeDef *IWDTx) +{ + return (uint32_t)(READ_REG(IWDTx->BKPR)); +} +/** + * @} + */ + +/** @defgroup MD_IWDT_Public_Functions_Group4 BKRLR + * @{ + */ + +/** + * @brief Specify the IWDT down-counter reload value + * @param IWDTx IWDT Instance + * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void md_iwdt_set_reload(IWDT_TypeDef *IWDTx, uint32_t Counter) +{ + WRITE_REG(IWDTx->BKRLR, Counter); +} + +/** + * @brief Get the specified IWDT down-counter reload value + * @param IWDTx IWDT Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t md_iwdt_get_reload(IWDT_TypeDef *IWDTx) +{ + return (uint32_t)(READ_REG(IWDTx->BKRLR)); +} +/** + * @} + */ + +/** @defgroup MD_IWDT_Public_Functions_Group5 BKFR + * @{ + */ + +/** + * @brief Get Register update + * @param IWDTx IWDT Instance + * @retval + */ +__STATIC_INLINE uint32_t md_iwdt_is_active_flag_busy(IWDT_TypeDef *IWDTx) +{ + return (READ_REG(IWDTx->BKFR)); +} +/** + * @} + */ + +/** @defgroup MD_IWDT_Public_Functions_Group6 BKWINR + * @{ + */ + +/** + * @brief Specify high limit of the window value to be compared to the down-counter. + * @param IWDTx IWDT Instance + * @param Window Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void md_iwdt_set_window(IWDT_TypeDef *IWDTx, uint32_t Window) +{ + WRITE_REG(IWDTx->BKWINR, Window); +} + +/** + * @brief Get the high limit of the window value specified. + * @param IWDTx IWDT Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t md_iwdt_get_window(IWDT_TypeDef *IWDTx) +{ + return (uint32_t)(READ_REG(IWDTx->BKWINR)); +} +/** + * @} + */ + +/** @defgroup MD_IWDT_Public_Functions_Group7 BKSR + * @{ + */ + +/** + * @brief Get 12-bit counter. + * @param IWDTx IWDT Instance + * @retval + */ +__STATIC_INLINE uint32_t md_iwdt_get_count_value(IWDT_TypeDef *IWDTx) +{ + return (uint32_t)(READ_REG(IWDTx->BKSR)); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_kbcu.h b/os/common/ext/CMSIS/ES32/FS026/md/md_kbcu.h new file mode 100644 index 00000000000..fdfa645da2e --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_kbcu.h @@ -0,0 +1,3128 @@ +/********************************************************************************** + * + * @file md_kbcu.h + * @brief header file of md_kbcu.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 23 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_KBCU_H__ +#define __MD_KBCU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_KBCU KBCU + * @brief KBCU micro driver + * @{ + */ + +/** @defgroup MD_KBCU_Public_Macros KBCU Public Macros + * @{ + */ + + +/** + * @brief MD_KBCU_CON1_COL_CTRL Column Control + */ +#define MD_KBCU_CON1_COL_CTRL_DEF_H 0x00000000U /*!< Column Default Output High. Output Low when enabled. */ +#define MD_KBCU_CON1_COL_CTRL_DEF_L KBCU_CON1_COL_CTRL /*!< Column Default Output Low. Output High when enabled. */ + +/** + * @brief MD_KBCU_CON1_LED_CTRL LED Control + */ +#define MD_KBCU_CON1_LED_CTRL_DEF_L 0x00000000U /*!< PWM Default Output Low. Output High to Drive LED. */ +#define MD_KBCU_CON1_LED_CTRL_DEF_H KBCU_CON1_LED_CTRL /*!< PWM Default Output High. Output Low to Drive LED. */ + +/** + * @brief MD_KBCU_CON1_KEY_CTRL KEY Control + */ +#define MD_KBCU_CON1_KEY_CTRL_DETECT_L 0x00000000U /*!< Key Detect when Input Low. */ +#define MD_KBCU_CON1_KEY_CTRL_DETECT_H KBCU_CON1_KEY_CTRL /*!< Key Detect when Input High. */ + +/** + * @brief MD_KBCU_CON1_COLUMN_SEL Number of Column + */ +#define MD_KBCU_CON1_COLUMN_SEL_15 (0U) /*!< 15 columns*/ +#define MD_KBCU_CON1_COLUMN_SEL_16 (1U) /*!< 16 columns*/ +#define MD_KBCU_CON1_COLUMN_SEL_17 (2U) /*!< 17 columns*/ +#define MD_KBCU_CON1_COLUMN_SEL_18 (3U) /*!< 18 columns*/ +#define MD_KBCU_CON1_COLUMN_SEL_19 (4U) /*!< 19 columns*/ +#define MD_KBCU_CON1_COLUMN_SEL_20 (5U) /*!< 20 columns*/ +#define MD_KBCU_CON1_COLUMN_SEL_21 (6U) /*!< 21 columns*/ +#define MD_KBCU_CON1_COLUMN_SEL_22 (7U) /*!< 22 columns*/ +#define MD_KBCU_CON1_COLUMN_SEL_23 (8U) /*!< 23 columns*/ +#define MD_KBCU_CON1_COLUMN_SEL_24 (9U) /*!< 24 columns*/ + +/** + * @brief MD_KBCU_CON2_COLVALUE Number of Cycle in one Column + */ +#define MD_KBCU_CON2_COLVALUE_1 (0U ) /*!< 1 cycle in one column*/ +#define MD_KBCU_CON2_COLVALUE_2 (1U ) /*!< 2 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_3 (2U ) /*!< 3 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_4 (3U ) /*!< 4 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_5 (4U ) /*!< 5 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_6 (5U ) /*!< 6 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_7 (6U ) /*!< 7 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_8 (7U ) /*!< 8 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_9 (8U ) /*!< 9 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_10 (9U ) /*!< 10 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_11 (10U) /*!< 11 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_12 (11U) /*!< 12 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_13 (12U) /*!< 13 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_14 (13U) /*!< 14 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_15 (14U) /*!< 15 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_16 (15U) /*!< 16 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_17 (16U) /*!< 17 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_18 (17U) /*!< 18 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_19 (18U) /*!< 19 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_20 (19U) /*!< 20 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_21 (20U) /*!< 21 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_22 (21U) /*!< 22 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_23 (22U) /*!< 23 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_24 (23U) /*!< 24 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_25 (24U) /*!< 25 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_26 (25U) /*!< 26 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_27 (26U) /*!< 27 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_28 (27U) /*!< 28 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_29 (28U) /*!< 29 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_30 (29U) /*!< 30 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_31 (30U) /*!< 31 cycles in one column*/ +#define MD_KBCU_CON2_COLVALUE_32 (31U) /*!< 32 cycles in one column*/ + +/** + * @brief MD_KBCU_CON2_DTVALUE Dead Time Value + */ +#define MD_KBCU_CON2_DTVALUE_NONE (0U) /*!< None Dead Time*/ +#define MD_KBCU_CON2_DTVALUE_1 (1U) /*!< 1 Dead Time*/ +#define MD_KBCU_CON2_DTVALUE_2 (2U) /*!< 2 Dead Time*/ +#define MD_KBCU_CON2_DTVALUE_3 (3U) /*!< 3 Dead Time*/ +#define MD_KBCU_CON2_DTVALUE_4 (4U) /*!< 4 Dead Time*/ +#define MD_KBCU_CON2_DTVALUE_5 (5U) /*!< 5 Dead Time*/ +#define MD_KBCU_CON2_DTVALUE_6 (6U) /*!< 6 Dead Time*/ +#define MD_KBCU_CON2_DTVALUE_7 (7U) /*!< 7 Dead Time*/ + +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions KBCU Public Functions + * @{ + */ + +/** @defgroup MD_KBCU_Public_Functions_Group2 IER + * @{ + */ +/** + * @brief KBCU Set IER + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_ier(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->IER, Reg_Value); +} + +/** + * @brief Enable key interrupt + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_it_key(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->IER, KBCU_IER_KEY); +} + +/** + * @brief Enable column interrupt + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_it_column(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->IER, KBCU_IER_COLUMN); +} + +/** + * @brief Enable frame interrupt + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_it_frame(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->IER, KBCU_IER_FRAME); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group3 IDR + * @{ + */ +/** + * @brief KBCU Set IDR + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_idr(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->IDR, Reg_Value); +} + +/** + * @brief Disable key interrupt + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_it_key(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->IDR, KBCU_IDR_KEY); +} + +/** + * @brief Disable column interrupt + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_it_column(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->IDR, KBCU_IDR_COLUMN); +} + +/** + * @brief Disable frame interrupt + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_it_frame(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->IDR, KBCU_IDR_FRAME); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group4 IVS + * @{ + */ +/** + * @brief Get KBCU IVS + * @note None + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_ivs(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->IVS)); +} + +/** + * @brief Check if key interrupt is enabled + * @note None + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_it_key(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->IVS, KBCU_IVS_KEY) == (KBCU_IVS_KEY)); +} + +/** + * @brief Check if column interrupt is enabled + * @note None + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_it_column(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->IVS, KBCU_IVS_COLUMN) == (KBCU_IVS_COLUMN)); +} + +/** + * @brief Check if frame interrupt is enabled + * @note None + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_it_frame(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->IVS, KBCU_IVS_FRAME) == (KBCU_IVS_FRAME)); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group5 RIF + * @{ + */ +/** + * @brief Get KBCU RIF + * @note None + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_rif(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->RIF)); +} + +/** + * @brief Get key raw interrupt flag + * @note None + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_active_flag_key(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->RIF, KBCU_RIF_KEY) == (KBCU_RIF_KEY)); +} + +/** + * @brief Get column raw interrupt flag + * @note None + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_active_flag_column(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->RIF, KBCU_RIF_COLUMN) == (KBCU_RIF_COLUMN)); +} + +/** + * @brief Get frame raw interrupt flag + * @note None + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_active_flag_frame(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->RIF, KBCU_RIF_FRAME) == (KBCU_RIF_FRAME)); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group6 IFM + * @{ + */ +/** + * @brief Get KBCU IFM + * @note None + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_ifm(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->IFM)); +} + +/** + * @brief Get key interrupt flag massked status + * @note None + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_masked_it_key(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->IFM, KBCU_IFM_KEY) == (KBCU_IFM_KEY)); +} + +/** + * @brief Get column interrupt flag massked status + * @note None + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_masked_it_column(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->IFM, KBCU_IFM_COLUMN) == (KBCU_IFM_COLUMN)); +} + +/** + * @brief Get frame interrupt flag massked status + * @note None + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_masked_it_frame(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->IFM, KBCU_IFM_FRAME) == (KBCU_IFM_FRAME)); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group7 ICR + * @{ + */ +/** + * @brief Set KBCU ICR + * @note None + * @param KBCUx KBCU Instance + * @param icr + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_icr(KBCU_TypeDef *KBCUx, uint32_t icr) +{ + WRITE_REG(KBCUx->ICR, icr); +} + +/** + * @brief Clear key raw interrupt flag + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_clear_it_key(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->ICR, KBCU_ICR_KEY); +} + +/** + * @brief Clear column raw interrupt flag + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_clear_it_column(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->ICR, KBCU_ICR_COLUMN); +} + +/** + * @brief Clear frame raw interrupt flag + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_clear_it_frame(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->ICR, KBCU_ICR_FRAME); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group8 CON1 + * @{ + */ +/** + * @brief Set KBCU CON1 + * @note None + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con1(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->CON1, Reg_Value); +} + +/** + * @brief Get KBCU CON1 + * @note None + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_con1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->CON1)); +} + +/** + * @brief Set KBCU col_ctrl bit + * @param KBCUx KBCU Instance + * @param col_ctrl + * @arg @ref MD_KBCU_CON1_COL_CTRL_DEF_H + * @arg @ref MD_KBCU_CON1_COL_CTRL_DEF_L + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con1_col_ctrl(KBCU_TypeDef *KBCUx, uint32_t col_ctrl) +{ + MODIFY_REG(KBCUx->CON1, KBCU_CON1_COL_CTRL, col_ctrl); +} + +/** + * @brief Get KBCU col_ctrl bit + * @note None + * @param KBCUx KBCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_KBCU_CON1_COL_CTRL_DEF_H + * @arg @ref MD_KBCU_CON1_COL_CTRL_DEF_L + */ +__STATIC_INLINE uint32_t md_kbcu_get_con1_col_ctrl(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->CON1, KBCU_CON1_COL_CTRL)); +} + +/** + * @brief Set KBCU led_ctrl bit + * @param KBCUx KBCU Instance + * @param led_ctrl + * @arg @ref MD_KBCU_CON1_LED_CTRL_DEF_L + * @arg @ref MD_KBCU_CON1_LED_CTRL_DEF_H + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con1_led_ctrl(KBCU_TypeDef *KBCUx, uint32_t led_ctrl) +{ + MODIFY_REG(KBCUx->CON1, KBCU_CON1_LED_CTRL, led_ctrl); +} + +/** + * @brief Get KBCU led_ctrl bit + * @note None + * @param KBCUx KBCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_KBCU_CON1_LED_CTRL_DEF_L + * @arg @ref MD_KBCU_CON1_LED_CTRL_DEF_H + */ +__STATIC_INLINE uint32_t md_kbcu_get_con1_led_ctrl(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->CON1, KBCU_CON1_LED_CTRL)); +} + +/** + * @brief Set KBCU key_ctrl bit + * @param KBCUx KBCU Instance + * @param key_ctrl + * @arg @ref MD_KBCU_CON1_KEY_CTRL_DETECT_L + * @arg @ref MD_KBCU_CON1_KEY_CTRL_DETECT_H + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con1_key_ctrl(KBCU_TypeDef *KBCUx, uint32_t key_ctrl) +{ + MODIFY_REG(KBCUx->CON1, KBCU_CON1_KEY_CTRL, key_ctrl); +} + +/** + * @brief Get KBCU key_ctrl bit + * @note None + * @param KBCUx KBCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_KBCU_CON1_KEY_CTRL_DETECT_L + * @arg @ref MD_KBCU_CON1_KEY_CTRL_DETECT_H + */ +__STATIC_INLINE uint32_t md_kbcu_get_con1_key_ctrl(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->CON1, KBCU_CON1_KEY_CTRL)); +} + +/** + * @brief Get column switch flag + * @note The flag is clear when KBCU_LEDn is written. n=0~6. + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_active_flag_con1_col_flag(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->CON1, KBCU_CON1_COL_FLAG) == (KBCU_CON1_COL_FLAG)); +} + +/** + * @brief Set KBCU column mask number + * @note It is useless when the value of col_mask is bigger than that of colvalue. + * @param KBCUx KBCU Instance + * @param column_mask + * @arg Max Value 0x1F + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con1_col_mask(KBCU_TypeDef *KBCUx, uint32_t column_mask) +{ + MODIFY_REG(KBCUx->CON1, KBCU_CON1_COL_MASK, column_mask << KBCU_CON1_COL_MASK_POSS); +} + +/** + * @brief Get KBCU column mask number + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x1F + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_con1_col_mask(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->CON1, KBCU_CON1_COL_MASK) >> KBCU_CON1_COL_MASK_POSS); +} + +/** + * @brief Set KBCU number of column + * @note It will disable the column output when column_sel is written unexpected value. + * @param KBCUx KBCU Instance + * @param column_sel + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_15 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_16 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_17 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_18 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_19 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_20 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_21 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_22 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_23 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_24 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con1_column_sel(KBCU_TypeDef *KBCUx, uint32_t column_sel) +{ + MODIFY_REG(KBCUx->CON1, KBCU_CON1_COLUMN_SEL, column_sel << KBCU_CON1_COLUMN_SEL_POSS); +} + +/** + * @brief Get KBCU number of column + * @param KBCUx KBCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_15 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_16 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_17 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_18 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_19 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_20 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_21 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_22 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_23 + * @arg @ref MD_KBCU_CON1_COLUMN_SEL_24 + */ +__STATIC_INLINE uint32_t md_kbcu_get_con1_column_sel(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->CON1, KBCU_CON1_COL_MASK) >> KBCU_CON1_COLUMN_SEL_POSS); +} + +/** + * @brief Enable KBCU blink function + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_con1_blink(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->CON1, KBCU_CON1_BLINK); +} + +/** + * @brief Disable KBCU blink function + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_con1_blink(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->CON1, KBCU_CON1_BLINK); +} + +/** + * @brief Indicate if KBCU blink is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_con1_blink(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->CON1, KBCU_CON1_BLINK) == (KBCU_CON1_BLINK)); +} + +/** + * @brief Enable KBCU + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_con1_kben(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->CON1, KBCU_CON1_KBEN); +} + +/** + * @brief Disable KBCU + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_con1_kben(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->CON1, KBCU_CON1_KBEN); +} + +/** + * @brief Indicate if KBCU is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_con1_kben(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->CON1, KBCU_CON1_KBEN) == (KBCU_CON1_KBEN)); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group9 CON2 + * @{ + */ +/** + * @brief Set KBCU CON2 + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con2(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->CON2, Reg_Value); +} + +/** + * @brief Get KBCU CON2 + * @note None + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_con2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->CON2)); +} + +/** + * @brief Set KBCU the value of cycle in one column + * @note None + * @param KBCUx KBCU Instance + * @param colvalue + * @arg @ref MD_KBCU_CON2_COLVALUE_1 + * @arg @ref MD_KBCU_CON2_COLVALUE_2 + * @arg @ref MD_KBCU_CON2_COLVALUE_3 + * @arg @ref MD_KBCU_CON2_COLVALUE_4 + * @arg @ref MD_KBCU_CON2_COLVALUE_5 + * @arg @ref MD_KBCU_CON2_COLVALUE_6 + * @arg @ref MD_KBCU_CON2_COLVALUE_7 + * @arg @ref MD_KBCU_CON2_COLVALUE_8 + * @arg @ref MD_KBCU_CON2_COLVALUE_9 + * @arg @ref MD_KBCU_CON2_COLVALUE_10 + * @arg @ref MD_KBCU_CON2_COLVALUE_11 + * @arg @ref MD_KBCU_CON2_COLVALUE_12 + * @arg @ref MD_KBCU_CON2_COLVALUE_13 + * @arg @ref MD_KBCU_CON2_COLVALUE_14 + * @arg @ref MD_KBCU_CON2_COLVALUE_15 + * @arg @ref MD_KBCU_CON2_COLVALUE_16 + * @arg @ref MD_KBCU_CON2_COLVALUE_17 + * @arg @ref MD_KBCU_CON2_COLVALUE_18 + * @arg @ref MD_KBCU_CON2_COLVALUE_19 + * @arg @ref MD_KBCU_CON2_COLVALUE_20 + * @arg @ref MD_KBCU_CON2_COLVALUE_21 + * @arg @ref MD_KBCU_CON2_COLVALUE_22 + * @arg @ref MD_KBCU_CON2_COLVALUE_23 + * @arg @ref MD_KBCU_CON2_COLVALUE_24 + * @arg @ref MD_KBCU_CON2_COLVALUE_25 + * @arg @ref MD_KBCU_CON2_COLVALUE_26 + * @arg @ref MD_KBCU_CON2_COLVALUE_27 + * @arg @ref MD_KBCU_CON2_COLVALUE_28 + * @arg @ref MD_KBCU_CON2_COLVALUE_29 + * @arg @ref MD_KBCU_CON2_COLVALUE_30 + * @arg @ref MD_KBCU_CON2_COLVALUE_31 + * @arg @ref MD_KBCU_CON2_COLVALUE_32 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con2_colvalue(KBCU_TypeDef *KBCUx, uint32_t colvalue) +{ + MODIFY_REG(KBCUx->CON2, KBCU_CON2_COLVALUE, colvalue << KBCU_CON2_COLVALUE_POSS); +} + +/** + * @brief Get KBCU the value of cycle in one column + * @param KBCUx KBCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_KBCU_CON2_COLVALUE_1 + * @arg @ref MD_KBCU_CON2_COLVALUE_2 + * @arg @ref MD_KBCU_CON2_COLVALUE_3 + * @arg @ref MD_KBCU_CON2_COLVALUE_4 + * @arg @ref MD_KBCU_CON2_COLVALUE_5 + * @arg @ref MD_KBCU_CON2_COLVALUE_6 + * @arg @ref MD_KBCU_CON2_COLVALUE_7 + * @arg @ref MD_KBCU_CON2_COLVALUE_8 + * @arg @ref MD_KBCU_CON2_COLVALUE_9 + * @arg @ref MD_KBCU_CON2_COLVALUE_10 + * @arg @ref MD_KBCU_CON2_COLVALUE_11 + * @arg @ref MD_KBCU_CON2_COLVALUE_12 + * @arg @ref MD_KBCU_CON2_COLVALUE_13 + * @arg @ref MD_KBCU_CON2_COLVALUE_14 + * @arg @ref MD_KBCU_CON2_COLVALUE_15 + * @arg @ref MD_KBCU_CON2_COLVALUE_16 + * @arg @ref MD_KBCU_CON2_COLVALUE_17 + * @arg @ref MD_KBCU_CON2_COLVALUE_18 + * @arg @ref MD_KBCU_CON2_COLVALUE_19 + * @arg @ref MD_KBCU_CON2_COLVALUE_20 + * @arg @ref MD_KBCU_CON2_COLVALUE_21 + * @arg @ref MD_KBCU_CON2_COLVALUE_22 + * @arg @ref MD_KBCU_CON2_COLVALUE_23 + * @arg @ref MD_KBCU_CON2_COLVALUE_24 + * @arg @ref MD_KBCU_CON2_COLVALUE_25 + * @arg @ref MD_KBCU_CON2_COLVALUE_26 + * @arg @ref MD_KBCU_CON2_COLVALUE_27 + * @arg @ref MD_KBCU_CON2_COLVALUE_28 + * @arg @ref MD_KBCU_CON2_COLVALUE_29 + * @arg @ref MD_KBCU_CON2_COLVALUE_30 + * @arg @ref MD_KBCU_CON2_COLVALUE_31 + * @arg @ref MD_KBCU_CON2_COLVALUE_32 + */ +__STATIC_INLINE uint32_t md_kbcu_get_con2_colvalue(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->CON2, KBCU_CON2_COLVALUE) >> KBCU_CON2_COLVALUE_POSS); +} + +/** + * @brief Set KBCU dead time value + * @note None + * @param KBCUx KBCU Instance + * @param dtvalue + * @arg @ref MD_KBCU_CON2_DTVALUE_NONE + * @arg @ref MD_KBCU_CON2_DTVALUE_1 + * @arg @ref MD_KBCU_CON2_DTVALUE_2 + * @arg @ref MD_KBCU_CON2_DTVALUE_3 + * @arg @ref MD_KBCU_CON2_DTVALUE_4 + * @arg @ref MD_KBCU_CON2_DTVALUE_5 + * @arg @ref MD_KBCU_CON2_DTVALUE_6 + * @arg @ref MD_KBCU_CON2_DTVALUE_7 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con2_dtvalue(KBCU_TypeDef *KBCUx, uint32_t dtvalue) +{ + MODIFY_REG(KBCUx->CON2, KBCU_CON2_DTVALUE, dtvalue << KBCU_CON2_DTVALUE_POSS); +} + +/** + * @brief Get KBCU dead time value + * @param KBCUx KBCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_KBCU_CON2_DTVALUE_NONE + * @arg @ref MD_KBCU_CON2_DTVALUE_1 + * @arg @ref MD_KBCU_CON2_DTVALUE_2 + * @arg @ref MD_KBCU_CON2_DTVALUE_3 + * @arg @ref MD_KBCU_CON2_DTVALUE_4 + * @arg @ref MD_KBCU_CON2_DTVALUE_5 + * @arg @ref MD_KBCU_CON2_DTVALUE_6 + * @arg @ref MD_KBCU_CON2_DTVALUE_7 + */ +__STATIC_INLINE uint32_t md_kbcu_get_con2_dtvalue(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->CON2, KBCU_CON2_DTVALUE) >> KBCU_CON2_DTVALUE_POSS); +} + +/** + * @brief Set KBCU the number of frame to trigger frame interrupt + * @note None + * @param KBCUx KBCU Instance + * @param fcvalue + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con2_fcvalue(KBCU_TypeDef *KBCUx, uint32_t fcvalue) +{ + MODIFY_REG(KBCUx->CON2, KBCU_CON2_FCVALUE, fcvalue << KBCU_CON2_FCVALUE_POSS); +} + +/** + * @brief Get KBCU the number of frame to trigger frame interrupt + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_con2_fcvalue(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->CON2, KBCU_CON2_FCVALUE) >> KBCU_CON2_FCVALUE_POSS); +} + +/** + * @brief Set KBCU the divider of HCLK + * @note None + * @param KBCUx KBCU Instance + * @param frdiv + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con2_frdiv(KBCU_TypeDef *KBCUx, uint32_t frdiv) +{ + MODIFY_REG(KBCUx->CON2, KBCU_CON2_FRDIV, frdiv << KBCU_CON2_FRDIV_POSS); +} + +/** + * @brief Get KBCU the divider of HCLK + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_con2_frdiv(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->CON2, KBCU_CON2_FRDIV) >> KBCU_CON2_FRDIV_POSS); +} + +/** + * @brief Set KBCU the auto reload value + * @note None + * @param KBCUx KBCU Instance + * @param arvalue + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_con2_arvalue(KBCU_TypeDef *KBCUx, uint32_t arvalue) +{ + MODIFY_REG(KBCUx->CON2, KBCU_CON2_ARVALUE, arvalue << KBCU_CON2_ARVALUE_POSS); +} + +/** + * @brief Get KBCU the auto reload value + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_con2_arvalue(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->CON2, KBCU_CON2_ARVALUE) >> KBCU_CON2_ARVALUE_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group10 SCAN0 + * @{ + */ +/** + * @brief Get KBCU SCAN0 + * @note Reading SCAN0 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan0(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->SCAN0)); +} + +/** + * @brief Get KBCU the position of pressed keys in column3 + * @note Reading SCAN0 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan0_column3(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN0, KBCU_SCAN0_COLUMN3) >> KBCU_SCAN0_COLUMN3_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column2 + * @note Reading SCAN0 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan0_column2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN0, KBCU_SCAN0_COLUMN2) >> KBCU_SCAN0_COLUMN2_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column1 + * @note Reading SCAN0 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan0_column1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN0, KBCU_SCAN0_COLUMN1) >> KBCU_SCAN0_COLUMN1_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column0 + * @note Reading SCAN0 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan0_column0(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN0, KBCU_SCAN0_COLUMN0) >> KBCU_SCAN0_COLUMN0_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group11 SCAN1 + * @{ + */ +/** + * @brief Get KBCU SCAN1 + * @note Reading SCAN1 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->SCAN1)); +} + +/** + * @brief Get KBCU the position of pressed keys in column7 + * @note Reading SCAN1 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan1_column7(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN1, KBCU_SCAN1_COLUMN7) >> KBCU_SCAN1_COLUMN7_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column6 + * @note Reading SCAN1 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan1_column6(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN1, KBCU_SCAN1_COLUMN6) >> KBCU_SCAN1_COLUMN6_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column5 + * @note Reading SCAN1 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan1_column5(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN1, KBCU_SCAN1_COLUMN5) >> KBCU_SCAN1_COLUMN5_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column4 + * @note Reading SCAN1 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan1_column4(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN1, KBCU_SCAN1_COLUMN4) >> KBCU_SCAN1_COLUMN4_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group12 SCAN2 + * @{ + */ +/** + * @brief Get KBCU SCAN2 + * @note Reading SCAN2 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->SCAN2)); +} + +/** + * @brief Get KBCU the position of pressed keys in column11 + * @note Reading SCAN2 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan2_column11(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN2, KBCU_SCAN2_COLUMN11) >> KBCU_SCAN2_COLUMN11_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column10 + * @note Reading SCAN2 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan2_column10(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN2, KBCU_SCAN2_COLUMN10) >> KBCU_SCAN2_COLUMN10_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column9 + * @note Reading SCAN2 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan2_column9(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN2, KBCU_SCAN2_COLUMN9) >> KBCU_SCAN2_COLUMN9_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column8 + * @note Reading SCAN2 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan2_column8(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN2, KBCU_SCAN2_COLUMN8) >> KBCU_SCAN2_COLUMN8_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group13 SCAN3 + * @{ + */ +/** + * @brief Get KBCU SCAN3 + * @note Reading SCAN3 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan3(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->SCAN3)); +} + +/** + * @brief Get KBCU the position of pressed keys in column15 + * @note Reading SCAN3 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan3_column15(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN3, KBCU_SCAN3_COLUMN15) >> KBCU_SCAN3_COLUMN15_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column14 + * @note Reading SCAN3 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan3_column14(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN3, KBCU_SCAN3_COLUMN14) >> KBCU_SCAN3_COLUMN14_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column13 + * @note Reading SCAN3 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan3_column13(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN3, KBCU_SCAN3_COLUMN13) >> KBCU_SCAN3_COLUMN13_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column12 + * @note Reading SCAN3 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan3_column12(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN3, KBCU_SCAN3_COLUMN12) >> KBCU_SCAN3_COLUMN12_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group14 SCAN4 + * @{ + */ +/** + * @brief Get KBCU SCAN4 + * @note Reading SCAN4 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan4(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->SCAN4)); +} + +/** + * @brief Get KBCU the position of pressed keys in column19 + * @note Reading SCAN4 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan4_column19(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN4, KBCU_SCAN4_COLUMN19) >> KBCU_SCAN4_COLUMN19_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column18 + * @note Reading SCAN4 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan4_column18(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN4, KBCU_SCAN4_COLUMN18) >> KBCU_SCAN4_COLUMN18_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column17 + * @note Reading SCAN4 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan4_column17(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN4, KBCU_SCAN4_COLUMN17) >> KBCU_SCAN4_COLUMN17_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column16 + * @note Reading SCAN4 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan4_column16(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN4, KBCU_SCAN4_COLUMN16) >> KBCU_SCAN4_COLUMN16_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group15 SCAN5 + * @{ + */ +/** + * @brief Get KBCU SCAN5 + * @note Reading SCAN5 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan5(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->SCAN5)); +} + +/** + * @brief Get KBCU the position of pressed keys in column23 + * @note Reading SCAN5 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan5_column23(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN5, KBCU_SCAN5_COLUMN23) >> KBCU_SCAN5_COLUMN23_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column22 + * @note Reading SCAN5 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan5_column22(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN5, KBCU_SCAN5_COLUMN22) >> KBCU_SCAN5_COLUMN22_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column21 + * @note Reading SCAN5 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan5_column21(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN5, KBCU_SCAN5_COLUMN21) >> KBCU_SCAN5_COLUMN21_POSS); +} + +/** + * @brief Get KBCU the position of pressed keys in column20 + * @note Reading SCAN5 automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Row0 + * Bit1 mapping Row1 + * Bit2 mapping Row2 + * Bit3 mapping Row3 + * Bit4 mapping Row4 + * Bit5 mapping Row5 + * Bit6 mapping Row6 + */ +__STATIC_INLINE uint32_t md_kbcu_get_scan5_column20(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->SCAN5, KBCU_SCAN5_COLUMN20) >> KBCU_SCAN5_COLUMN20_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group16 STAT + * @{ + */ +/** + * @brief Get KBCU STAT + * @note Reading STAT automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_stat(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->STAT)); +} + +/** + * @brief Get KBCU which columns where there are pressed keys are detected. + * @note Reading STAT automatically clears it to 0. + * @param KBCUx KBCU Instance + * @retval Bitmap: + * Bit0 mapping Column0 + * Bit1 mapping Column1 + * Bit2 mapping Column2 + * . + * . + * . + * Bit21 mapping Column21 + * Bit22 mapping Column22 + * Bit23 mapping Column23 + */ +__STATIC_INLINE uint32_t md_kbcu_get_stat_column(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->STAT, KBCU_STAT_COLUMN) >> KBCU_STAT_COLUMN_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group17 LED0 + * @{ + */ +/** + * @brief Set KBCU LED0 + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led0(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->LED0, Reg_Value); +} + +/** + * @brief Get KBCU LED0 + * @note None. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_led0(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->LED0)); +} + +/** + * @brief Set KBCU the PWM mask in one column in Row0 + * @note None + * @param KBCUx KBCU Instance + * @param mask + * @arg Max Value 0x1F + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led0_mask(KBCU_TypeDef *KBCUx, uint32_t mask) +{ + MODIFY_REG(KBCUx->LED0, KBCU_LED0_MASK, mask << KBCU_LED0_MASK_POSS); +} + +/** + * @brief Get KBCU the PWM mask in one column in Row0 + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x1F + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led0_mask(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED0, KBCU_LED0_MASK) >> KBCU_LED0_MASK_POSS); +} + +/** + * @brief Enable KBCU Row0 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led0_duty2_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED0, KBCU_LED0_DUTY2_H); +} + +/** + * @brief Disable KBCU Row0 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led0_duty2_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED0, KBCU_LED0_DUTY2_H); +} + +/** + * @brief Indicate if Row0 PWM2 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led0_duty2_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED0, KBCU_LED0_DUTY2_H) == (KBCU_LED0_DUTY2_H)); +} + +/** + * @brief Enable KBCU Row0 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led0_duty1_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED0, KBCU_LED0_DUTY1_H); +} + +/** + * @brief Disable KBCU Row0 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led0_duty1_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED0, KBCU_LED0_DUTY1_H); +} + +/** + * @brief Indicate if Row0 PWM1 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led0_duty1_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED0, KBCU_LED0_DUTY1_H) == (KBCU_LED0_DUTY1_H)); +} + +/** + * @brief Enable KBCU Row0 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led0_duty0_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED0, KBCU_LED0_DUTY0_H); +} + +/** + * @brief Disable KBCU Row0 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led0_duty0_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED0, KBCU_LED0_DUTY0_H); +} + +/** + * @brief Indicate if Row0 PWM0 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led0_duty0_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED0, KBCU_LED0_DUTY0_H) == (KBCU_LED0_DUTY0_H)); +} + +/** + * @brief Set KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row0. + * @param KBCUx KBCU Instance + * @param duty2 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led0_duty2(KBCU_TypeDef *KBCUx, uint32_t duty2) +{ + MODIFY_REG(KBCUx->LED0, KBCU_LED0_DUTY2, duty2 << KBCU_LED0_DUTY2_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row0. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led0_duty2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED0, KBCU_LED0_DUTY2) >> KBCU_LED0_DUTY2_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row0. + * @param KBCUx KBCU Instance + * @param duty1 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led0_duty1(KBCU_TypeDef *KBCUx, uint32_t duty1) +{ + MODIFY_REG(KBCUx->LED0, KBCU_LED0_DUTY1, duty1 << KBCU_LED0_DUTY1_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row0. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led0_duty1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED0, KBCU_LED0_DUTY1) >> KBCU_LED0_DUTY1_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row0. + * @param KBCUx KBCU Instance + * @param duty0 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led0_duty0(KBCU_TypeDef *KBCUx, uint32_t duty0) +{ + MODIFY_REG(KBCUx->LED0, KBCU_LED0_DUTY0, duty0 << KBCU_LED0_DUTY0_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row0. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led0_duty0(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED0, KBCU_LED0_DUTY0) >> KBCU_LED0_DUTY0_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group18 LED1 + * @{ + */ +/** + * @brief Set KBCU LED1 + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led1(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->LED1, Reg_Value); +} + +/** + * @brief Get KBCU LED1 + * @note None. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_led1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->LED1)); +} + +/** + * @brief Set KBCU the PWM mask in one column in Row1 + * @note None + * @param KBCUx KBCU Instance + * @param mask + * @arg Max Value 0x1F + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led1_mask(KBCU_TypeDef *KBCUx, uint32_t mask) +{ + MODIFY_REG(KBCUx->LED1, KBCU_LED1_MASK, mask << KBCU_LED1_MASK_POSS); +} + +/** + * @brief Get KBCU the PWM mask in one column in Row1 + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x1F + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led1_mask(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED1, KBCU_LED1_MASK) >> KBCU_LED1_MASK_POSS); +} + +/** + * @brief Enable KBCU Row1 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led1_duty2_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED1, KBCU_LED1_DUTY2_H); +} + +/** + * @brief Disable KBCU Row1 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led1_duty2_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED1, KBCU_LED1_DUTY2_H); +} + +/** + * @brief Indicate if Row1 PWM2 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led1_duty2_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED1, KBCU_LED1_DUTY2_H) == (KBCU_LED1_DUTY2_H)); +} + +/** + * @brief Enable KBCU Row1 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led1_duty1_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED1, KBCU_LED1_DUTY1_H); +} + +/** + * @brief Disable KBCU Row1 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led1_duty1_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED1, KBCU_LED1_DUTY1_H); +} + +/** + * @brief Indicate if Row1 PWM1 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led1_duty1_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED1, KBCU_LED1_DUTY1_H) == (KBCU_LED1_DUTY1_H)); +} + +/** + * @brief Enable KBCU Row1 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led1_duty0_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED1, KBCU_LED1_DUTY0_H); +} + +/** + * @brief Disable KBCU Row1 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led1_duty0_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED1, KBCU_LED1_DUTY0_H); +} + +/** + * @brief Indicate if Row1 PWM0 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led1_duty0_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED1, KBCU_LED1_DUTY0_H) == (KBCU_LED1_DUTY0_H)); +} + +/** + * @brief Set KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row1. + * @param KBCUx KBCU Instance + * @param duty2 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led1_duty2(KBCU_TypeDef *KBCUx, uint32_t duty2) +{ + MODIFY_REG(KBCUx->LED1, KBCU_LED1_DUTY2, duty2 << KBCU_LED1_DUTY2_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row1. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led1_duty2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED1, KBCU_LED1_DUTY2) >> KBCU_LED1_DUTY2_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row1. + * @param KBCUx KBCU Instance + * @param duty1 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led1_duty1(KBCU_TypeDef *KBCUx, uint32_t duty1) +{ + MODIFY_REG(KBCUx->LED1, KBCU_LED1_DUTY1, duty1 << KBCU_LED1_DUTY1_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row1. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led1_duty1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED1, KBCU_LED1_DUTY1) >> KBCU_LED1_DUTY1_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row1. + * @param KBCUx KBCU Instance + * @param duty0 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led1_duty0(KBCU_TypeDef *KBCUx, uint32_t duty0) +{ + MODIFY_REG(KBCUx->LED1, KBCU_LED1_DUTY0, duty0 << KBCU_LED1_DUTY0_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row1. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led1_duty0(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED1, KBCU_LED1_DUTY0) >> KBCU_LED1_DUTY0_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group19 LED2 + * @{ + */ +/** + * @brief Set KBCU LED2 + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led2(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->LED2, Reg_Value); +} + +/** + * @brief Get KBCU LED2 + * @note None. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_led2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->LED2)); +} + +/** + * @brief Set KBCU the PWM mask in one column in Row2 + * @note None + * @param KBCUx KBCU Instance + * @param mask + * @arg Max Value 0x1F + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led2_mask(KBCU_TypeDef *KBCUx, uint32_t mask) +{ + MODIFY_REG(KBCUx->LED2, KBCU_LED2_MASK, mask << KBCU_LED2_MASK_POSS); +} + +/** + * @brief Get KBCU the PWM mask in one column in Row2 + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x1F + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led2_mask(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED2, KBCU_LED2_MASK) >> KBCU_LED2_MASK_POSS); +} + +/** + * @brief Enable KBCU Row2 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led2_duty2_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED2, KBCU_LED2_DUTY2_H); +} + +/** + * @brief Disable KBCU Row2 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led2_duty2_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED2, KBCU_LED2_DUTY2_H); +} + +/** + * @brief Indicate if Row2 PWM2 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led2_duty2_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED2, KBCU_LED2_DUTY2_H) == (KBCU_LED2_DUTY2_H)); +} + +/** + * @brief Enable KBCU Row2 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led2_duty1_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED2, KBCU_LED2_DUTY1_H); +} + +/** + * @brief Disable KBCU Row2 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led2_duty1_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED2, KBCU_LED2_DUTY1_H); +} + +/** + * @brief Indicate if Row2 PWM1 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led2_duty1_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED2, KBCU_LED2_DUTY1_H) == (KBCU_LED2_DUTY1_H)); +} + +/** + * @brief Enable KBCU Row2 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led2_duty0_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED2, KBCU_LED2_DUTY0_H); +} + +/** + * @brief Disable KBCU Row2 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led2_duty0_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED2, KBCU_LED2_DUTY0_H); +} + +/** + * @brief Indicate if Row2 PWM0 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led2_duty0_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED2, KBCU_LED2_DUTY0_H) == (KBCU_LED2_DUTY0_H)); +} + +/** + * @brief Set KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row2. + * @param KBCUx KBCU Instance + * @param duty2 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led2_duty2(KBCU_TypeDef *KBCUx, uint32_t duty2) +{ + MODIFY_REG(KBCUx->LED2, KBCU_LED2_DUTY2, duty2 << KBCU_LED2_DUTY2_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row2. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led2_duty2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED2, KBCU_LED2_DUTY2) >> KBCU_LED2_DUTY2_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row2. + * @param KBCUx KBCU Instance + * @param duty1 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led2_duty1(KBCU_TypeDef *KBCUx, uint32_t duty1) +{ + MODIFY_REG(KBCUx->LED2, KBCU_LED2_DUTY1, duty1 << KBCU_LED2_DUTY1_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row2. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led2_duty1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED2, KBCU_LED2_DUTY1) >> KBCU_LED2_DUTY1_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row2. + * @param KBCUx KBCU Instance + * @param duty0 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led2_duty0(KBCU_TypeDef *KBCUx, uint32_t duty0) +{ + MODIFY_REG(KBCUx->LED2, KBCU_LED2_DUTY0, duty0 << KBCU_LED2_DUTY0_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row2. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led2_duty0(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED2, KBCU_LED2_DUTY0) >> KBCU_LED2_DUTY0_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group20 LED3 + * @{ + */ +/** + * @brief Set KBCU LED3 + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led3(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->LED3, Reg_Value); +} + +/** + * @brief Get KBCU LED3 + * @note None. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_led3(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->LED3)); +} + +/** + * @brief Set KBCU the PWM mask in one column in Row3 + * @note None + * @param KBCUx KBCU Instance + * @param mask + * @arg Max Value 0x1F + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led3_mask(KBCU_TypeDef *KBCUx, uint32_t mask) +{ + MODIFY_REG(KBCUx->LED3, KBCU_LED3_MASK, mask << KBCU_LED3_MASK_POSS); +} + +/** + * @brief Get KBCU the PWM mask in one column in Row3 + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x1F + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led3_mask(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED3, KBCU_LED3_MASK) >> KBCU_LED3_MASK_POSS); +} + +/** + * @brief Enable KBCU Row3 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led3_duty2_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED3, KBCU_LED3_DUTY2_H); +} + +/** + * @brief Disable KBCU Row3 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led3_duty2_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED3, KBCU_LED3_DUTY2_H); +} + +/** + * @brief Indicate if Row3 PWM2 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led3_duty2_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED3, KBCU_LED3_DUTY2_H) == (KBCU_LED3_DUTY2_H)); +} + +/** + * @brief Enable KBCU Row3 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led3_duty1_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED3, KBCU_LED3_DUTY1_H); +} + +/** + * @brief Disable KBCU Row3 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led3_duty1_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED3, KBCU_LED3_DUTY1_H); +} + +/** + * @brief Indicate if Row3 PWM1 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led3_duty1_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED3, KBCU_LED3_DUTY1_H) == (KBCU_LED3_DUTY1_H)); +} + +/** + * @brief Enable KBCU Row3 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led3_duty0_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED3, KBCU_LED3_DUTY0_H); +} + +/** + * @brief Disable KBCU Row3 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led3_duty0_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED3, KBCU_LED3_DUTY0_H); +} + +/** + * @brief Indicate if Row3 PWM0 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led3_duty0_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED3, KBCU_LED3_DUTY0_H) == (KBCU_LED3_DUTY0_H)); +} + +/** + * @brief Set KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row3. + * @param KBCUx KBCU Instance + * @param duty2 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led3_duty2(KBCU_TypeDef *KBCUx, uint32_t duty2) +{ + MODIFY_REG(KBCUx->LED3, KBCU_LED3_DUTY2, duty2 << KBCU_LED3_DUTY2_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row3. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led3_duty2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED3, KBCU_LED3_DUTY2) >> KBCU_LED3_DUTY2_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row3. + * @param KBCUx KBCU Instance + * @param duty1 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led3_duty1(KBCU_TypeDef *KBCUx, uint32_t duty1) +{ + MODIFY_REG(KBCUx->LED3, KBCU_LED3_DUTY1, duty1 << KBCU_LED3_DUTY1_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row3. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led3_duty1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED3, KBCU_LED3_DUTY1) >> KBCU_LED3_DUTY1_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row3. + * @param KBCUx KBCU Instance + * @param duty0 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led3_duty0(KBCU_TypeDef *KBCUx, uint32_t duty0) +{ + MODIFY_REG(KBCUx->LED3, KBCU_LED3_DUTY0, duty0 << KBCU_LED3_DUTY0_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row3. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led3_duty0(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED3, KBCU_LED3_DUTY0) >> KBCU_LED3_DUTY0_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group21 LED4 + * @{ + */ +/** + * @brief Set KBCU LED4 + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led4(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->LED4, Reg_Value); +} + +/** + * @brief Get KBCU LED4 + * @note None. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_led4(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->LED4)); +} + +/** + * @brief Set KBCU the PWM mask in one column in Row4 + * @note None + * @param KBCUx KBCU Instance + * @param mask + * @arg Max Value 0x1F + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led4_mask(KBCU_TypeDef *KBCUx, uint32_t mask) +{ + MODIFY_REG(KBCUx->LED4, KBCU_LED4_MASK, mask << KBCU_LED4_MASK_POSS); +} + +/** + * @brief Get KBCU the PWM mask in one column in Row4 + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x1F + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led4_mask(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED4, KBCU_LED4_MASK) >> KBCU_LED4_MASK_POSS); +} + +/** + * @brief Enable KBCU Row4 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led4_duty2_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED4, KBCU_LED4_DUTY2_H); +} + +/** + * @brief Disable KBCU Row4 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led4_duty2_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED4, KBCU_LED4_DUTY2_H); +} + +/** + * @brief Indicate if Row4 PWM2 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led4_duty2_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED4, KBCU_LED4_DUTY2_H) == (KBCU_LED4_DUTY2_H)); +} + +/** + * @brief Enable KBCU Row4 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led4_duty1_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED4, KBCU_LED4_DUTY1_H); +} + +/** + * @brief Disable KBCU Row4 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led4_duty1_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED4, KBCU_LED4_DUTY1_H); +} + +/** + * @brief Indicate if Row4 PWM1 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led4_duty1_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED4, KBCU_LED4_DUTY1_H) == (KBCU_LED4_DUTY1_H)); +} + +/** + * @brief Enable KBCU Row4 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led4_duty0_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED4, KBCU_LED4_DUTY0_H); +} + +/** + * @brief Disable KBCU Row4 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led4_duty0_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED4, KBCU_LED4_DUTY0_H); +} + +/** + * @brief Indicate if Row4 PWM0 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led4_duty0_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED4, KBCU_LED4_DUTY0_H) == (KBCU_LED4_DUTY0_H)); +} + +/** + * @brief Set KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row4. + * @param KBCUx KBCU Instance + * @param duty2 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led4_duty2(KBCU_TypeDef *KBCUx, uint32_t duty2) +{ + MODIFY_REG(KBCUx->LED4, KBCU_LED4_DUTY2, duty2 << KBCU_LED4_DUTY2_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row4. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led4_duty2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED4, KBCU_LED4_DUTY2) >> KBCU_LED4_DUTY2_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row4. + * @param KBCUx KBCU Instance + * @param duty1 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led4_duty1(KBCU_TypeDef *KBCUx, uint32_t duty1) +{ + MODIFY_REG(KBCUx->LED4, KBCU_LED4_DUTY1, duty1 << KBCU_LED4_DUTY1_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row4. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led4_duty1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED4, KBCU_LED4_DUTY1) >> KBCU_LED4_DUTY1_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row4. + * @param KBCUx KBCU Instance + * @param duty0 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led4_duty0(KBCU_TypeDef *KBCUx, uint32_t duty0) +{ + MODIFY_REG(KBCUx->LED4, KBCU_LED4_DUTY0, duty0 << KBCU_LED4_DUTY0_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row4. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led4_duty0(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED4, KBCU_LED4_DUTY0) >> KBCU_LED4_DUTY0_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group22 LED5 + * @{ + */ +/** + * @brief Set KBCU LED5 + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led5(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->LED5, Reg_Value); +} + +/** + * @brief Get KBCU LED5 + * @note None. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_led5(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->LED5)); +} + +/** + * @brief Set KBCU the PWM mask in one column in Row5 + * @note None + * @param KBCUx KBCU Instance + * @param mask + * @arg Max Value 0x1F + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led5_mask(KBCU_TypeDef *KBCUx, uint32_t mask) +{ + MODIFY_REG(KBCUx->LED5, KBCU_LED5_MASK, mask << KBCU_LED5_MASK_POSS); +} + +/** + * @brief Get KBCU the PWM mask in one column in Row5 + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x1F + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led5_mask(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED5, KBCU_LED5_MASK) >> KBCU_LED5_MASK_POSS); +} + +/** + * @brief Enable KBCU Row5 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led5_duty2_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED5, KBCU_LED5_DUTY2_H); +} + +/** + * @brief Disable KBCU Row5 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led5_duty2_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED5, KBCU_LED5_DUTY2_H); +} + +/** + * @brief Indicate if Row5 PWM2 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led5_duty2_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED5, KBCU_LED5_DUTY2_H) == (KBCU_LED5_DUTY2_H)); +} + +/** + * @brief Enable KBCU Row5 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led5_duty1_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED5, KBCU_LED5_DUTY1_H); +} + +/** + * @brief Disable KBCU Row5 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led5_duty1_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED5, KBCU_LED5_DUTY1_H); +} + +/** + * @brief Indicate if Row5 PWM1 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led5_duty1_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED5, KBCU_LED5_DUTY1_H) == (KBCU_LED5_DUTY1_H)); +} + +/** + * @brief Enable KBCU Row5 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led5_duty0_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED5, KBCU_LED5_DUTY0_H); +} + +/** + * @brief Disable KBCU Row5 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led5_duty0_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED5, KBCU_LED5_DUTY0_H); +} + +/** + * @brief Indicate if Row5 PWM0 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led5_duty0_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED5, KBCU_LED5_DUTY0_H) == (KBCU_LED5_DUTY0_H)); +} + +/** + * @brief Set KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row5. + * @param KBCUx KBCU Instance + * @param duty2 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led5_duty2(KBCU_TypeDef *KBCUx, uint32_t duty2) +{ + MODIFY_REG(KBCUx->LED5, KBCU_LED5_DUTY2, duty2 << KBCU_LED5_DUTY2_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row5. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led5_duty2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED5, KBCU_LED5_DUTY2) >> KBCU_LED5_DUTY2_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row5. + * @param KBCUx KBCU Instance + * @param duty1 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led5_duty1(KBCU_TypeDef *KBCUx, uint32_t duty1) +{ + MODIFY_REG(KBCUx->LED5, KBCU_LED5_DUTY1, duty1 << KBCU_LED5_DUTY1_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row5. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led5_duty1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED5, KBCU_LED5_DUTY1) >> KBCU_LED5_DUTY1_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row5. + * @param KBCUx KBCU Instance + * @param duty0 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led5_duty0(KBCU_TypeDef *KBCUx, uint32_t duty0) +{ + MODIFY_REG(KBCUx->LED5, KBCU_LED5_DUTY0, duty0 << KBCU_LED5_DUTY0_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row5. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led5_duty0(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED5, KBCU_LED5_DUTY0) >> KBCU_LED5_DUTY0_POSS); +} +/** + * @} + */ + +/** @defgroup MD_KBCU_Public_Functions_Group23 LED6 + * @{ + */ +/** + * @brief Set KBCU LED6 + * @param KBCUx KBCU Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led6(KBCU_TypeDef *KBCUx, uint32_t Reg_Value) +{ + WRITE_REG(KBCUx->LED6, Reg_Value); +} + +/** + * @brief Get KBCU LED6 + * @note None. + * @param KBCUx KBCU Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_kbcu_get_led6(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_REG(KBCUx->LED6)); +} + +/** + * @brief Set KBCU the PWM mask in one column in Row6 + * @note None + * @param KBCUx KBCU Instance + * @param mask + * @arg Max Value 0x1F + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led6_mask(KBCU_TypeDef *KBCUx, uint32_t mask) +{ + MODIFY_REG(KBCUx->LED6, KBCU_LED6_MASK, mask << KBCU_LED6_MASK_POSS); +} + +/** + * @brief Get KBCU the PWM mask in one column in Row6 + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x1F + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led6_mask(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED6, KBCU_LED6_MASK) >> KBCU_LED6_MASK_POSS); +} + +/** + * @brief Enable KBCU Row6 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led6_duty2_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED6, KBCU_LED6_DUTY2_H); +} + +/** + * @brief Disable KBCU Row6 PWM2 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led6_duty2_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED6, KBCU_LED6_DUTY2_H); +} + +/** + * @brief Indicate if Row6 PWM2 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led6_duty2_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED6, KBCU_LED6_DUTY2_H) == (KBCU_LED6_DUTY2_H)); +} + +/** + * @brief Enable KBCU Row6 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led6_duty1_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED6, KBCU_LED6_DUTY1_H); +} + +/** + * @brief Disable KBCU Row6 PWM1 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led6_duty1_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED6, KBCU_LED6_DUTY1_H); +} + +/** + * @brief Indicate if Row6 PWM1 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led6_duty1_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED6, KBCU_LED6_DUTY1_H) == (KBCU_LED6_DUTY1_H)); +} + +/** + * @brief Enable KBCU Row6 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_enable_led6_duty0_h(KBCU_TypeDef *KBCUx) +{ + SET_BIT(KBCUx->LED6, KBCU_LED6_DUTY0_H); +} + +/** + * @brief Disable KBCU Row6 PWM0 Duty-Cycle 100% + * @note None + * @param KBCUx KBCU Instance + * @retval None + */ +__STATIC_INLINE void md_kbcu_disable_led6_duty0_h(KBCU_TypeDef *KBCUx) +{ + CLEAR_BIT(KBCUx->LED6, KBCU_LED6_DUTY0_H); +} + +/** + * @brief Indicate if Row6 PWM0 Duty-Cycle 100% function is enabled + * @param KBCUx KBCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_kbcu_is_enabled_led6_duty0_h(KBCU_TypeDef *KBCUx) +{ + return (READ_BIT(KBCUx->LED6, KBCU_LED6_DUTY0_H) == (KBCU_LED6_DUTY0_H)); +} + +/** + * @brief Set KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row6. + * @param KBCUx KBCU Instance + * @param duty2 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led6_duty2(KBCU_TypeDef *KBCUx, uint32_t duty2) +{ + MODIFY_REG(KBCUx->LED6, KBCU_LED6_DUTY2, duty2 << KBCU_LED6_DUTY2_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM2 determined by the value of the DUTY2 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row6. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led6_duty2(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED6, KBCU_LED6_DUTY2) >> KBCU_LED6_DUTY2_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row6. + * @param KBCUx KBCU Instance + * @param duty1 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led6_duty1(KBCU_TypeDef *KBCUx, uint32_t duty1) +{ + MODIFY_REG(KBCUx->LED6, KBCU_LED6_DUTY1, duty1 << KBCU_LED6_DUTY1_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM1 determined by the value of the DUTY1 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row6. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led6_duty1(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED6, KBCU_LED6_DUTY1) >> KBCU_LED6_DUTY1_POSS); +} + +/** + * @brief Set KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row6. + * @param KBCUx KBCU Instance + * @param duty0 + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_kbcu_set_led6_duty0(KBCU_TypeDef *KBCUx, uint32_t duty0) +{ + MODIFY_REG(KBCUx->LED6, KBCU_LED6_DUTY0, duty0 << KBCU_LED6_DUTY0_POSS); +} + +/** + * @brief Get KBCU a duty cycle of PWM0 determined by the value of the DUTY0 + * @note It is a PWM signal with a frequency determined by ARVALUE in Row6. + * @param KBCUx KBCU Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_kbcu_get_led6_duty0(KBCU_TypeDef *KBCUx) +{ + return (uint32_t)(READ_BIT(KBCUx->LED6, KBCU_LED6_DUTY0) >> KBCU_LED6_DUTY0_POSS); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c b/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c new file mode 100644 index 00000000000..3ec98008142 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c @@ -0,0 +1,408 @@ +/********************************************************************************** + * + * @file md_rcu.c + * @brief md_rcu C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 24 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "system_fs026.h" +#include "md_rcu.h" +#include "md_fc.h" +#include "md_tick.h" +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup RCU RCU + * @brief RCU micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +static uint32_t TICKms; +static uint32_t TICK100us; +static uint32_t TICK10us; +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +#define TICK_CLOCKSOURCE 4000000 + +/** @defgroup MD_RCU_Private_Macros RCU Private Macros + * @{ + */ + +/** + * @} MD_RCU_Private_Macros + */ + +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_RCU_Public_Functions RCU Public Functions + * @{ + */ +void md_tick_init_rcu(void) +{ + TICKms = TICK_CLOCKSOURCE / 1000; + TICK100us = TICK_CLOCKSOURCE / 10000; + TICK10us = TICK_CLOCKSOURCE / 100000; + + md_tick_set_rvr_reload(TICK, ((1 << 24) - 1)); /* Maximun ReLoad */ + md_tick_set_cvr_current(TICK, 0); /* Reset CVR */ + md_tick_set_csr_clksrc(TICK, MD_SYSTICK_CLKSRC_HCLK); /* MCU Clock */ + md_tick_enable_csr_enable(TICK); /* Counter Enable */ +} + +void md_tick_waitms_rcu(uint8_t Unit, uint16_t msCnt) +{ + uint32_t mstime; + + mstime = (1 << 24) - (Unit * TICKms); + + while (msCnt--) + { + md_tick_set_cvr_current(TICK, ((1 << 24) - 1)); /* Reset CVR */ + + while (md_tick_get_cvr_current(TICK) > mstime); + } +} + +void md_tick_wait100us_rcu(uint16_t Unit, uint16_t usCnt) +{ + uint32_t ustime; + + ustime = (1 << 24) - (Unit * TICK100us); + + while (usCnt--) + { + md_tick_set_cvr_current(TICK, ((1 << 24) - 1)); /* Reset CVR */ + + while (md_tick_get_cvr_current(TICK) > ustime); + } +} + +void md_tick_wait10us_rcu(uint16_t Unit, uint16_t usCnt) +{ + uint32_t ustime; + + ustime = (1 << 24) - (Unit * TICK10us); + + while (usCnt--) + { + md_tick_set_cvr_current(TICK, ((1 << 24) - 1)); /* Reset CVR */ + + while (md_tick_get_cvr_current(TICK) > ustime); + } +} + +void md_rcu_check_hosc_ready(void) +{ + md_tick_init_rcu(); + + md_tick_waitms_rcu(1, 1); + + while (md_rcu_is_active_flag_hosc_ready(RCU) == MD_RCU_HOSCRDY_NOT_READY) + { + md_rcu_disable_hosc(RCU); + + md_tick_waitms_rcu(1, 1); + + md_rcu_enable_hosc(RCU); + + md_tick_waitms_rcu(1, 1); + + } +} + +/** + * @} MD_RCU_Check_Hosc_Ready + */ + +/** @addtogroup MD_RCU_Init + * @{ + */ +void md_rcu_sys_init(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct) +{ + uint32_t PLL0_Frequency; + uint32_t PLL0_Ref_Frequency; + double fration; + + md_fc_set_read_latency(FC, MD_FC_WAIT_MORE_THAN_72Mhz); + + if (RCU_InitStruct->HS_Clock & RCU_CON_PLL0ON) + md_rcu_enable_pll0(rcu); + else + md_rcu_disable_pll0(rcu); + + if (RCU_InitStruct->HS_Clock & RCU_CON_HRC48ON) + md_rcu_enable_hrc48(rcu); + else + md_rcu_disable_hrc48(rcu); + + if (RCU_InitStruct->HS_Clock & RCU_CON_HOSCON) + md_rcu_enable_hosc(rcu); + else + md_rcu_disable_hosc(rcu); + + if (RCU_InitStruct->HS_Clock & RCU_CON_HRCON) + md_rcu_enable_hrc(rcu); + else + md_rcu_disable_hrc(rcu); + + if (RCU_InitStruct->LS_Clock & RCU_LCON_LOSCON) + md_rcu_enable_losc(rcu); + else + md_rcu_disable_losc(rcu); + + if (RCU_InitStruct->LS_Clock & RCU_LCON_LRCON) + md_rcu_enable_lrc(rcu); + else + md_rcu_disable_lrc(rcu); + + //make sure HOSC CLK Ready + if ((RCU_InitStruct->HS_Clock & RCU_CON_HOSCON)) + md_rcu_check_hosc_ready(); + + while ( + ((RCU->CON & RCU_CON_PLL0ON) && (md_rcu_is_active_flag_pll0_ready(rcu) == MD_RCU_PLL0RDY_NOT_READY)) + || ((RCU->CON & RCU_CON_HRC48ON) && (md_rcu_is_active_flag_hrc48_ready(rcu) == MD_RCU_HRC48RDY_NOT_READY)) + || ((RCU->CON & RCU_CON_HOSCON) && (md_rcu_is_active_flag_hosc_ready(rcu) == MD_RCU_HOSCRDY_NOT_READY)) + || ((RCU->CON & RCU_CON_HRCON) && (md_rcu_is_active_flag_hrc_ready(rcu) == MD_RCU_HRCRDY_NOT_READY)) + || ((RCU->LCON & RCU_LCON_LRCON) && (md_rcu_is_active_flag_lrc_ready(rcu) == MD_RCU_LRCRDY_NOT_READY)) + || ((RCU->LCON & RCU_LCON_LOSCON) && (md_rcu_is_active_flag_losc_ready(rcu) == MD_RCU_LOSCRDY_NOT_READY)) + ); + + md_rcu_set_mco_div(rcu, RCU_InitStruct->Mpre); + md_rcu_set_mco_source(rcu, RCU_InitStruct->Msw); + md_rcu_set_pclk_div(rcu, RCU_InitStruct->Ppre); + md_rcu_set_hclk_div(rcu, RCU_InitStruct->Hpre); + md_rcu_set_system_clock_source(rcu, RCU_InitStruct->Sw); + + switch ((RCU_InitStruct->PllSrc)) + { + case MD_RCU_PLLSRC_HRC : + PLL0_Ref_Frequency = (uint32_t)(__HRC); + break; + + case MD_RCU_PLLSRC_HOSC : + PLL0_Ref_Frequency = (uint32_t)(__HOSC); + break; + + case MD_RCU_PLLSRC_HRC48 : + PLL0_Ref_Frequency = (uint32_t)(__HRC48); + break; + + default : + PLL0_Ref_Frequency = (uint32_t)(__HRC); + break; + } + + PLL0_Ref_Frequency /= (md_rcu_get_pll_prediv(rcu) + 1); + fration = (double)md_rcu_get_pll0_fn(rcu) + ((double)md_rcu_get_pll0_fk(rcu) / (1 << 19)); + PLL0_Frequency = (uint32_t)(PLL0_Ref_Frequency * fration / (1 << (md_rcu_get_pll0_fm(rcu) + 3))); + + /* System Frequency */ + switch (md_rcu_get_current_system_clock(rcu)) /* System clock switch(SYSCLK) */ + { + case MD_RCU_SWS_SYSCLK_HRC: /*================= HRC selected as system clock*/ + SystemCoreClock = (uint32_t)(__HRC); + break; + + case MD_RCU_SWS_SYSCLK_HOSC: /*================= HOSC selected as system clock*/ + SystemCoreClock = (uint32_t)(__HOSC); + break; + + case MD_RCU_SWS_SYSCLK_PLL0: /*================= PLL selected as system clock*/ + SystemCoreClock = PLL0_Frequency; + break; + + case MD_RCU_SWS_SYSCLK_HRC48: /*================= HRC48 selected as system clock*/ + SystemCoreClock = (uint32_t)(__HRC48); + break; + + default: + SystemCoreClock = (uint32_t)(__HRC); + break; + } + + /* Core Frequency */ + SystemFrequency_SysClk = SystemCoreClock; + + /* AHB Frequency */ + if ((md_rcu_get_hclk_div(rcu) >= 12)) + SystemFrequency_AHBClk = SystemCoreClock >> ((md_rcu_get_hclk_div(rcu) & 0x07) + 2); + else if ((md_rcu_get_hclk_div(rcu)) >= 8) + SystemFrequency_AHBClk = SystemCoreClock >> ((md_rcu_get_hclk_div(rcu) & 0x07) + 1); + else + SystemFrequency_AHBClk = SystemCoreClock; + + /* APB Frequency */ + if (md_rcu_get_pclk_div(rcu)) + SystemFrequency_APBClk = SystemFrequency_AHBClk >> ((md_rcu_get_pclk_div(rcu) & 0x03) + 1); + else + SystemFrequency_APBClk = SystemFrequency_AHBClk; + + if (RCU_InitStruct->HS_Clock & RCU_CON_CSSON) + md_rcu_enable_hosc_css(rcu); + else + md_rcu_disable_hosc_css(rcu); + + md_rcu_set_current_system_frequency(RCU, (SystemFrequency_SysClk / 1000000)); + + if (SystemFrequency_AHBClk / 1000000 > 72) + md_fc_set_read_latency(FC, MD_FC_WAIT_MORE_THAN_72Mhz); + else if (SystemFrequency_AHBClk / 1000000 > 48) + md_fc_set_read_latency(FC, MD_FC_WAIT_BETWEEN_48MHz_AND_72Mhz); + else if (SystemFrequency_AHBClk / 1000000 > 24) + md_fc_set_read_latency(FC, MD_FC_WAIT_BETWEEN_24MHz_AND_48Mhz); + else + md_fc_set_read_latency(FC, MD_FC_WAIT_LESS_THAN_24MHz); +} + +/** + * @} MD_RCU_Init + */ + +/** @addtogroup MD_RCU_Pll0_Init + * @{ + */ +void md_rcu_pll0_init(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct) +{ + uint32_t fpllin; + uint32_t fvco; + + md_rcu_disable_pll0(rcu); + + while (md_rcu_is_active_flag_pll0_ready(rcu) == MD_RCU_PLL0RDY_READY); + + md_rcu_set_pll_source(rcu, RCU_InitStruct->PllSrc); + + switch ((RCU_InitStruct->PllSrc)) + { + case MD_RCU_PLLSRC_HRC : + fpllin = (uint32_t)(__HRC); + break; + + case MD_RCU_PLLSRC_HOSC : + fpllin = (uint32_t)(__HOSC); + break; + + case MD_RCU_PLLSRC_HRC48 : + fpllin = (uint32_t)(__HRC48); + break; + + default : + fpllin = (uint32_t)(__HRC); + break; + } + + md_rcu_set_pll_prediv(rcu, ((fpllin / __PLL0_CLKREF) - 1)); + + if (RCU_InitStruct->Pllclk <= 72000000 && RCU_InitStruct->Pllclk >= 4000000) + { + if ((RCU_InitStruct->Pllclk / 1000000) >= 32) + md_rcu_set_pll0_fm(rcu, MD_RCU_FM_PLL0_DIV_8); + else if ((RCU_InitStruct->Pllclk / 1000000) >= 16) + md_rcu_set_pll0_fm(rcu, MD_RCU_FM_PLL0_DIV_16); + else if ((RCU_InitStruct->Pllclk / 1000000) >= 8) + md_rcu_set_pll0_fm(rcu, MD_RCU_FM_PLL0_DIV_32); + else + md_rcu_set_pll0_fm(rcu, MD_RCU_FM_PLL0_DIV_64); + + fvco = RCU_InitStruct->Pllclk * (1 << (md_rcu_get_pll0_fm(rcu) + 3)); + + md_rcu_set_pll0_fn(rcu, fvco / __PLL0_CLKREF); + + md_rcu_set_pll0_fk(rcu, (((long long)(fvco) << 19) / __PLL0_CLKREF) & 0x7FFFF); + + md_rcu_enable_pll0(rcu); + + while (md_rcu_is_active_flag_pll0_ready(rcu) == 0); + } +} + +/** + * @} MD_RCU_Pll0_Init + */ + +/** @addtogroup MD_RCU HRC/HRC48 Trim + * @{ + */ + +void md_rcu_hrc_software_trim(RCU_TypeDef *rcu, uint8_t trim_value) +{ + md_rcu_set_hrctrim_source(rcu, MD_RCU_HRCSEL_HRCTRIM); + md_rcu_set_hrctrim(rcu, trim_value); +} + +void md_rcu_hrc_disable_software_trim(RCU_TypeDef *rcu) +{ + md_rcu_set_hrctrim_source(rcu, MD_RCU_HRCSEL_OPTIONBYTE); +} + +void md_rcu_hrc48_software_trim(RCU_TypeDef *rcu, uint16_t trim_value) +{ + md_rcu_set_hrc48trim_source(rcu, MD_RCU_HRC48SEL_HRC48TRIM); + md_rcu_set_hrc48trim(rcu, trim_value); + md_rcu_trigger_hrc48trim_update(rcu); +} + +void md_rcu_hrc48_disable_software_trim(RCU_TypeDef *rcu) +{ + md_rcu_set_hrc48trim_source(rcu, MD_RCU_HRC48SEL_OPTIONBYTE); +} + +uint16_t md_rcu_get_hrc_option_trim_value(RCU_TypeDef *rcu) +{ + md_rcu_set_hrctrim_source(rcu, MD_RCU_HRCSEL_OPTIONBYTE); + return md_rcu_get_hrctrim(rcu); +} + +uint16_t md_rcu_get_hrc48_option_trim_value(RCU_TypeDef *rcu) +{ + md_rcu_set_hrc48trim_source(rcu, MD_RCU_HRC48SEL_OPTIONBYTE); + return md_rcu_get_hrc48trim(rcu); +} +/** + * @} + */ + +/** + * @} MD_RCU_Public_Functions + */ + +/** + * @} RCU + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.h b/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.h new file mode 100644 index 00000000000..aba765b65c7 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.h @@ -0,0 +1,5579 @@ +/********************************************************************************** + * + * @file md_rcu.h + * @brief header file of md_rcu.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 24 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_RCU_H__ +#define __MD_RCU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + + +/** @defgroup MD_RCU RCU + * @brief RCU micro driver + * @{ + */ + +/** @defgroup MD_RCU_Pubulic_Types RCU Pubulic Types + * @{ + */ +/** + * @brief MD_RCU_Public_Types RCU Init Type + */ + +typedef struct +{ + uint32_t Mpre; /*! MCO clock prescaler */ + uint32_t Msw; /*! MCO clock output */ + uint32_t PllSrc; /*! PLL clock source */ + uint32_t Pllclk; /*! PLL clock */ + uint32_t Ppre; /*! APB clock prescaler */ + uint32_t Hpre; /*! AHB clock prescaler */ + uint32_t Sw; /*! system clock */ + uint32_t HS_Clock; /*! high spped clock enable */ + uint32_t LS_Clock; /*! low spped clock enable */ +} md_rcu_init_typedef; + +/** + * @} + */ +/** @defgroup MD_RCU_Public_Macros RCU Public Macros + * @{ + */ + +#ifndef __HOSC +#define __HOSC ( 8000000UL) +#endif +#define __HRC ( 4000000UL) +#define __LOSC ( 32768UL) +#define __LRC ( 32000UL) +#define __PLL0_CLKREF ( 4000000UL) +#define __HRC48 (48000000UL) + +/** + * @brief MD_RCU_LOSCRDY_FLAG LOSC clock ready flag + */ +#define MD_RCU_LOSCRDY_NOT_READY (0x00000000UL) /** @brief LOSC oscillator not ready */ +#define MD_RCU_LOSCRDY_READY (0x00000001UL) /** @brief LOSC oscillator ready */ + +/** + * @brief MD_RCU_LRCRDY_FLAG LRC clock ready flag + */ +#define MD_RCU_LRCRDY_NOT_READY (0x00000000UL) /** @brief LRC oscillator not ready */ +#define MD_RCU_LRCRDY_READY (0x00000001UL) /** @brief LRC oscillator ready */ + +/** + * @brief MD_RCU_PLL0_FLAG PLL0 clock ready flag + */ +#define MD_RCU_PLL0RDY_NOT_READY (0x00000000UL) /** @brief PLL0 not ready */ +#define MD_RCU_PLL0RDY_READY (0x00000001UL) /** @brief PLL0 ready */ + +/** + * @brief MD_RCU_HRC48RDY_FLAG HRC48 clock ready flag + */ +#define MD_RCU_HRC48RDY_NOT_READY (0x00000000UL) /** @brief HRC48 oscillator not ready */ +#define MD_RCU_HRC48RDY_READY (0x00000001UL) /** @brief HRC48 oscillator ready */ + +/** + * @brief MD_RCU_HOSCRDY_FLAG HOSC clock ready flag + */ +#define MD_RCU_HOSCRDY_NOT_READY (0x00000000UL) /** @brief HOSC oscillator not ready */ +#define MD_RCU_HOSCRDY_READY (0x00000001UL) /** @brief HOSC oscillator ready */ + +/** + * @brief MD_RCU_HRCRDY_FLAG HRC clock ready flag + */ +#define MD_RCU_HRCRDY_NOT_READY (0x00000000UL) /** @brief HRC oscillator not ready */ +#define MD_RCU_HRCRDY_READY (0x00000001UL) /** @brief HRC oscillator ready */ + +/** + * @brief MD_RCU_MCO_DIV Microcontroller clock output select + */ +#define MD_RCU_MPRE_MCO_DIV1 (0x00000000UL) /** @brief MCO DIV = 1 */ +#define MD_RCU_MPRE_MCO_DIV2 (0x00000001UL) /** @brief MCO DIV = 2 */ +#define MD_RCU_MPRE_MCO_DIV4 (0x00000002UL) /** @brief MCO DIV = 4 */ +#define MD_RCU_MPRE_MCO_DIV8 (0x00000003UL) /** @brief MCO DIV = 8 */ +#define MD_RCU_MPRE_MCO_DIV16 (0x00000004UL) /** @brief MCO DIV = 16 */ +#define MD_RCU_MPRE_MCO_DIV32 (0x00000005UL) /** @brief MCO DIV = 32 */ +#define MD_RCU_MPRE_MCO_DIV64 (0x00000006UL) /** @brief MCO DIV = 64 */ +#define MD_RCU_MPRE_MCO_DIV128 (0x00000007UL) /** @brief MCO DIV = 128*/ + +/** + * @brief MD_RCU_MCO_OUTPUT Microcontroller clock output select + */ +#define MD_RCU_MSW_MCO_DISABLE (0x00000000UL) /** @brief MCO output disabled, no clock on MCO */ +#define MD_RCU_MSW_MCO_LRC (0x00000001UL) /** @brief Internal low speed (LRC) oscillator clock selected */ +#define MD_RCU_MSW_MCO_LOSC (0x00000002UL) /** @brief External low speed (LOSC) oscillator clock selected */ +#define MD_RCU_MSW_MCO_HRC (0x00000003UL) /** @brief Internal high speed (HRC) oscillator clock selected */ +#define MD_RCU_MSW_MCO_HOSC (0x00000004UL) /** @brief External high speed (HOSC) oscillator clock selected */ +#define MD_RCU_MSW_MCO_HRC48 (0x00000005UL) /** @brief HRC48 clock selected */ +#define MD_RCU_MSW_MCO_PLL0 (0x00000006UL) /** @brief PLL0 clock selected */ +#define MD_RCU_MSW_MCO_SYSCLK (0x00000008UL) /** @brief System clock selected(SYSCLK) */ +#define MD_RCU_MSW_MCO_HCLK (0x00000009UL) /** @brief AHB clock selected(HCLK) */ +#define MD_RCU_MSW_MCO_PCLK (0x0000000AUL) /** @brief APB clock selected(PCLK) */ + +/** + * @brief MD_RCU_PLLSRC PLL reference clock source + */ +#define MD_RCU_PLLSRC_HRC (0x00000000UL) /** @brief HRC/PREDIV selected as PLL reference clock */ +#define MD_RCU_PLLSRC_HOSC (0x00000001UL) /** @brief HOSC/PREDIV selected as PLL reference clock */ +#define MD_RCU_PLLSRC_HRC48 (0x00000002UL) /** @brief HRC48/PREDIV selected as PLL reference clock */ + +/** + * @brief MD_RCU_PLL_CLK PLL reference clock source + */ +#define MD_RCU_PLLCLK_PASS 0 +#define MD_RCU_PLLCLK_4M 4000000 +#define MD_RCU_PLLCLK_8M 8000000 +#define MD_RCU_PLLCLK_12M 12000000 +#define MD_RCU_PLLCLK_16M 16000000 +#define MD_RCU_PLLCLK_24M 24000000 +#define MD_RCU_PLLCLK_32M 32000000 +#define MD_RCU_PLLCLK_36M 36000000 +#define MD_RCU_PLLCLK_40M 40000000 +#define MD_RCU_PLLCLK_48M 48000000 +#define MD_RCU_PLLCLK_64M 64000000 +#define MD_RCU_PLLCLK_72M 72000000 + +/** + * @brief MD_RCU_PLL_DIV Microcontroller clock output select + */ +#define MD_RCU_PREDIV_PLL_DIV1 (0x00000000UL) /** @brief PLL DIV = 1 */ +#define MD_RCU_PREDIV_PLL_DIV2 (0x00000001UL) /** @brief PLL DIV = 2 */ +#define MD_RCU_PREDIV_PLL_DIV3 (0x00000002UL) /** @brief PLL DIV = 3 */ +#define MD_RCU_PREDIV_PLL_DIV4 (0x00000003UL) /** @brief PLL DIV = 4 */ +#define MD_RCU_PREDIV_PLL_DIV5 (0x00000004UL) /** @brief PLL DIV = 5 */ +#define MD_RCU_PREDIV_PLL_DIV6 (0x00000005UL) /** @brief PLL DIV = 6 */ +#define MD_RCU_PREDIV_PLL_DIV7 (0x00000006UL) /** @brief PLL DIV = 7 */ +#define MD_RCU_PREDIV_PLL_DIV8 (0x00000007UL) /** @brief PLL DIV = 8 */ +#define MD_RCU_PREDIV_PLL_DIV9 (0x00000008UL) /** @brief PLL DIV = 9 */ +#define MD_RCU_PREDIV_PLL_DIV10 (0x00000009UL) /** @brief PLL DIV = 10*/ +#define MD_RCU_PREDIV_PLL_DIV11 (0x0000000AUL) /** @brief PLL DIV = 11*/ +#define MD_RCU_PREDIV_PLL_DIV12 (0x0000000BUL) /** @brief PLL DIV = 12*/ +#define MD_RCU_PREDIV_PLL_DIV13 (0x0000000CUL) /** @brief PLL DIV = 13*/ +#define MD_RCU_PREDIV_PLL_DIV14 (0x0000000DUL) /** @brief PLL DIV = 14*/ +#define MD_RCU_PREDIV_PLL_DIV15 (0x0000000EUL) /** @brief PLL DIV = 15*/ +#define MD_RCU_PREDIV_PLL_DIV16 (0x0000000FUL) /** @brief PLL DIV = 16*/ + +/** + * @brief MD_RCU_APB_CLK_DIV APB clock prescaler(PCLK) + */ +#define MD_RCU_PPRE_HCLK_DIV_1 (0x00000000UL) /** @brief HCLK not divided */ +#define MD_RCU_PPRE_HCLK_DIV_2 (0x00000004UL) /** @brief HCLK divided by 2 */ +#define MD_RCU_PPRE_HCLK_DIV_4 (0x00000005UL) /** @brief HCLK divided by 4 */ +#define MD_RCU_PPRE_HCLK_DIV_8 (0x00000006UL) /** @brief HCLK divided by 8 */ +#define MD_RCU_PPRE_HCLK_DIV_16 (0x00000007UL) /** @brief HCLK divided by 16 */ + + +/** + * @brief MD_RCU_AHB_CLK_DIV AHB clock prescaler(HCLK) + */ +#define MD_RCU_HPRE_SYSCLK_DIV_1 (0x00000000UL) /** @brief SYSCLK not divided */ +#define MD_RCU_HPRE_SYSCLK_DIV_2 (0x00000008UL) /** @brief SYSCLK divided by 2 */ +#define MD_RCU_HPRE_SYSCLK_DIV_4 (0x00000009UL) /** @brief SYSCLK divided by 4 */ +#define MD_RCU_HPRE_SYSCLK_DIV_8 (0x0000000AUL) /** @brief SYSCLK divided by 8 */ +#define MD_RCU_HPRE_SYSCLK_DIV_16 (0x0000000BUL) /** @brief SYSCLK divided by 16 */ +#define MD_RCU_HPRE_SYSCLK_DIV_64 (0x0000000CUL) /** @brief SYSCLK divided by 64 */ +#define MD_RCU_HPRE_SYSCLK_DIV_128 (0x0000000DUL) /** @brief SYSCLK divided by 128 */ +#define MD_RCU_HPRE_SYSCLK_DIV_256 (0x0000000EUL) /** @brief SYSCLK divided by 256 */ +#define MD_RCU_HPRE_SYSCLK_DIV_512 (0x0000000FUL) /** @brief SYSCLK divided by 512 */ + +/** + * @brief MD_RCU_SYS_CLK_SWS System clock switch(SYSCLK) + */ +#define MD_RCU_SWS_SYSCLK_HRC (0x00000000UL) /** @brief HRC selected as system clock */ +#define MD_RCU_SWS_SYSCLK_HOSC (0x00000001UL) /** @brief HOSC selected as system clock */ +#define MD_RCU_SWS_SYSCLK_PLL0 (0x00000002UL) /** @brief PLL0 selected as system clock */ +#define MD_RCU_SWS_SYSCLK_HRC48 (0x00000003UL) /** @brief HRC48 selected as system clock */ + +/** + * @brief MD_RCU_SYS_CLK_SW System clock switch(SYSCLK) + */ +#define MD_RCU_SW_SYSCLK_HRC (0x00000000UL) /** @brief HRC selected as system clock */ +#define MD_RCU_SW_SYSCLK_HOSC (0x00000001UL) /** @brief HOSC selected as system clock */ +#define MD_RCU_SW_SYSCLK_PLL0 (0x00000002UL) /** @brief PLL0 selected as system clock */ +#define MD_RCU_SW_SYSCLK_HRC48 (0x00000003UL) /** @brief HRC48 selected as system clock */ + +/** + * @brief MD_RCU_PLL0_DIV + */ +#define MD_RCU_FM_PLL0_DIV_8 (0x00000000UL) +#define MD_RCU_FM_PLL0_DIV_16 (0x00000001UL) +#define MD_RCU_FM_PLL0_DIV_32 (0x00000002UL) +#define MD_RCU_FM_PLL0_DIV_64 (0x00000003UL) + +/** + * @brief MD_RCU_USBCLK USB Clock Source Select + */ +#define MD_RCU_USBSW_USBCLK_HRC48CLK (0x00000000UL) +#define MD_RCU_USBSW_USBCLK_PLL0CLK (0x00000002UL) + +/** + * @brief MD_RCU_I2SCKSL I2S Clock Source Select + */ +#define MD_RCU_I2SSW_I2SCLK_HRC48CLK (0x00000000UL) +#define MD_RCU_I2SSW_I2SCLK_HOSCCLK (0x00000001UL) +#define MD_RCU_I2SSW_I2SCLK_PLL0CLK (0x00000002UL) + +/** + * @brief MD_RCU_SRCSEL Calibration Clock Source Select + */ +#define MD_RCU_SRCSEL_HRC_4MHZ (0x00000000UL) +#define MD_RCU_SRCSEL_HRC_48MHZ (0x00000001UL) + +/** + * @brief MD_RCU_HRC48SEL HRC48 calibration value selection + */ +#define MD_RCU_HRC48SEL_OPTIONBYTE (0x00000000UL) +#define MD_RCU_HRC48SEL_HRC48TRIM (0x00000001UL) + +/** + * @brief MD_RCU_HRCSEL HRCSEL calibration value selection + */ +#define MD_RCU_HRCSEL_OPTIONBYTE (0x00000000UL) +#define MD_RCU_HRCSEL_HRCTRIM (0x00000001UL) + +/** + * @brief MD_RCU_LRCSEL LRCSEL calibration value selection + */ +#define MD_RCU_LRCSEL_OPTIONBYTE (0x00000000UL) +#define MD_RCU_LRCSEL_LRCTRIM (0x00000001UL) + +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions RCU Public Functions + * @{ + */ + +/** @defgroup MD_RCU_Public_Functions_Group2 CON + * @{ + */ +/** + * @brief Set RCU_CON Register + * @param rcu RCU Instance + * @param con + * @retval None + */ +__STATIC_INLINE void md_rcu_set_con(RCU_TypeDef *rcu, uint32_t con) +{ + WRITE_REG(rcu->CON, con); +} + +/** + * @brief Get RCU_CON Register + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rcu_get_con(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->CON)); +} + +/** + * @brief Clock security system enable(CSS) + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_hosc_css(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_CSSON); +} + +/** + * @brief Clock security system disable(CSS) + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_hosc_css(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_CSSON); +} + +/** + * @brief Get Clock security system (CSS) + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Hosc css enable + * @arg 0x0 : Hosc css disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_hosc_css(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_CSSON) == (RCU_CON_CSSON)); +} + +/** + * @brief Get PLL0 clock ready flag + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_PLL0RDY_NOT_READY + * @arg @ref MD_RCU_PLL0RDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_pll0_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_PLL0RDY) == (RCU_CON_PLL0RDY)); +} + +/** + * @brief PLL0 enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_pll0(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_PLL0ON); +} + +/** + * @brief PLL0 disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_pll0(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_PLL0ON); +} + +/** + * @brief Get PLL0 bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : PLL0 enable + * @arg 0x0 : PLL0 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_pll0(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_PLL0ON) == (RCU_CON_PLL0ON)); +} + +/** + * @brief Get HRC48 clock ready flag + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_HRC48RDY_NOT_READY + * @arg @ref MD_RCU_HRC48RDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_hrc48_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HRC48RDY) == (RCU_CON_HRC48RDY)); +} + +/** + * @brief HRC48 enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_hrc48(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_HRC48ON); +} + +/** + * @brief HRC48 disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_hrc48(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_HRC48ON); +} + +/** + * @brief Get HRC48 bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : HRC48 enable + * @arg 0x0 : HRC48 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_hrc48(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HRC48ON) == (RCU_CON_HRC48ON)); +} + +/** + * @brief HOSC bypass mode enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_hosc_bypass(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_HOSCBYP); +} + +/** + * @brief HOSC bypass mode disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_hosc_bypass(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_HOSCBYP); +} + +/** + * @brief Get HOSC bypass mode bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Hosc bypass enable + * @arg 0x0 : Hosc bypass disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_hosc_bypass(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HOSCBYP) == (RCU_CON_HOSCBYP)); +} + +/** + * @brief Get HOSC clock ready flag + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_HOSCRDY_NOT_READY + * @arg @ref MD_RCU_HOSCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_hosc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HOSCRDY) == (RCU_CON_HOSCRDY)); +} + +/** + * @brief HOSC enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_hosc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_HOSCON); +} + +/** + * @brief HOSC disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_hosc(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_HOSCON); +} + +/** + * @brief Get HOSC bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Hosc enable + * @arg 0x0 : Hosc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_hosc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HOSCON) == (RCU_CON_HOSCON)); +} + +/** + * @brief Get HRCRDY clock ready flag + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_HRCRDY_NOT_READY + * @arg @ref MD_RCU_HRCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_hrc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HRCRDY) == (RCU_CON_HRCRDY)); +} + +/** + * @brief HRC enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_hrc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_HRCON); +} + +/** + * @brief HRC disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_hrc(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_HRCON); +} + +/** + * @brief Get HRC bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Hrc enable + * @arg 0x0 : Hrc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_hrc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HRCON) == (RCU_CON_HRCON)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group3 CFG + * @{ + */ +/** + * @brief Set RCU_CFG Register + * @param rcu RCU Instance + * @param cfg + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg(RCU_TypeDef *rcu, uint32_t cfg) +{ + WRITE_REG(rcu->CFG, cfg); +} + +/** + * @brief Get RCU_CFG Register + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rcu_get_cfg(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->CFG)); +} + +/** + * @brief Set MCO clock output prescaler + * @note Output Frequency = MCO/(MPRE+1) + * @param rcu RCU Instance + * @param mpre This parameter can be one of the following values: + * @arg @ref MD_RCU_MPRE_MCO_DIV1 + * @arg @ref MD_RCU_MPRE_MCO_DIV2 + * @arg @ref MD_RCU_MPRE_MCO_DIV4 + * @arg @ref MD_RCU_MPRE_MCO_DIV8 + * @arg @ref MD_RCU_MPRE_MCO_DIV16 + * @arg @ref MD_RCU_MPRE_MCO_DIV32 + * @arg @ref MD_RCU_MPRE_MCO_DIV64 + * @arg @ref MD_RCU_MPRE_MCO_DIV128 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_mco_div(RCU_TypeDef *rcu, uint32_t mpre) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_MPRE, mpre << RCU_CFG_MPRE_POSS); +} + +/** + * @brief Get MCO clock output prescaler + * @note Output Frequency = MCO/(MPRE+1) + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_MPRE_MCO_DIV1 + * @arg @ref MD_RCU_MPRE_MCO_DIV2 + * @arg @ref MD_RCU_MPRE_MCO_DIV4 + * @arg @ref MD_RCU_MPRE_MCO_DIV8 + * @arg @ref MD_RCU_MPRE_MCO_DIV16 + * @arg @ref MD_RCU_MPRE_MCO_DIV32 + * @arg @ref MD_RCU_MPRE_MCO_DIV64 + * @arg @ref MD_RCU_MPRE_MCO_DIV128 + */ +__STATIC_INLINE uint32_t md_rcu_get_mco_div(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG, RCU_CFG_MPRE) >> RCU_CFG_MPRE_POSS); +} + +/** + * @brief Set MCO clock output (MCO) + * @param rcu RCU Instance + * @arg @ref MD_RCU_MSW_MCO_DISABLE + * @arg @ref MD_RCU_MSW_MCO_LRC + * @arg @ref MD_RCU_MSW_MCO_LOSC + * @arg @ref MD_RCU_MSW_MCO_HRC + * @arg @ref MD_RCU_MSW_MCO_HOSC + * @arg @ref MD_RCU_MSW_MCO_HRC48 + * @arg @ref MD_RCU_MSW_MCO_PLL0 + * @arg @ref MD_RCU_MSW_MCO_SYSCLK + * @arg @ref MD_RCU_MSW_MCO_HCLK + * @arg @ref MD_RCU_MSW_MCO_PCLK + * @retval None + */ +__STATIC_INLINE void md_rcu_set_mco_source(RCU_TypeDef *rcu, uint32_t msw) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_MSW, msw << RCU_CFG_MSW_POSS); +} + +/** + * @brief Get Microcontroller clock output (MCO) + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_MSW_MCO_DISABLE + * @arg @ref MD_RCU_MSW_MCO_LRC + * @arg @ref MD_RCU_MSW_MCO_LOSC + * @arg @ref MD_RCU_MSW_MCO_HRC + * @arg @ref MD_RCU_MSW_MCO_HOSC + * @arg @ref MD_RCU_MSW_MCO_HRC48 + * @arg @ref MD_RCU_MSW_MCO_PLL0 + * @arg @ref MD_RCU_MSW_MCO_SYSCLK + * @arg @ref MD_RCU_MSW_MCO_HCLK + * @arg @ref MD_RCU_MSW_MCO_PCLK + */ +__STATIC_INLINE uint32_t md_rcu_get_mco_source(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG, RCU_CFG_MSW) >> RCU_CFG_MSW_POSS); +} + +/** + * @brief Set PLL0 reference clock source + * @param rcu RCU Instance + * @arg @ref MD_RCU_PLLSRC_HRC + * @arg @ref MD_RCU_PLLSRC_HOSC + * @arg @ref MD_RCU_PLLSRC_HRC48 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_pll_source(RCU_TypeDef *rcu, uint32_t pllsrc) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_PLLSRC, pllsrc << RCU_CFG_PLLSRC_POSS); +} + +/** + * @brief Get PLL0/1 reference clock source + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_PLLSRC_HRC + * @arg @ref MD_RCU_PLLSRC_HOSC + * @arg @ref MD_RCU_PLLSRC_HRC48 + */ +__STATIC_INLINE uint32_t md_rcu_get_pll_source(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG, RCU_CFG_PLLSRC) >> RCU_CFG_PLLSRC_POSS); +} + +/** + * @brief Set PLL0 reference clock pre-divider + * @param rcu RCU Instance + * @arg @ref MD_RCU_PREDIV_PLL_DIV1 + * @arg @ref MD_RCU_PREDIV_PLL_DIV2 + * @arg @ref MD_RCU_PREDIV_PLL_DIV3 + * @arg @ref MD_RCU_PREDIV_PLL_DIV4 + * @arg @ref MD_RCU_PREDIV_PLL_DIV5 + * @arg @ref MD_RCU_PREDIV_PLL_DIV6 + * @arg @ref MD_RCU_PREDIV_PLL_DIV7 + * @arg @ref MD_RCU_PREDIV_PLL_DIV8 + * @arg @ref MD_RCU_PREDIV_PLL_DIV9 + * @arg @ref MD_RCU_PREDIV_PLL_DIV10 + * @arg @ref MD_RCU_PREDIV_PLL_DIV11 + * @arg @ref MD_RCU_PREDIV_PLL_DIV12 + * @arg @ref MD_RCU_PREDIV_PLL_DIV13 + * @arg @ref MD_RCU_PREDIV_PLL_DIV14 + * @arg @ref MD_RCU_PREDIV_PLL_DIV15 + * @arg @ref MD_RCU_PREDIV_PLL_DIV16 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_pll_prediv(RCU_TypeDef *rcu, uint32_t prediv) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_PREDIV, prediv << RCU_CFG_PREDIV_POSS); +} +/** + * @brief Get PLL0 reference clock pre-divider + * @note + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_PREDIV_PLL_DIV1 + * @arg @ref MD_RCU_PREDIV_PLL_DIV2 + * @arg @ref MD_RCU_PREDIV_PLL_DIV3 + * @arg @ref MD_RCU_PREDIV_PLL_DIV4 + * @arg @ref MD_RCU_PREDIV_PLL_DIV5 + * @arg @ref MD_RCU_PREDIV_PLL_DIV6 + * @arg @ref MD_RCU_PREDIV_PLL_DIV7 + * @arg @ref MD_RCU_PREDIV_PLL_DIV8 + * @arg @ref MD_RCU_PREDIV_PLL_DIV9 + * @arg @ref MD_RCU_PREDIV_PLL_DIV10 + * @arg @ref MD_RCU_PREDIV_PLL_DIV11 + * @arg @ref MD_RCU_PREDIV_PLL_DIV12 + * @arg @ref MD_RCU_PREDIV_PLL_DIV13 + * @arg @ref MD_RCU_PREDIV_PLL_DIV14 + * @arg @ref MD_RCU_PREDIV_PLL_DIV15 + * @arg @ref MD_RCU_PREDIV_PLL_DIV16 + */ +__STATIC_INLINE uint32_t md_rcu_get_pll_prediv(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG, RCU_CFG_PREDIV) >> RCU_CFG_PREDIV_POSS); +} + +/** + * @brief Set APB clock prescaler(PCLK) + * @param rcu RCU Instance + * @arg @ref MD_RCU_PPRE_HCLK_DIV_1 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_2 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_4 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_8 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_16 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_pclk_div(RCU_TypeDef *rcu, uint32_t ppre) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_PPRE, ppre << RCU_CFG_PPRE_POSS); +} + +/** + * @brief Get APB clock prescaler(PCLK) + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_PPRE_HCLK_DIV_1 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_2 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_4 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_8 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_16 + */ +__STATIC_INLINE uint32_t md_rcu_get_pclk_div(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG, RCU_CFG_PPRE) >> RCU_CFG_PPRE_POSS); +} + +/** + * @brief Set AHB clock prescaler(HCLK) + * @param rcu RCU Instance + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_1 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_2 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_4 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_8 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_16 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_64 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_128 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_256 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_hclk_div(RCU_TypeDef *rcu, uint32_t hpre) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_HPRE, hpre << RCU_CFG_HPRE_POSS); +} + +/** + * @brief Get AHB clock prescaler(HCLK) + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_1 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_2 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_4 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_8 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_16 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_64 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_128 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_256 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t md_rcu_get_hclk_div(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG, RCU_CFG_HPRE) >> RCU_CFG_HPRE_POSS); +} + +/** + * @brief System clock selection status + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_SWS_SYSCLK_HRC + * @arg @ref MD_RCU_SWS_SYSCLK_HOSC + * @arg @ref MD_RCU_SWS_SYSCLK_PLL0 + * @arg @ref MD_RCU_SWS_SYSCLK_HRC48 + */ +__STATIC_INLINE uint32_t md_rcu_get_current_system_clock(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG, RCU_CFG_SWS) >> RCU_CFG_SWS_POSS); +} + +/** + * @brief Select system clock (SYSCLK) source + * @param rcu RCU Instance + * @arg @ref MD_RCU_SW_SYSCLK_HRC + * @arg @ref MD_RCU_SW_SYSCLK_HOSC + * @arg @ref MD_RCU_SW_SYSCLK_PLL0 + * @arg @ref MD_RCU_SW_SYSCLK_HRC48 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_system_clock_source(RCU_TypeDef *rcu, uint32_t sw) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_SW, sw << RCU_CFG_SW_POSS); +} + +/** + * @brief Get Select system clock (SYSCLK) source + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_SW_SYSCLK_HRC + * @arg @ref MD_RCU_SW_SYSCLK_HOSC + * @arg @ref MD_RCU_SW_SYSCLK_PLL0 + * @arg @ref MD_RCU_SW_SYSCLK_HRC48 + */ +__STATIC_INLINE uint32_t md_rcu_get_system_clock_source(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG, RCU_CFG_SW) >> RCU_CFG_SW_POSS); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group4 PLL0 + * @{ + */ +/** + * @brief Set RCU_PLL0 Register + * @param rcu RCU Instance + * @param pll0 + */ +__STATIC_INLINE void md_rcu_set_pll0(RCU_TypeDef *rcu, uint32_t pll0) +{ + WRITE_REG(rcu->PLL0, pll0); +} + +/** + * @brief Get RCU_PLL0 Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_rcu_get_pll0(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->PLL0)); +} + +/** + * @brief Set PLL0 VCO frequency fractional multiplication value + * @param rcu RCU Instance + * @param fk + * @retval + */ +__STATIC_INLINE void md_rcu_set_pll0_fk(RCU_TypeDef *rcu, uint32_t fk) +{ + MODIFY_REG(rcu->PLL0, RCU_PLL0_FK, (fk << RCU_PLL0_FK_POSS)); +} + +/** + * @brief Get PLL0 VCO frequency fractional multiplication value + * @param rcu RCU Instance + * @retval fk + */ +__STATIC_INLINE uint32_t md_rcu_get_pll0_fk(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->PLL0, RCU_PLL0_FK) >> RCU_PLL0_FK_POSS); +} + +/** + * @brief Set PLL0 VCO frequency integer multiplication value + * @param rcu RCU Instance + * @param fn + * @retval + */ +__STATIC_INLINE void md_rcu_set_pll0_fn(RCU_TypeDef *rcu, uint32_t fn) +{ + MODIFY_REG(rcu->PLL0, RCU_PLL0_FN, (fn << RCU_PLL0_FN_POSS)); +} + +/** + * @brief Get PLL0 VCO frequency integer multiplication value + * @param rcu RCU Instance + * @retval fn + */ +__STATIC_INLINE uint32_t md_rcu_get_pll0_fn(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->PLL0, RCU_PLL0_FN) >> RCU_PLL0_FN_POSS); +} + +/** + * @brief Set PLL0 clock output frequency division ratio + * @param rcu RCU Instance + * @arg @ref MD_RCU_FM_PLL0_DIV_8 + * @arg @ref MD_RCU_FM_PLL0_DIV_16 + * @arg @ref MD_RCU_FM_PLL0_DIV_32 + * @arg @ref MD_RCU_FM_PLL0_DIV_64 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_pll0_fm(RCU_TypeDef *rcu, uint32_t fm) +{ + MODIFY_REG(rcu->PLL0, RCU_PLL0_FM, fm << RCU_PLL0_FM_POSS); +} + +/** + * @brief Get PLL0 clock output frequency division ratio + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_FM_PLL0_DIV_8 + * @arg @ref MD_RCU_FM_PLL0_DIV_16 + * @arg @ref MD_RCU_FM_PLL0_DIV_32 + * @arg @ref MD_RCU_FM_PLL0_DIV_64 + */ +__STATIC_INLINE uint32_t md_rcu_get_pll0_fm(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->PLL0, RCU_PLL0_FM) >> RCU_PLL0_FM_POSS); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group5 CFG2 + * @{ + */ +/** + * @brief Set RCU_CFG2 Register + * @param rcu RCU Instance + * @param cfg2 + */ +__STATIC_INLINE void md_rcu_set_cfg2(RCU_TypeDef *rcu, uint32_t cfg2) +{ + WRITE_REG(rcu->CFG2, cfg2); +} + +/** + * @brief Get RCU_CFG2 Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_rcu_get_cfg2(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->CFG2)); +} + +/** + * @brief Set Current system clock frequency + * @param rcu RCU Instance + * @param sysfreq + * @arg Max Value 0xFF + * @arg Min Value 0x4 + * @retval + */ +__STATIC_INLINE void md_rcu_set_current_system_frequency(RCU_TypeDef *rcu, uint32_t sysfreq) +{ + MODIFY_REG(rcu->CFG2, RCU_CFG2_SYSFREQ, (sysfreq << RCU_CFG2_SYSFREQ_POSS)); +} + +/** + * @brief Get Current system clock frequency + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xFF + * @arg Min Value 0x4 + */ +__STATIC_INLINE uint32_t md_rcu_get_current_system_frequency(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG2, RCU_CFG2_SYSFREQ) >> RCU_CFG2_SYSFREQ_POSS); +} + +/** + * @brief Set USB clock (USBCLK) source + * @param rcu RCU Instance + * @param usbsw + * @arg @ref MD_RCU_USBSW_USBCLK_HRC48CLK + * @arg @ref MD_RCU_USBSW_USBCLK_PLL0CLK + * @retval None + */ +__STATIC_INLINE void md_rcu_set_usb_phyclk_source(RCU_TypeDef *rcu, uint32_t usbsw) +{ + MODIFY_REG(rcu->CFG2, RCU_CFG2_USBSW, usbsw << RCU_CFG2_USBSW_POSS); +} + +/** + * @brief Get USB clock (USBCLK) source + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_USBSW_USBCLK_HRC48CLK + * @arg @ref MD_RCU_USBSW_USBCLK_PLL0CLK + */ +__STATIC_INLINE uint32_t md_rcu_get_usb_phyclk_source(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG2, RCU_CFG2_USBSW) >> RCU_CFG2_USBSW_POSS); +} + +/** + * @brief Set I2S clock (I2SCLK) source + * @param rcu RCU Instance + * @param i2ssw + * @arg @ref MD_RCU_I2SSW_I2SCLK_HRC48CLK + * @arg @ref MD_RCU_I2SSW_I2SCLK_HOSCCLK + * @arg @ref MD_RCU_I2SSW_I2SCLK_PLL0CLK + * @retval None + */ +__STATIC_INLINE void md_rcu_set_i2s_clk_source(RCU_TypeDef *rcu, uint32_t i2ssw) +{ + MODIFY_REG(rcu->CFG2, RCU_CFG2_I2SSW, i2ssw << RCU_CFG2_I2SSW_POSS); +} + +/** + * @brief Get I2S clock (I2SCLK) source + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_I2SSW_I2SCLK_HRC48CLK + * @arg @ref MD_RCU_I2SSW_I2SCLK_HOSCCLK + * @arg @ref MD_RCU_I2SSW_I2SCLK_PLL0CLK + */ +__STATIC_INLINE uint32_t md_rcu_get_i2s_clk_source(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CFG2, RCU_CFG2_I2SSW) >> RCU_CFG2_I2SSW_POSS); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group6 IER + * @{ + */ +/** + * @brief Set RCU_IER Register + * @param rcu RCU Instance + * @param ier + */ +__STATIC_INLINE void md_rcu_set_ier(RCU_TypeDef *rcu, uint32_t ier) +{ + WRITE_REG(rcu->IER, ier); +} + +/** + * @brief Clock security system interrupt enable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_enable_it_css_hosc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IER, RCU_IER_CSSHOSC); +} + +/** + * @brief PLL clock source stable interrupt enable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_enable_it_pll0_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IER, RCU_IER_PLL0RDY); +} + +/** + * @brief HRC48 clock source stable interrupt enable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_enable_it_hrc48_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IER, RCU_IER_HRC48RDY); +} + +/** + * @brief HOSC clock source stable interrupt enable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_enable_it_hosc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IER, RCU_IER_HOSCRDY); +} + +/** + * @brief HRC clock source stable interrupt enable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_enable_it_hrc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IER, RCU_IER_HRCRDY); +} + +/** + * @brief LOSC clock source stable interrupt enable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_enable_it_losc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IER, RCU_IER_LOSCRDY); +} + +/** + * @brief LRC clock source stable interrupt enable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_enable_it_lrc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IER, RCU_IER_LRCRDY); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group7 IDR + * @{ + */ +/** + * @brief Set RCU_IDR Register + * @param rcu RCU Instance + * @param idr + */ +__STATIC_INLINE void md_rcu_set_idr(RCU_TypeDef *rcu, uint32_t idr) +{ + WRITE_REG(rcu->IDR, idr); +} + +/** + * @brief Clock security system interrupt disable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_disable_it_css_hosc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IDR, RCU_IDR_CSSHOSC); +} + +/** + * @brief PLL clock source stable interrupt disable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_disable_it_pll0_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IDR, RCU_IDR_PLL0RDY); +} + +/** + * @brief HRC48 clock source stable interrupt disable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_disable_it_hrc48_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IDR, RCU_IDR_HRC48RDY); +} + +/** + * @brief HOSC clock source stable interrupt disable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_disable_it_hosc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IDR, RCU_IDR_HOSCRDY); +} + +/** + * @brief HRC clock source stable interrupt disable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_disable_it_hrc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IDR, RCU_IDR_HRCRDY); +} + +/** + * @brief LOSC clock source stable interrupt disable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_disable_it_losc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IDR, RCU_IDR_LOSCRDY); +} + +/** + * @brief LRC clock source stable interrupt disable + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE void md_rcu_disable_it_lrc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->IDR, RCU_IDR_LRCRDY); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group8 IVS + * @{ + */ +/** + * @brief Set RCU_IVS Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_rcu_get_ivs(RCU_TypeDef *rcu) +{ + return (uint32_t) READ_REG(rcu->IVS); +} + +/** + * @brief Clock security system interrupt active state + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_it_css_hosc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IVS, RCU_IVS_CSSHOSC) == (RCU_IVS_CSSHOSC)); +} + +/** + * @brief PLL clock source stable interrupt active state + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_it_pll0_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IVS, RCU_IVS_PLL0RDY) == (RCU_IVS_PLL0RDY)); +} + +/** + * @brief HRC48 clock source stable interrupt active state + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_it_hrc48_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IVS, RCU_IVS_HRC48RDY) == (RCU_IVS_HRC48RDY)); +} + +/** + * @brief HOSC clock source stable interrupt active state + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_it_hosc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IVS, RCU_IVS_HOSCRDY) == (RCU_IVS_HOSCRDY)); +} + +/** + * @brief HRC clock source stable interrupt active state + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_it_hrc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IVS, RCU_IVS_HRCRDY) == (RCU_IVS_HRCRDY)); +} + +/** + * @brief LOSC clock source stable interrupt active state + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_it_losc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IVS, RCU_IVS_LOSCRDY) == (RCU_IVS_LOSCRDY)); +} + +/** + * @brief LRC clock source stable interrupt active state + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_it_lrc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IVS, RCU_IVS_LRCRDY) == (RCU_IVS_LRCRDY)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group9 RIF + * @{ + */ +/** + * @brief Set RCU_RIF Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_rcu_get_rif(RCU_TypeDef *rcu) +{ + return (uint32_t)READ_REG(rcu->RIF); +} + +/** + * @brief Clock security system unmasked interrupt flag status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_active_it_css_hosc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RIF, RCU_RIF_CSSHOSC) == (RCU_RIF_CSSHOSC)); +} + +/** + * @brief PLL clock source stable unmasked interrupt flag status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_active_it_pll0_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RIF, RCU_RIF_PLL0RDY) == (RCU_RIF_PLL0RDY)); +} + +/** + * @brief HRC48 clock source stable unmasked interrupt flag status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_active_it_hrc48_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RIF, RCU_RIF_HRC48RDY) == (RCU_RIF_HRC48RDY)); +} + +/** + * @brief HOSC clock source stable unmasked interrupt flag status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_active_it_hosc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RIF, RCU_RIF_HOSCRDY) == (RCU_RIF_HOSCRDY)); +} + +/** + * @brief HRC clock source stable unmasked interrupt flag status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_active_it_hrc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RIF, RCU_RIF_HRCRDY) == (RCU_RIF_HRCRDY)); +} + +/** + * @brief LOSC clock source stable unmasked interrupt flag status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_active_it_losc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RIF, RCU_RIF_LOSCRDY) == (RCU_RIF_LOSCRDY)); +} + +/** + * @brief LRC clock source stable unmasked interrupt flag status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_active_it_lrc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RIF, RCU_RIF_LRCRDY) == (RCU_RIF_LRCRDY)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group10 IFM + * @{ + */ +/** + * @brief Set RCU_IFM Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_rcu_get_ifm(RCU_TypeDef *rcu) +{ + return (uint32_t)READ_REG(rcu->IFM); +} + +/** + * @brief Clock security system interrupt flag mask status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_masked_it_css_hosc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IFM, RCU_IFM_CSSHOSC) == (RCU_IFM_CSSHOSC)); +} + +/** + * @brief PLL clock source stable interrupt flag mask status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_masked_it_pll0_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IFM, RCU_IFM_PLL0RDY) == (RCU_IFM_PLL0RDY)); +} + +/** + * @brief HRC48 clock source stable interrupt flag mask status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_masked_it_hrc48_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IFM, RCU_IFM_HRC48RDY) == (RCU_IFM_HRC48RDY)); +} + +/** + * @brief HOSC clock source stable interrupt flag mask status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_masked_it_hosc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IFM, RCU_IFM_HOSCRDY) == (RCU_IFM_HOSCRDY)); +} + +/** + * @brief HRC clock source stable interrupt flag mask status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_masked_it_hrc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IFM, RCU_IFM_HRCRDY) == (RCU_IFM_HRCRDY)); +} + +/** + * @brief LOSC clock source stable interrupt flag mask status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_masked_it_losc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IFM, RCU_IFM_LOSCRDY) == (RCU_IFM_LOSCRDY)); +} + +/** + * @brief LRC clock source stable interrupt flag mask status + * @param rcu RCU Instance + * @retval None. + */ +__STATIC_INLINE uint32_t md_rcu_is_masked_it_lrc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->IFM, RCU_IFM_LRCRDY) == (RCU_IFM_LRCRDY)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group11 ICR + * @{ + */ +/** + * @brief Set RCU_ICR Register + * @param rcu RCU Instance + * @param icr + */ +__STATIC_INLINE void md_rcu_set_icr(RCU_TypeDef *rcu, uint32_t icr) +{ + WRITE_REG(rcu->ICR, icr); +} + +/** + * @brief Clear Clock security system interrupt + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_rcu_clear_it_css_hosc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->ICR, RCU_ICR_CSSHOSC); +} + +/** + * @brief Clear PLL0 clock source stable interrupt flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_rcu_clear_it_pll0_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->ICR, RCU_ICR_PLL0RDY); +} + +/** + * @brief Clear HRC48 clock source stable interrupt flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_rcu_clear_it_hrc48_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->ICR, RCU_ICR_HRC48RDY); +} + +/** + * @brief Clear HOSC clock source stable interrupt flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_rcu_clear_it_hosc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->ICR, RCU_ICR_HOSCRDY); +} + +/** + * @brief Clear HRC clock source stable interrupt flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_rcu_clear_it_hrc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->ICR, RCU_ICR_HRCRDY); +} + +/** + * @brief Clear LOSC clock source stable interrupt flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_rcu_clear_it_losc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->ICR, RCU_ICR_LOSCRDY); +} + +/** + * @brief Clear LRC clock source stable interrupt flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_rcu_clear_it_lrc_ready(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->ICR, RCU_ICR_LRCRDY); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group12 AHBRST + * @{ + */ +/** + * @brief Set RCU_AHBRST Register + * @param rcu RCU Instance + * @param ahbrst + */ +__STATIC_INLINE void md_rcu_set_ahbrst(RCU_TypeDef *rcu, uint32_t ahbrst) +{ + WRITE_REG(rcu->AHBRST, ahbrst); +} + +/** + * @brief Get RCU_AHBRST Register + * @param rcu RCU Instance + * @param ahbrst + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->AHBRST)); +} + +/** + * @brief GPIOD reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpiod_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN); +} + +/** + * @brief GPIOD reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpiod_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN); +} + +/** + * @brief Get GPIOD reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpiod_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN) == (RCU_AHBRST_GPDEN)); +} + +/** + * @brief GPIOC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpioc_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN); +} + +/** + * @brief GPIOC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpioc_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN); +} + +/** + * @brief Get GPIOC reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpioc_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN) == (RCU_AHBRST_GPCEN)); +} + +/** + * @brief GPIOB reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpiob_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN); +} + +/** + * @brief GPIOB reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpiob_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN); +} + +/** + * @brief Get GPIOB reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpiob_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN) == (RCU_AHBRST_GPBEN)); +} + +/** + * @brief GPIOA reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpioa_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN); +} + +/** + * @brief GPIOA reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpioa_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN); +} + +/** + * @brief Get GPIOA reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpioa_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN) == (RCU_AHBRST_GPAEN)); +} + +/** + * @brief CALC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_calc_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_CALCEN); +} + +/** + * @brief CALC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_calc_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_CALCEN); +} + +/** + * @brief Get CALC reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_calc_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_CALCEN) == (RCU_AHBRST_CALCEN)); +} + +/** + * @brief USB reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_usb_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_USBEN); +} + +/** + * @brief USB reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_usb_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_USBEN); +} + +/** + * @brief Get USB reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_usb_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_USBEN) == (RCU_AHBRST_USBEN)); +} + +/** + * @brief AES reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_aes_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_AESEN); +} + +/** + * @brief AES reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_aes_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_AESEN); +} + +/** + * @brief Get AES reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_aes_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_AESEN) == (RCU_AHBRST_AESEN)); +} + +/** + * @brief CRC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_crc_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN); +} + +/** + * @brief CRC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_crc_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN); +} + +/** + * @brief Get CRC reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_crc_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN) == (RCU_AHBRST_CRCEN)); +} + +/** + * @brief CSU reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_csu_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_CSUEN); +} + +/** + * @brief CSU reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_csu_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_CSUEN); +} + +/** + * @brief Get CSU reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_csu_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_CSUEN) == (RCU_AHBRST_CSUEN)); +} + +/** + * @brief KBCU reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_kbcu_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_KBCUEN); +} + +/** + * @brief KBCU reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_kbcu_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_KBCUEN); +} + +/** + * @brief Get KBCU reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_kbcu_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_KBCUEN) == (RCU_AHBRST_KBCUEN)); +} + +/** + * @brief RTC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_rtc_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN); +} + +/** + * @brief RTC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_rtc_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN); +} + +/** + * @brief Get RTC reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_rtc_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN) == (RCU_AHBRST_RTCEN)); +} + +/** + * @brief DMA1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_dma1_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN); +} + +/** + * @brief DMA1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_dma1_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN); +} + +/** + * @brief Get DMA1 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_dma1_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN) == (RCU_AHBRST_DMA1EN)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group13 APB1RST + * @{ + */ +/** + * @brief Set RCU_APB1RST Register + * @param rcu RCU Instance + * @param apb1rst + */ +__STATIC_INLINE void md_rcu_set_apb1rst(RCU_TypeDef *rcu, uint32_t apb1rst) +{ + WRITE_REG(rcu->APB1RST, apb1rst); +} + +/** + * @brief Get RCU_APB1RST Register + * @param rcu RCU Instance + * @param apb1rst + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->APB1RST)); +} + +/** + * @brief I2C2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_i2c2_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN); +} + +/** + * @brief I2C2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_i2c2_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN); +} + +/** + * @brief Get I2C2 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_i2c2_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN) == (RCU_APB1RST_I2C2EN)); +} + +/** + * @brief I2C1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_i2c1_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN); +} + +/** + * @brief I2C1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_i2c1_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN); +} + +/** + * @brief Get I2C1 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_i2c1_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN) == (RCU_APB1RST_I2C1EN)); +} + +/** + * @brief UART4 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart4_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_UART4EN); +} + +/** + * @brief UART4 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart4_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_UART4EN); +} + +/** + * @brief Get UART4 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart4_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_UART4EN) == (RCU_APB1RST_UART4EN)); +} + +/** + * @brief UART3 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart3_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN); +} + +/** + * @brief UART3 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart3_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN); +} + +/** + * @brief Get UART3 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart3_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN) == (RCU_APB1RST_UART3EN)); +} + +/** + * @brief UART2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart2_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN); +} + +/** + * @brief UART2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart2_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN); +} + +/** + * @brief Get UART2 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart2_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN) == (RCU_APB1RST_UART2EN)); +} + +/** + * @brief SPI3 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_spi3_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_SPI3EN); +} + +/** + * @brief SPI3 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_spi3_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SPI3EN); +} + +/** + * @brief Get SPI3 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_spi3_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SPI3EN) == (RCU_APB1RST_SPI3EN)); +} + +/** + * @brief SPI2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_spi2_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN); +} + +/** + * @brief SPI2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_spi2_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN); +} + +/** + * @brief Get SPI2 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_spi2_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN) == (RCU_APB1RST_SPI2EN)); +} + +/** + * @brief WWDT reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_wwdt_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN); +} + +/** + * @brief WWDT reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_wwdt_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN); +} + +/** + * @brief Get WWDT reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_wwdt_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN) == (RCU_APB1RST_WWDTEN)); +} + +/** + * @brief BS16T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_bs16t1_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN); +} + +/** + * @brief BS16T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_bs16t1_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN); +} + +/** + * @brief Get BS16T1 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_bs16t1_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN) == (RCU_APB1RST_BS16T1EN)); +} + +/** + * @brief GP16C4T3 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c4t3_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN); +} + +/** + * @brief GP16C4T3 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c4t3_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN); +} + +/** + * @brief Get GP16C4T3 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c4t3_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN) == (RCU_APB1RST_GP16C4T3EN)); +} + +/** + * @brief GP16C4T2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c4t2_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN); +} + +/** + * @brief GP16C4T2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c4t2_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN); +} + +/** + * @brief Get GP16C4T2 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c4t2_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN) == (RCU_APB1RST_GP16C4T2EN)); +} + +/** + * @brief GP16C4T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c4t1_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN); +} + +/** + * @brief GP16C4T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c4t1_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN); +} + +/** + * @brief Get GP16C4T1 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c4t1_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN) == (RCU_APB1RST_GP16C4T1EN)); +} + +/** + * @brief GP32C4T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp32c4t1_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN); +} + +/** + * @brief GP32C4T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp32c4t1_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN); +} + +/** + * @brief Get GP32C4T1 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp32c4t1_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN) == (RCU_APB1RST_GP32C4T1EN)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group14 APB2RST + * @{ + */ +/** + * @brief Set RCU_APB2RST Register + * @param rcu RCU Instance + * @param apb2rst + */ +__STATIC_INLINE void md_rcu_set_apb2rst(RCU_TypeDef *rcu, uint32_t apb2rst) +{ + WRITE_REG(rcu->APB2RST, apb2rst); +} + +/** + * @brief Get RCU_APB2RST Register + * @param rcu RCU Instance + * @param apb2rst + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->APB2RST)); +} + +/** + * @brief CMP reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_cmp_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN); +} + +/** + * @brief CMP reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_cmp_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN); +} + +/** + * @brief Get CMP reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_cmp_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN) == (RCU_APB2RST_CMPEN)); +} + +/** + * @brief GP16C2T4 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t4_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN); +} + +/** + * @brief GP16C2T4 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t4_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN); +} + +/** + * @brief Get GP16C2T4 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t4_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN) == (RCU_APB2RST_GP16C2T4EN)); +} + +/** + * @brief GP16C2T3 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t3_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN); +} + +/** + * @brief GP16C2T3 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t3_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN); +} + +/** + * @brief Get GP16C2T3 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t3_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN) == (RCU_APB2RST_GP16C2T3EN)); +} + +/** + * @brief GP16C2T2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t2_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN); +} + +/** + * @brief GP16C2T2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t2_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN); +} + +/** + * @brief Get GP16C2T2 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t2_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN) == (RCU_APB2RST_GP16C2T2EN)); +} + +/** + * @brief GP16C2T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t1_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN); +} + +/** + * @brief GP16C2T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t1_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN); +} + +/** + * @brief Get GP16C2T1 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t1_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN) == (RCU_APB2RST_GP16C2T1EN)); +} + +/** + * @brief UART1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart1_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN); +} + +/** + * @brief UART1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart1_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN); +} + +/** + * @brief Get UART1 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart1_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN) == (RCU_APB2RST_UART1EN)); +} + +/** + * @brief SPI1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_spi1_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN); +} + +/** + * @brief I2S1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_i2s1_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN); +} + + +/** + * @brief SPI1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_spi1_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN); +} + +/** + * @brief I2S1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_i2s1_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN); +} + +/** + * @brief Get SPI1 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_spi1_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN) == (RCU_APB2RST_SPI1EN)); +} + +/** + * @brief Get I2S1 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_i2s1_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN) == (RCU_APB2RST_SPI1EN)); +} + +/** + * @brief AD16C4T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ad16c4t1_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN); +} + +/** + * @brief AD16C4T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ad16c4t1_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN); +} + +/** + * @brief Get AD16C4T1 reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_ad16c4t1_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN) == (RCU_APB2RST_AD16C4T1EN)); +} + +/** + * @brief ADC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_adc_reset(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN); +} + +/** + * @brief ADC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_adc_reset(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN); +} + +/** + * @brief Get ADC reset request bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Reset enable + * @arg 0x0 : Reset disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_adc_reset(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN) == (RCU_APB2RST_ADCEN)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group15 AHBEN + * @{ + */ +/** + * @brief Set RCU_AHBEN Register + * @param rcu RCU Instance + * @param ahben + */ +__STATIC_INLINE void md_rcu_set_ahben(RCU_TypeDef *rcu, uint32_t ahben) +{ + WRITE_REG(rcu->AHBEN, ahben); +} + +/** + * @brief Get RCU_AHBEN Register + * @param rcu RCU Instance + * @param ahben + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->AHBEN)); +} + +/** + * @brief GPIOD clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpiod(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN); +} + +/** + * @brief GPIOD Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpiod(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN); +} + +/** + * @brief Get GPIOD Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpiod enable + * @arg 0x0 : gpiod disable. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpiod(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN) == (RCU_AHBEN_GPDEN)); +} + +/** + * @brief GPIOC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpioc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN); +} + +/** + * @brief GPIOC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpioc(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN); +} + +/** + * @brief Get GPIOC Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpioc enable + * @arg 0x0 : gpioc disable. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpioc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN) == (RCU_AHBEN_GPCEN)); +} + +/** + * @brief GPIOB clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpiob(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN); +} + +/** + * @brief GPIOB Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpiob(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN); +} + +/** + * @brief Get GPIOB Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpiob enable + * @arg 0x0 : gpiob disable. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpiob(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN) == (RCU_AHBEN_GPBEN)); +} + +/** + * @brief GPIOA clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpioa(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN); +} + +/** + * @brief GPIOA Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpioa(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN); +} + +/** + * @brief Get GPIOA Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpioa enable + * @arg 0x0 : gpioa disable. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpioa(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN) == (RCU_AHBEN_GPAEN)); +} + +/** + * @brief CALC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_calc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_CALCEN); +} + +/** + * @brief CALC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_calc(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_CALCEN); +} + +/** + * @brief Get CALC Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : calc enable + * @arg 0x0 : calc disable. + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_calc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_CALCEN) == (RCU_AHBEN_CALCEN)); +} + +/** + * @brief USB clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_usb(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_USBEN); +} + +/** + * @brief USB Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_usb(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_USBEN); +} + +/** + * @brief Get USB Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : usb enable + * @arg 0x0 : usb disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_usb(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_USBEN) == (RCU_AHBEN_USBEN)); +} + +/** + * @brief AES clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_aes(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_AESEN); +} + +/** + * @brief AES Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_aes(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_AESEN); +} + +/** + * @brief Get AES Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : aes enable + * @arg 0x0 : aes disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_aes(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_AESEN) == (RCU_AHBEN_AESEN)); +} + +/** + * @brief CRC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_crc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN); +} + +/** + * @brief CRC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_crc(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN); +} + +/** + * @brief Get CRC Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : crc enable + * @arg 0x0 : crc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_crc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN) == (RCU_AHBEN_CRCEN)); +} + +/** + * @brief CSU clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_csu(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_CSUEN); +} + +/** + * @brief CSU Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_csu(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_CSUEN); +} + +/** + * @brief Get CSU Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : csu enable + * @arg 0x0 : csu disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_csu(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_CSUEN) == (RCU_AHBEN_CSUEN)); +} + +/** + * @brief KBCU clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_kbcu(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_KBCUEN); +} + +/** + * @brief KBCU Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_kbcu(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_KBCUEN); +} + +/** + * @brief Get KBCU Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : kbcu enable + * @arg 0x0 : kbcu disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_kbcu(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_KBCUEN) == (RCU_AHBEN_KBCUEN)); +} + +/** + * @brief RTC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_rtc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN); +} + +/** + * @brief RTC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_rtc(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN); +} + +/** + * @brief Get RTC Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : rtc enable + * @arg 0x0 : rtc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_rtc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN) == (RCU_AHBEN_RTCEN)); +} + +/** + * @brief DMA1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_dma1(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN); +} + +/** + * @brief DMA1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_dma1(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN); +} + +/** + * @brief Get DMA1 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : dma1 enable + * @arg 0x0 : dma1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_dma1(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN) == (RCU_AHBEN_DMA1EN)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group16 APB1EN + * @{ + */ +/** + * @brief Set RCU_APB1EN Register + * @param rcu RCU Instance + * @param apb1en + */ +__STATIC_INLINE void md_rcu_set_apb1en(RCU_TypeDef *rcu, uint32_t apb1en) +{ + WRITE_REG(rcu->APB1EN, apb1en); +} + +/** + * @brief Get RCU_APB1EN Register + * @param rcu RCU Instance + * @param apb1en + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->APB1EN)); +} + +/** + * @brief I2C2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_i2c2(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN); +} + +/** + * @brief I2C2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_i2c2(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN); +} + +/** + * @brief Get I2C2 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : i2c2 enable + * @arg 0x0 : i2c2 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_i2c2(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN) == (RCU_APB1EN_I2C2EN)); +} + +/** + * @brief I2C1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_i2c1(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN); +} + +/** + * @brief I2C1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_i2c1(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN); +} + +/** + * @brief Get I2C1 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : i2c1 enable + * @arg 0x0 : i2c1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_i2c1(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN) == (RCU_APB1EN_I2C1EN)); +} + +/** + * @brief UART4 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart4(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_UART4EN); +} + +/** + * @brief UART4 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart4(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_UART4EN); +} + +/** + * @brief Get UART4 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart4 enable + * @arg 0x0 : uart4 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart4(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_UART4EN) == (RCU_APB1EN_UART4EN)); +} + +/** + * @brief UART3 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart3(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN); +} + +/** + * @brief UART3 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart3(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN); +} + +/** + * @brief Get UART3 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart3 enable + * @arg 0x0 : uart3 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart3(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN) == (RCU_APB1EN_UART3EN)); +} + +/** + * @brief UART2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart2(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN); +} + +/** + * @brief UART2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart2(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN); +} + +/** + * @brief Get UART2 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart2 enable + * @arg 0x0 : uart2 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart2(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN) == (RCU_APB1EN_UART2EN)); +} + + +/** + * @brief SPI3 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_spi3(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_SPI3EN); +} + +/** + * @brief SPI3 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_spi3(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SPI3EN); +} + +/** + * @brief Get SPI3 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi3 enable + * @arg 0x0 : spi3 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_spi3(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SPI3EN) == (RCU_APB1EN_SPI3EN)); +} + + +/** + * @brief SPI2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_spi2(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN); +} + +/** + * @brief SPI2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_spi2(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN); +} + +/** + * @brief Get SPI2 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi2 enable + * @arg 0x0 : spi2 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_spi2(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN) == (RCU_APB1EN_SPI2EN)); +} + +/** + * @brief WWDT clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_wwdt(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN); +} + +/** + * @brief WWDT Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_wwdt(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN); +} + +/** + * @brief Get WWDT Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : wwdt enable + * @arg 0x0 : wwdt disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_wwdt(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN) == (RCU_APB1EN_WWDTEN)); +} + +/** + * @brief BS16T1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_bs16t1(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN); +} + +/** + * @brief BS16T1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_bs16t1(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN); +} + +/** + * @brief Get BS16T1 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : bs16t1 enable + * @arg 0x0 : bs16t1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_bs16t1(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN) == (RCU_APB1EN_BS16T1EN)); +} + +/** + * @brief GP16C4T3 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c4t3(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN); +} + +/** + * @brief GP16C4T3 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c4t3(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN); +} + +/** + * @brief Get GP16C4T3 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c4t3 enable + * @arg 0x0 : gp16c4t3 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c4t3(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN) == (RCU_APB1EN_GP16C4T3EN)); +} + +/** + * @brief GP16C4T2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c4t2(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN); +} + +/** + * @brief GP16C4T2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c4t2(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN); +} + +/** + * @brief Get GP16C4T2 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c4t2 enable + * @arg 0x0 : gp16c4t2 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c4t2(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN) == (RCU_APB1EN_GP16C4T2EN)); +} + +/** + * @brief GP16C4T1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c4t1(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN); +} + +/** + * @brief GP16C4T1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c4t1(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN); +} + +/** + * @brief Get GP16C4T1 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c4t1 enable + * @arg 0x0 : gp16c4t1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c4t1(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN) == (RCU_APB1EN_GP16C4T1EN)); +} + +/** + * @brief GP32C4T1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp32c4t1(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN); +} + +/** + * @brief GP32C4T1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp32c4t1(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN); +} + +/** + * @brief Get GP32C4T1 Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp32c4t1 enable + * @arg 0x0 : gp32c4t1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp32c4t1(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN) == (RCU_APB1EN_GP32C4T1EN)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group17 APB2EN + * @{ + */ +/** + * @brief Set RCU_APB2EN Register + * @param rcu RCU Instance + * @param apb2en + */ +__STATIC_INLINE void md_rcu_set_apb2en(RCU_TypeDef *rcu, uint32_t apb2en) +{ + WRITE_REG(rcu->APB2EN, apb2en); +} + +/** + * @brief Get RCU_APB2EN Register + * @param rcu RCU Instance + * @param apb2en + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->APB2EN)); +} + +/** + * @brief CMP clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_cmp(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN); +} + +/** + * @brief CMP Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_cmp(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN); +} + +/** + * @brief Get CMP Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : cmp enable + * @arg 0x0 : cmp disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_cmp(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN) == (RCU_APB2EN_CMPEN)); +} + +/** + * @brief GP16C2T4EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t4(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN); +} + +/** + * @brief GP16C2T4EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t4(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN); +} + +/** + * @brief Get GP16C2T4EN Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t4 enable + * @arg 0x0 : gp16c2t4 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t4(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN) == (RCU_APB2EN_GP16C2T4EN)); +} + +/** + * @brief GP16C2T3EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t3(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN); +} + +/** + * @brief GP16C2T3EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t3(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN); +} + +/** + * @brief Get GP16C2T3EN Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t3 enable + * @arg 0x0 : gp16c2t3 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t3(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN) == (RCU_APB2EN_GP16C2T3EN)); +} + +/** + * @brief GP16C2T2EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t2(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN); +} + +/** + * @brief GP16C2T2EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t2(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN); +} + +/** + * @brief Get GP16C2T2EN Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t2 enable + * @arg 0x0 : gp16c2t2 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t2(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN) == (RCU_APB2EN_GP16C2T2EN)); +} + +/** + * @brief GP16C2T1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t1(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN); +} + +/** + * @brief GP16C2T1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t1(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN); +} + +/** + * @brief Get GP16C2T1EN Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t1 enable + * @arg 0x0 : gp16c2t1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t1(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN) == (RCU_APB2EN_GP16C2T1EN)); +} + +/** + * @brief UART1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart1(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN); +} + +/** + * @brief UART1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart1(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN); +} + +/** + * @brief Get UART1EN Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart1 enable + * @arg 0x0 : uart1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart1(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN) == (RCU_APB2EN_UART1EN)); +} + +/** + * @brief SPI1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_spi1(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN); +} + +/** + * @brief I2S1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_i2s1(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN); +} + +/** + * @brief SPI1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_spi1(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN); +} + +/** + * @brief I2S1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_i2s1(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN); +} + +/** + * @brief Get SPI1EN Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi1 enable + * @arg 0x0 : spi1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_spi1(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN) == (RCU_APB2EN_SPI1EN)); +} + +/** + * @brief Get I2S1EN Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi1 enable + * @arg 0x0 : spi1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_i2s1(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN) == (RCU_APB2EN_SPI1EN)); +} + +/** + * @brief AD16C4T1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ad16c4t1(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN); +} + +/** + * @brief AD16C4T1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ad16c4t1(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN); +} + +/** + * @brief Get AD16C4T1EN Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : ad16c4t1 enable + * @arg 0x0 : ad16c4t1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_ad16c4t1(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN) == (RCU_APB2EN_AD16C4T1EN)); +} + +/** + * @brief ADCEN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_adc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN); +} + +/** + * @brief ADCEN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_adc(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN); +} + +/** + * @brief Get ADCEN Clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : adc enable + * @arg 0x0 : adc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_adc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN) == (RCU_APB2EN_ADCEN)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group18 AHBSL + * @{ + */ +/** + * @brief Set RCU_AHBSL Register + * @param rcu RCU Instance + * @param ahbsl + */ +__STATIC_INLINE void md_rcu_set_ahbsl(RCU_TypeDef *rcu, uint32_t ahbsl) +{ + WRITE_REG(rcu->AHBSL, ahbsl); +} + +/** + * @brief Get RCU_AHBSL Register + * @param rcu RCU Instance + * @param ahbsl + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->AHBSL)); +} + +/** + * @brief GPDEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpiod_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN); +} + +/** + * @brief GPDEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpiod_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN); +} + +/** + * @brief Get GPDEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpiod enable + * @arg 0x0 : gpiod disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpiod_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN) == (RCU_AHBSL_GPDEN)); +} + +/** + * @brief GPCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpioc_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN); +} + +/** + * @brief GPCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpioc_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN); +} + +/** + * @brief Get GPCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpioc enable + * @arg 0x0 : gpioc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpioc_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN) == (RCU_AHBSL_GPCEN)); +} + +/** + * @brief GPBEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpiob_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN); +} + +/** + * @brief GPBEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpiob_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN); +} + +/** + * @brief Get GPBEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpiob enable + * @arg 0x0 : gpiob disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpiob_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN) == (RCU_AHBSL_GPBEN)); +} + +/** + * @brief GPAEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gpioa_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN); +} + +/** + * @brief GPAEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gpioa_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN); +} + +/** + * @brief Get GPAEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpioa enable + * @arg 0x0 : gpioa disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gpioa_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN) == (RCU_AHBSL_GPAEN)); +} + +/** + * @brief CALCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_calc_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_CALCEN); +} + +/** + * @brief CALCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_calc_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_CALCEN); +} + +/** + * @brief Get CALCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : calc enable + * @arg 0x0 : calc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_calc_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_CALCEN) == (RCU_AHBSL_CALCEN)); +} + +/** + * @brief USBEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_usb_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_USBEN); +} + +/** + * @brief USBEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_usb_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_USBEN); +} + +/** + * @brief Get USBEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : usb enable + * @arg 0x0 : usb disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_usb_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_USBEN) == (RCU_AHBSL_USBEN)); +} + +/** + * @brief AESEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_aes_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_AESEN); +} + +/** + * @brief AESEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_aes_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_AESEN); +} + +/** + * @brief Get AESEN clock during Sleep mode bit. + * @param rcu RCU InstanceInstance + * @retval The retval can be one of the following values: + * @arg 0x1 : aes enable + * @arg 0x0 : aes disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_aes_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_AESEN) == (RCU_AHBSL_AESEN)); +} + +/** + * @brief CRCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_crc_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN); +} + +/** + * @brief CRCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_crc_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN); +} + +/** + * @brief Get CRCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : crc enable + * @arg 0x0 : crc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_crc_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN) == (RCU_AHBSL_CRCEN)); +} + +/** + * @brief CSUEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_csu_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_CSUEN); +} + +/** + * @brief CSUEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_csu_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_CSUEN); +} + +/** + * @brief Get CSUEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : csu enable + * @arg 0x0 : csu disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_csu_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_CSUEN) == (RCU_AHBSL_CSUEN)); +} + +/** + * @brief KBCUEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_kbcu_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_KBCUEN); +} + +/** + * @brief KBCUEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_kbcu_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_KBCUEN); +} + +/** + * @brief Get KBCUEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : kbcu enable + * @arg 0x0 : kbcu disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_kbcu_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_KBCUEN) == (RCU_AHBSL_KBCUEN)); +} + +/** + * @brief RTCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_rtc_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN); +} + +/** + * @brief RTCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_rtc_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN); +} + +/** + * @brief Get RTCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : rtc enable + * @arg 0x0 : rtc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_rtc_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN) == (RCU_AHBSL_RTCEN)); +} + +/** + * @brief DMA1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_dma1_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN); +} + +/** + * @brief DMA1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_dma1_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN); +} + +/** + * @brief Get DMA1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : dma1 enable + * @arg 0x0 : dma1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_dma1_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN) == (RCU_AHBSL_DMA1EN)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group19 APB1SL + * @{ + */ +/** + * @brief Set RCU_APB1SL Register + * @param rcu RCU Instance + * @param apb1sl + */ +__STATIC_INLINE void md_rcu_set_apb1sl(RCU_TypeDef *rcu, uint32_t apb1sl) +{ + WRITE_REG(rcu->APB1SL, apb1sl); +} + +/** + * @brief Get RCU_APB1SL Register + * @param rcu RCU Instance + * @param apb1sl + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->APB1SL)); +} + +/** + * @brief I2C2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_i2c2_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN); +} + +/** + * @brief I2C2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_i2c2_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN); +} + +/** + * @brief Get I2C2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : i2c2 enable + * @arg 0x0 : i2c2 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_i2c2_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN) == (RCU_APB1SL_I2C2EN)); +} + +/** + * @brief I2C1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_i2c1_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN); +} + +/** + * @brief I2C1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_i2c1_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN); +} + +/** + * @brief Get I2C1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : i2c1 enable + * @arg 0x0 : i2c1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_i2c1_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN) == (RCU_APB1SL_I2C1EN)); +} + +/** + * @brief UART4EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart4_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_UART4EN); +} + +/** + * @brief UART4EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart4_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_UART4EN); +} + +/** + * @brief Get UART4EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart4 enable + * @arg 0x0 : uart4 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart4_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_UART4EN) == (RCU_APB1SL_UART4EN)); +} + +/** + * @brief UART3EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart3_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN); +} + +/** + * @brief UART3EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart3_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN); +} + +/** + * @brief Get UART3EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart3 enable + * @arg 0x0 : uart3 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart3_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN) == (RCU_APB1SL_UART3EN)); +} + +/** + * @brief UART2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart2_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN); +} + +/** + * @brief UART2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart2_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN); +} + +/** + * @brief Get UART2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart2 enable + * @arg 0x0 : uart2 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart2_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN) == (RCU_APB1SL_UART2EN)); +} + +/** + * @brief SPI3EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_spi3_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_SPI3EN); +} + +/** + * @brief SPI3EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_spi3_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SPI3EN); +} + +/** + * @brief Get SPI3EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi3 enable + * @arg 0x0 : spi3 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_spi3_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SPI3EN) == (RCU_APB1SL_SPI3EN)); +} + +/** + * @brief SPI2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_spi2_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN); +} + +/** + * @brief SPI2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_spi2_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN); +} + +/** + * @brief Get SPI2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi2 enable + * @arg 0x0 : spi2 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_spi2_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN) == (RCU_APB1SL_SPI2EN)); +} + +/** + * @brief WWDTEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_wwdt_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN); +} + +/** + * @brief WWDTEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_wwdt_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN); +} + +/** + * @brief Get WWDTEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : wwdt enable + * @arg 0x0 : wwdt disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_wwdt_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN) == (RCU_APB1SL_WWDTEN)); +} + +/** + * @brief BS16T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_bs16t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN); +} + +/** + * @brief BS16T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_bs16t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN); +} + +/** + * @brief Get BS16T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : bs16t1 enable + * @arg 0x0 : bs16t1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_bs16t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN) == (RCU_APB1SL_BS16T1EN)); +} + +/** + * @brief GP16C4T3EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c4t3_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN); +} + +/** + * @brief GP16C4T3EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c4t3_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN); +} + +/** + * @brief Get GP16C4T3EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c4t3 enable + * @arg 0x0 : gp16c4t3 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c4t3_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN) == (RCU_APB1SL_GP16C4T3EN)); +} + +/** + * @brief GP16C4T2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c4t2_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN); +} + +/** + * @brief GP16C4T2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c4t2_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN); +} + +/** + * @brief Get GP16C4T2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c4t2 enable + * @arg 0x0 : gp16c4t2 disable +y */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c4t2_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN) == (RCU_APB1SL_GP16C4T2EN)); +} + +/** + * @brief GP16C4T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c4t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN); +} + +/** + * @brief GP16C4T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c4t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN); +} + +/** + * @brief Get GP16C4T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c4t1 enable + * @arg 0x0 : gp16c4t1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c4t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN) == (RCU_APB1SL_GP16C4T1EN)); +} + +/** + * @brief GP32C4T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp32c4t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN); +} + +/** + * @brief GP32C4T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp32c4t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN); +} + +/** + * @brief Get GP32C4T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp32c4t1 enable + * @arg 0x0 : gp32c4t1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp32c4t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN) == (RCU_APB1SL_GP32C4T1EN)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group20 APB2SL + * @{ + */ +/** + * @brief Set RCU_APB2SL Register + * @param rcu RCU Instance + * @param apb2sl + */ +__STATIC_INLINE void md_rcu_set_apb2sl(RCU_TypeDef *rcu, uint32_t apb2sl) +{ + WRITE_REG(rcu->APB2SL, apb2sl); +} + +/** + * @brief Get RCU_APB2SL Register + * @param rcu RCU Instance + * @param apb2sl + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->APB2SL)); +} + +/** + * @brief CMP clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_cmp_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN); +} + +/** + * @brief CMP clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_cmp_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN); +} + +/** + * @brief Get CMP clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : cmp enable + * @arg 0x0 : cmp disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_cmp_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN) == (RCU_APB2SL_CMPEN)); +} + +/** + * @brief GP16C2T4EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t4_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN); +} + +/** + * @brief GP16C2T4EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t4_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN); +} + +/** + * @brief Get GP16C2T4EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t4 enable + * @arg 0x0 : gp16c2t4 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t4_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN) == (RCU_APB2SL_GP16C2T4EN)); +} + +/** + * @brief GP16C2T3EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t3_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN); +} + +/** + * @brief GP16C2T3EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t3_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN); +} + +/** + * @brief Get GP16C2T3EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t3 enable + * @arg 0x0 : gp16c2t3 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t3_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN) == (RCU_APB2SL_GP16C2T3EN)); +} + +/** + * @brief GP16C2T2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t2_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN); +} + +/** + * @brief GP16C2T2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t2_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN); +} + +/** + * @brief Get GP16C2T2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t2 enable + * @arg 0x0 : gp16c2t2 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t2_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN) == (RCU_APB2SL_GP16C2T2EN)); +} + +/** + * @brief GP16C2T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_gp16c2t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN); +} + +/** + * @brief GP16C2T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_gp16c2t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN); +} + +/** + * @brief Get GP16C2T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t1 enable + * @arg 0x0 : gp16c2t1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_gp16c2t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN) == (RCU_APB2SL_GP16C2T1EN)); +} + +/** + * @brief UART1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_uart1_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN); +} + +/** + * @brief UART1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_uart1_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN); +} + +/** + * @brief Get UART1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart1 enable + * @arg 0x0 : uart1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_uart1_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN) == (RCU_APB2SL_UART1EN)); +} + +/** + * @brief SPI1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_spi1_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN); +} + +/** + * @brief I2S1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_i2s1_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN); +} + +/** + * @brief SPI1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_spi1_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN); +} + +/** + * @brief I2S1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_i2s1_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN); +} + + +/** + * @brief Get SPI1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi1 enable + * @arg 0x0 : spi1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_spi1_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN) == (RCU_APB2SL_SPI1EN)); +} + +/** + * @brief Get I2S1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi1 enable + * @arg 0x0 : spi1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_i2s1_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN) == (RCU_APB2SL_SPI1EN)); +} + +/** + * @brief AD16C4T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ad16c4t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN); +} + +/** + * @brief AD16C4T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ad16c4t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN); +} + +/** + * @brief Get AD16C4T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : ad16c4t1 enable + * @arg 0x0 : ad16c4t1 disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_ad16c4t1_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN) == (RCU_APB2SL_AD16C4T1EN)); +} + +/** + * @brief ADCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_adc_in_sleep_mode(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN); +} + +/** + * @brief ADCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_adc_in_sleep_mode(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN); +} + +/** + * @brief Get ADCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : adc enable + * @arg 0x0 : adc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_adc_in_sleep_mode(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN) == (RCU_APB2SL_ADCEN)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group21 LCON + * @{ + */ +/** + * @brief Set RCU_LCON Register + * @param rcu RCU Instance + * @param lcon + */ +__STATIC_INLINE void md_rcu_set_lcon(RCU_TypeDef *rcu, uint32_t lcon) +{ + WRITE_REG(rcu->LCON, lcon); +} + +/** + * @brief Get RCU_LCON Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_rcu_get_lcon(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_REG(rcu->LCON)); +} + +/** + * @brief Set LOSC bypass mode enabled + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_losc_bypass(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->LCON, RCU_LCON_LOSCBYP); +} + +/** + * @brief Set LOSC bypass mode disabled + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_losc_bypass(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->LCON, RCU_LCON_LOSCBYP); +} + +/** + * @brief Get LOSC bypass mode + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : losc bypass enable + * @arg 0x0 : losc bypass disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_losc_bypass(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->LCON, RCU_LCON_LOSCBYP) == (RCU_LCON_LOSCBYP)); +} + +/** + * @brief Get LOSCRDY clock ready flag + * @note + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_LOSCRDY_NOT_READY + * @arg @ref MD_RCU_LOSCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_losc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->LCON, RCU_LCON_LOSCRDY) == (RCU_LCON_LOSCRDY)); +} + +/** + * @brief Set LOSC enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_losc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->LCON, RCU_LCON_LOSCON); +} + +/** + * @brief Set LOSC disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_losc(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->LCON, RCU_LCON_LOSCON); +} + +/** + * @brief Get LOSC bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : losc enable + * @arg 0x0 : losc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_losc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->LCON, RCU_LCON_LOSCON) == (RCU_LCON_LOSCON)); +} + +/** + * @brief Get LRCRDY clock ready flag + * @note + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_LRCRDY_NOT_READY + * @arg @ref MD_RCU_LRCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_lrc_ready(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->LCON, RCU_LCON_LRCRDY) == (RCU_LCON_LRCRDY)); +} + +/** + * @brief Set LRC enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_lrc(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->LCON, RCU_LCON_LRCON); +} + +/** + * @brief Set LRC disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_lrc(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->LCON, RCU_LCON_LRCON); +} + +/** + * @brief Get LRC clock bit + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : lrc enable + * @arg 0x0 : lrc disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_lrc(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->LCON, RCU_LCON_LRCON) == (RCU_LCON_LRCON)); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group22 RSTF + * @{ + */ +/** + * @brief Set RCU_RSTF Register + * @param rcu RCU Instance + */ +__STATIC_INLINE void md_rcu_set_rstf(RCU_TypeDef *rcu, uint32_t rstf) +{ + WRITE_REG(rcu->RSTF, rstf); +} + +/** + * @brief Get RCU_RSTF Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_rcu_get_rstf(RCU_TypeDef *rcu) +{ + return (uint32_t)READ_REG(rcu->RSTF); +} + +/** + * @brief Get Low power reset flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_wakeup(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RSTF, RCU_RSTF_LPRSTF) == (RCU_RSTF_LPRSTF)); +} + +/** + * @brief Get WWDT reset flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_wwdt(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RSTF, RCU_RSTF_WWDTRSTF) == (RCU_RSTF_WWDTRSTF)); +} + +/** + * @brief Get IWDT reset flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_iwdt(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RSTF, RCU_RSTF_IWDTRSTF) == (RCU_RSTF_IWDTRSTF)); +} + +/** + * @brief Get SW reset flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_software(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RSTF, RCU_RSTF_SWRSTF) == (RCU_RSTF_SWRSTF)); +} + +/** + * @brief Get Option Byte reload reset flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_option_byte_reload(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RSTF, RCU_RSTF_OBLRSTF) == (RCU_RSTF_OBLRSTF)); +} + +/** + * @brief Get NRST external pin reset flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_nrst(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RSTF, RCU_RSTF_NRSTF) == (RCU_RSTF_NRSTF)); +} + +/** + * @brief Get BOR reset flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_bor(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RSTF, RCU_RSTF_BORRSTF) == (RCU_RSTF_BORRSTF)); +} + +/** + * @brief Get POR/PDR reset flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_is_active_flag_por(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->RSTF, RCU_RSTF_PORRSTF) == (RCU_RSTF_PORRSTF)); +} + +/** + * @brief Clear reset flag + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_rcu_clear_flag_reset_flag(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->RSTF, RCU_RSTF_CLRFLG); +} +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group27 CKTRIM + * @{ + */ +/** + * @brief Set RCU_CKTRIM Register + * @param rcu RCU Instance + * @param cktrim + */ +__STATIC_INLINE void md_rcu_set_cktrim(RCU_TypeDef *rcu, uint32_t cktrim) +{ + WRITE_REG(rcu->CKTRIM, cktrim); +} + +/** + * @brief Get RCU_CKTRIM Register + * @param rcu RCU Instance + * @param cktrim + */ +__STATIC_INLINE uint32_t md_rcu_get_cktrim(RCU_TypeDef *rcu) +{ + return (uint32_t)READ_REG(rcu->CKTRIM); +} + +/** + * @brief HRC48 update event + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_trigger_hrc48trim_update(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CKTRIM, RCU_CKTRIM_HRC48UE); +} + +/** + * @brief Set HRC48 calibration value selection + * @param rcu RCU Instance + * @arg @ref MD_RCU_HRC48SEL_OPTIONBYTE + * @arg @ref MD_RCU_HRC48SEL_HRC48TRIM + * @retval None + */ +__STATIC_INLINE void md_rcu_set_hrc48trim_source(RCU_TypeDef *rcu, uint32_t hrc48sel) +{ + MODIFY_REG(rcu->CKTRIM, RCU_CKTRIM_HRC48SEL, hrc48sel << RCU_CKTRIM_HRC48SEL_POS); +} + +/** + * @brief Get HRC48 calibration value selection + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_HRC48SEL_OPTIONBYTE + * @arg @ref MD_RCU_HRC48SEL_HRC48TRIM + */ +__STATIC_INLINE uint32_t md_rcu_get_hrc48trim_source(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CKTRIM, RCU_CKTRIM_HRC48SEL) >> RCU_CKTRIM_HRC48SEL_POS); +} + +/** + * @brief Set HRC calibration value selection + * @param rcu RCU Instance + * @param hrcsel + * @arg @ref MD_RCU_HRCSEL_OPTIONBYTE + * @arg @ref MD_RCU_HRCSEL_HRCTRIM + * @retval None + */ +__STATIC_INLINE void md_rcu_set_hrctrim_source(RCU_TypeDef *rcu, uint32_t hrcsel) +{ + MODIFY_REG(rcu->CKTRIM, RCU_CKTRIM_HRCSEL, hrcsel << RCU_CKTRIM_HRCSEL_POS); +} + +/** + * @brief Get HRC calibration value selection + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_HRCSEL_OPTIONBYTE + * @arg @ref MD_RCU_HRCSEL_HRCTRIM + */ +__STATIC_INLINE uint32_t md_rcu_get_hrctrim_source(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CKTRIM, RCU_CKTRIM_HRCSEL) >> RCU_CKTRIM_HRCSEL_POS); +} + +/** + * @brief Set HRC48 calibration value + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_set_hrc48trim(RCU_TypeDef *rcu, uint32_t hrc48trim) +{ + MODIFY_REG(rcu->CKTRIM, RCU_CKTRIM_HRC48TRIM, (hrc48trim << RCU_CKTRIM_HRC48TRIM_POSS)); +} + +/** + * @brief Get HRC48 calibration value + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rcu_get_hrc48trim(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CKTRIM, RCU_CKTRIM_HRC48TRIM) >> RCU_CKTRIM_HRC48TRIM_POSS); +} + +/** + * @brief Set HRC calibration value + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_set_hrctrim(RCU_TypeDef *rcu, uint32_t hrctrim) +{ + MODIFY_REG(rcu->CKTRIM, RCU_CKTRIM_HRCTRIM, (hrctrim << RCU_CKTRIM_HRCTRIM_POSS)); +} + +/** + * @brief Get HRC calibration value + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rcu_get_hrctrim(RCU_TypeDef *rcu) +{ + return (uint32_t)(READ_BIT(rcu->CKTRIM, RCU_CKTRIM_HRCTRIM) >> RCU_CKTRIM_HRCTRIM_POSS); +} + +/** + * @} + */ + +/** @defgroup MD_RCU_Public_Functions_Group1 Initialization + * @{ + */ +void md_rcu_pll0_init(RCU_TypeDef *, md_rcu_init_typedef *); +void md_rcu_sys_init(RCU_TypeDef *, md_rcu_init_typedef *); +void md_tick_waitms_rcu(uint8_t Unit, uint16_t msCnt); + +void md_rcu_hrc_software_trim(RCU_TypeDef *, uint8_t); +void md_rcu_hrc_disable_software_trim(RCU_TypeDef *); +void md_rcu_hrc48_software_trim(RCU_TypeDef *, uint16_t); +void md_rcu_hrc48_disable_software_trim(RCU_TypeDef *); +uint16_t md_rcu_get_hrc_option_trim_value(RCU_TypeDef *); +uint16_t md_rcu_get_hrc48_option_trim_value(RCU_TypeDef *); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_rtc.c b/os/common/ext/CMSIS/ES32/FS026/md/md_rtc.c new file mode 100644 index 00000000000..aba2e996c59 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_rtc.c @@ -0,0 +1,296 @@ +/********************************************************************************** + * + * @file md_rtc.c + * @brief md_rtc C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "system_fs026.h" +#include "md_rtc.h" +#include "md_rcu.h" +/** @addtogroup Micro_Driver + * @{ + */ + + +/** @defgroup RTC RTC + * @brief RTC micro driver + * @{ + */ + + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_RTC_Public_Functions RTC Public Functions + * @{ + */ + +/** + * @brief De-initialize RTC registers (Registers restored to their default values). + * @param rtc RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: CRC registers are de-initialized + * - ERROR: CRC registers are not de-initialized + */ +ErrorStatus md_rtc_deinit(RTC_TypeDef *rtc) +{ + ErrorStatus status = SUCCESS; + + if (rtc == RTC) + { + md_rtc_disable_rtc(rtc); + + /* Force CRC reset */ + md_rcu_enable_rtc_reset(RCU); + + /* Release CRC reset */ + md_rcu_disable_rtc_reset(RCU); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param rtc RTC Instance + * @param RTC_InitStruct pointer to a @ref md_rtc_inittypedef structure that contains + * the configuration information for the RTC peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus md_rtc_init(RTC_TypeDef *rtc, md_rtc_inittypedef *RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + md_rtc_set_scale(rtc, RTC_InitStruct->Scale); + md_rtc_set_prescale(rtc, RTC_InitStruct->Pre_Scale); + md_rtc_set_ref_clock(rtc, RTC_InitStruct->Clock_Sel); + + status = SUCCESS; + + return status; +} + +/** + * @brief Set each @ref md_rtc_inittypedef field to default value. + * @param RTC_InitStruct pointer to a @ref md_rtc_inittypedef structure which will be initialized. + * @retval None + */ +void md_rtc_structinit(md_rtc_inittypedef *RTC_InitStruct) +{ + /* Set RTC_InitStruct fields to default values */ + RTC_InitStruct->Scale = 0xFF; + RTC_InitStruct->Pre_Scale = 0x7F; + RTC_InitStruct->Clock_Sel = MD_RTC_CTRL_CKSEL_LRC; +} + +/** + * @brief Set the RTC current time. + * @param rtc RTC Instance + * @param RTC_TimeStruct pointer to a md_rtc_timetypedef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus md_rtc_time_init(RTC_TypeDef *rtc, md_rtc_timetypedef *RTC_TimeStruct) +{ + ErrorStatus status = ERROR; + + md_rtc_set_date_weekday(rtc, RTC_TimeStruct->Week); + md_rtc_set_time_hour(rtc, RTC_TimeStruct->Hour); + md_rtc_set_time_minute(rtc, RTC_TimeStruct->Min); + md_rtc_set_time_second(rtc, RTC_TimeStruct->Sec); + + status = SUCCESS; + + return status; +} + +/** + * @brief Set each @ref md_rtc_timetypedef field to default value (Time = 01w:00h:00min:00sec). + * @param RTC_TimeStruct pointer to a @ref md_rtc_timetypedef structure which will be initialized. + * @retval None + */ +void md_rtc_time_structinit(md_rtc_timetypedef *RTC_TimeStruct) +{ + /* Time = 01w:00h:00min:00sec */ + RTC_TimeStruct->Week = 1U; + RTC_TimeStruct->Hour = 0U; + RTC_TimeStruct->Min = 0U; + RTC_TimeStruct->Sec = 0U; +} + +/** + * @brief Set the RTC current date. + * @param rtc RTC Instance + * @param RTC_DateStruct pointer to a md_rtc_datetypedef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus md_rtc_date_init(RTC_TypeDef *rtc, md_rtc_datetypedef *RTC_DateStruct) +{ + ErrorStatus status = ERROR; + + md_rtc_set_date_year(rtc, RTC_DateStruct->Year); + md_rtc_set_date_month(rtc, RTC_DateStruct->Month); + md_rtc_set_date_day(rtc, RTC_DateStruct->Date); + + status = SUCCESS; + + return status; +} + +/** + * @brief Set each @ref md_rtc_datetypedef field to default value (Date = xx00 01 01 ). + * @param RTC_DateStruct pointer to a @ref md_rtc_datetypedef structure which will be initialized. + * @retval None + */ +void md_rtc_date_structinit(md_rtc_datetypedef *RTC_DateStruct) +{ + /* Date = xx00 01 01 */ + RTC_DateStruct->Year = 0U; + RTC_DateStruct->Month = 1U; + RTC_DateStruct->Date = 1U; +} + +/** + * @brief Set the RTC Alarm. + * @param rtc RTC Instance + * @param RTC_AlarmStruct pointer to a md_rtc_alarmtypedef structure that contains + * the alarm configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus md_rtc_alarm_init(RTC_TypeDef *rtc, md_rtc_alarmtypedef *RTC_AlarmStruct) +{ + ErrorStatus status = ERROR; + + md_rtc_set_alarm_weekday(rtc, RTC_AlarmStruct->AlarmWeek); + md_rtc_set_alarm_hour(rtc, RTC_AlarmStruct->AlarmHour); + md_rtc_set_alarm_minute(rtc, RTC_AlarmStruct->AlarmMin); + md_rtc_set_alarm_second(rtc, RTC_AlarmStruct->AlarmSec); + + md_rtc_set_alarm_year(rtc, RTC_AlarmStruct->AlarmYear); + md_rtc_set_alarm_month(rtc, RTC_AlarmStruct->AlarmMonth); + md_rtc_set_alarm_day(rtc, RTC_AlarmStruct->AlarmDate); + + md_rtc_set_alarmen(rtc, RTC_AlarmStruct->AlarmMask); + md_rtc_set_ier(rtc, RTC_AlarmStruct->AlarmInterrupt); + + status = SUCCESS; + + return status; +} + +/** + * @brief Set each @ref md_rtc_alarmenabletypedef of ALARMA field to default value. + * @param RTC_AlarmEnableStruct pointer to a @ref md_rtc_alarmenabletypedef structure which will be initialized. + * @retval None + */ +void md_rtc_alarm_structinit(md_rtc_alarmtypedef *RTC_AlarmStruct) +{ + RTC_AlarmStruct->AlarmWeek = 1U; + RTC_AlarmStruct->AlarmHour = 0U; + RTC_AlarmStruct->AlarmMin = 0U; + RTC_AlarmStruct->AlarmSec = 0U; + + RTC_AlarmStruct->AlarmYear = 0U; + RTC_AlarmStruct->AlarmMonth = 1U; + RTC_AlarmStruct->AlarmDate = 1U; + + RTC_AlarmStruct->AlarmMask = MD_RTC_ALEN_NONE; +} + +/** + * @brief Enters the RTC Initialization mode. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is closed + * - ERROR: Not applicable + */ +ErrorStatus md_rtc_disable(RTC_TypeDef *rtc) +{ + md_rtc_disable_rtc(rtc); + + return SUCCESS; +} + +/** + * @brief Exit the RTC Initialization mode. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC starts + * - ERROR: Not applicable + */ +ErrorStatus md_rtc_enable(RTC_TypeDef *rtc) +{ + md_rtc_enable_rtc(rtc); + + return SUCCESS; +} + + + +/** @addtogroup MD_RTC_Init + * @{ + */ + + +/** + * @} MD_RTC_Init + */ + + +/** + * @} MD_RTC_Public_Functions + */ + +/** + * @} RTC + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_rtc.h b/os/common/ext/CMSIS/ES32/FS026/md/md_rtc.h new file mode 100644 index 00000000000..43fd8eb4e89 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_rtc.h @@ -0,0 +1,2929 @@ +/********************************************************************************** + * + * @file md_rtc.h + * @brief header file of md_rtc.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 24 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_RTC_H__ +#define __MD_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_RTC RTC + * @brief RTC micro driver + * @{ + */ + +/** @defgroup MD_RTC_Pubulic_Types RTC Pubulic Types + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t Scale; /*!< Specifies the RTC count frequency division. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF*/ + + uint32_t Pre_Scale; /*!< Specifies the RTC count pre-divider. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F*/ + + uint32_t Clock_Sel; /*!< Specifies the RTC clock source selection. + This parameter can be a value of @ref MD_RTC_CTRL_CKSEL_LOSC + @ref MD_RTC_CTRL_CKSEL_LRC */ +} md_rtc_inittypedef; + +/** + * @brief RTC Time structures definition + */ +typedef struct +{ + uint32_t Week; /*!< Specifies the RTC Weekday. + This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x7*/ + + uint32_t Hour; /*!< Specifies the RTC Hour. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x23*/ + + uint32_t Min; /*!< Specifies the RTC Minute. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59*/ + + uint32_t Sec; /*!< Specifies the RTC Second. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59*/ +} md_rtc_timetypedef; + +/** + * @brief RTC Date structures definition + */ +typedef struct +{ + uint32_t Year; /*!< Specifies the RTC Year. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x99*/ + + uint32_t Month; /*!< Specifies the RTC Month. + This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x12*/ + + uint32_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x31*/ + +} md_rtc_datetypedef; + + +/** + * @brief RTC Alarm structures definition + */ +typedef struct +{ + uint32_t AlarmYear; /*!< Specifies the RTC Alarm Year. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x99*/ + + uint32_t AlarmMonth; /*!< Specifies the RTC Alarm Month. + This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x12*/ + + uint32_t AlarmDate; /*!< Specifies the RTC Alarm Date. + This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x31*/ + + uint32_t AlarmWeek; /*!< Specifies the RTC Alarm Weekday. + This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x7*/ + + uint32_t AlarmHour; /*!< Specifies the RTC Alarm Hour. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x23*/ + + uint32_t AlarmMin; /*!< Specifies the RTC Alarm Minute. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59*/ + + uint32_t AlarmSec; /*!< Specifies the RTC Alarm Second. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59*/ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref MD_RTC_ALEN_NONE + @ref MD_RTC_ALEN_YEAR + @ref MD_RTC_ALEN_MONTH + @ref MD_RTC_ALEN_DATE + @ref MD_RTC_ALEN_WEEK + @ref MD_RTC_ALEN_HOUR + @ref MD_RTC_ALEN_MIN + @ref MD_RTC_ALEN_SEC + @ref MD_RTC_ALEN_ALL */ + uint32_t AlarmInterrupt; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref MD_RTC_EVENT_AMALL + @ref MD_RTC_EVENT_AYEAR + @ref MD_RTC_EVENT_AMONTH + @ref MD_RTC_EVENT_ADATE + @ref MD_RTC_EVENT_AWEEK + @ref MD_RTC_EVENT_AHOUR + @ref MD_RTC_EVENT_AMIN + @ref MD_RTC_EVENT_ASEC */ + +} md_rtc_alarmtypedef; +/** + * @} + */ + + +/** @defgroup MD_RTC_Public_Macros RTC Public Macros + * @{ + */ + + +/** + * @brief MD_RTC_CTRL_CKSEL_ RTC Clock Source Selection + */ +#define MD_RTC_CTRL_CKSEL_LOSC (0X00000001UL) /** @brief LOSC oscillator clock used as RTC clock */ +#define MD_RTC_CTRL_CKSEL_LRC (0x00000002UL) /** @brief LRC oscillator clock used as RTC clock */ + +/** + * @brief MD_RTC_WKUP_WKSCAL RTC Wakeup Counter Scale Value + */ +#define MD_RTC_WKUP_WKSCAL_DIV1 (0x00000000UL) /** @brief Divide 1, wakeup counter will count each second. */ +#define MD_RTC_WKUP_WKSCAL_DIV2 (0X00000001UL) /** @brief Divide 2, wakeup counter will count each 1/2 second. */ +#define MD_RTC_WKUP_WKSCAL_DIV4 (0x00000002UL) /** @brief Divide 4, wakeup counter will count each 1/4 second. */ +#define MD_RTC_WKUP_WKSCAL_DIV8 (0X00000003UL) /** @brief Divide 8, wakeup counter will count each 1/8 second. */ +#define MD_RTC_WKUP_WKSCAL_DIV16 (0X00000004UL) /** @brief Divide 16, wakeup counter will count each 1/16 second. */ + +/** + * @brief MD_RTC_WKUP_WKSEL RTC Wakeup Counter Events Select + */ +#define MD_RTC_WKUP_WKSEL_OFF (0x00000000UL) /** @brief OFF */ +#define MD_RTC_WKUP_WKSEL_RTC (0X00000001UL) /** @brief Start counter when RTC start. */ +#define MD_RTC_WKUP_WKSEL_SLEEP (0x00000002UL) /** @brief Start counter when receive sleep flag. */ + +/** + * @brief MD_RTC_CALIB_MODE_ RTC Clock Calibration Mode + */ +#define MD_RTC_CON_MODE_INCR (0x00000000UL) /** @brief Increase calibration value when match calibration cycle. */ +#define MD_RTC_CON_MODE_DECR (0X00000001UL) /** @brief DMA Decrease calibration value when match calibration cycle. */ + +/** + * @brief MD_RTC_STAT_SYNDONE RTC Calendar Synchronization status + */ +#define MD_RTC_STA_SYNDONE_UNDER (0x00000000UL) /** @brief RTC is under Synchronization procedure */ +#define MD_RTC_STA_SYNDONE_CMP (0X00000001UL) /** @brief RTC Synchronization procedure is Completed */ + +/** + * @brief MD_RTC_BKEN_BKEN Read RTC Backup Register Enable + */ +#define MD_RTC_BKEN_RTC_REGISTER (0x00000000UL) /** @brief Read RTCTIME & RTCCAL From control register. */ +#define MD_RTC_BKEN_BACKUP_REGISTER (0X00000001UL) /** @brief Read RTCTIME & RTCCAL From backup register. */ + +/** + * @brief MD_RTC_ALEN Alarm switch register + */ +#define MD_RTC_ALEN_NONE 0x00000000U /** @brief None alarm. */ +#define MD_RTC_ALEN_YEAR (RTC_ALEN_YEAR) /** @brief Year alarm switch. */ +#define MD_RTC_ALEN_MONTH (RTC_ALEN_MONTH) /** @brief Month alarm switch.*/ +#define MD_RTC_ALEN_DATE (RTC_ALEN_DATE) /** @brief Date alarm switch. */ +#define MD_RTC_ALEN_WEEK (RTC_ALEN_WEEK) /** @brief Week alarm switch. */ +#define MD_RTC_ALEN_HOUR (RTC_ALEN_HOUR) /** @brief Hour alarm switch. */ +#define MD_RTC_ALEN_MIN (RTC_ALEN_MIN) /** @brief Min alarm switch. */ +#define MD_RTC_ALEN_SEC (RTC_ALEN_SEC) /** @brief Sec alarm switch. */ +#define MD_RTC_ALEN_ALL (RTC_ALEN_YEAR | RTC_ALEN_MONTH | RTC_ALEN_DATE | RTC_ALEN_WEEK | RTC_ALEN_HOUR | RTC_ALEN_MIN | RTC_ALEN_SEC) /** @brief All alarm switch. */ + +/** + * @brief MD_RTC_EVENT RTC_TRIG/RTC_IER/RTC_IDR/RTC_IVS/RTC_RIF/RTC_IFM/RTC_ICR + */ +#define MD_RTC_EVENT_WKTM (1 << 16 ) /** @brief The RTC wake-up counter has finished counting. */ +#define MD_RTC_EVENT_F1HZ (1 << 15 ) /** @brief RTC 1Hz. */ +#define MD_RTC_EVENT_RYEAR (1 << 14 ) /** @brief RTC cross the century. */ +#define MD_RTC_EVENT_RMON (1 << 13 ) /** @brief RTC cross the year. */ +#define MD_RTC_EVENT_RDATE (1 << 12 ) /** @brief RTC cross the month. */ +#define MD_RTC_EVENT_RWEEK (1 << 11 ) /** @brief RTC cross the week. */ +#define MD_RTC_EVENT_RHOUR (1 << 10 ) /** @brief RTC cross the day. */ +#define MD_RTC_EVENT_RMIN (1 << 9 ) /** @brief RTC cross the hour. */ +#define MD_RTC_EVENT_RSEC (1 << 8 ) /** @brief RTC cross the min. */ +#define MD_RTC_EVENT_AMALL (1 << 7 ) /** @brief RTC full alarm clock. */ +#define MD_RTC_EVENT_AYEAR (1 << 6 ) /** @brief RTC year alarm clock. */ +#define MD_RTC_EVENT_AMONTH (1 << 5 ) /** @brief RTC month alarm clock. */ +#define MD_RTC_EVENT_ADATE (1 << 4 ) /** @brief RTC date alarm clock. */ +#define MD_RTC_EVENT_AWEEK (1 << 3 ) /** @brief RTC week alarm clock. */ +#define MD_RTC_EVENT_AHOUR (1 << 2 ) /** @brief RTC hour alarm clock. */ +#define MD_RTC_EVENT_AMIN (1 << 1 ) /** @brief RTC min alarm clock. */ +#define MD_RTC_EVENT_ASEC (1 << 0 ) /** @brief RTC sec alarm clock. */ + +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions RTC Public Functions + * @{ + */ + +/** @defgroup MD_RTC_Public_Functions_Group2 CTRL + * @{ + */ +/** + * @brief Set RTC_CTRL Register + * @param rtc RTC Instance + * @param ctrl + * @retval None + */ +__STATIC_INLINE void md_rtc_set_contrl(RTC_TypeDef *rtc, uint32_t ctrl) +{ + WRITE_REG(RTC->CTRL, ctrl); +} + +/** + * @brief Get RTC_CTRL Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_contrl(RTC_TypeDef *rtc) +{ + return (uint32_t) READ_REG(RTC->CTRL); +} + +/** + * @brief Set RTC Clock Counter Scale + * @param rtc RTC Instance + * @param scale Max divider of This counter is (SCALE+1). + * @retval None + */ +__STATIC_INLINE void md_rtc_set_scale(RTC_TypeDef *rtc, uint32_t scale) +{ + MODIFY_REG(rtc->CTRL, RTC_CTRL_SCALE, (scale << RTC_CTRL_SCALE_POSS)); +} + +/** + * @brief Get RTC Clock Counter Scale + * @param rtc RTC Instance + * @retval Max divider of This counter is (SCALE+1). + */ +__STATIC_INLINE uint32_t md_rtc_get_scale(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->CTRL, RTC_CTRL_SCALE) >> RTC_CTRL_SCALE_POSS); +} + +/** + * @brief Set RTC Clock Counter Prescale + * @param rtc RTC Instance + * @param pscale Max divider of This counter is (PSCALE+1). + * @retval None + */ +__STATIC_INLINE void md_rtc_set_prescale(RTC_TypeDef *rtc, uint32_t pscale) +{ + MODIFY_REG(rtc->CTRL, RTC_CTRL_PSCALE, (pscale << RTC_CTRL_PSCALE_POSS)); +} + +/** + * @brief Get RTC Clock Counter Prescale + * @param rtc RTC Instance + * @retval Max divider of This counter is (PSCALE+1). + */ +__STATIC_INLINE uint32_t md_rtc_get_prescale(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->CTRL, RTC_CTRL_PSCALE) >> RTC_CTRL_PSCALE_POSS); +} + +/** + * @brief Set RTC Clock Source Selection + * @param rtc RTC Instance + * @param cksel This parameter can be one of the following values: + * @arg @ref MD_RTC_CTRL_CKSEL_LOSC + * @arg @ref MD_RTC_CTRL_CKSEL_LRC + * @retval None + */ +__STATIC_INLINE void md_rtc_set_ref_clock(RTC_TypeDef *rtc, uint32_t cksel) +{ + MODIFY_REG(rtc->CTRL, RTC_CTRL_CKSEL, cksel << RTC_CTRL_CKSEL_POSS); +} +/** + * @brief Get RTC Clock Source Selection + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RTC_CTRL_CKSEL_LOSC + * @arg @ref MD_RTC_CTRL_CKSEL_LRC + */ +__STATIC_INLINE uint32_t md_rtc_get_ref_clock(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->CTRL, RTC_CTRL_CKSEL) >> RTC_CTRL_CKSEL_POSS); +} +/** + * @brief Set RTC Counter Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_rtc(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->CTRL, RTC_CTRL_RTCEN); +} + +/** + * @brief Set RTC Counter Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_rtc(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->CTRL, RTC_CTRL_RTCEN); +} + +/** + * @brief Get Enable or Disable + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_rtc(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->CTRL, RTC_CTRL_RTCEN) == (RTC_CTRL_RTCEN)); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group3 WKUP + * @{ + */ +/** + * @brief Set RTC_WKUP Register + * @param rtc RTC Instance + * @param ctrl + * @retval None + */ +__STATIC_INLINE void md_rtc_set_wakeup(RTC_TypeDef *rtc, uint32_t wkup) +{ + WRITE_REG(RTC->WKUP, wkup); +} + +/** + * @brief Get RTC_WKUP Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_wakeup(RTC_TypeDef *rtc) +{ + return (uint32_t) READ_REG(RTC->WKUP); +} + +/** + * @brief Set RTC Wakeup Counter Scale Value + * @param rtc RTC Instance + * @param wkscal This parameter can be one of the following values: + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV1 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV2 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV4 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV8 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV16 + * @retval None + */ +__STATIC_INLINE void md_rtc_set_wakeup_count_clock(RTC_TypeDef *rtc, uint32_t wkscal) +{ + MODIFY_REG(rtc->WKUP, RTC_WKUP_WKSCAL, wkscal << RTC_WKUP_WKSCAL_POSS); +} +/** + * @brief Get RTC Wakeup Counter Scale Value + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV1 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV2 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV4 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV8 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV16 + */ +__STATIC_INLINE uint32_t md_rtc_get_wakeup_count_clock(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->WKUP, RTC_WKUP_WKSCAL) >> RTC_WKUP_WKSCAL_POSS); +} +/** + * @brief Set RTC Wakeup Counter Events Select + * @param rtc RTC Instance + * @param wksel This parameter can be one of the following values: + * @arg @ref MD_RTC_WKUP_WKSEL_OFF + * @arg @ref MD_RTC_WKUP_WKSEL_RTC + * @arg @ref MD_RTC_WKUP_WKSEL_SLEEP + * @retval None + */ +__STATIC_INLINE void md_rtc_set_wakeup_count_event(RTC_TypeDef *rtc, uint32_t wksel) +{ + MODIFY_REG(rtc->WKUP, RTC_WKUP_WKSEL, wksel << RTC_WKUP_WKSEL_POSS); +} +/** + * @brief Get RTC Wakeup Counter Events Select + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RTC_WKUP_WKSEL_OFF + * @arg @ref MD_RTC_WKUP_WKSEL_RTC + * @arg @ref MD_RTC_WKUP_WKSEL_SLEEP + */ +__STATIC_INLINE uint32_t md_rtc_get_wakeup_count_event(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->WKUP, RTC_WKUP_WKSEL) >> RTC_WKUP_WKSEL_POSS); +} +/** + * @brief Set RTC Wakeup Counter setting value + * @param rtc RTC Instance + * @param wkcal Max value is WKCAL seconds + * @retval None + */ +__STATIC_INLINE void md_rtc_set_wakeup_count_reload(RTC_TypeDef *rtc, uint32_t wkcal) +{ + MODIFY_REG(rtc->WKUP, RTC_WKUP_WKCAL, wkcal); +} +/** + * @brief Get RTC Wakeup Counter setting value + * @param rtc RTC Instance + * @retval Max value is WKCAL seconds + */ +__STATIC_INLINE uint32_t md_rtc_get_wakeup_count_reload(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->WKUP, RTC_WKUP_WKCAL)); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group4 TIME + * @{ + */ +/** + * @brief Set RTC_TIME Register + * @param rtc RTC Instance + * @param ctrl + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time(RTC_TypeDef *rtc, uint32_t time) +{ + WRITE_REG(RTC->TIME, time); +} + +/** + * @brief Get RTC_TIME Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_time(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_REG(RTC->TIME)); +} + +/** + * @brief Set Week Value + * @param rtc RTC Instance + * @param week value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_date_weekday(RTC_TypeDef *rtc, uint32_t week) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_WEEK, (week << RTC_TIME_WEEK_POSS)); +} +/** + * @brief Get Week Value + * @param rtc RTC Instance + * @retval Week value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_date_weekday(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->TIME, RTC_TIME_WEEK) >> RTC_TIME_WEEK_POSS); +} + +/** + * @brief Set Hour Value + * @param rtc RTC Instance + * @param hour Hour value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_hour(RTC_TypeDef *rtc, uint32_t hour) +{ + MODIFY_REG(rtc->TIME, (RTC_TIME_HOUR_T | RTC_TIME_HOUR_U), (hour << RTC_TIME_HOUR_U_POSS)); +} + +/** + * @brief Get Hour Value + * @param rtc RTC Instance + * @retval Hour value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_time_hour(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->TIME, (RTC_TIME_HOUR_T | RTC_TIME_HOUR_U)) >> RTC_TIME_HOUR_U_POSS); +} + +/** + * @brief Set Minute Value + * @param rtc RTC Instance + * @param min Minute value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_minute(RTC_TypeDef *rtc, uint32_t min) +{ + MODIFY_REG(rtc->TIME, (RTC_TIME_MIN_T | RTC_TIME_MIN_U), (min << RTC_TIME_MIN_U_POSS)); +} +/** + * @brief Get Minute Value + * @param rtc RTC Instance + * @retval Minute value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_time_minute(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->TIME, (RTC_TIME_MIN_T | RTC_TIME_MIN_U)) >> RTC_TIME_MIN_U_POSS); +} + +/** + * @brief Set Second Value + * @param rtc RTC Instance + * @param sec Second value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_second(RTC_TypeDef *rtc, uint32_t sec) +{ + MODIFY_REG(rtc->TIME, (RTC_TIME_SEC_T | RTC_TIME_SEC_U), (sec << RTC_TIME_SEC_U_POSS)); +} + +/** + * @brief Get Second Value + * @param rtc RTC Instance + * @retval Second value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_time_second(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->TIME, (RTC_TIME_SEC_T | RTC_TIME_SEC_U)) >> RTC_TIME_SEC_U_POSS); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group5 CAL + * @{ + */ +/** + * @brief Set RTC_CAL Register + * @param rtc RTC Instance + * @param ctrl + * @retval None + */ +__STATIC_INLINE void md_rtc_set_date(RTC_TypeDef *rtc, uint32_t cal) +{ + WRITE_REG(RTC->CAL, cal); +} + +/** + * @brief Get RTC_CAL Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_date(RTC_TypeDef *rtc) +{ + return (uint32_t) READ_REG(RTC->CAL); +} + +/** + * @brief Set Year Value + * @param rtc RTC Instance + * @param year Year value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_date_year(RTC_TypeDef *rtc, uint32_t year) +{ + MODIFY_REG(rtc->CAL, (RTC_CAL_YEAR_T | RTC_CAL_YEAR_U), (year << RTC_CAL_YEAR_U_POSS)); +} + +/** + * @brief Get Year Value + * @param rtc RTC Instance + * @retval Year value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_date_year(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->CAL, (RTC_CAL_YEAR_T | RTC_CAL_YEAR_U)) >> RTC_CAL_YEAR_U_POSS); +} + +/** + * @brief Set Month Value + * @param rtc RTC Instance + * @param mon Month value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_date_month(RTC_TypeDef *rtc, uint32_t mon) +{ + MODIFY_REG(rtc->CAL, (RTC_CAL_MON_T | RTC_CAL_MON_U), (mon << RTC_CAL_MON_U_POSS)); +} + +/** + * @brief Get Month Value + * @param rtc RTC Instance + * @retval Month value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_date_month(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->CAL, (RTC_CAL_MON_T | RTC_CAL_MON_U)) >> RTC_CAL_MON_U_POSS); +} + +/** + * @brief Set Date Value + * @param rtc RTC Instance + * @param date Date value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_date_day(RTC_TypeDef *rtc, uint32_t date) +{ + MODIFY_REG(rtc->CAL, (RTC_CAL_DATE_T | RTC_CAL_DATE_U), (date << RTC_CAL_DATE_U_POSS)); +} +/** + * @brief Get Date Value + * @param rtc RTC Instance + * @retval Date value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_date_day(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->CAL, (RTC_CAL_DATE_T | RTC_CAL_DATE_U)) >> RTC_CAL_DATE_U_POSS); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group6 CALIB + * @{ + */ +/** + * @brief Set RTC_CALIB Register + * @param rtc RTC Instance + * @param ctrl + * @retval None + */ +__STATIC_INLINE void md_rtc_set_calibration(RTC_TypeDef *rtc, uint32_t calib) +{ + WRITE_REG(RTC->CALIB, calib); +} + +/** + * @brief Get RTC_CALIB Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_calibration(RTC_TypeDef *rtc) +{ + return (uint32_t) READ_REG(RTC->CALIB); +} + +/** + * @brief Set RTC 1Hz Calibration value + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_set_calibration_value(RTC_TypeDef *rtc, uint32_t calib) +{ + MODIFY_REG(rtc->CALIB, RTC_CALIB_CALIB, (calib << RTC_CALIB_CALIB_POSS)); +} +/** + * @brief Get RTC 1Hz Calibration value + * @param rtc RTC Instance + */ +__STATIC_INLINE uint32_t md_rtc_get_calibration_value(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->CALIB, RTC_CALIB_CALIB) >> RTC_CALIB_CALIB_POSS); +} + +/** + * @brief Set RTC Clock Calibration Mode + * @param rtc RTC Instance + * @param mode can be one of the following values: + * @arg @ref MD_RTC_CON_MODE_INCR + * @arg @ref MD_RTC_CON_MODE_DECR + * @retval None + */ +__STATIC_INLINE void md_rtc_set_calibration_mode(RTC_TypeDef *rtc, uint32_t mode) +{ + MODIFY_REG(rtc->CALIB, RTC_CALIB_MODE, mode << RTC_CALIB_MODE_POS); +} +/** + * @brief Get RTC Clock Calibration Mode + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RTC_CON_MODE_INCR + * @arg @ref MD_RTC_CON_MODE_DECR + */ +__STATIC_INLINE uint32_t md_rtc_get_calibration_mode(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->CALIB, RTC_CALIB_MODE) >> RTC_CALIB_MODE_POS); +} + +/** + * @brief Set RTC Calibration enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_calibration(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->CALIB, RTC_CALIB_CALIBEN); +} + +/** + * @brief Set RTC Calibration disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_calibration(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->CALIB, RTC_CALIB_CALIBEN); +} + +/** + * @brief Get RTC Calibration enable or disable + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_calibration(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->CALIB, RTC_CALIB_CALIBEN) == (RTC_CALIB_CALIBEN)); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group7 ALTIME + * @{ + */ +/** + * @brief Set RTC_ALTIME Register + * @param rtc RTC Instance + * @param ctrl + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alarm_time(RTC_TypeDef *rtc, uint32_t altime) +{ + WRITE_REG(RTC->ALTIME, altime); +} + +/** + * @brief Get RTC_ALTIME Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_alarm_time(RTC_TypeDef *rtc) +{ + return (uint32_t) READ_REG(RTC->ALTIME); +} + +/** + * @brief Set Alarm Week Value + * @param rtc RTC Instance + * @param week Alarm Week value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alarm_weekday(RTC_TypeDef *rtc, uint32_t week) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_WEEK, (week << RTC_ALTIME_WEEK_POSS)); +} + +/** + * @brief Get Alarm Week Value + * @param rtc RTC Instance + * @retval Alarm Week value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_alarm_weekday(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->ALTIME, RTC_ALTIME_WEEK) >> RTC_ALTIME_WEEK_POSS); +} + +/** + * @brief Set Alarm Hour Value + * @param rtc RTC Instance + * @param hour Alarm Hour value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alarm_hour(RTC_TypeDef *rtc, uint32_t hour) +{ + MODIFY_REG(rtc->ALTIME, (RTC_ALTIME_HOUR_T | RTC_ALTIME_HOUR_U), (hour << RTC_ALTIME_HOUR_U_POSS)); +} + +/** + * @brief Get Alarm Hour Value + * @param rtc RTC Instance + * @retval Alarm Hour value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_alarm_hour(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->ALTIME, (RTC_ALTIME_HOUR_T | RTC_ALTIME_HOUR_U)) >> RTC_ALTIME_HOUR_U_POSS); +} + +/** + * @brief Set Alarm Minute Value + * @param rtc RTC Instance + * @param min Alarm Minute value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alarm_minute(RTC_TypeDef *rtc, uint32_t min) +{ + MODIFY_REG(rtc->ALTIME, (RTC_ALTIME_MIN_T | RTC_ALTIME_MIN_U), (min << RTC_ALTIME_MIN_U_POSS)); +} + +/** + * @brief Get Alarm Minute Value + * @param rtc RTC Instance + * @retval Alarm Minute value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_alarm_minute(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->ALTIME, (RTC_ALTIME_MIN_T | RTC_ALTIME_MIN_U)) >> RTC_ALTIME_MIN_U_POSS); +} + +/** + * @brief Set Alarm Second Value + * @param rtc RTC Instance + * @param sec Alarm Second value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alarm_second(RTC_TypeDef *rtc, uint32_t sec) +{ + MODIFY_REG(rtc->ALTIME, (RTC_ALTIME_SEC_T | RTC_ALTIME_SEC_U), (sec << RTC_ALTIME_SEC_U_POSS)); +} + +/** + * @brief Get Alarm Second Value + * @param rtc RTC Instance + * @retval Alarm Second value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_alarm_second(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->ALTIME, (RTC_ALTIME_SEC_T | RTC_ALTIME_SEC_U)) >> RTC_ALTIME_SEC_U_POSS); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group8 ALCAL + * @{ + */ +/** + * @brief Set RTC_ALCAL Register + * @param rtc RTC Instance + * @param ctrl + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alarm_date(RTC_TypeDef *rtc, uint32_t alcal) +{ + WRITE_REG(RTC->ALCAL, alcal); +} + +/** + * @brief Get RTC_ALCAL Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_alarm_date(RTC_TypeDef *rtc) +{ + return (uint32_t) READ_REG(RTC->ALCAL); +} + +/** + * @brief Set Alarm Year Value + * @param rtc RTC Instance + * @param year Alarm Year value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alarm_year(RTC_TypeDef *rtc, uint32_t year) +{ + MODIFY_REG(rtc->ALCAL, (RTC_ALCAL_YEAR_T | RTC_ALCAL_YEAR_U), (year << RTC_ALCAL_YEAR_U_POSS)); +} + +/** + * @brief Get Alarm Year Value + * @param rtc RTC Instance + * @retval Alarm Year value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_alarm_year(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->ALCAL, (RTC_ALCAL_YEAR_T | RTC_ALCAL_YEAR_U)) >> RTC_ALCAL_YEAR_U_POSS); +} + + +/** + * @brief Set Alarm Month Value + * @param rtc RTC Instance + * @param mon Alarm Month value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alarm_month(RTC_TypeDef *rtc, uint32_t mon) +{ + MODIFY_REG(rtc->ALCAL, (RTC_ALCAL_MON_T | RTC_ALCAL_MON_U), (mon << RTC_ALCAL_MON_U_POSS)); +} + +/** + * @brief Get Alarm Month Value + * @param rtc RTC Instance + * @retval Alarm Month value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_alarm_month_tens(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->ALCAL, (RTC_ALCAL_MON_T | RTC_ALCAL_MON_U)) >> RTC_ALCAL_MON_U_POSS); +} + +/** + * @brief Set Alarm Date Value + * @param rtc RTC Instance + * @param date Alarm Date value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alarm_day(RTC_TypeDef *rtc, uint32_t date) +{ + MODIFY_REG(rtc->ALCAL, (RTC_ALCAL_DATE_T | RTC_ALCAL_DATE_U), (date << RTC_ALCAL_DATE_U_POSS)); +} + +/** + * @brief Get Alarm Date Value + * @param rtc RTC Instance + * @retval Alarm Date value in RTC timer, in BCD format. + */ +__STATIC_INLINE uint32_t md_rtc_get_alarm_day(RTC_TypeDef *rtc) +{ + return (uint32_t)(READ_BIT(rtc->ALCAL, (RTC_ALCAL_DATE_T | RTC_ALCAL_DATE_U)) >> RTC_ALCAL_DATE_U_POSS); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group9 ALEN + * @{ + */ +/** + * @brief Set RTC_ALEN Register + * @param rtc RTC Instance + * @param ctrl + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alarmen(RTC_TypeDef *rtc, uint32_t alen) +{ + WRITE_REG(RTC->ALEN, alen); +} + +/** + * @brief Get RTC_ALEN Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_alarmen(RTC_TypeDef *rtc) +{ + return (uint32_t) READ_REG(RTC->ALEN); +} + +/** + * @brief Set Year Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_alarm_year(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ALEN, RTC_ALEN_YEAR); +} + +/** + * @brief Set Year Alarm Function Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_alarm_year(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->ALEN, RTC_ALEN_YEAR); +} + +/** + * @brief Get Year Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_alarm_year(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->ALEN, RTC_ALEN_YEAR) == (RTC_ALEN_YEAR)); +} + +/** + * @brief Set Month Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_alarm_month(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ALEN, RTC_ALEN_MONTH); +} + +/** + * @brief Set Month Alarm Function Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_alarm_month(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->ALEN, RTC_ALEN_MONTH); +} + +/** + * @brief Get Month Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_alarm_month(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->ALEN, RTC_ALEN_MONTH) == (RTC_ALEN_MONTH)); +} + +/** + * @brief Set Date Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_alarm_day(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ALEN, RTC_ALEN_DATE); +} + +/** + * @brief Set Date Alarm Function Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_alarm_day(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->ALEN, RTC_ALEN_DATE); +} + +/** + * @brief Get Date Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_alarm_day(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->ALEN, RTC_ALEN_DATE) == (RTC_ALEN_DATE)); +} + +/** + * @brief Set Week Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_alarm_weekday(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ALEN, RTC_ALEN_WEEK); +} + +/** + * @brief Set Week Alarm Function Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_alarm_weekday(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->ALEN, RTC_ALEN_WEEK); +} + +/** + * @brief Get Week Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_alarm_weekday(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->ALEN, RTC_ALEN_WEEK) == (RTC_ALEN_WEEK)); +} + +/** + * @brief Set Hour Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_alarm_hour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ALEN, RTC_ALEN_HOUR); +} + +/** + * @brief Set Hour Alarm Function Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_alarm_hour(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->ALEN, RTC_ALEN_HOUR); +} + +/** + * @brief Get Hour Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_alarm_hour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->ALEN, RTC_ALEN_HOUR) == (RTC_ALEN_HOUR)); +} + +/** + * @brief Set Minute Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_alarm_minute(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ALEN, RTC_ALEN_MIN); +} + +/** + * @brief Set Minute Alarm Function Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_alarm_minute(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->ALEN, RTC_ALEN_MIN); +} + +/** + * @brief Get Minute Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_alarm_minute(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->ALEN, RTC_ALEN_MIN) == (RTC_ALEN_MIN)); +} + +/** + * @brief Set Second Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_alarm_second(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ALEN, RTC_ALEN_SEC); +} + +/** + * @brief Set Second Alarm Function Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_alarm_second(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->ALEN, RTC_ALEN_SEC); +} + +/** + * @brief Get Second Alarm Function Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_alarm_second(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->ALEN, RTC_ALEN_SEC) == (RTC_ALEN_SEC)); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group10 TRIG + * @{ + */ +/** + * @brief Set RTC_TRIG Register + * @param rtc RTC Instance + * @param ctrl + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig(RTC_TypeDef *rtc, uint32_t trig) +{ + WRITE_REG(RTC->TRIG, trig); +} + +/** + * @brief Get RTC_TRIG Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_trig(RTC_TypeDef *rtc) +{ + return (uint32_t) READ_REG(RTC->TRIG); +} + +/** + * @brief Set RTC Wakeup Counter Match Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_wakeup_count_match(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_WKTM); +} + +/** + * @brief Set RTC Wakeup Counter Match Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_wakeup_count_match(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_WKTM); +} + +/** + * @brief Get RTC Wakeup Counter Match Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_wakeuptimer_count_match(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_WKTM) == (RTC_TRIG_WKTM)); +} + +/** + * @brief Set RTC 1 Hz Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_freq1hz(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_F1HZ); +} + +/** + * @brief Set RTC 1 Hz Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_freq1hz(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_F1HZ); +} + +/** + * @brief Get RTC 1 Hz Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_freq1hz(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_F1HZ) == (RTC_TRIG_F1HZ)); +} + +/** + * @brief Set RTC Year Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_rollover_year(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_RYEAR); +} + +/** + * @brief Set RTC Year Roll Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_rollover_year(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_RYEAR); +} + +/** + * @brief Get RTC Year Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_rollover_year(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_RYEAR) == (RTC_TRIG_RYEAR)); +} + +/** + * @brief Set RTC Month Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_rollover_month(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_RMON); +} + +/** + * @brief Set RTC Month Roll Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_rollover_month(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_RMON); +} + +/** + * @brief Get RTC Month Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_rollover_month(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_RMON) == (RTC_TRIG_RMON)); +} + +/** + * @brief Set RTC Date Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_rollover_day(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_RDATE); +} + +/** + * @brief Set RTC Date Roll Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_rollover_day(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_RDATE); +} + +/** + * @brief Get RTC Date Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_rollover_day(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_RDATE) == (RTC_TRIG_RDATE)); +} + +/** + * @brief Set RTC Week Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_rollover_weekday(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_RWEEK); +} + +/** + * @brief Set RTC Week Roll Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_rollover_weekday(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_RWEEK); +} + +/** + * @brief Get RTC Week Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_rollover_weekday(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_RWEEK) == (RTC_TRIG_RWEEK)); +} + +/** + * @brief Set RTC Hour Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_rollover_hour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_RHOUR); +} + +/** + * @brief Set RTC Hour Roll Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disble_trig_rollover_hour(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_RHOUR); +} + +/** + * @brief Get RTC Hour Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_rollover_hour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_RHOUR) == (RTC_TRIG_RHOUR)); +} + +/** + * @brief Set RTC Minute Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_rollover_minute(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_RMIN); +} + +/** + * @brief Set RTC Minute Roll Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_rollover_minute(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_RMIN); +} + +/** + * @brief Get RTC Minute Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_rollover_minute(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_RMIN) == (RTC_TRIG_RMIN)); +} + +/** + * @brief Set RTC Second Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_rollover_second(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_RSEC); +} + +/** + * @brief Set RTC Second Roll Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_rollover_second(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_RSEC); +} + +/** + * @brief Get RTC Second Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_rollover_second(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_RSEC) == (RTC_TRIG_RSEC)); +} + +/** + * @brief Set RTC Match All Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_alarm_all(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_AMALL); +} + +/** + * @brief Set RTC Match All Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_alarm_all(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_AMALL); +} + +/** + * @brief Get RTC Match All Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_alarm_all(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_AMALL) == (RTC_TRIG_AMALL)); +} + +/** + * @brief Set RTC Match Year Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_alarm_year(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_AYEAR); +} + +/** + * @brief Set RTC Match Year Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_alarm_year(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_AYEAR); +} + +/** + * @brief Get RTC Match Year Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_alarm_year(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_AYEAR) == (RTC_TRIG_AYEAR)); +} + +/** + * @brief Set RTC Match Month Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_alarm_month(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_AMONTH); +} + +/** + * @brief Set RTC Match Month Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_alarm_month(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_AMONTH); +} + +/** + * @brief Get RTC Match Month Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_alarm_month(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_AMONTH) == (RTC_TRIG_AMONTH)); +} + +/** + * @brief Set RTC Match Date Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_alarm_day(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_ADTAE); +} + +/** + * @brief Set RTC Match Date Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_alarm_day(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_ADTAE); +} + +/** + * @brief Get RTC Match Date Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_alarm_day(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_ADTAE) == (RTC_TRIG_ADTAE)); +} + +/** + * @brief Set RTC Match Week Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_alarm_weekday(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_AWEEK); +} + +/** + * @brief Set RTC Match Week Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_alarm_weekday(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_AWEEK); +} + +/** + * @brief Get RTC Match Week Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_alarm_weekday(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_AWEEK) == (RTC_TRIG_AWEEK)); +} + +/** + * @brief Set RTC Match Hour Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_alarm_hour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_AHOUR); +} + +/** + * @brief Set RTC Match Hour Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_alarm_hour(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_AHOUR); +} + +/** + * @brief Get RTC Match Hour Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_alarm_hour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_AHOUR) == (RTC_TRIG_AHOUR)); +} + +/** + * @brief Set RTC Match Minute Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_alarm_minute(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_AMIN); +} + +/** + * @brief Set RTC Match Minute Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_alarm_minute(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_AMIN); +} + +/** + * @brief Get RTC Match Minute Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_alarm_minute(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_AMIN) == (RTC_TRIG_AMIN)); +} + +/** + * @brief Set RTC Match Second Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_trig_alarm_second(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->TRIG, RTC_TRIG_ASEC); +} + +/** + * @brief Set RTC Match Second Alarm Trigger Disable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_trig_alarm_second(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->TRIG, RTC_TRIG_ASEC); +} + +/** + * @brief Get RTC Match Second Alarm Trigger Enable + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_trig_alarm_second(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->TRIG, RTC_TRIG_ASEC) == (RTC_TRIG_ASEC)); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group11 IER + * @{ + */ +/** + * @brief Set RTC_IER Register + * @param rtc RTC Instance + * @param ier + */ +__STATIC_INLINE void md_rtc_set_ier(RTC_TypeDef *rtc, uint32_t ier) +{ + WRITE_REG(RTC->IER, ier); +} + +/** + * @brief Set RTC Wakeup Counter Match Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_wakeup_count_match(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_WKTM); +} + +/** + * @brief Set RTC 1 Hz Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_freq1hz(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_F1HZ); +} + +/** + * @brief Set RTC Year Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_rollover_year(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RYEAR); +} + +/** + * @brief Set RTC Month Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_rollover_month(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RMON); +} + +/** + * @brief Set RTC Date Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_rollover_day(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RDATE); +} + +/** + * @brief Set RTC Week Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_rollover_weekday(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RWEEK); +} + +/** + * @brief Set RTC Hour Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_rollover_hour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RHOUR); +} + +/** + * @brief Set RTC Minute Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_rollover_minute(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RMIN); +} + +/** + * @brief Set RTC Second Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_rollover_second(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RSEC); +} + +/** + * @brief Set RTC Match All Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_alarm_all(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AMALL); +} + +/** + * @brief Set RTC Match Year Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_alarm_year(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AYEAR); +} + +/** + * @brief Set RTC Match Month Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_alarm_month(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AMONTH); +} + +/** + * @brief Set RTC Match Date Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_alarm_day(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_ADTAE); +} + +/** + * @brief Set RTC Match Week Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_alarm_weekday(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AWEEK); +} + +/** + * @brief Set RTC Match Hour Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_alarm_hour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AHOUR); +} + +/** + * @brief Set RTC Match Minute Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_alarm_minute(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AMIN); +} + +/** + * @brief Set RTC Match Second Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_it_alarm_second(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_ASEC); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group12 IDR + * @{ + */ +/** + * @brief Set RTC_IER Register + * @param rtc RTC Instance + * @param idr + */ +__STATIC_INLINE void md_rtc_set_idr(RTC_TypeDef *rtc, uint32_t idr) +{ + WRITE_REG(RTC->IDR, idr); +} + +/** + * @brief Set RTC Wakeup Counter Match Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_wakeup_count_match(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_WKTM); +} + +/** + * @brief Set RTC 1 Hz Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_freq1hz(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_F1HZ); +} + +/** + * @brief Set RTC Year Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_rollover_year(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RYEAR); +} + +/** + * @brief Set RTC Month Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_rollover_month(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RMON); +} + +/** + * @brief Set RTC Date Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_rollover_day(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RDATE); +} + +/** + * @brief Set RTC Week Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_rollover_weekday(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RWEEK); +} + +/** + * @brief Set RTC Hour Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_rollover_hour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RHOUR); +} + +/** + * @brief Set RTC Minute Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_rollover_minute(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RMIN); +} + +/** + * @brief Set RTC Second Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_rollover_second(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RSEC); +} + +/** + * @brief Set RTC Match All Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_alarm_all(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AMALL); +} + +/** + * @brief Set RTC Match Year Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_alarm_year(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AYEAR); +} + +/** + * @brief Set RTC Match Month Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_alarm_month(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AMONTH); +} + +/** + * @brief Set RTC Match Date Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_alarm_day(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_ADTAE); +} + +/** + * @brief Set RTC Match Week Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_alarm_weekday(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AWEEK); +} + +/** + * @brief Set RTC Match Hour Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_alarm_hour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AHOUR); +} + +/** + * @brief Set RTC Match Minute Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_alarm_minute(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AMIN); +} + +/** + * @brief Set RTC Match Second Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_it_alarm_second(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_ASEC); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group13 IVS + * @{ + */ +/** + * @brief Get RTC_IVS Register + * @param rtc RTC Instance + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs(RTC_TypeDef *rtc) +{ + return (uint32_t)READ_REG(RTC->IVS); +} + +/** + * @brief Get RTC Wakeup Counter Match Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_wakeup_count_match(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_WKTM) == (RTC_IVS_WKTM)); +} + +/** + * @brief Get RTC 1 Hz Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_freq1hz(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_F1HZ) == (RTC_IVS_F1HZ)); +} + +/** + * @brief Get RTC Year Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_rollover_year(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RYEAR) == (RTC_IVS_RYEAR)); +} + +/** + * @brief Get RTC Month Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_rollover_month(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RMON) == (RTC_IVS_RMON)); +} + +/** + * @brief Get RTC Date Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_rollover_day(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RDATE) == (RTC_IVS_RDATE)); +} + +/** + * @brief Get RTC Week Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_rollover_weekday(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RWEEK) == (RTC_IVS_RWEEK)); +} + +/** + * @brief Get RTC Hour Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_rollover_hour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RHOUR) == (RTC_IVS_RHOUR)); +} + +/** + * @brief Get RTC Minute Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_rollover_minute(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RMIN) == (RTC_IVS_RMIN)); +} + +/** + * @brief Get RTC Second Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_rollover_second(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RSEC) == (RTC_IVS_RSEC)); +} + +/** + * @brief Get RTC Match All Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_alarm_all(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AMALL) == (RTC_IVS_AMALL)); +} + +/** + * @brief Get RTC Match Year Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_alarm_year(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AYEAR) == (RTC_IVS_AYEAR)); +} + +/** + * @brief Get RTC Match Month Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_alarm_month(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AMONTH) == (RTC_IVS_AMONTH)); +} + +/** + * @brief Get RTC Match Date Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_alarm_day(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_ADTAE) == (RTC_IVS_ADTAE)); +} + +/** + * @brief Get RTC Match Week Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_alarm_weekday(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AWEEK) == (RTC_IVS_AWEEK)); +} + +/** + * @brief Get RTC Match Hour Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_alarm_hour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AHOUR) == (RTC_IVS_AHOUR)); +} + +/** + * @brief Get RTC Match Minute Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_alarm_minute(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AMIN) == (RTC_IVS_AMIN)); +} + +/** + * @brief Get RTC Match Second Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_it_alarm_second(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_ASEC) == (RTC_IVS_ASEC)); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group14 RIF + * @{ + */ +/** + * @brief Get RTC_RIF Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_rif(RTC_TypeDef *rtc) +{ + return (uint32_t)READ_REG(RTC->RIF); +} + +/** + * @brief Get RTC Wakeup Counter Match Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_wakeup_count_match(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_WKTM) == (RTC_RIF_WKTM)); +} + +/** + * @brief Get RTC 1 Hz Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_freq1hz(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_F1HZ) == (RTC_RIF_F1HZ)); +} + +/** + * @brief Get RTC Year Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_rollover_year(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RYEAR) == (RTC_RIF_RYEAR)); +} +/** + * @brief Get RTC Month Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_rollover_month(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RMON) == (RTC_RIF_RMON)); +} +/** + * @brief Get RTC Date Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_rollover_day(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RDATE) == (RTC_RIF_RDATE)); +} +/** + * @brief Get RTC Week Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_rollover_weekday(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RWEEK) == (RTC_RIF_RWEEK)); +} +/** + * @brief Get RTC Hour Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_rollover_hour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RHOUR) == (RTC_RIF_RHOUR)); +} +/** + * @brief Get RTC Minute Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_rollover_minute(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RMIN) == (RTC_RIF_RMIN)); +} +/** + * @brief Get RTC Second Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_rollover_second(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RSEC) == (RTC_RIF_RSEC)); +} +/** + * @brief Get RTC Match All Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_alarm_all(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AMALL) == (RTC_RIF_AMALL)); +} +/** + * @brief Get RTC Match Year Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_alarm_year(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AYEAR) == (RTC_RIF_AYEAR)); +} +/** + * @brief Get RTC Match Month Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_alarm_month(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AMONTH) == (RTC_RIF_AMONTH)); +} +/** + * @brief Get RTC Match Date Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_alarm_day(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_ADTAE) == (RTC_RIF_ADTAE)); +} +/** + * @brief Get RTC Match Week Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_alarm_weekday(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AWEEK) == (RTC_RIF_AWEEK)); +} +/** + * @brief Get RTC Match Hour Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_alarm_hour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AHOUR) == (RTC_RIF_AHOUR)); +} +/** + * @brief Get RTC Match Minute Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_alarm_minute(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AMIN) == (RTC_RIF_AMIN)); +} +/** + * @brief Get RTC Match Second Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_it_alarm_second(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_ASEC) == (RTC_RIF_ASEC)); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group15 IFM + * @{ + */ +/** + * @brief Get RTC_RIF Register + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm(RTC_TypeDef *rtc) +{ + return (uint32_t)READ_REG(RTC->IFM); +} + +/** + * @brief Get RTC Wakeup Counter Match Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_wakeup_count_match(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_WKTM) == (RTC_IFM_WKTM)); +} + +/** + * @brief Get RTC 1 Hz Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_freq1hz(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_F1HZ) == (RTC_IFM_F1HZ)); +} + +/** + * @brief Get RTC Year Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_rollover_year(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RYEAR) == (RTC_IFM_RYEAR)); +} + +/** + * @brief Get RTC Month Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_rollover_month(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RMON) == (RTC_IFM_RMON)); +} + +/** + * @brief Get RTC Date Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_rollover_day(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RDATE) == (RTC_IFM_RDATE)); +} + +/** + * @brief Get RTC Week Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_rollover_weekday(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RWEEK) == (RTC_IFM_RWEEK)); +} + +/** + * @brief Get RTC Hour Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_rollover_hour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RHOUR) == (RTC_IFM_RHOUR)); +} + +/** + * @brief Get RTC Minute Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_rollover_minute(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RMIN) == (RTC_IFM_RMIN)); +} + +/** + * @brief Get RTC Second Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_rollover_second(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RSEC) == (RTC_IFM_RSEC)); +} + +/** + * @brief Get RTC Match All Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_alarm_all(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AMALL) == (RTC_IFM_AMALL)); +} + +/** + * @brief Get RTC Match Year Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_alarm_year(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AYEAR) == (RTC_IFM_AYEAR)); +} + +/** + * @brief Get RTC Match Month Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_alarm_month(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AMONTH) == (RTC_IFM_AMONTH)); +} + +/** + * @brief Get RTC Match Date Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_alarm_day(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_ADTAE) == (RTC_IFM_ADTAE)); +} + +/** + * @brief Get RTC Match Week Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_alarm_weekday(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AWEEK) == (RTC_IFM_AWEEK)); +} + +/** + * @brief Get RTC Match Hour Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_alarm_hour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AHOUR) == (RTC_IFM_AHOUR)); +} + +/** + * @brief Get RTC Match Minute Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_alarm_minute(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AMIN) == (RTC_IFM_AMIN)); +} + +/** + * @brief Get RTC Match Second Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_masked_it_alarm_second(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_ASEC) == (RTC_IFM_ASEC)); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group16 ICR + * @{ + */ +/** + * @brief Get RTC_ICR Register + * @param rtc RTC Instance + * @param icr + * @retval None + */ +__STATIC_INLINE void md_rtc_get_icr(RTC_TypeDef *rtc, uint32_t icr) +{ + WRITE_REG(RTC->ICR, icr); +} + +/** + * @brief Set RTC Wakeup Counter Match Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_wakeup_count_match(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_WKTM); +} +/** + * @brief Set RTC 1 Hz Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_freq1hz(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_F1HZ); +} +/** + * @brief Set RTC Year Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_rollover_year(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RYEAR); +} +/** + * @brief Set RTC Month Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_rollover_month(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RMON); +} +/** + * @brief Set RTC Date Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_rollover_day(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RDATE); +} +/** + * @brief Set RTC Week Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_rollover_weekday(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RWEEK); +} +/** + * @brief Set RTC Hour Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_rollover_hour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RHOUR); +} +/** + * @brief Set RTC Minute Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_rollover_minute(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RMIN); +} +/** + * @brief Set RTC Second Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_rollover_second(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RSEC); +} +/** + * @brief Set RTC Match All Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_alarm_all(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AMALL); +} +/** + * @brief Set RTC Match Year Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_alarm_year(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AYEAR); +} +/** + * @brief Set RTC Match Month Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_alarm_month(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AMONTH); +} +/** + * @brief Set RTC Match Date Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_alarm_day(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_ADTAE); +} +/** + * @brief Set RTC Match Week Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_alarm_weekday(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AWEEK); +} +/** + * @brief Set RTC Match Hour Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_alarm_hour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AHOUR); +} +/** + * @brief Set RTC Match Minute Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_alarm_minute(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AMIN); +} +/** + * @brief Set RTC Match Second Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_it_alarm_second(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_ASEC); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group17 STA + * @{ + */ +/** + * @brief Get RTC Calendar Synchronization status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_flag_sync_done(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->STA, RTC_STA_SYNDONE) == (RTC_STA_SYNDONE)); +} +/** + * @brief Get RTC Calendar Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rtc_is_active_flag_empty(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->STA, RTC_STA_EMPTY) == (RTC_STA_EMPTY)); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group18 BKEN + * @{ + */ +/** + * @brief Enable RTC backup register to read + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_bkreg_bypass(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->BKEN, RTC_BKEN_BKEN); +} + +/** + * @brief Disable RTC backup register to read + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_disable_bkreg_bypass(RTC_TypeDef *rtc) +{ + CLEAR_BIT(rtc->BKEN, RTC_BKEN_BKEN); +} + +/** + * @brief Get RTC backup register read enable or disable + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RTC_BKEN_RTC_REGISTER + * @arg @ref MD_RTC_BKEN_BACKUP_REGISTER + */ +__STATIC_INLINE uint32_t md_rtc_is_enabled_bkreg_bypass(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->BKEN, RTC_BKEN_BKEN) == (RTC_BKEN_BKEN)); +} +/** + * @} + */ + +/** @defgroup MD_RTC_Public_Functions_Group1 Initialization + * @{ + */ +ErrorStatus md_rtc_deinit(RTC_TypeDef *); +ErrorStatus md_rtc_init(RTC_TypeDef *, md_rtc_inittypedef *); +void md_rtc_structinit(md_rtc_inittypedef *); +ErrorStatus md_rtc_time_init(RTC_TypeDef *, md_rtc_timetypedef *); +void md_rtc_time_structinit(md_rtc_timetypedef *); +ErrorStatus md_rtc_date_init(RTC_TypeDef *rtc, md_rtc_datetypedef *); +void md_rtc_date_structinit(md_rtc_datetypedef *); +ErrorStatus md_rtc_alarm_init(RTC_TypeDef *rtc, md_rtc_alarmtypedef *); +void md_rtc_alarm_structinit(md_rtc_alarmtypedef *); +ErrorStatus md_rtc_enable(RTC_TypeDef *rtc); +ErrorStatus md_rtc_disable(RTC_TypeDef *rtc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_spi.c b/os/common/ext/CMSIS/ES32/FS026/md/md_spi.c new file mode 100644 index 00000000000..a8d21e9ce37 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_spi.c @@ -0,0 +1,231 @@ +/********************************************************************************** + * + * @file md_spi.c + * @brief md_spi C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 30 Dec 2021 Ginger Modify the function name + * 25 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_spi.h" +#include "md_rcu.h" +#include +#include "stdint.h" +/** @addtogroup Micro_Driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_initStruct. + * @note The parameters in md_spi_init should be expected values. Otherwise, ERROR result will be returned. + * @param SPI_InitStruct pointer to a @ref SPI_initStruct structure + * @retval None + */ +void md_spi_struct_init(md_spi_inittypedef *SPI_InitStruct) +{ + SPI_InitStruct->Mode = MD_SPI_MODE_MASTER; + SPI_InitStruct->ClockPhase = MD_SPI_PHASE_1EDGE; + SPI_InitStruct->ClockPolarity = MD_SPI_POLARITY_LOW; + SPI_InitStruct->BaudRate = MD_SPI_BAUDRATEPRESCALER_DIV16; + SPI_InitStruct->BitOrder = MD_SPI_MSB_FIRST; + SPI_InitStruct->TransferDirection = MD_SPI_FULL_DUPLEX; + SPI_InitStruct->DataWidth = MD_SPI_FRAME_FORMAT_8BIT; + SPI_InitStruct->CRCCalculation = MD_SPI_CRCCALCULATION_DISABLE; + SPI_InitStruct->CRCPoly = 0x7; + SPI_InitStruct->NSS = MD_SPI_NSS_HARD; +} + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_initStruct. + * @note The parameters in md_spi_init should be expected values. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_InitStruct pointer to a @ref SPI_InitStruct structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus md_spi_init(SPI_TypeDef *SPIx, md_spi_inittypedef *SPI_InitStruct) +{ + ErrorStatus status = ERROR; + + md_spi_disable(SPIx); + + if (SPI_InitStruct->Mode == MD_SPI_MODE_MASTER) + md_spi_enable_master_mode(SPIx); + else + md_spi_enable_slave_mode(SPIx); + + if (SPI_InitStruct->ClockPhase == MD_SPI_PHASE_1EDGE) + md_spi_enable_sample_first_edge(SPIx); + else + md_spi_enable_sample_sec_edge(SPIx); + + if (SPI_InitStruct->ClockPolarity == MD_SPI_POLARITY_LOW) + md_spi_enable_sck_low_idle(SPIx); + else + md_spi_enable_sck_high_idle(SPIx); + + md_spi_set_commumication_baud(SPIx, SPI_InitStruct->BaudRate); + + if (SPI_InitStruct->BitOrder == MD_SPI_LSB_FIRST) + md_spi_enable_first_transmit_lsb(SPIx); + else + md_spi_enable_first_transmit_msb(SPIx); + + if (SPI_InitStruct->TransferDirection == MD_SPI_HALF_DUPLEX) + md_spi_set_simplex_line_duplex(SPIx); + else + md_spi_set_duplex_line_simplex(SPIx); + + if (SPI_InitStruct->DataWidth == MD_SPI_FRAME_FORMAT_16BIT) + md_spi_enable_16_byte_commumication(SPIx); + else + md_spi_enable_8_byte_commumication(SPIx); + + + + if (SPI_InitStruct->NSS == MD_SPI_NSS_SOFT) + { + md_spi_enable_control_slave(SPIx); + md_spi_enable_ss_output_high(SPIx); + } + else + md_spi_disable_control_slave(SPIx); + + md_spi_enable_nss_output(SPIx); + + md_spi_enable(SPIx); + + status = SUCCESS; + + return status; +} + + +/** + * @brief De-Initialize the SPI registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus md_spi_deinit(SPI_TypeDef *SPIx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + md_spi_disable(SPIx); + + if (SPIx == SPI1) + { + /* Force reset of SPI clock */ + md_rcu_enable_spi1_reset(RCU); + + /* Release reset of SPI clock */ + md_rcu_disable_spi1_reset(RCU); + } + + if (SPIx == SPI2) + { + /* Force reset of SPI clock */ + md_rcu_enable_spi2_reset(RCU); + + /* Release reset of SPI clock */ + md_rcu_disable_spi2_reset(RCU); + } + + if (SPIx == SPI3) + { + /* Force reset of SPI clock */ + md_rcu_enable_spi3_reset(RCU); + + /* Release reset of SPI clock */ + md_rcu_disable_spi2_reset(RCU); + } + + status = SUCCESS; + + return status; +} + +/** + * @brief use to receive single one byte data. + * @note SPI Slave receive data + * @param SPIx SPI Instance + * @retval Data. + */ +uint8_t md_spi_recv_byte(SPI_TypeDef *SPIx) +{ + while (!md_spi_is_active_flag_rxne(SPIx)); + + return (md_spi_get_data_reg(SPIx)); +} + +/** + * @brief use to send single one byte data. + * @note SPI send data + * @param SPIx SPI Instance + * @param data SPI send one byte data. + */ +void md_spi_send_byte(SPI_TypeDef *SPIx, uint8_t data) +{ + md_spi_set_data_reg(SPIx, data); + + while (!(md_spi_is_active_flag_txe(SPIx))); +} + +/** + * @brief use to receive single one halfword data. + * @note SPI Slave receive data + * @param SPIx SPI Instance + * @retval Data. + */ +uint16_t md_spi_recv_halfword(SPI_TypeDef *SPIx) +{ + while (!md_spi_is_active_flag_rxne(SPIx)); + + return (md_spi_get_data_reg(SPIx)); +} + +/** + * @brief use to send single one halfword data. + * @note SPI send data + * @param SPIx SPI Instance + * @param data SPI send one halfword data. + */ +void md_spi_send_halfword(SPI_TypeDef *SPIx, uint16_t data) +{ + md_spi_set_data_reg(SPIx, data); + + while (!(md_spi_is_active_flag_txe(SPIx))); +} + +/** + * @} Micro_Driver + */ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_spi.h b/os/common/ext/CMSIS/ES32/FS026/md/md_spi.h new file mode 100644 index 00000000000..9629a533261 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_spi.h @@ -0,0 +1,3535 @@ +/********************************************************************************** + * + * @file md_spi.h + * @brief header file of md_spi.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 30 Dec 2021 Ginger Modify the function name + * 25 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_SPI_H__ +#define __MD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_SPI SPI + * @brief SPI micro driver + * @{ + */ + +/** @defgroup MD_SPI_Pubulic_Types SPI Pubulic Types + * @{ + */ + +/** + * @brief SPI Init structure. + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref MD_SPI_PC_MODE. + + This feature can be modified afterwards using unitary function @ref md_spi_enable_master_mode() and @ref md_spi_enable_slave_mode().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref MD_SPI_PC_PHASE. + + This feature can be modified afterwards using unitary function @ref md_spi_enable_sample_first_edge() and @ref md_spi_enable_sample_sec_edge().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref MD_SPI_PC_POLARITY. + + This feature can be modified afterwards using unitary function @ref md_spi_enable_sck_low_idle() and @ref md_spi_enable_sck_high_idle().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref MD_SPI_PC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function @ref md_spi_set_commumication_baud().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref MD_SPI_PC_BIT_ORDER. + + This feature can be modified afterwards using unitary function @ref md_spi_enable_first_transmit_lsb() and @ref md_spi_enable_first_transmit_msb().*/ + + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref MD_SPI_PC_TRANSFER_DIRECTION. + + This feature can be modified afterwards using unitary function @ref md_spi_set_simplex_line_duplex() and @ref md_spi_set_duplex_line_simplex().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref MD_SPI_PC_FRAME_FORMAT. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_dlen().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref MD_SPI_PC_NSS_MODE. + + This feature can be modified afterwards using unitary function @ref md_spi_enable_ss_output_high() and @ref md_spi_enable_ss_output_low().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref MD_SPI_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary functions @ref md_spi_enable_con1_crcen() and @ref md_spi_disable_con1_crcen().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function.*/ + +} md_spi_inittypedef, md_i2s_inittypedef; + +typedef struct md_spi_handle_s +{ + SPI_TypeDef *SPI; + md_spi_inittypedef init; + uint8_t tx_size; + uint8_t rx_size; + uint8_t tx_count; + uint8_t rx_count; + uint8_t *tx_buf; + uint8_t *rx_buf; + uint32_t ifm_buf; +} md_spi_handle_t; +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Macros SPI Public Macros + * @{ + */ + +/** + * @brief SPI Operation Mode + */ +#define MD_SPI_MODE_SLAVE (0U) /*!< Slave configuration */ +#define MD_SPI_MODE_MASTER (1U) /*!< Master configuration */ + +/** + * @brief SPI Serial Protocol + */ +#define MD_SPI_PROTOCOL_MOTOROLA (0U) /*!< Motorola mode. Used as default value */ +#define MD_SPI_PROTOCOL_TI (1U) /*!< TI mode */ + +/** + * @brief SPI Clock Phase + */ +#define MD_SPI_PHASE_1EDGE (0U) /*!< First clock transition is the first data capture edge */ +#define MD_SPI_PHASE_2EDGE (1U) /*!< Second clock transition is the first data capture edge */ + +/** + * @brief SPI Clock Polarity + */ +#define MD_SPI_POLARITY_LOW (0U) /*!< Clock to 0 when idle */ +#define MD_SPI_POLARITY_HIGH (1U) /*!< Clock to 1 when idle */ + +/** + * @brief SPI Baud Rate Prescaler + */ +#define MD_SPI_BAUDRATEPRESCALER_DIV2 (0U) /*!< BaudRate control equal to fPCLK/2 */ +#define MD_SPI_BAUDRATEPRESCALER_DIV4 (1U) /*!< BaudRate control equal to fPCLK/4 */ +#define MD_SPI_BAUDRATEPRESCALER_DIV8 (2U) /*!< BaudRate control equal to fPCLK/8 */ +#define MD_SPI_BAUDRATEPRESCALER_DIV16 (3U) /*!< BaudRate control equal to fPCLK/16 */ +#define MD_SPI_BAUDRATEPRESCALER_DIV32 (4U) /*!< BaudRate control equal to fPCLK/32 */ +#define MD_SPI_BAUDRATEPRESCALER_DIV64 (5U) /*!< BaudRate control equal to fPCLK/64 */ +#define MD_SPI_BAUDRATEPRESCALER_DIV128 (6U) /*!< BaudRate control equal to fPCLK/128 */ +#define MD_SPI_BAUDRATEPRESCALER_DIV256 (7U) /*!< BaudRate control equal to fPCLK/256 */ + +/** + * @brief SPI Transmission Bit Order + */ +#define MD_SPI_LSB_FIRST (1U) /*!< Data is transmitted/received with the LSB first */ +#define MD_SPI_MSB_FIRST (0U) /*!< Data is transmitted/received with the MSB first */ + +/** + * @brief SPI Software control chip select output + */ +#define MD_SPI_NSS_0 (0U) /*!< NSS pin input is 0 */ +#define MD_SPI_NSS_1 (1U) /*!< NSS pin input is 1 */ + +/** + * @brief SPI Software control chip select output + */ +#define MD_SPI_TX_RX (0U) /*!< Full duplex (transmit and receive) */ +#define MD_SPI_RX_ONLY (1U) /*!< Turn off output (receive mode only) */ + +/** + * @brief SPI Transfer Mode + */ +#define MD_SPI_FRAME_FORMAT_8BIT (0U) /*!< 8 bits data format */ +#define MD_SPI_FRAME_FORMAT_16BIT (1U) /*!< 16 bits data format */ + +/** + * @brief SPI transmission CRC Mode + */ +#define MD_SPI_CRC_NOT (0U) /*!< Do not transmit CRC at the end of data transmission */ +#define MD_SPI_CRC_TRANSMIT (1U) /*!< CRC is transmitted at the end of data transmission */ + +/** + * @brief SPI Transfer Direction + */ +#define MD_SPI_FULL_DUPLEX (0U) /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define MD_SPI_HALF_DUPLEX (1U) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ + +/** + * @brief SPI RX FIFO Threshold + */ +#define MD_SPI_RX_FIFO_1_CHARACTER_IN_THE_FIFO (0U) /*!< RXTHIE event is generated if FIFO level is greater than or equel to 1 character */ +#define MD_SPI_RX_FIFO_QUARTER_FULL (1U) /*!< RXTHIE event is generated if FIFO level is greater than or equel to FIFO quarter full */ +#define MD_SPI_RX_FIFO_HALF_FULL (2U) /*!< RXTHIE event is generated if FIFO level is greater than or equel to FIFO half full */ +#define MD_SPI_RX_FIFO_2_LESS_THAN_FULL (3U) /*!< RXTHIE event is generated if FIFO level is greater than or equel to FIFO 2 less than full */ + +/** + * @brief SPI TX FIFO Threshold + */ +#define MD_SPI_TX_FIFO_EMPTY (0U) /*!< TXTHIE event is generated if FIFO level is equel to FIFO empty */ +#define MD_SPI_TX_FIFO_2_CHARACTERS_IN_THE_FIFO (1U) /*!< TXTHIE event is generated if FIFO level is below than or equel to 2 characters in the FIFO */ +#define MD_SPI_TX_FIFO_QUARTER_FULL (2U) /*!< TXTHIE event is generated if FIFO level is below than or equel to FIFO quarter full */ +#define MD_SPI_TX_FIFO_HALF_FULL (3U) /*!< TXTHIE event is generated if FIFO level is below than or equel to FIFO half full */ + +/** + * @brief SPI Slave Select Pin Mode + */ +#define MD_SPI_NSS_SOFT (1U) /*!< NSS managed internally */ +#define MD_SPI_NSS_HARD (0U) /*!< NSS pin is controled by hardware */ + +/** + * @brief SPI CRC Calculation + */ +#define MD_SPI_CRCCALCULATION_DISABLE (0U) /*!< CRC calculation disabled */ +#define MD_SPI_CRCCALCULATION_ENABLE (1U) /*!< CRC calculation enabled */ + +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions SPI Public Functions + * @{ + */ + +/** @defgroup MD_SPI_Public_Functions_Group2 CON1 + * @{ + */ +/** + * @brief Set SPI control register (SPIx_CON1) + * @param SPIx SPI Instance + * @param value The value write in SPIx_CON1 + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1(SPI_TypeDef *SPIx, uint32_t value) +{ + WRITE_REG(SPIx->CON1, value); +} + +/** + * @brief Get SPI control register (SPIx_CON1) + * @param SPIx SPI Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_spi_get_con1(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CON1)); +} + +/** + * @brief Set spi duplex line simplex direction commumication. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_duplex_line_simplex(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_BIDEN); +} + +/** + * @brief Set spi simplex line duplex direction commumication. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_simplex_line_duplex(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_BIDEN); +} + +/** + * @brief Check if spi is Enabled duplex line simplex direction commumication. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_duplex_line_simplex(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_BIDEN) != SPI_CON1_BIDEN); +} + +/** + * @brief Check if spi is Enabled simplex line duplex direction commumication + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_simplex_line_duplex(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_BIDEN) == SPI_CON1_BIDEN); +} + +/** + * @brief Enable spi duplex line mode data transmit. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_simplex_line_tx(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_BIDOEN); +} + +/** + * @brief Enable spi duplex line mode data receive. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_simplex_line_rx(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_BIDOEN); +} + +/** + * @brief Check if spi is Enabled duplex line mode data transmit + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_simplex_line_tx(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_BIDOEN) == SPI_CON1_BIDOEN); +} + +/** + * @brief Check if spi is Enabled duplex line mode data receive + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_simplex_line_rx(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_BIDOEN) != SPI_CON1_BIDOEN); +} + +/** + * @brief Enable spi crc by hardware. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_crc_hardware(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_CRCEN); +} + +/** + * @brief Disable spi crc by hardware. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_crc_hardware(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_CRCEN); +} + +/** + * @brief Check if spi is enabled crc by hardware. + * @param SPIx: SPI Instance. + * @retval State for 1 or 0. + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_crc_hardware(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_CRCEN) == SPI_CON1_CRCEN); +} + +/** + * @brief Enable spi next time transmit is crc. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_next_crc_transmit(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_NXTCRC); +} + +/** + * @brief Disable spi next time transmit is crc. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_next_crc_transmit(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_NXTCRC); +} + +/** + * @brief Check if spi is enable next time transmit is crc. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_next_crc_transmit(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_NXTCRC) == SPI_CON1_NXTCRC); +} + +/** + * @brief Enable spi 16 bytes commumication data . + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_16_byte_commumication(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_FLEN); +} + +/** + * @brief Enable spi 8 bytes commumication data . + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_8_byte_commumication(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_FLEN); +} + +/** + * @brief Check if spi is enabled 16 bytes commumication data. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_16_byte_commumication(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_FLEN) == SPI_CON1_FLEN); +} + +/** + * @brief Check if spi is enabled 8 bytes commumication data. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_8_byte_commumication(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_FLEN) != SPI_CON1_FLEN); +} + +/** + * @brief Enable spi only receive mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_recv_only(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_RXO); +} + +/** + * @brief Disable spi only receive mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_recv_only(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_RXO); +} + +/** + * @brief Check if spi is enabled only receive mode. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_spi_is_enabled_recv_only(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_RXO) == SPI_CON1_RXO); +} + +/** + * @brief Enable spi control slave device by software. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_control_slave(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_SSEN); +} + +/** + * @brief Disable spi control slave device by software. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_control_slave(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_SSEN); +} + +/** + * @brief Check if spi is enabled control slave device by software. + * @param SPIx: SPI Instance. + * @retval State for bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_control_slave(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SSEN) == SPI_CON1_SSEN); +} + +/** + * @brief Enable spi chip select output high. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_ss_output_high(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_SSOUT); +} + +/** + * @brief Enable spi chip select output low. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_ss_output_low(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_SSOUT); +} + +/** + * @brief Check if spi is enabled chip select output high. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ss_output_high(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SSOUT) == SPI_CON1_SSOUT); +} + +/** + * @brief Check if spi is enabled chip select output low. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ss_output_low(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SSOUT) != SPI_CON1_SSOUT); +} + +/** + * @brief Enable spi data first transmit MSB. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_first_transmit_msb(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_LSBFST); +} + +/** + * @brief Enable spi data first transmit LSB. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_first_transmit_lsb(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_LSBFST); +} + +/** + * @brief Check if spi is enabled data first transmit LSB. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_first_transmit_lsb(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_LSBFST) == SPI_CON1_LSBFST); +} + +/** + * @brief Check if spi is enabled data first transmit MSB. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_first_transmit_msb(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_LSBFST) != SPI_CON1_LSBFST); +} + +/** + * @brief Enable SPI module. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_SPIEN); +} + +/** + * @brief Disable SPI module. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_SPIEN); +} + +/** + * @brief Check if is enabled spi. + * @param SPIx: SPI Instance. + * @retval State for bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_spi_is_enabled(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SPIEN) == SPI_CON1_SPIEN); +} + +/** + * @brief Set spi commumication baudrate. + * @param SPIx: SPI Instance. + * @param BaudRate This parameter can be one of the following values: + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None. + */ +__STATIC_INLINE void md_spi_set_commumication_baud(SPI_TypeDef *SPIx, uint8_t BaudRate) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_BAUD, BaudRate << SPI_CON1_BAUD_POSS); +} + +/** + * @brief Get spi commumication baudrate. + * @param SPIx: SPI Instance. + * @retval The retval can be one of the following values: + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t md_spi_get_commumication_baud(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_BAUD) >> SPI_CON1_BAUD_POSS); +} + +/** + * @brief Enable spi master mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_master_mode(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_MSTREN); +} + +/** + * @brief Enable spi slave mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_slave_mode(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_MSTREN); +} +/** + * @brief Check if spi is enabled master mode. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_master_mode(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_MSTREN) == SPI_CON1_MSTREN); +} + +/** + * @brief Enable spi sck bus keep high polarity in idle mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_sck_high_idle(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_CPOL); +} + +/** + * @brief Enable spi sck bus keep low polarity in idle mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_sck_low_idle(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_CPOL); +} + +/** + * @brief Check if spi is enabled sck keep high in idle. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_sck_high_idle(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_CPOL) == SPI_CON1_CPOL); +} + +/** + * @brief Check if spi is enabled sck keep low in idle. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_sck_low_idle(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_CPOL) != SPI_CON1_CPOL); +} + +/** + * @brief Enable spi sample data in seconde time edge. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_sample_sec_edge(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_CPHA); +} + +/** + * @param SPIx: SPI Instance. + * @brief Enable spi sample data in first time edge. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_sample_first_edge(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_CPHA); +} + +/** + * @brief Check is spi is enabled sample data in seconde time edge. + * @param SPIx: SPI Instance. + * @retval State of bit (0 or 1). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_sample_sec_edge(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_CPHA) == SPI_CON1_CPHA); +} + +/** + * @brief Check is spi is enabled sample data in first time edge. + * @param SPIx: SPI Instance. + * @retval State of bit (0 or 1). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_sample_first_edge(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_CPHA) != SPI_CON1_CPHA); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group3 CON2 + * @{ + */ +/** + * @brief Set SPI control register 2 (SPIx_CON2) + * @param SPIx SPI Instance + * @param value The value write in SPIx_CON2 + * @retval None + */ +__STATIC_INLINE void md_spi_set_con2(SPI_TypeDef *SPIx, uint32_t value) +{ + WRITE_REG(SPIx->CON2, value); +} + +/** + * @brief Get SPI control register 2(SPIx_CON2) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_con2(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CON2)); +} + +/** + * @brief Set spi receive fifo threshold. + * @param SPIx: SPI Instance. + * @param Threshold This parameter can be one of the following values: + * @arg @ref MD_SPI_RX_FIFO_1_CHARACTER_IN_THE_FIFO + * @arg @ref MD_SPI_RX_FIFO_QUARTER_FULL + * @arg @ref MD_SPI_RX_FIFO_HALF_FULL + * @arg @ref MD_SPI_RX_FIFO_2_LESS_THAN_FULL + * @retval None. + */ +__STATIC_INLINE void md_spi_set_rxfifo_threshold(SPI_TypeDef *SPIx, uint8_t Threshold) +{ + MODIFY_REG(SPIx->CON2, SPI_CON2_RXFTH, Threshold << SPI_CON2_RXFTH_POSS); +} + +/** + * @brief Get spi receive fifo threshold. + * @param SPIx: SPI Instance. + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_RX_FIFO_1_CHARACTER_IN_THE_FIFO + * @arg @ref MD_SPI_RX_FIFO_QUARTER_FULL + * @arg @ref MD_SPI_RX_FIFO_HALF_FULL + * @arg @ref MD_SPI_RX_FIFO_2_LESS_THAN_FULL + */ +__STATIC_INLINE uint8_t md_spi_get_rxfifo_threshold(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_RXFTH) >> SPI_CON2_RXFTH_POSS); +} + +/** + * @brief Set spi transmit fifo threshold. + * @param SPIx: SPI Instance. + * @param Threshold This parameter can be one of the following values: + * @arg @ref MD_SPI_TX_FIFO_EMPTY + * @arg @ref MD_SPI_TX_FIFO_2_CHARACTERS_IN_THE_FIFO + * @arg @ref MD_SPI_TX_FIFO_QUARTER_FULL + * @arg @ref MD_SPI_TX_FIFO_HALF_FULL + * @retval None. + */ +__STATIC_INLINE void md_spi_set_txfifo_threshold(SPI_TypeDef *SPIx, uint8_t Threshold) +{ + MODIFY_REG(SPIx->CON2, SPI_CON2_TXFTH, Threshold << SPI_CON2_TXFTH_POSS); +} + +/** + * @brief Get spi transmit fifo threshold. + * @param SPIx: SPI Instance. + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_TX_FIFO_EMPTY + * @arg @ref MD_SPI_TX_FIFO_2_CHARACTERS_IN_THE_FIFO + * @arg @ref MD_SPI_TX_FIFO_QUARTER_FULL + * @arg @ref MD_SPI_TX_FIFO_HALF_FULL + */ +__STATIC_INLINE uint8_t md_spi_get_txfifo_threshold(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_TXFTH) >> SPI_CON2_TXFTH_POSS); +} + +/** + * @brief Set MOTO SPI mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_moto_mode(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_FRF); +} + +/** + * @brief Set TI SPI mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_ti_mode(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_FRF); +} + +/** + * @brief Get spi mode. + * @param SPIx: SPI Instance. + * @retval The retval can be one of the following values: + * @arg @ref MD_SPI_PROTOCOL_MOTOROLA + * @arg @ref MD_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint8_t md_spi_get_mode(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_FRF) >> SPI_CON2_FRF_POS); +} + +/** + * @brief Produce spi NSS pulse management(master mode). + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_nss_pulse(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_NSSP); +} + +/** + * @brief Stop spi NSS pulse management(master mode). + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_nss_pulse(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_NSSP); +} + +/** + * @brief Check if spi is enabled NSS pulse management(master mode). + * @param SPIx: SPI Instance. + * @retval SPI mode(0: CLK Disable 1: CLK Enable). + */ +__STATIC_INLINE uint8_t md_spi_is_enabled_nss_pulse(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_NSSP) == SPI_CON2_NSSP); +} + +/** + * @brief Enable nss output function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_nss_output(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_NSSOE); +} + +/** + * @brief Disable nss output function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_nss_output(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_NSSOE); +} + +/** + * @brief Check if spi is enabled nss output function. + * @param SPIx: SPI Instance. + * @retval nss mode(0: Output Disable 1: Output Enable). + */ +__STATIC_INLINE uint8_t md_spi_is_enabled_nss_output(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_NSSOE) == SPI_CON2_NSSOE); +} + +/** + * @brief Enable spi tx_dma function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_txdma(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_TXDMA); +} + +/** + * @brief Disable spi tx_dma function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_txdma(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_TXDMA); +} + +/** + * @brief Check if spi is enabled txdma. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_txdma(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_TXDMA) == SPI_CON2_TXDMA); +} + +/** + * @brief Enable spi rx_dma function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_rxdma(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_RXDMA); +} + +/** + * @brief Disable spi rx_dma function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_rxdma(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_RXDMA); +} + +/** + * @brief Check if spi is enabled rxdma. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_rxdma(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_RXDMA) == SPI_CON2_RXDMA); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group4 STAT + * @{ + */ +/** + * @brief Get SPI status register(SPIx_STAT) + * @param SPIx SPI Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_spi_get_stat(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->STAT)); +} + +/** + * @brief Get spi rxfifo value. + * @param SPIx: SPI Instance. + * @retval rxfifo threshold. + */ +__STATIC_INLINE uint32_t md_spi_get_rxfifo_value(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXFLV) >> SPI_STAT_RXFLV_POSS); +} + +/** + * @brief Get spi txfifo value. + * @param SPIx: SPI Instance. + * @retval txfifo threshold. + */ +__STATIC_INLINE uint32_t md_spi_get_txfifo_value(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXFLV) >> SPI_STAT_TXFLV_POSS); +} + +/** + * @brief Get spi busy flag. + * @param SPIx: SPI Instance. + * @retval State for bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_busy(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_BUSY) == SPI_STAT_BUSY); +} + +/** + * @brief Get spi rx threshold flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rxth(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXTH) == SPI_STAT_RXTH); +} + +/** + * @brief Get spi rx under flow flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rxud(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXUD) == SPI_STAT_RXUD); +} + +/** + * @brief Get spi rx over flow flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rxov(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXOV) == SPI_STAT_RXOV); +} + +/** + * @brief Get spi rx buffer full flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rxf(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXF) == SPI_STAT_RXF); +} + +/** + * @brief Get spi rx buffer not empty flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rxne(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXNE) == SPI_STAT_RXNE); +} + +/** + * @brief Get spi tx threshold flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_txth(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXTH) == SPI_STAT_TXTH); +} + +/** + * @brief Get spi tx under flow flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_txud(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXUD) == SPI_STAT_TXUD); +} + +/** + * @brief Get spi tx over flow flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_txov(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXOV) == SPI_STAT_TXOV); +} + +/** + * @brief Get spi tx buffer full flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_txf(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXF) == SPI_STAT_TXF); +} + +/** + * @brief Get spi tx buffer empty flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_txe(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXE) == SPI_STAT_TXE); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group5 DATA + * @{ + */ +/** + * @brief Set spi data register value. + * @param SPIx: SPI Instance. + * @param data: tx data. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_data_reg(SPI_TypeDef *SPIx, uint32_t Data) +{ + WRITE_REG(SPIx->DATA, Data); +} + +/** + * @brief Get spi data register value. + * @param SPIx: SPI Instance. + * @retval data: value for data register. + */ +__STATIC_INLINE uint32_t md_spi_get_data_reg(SPI_TypeDef *SPIx) +{ + return READ_REG(SPIx->DATA); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group6 CRCPOLY + * @{ + */ +/** + * @brief Set spi crc register value. + * @note When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently \n + received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is \n + calculated serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are \n + considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CON1 is cleared). CRC \n + calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a \n + 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based \n + on any CRC16 standard. + Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not \n + used in I2S mode. + * @param SPIx: SPI Instance. + * @param data: crc data. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_crc_polynomial(SPI_TypeDef *SPIx, uint32_t data) +{ + WRITE_REG(SPIx->CRCPOLY, data); +} + +/** + * @brief Get spi crc register value. + * @param SPIx: SPI Instance. + * @retval data: value for crc register. + */ +__STATIC_INLINE uint32_t md_spi_get_crc_polynomial(SPI_TypeDef *SPIx) +{ + return READ_REG(SPIx->CRCPOLY); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group7 RXCRC + * @{ + */ +/** + * @brief Get spi receive data crc value. + * @note When CRC calculation is enabled, the RxCRC[7:0] bits contain the computed CRC value of the subsequently \n + transmitted bytes. This register is reset when the CRCEN bit of SPIx_CON1 is written to 1. The CRC is calculated \n + serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are considered \n + when the CRC frame format is set to be 8-bit length (FLEN bit in the SPIx_CON1 is cleared). CRC calculation is \n + done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame \n + format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. \n + Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used \n + in I2S mode. + * @param SPIx: SPI Instance. + * @retval data: value for receive crc. + */ +__STATIC_INLINE uint32_t md_spi_get_rx_data_crc(SPI_TypeDef *SPIx) +{ + return READ_REG(SPIx->RXCRC); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group8 TXCRC + * @{ + */ +/** + * @brief Get spi transmit data crc value. + * @note When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently \n + transmitted bytes. This register is reset when the CRCEN bit of SPIx_CON1 is written to 1. The CRC is calculated \n + serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are considered \n + when the CRC frame format is set to be 8-bit length (FLEN bit in the SPIx_CR1 is cleared). CRC calculation is \n + done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame \n + format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. \n + Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used \n + in I2S mode. + * @param SPIx: SPI Instance. + * @retval data: value for transmit crc. + */ +__STATIC_INLINE uint32_t md_spi_get_tx_data_crc(SPI_TypeDef *SPIx) +{ + return READ_REG(SPIx->TXCRC); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group9 IER + * @{ + */ +/** + * @brief Set SPI Interrupt enable Register + * @param SPIx SPI Instance + * @param ier + * @retval None + */ +__STATIC_INLINE void md_spi_set_ier(SPI_TypeDef *SPIx, uint32_t ier) +{ + WRITE_REG(SPIx->IER, ier); +} + +/** + * @brief Enable spi frame error interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_fre(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_FRE); +} + +/** + * @brief Enable spi mode fail interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_modf(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_MODF); +} + +/** + * @brief Enable spi crc error interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_crcerr(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_CRCERR); +} + +/** + * @brief Enable spi rx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_rxth(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXTH); +} + +/** + * @brief Enable spi rx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_rxud(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXUD); +} + +/** + * @brief Enable spi rx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_rxov(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXOV); +} + +/** + * @brief Enable spi rx full interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_rxf(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXF); +} + +/** + * @brief Enable spi rx not empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_rxne(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXNE); +} + +/** + * @brief Enable spi tx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_txth(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXTH); +} + +/** + * @brief Enable spi tx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_txud(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXUD); +} + +/** + * @brief Enable spi tx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_txov(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXOV); +} + +/** + * @brief Enable spi tx empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_txe(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXE); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group10 IDR + * @{ + */ +/** + * @brief Set SPI interrupt disable Register + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_set_idr(SPI_TypeDef *SPIx, uint32_t idr) +{ + WRITE_REG(SPIx->IDR, idr); +} + +/** + * @brief Disable spi frame error interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_fre(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_FRE); +} + +/** + * @brief Disable spi mode fail interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_modf(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_MODF); +} + +/** + * @brief Disable spi crc error interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_crcerr(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_CRCERR); +} + +/** + * @brief Disable spi rx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_rxth(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXTH); +} + +/** + * @brief Disable spi rx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_rxud(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXUD); +} + +/** + * @brief Disable spi rx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_rxov(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXOV); +} + +/** + * @brief Disable spi rx full interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_rxf(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXF); +} + +/** + * @brief Disable spi rx not empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_rxne(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXNE); +} + +/** + * @brief Disable spi tx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_txth(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXTH); +} + +/** + * @brief Disable spi tx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_txud(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXUD); +} + +/** + * @brief Disable spi tx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_txov(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXOV); +} + +/** + * @brief Disable spi tx empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_txe(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXE); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group11 IVS + * @{ + */ +/** + * @brief Get SPI_IVS Register + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_ivs(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->IVS)); +} + +/** + * @brief Check if the frame error interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_fre(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_FRE) == (SPI_IVS_FRE)); +} + +/** + * @brief Check if the mode fail interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_modf(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_MODF) == (SPI_IVS_MODF)); +} + +/** + * @brief Check if the crc error interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_crcerr(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_CRCERR) == (SPI_IVS_CRCERR)); +} + +/** + * @brief Check if the rx threshold interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_rxth(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXTH) == (SPI_IVS_RXTH)); +} + +/** + * @brief Check if the rx under flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_rxud(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXUD) == (SPI_IVS_RXUD)); +} + +/** + * @brief Check if the rx over flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_rxov(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXOV) == (SPI_IVS_RXOV)); +} + +/** + * @brief Check if the rx full interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_rxf(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXF) == (SPI_IVS_RXF)); +} + +/** + * @brief Check if the rx not empty interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_rxne(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXNE) == (SPI_IVS_RXNE)); +} + +/** + * @brief Check if the tx threshold interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_txth(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXTH) == (SPI_IVS_TXTH)); +} + +/** + * @brief Check if the tx under flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_txud(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXUD) == (SPI_IVS_TXUD)); +} + +/** + * @brief Check if the tx over flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_txov(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXOV) == (SPI_IVS_TXOV)); +} + +/** + * @brief Check if the tx empty interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_txe(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXE) == (SPI_IVS_TXE)); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group12 RIF + * @{ + */ +/** + * @brief Get SPI_RIF Register + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_rif(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RIF)); +} + +/** + * @brief Get frame error interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_fre(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_FRE) == (SPI_RIF_FRE)); +} + +/** + * @brief Get mode fail interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_modf(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_MODF) == (SPI_RIF_MODF)); +} + +/** + * @brief Get crc error interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_crcerr(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_CRCERR) == (SPI_RIF_CRCERR)); +} + +/** + * @brief Get rx threshold interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_rxth(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_RXTH) == (SPI_RIF_RXTH)); +} + +/** + * @brief Get rx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_rxud(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_RXUD) == (SPI_RIF_RXUD)); +} + +/** + * @brief Get rx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_rxov(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_RXOV) == (SPI_RIF_RXOV)); +} + +/** + * @brief Get rx full interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_rxf(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_RXF) == (SPI_RIF_RXF)); +} + +/** + * @brief Get rx not empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_rxne(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_RXNE) == (SPI_RIF_RXNE)); +} + +/** + * @brief Get tx threshold interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_txth(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_TXTH) == (SPI_RIF_TXTH)); +} + +/** + * @brief Get tx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_txud(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_TXUD) == (SPI_RIF_TXUD)); +} + +/** + * @brief Get tx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_txov(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_TXOV) == (SPI_RIF_TXOV)); +} + +/** + * @brief Get tx empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_txe(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_TXE) == (SPI_RIF_TXE)); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group13 IFM + * @{ + */ +/** + * @brief Get SPI_IFM Register + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_ifm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->IFM)); +} + +/** + * @brief Mask frame error interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_fre(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_FRE) == SPI_IFM_FRE); +} + +/** + * @brief Mask mode fail interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_modf(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_MODF) == SPI_IFM_MODF); +} + +/** + * @brief Mask crc error interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_crcerr(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_CRCERR) == SPI_IFM_CRCERR); +} + +/** + * @brief Mask rx threshold interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_rxth(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_RXTH) == SPI_IFM_RXTH); +} + +/** + * @brief Mask rx under flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_rxud(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_RXUD) == SPI_IFM_RXUD); +} + +/** + * @brief Mask rx over flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_rxov(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_RXOV) == SPI_IFM_RXOV); +} + +/** + * @brief Mask rx full interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_rxf(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_RXF) == SPI_IFM_RXF); +} + +/** + * @brief Mask rx not empty interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_rxne(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_RXNE) == SPI_IFM_RXNE); +} + +/** + * @brief Mask tx threshold interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_txth(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_TXTH) == SPI_IFM_TXTH); +} + +/** + * @brief Mask tx under flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_txud(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_TXUD) == SPI_IFM_TXUD); +} + +/** + * @brief Mask tx over flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_txov(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_TXOV) == SPI_IFM_TXOV); +} + +/** + * @brief Mask tx empty interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_masked_it_txe(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_TXE) == SPI_IFM_TXE); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group14 ICR + * @{ + */ +/** + * @brief Set SPI_ICR Register + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_set_icr(SPI_TypeDef *SPIx, uint32_t icr) +{ + WRITE_REG(SPIx->ICR, icr); +} + +/** + * @brief Clear frame error interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_fre(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_FRE); +} + +/** + * @brief Clear mode fail interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_modf(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_MODF); +} + +/** + * @brief Clear crc error interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_crcerr(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_CRCERR); +} + +/** + * @brief Clear rx threshold interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_rxth(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXTH); +} + +/** + * @brief Clear rx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_rxud(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXUD); +} + +/** + * @brief Clear rx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_rxov(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXOV); +} + +/** + * @brief Clear rx full interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_rxf(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXF); +} + +/** + * @brief Clear rx not empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_rxne(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXNE); +} + +/** + * @brief Clear tx threshold interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_txth(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXTH); +} + +/** + * @brief Clear tx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_txud(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXUD); +} + +/** + * @brief Clear tx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_txov(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXOV); +} + +/** + * @brief Clear tx empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_it_txe(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXE); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group11 Initialization + * @{ + */ +ErrorStatus md_spi_init(SPI_TypeDef *SPIx, md_spi_inittypedef *SPI_InitStruct); +ErrorStatus md_spi_deinit(SPI_TypeDef *SPIx); +void md_spi_struct_init(md_spi_inittypedef *SPI_InitStruct); +uint8_t md_spi_recv_byte(SPI_TypeDef *SPIx); +void md_spi_send_byte(SPI_TypeDef *SPIx, uint8_t data); +uint16_t md_spi_recv_halfword(SPI_TypeDef *SPIx); +void md_spi_send_halfword(SPI_TypeDef *SPIx, uint16_t data); +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MD_I2S_Public_Macros I2S Public Macros + * @{ + */ + +/** + * @brief I2S Channel length + */ +#define MD_I2S_CHANNEL_LENGTH_16BIT (0U) /*!< 16 bits wide */ +#define MD_I2S_CHANNEL_LENGTH_32BIT (1U) /*!< 32 bits wide */ + +/** + * @brief I2S Clock polarity + */ +#define MD_I2S_POLARITY_LOW (0U) /*!< Clock to 0 when idle */ +#define MD_I2S_POLARITY_HIGH (1U) /*!< Clock to 1 when idle */ + +/** + * @brief I2S Data Length + */ +#define MD_I2S_DATA_LENGTH_16BIT (0U) /*!< I2S data length to be transferred 16-bit data length */ +#define MD_I2S_DATA_LENGTH_24BIT (1U) /*!< I2S data length to be transferred 24-bit data length */ +#define MD_I2S_DATA_LENGTH_32BIT (2U) /*!< I2S data length to be transferred 32-bit data length */ +#define MD_I2S_DATA_LENGTH_NOT_ALLOWED (3U) /*!< I2S data length to be transferred Not allowed */ + +/** + * @brief I2S standard selection + */ +#define MD_I2S_PHILIPS_STANDARD (0U) /*!< I2S standard selection philips */ +#define MD_I2S_MSB_STANDARD (1U) /*!< I2S standard selection MSB */ +#define MD_I2S_LSB_STANDARD (2U) /*!< I2S standard selection LSB */ +#define MD_I2S_PCM_STANDARD (3U) /*!< I2S standard selection PCM */ + +/** + * @brief I2S Frame Synchronization + */ +#define MD_I2S_FRAME_SYN_SHORT (0U) /*!< Short frame synchronization */ +#define MD_I2S_FRAME_SYN_LONG (1U) /*!< Long frame synchronization */ + +/** + * @brief I2S Mode Selection + */ +#define MD_I2S_MODE_SPI (0U) /*!< SPI mode is selection */ +#define MD_I2S_MODE_I2S (1U) /*!< I2S mode is seleciton */ + +/** + * @brief I2S Configuration Mode + */ +#define MD_I2S_SLAVE_FULL_DUPLEX (0U) /*!< I2S configuartion mode slave duplex */ +#define MD_I2S_SLAVE_TX (1U) /*!< I2S configuartion mode slave transmit */ +#define MD_I2S_SLAVE_RX (2U) /*!< I2S configuartion mode slave receive */ +#define MD_I2S_MASTER_FULL_DUPLEX (4U) /*!< I2S configuartion mode master duplex */ +#define MD_I2S_MASTER_TX (5U) /*!< I2S configuartion mode master transmit */ +#define MD_I2S_MASTER_RX (6U) /*!< I2S configuartion mode master receive */ + +/** + * @brief I2S Extern Clock + */ +#define MD_I2S_EVEN (0U) /*!< Real divider value is = (I2SDIV * 2) */ +#define MD_I2S_ODD (1U) /*!< Real divider value is = (I2SDIV * 2)+1 */ + +/** + * @brief I2S Extern Clock + */ +#define MD_I2S_APB_CLOCK (0U) /*!< APB clock is selection */ +#define MD_I2S_EXTERNAL_CLOCK (1U) /*!< External clock is seleciton */ + +/** + * @} + */ + +/** @defgroup MD_I2S_Public_Functions I2S Public Functions + * @{ + */ + +/** @defgroup MD_I2S_Public_Functions_Group2 I2SCFG + * @{ + */ +/** + * @brief Set SPI I2S configuration register(SPIx_I2SCFG) + * @param SPIx SPI Instance + * @param value The value write in SPIx_I2SCFG + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg(SPI_TypeDef *SPIx, uint32_t value) +{ + WRITE_REG(SPIx->I2SCFG, value); +} + +/** + * @brief Get SPI I2S configuration register (SPIx_I2SCFG) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->I2SCFG)); +} + +/** + * @brief Enable I2S module. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SMOD | SPI_I2SCFG_I2SE); +} + +/** + * @brief Disable I2S module. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE); + CLEAR_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SMOD); +} + +/** + * @brief Check if I2S is enabled. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE) == SPI_I2SCFG_I2SE); +} + +/** + * @brief Set TX/RX mode. + * @param I2Sx: I2S Instance. + * @param value This bit can be set to: + * @arg @ref MD_I2S_SLAVE_FULL_DUPLEX + * @arg @ref MD_I2S_SLAVE_TX + * @arg @ref MD_I2S_SLAVE_RX + * @arg @ref MD_I2S_MASTER_FULL_DUPLEX + * @arg @ref MD_I2S_MASTER_TX + * @arg @ref MD_I2S_MASTER_RX + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_mode(SPI_TypeDef *SPIx, uint8_t mode) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SCFG, mode << SPI_I2SCFG_I2SCFG_POSS); +} + +/** + * @brief Get TX/RX mode. + * @param I2Sx: I2S Instance. + * @retval The retval can be one of the following values: + * @arg @ref MD_I2S_SLAVE_FULL_DUPLEX + * @arg @ref MD_I2S_SLAVE_TX + * @arg @ref MD_I2S_SLAVE_RX + * @arg @ref MD_I2S_MASTER_FULL_DUPLEX + * @arg @ref MD_I2S_MASTER_TX + * @arg @ref MD_I2S_MASTER_RX + */ +__STATIC_INLINE uint32_t md_i2s_get_mode(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SCFG) >> SPI_I2SCFG_I2SCFG_POSS); +} + +/** + * @brief Set PCM short frame. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_short_frame(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFG, SPI_I2SCFG_PCMSYNC); +} + +/** + * @brief Set PCM long frame. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_long_frame(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFG, SPI_I2SCFG_PCMSYNC); +} + +/** + * @brief Get PCM frame mode. + * @param I2Sx: I2S Instance. + * @retval The retval can be one of the following values: + * @arg @ref MD_I2S_FRAME_SYN_SHORT + * @arg @ref MD_I2S_FRAME_SYN_LONG + */ +__STATIC_INLINE uint32_t md_i2s_get_frame_mode(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_PCMSYNC) >> SPI_I2SCFG_PCMSYNC_POS); +} + +/** + * @brief Set I2S standard. + * @param I2Sx: I2S Instance. + * @param value This bit can be set to: + * @arg @ref MD_I2S_PHILIPS_STANDARD + * @arg @ref MD_I2S_MSB_STANDARD + * @arg @ref MD_I2S_LSB_STANDARD + * @arg @ref MD_I2S_PCM_STANDARD + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_standard(SPI_TypeDef *SPIx, uint8_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SSTD, value << SPI_I2SCFG_I2SSTD_POSS); +} + +/** + * @brief Get I2S standard. + * @param I2Sx: I2S Instance. + * @retval The retval can be one of the following values: + * @arg @ref MD_I2S_PHILIPS_STANDARD + * @arg @ref MD_I2S_MSB_STANDARD + * @arg @ref MD_I2S_LSB_STANDARD + * @arg @ref MD_I2S_PCM_STANDARD + */ +__STATIC_INLINE uint32_t md_i2s_get_standard(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SSTD) >> SPI_I2SCFG_I2SSTD_POSS); +} + +/** + * @brief Set I2S clock polarity. + * @param I2Sx: I2S Instance. + * @param value This bit can be set to: + * @arg @ref MD_I2S_POLARITY_LOW + * @arg @ref MD_I2S_POLARITY_HIGH + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_inactive_polarity(SPI_TypeDef *SPIx, uint8_t pol) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_CKPOL, pol << SPI_I2SCFG_CKPOL_POS); +} + +/** + * @brief Get I2S clock polarity. + * @param I2Sx: I2S Instance. + * @retval I2S polarity: + * - 0: low + * - 1: high + */ +__STATIC_INLINE uint32_t md_i2s_get_inactive_polarity(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_CKPOL) >> SPI_I2SCFG_CKPOL_POS); +} + +/** + * @brief Set I2S data length. + * @param I2Sx: I2S Instance. + * @param value This bit can be set to: + * @arg @ref MD_I2S_DATA_LENGTH_16BIT + * @arg @ref MD_I2S_DATA_LENGTH_24BIT + * @arg @ref MD_I2S_DATA_LENGTH_32BIT + * @arg @ref MD_I2S_DATA_LENGTH_NOT_ALLOWED + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_data_length(SPI_TypeDef *SPIx, uint8_t length) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_DATLEN, length << SPI_I2SCFG_DATLEN_POSS); +} + +/** + * @brief Get I2S data length. + * @param I2Sx: I2S Instance. + * @retval The retval can be one of the following values: + * @arg @ref MD_I2S_DATA_LENGTH_16BIT + * @arg @ref MD_I2S_DATA_LENGTH_24BIT + * @arg @ref MD_I2S_DATA_LENGTH_32BIT + * @arg @ref MD_I2S_DATA_LENGTH_NOT_ALLOWED + */ +__STATIC_INLINE uint32_t md_i2s_get_data_length(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_DATLEN) >> SPI_I2SCFG_DATLEN_POSS); +} + +/** + * @brief Set I2S channel length. + * @param I2Sx: I2S Instance. + * @param value This bit can be set to: + * @arg @ref MD_I2S_CHANNEL_LENGTH_16BIT + * @arg @ref MD_I2S_CHANNEL_LENGTH_32BIT + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_channel_length(SPI_TypeDef *SPIx, uint8_t length) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_CHLEN, length << SPI_I2SCFG_CHLEN_POS); +} + +/** + * @brief Get I2S channel length. + * @param I2Sx: I2S Instance. + * @retval Return: + * @arg @ref MD_I2S_CHANNEL_LENGTH_16BIT + * @arg @ref MD_I2S_CHANNEL_LENGTH_32BIT + */ +__STATIC_INLINE uint32_t md_i2s_get_channel_length(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_CHLEN) >> SPI_I2SCFG_CHLEN_POS); +} +/** + * @} + */ + +/** @defgroup MD_I2S_Public_Functions_Group3 I2SPR + * @{ + */ +/** + * @brief Set SPI I2S configuration register(SPIx_I2SPR) + * @param SPIx SPI Instance + * @param value The value write in SPIx_I2SPR + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2spr(SPI_TypeDef *SPIx, uint32_t value) +{ + WRITE_REG(SPIx->I2SPR, value); +} + +/** + * @brief Get SPI I2S configuration register (SPIx_I2SPR) + * @param SPIx SPI Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_spi_get_i2spr(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->I2SPR)); +} + +/** + * @brief Set I2S clock source. + * @param I2Sx: I2S Instance. + * @param value This bit can be set to: + * @arg MD_I2S_APB_CLOCK + * @arg MD_I2S_EXTERNAL_CLOCK + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_clock_cource(SPI_TypeDef *SPIx, uint8_t clk) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_EXTCKEN, clk << SPI_I2SPR_EXTCKEN_POS); +} + +/** + * @brief Get I2S clock source. + * @param I2Sx: I2S Instance. + * @retval The retval can be one of the following values: + * @arg MD_I2S_APB_CLOCK + * @arg MD_I2S_EXTERNAL_CLOCK + */ +__STATIC_INLINE uint32_t md_i2s_get_clock_cource(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_EXTCKEN) >> SPI_I2SPR_EXTCKEN_POS); +} + +/** + * @brief Enable I2S main clock output. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_enable_mclock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Disable I2S main clock output. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_disable_mclock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Check if main clock output is enabled. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_mclock(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == SPI_I2SPR_MCKOE); +} + +/** + * @brief Set I2S odd coefficient. + * @param I2Sx: I2S Instance. + * @param odd: Odd coefficient + * - 0: Frequency division = I2SDIV * 2 + * - 1: Frequency division = (I2SDIV * 2) + 1 + * @param value This bit can be set to: + * @arg MD_I2S_EVEN + * @arg MD_I2S_ODD + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_div_odd(SPI_TypeDef *SPIx, uint8_t odd) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, odd << SPI_I2SPR_ODD_POS); +} + +/** + * @brief Get I2S odd coefficient. + * @param I2Sx: I2S Instance. + * @retval Odd coefficient: + * - 0: Frequency division = I2SDIV * 2 + * - 1: Frequency division = (I2SDIV * 2) + 1 + * @retval The retval can be one of the following values: + * @arg MD_I2S_EVEN + * @arg MD_I2S_ODD + */ +__STATIC_INLINE uint32_t md_i2s_get_div_odd(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> SPI_I2SPR_ODD_POS); +} + +/** + * @brief Set I2S division + * @param I2Sx: I2S Instance. + * @param div: Frequency division. + * @param div This bit can be set to: + * @arg Max:255 + * @arg Min:1 + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_div(SPI_TypeDef *SPIx, uint8_t div) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, div << SPI_I2SPR_I2SDIV_POSS); +} + +/** + * @brief Get I2S division. + * @param I2Sx: I2S Instance. + * @retval Frequency division. + * @retval Return follow : + * @arg Max:255 + * @arg Min:1 + */ +__STATIC_INLINE uint32_t md_i2s_get_div(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV) >> SPI_I2SPR_I2SDIV_POSS); +} +/** + * @} + */ + +/** @defgroup MD_I2S_Public_Functions_Group4 I2S + * @{ + */ +/** + * @brief Set I2S control register 2 (SPIx_CON2) + * @param I2Sx: I2S Instance + * @param value The value write in SPIx_CON2 + * @retval None + */ +__STATIC_INLINE void md_i2s_set_con2(SPI_TypeDef *SPIx, uint32_t value) +{ + md_spi_set_con2(SPIx, value); +} + +/** + * @brief Get I2S control register 2(SPIx_CON2) + * @param I2Sx: I2S Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_i2s_get_con2(SPI_TypeDef *SPIx) +{ + return md_spi_get_con2(SPIx); +} + +/** + * @brief Set I2S receive fifo threshold. + * @param I2Sx: I2S Instance. + * @param Threshold This parameter can be one of the following values: + * @arg @ref MD_SPI_RX_FIFO_1_CHARACTER_IN_THE_FIFO + * @arg @ref MD_SPI_RX_FIFO_QUARTER_FULL + * @arg @ref MD_SPI_RX_FIFO_HALF_FULL + * @arg @ref MD_SPI_RX_FIFO_2_LESS_THAN_FULL + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_rxfifo_threshold(SPI_TypeDef *SPIx, uint8_t Threshold) +{ + md_spi_set_rxfifo_threshold(SPIx, Threshold); +} + +/** + * @brief Get I2S receive fifo threshold. + * @param I2Sx: I2S Instance. + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_RX_FIFO_1_CHARACTER_IN_THE_FIFO + * @arg @ref MD_SPI_RX_FIFO_QUARTER_FULL + * @arg @ref MD_SPI_RX_FIFO_HALF_FULL + * @arg @ref MD_SPI_RX_FIFO_2_LESS_THAN_FULL + */ +__STATIC_INLINE uint8_t md_i2s_get_rxfifo_threshold(SPI_TypeDef *SPIx) +{ + return md_spi_get_rxfifo_threshold(SPIx); +} + +/** + * @brief Set I2S transmit fifo threshold. + * @param I2Sx: I2S Instance. + * @param Threshold This parameter can be one of the following values: + * @arg @ref MD_SPI_TX_FIFO_EMPTY + * @arg @ref MD_SPI_TX_FIFO_2_CHARACTERS_IN_THE_FIFO + * @arg @ref MD_SPI_TX_FIFO_QUARTER_FULL + * @arg @ref MD_SPI_TX_FIFO_HALF_FULL + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_txfifo_threshold(SPI_TypeDef *SPIx, uint8_t Threshold) +{ + md_spi_set_txfifo_threshold(SPIx, Threshold); +} + +/** + * @brief Get I2S transmit fifo threshold. + * @param I2Sx: SPI Instance. + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_TX_FIFO_EMPTY + * @arg @ref MD_SPI_TX_FIFO_2_CHARACTERS_IN_THE_FIFO + * @arg @ref MD_SPI_TX_FIFO_QUARTER_FULL + * @arg @ref MD_SPI_TX_FIFO_HALF_FULL + */ +__STATIC_INLINE uint8_t md_i2s_get_txfifo_threshold(SPI_TypeDef *SPIx) +{ + return md_spi_get_txfifo_threshold(SPIx); +} + +/** + * @brief Enable I2S tx_dma function. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_enable_txdma(SPI_TypeDef *SPIx) +{ + md_spi_enable_txdma(SPIx); +} + +/** + * @brief Disable I2S tx_dma function. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_disable_txdma(SPI_TypeDef *SPIx) +{ + md_spi_disable_txdma(SPIx); +} + +/** + * @brief Check if I2S is enabled txdma. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_txdma(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_txdma(SPIx); +} + +/** + * @brief Enable I2S rx_dma function. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_enable_rxdma(SPI_TypeDef *SPIx) +{ + md_spi_enable_rxdma(SPIx); +} + +/** + * @brief Disable I2S rx_dma function. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_disable_rxdma(SPI_TypeDef *SPIx) +{ + md_spi_disable_rxdma(SPIx); +} + +/** + * @brief Check if I2S is enabled rxdma. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_rxdma(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_rxdma(SPIx); +} + +/** + * @brief Get I2S status register(SPIx_STAT) + * @param I2Sx: I2S Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2s_get_stat(SPI_TypeDef *SPIx) +{ + return md_spi_get_stat(SPIx); +} + +/** + * @brief Get I2S rxfifo value. + * @param I2Sx: I2S Instance. + * @retval rxfifo threshold. + */ +__STATIC_INLINE uint32_t md_i2s_get_rxfifo_value(SPI_TypeDef *SPIx) +{ + return md_spi_get_rxfifo_value(SPIx); +} + +/** + * @brief Get I2S txfifo value. + * @param I2Sx: I2S Instance. + * @retval txfifo threshold. + */ +__STATIC_INLINE uint32_t md_i2s_get_txfifo_value(SPI_TypeDef *SPIx) +{ + return md_spi_get_txfifo_value(SPIx); +} + +/** + * @brief Get I2S busy flag. + * @param I2Sx: I2S Instance. + * @retval State I2S bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_busy(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_busy(SPIx); +} + +/** + * @brief Get I2S channel side flag. + * @param I2Sx: I2S Instance. + * @retval channel flag (0: left or 1: right). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_chside(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_CHSIDE) == SPI_STAT_CHSIDE);; +} + +/** + * @brief Get I2S rx threshold flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_rxth(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_rxth(SPIx); +} + +/** + * @brief Get I2S rx under flow flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_rxud(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_rxud(SPIx); +} + +/** + * @brief Get I2S rx over flow flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_rxov(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_rxov(SPIx); +} + +/** + * @brief Get I2S rx buffer full flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_rxf(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_rxf(SPIx); +} + +/** + * @brief Get I2S rx buffer not empty flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_rxne(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_rxne(SPIx); +} + +/** + * @brief Get I2S tx threshold flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_txth(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_txth(SPIx); +} + +/** + * @brief Get I2S tx under flow flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_txud(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_txud(SPIx); +} + +/** + * @brief Get I2S tx over flow flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_txov(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_txov(SPIx); +} + +/** + * @brief Get I2S tx buffer full flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_txf(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_txf(SPIx); +} + +/** + * @brief Get I2S tx buffer empty flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_txe(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_flag_txe(SPIx); +} + +/** + * @brief Set I2S data register value. + * @param I2Sx: I2S Instance. + * @param data: tx data. + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_data_reg(SPI_TypeDef *SPIx, uint32_t data) +{ + md_spi_set_data_reg(SPIx, data); +} + +/** + * @brief Get I2S data register value. + * @param I2Sx: I2S Instance. + * @retval data: value for data register. + */ +__STATIC_INLINE uint32_t md_i2s_get_data_reg(SPI_TypeDef *SPIx) +{ + return md_spi_get_data_reg(SPIx); +} + +/** + * @brief Set I2S Interrupt enable Register + * @param SPIx SPI Instance + * @param ier + * @retval None + */ +__STATIC_INLINE void md_i2s_set_ier(SPI_TypeDef *SPIx, uint32_t ier) +{ + md_spi_set_ier(SPIx, ier); +} + +/** + * @brief Enable I2S frame error interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_fre(SPI_TypeDef *SPIx) +{ + md_spi_enable_it_fre(SPIx); +} + +/** + * @brief Enable I2S rx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_rxth(SPI_TypeDef *SPIx) +{ + md_spi_enable_it_rxth(SPIx); +} + +/** + * @brief Enable I2S rx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_rxud(SPI_TypeDef *SPIx) +{ + md_spi_enable_it_rxud(SPIx); +} + +/** + * @brief Enable I2S rx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_rxov(SPI_TypeDef *SPIx) +{ + md_spi_enable_it_rxov(SPIx); +} + +/** + * @brief Enable I2S rx full interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_rxf(SPI_TypeDef *SPIx) +{ + md_spi_enable_it_rxf(SPIx); +} + +/** + * @brief Enable I2S rx not empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_rxne(SPI_TypeDef *SPIx) +{ + md_spi_enable_it_rxne(SPIx); +} + +/** + * @brief Enable I2S tx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_txth(SPI_TypeDef *SPIx) +{ + md_spi_enable_it_txth(SPIx); +} + +/** + * @brief Enable I2S tx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_txud(SPI_TypeDef *SPIx) +{ + md_spi_enable_it_txud(SPIx); +} + +/** + * @brief Enable I2S tx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_txov(SPI_TypeDef *SPIx) +{ + md_spi_enable_it_txov(SPIx); +} + +/** + * @brief Enable I2S tx empty interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_txe(SPI_TypeDef *SPIx) +{ + md_spi_enable_it_txe(SPIx); +} + +/** + * @brief Set I2S interrupt disable Register + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_i2s_set_idr(SPI_TypeDef *SPIx, uint32_t idr) +{ + md_spi_set_idr(SPIx, idr); +} + +/** + * @brief Disable I2S frame error interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_fre(SPI_TypeDef *SPIx) +{ + md_spi_disable_it_fre(SPIx); +} + +/** + * @brief Disable I2S rx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_rxth(SPI_TypeDef *SPIx) +{ + md_spi_disable_it_rxth(SPIx); +} + +/** + * @brief Disable I2S rx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_rxud(SPI_TypeDef *SPIx) +{ + md_spi_disable_it_rxud(SPIx); +} + +/** + * @brief Disable I2S rx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_rxov(SPI_TypeDef *SPIx) +{ + md_spi_disable_it_rxov(SPIx); +} + +/** + * @brief Disable I2S rx full interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_rxf(SPI_TypeDef *SPIx) +{ + md_spi_disable_it_rxf(SPIx); +} + +/** + * @brief Disable I2S rx not empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_rxne(SPI_TypeDef *SPIx) +{ + md_spi_disable_it_rxne(SPIx); +} + +/** + * @brief Disable I2S tx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_txth(SPI_TypeDef *SPIx) +{ + md_spi_disable_it_txth(SPIx); +} + +/** + * @brief Disable I2S tx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_txud(SPI_TypeDef *SPIx) +{ + md_spi_disable_it_txud(SPIx); +} + +/** + * @brief Disable I2S tx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_txov(SPI_TypeDef *SPIx) +{ + md_spi_disable_it_txov(SPIx); +} + +/** + * @brief Disable I2S tx empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_txe(SPI_TypeDef *SPIx) +{ + md_spi_disable_it_txe(SPIx); +} + +/** + * @brief Get I2S_IVS Register + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_i2s_get_ivs(SPI_TypeDef *SPIx) +{ + return md_spi_get_ivs(SPIx); +} + +/** + * @brief Check if the frame error interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_it_fre(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_it_fre(SPIx); +} + +/** + * @brief Check if the rx threshold interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_it_rxth(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_it_rxth(SPIx); +} + +/** + * @brief Check if the rx under flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_it_rxud(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_it_rxud(SPIx); +} + +/** + * @brief Check if the rx over flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_it_rxov(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_it_rxov(SPIx); +} + +/** + * @brief Check if the rx full interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_it_rxf(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_it_rxf(SPIx); +} + +/** + * @brief Check if the rx not empty interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_it_rxne(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_it_rxne(SPIx); +} + +/** + * @brief Check if the tx threshold interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_it_txth(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_it_txth(SPIx); +} + +/** + * @brief Check if the tx under flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_it_txud(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_it_txud(SPIx); +} + +/** + * @brief Check if the tx over flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_it_txov(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_it_txov(SPIx); +} + +/** + * @brief Check if the tx empty interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enabled_it_txe(SPI_TypeDef *SPIx) +{ + return md_spi_is_enabled_it_txe(SPIx); +} + +/** + * @brief Get I2S_RIF Register + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_i2s_get_rif(SPI_TypeDef *SPIx) +{ + return md_spi_get_rif(SPIx); +} + +/** + * @brief Get frame error interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_fre(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_it_fre(SPIx); +} + +/** + * @brief Get rx threshold interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_rxth(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_it_rxth(SPIx); +} + +/** + * @brief Get rx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_rxud(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_it_rxud(SPIx); +} + +/** + * @brief Get rx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_rxov(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_it_rxov(SPIx); +} + +/** + * @brief Get rx full interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_rxf(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_it_rxf(SPIx); +} + +/** + * @brief Get rx not empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_rxne(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_it_rxne(SPIx); +} + +/** + * @brief Get tx threshold interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_txth(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_it_txth(SPIx); +} + +/** + * @brief Get tx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_txud(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_it_txud(SPIx); +} + +/** + * @brief Get tx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_txov(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_it_txov(SPIx); +} + +/** + * @brief Get tx empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_txe(SPI_TypeDef *SPIx) +{ + return md_spi_is_active_it_txe(SPIx); +} + +/** + * @brief Get I2S_IFM Register + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_i2s_get_ifm(SPI_TypeDef *SPIx) +{ + return md_spi_get_ifm(SPIx); +} + +/** + * @brief Mask frame error interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_masked_it_fre(SPI_TypeDef *SPIx) +{ + return md_spi_is_masked_it_fre(SPIx); +} + +/** + * @brief Mask rx threshold interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_masked_it_rxth(SPI_TypeDef *SPIx) +{ + return md_spi_is_masked_it_rxth(SPIx); +} + +/** + * @brief Mask rx under flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_masked_it_rxud(SPI_TypeDef *SPIx) +{ + return md_spi_is_masked_it_rxud(SPIx); +} + +/** + * @brief Mask rx over flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_masked_it_rxov(SPI_TypeDef *SPIx) +{ + return md_spi_is_masked_it_rxov(SPIx); +} + +/** + * @brief Mask rx full interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_masked_it_rxf(SPI_TypeDef *SPIx) +{ + return md_spi_is_masked_it_rxf(SPIx); +} + +/** + * @brief Mask rx not empty interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_masked_it_rxne(SPI_TypeDef *SPIx) +{ + return md_spi_is_masked_it_rxne(SPIx); +} + +/** + * @brief Mask tx threshold interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_masked_it_txth(SPI_TypeDef *SPIx) +{ + return md_spi_is_masked_it_txth(SPIx); +} + +/** + * @brief Mask tx under flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_masked_it_txud(SPI_TypeDef *SPIx) +{ + return md_spi_is_masked_it_txud(SPIx); +} + +/** + * @brief Mask tx over flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_masked_it_txov(SPI_TypeDef *SPIx) +{ + return md_spi_is_masked_it_txov(SPIx); +} + +/** + * @brief Mask tx empty interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_masked_it_txe(SPI_TypeDef *SPIx) +{ + return md_spi_is_masked_it_txe(SPIx); +} + +/** + * @brief Set I2S_ICR Register + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_i2s_set_icr(SPI_TypeDef *SPIx, uint32_t icr) +{ + md_spi_set_icr(SPIx, icr); +} + +/** + * @brief Clear frame error interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_it_fre(SPI_TypeDef *SPIx) +{ + md_spi_clear_it_fre(SPIx); +} + +/** + * @brief Clear rx threshold interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_it_rxth(SPI_TypeDef *SPIx) +{ + md_spi_clear_it_rxth(SPIx); +} + +/** + * @brief Clear rx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_it_rxud(SPI_TypeDef *SPIx) +{ + md_spi_clear_it_rxud(SPIx); +} + +/** + * @brief Clear rx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_it_rxov(SPI_TypeDef *SPIx) +{ + md_spi_clear_it_rxov(SPIx); +} + +/** + * @brief Clear rx full interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_it_rxf(SPI_TypeDef *SPIx) +{ + md_spi_clear_it_rxf(SPIx); +} + +/** + * @brief Clear rx not empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_it_rxne(SPI_TypeDef *SPIx) +{ + md_spi_clear_it_rxne(SPIx); +} + +/** + * @brief Clear tx threshold interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_it_txth(SPI_TypeDef *SPIx) +{ + md_spi_clear_it_txth(SPIx); +} + +/** + * @brief Clear tx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_it_txud(SPI_TypeDef *SPIx) +{ + md_spi_clear_it_txud(SPIx); +} + +/** + * @brief Clear tx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_it_txov(SPI_TypeDef *SPIx) +{ + md_spi_clear_it_txov(SPIx); +} + +/** + * @brief Clear tx empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_it_txe(SPI_TypeDef *SPIx) +{ + md_spi_clear_it_txe(SPIx); +} +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_syscfg.h b/os/common/ext/CMSIS/ES32/FS026/md/md_syscfg.h new file mode 100644 index 00000000000..eda12db5f56 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_syscfg.h @@ -0,0 +1,2494 @@ +/********************************************************************************** + * + * @file md_syscfg.h + * @brief header file of md_syscfg.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 25 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_SYSCFG_H__ +#define __MD_SYSCFG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_SYSCFG SYSCFG + * @brief SYSCFG micro driver + * @{ + */ + +/** @defgroup MD_SYSCFG_Public_Macros SYSCFG Public Macros + * @{ + */ + +/** + * @brief Memory mapping Status + */ +#define MD_SYSCFG_REALMOD_MAIN (0x00000000UL) /** @brief Main Flash memory mapped at 0x00000000 */ +#define MD_SYSCFG_REALMOD_BOOTROM (0x00000001UL) /** @brief Bootrom mapped at 0x00000000 */ +#define MD_SYSCFG_REALMOD_SRAM (0x00000002UL) /** @brief SRAM mapped at 0x00000000 */ + +/** + * @brief MD_SYSCFG_REMAP_MEMMOD_FLAG Memory mapping selection bits + */ +#define MD_SYSCFG_MEMMOD_MAIN (0x00000000UL) /** @brief Main Flash memory mapped at 0x00000000 */ +#define MD_SYSCFG_MEMMOD_BOOTROM (0x00000001UL) /** @brief Bootrom mapped at 0x00000000 */ +#define MD_SYSCFG_MEMMOD_SRAM (0x00000002UL) /** @brief SRAM mapped at 0x00000000 */ + +/** + * @brief MD_SYSCFG_PWR_RESSRC VRES voltage divider power supply selection + */ +#define MD_SYSCFG_PWR_VREFINT (0x00000000UL) /** @brief The voltage divider power supply selects VBG. */ +#define MD_SYSCFG_PWR_VDDA (0x00000001UL) /** @brief The voltage divider power supply selects VDDA. */ + +/** + * @brief MD_SYSCFG_IRSEL_PLR_FLAG IR Polarity + */ +#define MD_SYSCFG_PLR_INV_SEL1_AND_SEL2 (0x00000000UL) /** @brief IR out = ~(SEL1 & SEL2) */ +#define MD_SYSCFG_PLR_SEL1_AND_SEL2 (0x00000001UL) /** @brief IR out = SEL1 & SEL2 */ + +/** + * @brief MD_SYSCFG_IRSEL_SEL2 IR Select 2 + */ +#define MD_SYSCFG_SEL2_OFF (0x00000000UL) /** @brief 0000: OFF */ +#define MD_SYSCFG_SEL2_GP16C2T4_CH1 (0x00000001UL) /** @brief 0001: GP16C2T4_CH1 */ +#define MD_SYSCFG_SEL2_GP16C2T4_CH2 (0x00000002UL) /** @brief 0010: GP16C2T4_CH2 */ +#define MD_SYSCFG_SEL2_UART2_TX (0x00000004UL) /** @brief 0100: UART2_TX */ +#define MD_SYSCFG_SEL2_UART4_TX (0x00000008UL) /** @brief 1000: UART4_TX */ + +/** + * @brief MD_SYSCFG_IRSEL_SEL1 IR Select 1 + */ +#define MD_SYSCFG_SEL1_OFF (0x00000000UL) /** @brief 0000: OFF */ +#define MD_SYSCFG_SEL1_GP16C2T2_CH1 (0x00000001UL) /** @brief 0001: GP16C2T2_CH1 */ +#define MD_SYSCFG_SEL1_GP16C2T2_CH2 (0x00000002UL) /** @brief 0010: GP16C2T2_CH2 */ +#define MD_SYSCFG_SEL1_GP16C2T3_CH1 (0x00000004UL) /** @brief 0100: GP16C2T3_CH1 */ +#define MD_SYSCFG_SEL1_GP16C2T3_CH2 (0x00000008UL) /** @brief 1000: GP16C2T3_CH2 */ + +/** + * @brief MD_SYSCFG_MEMMOD_SMOD + */ +#define MD_SYSCFG_SMOD_32KB (0x0000001FUL) /** @brief 0x1F: 32KB */ +#define MD_SYSCFG_SMOD_16KB (0x0000000FUL) /** @brief 0x0F: 16KB */ +#define MD_SYSCFG_SMOD_8KB (0x00000007UL) /** @brief 0x07: 8KB */ +#define MD_SYSCFG_SMOD_4KB (0x00000003UL) /** @brief 0x03: 4KB */ +#define MD_SYSCFG_SMOD_2KB (0x00000001UL) /** @brief 0x01: 2KB */ + +/** + * @brief MD_SYSCFG_MEMMOD_FMOD + */ +#define MD_SYSCFG_FMOD_256KB (0x000000FFUL) /** @brief 0xFF: 256KB */ +#define MD_SYSCFG_FMOD_128KB (0x0000007FUL) /** @brief 0x7F: 128KB */ +#define MD_SYSCFG_FMOD_64KB (0x0000003FUL) /** @brief 0x3F: 64KB */ +#define MD_SYSCFG_FMOD_32KB (0x0000001FUL) /** @brief 0x1F: 32KB */ +#define MD_SYSCFG_FMOD_16KB (0x0000000FUL) /** @brief 0x0F: 16KB */ + +/** + * @brief MD_SYSCFG_PWRCON_BORLS These bits are written by software to select the Low voltage reset voltage + */ +#define MD_SYSCFG_SYS_BORLS_LV0 (0x00000000UL) /** @brief 0000: 2.0V */ +#define MD_SYSCFG_SYS_BORLS_LV1 (0x00000001UL) /** @brief 0001: 2.3V */ +#define MD_SYSCFG_SYS_BORLS_LV2 (0x00000002UL) /** @brief 0010: 2.6V */ +#define MD_SYSCFG_SYS_BORLS_LV3 (0x00000003UL) /** @brief 0011: 2.9V */ +#define MD_SYSCFG_SYS_BORLS_LV4 (0x00000004UL) /** @brief 0100: 3.2V */ +#define MD_SYSCFG_SYS_BORLS_LV5 (0x00000005UL) /** @brief 0101: 3.5V */ +#define MD_SYSCFG_SYS_BORLS_LV6 (0x00000006UL) /** @brief 0110: 3.8V */ +#define MD_SYSCFG_SYS_BORLS_LV7 (0x00000007UL) /** @brief 0111: 4.1V */ + +/** + * @brief MD_SYSCFG_CFG_DBGHEN DBG Halt enable bit + */ +#define MD_SYSCFG_DBGHEN_IWDT (0x00002000UL) /** @brief 1<<13: IWDT */ +#define MD_SYSCFG_DBGHEN_WWDT (0x00001000UL) /** @brief 1<<12: WWDT */ +#define MD_SYSCFG_DBGHEN_I2C2 (0x00000800UL) /** @brief 1<<11: I2C2 */ +#define MD_SYSCFG_DBGHEN_I2C1 (0x00000400UL) /** @brief 1<<10: I2C1 */ +#define MD_SYSCFG_DBGHEN_BS16T1 (0x00000200UL) /** @brief 1<<9 : BS16T1 */ +#define MD_SYSCFG_DBGHEN_GP16C4T3 (0x00000100UL) /** @brief 1<<8 : GP16C4T3 */ +#define MD_SYSCFG_DBGHEN_GP16C4T2 (0x00000080UL) /** @brief 1<<7 : GP16C4T2 */ +#define MD_SYSCFG_DBGHEN_GP16C4T1 (0x00000040UL) /** @brief 1<<6 : GP16C4T1 */ +#define MD_SYSCFG_DBGHEN_GP32C4T1 (0x00000020UL) /** @brief 1<<5 : GP32C4T1 */ +#define MD_SYSCFG_DBGHEN_GP16C2T4 (0x00000010UL) /** @brief 1<<4 : GP16C2T4 */ +#define MD_SYSCFG_DBGHEN_GP16C2T3 (0x00000008UL) /** @brief 1<<3 : GP16C2T3 */ +#define MD_SYSCFG_DBGHEN_GP16C2T2 (0x00000004UL) /** @brief 1<<2 : GP16C2T2 */ +#define MD_SYSCFG_DBGHEN_GP16C2T1 (0x00000002UL) /** @brief 1<<1 : GP16C2T1 */ +#define MD_SYSCFG_DBGHEN_AD16C4T1 (0x00000001UL) /** @brief 1<<0 : AD16C4T1 */ + +/** + * @brief MD_SYSCFG_PWRCON_BORLS These bits are written by software to select the Low voltage reset voltage + */ +#define MD_SYSCFG_BORLS_LV0 (0x00000000UL) /** @brief 0000: 2.0V */ +#define MD_SYSCFG_BORLS_LV1 (0x00000001UL) /** @brief 0001: 2.3V */ +#define MD_SYSCFG_BORLS_LV2 (0x00000002UL) /** @brief 0010: 2.6V */ +#define MD_SYSCFG_BORLS_LV3 (0x00000003UL) /** @brief 0011: 2.9V */ +#define MD_SYSCFG_BORLS_LV4 (0x00000004UL) /** @brief 0100: 3.2V */ +#define MD_SYSCFG_BORLS_LV5 (0x00000005UL) /** @brief 0101: 3.5V */ +#define MD_SYSCFG_BORLS_LV6 (0x00000006UL) /** @brief 0110: 3.8V */ +#define MD_SYSCFG_BORLS_LV7 (0x00000007UL) /** @brief 0111: 4.1V */ + +/** + * @brief MD_SYSCFG_PWRCON_LVDLS These bits are Low voltage detection voltage range selection + */ +#define MD_SYSCFG_LVDLS_R1V9_F2V (0x00000000UL) /** @brief 0000: R-1.9V, F-2.0V */ +#define MD_SYSCFG_LVDLS_R2V1_F2V2 (0x00000001UL) /** @brief 0001: R-2.1V, F-2.2V */ +#define MD_SYSCFG_LVDLS_R2V3_F2V4 (0x00000002UL) /** @brief 0010: R-2.3V, F-2.4V */ +#define MD_SYSCFG_LVDLS_R2V5_F2V6 (0x00000003UL) /** @brief 0011: R-2.5V, F-2.6V */ +#define MD_SYSCFG_LVDLS_R2V7_F2V8 (0x00000004UL) /** @brief 0100: R-2.7V, F-2.8V */ +#define MD_SYSCFG_LVDLS_R2V9_F3V (0x00000005UL) /** @brief 0101: R-2.9V, F-3.0V */ +#define MD_SYSCFG_LVDLS_R3V1_F3V2 (0x00000006UL) /** @brief 0110: R-3.1V, F-3.2V */ +#define MD_SYSCFG_LVDLS_R3V3_F3V4 (0x00000007UL) /** @brief 0111: R-3.3V, F-3.4V */ +#define MD_SYSCFG_LVDLS_R3V5_F3V6 (0x00000008UL) /** @brief 1000: R-3.5V, F-3.6V */ +#define MD_SYSCFG_LVDLS_R3V7_F3V8 (0x00000009UL) /** @brief 1001: R-3.7V, F-3.8V */ +#define MD_SYSCFG_LVDLS_R3V9_F4V (0x0000000AUL) /** @brief 1010: R-3.9V, F-4.0V */ +#define MD_SYSCFG_LVDLS_R4V1_F4V2 (0x0000000BUL) /** @brief 1011: R-4.1V, F-4.2V */ +#define MD_SYSCFG_LVDLS_R4V3_F4V4 (0x0000000CUL) /** @brief 1100: R-4.3V, F-4.4V */ +#define MD_SYSCFG_LVDLS_R4V5_F4V6 (0x0000000DUL) /** @brief 1101: R-4.5V, F-4.6V */ +#define MD_SYSCFG_LVDLS_R4V7_F4V8 (0x0000000EUL) /** @brief 1110: R-4.7V, F-4.8V */ +#define MD_SYSCFG_LVDLS_R4V9_F5V (0x0000000FUL) /** @brief 1111: R-4.9V, F-5.0V */ + +/** + * @brief MD_SYSCFG_WKTRIM_LOSCRCNT These bits are External low-speed clock oscillator, clock stabilization time counter + */ +#define MD_SYSCFG_LOSCRCNT_2048 (0x00000000UL) /** @brief 00: LOSC count 2048 */ +#define MD_SYSCFG_LOSCRCNT_4096 (0x00000001UL) /** @brief 01: LOSC count 4096 */ +#define MD_SYSCFG_LOSCRCNT_8192 (0x00000002UL) /** @brief 10: LOSC count 8192 */ +#define MD_SYSCFG_LOSCRCNT_16384 (0x00000003UL) /** @brief 11: LOSC count 16384 */ + +/** + * @brief MD_SYSCFG_WKTRIM_LOSCCURSEL These bits are External low-speed clock oscillator, start-up current configuration + */ +#define MD_SYSCFG_LOSCCURSEL_120NA (0x00000000UL) /** @brief 000: 120nA */ +#define MD_SYSCFG_LOSCCURSEL_200NA (0x00000001UL) /** @brief 001: 200nA */ +#define MD_SYSCFG_LOSCCURSEL_280NA (0x00000002UL) /** @brief 010: 280nA */ +#define MD_SYSCFG_LOSCCURSEL_360NA (0x00000003UL) /** @brief 011: 360nA */ +#define MD_SYSCFG_LOSCCURSEL_440NA (0x00000004UL) /** @brief 100: 440nA */ +#define MD_SYSCFG_LOSCCURSEL_520NA (0x00000005UL) /** @brief 101: 520nA */ +#define MD_SYSCFG_LOSCCURSEL_600NA (0x00000006UL) /** @brief 110: 600nA */ +#define MD_SYSCFG_LOSCCURSEL_680NA (0x00000007UL) /** @brief 111: 680nA */ + +/** + * @brief MD_SYSCFG_WKUP_WKEG WKEGx:WKUPx pin edge sensitive type select + */ +#define MD_SYSCFG_WKEG_USBDP (0x00008000UL) /** @brief 1<<15 */ +#define MD_SYSCFG_WKEG_USBDM (0x00004000UL) /** @brief 1<<14 */ +#define MD_SYSCFG_WKEG_RTC (0x00000800UL) /** @brief 1<<11 */ +#define MD_SYSCFG_WKEG_IWDT (0x00000400UL) /** @brief 1<<10 */ +#define MD_SYSCFG_WKEG_LVD (0x00000200UL) /** @brief 1<<9 */ +#define MD_SYSCFG_WKEG_NRST (0x00000100UL) /** @brief 1<<8 */ +#define MD_SYSCFG_WKEG_WKUP7 (0x00000080UL) /** @brief 1<<7 */ +#define MD_SYSCFG_WKEG_WKUP6 (0x00000040UL) /** @brief 1<<6 */ +#define MD_SYSCFG_WKEG_WKUP5 (0x00000020UL) /** @brief 1<<5 */ +#define MD_SYSCFG_WKEG_WKUP4 (0x00000010UL) /** @brief 1<<4 */ +#define MD_SYSCFG_WKEG_WKUP3 (0x00000008UL) /** @brief 1<<3 */ +#define MD_SYSCFG_WKEG_WKUP2 (0x00000004UL) /** @brief 1<<2 */ +#define MD_SYSCFG_WKEG_WKUP1 (0x00000002UL) /** @brief 1<<1 */ +#define MD_SYSCFG_WKEG_WKUP0 (0x00000001UL) /** @brief 1<<0 */ + +/** + * @brief MD_SYSCFG_WKUP_WKEN WKENx: Enable WKUPx pin or wakeup event + */ +#define MD_SYSCFG_WKEN_USBDP (0x00008000UL) /** @brief 1<<15 */ +#define MD_SYSCFG_WKEN_USBDM (0x00004000UL) /** @brief 1<<14 */ +#define MD_SYSCFG_WKEN_RTC (0x00000800UL) /** @brief 1<<11 */ +#define MD_SYSCFG_WKEN_IWDT (0x00000400UL) /** @brief 1<<10 */ +#define MD_SYSCFG_WKEN_LVD (0x00000200UL) /** @brief 1<<9 */ +#define MD_SYSCFG_WKEN_NRST (0x00000100UL) /** @brief 1<<8 */ +#define MD_SYSCFG_WKEN_WKUP7 (0x00000080UL) /** @brief 1<<7 */ +#define MD_SYSCFG_WKEN_WKUP6 (0x00000040UL) /** @brief 1<<6 */ +#define MD_SYSCFG_WKEN_WKUP5 (0x00000020UL) /** @brief 1<<5 */ +#define MD_SYSCFG_WKEN_WKUP4 (0x00000010UL) /** @brief 1<<4 */ +#define MD_SYSCFG_WKEN_WKUP3 (0x00000008UL) /** @brief 1<<3 */ +#define MD_SYSCFG_WKEN_WKUP2 (0x00000004UL) /** @brief 1<<2 */ +#define MD_SYSCFG_WKEN_WKUP1 (0x00000002UL) /** @brief 1<<1 */ +#define MD_SYSCFG_WKEN_WKUP0 (0x00000001UL) /** @brief 1<<0 */ + +/** + * @brief MD_SYSCFG_WKSR_LPLS Low Power Level Select + */ +#define MD_SYSCFG_LPLS_STOP_MODE (0x00000000UL) /** @brief 0 : Level 0, Stop Mode */ +#define MD_SYSCFG_LPLS_STANDBY0_MODE (0x00000001UL) /** @brief 1 : Level 1, Standby0 Mode */ +#define MD_SYSCFG_LPLS_STANDBY1_MODE (0x00000002UL) /** @brief 2 : Level 2, Standby1 Mode */ +#define MD_SYSCFG_LPLS_SHUTDOWN_MODE (0x00000003UL) /** @brief 3 : Level 3, Shutdown Mode */ + +/** + * @brief MD_SYSCFG_WKSR_FG FGx: WKUPx pin or wakeup event flag + */ +#define MD_SYSCFG_FG_USBDP (0x00008000UL) /** @brief 1<<15 */ +#define MD_SYSCFG_FG_USBDM (0x00004000UL) /** @brief 1<<14 */ +#define MD_SYSCFG_FG_RTC (0x00000800UL) /** @brief 1<<11 */ +#define MD_SYSCFG_FG_IWDT (0x00000400UL) /** @brief 1<<10 */ +#define MD_SYSCFG_FG_LVD (0x00000200UL) /** @brief 1<<9 */ +#define MD_SYSCFG_FG_NRST (0x00000100UL) /** @brief 1<<8 */ +#define MD_SYSCFG_FG_WKUP7 (0x00000080UL) /** @brief 1<<7 */ +#define MD_SYSCFG_FG_WKUP6 (0x00000040UL) /** @brief 1<<6 */ +#define MD_SYSCFG_FG_WKUP5 (0x00000020UL) /** @brief 1<<5 */ +#define MD_SYSCFG_FG_WKUP4 (0x00000010UL) /** @brief 1<<4 */ +#define MD_SYSCFG_FG_WKUP3 (0x00000008UL) /** @brief 1<<3 */ +#define MD_SYSCFG_FG_WKUP2 (0x00000004UL) /** @brief 1<<2 */ +#define MD_SYSCFG_FG_WKUP1 (0x00000002UL) /** @brief 1<<1 */ +#define MD_SYSCFG_FG_WKUP0 (0x00000001UL) /** @brief 1<<0 */ + +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions SYSCFG Public Functions + * @{ + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group2 REMAP + * @{ + */ +/** + * @brief Set SYSCFG_REMAP Register + * @param syscfg SYSCFG Instance + * @param remap + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_remap(SYSCFG_TypeDef *syscfg, uint32_t remap) +{ + WRITE_REG(syscfg->REMAP, remap); +} + +/** + * @brief Get SYSCFG_REMAP Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_remap(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)READ_REG(syscfg->REMAP); +} + +/** + * @brief Get Current flash start address status + * @note If set 0x1, it means second 4k Byte, If set 0x2, it means third 4k Byte, and so on. + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg Max Value 31 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_flash_remap_base_real(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->REMAP, SYSCFG_REMAP_REALBASE) >> SYSCFG_REMAP_REALBASE_POSS); +} + +/** + * @brief Get Current Memory mapping Status + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_SYSCFG_REALMOD_MAIN + * @arg @ref MD_SYSCFG_REALMOD_BOOTROM + * @arg @ref MD_SYSCFG_REALMOD_SRAM + */ +__STATIC_INLINE uint32_t md_syscfg_get_memory_mapping_real(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->REMAP, SYSCFG_REMAP_REALMOD) >> SYSCFG_REMAP_REALMOD_POSS); +} +/** + * @brief Set Remap Main Flash Base Address Selection + * @note If set 0x1, it means second 4k Byte, If set 0x2, it means third 4k Byte, and so on. + * @param syscfg SYSCFG Instance + * @param efbase This parameter can be one of the following values: + * @arg Max Value 31 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_flash_remap_base(SYSCFG_TypeDef *syscfg, uint32_t efbase) +{ + MODIFY_REG(syscfg->REMAP, SYSCFG_REMAP_EFBASE, (efbase << SYSCFG_REMAP_EFBASE_POSS)); +} +/** + * @brief Get Remap Main Flash Base Address Selection + * @note If read 0x1, it means second 4k Byte, If read 0x2, it means third 4k Byte, and so on. + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg Max Value 31 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_flash_remap_base(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->REMAP, SYSCFG_REMAP_EFBASE) >> SYSCFG_REMAP_EFBASE_POSS); +} +/** + * @brief Set Memory mapping selection bits + * @param syscfg SYSCFG Instance + * @param memmod This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_MEMMOD_MAIN + * @arg @ref MD_SYSCFG_MEMMOD_BOOTROM + * @arg @ref MD_SYSCFG_MEMMOD_SRAM + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_memory_mapping(SYSCFG_TypeDef *syscfg, uint32_t memmod) +{ + MODIFY_REG(syscfg->REMAP, SYSCFG_REMAP_MEMMOD, memmod << SYSCFG_REMAP_MEMMOD_POSS); +} +/** + * @brief Get Memory mapping selection bits + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_SYSCFG_MEMMOD_MAIN + * @arg @ref MD_SYSCFG_MEMMOD_BOOTROM + * @arg @ref MD_SYSCFG_MEMMOD_SRAM + */ +__STATIC_INLINE uint32_t md_syscfg_get_memory_mapping(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->REMAP, SYSCFG_REMAP_MEMMOD) >> SYSCFG_REMAP_MEMMOD_POSS); +} +/** + * @brief Set Start Remap bit + * @note This bit set High to start remapping process, that will be auto clear when process was finish. + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_memory_remap(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->REMAP, SYSCFG_REMAP_REMAP); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group3 PWR + * @{ + */ +/** + * @brief Set SYSCFG_PWR Register + * @param syscfg SYSCFG Instance + * @param pwr + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_pwr(SYSCFG_TypeDef *syscfg, uint32_t pwr) +{ + WRITE_REG(syscfg->PWR, pwr); +} + +/** + * @brief Get SYSCFG_PWR Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_pwr(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->PWR)); +} + +/** + * @brief Set LDOUSB regulator current mode enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_ldousb_lowpower(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->PWR, SYSCFG_PWR_LDOUSBSBY); +} + +/** + * @brief Set LDOUSB regulator current mode disable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_ldousb_lowpower(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->PWR, SYSCFG_PWR_LDOUSBSBY); +} +/** + * @brief Check if LDOUSB regulator current mode is enabled + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : ldousb lowpower mode enable + * @arg 0x0 : ldousb lowpower mode disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_ldousb_lowpower(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->PWR, SYSCFG_PWR_LDOUSBSBY) == (SYSCFG_PWR_LDOUSBSBY)); +} + +/** + * @brief Set LDOUSB regulator operation mode enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_ldousb(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->PWR, SYSCFG_PWR_LDOUSBEN); +} + +/** + * @brief Set LDOUSB regulator operation mode disable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_ldousb(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->PWR, SYSCFG_PWR_LDOUSBEN); +} +/** + * @brief Check if LDOUSB regulator operation mode is enabled + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : ldousb enable + * @arg 0x0 : ldousb disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_ldousb(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->PWR, SYSCFG_PWR_LDOUSBEN) == (SYSCFG_PWR_LDOUSBEN)); +} + +/** + * @brief Set VRES voltage divider power supply selection + * @param syscfg SYSCFG Instance + * @param ressrc voltage divider power supply selection + @arg @ref MD_SYSCFG_PWR_VREFINT + @arg @ref MD_SYSCFG_PWR_VDDA + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_vref_source(SYSCFG_TypeDef *syscfg, uint32_t ressrc) +{ + MODIFY_REG(syscfg->PWR, SYSCFG_PWR_RESSRC, ressrc << SYSCFG_PWR_RESSRC_POS); +} + +/** + * @brief Get VRES voltage divider power supply selection + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_PWR_VREFINT + @arg @ref MD_SYSCFG_PWR_VDDA + */ +__STATIC_INLINE uint32_t md_syscfg_get_vref_source(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->PWR, SYSCFG_PWR_RESSRC) >> SYSCFG_PWR_RESSRC_POS); +} + +/** + * @brief Set VRES voltage divider circuit switch enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_vref(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->PWR, SYSCFG_PWR_RESEN); +} + +/** + * @brief Set VRES voltage divider circuit switch disable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_vref(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->PWR, SYSCFG_PWR_RESEN); +} +/** + * @brief Check if VRES voltage divider circuit switch is enabled + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Vref enable + * @arg 0x0 : Vref disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_vref(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->PWR, SYSCFG_PWR_RESEN) == (SYSCFG_PWR_RESEN)); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group4 IRSEL + * @{ + */ +/** + * @brief Set SYSCFG_IRSEL Register + * @param syscfg SYSCFG Instance + * @param irsel + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_irsel(SYSCFG_TypeDef *syscfg, uint32_t irsel) +{ + WRITE_REG(syscfg->IRSEL, irsel); +} + +/** + * @brief Get SYSCFG_IRSEL Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_irsel(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->IRSEL)); +} + +/** + * @brief Set IR Polarity + * @param syscfg SYSCFG Instance + * @param plr This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_PLR_INV_SEL1_AND_SEL2 + * @arg @ref MD_SYSCFG_PLR_SEL1_AND_SEL2 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_ir_polarity(SYSCFG_TypeDef *syscfg, uint32_t plr) +{ + MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_PLR, plr << SYSCFG_IRSEL_PLR_POS); +} +/** + * @brief Get IR Polarity + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_SYSCFG_PLR_INV_SEL1_AND_SEL2 + * @arg @ref MD_SYSCFG_PLR_SEL1_AND_SEL2 + */ +__STATIC_INLINE uint32_t md_syscfg_get_ir_polarity(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->IRSEL, SYSCFG_IRSEL_PLR) >> SYSCFG_IRSEL_PLR_POS); +} +/** + * @brief Set IR Select 2 + * @param syscfg SYSCFG Instance + * @param sel2 This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_SEL2_OFF + * @arg @ref MD_SYSCFG_SEL2_GP16C2T4_CH1 + * @arg @ref MD_SYSCFG_SEL2_GP16C2T4_CH2 + * @arg @ref MD_SYSCFG_SEL2_UART2_TX + * @arg @ref MD_SYSCFG_SEL2_UART4_TX + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_ir_source2(SYSCFG_TypeDef *syscfg, uint32_t sel2) +{ + MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_SEL2, sel2 << SYSCFG_IRSEL_SEL2_POSS); +} +/** + * @brief Get IR Select 2 + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_SYSCFG_SEL2_OFF + * @arg @ref MD_SYSCFG_SEL2_GP16C2T4_CH1 + * @arg @ref MD_SYSCFG_SEL2_GP16C2T4_CH2 + * @arg @ref MD_SYSCFG_SEL2_UART2_TX + * @arg @ref MD_SYSCFG_SEL2_UART4_TX + */ +__STATIC_INLINE uint32_t md_syscfg_get_ir_source2(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->IRSEL, SYSCFG_IRSEL_SEL2) >> SYSCFG_IRSEL_SEL2_POSS); +} +/** + * @brief Set IR Select 1 + * @param syscfg SYSCFG Instance + * @param sel1 This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_SEL1_OFF + * @arg @ref MD_SYSCFG_SEL1_GP16C2T2_CH1 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T2_CH2 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T3_CH1 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T3_CH2 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_ir_source1(SYSCFG_TypeDef *syscfg, uint32_t sel1) +{ + MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_SEL1, sel1 << SYSCFG_IRSEL_SEL1_POSS); +} +/** + * @brief Get IR Select 1 + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_SYSCFG_SEL1_OFF + * @arg @ref MD_SYSCFG_SEL1_GP16C2T2_CH1 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T2_CH2 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T3_CH1 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T3_CH2 + */ +__STATIC_INLINE uint32_t md_syscfg_get_ir_source1(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->IRSEL, SYSCFG_IRSEL_SEL1) >> SYSCFG_IRSEL_SEL1_POSS); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group5 SYSTRIM + * @{ + */ +/** + * @brief Get SYSCFG_SYSTRIM Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_systrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->SYSTRIM)); +} + +/** + * @brief Get USB LDO calibration value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_usbldotrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->SYSTRIM, SYSCFG_SYSTRIM_USBLDOTRIM) >> SYSCFG_SYSTRIM_USBLDOTRIM_POSS); +} + +/** + * @brief Get Programmable low voltage detection calibration value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_lvdtrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->SYSTRIM, SYSCFG_SYSTRIM_LVDTRIM) >> SYSCFG_SYSTRIM_LVDTRIM_POSS); +} + +/** + * @brief Get BandGap reference voltage calibration value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_bandgaptrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->SYSTRIM, SYSCFG_SYSTRIM_BGTRIM) >> SYSCFG_SYSTRIM_BGTRIM_POSS); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group6 CLKTRIM + * @{ + */ +/** + * @brief Get SYSCFG_CLKTRIM Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_clktrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->CLKTRIM)); +} + +/** + * @brief Get PLL FNS control + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_pllfnstrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->CLKTRIM, SYSCFG_CLKTRIM_PLLFNS) >> SYSCFG_CLKTRIM_PLLFNS_POSS); +} + +/** + * @brief Get HRC 48MHz clock calibration value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_hrc48trim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->CLKTRIM, SYSCFG_CLKTRIM_HRC48TRIM) >> SYSCFG_CLKTRIM_HRC48TRIM_POSS); +} + +/** + * @brief Get LRC clock calibration value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_lrctrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->CLKTRIM, SYSCFG_CLKTRIM_LRCTRIM) >> SYSCFG_CLKTRIM_LRCTRIM_POSS); +} + +/** + * @brief Get HRC clock calibration value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_hrctrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->CLKTRIM, SYSCFG_CLKTRIM_HRCTRIM) >> SYSCFG_CLKTRIM_HRCTRIMM_POSS); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group7 OSCTRIM + * @{ + */ +/** + * @brief Get SYSCFG_OSCTRIM Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_osctrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->OSCTRIM)); +} + +/** + * @brief Get LOSC clock stable count value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_losc_ready_count(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->OSCTRIM, SYSCFG_OSCTRIM_LOSCRCNT) >> SYSCFG_OSCTRIM_LOSCRCNT_POSS); +} + +/** + * @brief Get LOSC current selection + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_losc_current_select(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->OSCTRIM, SYSCFG_OSCTRIM_LOSCCURSEL) >> SYSCFG_OSCTRIM_LOSCCURSEL_POSS); +} + +/** + * @brief Get HOSC clock stable count value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_hosc_ready_count(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->OSCTRIM, SYSCFG_OSCTRIM_HOSCRCNT) >> SYSCFG_OSCTRIM_HOSCRCNT_POSS); +} + +/** + * @brief Get HOSC current selection + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_hosc_current_select(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->OSCTRIM, SYSCFG_OSCTRIM_HOSCCURSEL) >> SYSCFG_OSCTRIM_HOSCCURSEL_POSS); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group8 IPTRIM + * @{ + */ +/** + * @brief Get SYSCFG_IPTRIM Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_iptrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->IPTRIM)); +} + +/** + * @brief Get Comparator 2 calibration value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_cmp2trim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->IPTRIM, SYSCFG_IPTRIM_CMP2TRIM) >> SYSCFG_IPTRIM_CMP2TRIM_POSS); +} + +/** + * @brief Get Comparator 1 calibration value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_option_cmp1trim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->IPTRIM, SYSCFG_IPTRIM_CMP1TRIM) >> SYSCFG_IPTRIM_CMP1TRIM_POSS); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group9 AHBIPEN + * @{ + */ +/** + * @brief Get SYSCFG_AHBIPEN Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_ahbipen(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->AHBIPEN)); +} + +/** + * @brief Get GPIO D Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpiod exist + * @arg 0x0 : gpiod non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gpiod_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_GPDEN) == (SYSCFG_AHBIPEN_GPDEN)); +} + +/** + * @brief Get GPIO C Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpioc exist + * @arg 0x0 : gpioc non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gpioc_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_GPCEN) == (SYSCFG_AHBIPEN_GPCEN)); +} + +/** + * @brief Get GPIO B Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpiob exist + * @arg 0x0 : gpiob non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gpiob_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_GPBEN) == (SYSCFG_AHBIPEN_GPBEN)); +} + +/** + * @brief Get GPIO A Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gpioa exist + * @arg 0x0 : gpioa non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gpioa_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_GPAEN) == (SYSCFG_AHBIPEN_GPAEN)); +} + +/** + * @brief Get CALC Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : calc exist + * @arg 0x0 : calc non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_calc_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_CALCEN) == (SYSCFG_AHBIPEN_CALCEN)); +} + +/** + * @brief Get USB Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : usb exist + * @arg 0x0 : usb non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_usb_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_USBEN) == (SYSCFG_AHBIPEN_USBEN)); +} + +/** + * @brief Get AES Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : aes exist + * @arg 0x0 : aes non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_aes_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_AESEN) == (SYSCFG_AHBIPEN_AESEN)); +} + +/** + * @brief Get CRC Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : crc exist + * @arg 0x0 : crc non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_crc_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_CRCEN) == (SYSCFG_AHBIPEN_CRCEN)); +} + +/** + * @brief Get CSU Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : csu exist + * @arg 0x0 : csu non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_csu_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_CSUEN) == (SYSCFG_AHBIPEN_CSUEN)); +} + +/** + * @brief Get KBCU Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : kbcu exist + * @arg 0x0 : kbcu non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_kbcu_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_KBCUEN) == (SYSCFG_AHBIPEN_KBCUEN)); +} + +/** + * @brief Get RTC Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : rtc exist + * @arg 0x0 : rtc non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_rtc_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_RTCEN) == (SYSCFG_AHBIPEN_RTCEN)); +} + +/** + * @brief Get DMA1 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : dma1 exist + * @arg 0x0 : dma1 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_dma1_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->AHBIPEN, SYSCFG_AHBIPEN_DMA1EN) == (SYSCFG_AHBIPEN_DMA1EN)); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group10 APB1IPEN + * @{ + */ +/** + * @brief Get SYSCFG_APB1IPEN Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_apb1ipen(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->APB1IPEN)); +} + +/** + * @brief Get I2C2 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : i2c2 exist + * @arg 0x0 : i2c2 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_i2c2_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_I2C2EN) == (SYSCFG_APB1IPEN_I2C2EN)); +} + +/** + * @brief Get I2C1 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : i2c1 exist + * @arg 0x0 : i2c1 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_i2c1_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_I2C1EN) == (SYSCFG_APB1IPEN_I2C1EN)); +} + +/** + * @brief Get UART4 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart4 exist + * @arg 0x0 : uart4 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_uart4_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_UART4EN) == (SYSCFG_APB1IPEN_UART4EN)); +} + +/** + * @brief Get UART3 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart3 exist + * @arg 0x0 : uart3 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_uart3_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_UART3EN) == (SYSCFG_APB1IPEN_UART3EN)); +} + +/** + * @brief Get UART2 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart2 exist + * @arg 0x0 : uart2 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_uart2_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_UART2EN) == (SYSCFG_APB1IPEN_UART2EN)); +} + +/** + * @brief Get SPI3 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi3 exist + * @arg 0x0 : spi3 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_spi3_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_SPI3EN) == (SYSCFG_APB1IPEN_SPI3EN)); +} + +/** + * @brief Get SPI2 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi2 exist + * @arg 0x0 : spi2 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_spi2_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_SPI2EN) == (SYSCFG_APB1IPEN_SPI2EN)); +} + +/** + * @brief Get IWDT Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : iwdt exist + * @arg 0x0 : iwdt non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_iwdt_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_IWDTEN) == (SYSCFG_APB1IPEN_IWDTEN)); +} + +/** + * @brief Get WWDT Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : wwdt exist + * @arg 0x0 : wwdt non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_wwdt_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_WWDTEN) == (SYSCFG_APB1IPEN_WWDTEN)); +} + +/** + * @brief Get BS16T1 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : bs16t1 exist + * @arg 0x0 : bs16t1 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_bs16t1_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_BS16T1EN) == (SYSCFG_APB1IPEN_BS16T1EN)); +} + +/** + * @brief Get GP16C4T3 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c4t3 exist + * @arg 0x0 : gp16c4t3 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gp16c4t3_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_GP16C4T3EN) == (SYSCFG_APB1IPEN_GP16C4T3EN)); +} + +/** + * @brief Get GP16C4T2 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c4t2 exist + * @arg 0x0 : gp16c4t2 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gp16c4t2_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_GP16C4T2EN) == (SYSCFG_APB1IPEN_GP16C4T2EN)); +} + +/** + * @brief Get GP16C4T1 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c4t1 exist + * @arg 0x0 : gp16c4t1 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gp16c4t1_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_GP16C4T1EN) == (SYSCFG_APB1IPEN_GP16C4T1EN)); +} + +/** + * @brief Get GP32C4T1 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp32c4t1 exist + * @arg 0x0 : gp32c4t1 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gp32c4t1_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB1IPEN, SYSCFG_APB1IPEN_GP32C4T1EN) == (SYSCFG_APB1IPEN_GP32C4T1EN)); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group11 APB2IPEN + * @{ + */ +/** + * @brief Get SYSCFG_APB2IPEN Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_apb2ipen(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->APB2IPEN)); +} + +/** + * @brief Get CMP Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : cmp exist + * @arg 0x0 : cmp non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_cmp_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB2IPEN, SYSCFG_APB2IPEN_CMPEN) == (SYSCFG_APB2IPEN_CMPEN)); +} + +/** + * @brief Get GP16C2T4 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t4 exist + * @arg 0x0 : gp16c2t4 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gp16c2t4_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB2IPEN, SYSCFG_APB2IPEN_GP16C2T4EN) == (SYSCFG_APB2IPEN_GP16C2T4EN)); +} + +/** + * @brief Get GP16C2T3 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t3 exist + * @arg 0x0 : gp16c2t3 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gp16c2t3_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB2IPEN, SYSCFG_APB2IPEN_GP16C2T3EN) == (SYSCFG_APB2IPEN_GP16C2T3EN)); +} + +/** + * @brief Get GP16C2T2 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t2 exist + * @arg 0x0 : gp16c2t2 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gp16c2t2_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB2IPEN, SYSCFG_APB2IPEN_GP16C2T2EN) == (SYSCFG_APB2IPEN_GP16C2T2EN)); +} + +/** + * @brief Get GP16C2T1 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : gp16c2t1 exist + * @arg 0x0 : gp16c2t1 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_gp16c2t1_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB2IPEN, SYSCFG_APB2IPEN_GP16C2T1EN) == (SYSCFG_APB2IPEN_GP16C2T1EN)); +} + +/** + * @brief Get UART1 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : uart1 exist + * @arg 0x0 : uart1 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_uart1_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB2IPEN, SYSCFG_APB2IPEN_UART1EN) == (SYSCFG_APB2IPEN_UART1EN)); +} + +/** + * @brief Get SPI1 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : spi1 exist + * @arg 0x0 : spi1 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_spi1_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB2IPEN, SYSCFG_APB2IPEN_SPI1EN) == (SYSCFG_APB2IPEN_SPI1EN)); +} + +/** + * @brief Get AD16C4T1 Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : ad16c4t1 exist + * @arg 0x0 : ad16c4t1 non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_ad16c4t1_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB2IPEN, SYSCFG_APB2IPEN_AD16C4T1EN) == (SYSCFG_APB2IPEN_AD16C4T1EN)); +} + +/** + * @brief Get ADC Peripheral valid state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : adc exist + * @arg 0x0 : adc non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_adc_exist(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->APB2IPEN, SYSCFG_APB2IPEN_ADCEN) == (SYSCFG_APB2IPEN_ADCEN)); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group12 MEMMOD + * @{ + */ +/** + * @brief Get SYSCFG_MEMMOD Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_memmod(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->MEMMOD)); +} + +/** + * @brief Get memory size + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_SMOD_32KB + @arg @ref MD_SYSCFG_SMOD_16KB + @arg @ref MD_SYSCFG_SMOD_8KB + @arg @ref MD_SYSCFG_SMOD_4KB + @arg @ref MD_SYSCFG_SMOD_2KB + */ +__STATIC_INLINE uint32_t md_syscfg_get_sram_size(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->MEMMOD, SYSCFG_MEMMOD_SMOD) >> SYSCFG_MEMMOD_SMOD_POSS); +} + +/** + * @brief Get flash size + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_FMOD_256KB + @arg @ref MD_SYSCFG_FMOD_128KB + @arg @ref MD_SYSCFG_FMOD_64KB + @arg @ref MD_SYSCFG_FMOD_32KB + @arg @ref MD_SYSCFG_FMOD_16KB + */ +__STATIC_INLINE uint32_t md_syscfg_get_flash_size(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->MEMMOD, SYSCFG_MEMMOD_FMOD) >> SYSCFG_MEMMOD_FMOD_POSS); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group13 ADCVREF + * @{ + */ +/** + * @brief Get ADC reference voltage measurement value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_adc_reference(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->ADCVREF, SYSCFG_ADCVREF_ADCVREF)); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group14 ADCTEMP + * @{ + */ +/** + * @brief Get SYSCFG_ADCTEMP Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_adctemp(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->ADCTEMP)); +} + +/** + * @brief Get ADC temperature sensor high temperature measurement value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_adc_high_temperature_reference(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->ADCTEMP, SYSCFG_ADCTEMP_ADCTEMPH) >> SYSCFG_ADCTEMP_ADCTEMPH_POSS); +} + +/** + * @brief Get ADC temperature sensor low temperature measurement value + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_adc_low_temperature_reference(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->ADCTEMP, SYSCFG_ADCTEMP_ADCTEMPL) >> SYSCFG_ADCTEMP_ADCTEMPL_POSS); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group15 SYSSET + * @{ + */ +/** + * @brief Get SYSCFG_SYSSET Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_sysset(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->SYSSET)); +} + +/** + * @brief Get User configuration word IWDT switch + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_iwdt_hardware_enable(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->SYSSET, SYSCFG_SYSSET_SYS_IWDTEN) >> SYSCFG_SYSSET_SYS_IWDTEN_POSS); +} + +/** + * @brief Get User configuration word IWDT switch + * @param syscfg SYSCFG Instance + * @retval + */ +__STATIC_INLINE uint32_t md_syscfg_get_bor_hardware_enable(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->SYSSET, SYSCFG_SYSSET_SYS_BOREN) >> SYSCFG_SYSSET_SYS_BOREN_POSS); +} + +/** + * @brief Get User configuration word IWDT switch + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_SYS_BORLS_LV0 + @arg @ref MD_SYSCFG_SYS_BORLS_LV1 + @arg @ref MD_SYSCFG_SYS_BORLS_LV2 + @arg @ref MD_SYSCFG_SYS_BORLS_LV3 + @arg @ref MD_SYSCFG_SYS_BORLS_LV4 + @arg @ref MD_SYSCFG_SYS_BORLS_LV5 + @arg @ref MD_SYSCFG_SYS_BORLS_LV6 + @arg @ref MD_SYSCFG_SYS_BORLS_LV7 + */ +__STATIC_INLINE uint32_t md_syscfg_get_bor_level_hardware_select(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->SYSSET, SYSCFG_SYSSET_SYS_BORLS) >> SYSCFG_SYSSET_SYS_BORLS_POSS); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group16 CFG + * @{ + */ +/** + * @brief Set SYSCFG_CFG Register + * @param syscfg SYSCFG Instance + * @param cfg + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_cfg(SYSCFG_TypeDef *syscfg, uint32_t cfg) +{ + WRITE_REG(syscfg->CFG, cfg); +} + +/** + * @brief Get SYSCFG_CFG Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->CFG)); +} + +/** + * @brief Set DBG Halt enable bit + * @note Set bit to stopped the counter clock when the core is halted + * @param syscfg SYSCFG Instance + * @param dbghen This parameter can be one of the following values: + @arg @ref MD_SYSCFG_DBGHEN_IWDT + @arg @ref MD_SYSCFG_DBGHEN_WWDT + @arg @ref MD_SYSCFG_DBGHEN_I2C2 + @arg @ref MD_SYSCFG_DBGHEN_I2C1 + @arg @ref MD_SYSCFG_DBGHEN_BS16T1 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T3 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T2 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T1 + @arg @ref MD_SYSCFG_DBGHEN_GP32C4T1 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T4 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T3 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T2 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T1 + @arg @ref MD_SYSCFG_DBGHEN_AD16C4T1 + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_debug_hault(SYSCFG_TypeDef *syscfg, uint32_t dbghen) +{ + SET_BIT(syscfg->CFG, dbghen << SYSCFG_CFG_DBGHEN_POSS); +} + +/** + * @brief Set DBG Halt disable bit + * @note Set bit to let the counter clock continuous output when the core is halted + * @param syscfg SYSCFG Instance + * @param dbghen This parameter can be one of the following values: + @arg @ref MD_SYSCFG_DBGHEN_IWDT + @arg @ref MD_SYSCFG_DBGHEN_WWDT + @arg @ref MD_SYSCFG_DBGHEN_I2C2 + @arg @ref MD_SYSCFG_DBGHEN_I2C1 + @arg @ref MD_SYSCFG_DBGHEN_BS16T1 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T3 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T2 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T1 + @arg @ref MD_SYSCFG_DBGHEN_GP32C4T1 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T4 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T3 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T2 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T1 + @arg @ref MD_SYSCFG_DBGHEN_AD16C4T1 + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_debug_hault(SYSCFG_TypeDef *syscfg, uint32_t dbghen) +{ + CLEAR_BIT(syscfg->CFG, dbghen << SYSCFG_CFG_DBGHEN_POSS); +} + +/** + * @brief Get DBG Halt enable bit + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_DBGHEN_IWDT + @arg @ref MD_SYSCFG_DBGHEN_WWDT + @arg @ref MD_SYSCFG_DBGHEN_I2C2 + @arg @ref MD_SYSCFG_DBGHEN_I2C1 + @arg @ref MD_SYSCFG_DBGHEN_BS16T1 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T3 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T2 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T1 + @arg @ref MD_SYSCFG_DBGHEN_GP32C4T1 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T4 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T3 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T2 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T1 + @arg @ref MD_SYSCFG_DBGHEN_AD16C4T1 + */ +__STATIC_INLINE uint32_t md_syscfg_get_debug_hault(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->CFG, SYSCFG_CFG_DBGHEN) >> SYSCFG_CFG_DBGHEN_POSS); +} + +/** + * @brief DBG Halt bit is enabled + * @param syscfg SYSCFG Instance + @arg @ref MD_SYSCFG_DBGHEN_IWDT + @arg @ref MD_SYSCFG_DBGHEN_WWDT + @arg @ref MD_SYSCFG_DBGHEN_I2C2 + @arg @ref MD_SYSCFG_DBGHEN_I2C1 + @arg @ref MD_SYSCFG_DBGHEN_BS16T1 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T3 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T2 + @arg @ref MD_SYSCFG_DBGHEN_GP16C4T1 + @arg @ref MD_SYSCFG_DBGHEN_GP32C4T1 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T4 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T3 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T2 + @arg @ref MD_SYSCFG_DBGHEN_GP16C2T1 + @arg @ref MD_SYSCFG_DBGHEN_AD16C4T1 + * @retval The retval can be one of the following values: + * @arg 0x1 : IP debug hault enable + * @arg 0x0 : IP debug hault disable + */ +__STATIC_INLINE uint32_t md_rcu_is_enabled_debug_hault(SYSCFG_TypeDef *syscfg, uint32_t dbgh) +{ + return (READ_BIT(syscfg->CFG, dbgh << SYSCFG_CFG_DBGHEN_POSS) == (dbgh << SYSCFG_CFG_DBGHEN_POSS)); +} + +/** + * @brief Low voltage detection (LVD) event input switch enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_timer_break_lvd(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_LVDLCK); +} +/** + * @brief Low voltage detection (LVD) event input switch disable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_timer_break_lvd(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_LVDLCK); +} +/** + * @brief Check if Low voltage detection (LVD) event input switch is enabled + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : LVD Timer break function enable + * @arg 0x0 : LVD Timer break function disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_timer_break_lvd(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_LVDLCK) == (SYSCFG_CFG_LVDLCK)); +} + +/** + * @brief Clock Security Event (CSS) input switch enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_timer_break_css(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_CSSLCK); +} +/** + * @brief Clock Security Event (CSS) input switch disable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_timer_break_css(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CSSLCK); +} +/** + * @brief Check if Clock Security Event (CSS) input switch is enabled + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : CSS Timer break function enable + * @arg 0x0 : CSS Timer break function disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_timer_break_css(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CSSLCK) == (SYSCFG_CFG_CSSLCK)); +} + +/** + * @brief CPU Lockup event input switch enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_timer_break_cpu_lockup(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_CPULCK); +} +/** + * @brief CPU Lockup event input switch disable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_timer_break_cpu_lockup(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CPULCK); +} +/** + * @brief Check if CPU Lockup event input switch is enabled + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : CPU Lockup Timer break function enable + * @arg 0x0 : CPU Lockup Timer break function disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_timer_break_cpu_lockup(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CPULCK) == (SYSCFG_CFG_CPULCK)); +} + +/** + * @brief Get Backup register bus idle flag + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_is_active_flag_backup_bus_idle(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_BKREADY) == (SYSCFG_CFG_BKREADY)); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group17 PWRCON + * @{ + */ +/** + * @brief Set SYSCFG_PWRCON register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_pwrcon(SYSCFG_TypeDef *syscfg, uint32_t pwrcon) +{ + WRITE_REG(syscfg->PWRCON, pwrcon); +} + +/** + * @brief Get SYSCFG_PWRCON Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_pwrcon(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->PWRCON)); +} + +/** + * @brief Get IWDT state + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : IWDT enable + * @arg 0x0 : IWDT disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_iwdt(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->PWRCON, SYSCFG_PWRCON_IWDTEN) == (SYSCFG_PWRCON_IWDTEN)); +} + +/** + * @brief Low voltage reset switch enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_bor(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->PWRCON, SYSCFG_PWRCON_BOREN); +} +/** + * @brief Low voltage reset switch disable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_bor(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->PWRCON, SYSCFG_PWRCON_BOREN); +} +/** + * @brief Check if Low voltage reset switch is enabled + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_is_enable_bor(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->PWRCON, SYSCFG_PWRCON_BOREN) == (SYSCFG_PWRCON_BOREN)); +} + +/** + * @brief Set Low voltage reset voltage interval selection + * @param syscfg SYSCFG Instance + * @param borls Low voltage reset voltage interval selection + @arg @ref MD_SYSCFG_BORLS_LV0 + @arg @ref MD_SYSCFG_BORLS_LV1 + @arg @ref MD_SYSCFG_BORLS_LV2 + @arg @ref MD_SYSCFG_BORLS_LV3 + @arg @ref MD_SYSCFG_BORLS_LV4 + @arg @ref MD_SYSCFG_BORLS_LV5 + @arg @ref MD_SYSCFG_BORLS_LV6 + @arg @ref MD_SYSCFG_BORLS_LV7 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bor_level(SYSCFG_TypeDef *syscfg, uint32_t borls) +{ + MODIFY_REG(syscfg->PWRCON, SYSCFG_PWRCON_BORLS, borls << SYSCFG_PWRCON_BORLS_POSS); +} + +/** + * @brief Get Low voltage reset voltage interval selection + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_BORLS_LV0 + @arg @ref MD_SYSCFG_BORLS_LV1 + @arg @ref MD_SYSCFG_BORLS_LV2 + @arg @ref MD_SYSCFG_BORLS_LV3 + @arg @ref MD_SYSCFG_BORLS_LV4 + @arg @ref MD_SYSCFG_BORLS_LV5 + @arg @ref MD_SYSCFG_BORLS_LV6 + @arg @ref MD_SYSCFG_BORLS_LV7 + */ +__STATIC_INLINE uint32_t md_syscfg_get_bor_level(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->PWRCON, SYSCFG_PWRCON_BORLS) >> SYSCFG_PWRCON_BORLS_POSS); +} + +/** + * @brief Low voltage detection switch enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_lvd(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->PWRCON, SYSCFG_PWRCON_LVDEN); +} +/** + * @brief Low voltage detection switch disable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_lvd(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->PWRCON, SYSCFG_PWRCON_LVDEN); +} +/** + * @brief Check if Low voltage detection switch is enabled + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : LVD enable + * @arg 0x0 : LVD disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_lvd(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->PWRCON, SYSCFG_PWRCON_LVDEN) == (SYSCFG_PWRCON_LVDEN)); +} + +/** + * @brief Set Low voltage detection voltage range selection + * @param syscfg SYSCFG Instance + * @param lvdls Low voltage detection voltage range selection + @arg @ref MD_SYSCFG_LVDLS_R1V9_F2V + @arg @ref MD_SYSCFG_LVDLS_R2V1_F2V2 + @arg @ref MD_SYSCFG_LVDLS_R2V3_F2V4 + @arg @ref MD_SYSCFG_LVDLS_R2V5_F2V6 + @arg @ref MD_SYSCFG_LVDLS_R2V7_F2V8 + @arg @ref MD_SYSCFG_LVDLS_R2V9_F3V + @arg @ref MD_SYSCFG_LVDLS_R3V1_F3V2 + @arg @ref MD_SYSCFG_LVDLS_R3V3_F3V4 + @arg @ref MD_SYSCFG_LVDLS_R3V5_F3V6 + @arg @ref MD_SYSCFG_LVDLS_R3V7_F3V8 + @arg @ref MD_SYSCFG_LVDLS_R3V9_F4V + @arg @ref MD_SYSCFG_LVDLS_R4V1_F4V2 + @arg @ref MD_SYSCFG_LVDLS_R4V3_F4V4 + @arg @ref MD_SYSCFG_LVDLS_R4V5_F4V6 + @arg @ref MD_SYSCFG_LVDLS_R4V7_F4V8 + @arg @ref MD_SYSCFG_LVDLS_R4V9_F5V + @arg @ref MD_SYSCFG_LVDLS_R4V9_F5V + * @retval None +*/ +__STATIC_INLINE void md_syscfg_set_lvd_level(SYSCFG_TypeDef *syscfg, uint32_t lvdls) +{ + MODIFY_REG(syscfg->PWRCON, SYSCFG_PWRCON_LVDLS, lvdls << SYSCFG_PWRCON_LVDLS_POSS); +} + +/** + * @brief Get Low voltage detection voltage range selection + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_LVDLS_R1V9_F2V + @arg @ref MD_SYSCFG_LVDLS_R2V1_F2V2 + @arg @ref MD_SYSCFG_LVDLS_R2V3_F2V4 + @arg @ref MD_SYSCFG_LVDLS_R2V5_F2V6 + @arg @ref MD_SYSCFG_LVDLS_R2V7_F2V8 + @arg @ref MD_SYSCFG_LVDLS_R2V9_F3V + @arg @ref MD_SYSCFG_LVDLS_R3V1_F3V2 + @arg @ref MD_SYSCFG_LVDLS_R3V3_F3V4 + @arg @ref MD_SYSCFG_LVDLS_R3V5_F3V6 + @arg @ref MD_SYSCFG_LVDLS_R3V7_F3V8 + @arg @ref MD_SYSCFG_LVDLS_R3V9_F4V + @arg @ref MD_SYSCFG_LVDLS_R4V1_F4V2 + @arg @ref MD_SYSCFG_LVDLS_R4V3_F4V4 + @arg @ref MD_SYSCFG_LVDLS_R4V5_F4V6 + @arg @ref MD_SYSCFG_LVDLS_R4V7_F4V8 + @arg @ref MD_SYSCFG_LVDLS_R4V9_F5V + */ +__STATIC_INLINE uint32_t md_syscfg_get_lvd_level(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->PWRCON, SYSCFG_PWRCON_LVDLS) >> SYSCFG_PWRCON_LVDLS_POSS); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group18 WKTRIM + * @{ + */ +/** + * @brief Set SYSCFG_WKTRIM register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wktrim(SYSCFG_TypeDef *syscfg, uint32_t wktrim) +{ + WRITE_REG(syscfg->WKTRIM, wktrim); +} + +/** + * @brief Get SYSCFG_WKTRIM Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_wktrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->WKTRIM)); +} + +/** + * @brief Set External low-speed clock oscillator, clock stabilization time counter + * @param syscfg SYSCFG Instance + * @param loscrcnt clock stabilization time counter + @arg @ref MD_SYSCFG_LOSCRCNT_2048 + @arg @ref MD_SYSCFG_LOSCRCNT_4096 + @arg @ref MD_SYSCFG_LOSCRCNT_8192 + @arg @ref MD_SYSCFG_LOSCRCNT_16384 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_losc_ready_count(SYSCFG_TypeDef *syscfg, uint32_t loscrcnt) +{ + MODIFY_REG(syscfg->WKTRIM, SYSCFG_WKTRIM_LOSCRCNT, loscrcnt << SYSCFG_WKTRIM_LOSCRCNT_POSS); +} + +/** + * @brief Get External low-speed clock oscillator, clock stabilization time counter + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_LOSCRCNT_2048 + @arg @ref MD_SYSCFG_LOSCRCNT_4096 + @arg @ref MD_SYSCFG_LOSCRCNT_8192 + @arg @ref MD_SYSCFG_LOSCRCNT_16384 + */ +__STATIC_INLINE uint32_t md_syscfg_get_losc_ready_count(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->WKTRIM, SYSCFG_WKTRIM_LOSCRCNT) >> SYSCFG_WKTRIM_LOSCRCNT_POSS); +} + +/** + * @brief Set External low-speed clock oscillator, start-up current configuration + * @param syscfg SYSCFG Instance + * @param losccursel Starting current configuration + @arg @ref MD_SYSCFG_LOSCCURSEL_120NA + @arg @ref MD_SYSCFG_LOSCCURSEL_200NA + @arg @ref MD_SYSCFG_LOSCCURSEL_280NA + @arg @ref MD_SYSCFG_LOSCCURSEL_360NA + @arg @ref MD_SYSCFG_LOSCCURSEL_440NA + @arg @ref MD_SYSCFG_LOSCCURSEL_520NA + @arg @ref MD_SYSCFG_LOSCCURSEL_600NA + @arg @ref MD_SYSCFG_LOSCCURSEL_680NA + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_losc_current_select(SYSCFG_TypeDef *syscfg, uint32_t losccursel) +{ + MODIFY_REG(syscfg->WKTRIM, SYSCFG_WKTRIM_LOSCCURSEL, losccursel << SYSCFG_WKTRIM_LOSCCURSEL_POSS); +} + +/** + * @brief Get External low-speed clock oscillator, start-up current configuration + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_LOSCCURSEL_120NA + @arg @ref MD_SYSCFG_LOSCCURSEL_200NA + @arg @ref MD_SYSCFG_LOSCCURSEL_280NA + @arg @ref MD_SYSCFG_LOSCCURSEL_360NA + @arg @ref MD_SYSCFG_LOSCCURSEL_440NA + @arg @ref MD_SYSCFG_LOSCCURSEL_520NA + @arg @ref MD_SYSCFG_LOSCCURSEL_600NA + @arg @ref MD_SYSCFG_LOSCCURSEL_680NA + */ +__STATIC_INLINE uint32_t md_syscfg_get_losc_current_select(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->WKTRIM, SYSCFG_WKTRIM_LOSCCURSEL) >> SYSCFG_WKTRIM_LOSCCURSEL_POSS); +} + +/** + * @brief Get Low voltage detection (LVD) calibration value + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_lvdtrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->WKTRIM, SYSCFG_WKTRIM_LVDTRIM) >> SYSCFG_WKTRIM_LVDTRIM_POSS); +} + +/** + * @brief Get BandGap calibration value + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg Max Value 15 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_bandgaptrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->WKTRIM, SYSCFG_WKTRIM_BGTRIM) >> SYSCFG_WKTRIM_BGTRIM_POSS); +} + +/** + * @brief Get LRC clock calibration value + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg Max Value 127 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_lrctrim(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->WKTRIM, SYSCFG_WKTRIM_LRCTRIM) >> SYSCFG_WKTRIM_LRCTRIM_POSS); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group19 WKUP + * @{ + */ +/** + * @brief Set SYSCFG_WKUP register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wkup(SYSCFG_TypeDef *syscfg, uint32_t wkup) +{ + WRITE_REG(syscfg->WKUP, wkup); +} + +/** + * @brief Get SYSCFG_WKUP Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_wkup(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->WKUP)); +} + +/** + * @brief Enable Wake-up event rising edge mode + * @param syscfg SYSCFG Instance + * @param wkeg Wake-up event rising edge or falling edge mode + @arg @ref MD_SYSCFG_WKEG_USBDP + @arg @ref MD_SYSCFG_WKEG_USBDM + @arg @ref MD_SYSCFG_WKEG_RTC + @arg @ref MD_SYSCFG_WKEG_IWDT + @arg @ref MD_SYSCFG_WKEG_LVD + @arg @ref MD_SYSCFG_WKEG_NRST + @arg @ref MD_SYSCFG_WKEG_WKUP7 + @arg @ref MD_SYSCFG_WKEG_WKUP6 + @arg @ref MD_SYSCFG_WKEG_WKUP5 + @arg @ref MD_SYSCFG_WKEG_WKUP4 + @arg @ref MD_SYSCFG_WKEG_WKUP3 + @arg @ref MD_SYSCFG_WKEG_WKUP2 + @arg @ref MD_SYSCFG_WKEG_WKUP1 + @arg @ref MD_SYSCFG_WKEG_WKUP0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_wakeup_edge_rising(SYSCFG_TypeDef *syscfg, uint32_t wkeg) +{ + SET_BIT(syscfg->WKUP, wkeg << SYSCFG_WKUP_WKEG_POSS); +} + +/** + * @brief Enable Wake-up event falling edge mode + * @param syscfg SYSCFG Instance + * @param wkeg Wake-up event rising edge or falling edge mode + @arg @ref MD_SYSCFG_WKEG_USBDP + @arg @ref MD_SYSCFG_WKEG_USBDM + @arg @ref MD_SYSCFG_WKEG_RTC + @arg @ref MD_SYSCFG_WKEG_IWDT + @arg @ref MD_SYSCFG_WKEG_LVD + @arg @ref MD_SYSCFG_WKEG_NRST + @arg @ref MD_SYSCFG_WKEG_WKUP7 + @arg @ref MD_SYSCFG_WKEG_WKUP6 + @arg @ref MD_SYSCFG_WKEG_WKUP5 + @arg @ref MD_SYSCFG_WKEG_WKUP4 + @arg @ref MD_SYSCFG_WKEG_WKUP3 + @arg @ref MD_SYSCFG_WKEG_WKUP2 + @arg @ref MD_SYSCFG_WKEG_WKUP1 + @arg @ref MD_SYSCFG_WKEG_WKUP0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_wakeup_edge_falling(SYSCFG_TypeDef *syscfg, uint32_t wkeg) +{ + CLEAR_BIT(syscfg->WKUP, wkeg << SYSCFG_WKUP_WKEG_POSS); +} + +/** + * @brief Get Wake-up event rising edge or falling edge mode + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_WKEG_USBDP + @arg @ref MD_SYSCFG_WKEG_USBDM + @arg @ref MD_SYSCFG_WKEG_RTC + @arg @ref MD_SYSCFG_WKEG_IWDT + @arg @ref MD_SYSCFG_WKEG_LVD + @arg @ref MD_SYSCFG_WKEG_NRST + @arg @ref MD_SYSCFG_WKEG_WKUP7 + @arg @ref MD_SYSCFG_WKEG_WKUP6 + @arg @ref MD_SYSCFG_WKEG_WKUP5 + @arg @ref MD_SYSCFG_WKEG_WKUP4 + @arg @ref MD_SYSCFG_WKEG_WKUP3 + @arg @ref MD_SYSCFG_WKEG_WKUP2 + @arg @ref MD_SYSCFG_WKEG_WKUP1 + @arg @ref MD_SYSCFG_WKEG_WKUP0 + * @arg 0x1 : rising edge enable + * @arg 0x0 : falling edge enable + */ +__STATIC_INLINE uint32_t md_syscfg_get_wakeup_edge(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->WKUP, SYSCFG_WKUP_WKEG) >> SYSCFG_WKUP_WKEG_POSS); +} + +/** + * @brief Wake-up event rising edge is enabled + * @param syscfg SYSCFG Instance + @arg @ref MD_SYSCFG_WKEG_USBDP + @arg @ref MD_SYSCFG_WKEG_USBDM + @arg @ref MD_SYSCFG_WKEG_RTC + @arg @ref MD_SYSCFG_WKEG_IWDT + @arg @ref MD_SYSCFG_WKEG_LVD + @arg @ref MD_SYSCFG_WKEG_NRST + @arg @ref MD_SYSCFG_WKEG_WKUP7 + @arg @ref MD_SYSCFG_WKEG_WKUP6 + @arg @ref MD_SYSCFG_WKEG_WKUP5 + @arg @ref MD_SYSCFG_WKEG_WKUP4 + @arg @ref MD_SYSCFG_WKEG_WKUP3 + @arg @ref MD_SYSCFG_WKEG_WKUP2 + @arg @ref MD_SYSCFG_WKEG_WKUP1 + @arg @ref MD_SYSCFG_WKEG_WKUP0 + * @retval The retval can be one of the following values: + * @arg 0x1 : rising edge enable + * @arg 0x0 : falling edge enable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_wakeup_edge_rising(SYSCFG_TypeDef *syscfg, uint32_t wkeg) +{ + return (READ_BIT(syscfg->WKUP, wkeg << SYSCFG_WKUP_WKEG_POSS) == (wkeg << SYSCFG_WKUP_WKEG_POSS)); +} + +/** + * @brief Wake-up event falling edge is enabled + * @param syscfg SYSCFG Instance + The retval can be one of the following values: + @arg @ref MD_SYSCFG_WKEG_USBDP + @arg @ref MD_SYSCFG_WKEG_USBDM + @arg @ref MD_SYSCFG_WKEG_RTC + @arg @ref MD_SYSCFG_WKEG_IWDT + @arg @ref MD_SYSCFG_WKEG_LVD + @arg @ref MD_SYSCFG_WKEG_NRST + @arg @ref MD_SYSCFG_WKEG_WKUP7 + @arg @ref MD_SYSCFG_WKEG_WKUP6 + @arg @ref MD_SYSCFG_WKEG_WKUP5 + @arg @ref MD_SYSCFG_WKEG_WKUP4 + @arg @ref MD_SYSCFG_WKEG_WKUP3 + @arg @ref MD_SYSCFG_WKEG_WKUP2 + @arg @ref MD_SYSCFG_WKEG_WKUP1 + @arg @ref MD_SYSCFG_WKEG_WKUP0 + * @retval The retval can be one of the following values: + * @arg 0x1 : falling edge enable + * @arg 0x0 : rising edge enable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_wakeup_edge_falling(SYSCFG_TypeDef *syscfg, uint32_t wkeg) +{ + return (READ_BIT(syscfg->WKUP, wkeg << SYSCFG_WKUP_WKEG_POSS) == 0); +} + +/** + * @brief Enable Wake-up pin or wake-up event switch + * @param syscfg SYSCFG Instance + * @param wken Wake-up pin or wake-up event switch + @arg @ref MD_SYSCFG_WKEN_USBDP + @arg @ref MD_SYSCFG_WKEN_USBDM + @arg @ref MD_SYSCFG_WKEN_RTC + @arg @ref MD_SYSCFG_WKEN_IWDT + @arg @ref MD_SYSCFG_WKEN_LVD + @arg @ref MD_SYSCFG_WKEN_NRST + @arg @ref MD_SYSCFG_WKEN_WKUP7 + @arg @ref MD_SYSCFG_WKEN_WKUP6 + @arg @ref MD_SYSCFG_WKEN_WKUP5 + @arg @ref MD_SYSCFG_WKEN_WKUP4 + @arg @ref MD_SYSCFG_WKEN_WKUP3 + @arg @ref MD_SYSCFG_WKEN_WKUP2 + @arg @ref MD_SYSCFG_WKEN_WKUP1 + @arg @ref MD_SYSCFG_WKEN_WKUP0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_wakeup(SYSCFG_TypeDef *syscfg, uint32_t wken) +{ + SET_BIT(syscfg->WKUP, wken); +} + +/** + * @brief disable Wake-up pin or wake-up event switch + * @param syscfg SYSCFG Instance + * @param wken Wake-up pin or wake-up event switch + @arg @ref MD_SYSCFG_WKEN_USBDP + @arg @ref MD_SYSCFG_WKEN_USBDM + @arg @ref MD_SYSCFG_WKEN_RTC + @arg @ref MD_SYSCFG_WKEN_IWDT + @arg @ref MD_SYSCFG_WKEN_LVD + @arg @ref MD_SYSCFG_WKEN_NRST + @arg @ref MD_SYSCFG_WKEN_WKUP7 + @arg @ref MD_SYSCFG_WKEN_WKUP6 + @arg @ref MD_SYSCFG_WKEN_WKUP5 + @arg @ref MD_SYSCFG_WKEN_WKUP4 + @arg @ref MD_SYSCFG_WKEN_WKUP3 + @arg @ref MD_SYSCFG_WKEN_WKUP2 + @arg @ref MD_SYSCFG_WKEN_WKUP1 + @arg @ref MD_SYSCFG_WKEN_WKUP0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_wakeup(SYSCFG_TypeDef *syscfg, uint32_t wken) +{ + CLEAR_BIT(syscfg->WKUP, wken); +} + +/** + * @brief Wake-up pin or wake-up event switch is enabled + * @param syscfg SYSCFG Instance + * @param wken Wake-up pin or wake-up event switch + @arg @ref MD_SYSCFG_WKEN_USBDP + @arg @ref MD_SYSCFG_WKEN_USBDM + @arg @ref MD_SYSCFG_WKEN_RTC + @arg @ref MD_SYSCFG_WKEN_IWDT + @arg @ref MD_SYSCFG_WKEN_LVD + @arg @ref MD_SYSCFG_WKEN_NRST + @arg @ref MD_SYSCFG_WKEN_WKUP7 + @arg @ref MD_SYSCFG_WKEN_WKUP6 + @arg @ref MD_SYSCFG_WKEN_WKUP5 + @arg @ref MD_SYSCFG_WKEN_WKUP4 + @arg @ref MD_SYSCFG_WKEN_WKUP3 + @arg @ref MD_SYSCFG_WKEN_WKUP2 + @arg @ref MD_SYSCFG_WKEN_WKUP1 + @arg @ref MD_SYSCFG_WKEN_WKUP0 + * @retval The retval can be one of the following values: + * @arg 0x1 : wakeup event enable + * @arg 0x0 : wakeup event disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enabled_wakeup(SYSCFG_TypeDef *syscfg, uint32_t wken) +{ + return (READ_BIT(syscfg->WKUP, wken) == wken); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group20 WKSR + * @{ + */ +/** + * @brief Set SYSCFG_WKSR register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wksr(SYSCFG_TypeDef *syscfg, uint32_t wksr) +{ + WRITE_REG(syscfg->WKSR, wksr); +} + +/** + * @brief Get SYSCFG_WKSR Register + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_syscfg_get_wksr(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->WKSR)); +} + + +/** + * @brief Clear the wake-up flag + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_clear_flag_wakeup(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->WKSR, SYSCFG_WKSR_WKCLR); +} + +/** + * @brief Set Low power mode selection + * @param syscfg SYSCFG Instance + * @param lpls Low power mode selection + @arg @ref MD_SYSCFG_LPLS_STOP_MODE + @arg @ref MD_SYSCFG_LPLS_STANDBY0_MODE + @arg @ref MD_SYSCFG_LPLS_STANDBY1_MODE + @arg @ref MD_SYSCFG_LPLS_SHUTDOWN_MODE + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_lowpower_mode(SYSCFG_TypeDef *syscfg, uint32_t lpls) +{ + MODIFY_REG(syscfg->WKSR, SYSCFG_WKSR_LPLS, lpls << SYSCFG_WKSR_LPLS_POSS); +} + +/** + * @brief Get Low power mode selection + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_LPLS_STOP_MODE + @arg @ref MD_SYSCFG_LPLS_STANDBY0_MODE + @arg @ref MD_SYSCFG_LPLS_STANDBY1_MODE + @arg @ref MD_SYSCFG_LPLS_SHUTDOWN_MODE + */ +__STATIC_INLINE uint32_t md_syscfg_get_lowpower_mode(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->WKSR, SYSCFG_WKSR_LPLS) >> SYSCFG_WKSR_LPLS_POSS); +} + +/** + * @brief Get Wake flag + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : wakeup flag exist + * @arg 0x0 : wakeup flag non-existent + */ +__STATIC_INLINE uint32_t md_syscfg_is_active_flag_wakeup(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->WKSR, SYSCFG_WKSR_FLAG) == (SYSCFG_WKSR_FLAG)); +} + +/** + * @brief Get Low-power mode wake-up flag + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_FG_USBDP + @arg @ref MD_SYSCFG_FG_USBDM + @arg @ref MD_SYSCFG_FG_RTC + @arg @ref MD_SYSCFG_FG_IWDT + @arg @ref MD_SYSCFG_FG_LVD + @arg @ref MD_SYSCFG_FG_NRST + @arg @ref MD_SYSCFG_FG_WKUP7 + @arg @ref MD_SYSCFG_FG_WKUP6 + @arg @ref MD_SYSCFG_FG_WKUP5 + @arg @ref MD_SYSCFG_FG_WKUP4 + @arg @ref MD_SYSCFG_FG_WKUP3 + @arg @ref MD_SYSCFG_FG_WKUP2 + @arg @ref MD_SYSCFG_FG_WKUP1 + @arg @ref MD_SYSCFG_FG_WKUP0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_wakeup_event(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_BIT(syscfg->WKSR, SYSCFG_WKSR_FG) >> SYSCFG_WKSR_FG_POSS); +} + +/** + * @brief Get Low-power mode wake-up flag + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + @arg @ref MD_SYSCFG_FG_USBDP + @arg @ref MD_SYSCFG_FG_USBDM + @arg @ref MD_SYSCFG_FG_RTC + @arg @ref MD_SYSCFG_FG_IWDT + @arg @ref MD_SYSCFG_FG_LVD + @arg @ref MD_SYSCFG_FG_NRST + @arg @ref MD_SYSCFG_FG_WKUP7 + @arg @ref MD_SYSCFG_FG_WKUP6 + @arg @ref MD_SYSCFG_FG_WKUP5 + @arg @ref MD_SYSCFG_FG_WKUP4 + @arg @ref MD_SYSCFG_FG_WKUP3 + @arg @ref MD_SYSCFG_FG_WKUP2 + @arg @ref MD_SYSCFG_FG_WKUP1 + @arg @ref MD_SYSCFG_FG_WKUP0 + */ +__STATIC_INLINE uint32_t md_syscfg_is_active_flag_wakeup_event(SYSCFG_TypeDef *syscfg, uint32_t wkfg) +{ + return (READ_BIT(syscfg->WKSR, wkfg) == wkfg); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group21 BKREG0 + * @{ + */ +/** + * @brief Set Backup Register 0. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg0 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg0(SYSCFG_TypeDef *syscfg, uint32_t bkreg0) +{ + WRITE_REG(syscfg->BKREG0, bkreg0); +} +/** + * @brief Get Backup Register 0. + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_bkreg0(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->BKREG0)); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group22 BKREG1 + * @{ + */ +/** + * @brief Set Backup Register 1. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg1 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg1(SYSCFG_TypeDef *syscfg, uint32_t bkreg1) +{ + WRITE_REG(syscfg->BKREG1, bkreg1); +} +/** + * @brief Get Backup Register 1. + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_bkreg1(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->BKREG1)); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group23 BKREG2 + * @{ + */ +/** + * @brief Set Backup Register 2. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg2 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg2(SYSCFG_TypeDef *syscfg, uint32_t bkreg2) +{ + WRITE_REG(syscfg->BKREG2, bkreg2); +} +/** + * @brief Get Backup Register 2. + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_bkreg2(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->BKREG2)); +} +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group24 BKREG3 + * @{ + */ +/** + * @brief Set Backup Register 3. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg3 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg3(SYSCFG_TypeDef *syscfg, uint32_t bkreg3) +{ + WRITE_REG(syscfg->BKREG3, bkreg3); +} +/** + * @brief Get Backup Register 3. + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_bkreg3(SYSCFG_TypeDef *syscfg) +{ + return (uint32_t)(READ_REG(syscfg->BKREG3)); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_tick.c b/os/common/ext/CMSIS/ES32/FS026/md/md_tick.c new file mode 100644 index 00000000000..0e0779bfef1 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_tick.c @@ -0,0 +1,234 @@ +/********************************************************************************** + * + * @file md_tick.c + * @brief md_tick C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_tick.h" +#include "md_calc.h" +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (TICK) + +/** @addtogroup TICK TICK + * @brief TICK micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Private function prototypes ------------------------------------------------*/ + +#define CALCON 0 + +/* Private variables ----------------------------------------------------------*/ +/** @defgroup MD_TICK_Private_Variables TICK Private Variables + * @{ + */ +static uint32_t TICKms; +static uint32_t TICK100us; +static uint32_t TICK10us; + +/** + * @} MD_TICK_Private_Variables + */ +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_TICK_Public_Functions TICK Public Functions + * @{ + */ + +/** + * @brief Tick Initialization + * @note This function set the maximun load and enable TICK counter + * @note This function also calculate ms, 100us ans 10us counter + * @param clksrc + @arg @ref MD_SYSTICK_CLKSRC_HCLK_DIV8 + @arg @ref MD_SYSTICK_CLKSRC_HCLK + * @retval None + */ +void md_tick_init(uint8_t clksrc) +{ + uint32_t tick_source; + + if (clksrc) + tick_source = SystemFrequency_AHBClk; + else + tick_source = SystemFrequency_AHBClk / 8; + +#if CALCON + CALC->DIVDR = tick_source; + CALC->DIVSR = 1000; + TICKms = CALC->DIVQR; + CALC->DIVSR = 10000; + TICK100us = CALC->DIVQR; + CALC->DIVSR = 100000; + TICK10us = CALC->DIVQR; +#else + TICKms = tick_source / 1000; + TICK100us = tick_source / 10000; + TICK10us = tick_source / 100000; +#endif + + md_tick_set_rvr_reload(TICK, ((1 << 24) - 1)); /* Maximun ReLoad */ + md_tick_set_cvr_current(TICK, 0); /* Reset CVR */ + md_tick_set_csr_clksrc(TICK, clksrc); /* MCU Clock */ + md_tick_enable_csr_enable(TICK); /* Counter Enable */ +} + +/** + * @brief Retrive the TICK counter and converted to millisecond + * @param None + * @retval The ms value converted by TICK counter + */ +uint32_t md_tick_get_mscnt(void) +{ +#if CALCON + CALC->DIVDR = md_tick_get_cvr_current(); + CALC->DIVSR = TICKms; + return (HDIV->DIVQR); +#else + return (md_tick_get_cvr_current(TICK) / TICKms); +#endif +} + +/** + * @brief Retrive the TICK counter and converted to 100 microseconds + * @param None + * @retval The 100 microseconds value converted by TICK counter + */ +uint32_t md_tick_get_100uscnt(void) +{ +#if CALCON + CALC->DIVDR = md_tick_get_cvr_current(); + CALC->DIVSR = TICK100us; + return (HDIV->DIVQR); +#else + return (md_tick_get_cvr_current(TICK) / TICK100us); +#endif +} + +/** + * @brief Retrive the TICK counter and converted to 10 microseconds + * @param None + * @retval The 10 microseconds value converted by TICK counter + */ +uint32_t md_tick_get_10uscnt(void) +{ +#if CALCON + CALC->DIVDR = md_tick_get_cvr_current(); + CALC->DIVSR = TICK10us; + return (HDIV->DIVQR); +#else + return (md_tick_get_cvr_current(TICK) / TICK10us); +#endif +} + +/** + * @brief Delay based on milliseconds + * @param Unit The number of ms in one delay period + * @param msCnt The counter of delay period + * @note user can use the function to set the delay time, Delay time = Unit*msCnt (ms) + * @retVal None + */ +void md_tick_waitms(uint8_t Unit, uint16_t msCnt) +{ + uint32_t mstime; + + mstime = (1 << 24) - (Unit * TICKms); + + while (msCnt--) + { + md_tick_set_cvr_current(TICK, ((1 << 24) - 1)); /* Reset CVR */ + + while (md_tick_get_cvr_current(TICK) > mstime); + } +} + +/** + * @brief Delay based on 100 microseconds + * @param Unit The number of 100 microseconds in one delay period + * @param msCnt The counter of delay period + * @note user can use the function to set the delay time, Delay time = Unit*usCnt (100us) + * @etVal None + */ +void md_tick_wait100us(uint16_t Unit, uint16_t usCnt) +{ + uint32_t ustime; + + ustime = (1 << 24) - (Unit * TICK100us); + + while (usCnt--) + { + md_tick_set_cvr_current(TICK, ((1 << 24) - 1)); /* Reset CVR */ + + while (md_tick_get_cvr_current(TICK) > ustime); + } +} + +/** + * @brief Delay based on 10 microseconds + * @param Unit The number of 10 microseconds in one delay period + * @param msCnt The counter of delay period + * @note user can use the function to set the delay time, Delay time = Unit*usCnt (10us) + * @etVal None + */ +void md_tick_wait10us(uint16_t Unit, uint16_t usCnt) +{ + uint32_t ustime; + + ustime = (1 << 24) - (Unit * TICK10us); + + while (usCnt--) + { + md_tick_set_cvr_current(TICK, ((1 << 24) - 1)); /* Reset CVR */ + + while (md_tick_get_cvr_current(TICK) > ustime); + } +} + + +/** + * @} MD_TICK_Public_Functions + */ + +/** + * @} TICK + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_tick.h b/os/common/ext/CMSIS/ES32/FS026/md/md_tick.h new file mode 100644 index 00000000000..211910f8cce --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_tick.h @@ -0,0 +1,338 @@ +/********************************************************************************** + * + * @file md_tick.h + * @brief header file of md_tick.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_SYST_H__ +#define __MD_SYST_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_TICK TICK + * @brief TICK micro driver + * @{ + */ + +/** @defgroup MD_SYST_Public_Macros TICK Public Macros + * @{ + */ + +/** + * @brief MD_SYST_CLKSRC System Tick clock source selection + */ +#define MD_SYSTICK_CLKSRC_HCLK_DIV8 (0x00000000UL) /** @brief The clock source is an external reference clock. */ +#define MD_SYSTICK_CLKSRC_HCLK (0x00000001UL) /** @brief The core clock is used for SysTick. */ +/** + * @} + */ + +/** @defgroup MD_SYST_Public_Functions TICK Public Functions + * @{ + */ + +/** @defgroup MD_SYST_Public_Functions_Group2 CSR + * @{ + */ +/** + * @brief Set TICK CSR Register + * @param tick TICK Instance + * @param csr + * @arg Max Value 0x7 + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_csr(SYST_TypeDef *tick, uint32_t csr) +{ + WRITE_REG(tick->CSR, csr); +} + +/** + * @brief Get TICK CSR Register + * @param tick TICK Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_tick_get_csr(SYST_TypeDef *tick) +{ + return (uint32_t)(READ_REG(tick->CSR)); +} + +/** + * @brief Get TICK CSR Count Flag + * @param tick TICK Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_tick_is_active_flag_csr_count(SYST_TypeDef *tick) +{ + return (READ_BIT(tick->CSR, SYST_CSR_COUNT) == (SYST_CSR_COUNT)); +} + +/** + * @brief Set TICK CSR Clock Source + * @param tick TICK Instance + * @param ClkSource System Tick clock source selection + * @arg @ref MD_SYSTICK_CLKSRC_HCLK_DIV8 + * @arg @ref MD_SYSTICK_CLKSRC_HCLK + * @retval None + */ +__STATIC_INLINE void md_tick_set_csr_clksrc(SYST_TypeDef *tick, uint32_t ClkSource) +{ + MODIFY_REG(tick->CSR, SYST_CSR_CLKSRC, ClkSource << SYST_CSR_CLKSRC_POS); +} + +/** + * @brief Get TICK CSR Clock Source + * @param tick TICK Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_SYSTICK_CLKSRC_HCLK_DIV8 + * @arg @ref MD_SYSTICK_CLKSRC_HCLK + */ +__STATIC_INLINE uint32_t md_tick_get_csr_clksource(SYST_TypeDef *tick) +{ + return (uint32_t)(READ_BIT(tick->CSR, SYST_CSR_CLKSRC) >> SYST_CSR_CLKSRC_POS); +} + +/** + * @brief Enable TICK CSR Tick Interrupt + * @param tick TICK Instance + * @retval None + */ +__STATIC_INLINE void md_tick_enable_csr_tickie(SYST_TypeDef *tick) +{ + SET_BIT(tick->CSR, SYST_CSR_TICKIE); +} + +/** + * @brief Disable TICK CSR Tick Interrupt + * @param tick TICK Instance + * @retval None + */ +__STATIC_INLINE void md_tick_disable_csr_tickie(SYST_TypeDef *tick) +{ + CLEAR_BIT(tick->CSR, SYST_CSR_TICKIE); +} + +/** + * @brief is TICK CSR Tick Interrupt Enabled + * @param tick TICK Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_tick_is_enabled_csr_tickie(SYST_TypeDef *tick) +{ + return (READ_BIT(tick->CSR, SYST_CSR_TICKIE) == (SYST_CSR_TICKIE)); +} + +/** + * @brief Enable TICK CSR Enable + * @param tick TICK Instance + * @retval None + */ +__STATIC_INLINE void md_tick_enable_csr_enable(SYST_TypeDef *tick) +{ + SET_BIT(tick->CSR, SYST_CSR_ENABLE); +} + +/** + * @brief Disable TICK CSR Enable + * @param tick TICK Instance + * @retval None + */ +__STATIC_INLINE void md_tick_disable_csr_enable(SYST_TypeDef *tick) +{ + CLEAR_BIT(tick->CSR, SYST_CSR_ENABLE); +} + +/** + * @brief is TICK CSR Enable Enabled + * @param None + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_tick_is_enabled_csr_enable(SYST_TypeDef *tick) +{ + return (READ_BIT(tick->CSR, SYST_CSR_ENABLE) == (SYST_CSR_ENABLE)); +} +/** + * @} + */ + +/** @defgroup MD_SYST_Public_Functions_Group3 RVR + * @{ + */ +/** + * @brief Set TICK RVR Register + * @param tick TICK Instance + * @param rvr + * @arg Max Value 0xffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_rvr(SYST_TypeDef *tick, uint32_t rvr) +{ + WRITE_REG(tick->RVR, rvr); +} + +/** + * @brief Get TICK RVR Register + * @param tick TICK Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_rvr(SYST_TypeDef *tick) +{ + return (uint32_t)(READ_REG(tick->RVR)); +} + +/** + * @brief Set TICK RVR Reload + * @param tick TICK Instance + * @param Reload + * @arg Max Value 0xffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_rvr_reload(SYST_TypeDef *tick, uint32_t Reload) +{ + MODIFY_REG(tick->RVR, SYST_RVR_RELOAD, Reload); +} + +/** + * @brief Get TICK RVR Reload + * @param tick TICK Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xfffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_rvr_reload(SYST_TypeDef *tick) +{ + return (uint32_t)(READ_BIT(tick->RVR, SYST_RVR_RELOAD)); +} +/** + * @} + */ + +/** @defgroup MD_SYST_Public_Functions_Group4 CVR + * @{ + */ +/** + * @brief Set TICK CVR Register + * @param tick TICK Instance + * @param cvr + * @arg Max Value 0xffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_cvr(SYST_TypeDef *tick, uint32_t cvr) +{ + WRITE_REG(tick->CVR, cvr); +} + +/** + * @brief Get TICK CVR Register + * @param tick TICK Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_cvr(SYST_TypeDef *tick) +{ + return (uint32_t)(READ_REG(tick->CVR)); +} + +/** + * @brief Set TICK CVR Current + * @param tick TICK Instance + * @param Current + * @arg Max Value 0xffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_cvr_current(SYST_TypeDef *tick, uint32_t Current) +{ + MODIFY_REG(tick->CVR, SYST_CVR_CURRENT, Current); +} + +/** + * @brief Get TICK CVR Current + * @param tick TICK Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xfffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_cvr_current(SYST_TypeDef *tick) +{ + return (uint32_t)(READ_BIT(tick->CVR, SYST_CVR_CURRENT)); +} + +/** + * @} + */ + +/** @defgroup MD_SYST_Public_Functions_Group1 Initialization + * @{ + */ +void md_tick_init(uint8_t); +uint32_t md_tick_get_mscnt(void); +uint32_t md_tick_get_100uscnt(void); +uint32_t md_tick_get_10uscnt(void); +void md_tick_waitms(uint8_t Unit, uint16_t msCnt); +void md_tick_wait100us(uint16_t Unit, uint16_t usCnt); +void md_tick_wait10us(uint16_t Unit, uint16_t usCnt); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_timer.h b/os/common/ext/CMSIS/ES32/FS026/md/md_timer.h new file mode 100644 index 00000000000..ab0ad209b28 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_timer.h @@ -0,0 +1,5671 @@ +/********************************************************************************** + * + * @file md_timer.h + * @brief header file of md_timer.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 25 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_TIMER_H_ +#define __MD_TIMER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------*/ +#include "fs026.h" + + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_TIMER TIMER + * @brief TIMER micro driver + * @{ + */ + + +// Bob,Kevin ADD +/** @defgroup TIMER_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CHMRx[] = +{ + 0x00U, /* 0: timx_CH1 */ + 0x00U, /* 1: timx_CH1N */ + 0x00U, /* 2: timx_CH2 */ + 0x00U, /* 3: timx_CH2N */ + 0x04U, /* 4: timx_CH3 */ + 0x04U, /* 5: timx_CH3N */ + 0x04U, /* 6: timx_CH4 */ + 0x04U, /* 7: timx_CH4N */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: CH1MOD, CH1FEN, CH1PEN */ + 0U, /* 1: - NA */ + 8U, /* 2: CH2MOD, CH2FEN, CH2PEN */ + 0U, /* 3: - NA */ + 0U, /* 4: CH3MOD, CH3FEN, CH3PEN */ + 0U, /* 5: - NA */ + 8U, /* 6: CH4MOD, CH4FEN, CH4PEN */ + 0U, /* 7: - NA */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1SSEL, I1PRES, I1FLT */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2SSEL, I2PRES, I2FLT */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3SSEL, I3PRES, I3FLT */ + 0U, /* 5: - NA */ + 8U, /* 6: CC4SSEL, I4PRES, I4FLT */ + 0U, /* 7: - NA */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1POL */ + 2U, /* 1: CC1NPOL */ + 4U, /* 2: CC2POL */ + 6U, /* 3: CC2NPOL */ + 8U, /* 4: CC3POL */ + 10U, /* 5: CC3NPOL */ + 12U, /* 6: CC4POL */ + 14U, /* 7: CC4NPOL */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OISS1 */ + 1U, /* 1: OISS1N */ + 2U, /* 2: OISS2 */ + 3U, /* 3: OISS2N */ + 4U, /* 4: OISS3 */ + 5U, /* 5: OISS3N */ + 6U, /* 6: OISS4 */ +}; + +/** + * @brief TIMER_LL_EC_CHANNEL Channel + */ +#define LL_TIMER_CHANNEL_CH1 TIMER_CCEP_CC1EN /*!< Timer input/output channel 1 */ +#define LL_TIMER_CHANNEL_CH1N TIMER_CCEP_CC1NEN /*!< Timer complementary output channel 1 */ +#define LL_TIMER_CHANNEL_CH2 TIMER_CCEP_CC2EN /*!< Timer input/output channel 2 */ +#define LL_TIMER_CHANNEL_CH2N TIMER_CCEP_CC2NEN /*!< Timer complementary output channel 2 */ +#define LL_TIMER_CHANNEL_CH3 TIMER_CCEP_CC3EN /*!< Timer input/output channel 3 */ +#define LL_TIMER_CHANNEL_CH3N TIMER_CCEP_CC3NEN /*!< Timer complementary output channel 3 */ +#define LL_TIMER_CHANNEL_CH4 TIMER_CCEP_CC4EN /*!< Timer input/output channel 4 */ + + +/** + * @brief TIMER_LL_Private_Macros TIM Private Macros + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH1N + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH2N + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH3N + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval none + */ +#define TIMER_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIMER_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIMER_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIMER_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIMER_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIMER_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIMER_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIMER_CHANNEL_CH4) ? 6U :7U) + + +// Bob,Kevin ADDEND +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Macros TIMER Public Macros + * @{ + */ + +/* TIMER_CON1 macros define*/ +#define MD_TIMER_DEBUGSELECT_INPUT (0) /*!< Channel input*/ +#define MD_TIMER_DEBUGSELECT_OUTPUT (1) /*!< Channel output*/ + +#define MD_TIMER_CLOCKDIVSION_DIV1 (0) /*!< tDTS=tCK_INT*/ +#define MD_TIMER_CLOCKDIVSION_DIV2 (1) /*!< tDTS=2*tCK_INT*/ +#define MD_TIMER_CLOCKDIVSION_DIV4 (2) /*!< tDTS=4*tCK_INT*/ + +#define MD_TIMER_CENTERALIGNED_DISABLE (0) /*!< Edge-aligned mode*/ +#define MD_TIMER_CENTERALIGNED_DOWN (1) /*!< Center-aligned mode 1*/ +#define MD_TIMER_CENTERALIGNED_UP (2) /*!< Center-aligned mode 2*/ +#define MD_TIMER_CENTERALIGNED_BOTH (3) /*!< Center-aligned mode 3*/ + +#define MD_TIMER_UPCOUNTER (0) /*!< Counter used as upcounter*/ +#define MD_TIMER_DOWNCOUNTER (1) /*!< Counter used as downcounter*/ + +#define MD_TIMER_UPDATESOURCE_NORMAL (0) /*!< Counter overflow/underflow, Setting the UG bit, Update generation through the slave mode controller generate an update interrupt*/ +#define MD_TIMER_UPDATESOURCE_COUNTER (1) /*!< Only counter overflow/underflow generates an update interrupt or DMA request if Enabled*/ + +/* TIMER_CON2 macros define*/ +#define MD_TIMER_OISS4_IDLEOUTPUT_LOW (0) /*!< OISS4=0 (after a dead-time if CH4ON is implemented) when GOEN=0*/ +#define MD_TIMER_OISS4_IDLEOUTPUT_HIGH (1) /*!< OISS4=1 (after a dead-time if CH4ON is implemented) when GOEN=0*/ + +#define MD_TIMER_OISS3N_IDLEOUTPUT_LOW (0) /*!< OISS3N=0 (after a dead-time if CH3ON is implemented) when GOEN=0*/ +#define MD_TIMER_OISS3N_IDLEOUTPUT_HIGH (1) /*!< OISS3N=1 (after a dead-time if CH3ON is implemented) when GOEN=0*/ + +#define MD_TIMER_OISS3_IDLEOUTPUT_LOW (0) /*!< OISS3=0 (after a dead-time if CH3ON is implemented) when GOEN=0*/ +#define MD_TIMER_OISS3_IDLEOUTPUT_HIGH (1) /*!< OISS3=1 (after a dead-time if CH3ON is implemented) when GOEN=0*/ + +#define MD_TIMER_OISS2N_IDLEOUTPUT_LOW (0) /*!< OISS2N=0 (after a dead-time if CH2ON is implemented) when GOEN=0*/ +#define MD_TIMER_OISS2N_IDLEOUTPUT_HIGH (1) /*!< OISS2N=1 (after a dead-time if CH2ON is implemented) when GOEN=0*/ + +#define MD_TIMER_OISS2_IDLEOUTPUT_LOW (0) /*!< OISS2=0 (after a dead-time if CH2ON is implemented) when GOEN=0*/ +#define MD_TIMER_OISS2_IDLEOUTPUT_HIGH (1) /*!< OISS2=1 (after a dead-time if CH2ON is implemented) when GOEN=0*/ + +#define MD_TIMER_OISS1N_IDLEOUTPUT_LOW (0) /*!< OISS1N=0 (after a dead-time if CH1ON is implemented) when GOEN=0*/ +#define MD_TIMER_OISS1N_IDLEOUTPUT_HIGH (1) /*!< OISS1N=1 (after a dead-time if CH1ON is implemented) when GOEN=0*/ + +#define MD_TIMER_OISS1_IDLEOUTPUT_LOW (0) /*!< OISS1=0 (after a dead-time if CH1ON is implemented) when GOEN=0*/ +#define MD_TIMER_OISS1_IDLEOUTPUT_HIGH (1) /*!< OISS1=1 (after a dead-time if CH1ON is implemented) when GOEN=0*/ + +#define MD_TIMER_TI1INPUT_CH1 (0) /*!< The timx_CH1 pin is connected to TI1 input*/ +#define MD_TIMER_TI1INPUT_XOR (1) /*!< The timx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)*/ + +#define MD_TIMER_MASTERMODE_RESET (0) /*!< Reset mode*/ +#define MD_TIMER_MASTERMODE_ENABLE (1) /*!< Enable mode*/ +#define MD_TIMER_MASTERMODE_UPDATE (2) /*!< Update mode*/ +#define MD_TIMER_MASTERMODE_COMPAREPULSE (3) /*!< Compare Pulse mode*/ +#define MD_TIMER_MASTERMODE_COMPARE1 (4) /*!< Compare 1 mode*/ +#define MD_TIMER_MASTERMODE_COMPARE2 (5) /*!< Compare 2 mode*/ +#define MD_TIMER_MASTERMODE_COMPARE3 (6) /*!< Compare 3 mode*/ +#define MD_TIMER_MASTERMODE_COMPARE4 (7) /*!< Compare 4 mode*/ + +#define MD_TIMER_DMASELECTION_COMPARE (0) /*!< CCx DMA request sent when CCx event occurs*/ +#define MD_TIMER_DMASELECTION_UPDATE (1) /*!< CCx DMA requests sent when update event occurs*/ + +#define MD_TIMER_UPDATESELECTION_COMG (0) /*!< When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only*/ +#define MD_TIMER_UPDATESELECTION_BOTH (1) /*!< When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI*/ + +/* TIMER_SMCON macros define*/ +#define MD_TIMER_TRIGGER_IT0 ((0x0 >> 3) << TIMER_SMCON_TSSEL2_POSS | (0x0 & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Internal Trigger 0*/ +#define MD_TIMER_TRIGGER_IT1 ((0x1 >> 3) << TIMER_SMCON_TSSEL2_POSS | (0x1 & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Internal Trigger 1*/ +#define MD_TIMER_TRIGGER_IT2 ((0x2 >> 3) << TIMER_SMCON_TSSEL2_POSS | (0x2 & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Internal Trigger 2*/ +#define MD_TIMER_TRIGGER_IT3 ((0x3 >> 3) << TIMER_SMCON_TSSEL2_POSS | (0x3 & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Internal Trigger 3*/ +#define MD_TIMER_TRIGGER_I1F_ED ((0x4 >> 3) << TIMER_SMCON_TSSEL2_POSS | (0x4 & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< TI1 Edge Detector*/ +#define MD_TIMER_TRIGGER_I1F ((0x5 >> 3) << TIMER_SMCON_TSSEL2_POSS | (0x5 & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Filtered Timer Input 1*/ +#define MD_TIMER_TRIGGER_I2F ((0x6 >> 3) << TIMER_SMCON_TSSEL2_POSS | (0x6 & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Filtered Timer Input 2*/ +#define MD_TIMER_TRIGGER_ETF ((0x7 >> 3) << TIMER_SMCON_TSSEL2_POSS | (0x7 & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< External Trigger input*/ +#define MD_TIMER_TRIGGER_IT4 ((0x8 >> 3) << TIMER_SMCON_TSSEL2_POSS | (0x8 & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Internal Trigger 4*/ +#define MD_TIMER_TRIGGER_IT5 ((0x9 >> 3) << TIMER_SMCON_TSSEL2_POSS | (0x9 & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Internal Trigger 5*/ +#define MD_TIMER_TRIGGER_IT6 ((0xA >> 3) << TIMER_SMCON_TSSEL2_POSS | (0xA & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Internal Trigger 6*/ +#define MD_TIMER_TRIGGER_IT7 ((0xB >> 3) << TIMER_SMCON_TSSEL2_POSS | (0xB & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Internal Trigger 7*/ +#define MD_TIMER_TRIGGER_IT8 ((0xC >> 3) << TIMER_SMCON_TSSEL2_POSS | (0xC & 0x7) << TIMER_SMCON_TSSEL1_POSS) /*!< Internal Trigger 8*/ + +#define MD_TIMER_ETRPOLARITY_NONINVERTED (0) /*!< ETR is non-inverted*/ +#define MD_TIMER_ETRPOLARITY_INVERTED (1) /*!< ETR is inverted*/ + +#define MD_TIMER_ETRPRESCALER_DISABLE (0) /*!< Prescaler OFF*/ +#define MD_TIMER_ETRPRESCALER_DIV2 (1) /*!< ETR frequency divided by 2*/ +#define MD_TIMER_ETRPRESCALER_DIV4 (2) /*!< ETR frequency divided by 4*/ +#define MD_TIMER_ETRPRESCALER_DIV8 (3) /*!< ETR frequency divided by 8*/ + +#define MD_TIMER_ETRFILTER_FDIV1 (0 ) /*!< No filter*/ +#define MD_TIMER_ETRFILTER_FDIV1N2 (1 ) /*!< fSAMPLING = fCK_INT, N = 2*/ +#define MD_TIMER_ETRFILTER_FDIV1N4 (2 ) /*!< fSAMPLING = fCK_INT, N = 4*/ +#define MD_TIMER_ETRFILTER_FDIV1N8 (3 ) /*!< fSAMPLING = fCK_INT, N = 8*/ +#define MD_TIMER_ETRFILTER_FDIV2N6 (4 ) /*!< fSAMPLING = fDTS / 2, N = 6*/ +#define MD_TIMER_ETRFILTER_FDIV2N8 (5 ) /*!< fSAMPLING = fDTS / 2, N = 8*/ +#define MD_TIMER_ETRFILTER_FDIV4N6 (6 ) /*!< fSAMPLING = fDTS / 4, N = 6*/ +#define MD_TIMER_ETRFILTER_FDIV4N8 (7 ) /*!< fSAMPLING = fDTS / 4, N = 8*/ +#define MD_TIMER_ETRFILTER_FDIV8N6 (8 ) /*!< fSAMPLING = fDTS / 8, N = 6*/ +#define MD_TIMER_ETRFILTER_FDIV8N8 (9 ) /*!< fSAMPLING = fDTS / 8, N = 8*/ +#define MD_TIMER_ETRFILTER_FDIV16N5 (10) /*!< fSAMPLING = fDTS / 16, N = 5*/ +#define MD_TIMER_ETRFILTER_FDIV16N6 (11) /*!< fSAMPLING = fDTS / 16, N = 6*/ +#define MD_TIMER_ETRFILTER_FDIV16N8 (12) /*!< fSAMPLING = fDTS / 16, N = 8*/ +#define MD_TIMER_ETRFILTER_FDIV32N5 (13) /*!< fSAMPLING = fDTS / 32, N = 5*/ +#define MD_TIMER_ETRFILTER_FDIV32N6 (14) /*!< fSAMPLING = fDTS / 32, N = 6*/ +#define MD_TIMER_ETRFILTER_FDIV32N8 (15) /*!< fSAMPLING = fDTS / 32, N = 8*/ + +#define MD_TIMER_SLAVEMODE_DISABLE (0) /*!< Slave mode disabled*/ +#define MD_TIMER_SLAVEMODE_ENCODER1 (1) /*!< Encoder mode 1*/ +#define MD_TIMER_SLAVEMODE_ENCODER2 (2) /*!< Encoder mode 2*/ +#define MD_TIMER_SLAVEMODE_ENCODER3 (3) /*!< Encoder mode 3*/ +#define MD_TIMER_SLAVEMODE_RESET (4) /*!< Reset Mode*/ +#define MD_TIMER_SLAVEMODE_GATED (5) /*!< Gated Mode*/ +#define MD_TIMER_SLAVEMODE_TRIGGER (6) /*!< Trigger Mode*/ +#define MD_TIMER_SLAVEMODE_EXTERNALCLOCK (7) /*!< External Clock Mode 1*/ + +/* TIMER_CHMR1 and TIMER_CHMR2 output macros define*/ +#define MD_TIMER_OUTPUTMODE_DISABLE (0) /*!< Frozen*/ +#define MD_TIMER_OUTPUTMODE_HIGHONMSTCH (1) /*!< Set channel 1 to active level on match*/ +#define MD_TIMER_OUTPUTMODE_LOWONMSTCH (2) /*!< Set channel 1 to inactive level on match*/ +#define MD_TIMER_OUTPUTMODE_TOGGLE (3) /*!< Toggle*/ +#define MD_TIMER_OUTPUTMODE_FORCELOW (4) /*!< Force inactive level*/ +#define MD_TIMER_OUTPUTMODE_FORCEHIGH (5) /*!< Force active level*/ +#define MD_TIMER_OUTPUTMODE_PWMMODE1 (6) /*!< PWM mode 1*/ +#define MD_TIMER_OUTPUTMODE_PWMMODE2 (7) + +/* TIMER_CHMR1 and TIMER_CHMR2 input macros define*/ +#define MD_TIMER_INPUTFILTER_FDIV1 (0 ) /*!< No filter*/ +#define MD_TIMER_INPUTFILTER_FDIV1N2 (1 ) /*!< fSAMPLING = fCK_INT, N = 2*/ +#define MD_TIMER_INPUTFILTER_FDIV1N4 (2 ) /*!< fSAMPLING = fCK_INT, N = 4*/ +#define MD_TIMER_INPUTFILTER_FDIV1N8 (3 ) /*!< fSAMPLING = fCK_INT, N = 8*/ +#define MD_TIMER_INPUTFILTER_FDIV2N6 (4 ) /*!< fSAMPLING = fDTS / 2, N = 6*/ +#define MD_TIMER_INPUTFILTER_FDIV2N8 (5 ) /*!< fSAMPLING = fDTS / 2, N = 8*/ +#define MD_TIMER_INPUTFILTER_FDIV4N6 (6 ) /*!< fSAMPLING = fDTS / 4, N = 6*/ +#define MD_TIMER_INPUTFILTER_FDIV4N8 (7 ) /*!< fSAMPLING = fDTS / 4, N = 8*/ +#define MD_TIMER_INPUTFILTER_FDIV8N6 (8 ) /*!< fSAMPLING = fDTS / 8, N = 6*/ +#define MD_TIMER_INPUTFILTER_FDIV8N8 (9 ) /*!< fSAMPLING = fDTS / 8, N = 8*/ +#define MD_TIMER_INPUTFILTER_FDIV16N5 (10) /*!< fSAMPLING = fDTS / 16, N = 5*/ +#define MD_TIMER_INPUTFILTER_FDIV16N6 (11) /*!< fSAMPLING = fDTS / 16, N = 6*/ +#define MD_TIMER_INPUTFILTER_FDIV16N8 (12) /*!< fSAMPLING = fDTS / 16, N = 8*/ +#define MD_TIMER_INPUTFILTER_FDIV32N5 (13) /*!< fSAMPLING = fDTS / 32, N = 5*/ +#define MD_TIMER_INPUTFILTER_FDIV32N6 (14) /*!< fSAMPLING = fDTS / 32, N = 6*/ +#define MD_TIMER_INPUTFILTER_FDIV32N8 (15) /*!< fSAMPLING = fDTS / 32, N = 8*/ + +#define MD_TIMER_INPUTPRESCALE_DIV1 (0) /*!< no prescaler*/ +#define MD_TIMER_INPUTPRESCALE_DIV2 (1) /*!< capture is done once every 2 events*/ +#define MD_TIMER_INPUTPRESCALE_DIV4 (2) /*!< capture is done once every 4 events*/ +#define MD_TIMER_INPUTPRESCALE_DIV8 (3) /*!< capture is done once every 8 events*/ + +/* TIMER_CHMR1/CHMR2 input/output macros define*/ +#define MD_TIMER_CHMODE_OUTPUT (0) /*!< CCx channel is configured as output*/ +#define MD_TIMER_CHMODE_INPUT_DIRECT (1) /*!< CCx channel is configured as input, ICx is mapped direct*/ +#define MD_TIMER_CHMODE_INPUT_INDIRECT (2) /*!< CCx channel is configured as input, ICx is mapped indirect*/ +#define MD_TIMER_CHMODE_INPUT_TRC (3) /*!< CCx channel is configured as input, ICx is mapped TRC*/ + +/* TIMER_CCEP input macros define*/ +#define MD_TIMER_OUTPUTPOLARITY_HIGH (0) /*!< active high*/ +#define MD_TIMER_OUTPUTPOLARITY_LOW (1) /*!< active low*/ + +/* TIMER_BDCFG input macros define*/ +#define MD_TIMER_BREAKPOLARITY_LOW (0) /*!< Break input BRK is active low*/ +#define MD_TIMER_BREAKPOLARITY_HIGH (1) /*!< Break input BRK is active high */ + +#define MD_TIMER_OFFSTATERUN_DISABLE (0) /*!< This bit is used when MOE=1, when inactive, OC/OCN outputs are disabled*/ +#define MD_TIMER_OFFSTATERUN_ENABLE (1) /*!< This bit is used when MOE=1, when inactive, OC/OCN outputs are enabled*/ + +#define MD_TIMER_OFFSTATEIDLE_DISABLE (0) /*!< This bit is used when MOE=0, when inactive, OC/OCN outputs are disabled*/ +#define MD_TIMER_OFFSTATEIDLE_ENABLE (1) /*!< This bit is used when MOE=0, when inactive, OC/OCN outputs are forced*/ + +#define MD_TIMER_LOCKLEVEL_0 (0) /*!< LOCK OFF*/ +#define MD_TIMER_LOCKLEVEL_1 (1) /*!< LOCK Level 1*/ +#define MD_TIMER_LOCKLEVEL_2 (2) /*!< LOCK Level 2*/ +#define MD_TIMER_LOCKLEVEL_3 (3) /*!< LOCK Level 3*/ + +/* TIMER_OPTR input macros define*/ +#define MD_TIMER_ETRRMP_ETR (0) /*!< Timer ETR*/ +#define MD_TIMER_ETRRMP_CMP1 (1) /*!< CMP1 output*/ +#define MD_TIMER_ETRRMP_CMP2 (2) /*!< CMP2 output*/ +#define MD_TIMER_ETRRMP_ADCAWD (3) /*!< ADC watchdog*/ + +#define MD_TIMER_CH4RMP_CH4 (0) /*!< Timer channel 4*/ + +#define MD_TIMER_CH3RMP_CH3 (0) /*!< Timer channel 3*/ + +#define MD_TIMER_CH2RMP_CH2 (0) /*!< Timer channel 2*/ +#define MD_TIMER_CH2RMP_CMP2 (1) /*!< CMP2 output*/ + +#define MD_TIMER_CH1RMP_CH1 (0) /*!< Timer channel 1*/ +#define MD_TIMER_CH1RMP_CMP1 (1) /*!< CMP1 output*/ + +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions TIMER Public Functions + * @{ + */ + +/** @defgroup MD_TIMER_Public_Functions_Group2 CON1 + * @{ + */ +/** + * @brief Timer CON1 setup. + * @param timx TIMER instance + * @param value (DBGSEL | DFCKSEL | ARPEN | CMSEL | DIRSEL | SPMEN | UERSEL | DISUE | CNTEN) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_con1(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CON1, value); +} + +/** + * @brief GET Timer CON1 register value. + * @param timx TIMER instance + * @retval Timer CON1 register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_con1(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->CON1)); +} + +/** + * @brief Timer debug mode keep output enable. + * @param timx TIMER instance + * @param DebugSelect Debug mode output select + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_debug_keep_output(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CON1, TIMER_CON1_DBGSEL); +} + +/** + * @brief Timer debug mode keep output disable. + * @param timx TIMER instance + * @param DebugSelect Debug mode output select + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_debug_keep_output(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, TIMER_CON1_DBGSEL); +} + +/** + * @brief Timer debug mode keep output is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_debug_keep_output(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, TIMER_CON1_DBGSEL) == (TIMER_CON1_DBGSEL)); +} + +/** + * @brief Timer clock division setup. + * @param timx TIMER instance + * @param ClockDivision Clock division + @arg @ref MD_TIMER_CLOCKDIVSION_DIV1 + @arg @ref MD_TIMER_CLOCKDIVSION_DIV2 + @arg @ref MD_TIMER_CLOCKDIVSION_DIV4 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_df_clock_dfcksel(TIMER_TypeDef *timx, uint32_t ClockDivision) +{ + MODIFY_REG(timx->CON1, TIMER_CON1_DFCKSEL, ClockDivision << TIMER_CON1_DFCKSEL_POSS); +} + +/** + * @brief Get timer Clock division. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_CLOCKDIVSION_DIV1 + @arg @ref MD_TIMER_CLOCKDIVSION_DIV2 + @arg @ref MD_TIMER_CLOCKDIVSION_DIV4 + */ + +__STATIC_INLINE uint32_t md_timer_get_df_clock_dfcksel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON1, TIMER_CON1_DFCKSEL) >> TIMER_CON1_DFCKSEL_POSS); +} + +/** + * @brief Timer auto-reload preload enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_autoreload_preload_arpen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CON1, TIMER_CON1_ARPEN); +} + +/** + * @brief Timer auto-reload preload disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_autoreload_preload_arpen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, TIMER_CON1_ARPEN); +} + +/** + * @brief Indicates whether the timer auto-reload preload is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_autoreload_preload_arpen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, TIMER_CON1_ARPEN) == (TIMER_CON1_ARPEN)); +} + +/** + * @brief Timer center-aligned mode selection setup. + * @param timx TIMER instance + * @param CenterAlignedMode center-aligned mode selection + @arg @ref MD_TIMER_CENTERALIGNED_DISABLE + @arg @ref MD_TIMER_CENTERALIGNED_DOWN + @arg @ref MD_TIMER_CENTERALIGNED_UP + @arg @ref MD_TIMER_CENTERALIGNED_BOTH + * @retval None + */ + +__STATIC_INLINE void md_timer_set_counter_aligned_mode_cmsel(TIMER_TypeDef *timx, uint32_t CenterAlignedMode) +{ + MODIFY_REG(timx->CON1, TIMER_CON1_CMSEL, CenterAlignedMode << TIMER_CON1_CMSEL_POSS); +} + +/** + * @brief Get timer center-aligned mode selection. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_CENTERALIGNED_DISABLE + @arg @ref MD_TIMER_CENTERALIGNED_DOWN + @arg @ref MD_TIMER_CENTERALIGNED_UP + @arg @ref MD_TIMER_CENTERALIGNED_BOTH + */ + +__STATIC_INLINE uint32_t md_timer_get_counter_aligned_mode_cmsel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON1, TIMER_CON1_CMSEL) >> TIMER_CON1_CMSEL_POSS); +} + +/** + * @brief Timer counting direction setup. + * @param timx TIMER instance + * @param direction Counting direction + @arg @ref MD_TIMER_UPCOUNTER + @arg @ref MD_TIMER_DOWNCOUNTER + * @retval None + */ + +__STATIC_INLINE void md_timer_set_counter_direction_dirsel(TIMER_TypeDef *timx, uint32_t direction) +{ + MODIFY_REG(timx->CON1, TIMER_CON1_DIRSEL, direction << TIMER_CON1_DIRSEL_POS); +} + +/** + * @brief Get timer counting direction. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_UPCOUNTER + @arg @ref MD_TIMER_DOWNCOUNTER + */ + +__STATIC_INLINE uint32_t md_timer_get_counter_direction_dirsel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON1, TIMER_CON1_DIRSEL) >> TIMER_CON1_DIRSEL_POS); +} + +/** + * @brief Timer one pulse mode enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_onepulse_spmen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CON1, TIMER_CON1_SPMEN); +} + +/** + * @brief Timer one pulse mode disable. + * @param timx TIMER instance + * @retval None. + */ + +__STATIC_INLINE void md_timer_disable_onepulse_spmen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, TIMER_CON1_SPMEN); +} + +/** + * @brief Indicates whether the timer one pulse mode is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_onepulse_spmen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, TIMER_CON1_SPMEN) == (TIMER_CON1_SPMEN)); +} + +/** + * @brief Timer update request source setup. + * @param timx TIMER instance + * @param UpdateSource Update request source select + @arg @ref MD_TIMER_UPDATESOURCE_NORMAL + @arg @ref MD_TIMER_UPDATESOURCE_COUNTER + * @retval None + */ + +__STATIC_INLINE void md_timer_set_update_source_uersel(TIMER_TypeDef *timx, uint32_t UpdateSource) +{ + MODIFY_REG(timx->CON1, TIMER_CON1_UERSEL, UpdateSource << TIMER_CON1_UERSEL_POS); +} + +/** + * @brief Get timer update request source. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_UPDATESOURCE_NORMAL + @arg @ref MD_TIMER_UPDATESOURCE_COUNTER + */ + +__STATIC_INLINE uint32_t md_timer_get_update_source_uersel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON1, TIMER_CON1_UERSEL) >> TIMER_CON1_UERSEL_POS); +} + +/** + * @brief Timer update event enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_update_disue(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, TIMER_CON1_DISUE); +} + +/** + * @brief Timer update event disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_update_disue(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CON1, TIMER_CON1_DISUE); +} + +/** + * @brief Indicates whether the timer update event is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_update_disue(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, TIMER_CON1_DISUE) == (TIMER_CON1_DISUE)); +} + +/** + * @brief Timer counter enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_counter_cnten(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CON1, TIMER_CON1_CNTEN); +} + +/** + * @brief Timer counter disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_counter_cnten(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, TIMER_CON1_CNTEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_counter_cnten(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, TIMER_CON1_CNTEN) == (TIMER_CON1_CNTEN)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group3 CON2 + * @{ + */ +/** + * @brief Timer CON2 setup. + * @param timx TIMER instance + * @param value (OISS4 | OISS3N | OISS3 | OISS2N | OISS2 | OISS1N | OISS1 | I1SEL | MMSEL | CCDMASEL | CCUSEL | CCPCEN) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_con2(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CON2, value); +} + +/** + * @brief GET Timer CON2 register value. + * @param timx TIMER instance + * @retval Timer CON2 register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_con2(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->CON2)); +} + +/** + * @brief Timer output idle state 4 setup. + * @param timx TIMER instance + * @param IdleOutput Output idle state + @arg @ref MD_TIMER_OISS4_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS4_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_timer_set_ch4o_idle_select_oiss4(TIMER_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_OISS4, IdleOutput << TIMER_CON2_OISS4_POS); +} + +/** + * @brief Get timer output idle state 4. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OISS4_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS4_IDLEOUTPUT_HIGH + */ + +__STATIC_INLINE uint32_t md_timer_get_ch4o_idle_select_oiss4(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_OISS4) >> TIMER_CON2_OISS4_POS); +} + +/** + * @brief Timer output idle state 3N setup. + * @param timx TIMER instance + * @param IdleOutput Output idle state + @arg @ref MD_TIMER_OISS3N_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS3N_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_timer_set_ch3on_idle_select_oiss3n(TIMER_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_OISS3N, IdleOutput << TIMER_CON2_OISS3N_POS); +} + +/** + * @brief Get timer output idle state 3N. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OISS3N_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS3N_IDLEOUTPUT_HIGH + */ + +__STATIC_INLINE uint32_t md_timer_get_ch3on_idle_select_oiss3n(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_OISS3N) >> TIMER_CON2_OISS3N_POS); +} + +/** + * @brief Timer output idle state 3 setup. + * @param timx TIMER instance + * @param IdleOutput Output idle state + @arg @ref MD_TIMER_OISS3_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS3_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_timer_set_ch3o_idle_select_oiss3(TIMER_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_OISS3, IdleOutput << TIMER_CON2_OISS3_POS); +} + +/** + * @brief Get timer output idle state 3. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OISS3_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS3_IDLEOUTPUT_HIGH + */ + +__STATIC_INLINE uint32_t md_timer_get_ch3o_idle_select_oiss3(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_OISS3) >> TIMER_CON2_OISS3_POS); +} + +/** + * @brief Timer output idle state 2N setup. + * @param timx TIMER instance + * @param IdleOutput Output idle state + @arg @ref MD_TIMER_OISS2N_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS2N_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_timer_set_ch2on_idle_select_oiss2n(TIMER_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_OISS2N, IdleOutput << TIMER_CON2_OISS2N_POS); +} + +/** + * @brief Get timer output idle state 2N. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OISS2N_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS2N_IDLEOUTPUT_HIGH + */ + +__STATIC_INLINE uint32_t md_timer_get_ch2on_idle_select_oiss2n(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_OISS2N) >> TIMER_CON2_OISS2N_POS); +} + +/** + * @brief Timer output idle state 2 setup. + * @param timx TIMER instance + * @param IdleOutput Output idle state + @arg @ref MD_TIMER_OISS2_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS2_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_timer_set_ch2o_idle_select_oiss2(TIMER_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_OISS2, IdleOutput << TIMER_CON2_OISS2_POS); +} + +/** + * @brief Get timer output idle state 2. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OISS2_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS2_IDLEOUTPUT_HIGH + */ + +__STATIC_INLINE uint32_t md_timer_get_ch2o_idle_select_oiss2(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_OISS2) >> TIMER_CON2_OISS2_POS); +} + +/** + * @brief Timer output idle state 1N setup. + * @param timx TIMER instance + * @param IdleOutput Output idle state + @arg @ref MD_TIMER_OISS1N_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS1N_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_timer_set_ch1on_idle_select_oiss1n(TIMER_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_OISS1N, IdleOutput << TIMER_CON2_OISS1N_POS); +} + +/** + * @brief Get timer output idle state 1N. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OISS1N_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS1N_IDLEOUTPUT_HIGH + */ + +__STATIC_INLINE uint32_t md_timer_get_ch1on_idle_select_oiss1n(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_OISS1N) >> TIMER_CON2_OISS1N_POS); +} + +/** + * @brief Timer output idle state 1 setup. + * @param timx TIMER instance + * @param IdleOutput Output idle state + @arg @ref MD_TIMER_OISS1_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS1_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_timer_set_ch1o_idle_select_oiss1(TIMER_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_OISS1, IdleOutput << TIMER_CON2_OISS1_POS); +} + +/** + * @brief Get timer output idle state 1. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OISS1_IDLEOUTPUT_LOW + @arg @ref MD_TIMER_OISS1_IDLEOUTPUT_HIGH + */ + +__STATIC_INLINE uint32_t md_timer_get_ch1o_idle_select_oiss1(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_OISS1) >> TIMER_CON2_OISS1_POS); +} + +/** + * @brief Timer TI1 selection setup. + * @param timx TIMER instance + * @param TI1Input TI1 input select + @arg @ref MD_TIMER_TI1INPUT_CH1 + @arg @ref MD_TIMER_TI1INPUT_XOR + * @retval None + */ + +__STATIC_INLINE void md_timer_set_i1_func_select_i1sel(TIMER_TypeDef *timx, uint32_t TI1Input) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_I1SEL, TI1Input << TIMER_CON2_I1SEL_POS); +} + +/** + * @brief Get timer TI1 selection. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_TI1INPUT_CH1 + @arg @ref MD_TIMER_TI1INPUT_XOR + */ + +__STATIC_INLINE uint32_t md_timer_get_i1_func_select_i1sel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_I1SEL) >> TIMER_CON2_I1SEL_POS); +} + +/** + * @brief Timer master mode selection setup. + * @param timx TIMER instance + * @param MasterMode Master mode selection + @arg @ref MD_TIMER_MASTERMODE_RESET + @arg @ref MD_TIMER_MASTERMODE_ENABLE + @arg @ref MD_TIMER_MASTERMODE_UPDATE + @arg @ref MD_TIMER_MASTERMODE_COMPAREPULSE + @arg @ref MD_TIMER_MASTERMODE_COMPARE1 + @arg @ref MD_TIMER_MASTERMODE_COMPARE2 + @arg @ref MD_TIMER_MASTERMODE_COMPARE3 + @arg @ref MD_TIMER_MASTERMODE_COMPARE4 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_master_trgout_select_mmsel(TIMER_TypeDef *timx, uint32_t MasterMode) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_MMSEL, MasterMode << TIMER_CON2_MMSEL_POSS); +} + +/** + * @brief Get timer master mode selection. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_MASTERMODE_RESET + @arg @ref MD_TIMER_MASTERMODE_ENABLE + @arg @ref MD_TIMER_MASTERMODE_UPDATE + @arg @ref MD_TIMER_MASTERMODE_COMPAREPULSE + @arg @ref MD_TIMER_MASTERMODE_COMPARE1 + @arg @ref MD_TIMER_MASTERMODE_COMPARE2 + @arg @ref MD_TIMER_MASTERMODE_COMPARE3 + @arg @ref MD_TIMER_MASTERMODE_COMPARE4 + */ + +__STATIC_INLINE uint32_t md_timer_get_master_trgout_select_mmsel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_MMSEL) >> TIMER_CON2_MMSEL_POSS); +} + +/** + * @brief Timer capture/compare DMA selection setup. + * @param timx TIMER instance + * @param DMASelection Capture/compare DMA selection + @arg @ref MD_TIMER_DMASELECTION_COMPARE + @arg @ref MD_TIMER_DMASELECTION_UPDATE + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc_dma_select_ccdmasel(TIMER_TypeDef *timx, uint32_t DMASelection) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_CCDMASEL, DMASelection << TIMER_CON2_CCDMASEL_POS); +} + +/** + * @brief Get timer capture/compare DMA selection. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_DMASELECTION_COMPARE + @arg @ref MD_TIMER_DMASELECTION_UPDATE + */ + +__STATIC_INLINE uint32_t md_timer_get_cc_dma_select_ccdmasel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_CCDMASEL) >> TIMER_CON2_CCDMASEL_POS); +} + +/** + * @brief Timer capture/compare control update selection setup. + * @param timx TIMER instance + * @param UpdateSelection Capture/compare control update selection + @arg @ref MD_TIMER_UPDATESELECTION_COMG + @arg @ref MD_TIMER_UPDATESELECTION_BOTH + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc_update_select_ccusel(TIMER_TypeDef *timx, uint32_t UpdateSelection) +{ + MODIFY_REG(timx->CON2, TIMER_CON2_CCUSEL, UpdateSelection << TIMER_CON2_CCUSEL_POS); +} + +/** + * @brief Get timer capture/compare control update selection. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_UPDATESELECTION_COMG + @arg @ref MD_TIMER_UPDATESELECTION_BOTH + */ + +__STATIC_INLINE uint32_t md_timer_get_cc_update_select_ccusel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CON2, TIMER_CON2_CCUSEL) >> TIMER_CON2_CCUSEL_POS); +} + +/** + * @brief Timer capture/compare preloaded control enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_cc_preload_ccpcen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CON2, TIMER_CON2_CCPCEN); +} + +/** + * @brief Timer capture/compare preloaded control disable. + * @param timx TIMER instance + * @retval None. + */ + +__STATIC_INLINE void md_timer_disable_cc_preload_ccpcen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CON2, TIMER_CON2_CCPCEN); +} + +/** + * @brief Indicates whether the timer capture/compare preloaded control is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc_preload_ccpcen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, TIMER_CON2_CCPCEN) == (TIMER_CON2_CCPCEN)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group4 SMCON + * @{ + */ +/** + * @brief Timer SMCON setup. + * @param timx TIMER instance + * @param value (TSSEL2 | ETPOL | ECM2EN | ETPRES | ETFLT | MSCFG | TSSEL1 | SMODS) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_smcon(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->SMCON, value); +} + +/** + * @brief GET Timer SMCON register value. + * @param timx TIMER instance + * @retval Timer SMCON register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_smcon(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->SMCON)); +} + +/** + * @brief Timer trigger selection setup. + * @param timx TIMER instance + * @param TrigerSelect External trigger selection + @arg @ref MD_TIMER_TRIGGER_IT0 + @arg @ref MD_TIMER_TRIGGER_IT1 + @arg @ref MD_TIMER_TRIGGER_IT2 + @arg @ref MD_TIMER_TRIGGER_IT3 + @arg @ref MD_TIMER_TRIGGER_I1F_ED + @arg @ref MD_TIMER_TRIGGER_I1F + @arg @ref MD_TIMER_TRIGGER_I2F + @arg @ref MD_TIMER_TRIGGER_ETF + @arg @ref MD_TIMER_TRIGGER_IT4 + @arg @ref MD_TIMER_TRIGGER_IT5 + @arg @ref MD_TIMER_TRIGGER_IT6 + @arg @ref MD_TIMER_TRIGGER_IT7 + @arg @ref MD_TIMER_TRIGGER_IT8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_slave_trigger_tssel(TIMER_TypeDef *timx, uint32_t TrigerSelect) +{ + MODIFY_REG(timx->SMCON, (TIMER_SMCON_TSSEL2 | TIMER_SMCON_TSSEL1), TrigerSelect); +} + +/** + * @brief Get timer trigger selection setup. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_TRIGGER_IT0 + @arg @ref MD_TIMER_TRIGGER_IT1 + @arg @ref MD_TIMER_TRIGGER_IT2 + @arg @ref MD_TIMER_TRIGGER_IT3 + @arg @ref MD_TIMER_TRIGGER_I1F_ED + @arg @ref MD_TIMER_TRIGGER_I1F + @arg @ref MD_TIMER_TRIGGER_I2F + @arg @ref MD_TIMER_TRIGGER_ETF + @arg @ref MD_TIMER_TRIGGER_IT4 + @arg @ref MD_TIMER_TRIGGER_IT5 + @arg @ref MD_TIMER_TRIGGER_IT6 + @arg @ref MD_TIMER_TRIGGER_IT7 + @arg @ref MD_TIMER_TRIGGER_IT8 + */ + +__STATIC_INLINE uint32_t md_timer_get_slave_trigger_tssel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->SMCON, (TIMER_SMCON_TSSEL2 | TIMER_SMCON_TSSEL1))); +} + +/** + * @brief Timer external trigger polarity setup. + * @param timx TIMER instance + * @param ETRPolarity External trigger polarity + @arg @ref MD_TIMER_ETRPOLARITY_NONINVERTED + @arg @ref MD_TIMER_ETRPOLARITY_INVERTED + * @retval None + */ + +__STATIC_INLINE void md_timer_set_external_trigger_polarity_etpol(TIMER_TypeDef *timx, uint32_t ETRPolarity) +{ + MODIFY_REG(timx->SMCON, TIMER_SMCON_ETPOL, ETRPolarity << TIMER_SMCON_ETPOL_POS); +} + +/** + * @brief Timer external trigger polarity setup. + * @param timx TIMER instance + * @param ETRPolarity External trigger polarity + * @retval None + */ + +__STATIC_INLINE uint32_t md_timer_get_external_trigger_polarity_etpol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->SMCON, TIMER_SMCON_ETPOL) >> TIMER_SMCON_ETPOL_POS); +} + +/** + * @brief Timer external clock enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_external_clk2mode_ecm2en(TIMER_TypeDef *timx) +{ + SET_BIT(timx->SMCON, TIMER_SMCON_ECM2EN); +} + + +/** + * @brief Timer external clock disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_external_clk2mode_ecm2en(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->SMCON, TIMER_SMCON_ECM2EN); +} + +/** + * @brief Indicates whether the timer external clock is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_external_clk2mode_ecm2en(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, TIMER_SMCON_ECM2EN) == (TIMER_SMCON_ECM2EN)); +} + +/** + * @brief Timer external trigger prescaler setup. + * @param timx TIMER instance + * @param ETRPrescale External trigger prescaler + @arg @ref MD_TIMER_ETRPRESCALER_DISABLE + @arg @ref MD_TIMER_ETRPRESCALER_DIV2 + @arg @ref MD_TIMER_ETRPRESCALER_DIV4 + @arg @ref MD_TIMER_ETRPRESCALER_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_external_trigger_prescaler_etpres(TIMER_TypeDef *timx, uint32_t ETRPrescale) +{ + MODIFY_REG(timx->SMCON, TIMER_SMCON_ETPRES, ETRPrescale << TIMER_SMCON_ETPRES_POSS); +} + +/** + * @brief Get Timer external trigger prescaler setup. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_ETRPRESCALER_DISABLE + @arg @ref MD_TIMER_ETRPRESCALER_DIV2 + @arg @ref MD_TIMER_ETRPRESCALER_DIV4 + @arg @ref MD_TIMER_ETRPRESCALER_DIV8 + */ + +__STATIC_INLINE uint32_t md_timer_get_external_trigger_prescaler_etpres(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->SMCON, TIMER_SMCON_ETPRES) >> TIMER_SMCON_ETPRES_POSS); +} + +/** + * @brief Timer external trigger filter setup. + * @param timx TIMER instance + * @param ETRFilter External trigger filter + @arg @ref MD_TIMER_ETRFILTER_FDIV1 + @arg @ref MD_TIMER_ETRFILTER_FDIV1N2 + @arg @ref MD_TIMER_ETRFILTER_FDIV1N4 + @arg @ref MD_TIMER_ETRFILTER_FDIV1N8 + @arg @ref MD_TIMER_ETRFILTER_FDIV2N6 + @arg @ref MD_TIMER_ETRFILTER_FDIV2N8 + @arg @ref MD_TIMER_ETRFILTER_FDIV4N6 + @arg @ref MD_TIMER_ETRFILTER_FDIV4N8 + @arg @ref MD_TIMER_ETRFILTER_FDIV8N6 + @arg @ref MD_TIMER_ETRFILTER_FDIV8N8 + @arg @ref MD_TIMER_ETRFILTER_FDIV16N5 + @arg @ref MD_TIMER_ETRFILTER_FDIV16N6 + @arg @ref MD_TIMER_ETRFILTER_FDIV16N8 + @arg @ref MD_TIMER_ETRFILTER_FDIV32N5 + @arg @ref MD_TIMER_ETRFILTER_FDIV32N6 + @arg @ref MD_TIMER_ETRFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_external_trigger_filter_etflt(TIMER_TypeDef *timx, uint32_t ETRFilter) +{ + MODIFY_REG(timx->SMCON, TIMER_SMCON_ETFLT, ETRFilter << TIMER_SMCON_ETFLT_POSS); +} + +/** + * @brief Get timer external trigger filter. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_ETRFILTER_FDIV1 + @arg @ref MD_TIMER_ETRFILTER_FDIV1N2 + @arg @ref MD_TIMER_ETRFILTER_FDIV1N4 + @arg @ref MD_TIMER_ETRFILTER_FDIV1N8 + @arg @ref MD_TIMER_ETRFILTER_FDIV2N6 + @arg @ref MD_TIMER_ETRFILTER_FDIV2N8 + @arg @ref MD_TIMER_ETRFILTER_FDIV4N6 + @arg @ref MD_TIMER_ETRFILTER_FDIV4N8 + @arg @ref MD_TIMER_ETRFILTER_FDIV8N6 + @arg @ref MD_TIMER_ETRFILTER_FDIV8N8 + @arg @ref MD_TIMER_ETRFILTER_FDIV16N5 + @arg @ref MD_TIMER_ETRFILTER_FDIV16N6 + @arg @ref MD_TIMER_ETRFILTER_FDIV16N8 + @arg @ref MD_TIMER_ETRFILTER_FDIV32N5 + @arg @ref MD_TIMER_ETRFILTER_FDIV32N6 + @arg @ref MD_TIMER_ETRFILTER_FDIV32N8 + */ + +__STATIC_INLINE uint32_t md_timer_get_external_trigger_filter_etflt(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->SMCON, TIMER_SMCON_ETFLT) >> TIMER_SMCON_ETFLT_POSS); +} + +/** + * @brief Timer master/slave mode synchronize enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_master_mode_mscfg(TIMER_TypeDef *timx) +{ + SET_BIT(timx->SMCON, TIMER_SMCON_MSCFG); +} + +/** + * @brief Timer master/slave mode synchronize disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_master_mode_mscfg(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->SMCON, TIMER_SMCON_MSCFG); +} + +/** + * @brief Get timer master/slave mode. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_master_mode_mscfg(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, TIMER_SMCON_MSCFG) == TIMER_SMCON_MSCFG); +} + +/** + * @brief Timer slave mode selection setup. + * @param timx TIMER instance + * @param SlaveMode Slave mode selection + @arg @ref MD_TIMER_SLAVEMODE_DISABLE + @arg @ref MD_TIMER_SLAVEMODE_ENCODER1 + @arg @ref MD_TIMER_SLAVEMODE_ENCODER2 + @arg @ref MD_TIMER_SLAVEMODE_ENCODER3 + @arg @ref MD_TIMER_SLAVEMODE_RESET + @arg @ref MD_TIMER_SLAVEMODE_GATED + @arg @ref MD_TIMER_SLAVEMODE_TRIGGER + @arg @ref MD_TIMER_SLAVEMODE_EXTERNALCLOCK + * @retval None + */ + +__STATIC_INLINE void md_timer_set_slave_mode_smods(TIMER_TypeDef *timx, uint32_t SlaveMode) +{ + MODIFY_REG(timx->SMCON, TIMER_SMCON_SMODS, SlaveMode << TIMER_SMCON_SMODS_POSS); +} + +/** + * @brief Get timer slave mode selection. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_SLAVEMODE_DISABLE + @arg @ref MD_TIMER_SLAVEMODE_ENCODER1 + @arg @ref MD_TIMER_SLAVEMODE_ENCODER2 + @arg @ref MD_TIMER_SLAVEMODE_ENCODER3 + @arg @ref MD_TIMER_SLAVEMODE_RESET + @arg @ref MD_TIMER_SLAVEMODE_GATED + @arg @ref MD_TIMER_SLAVEMODE_TRIGGER + @arg @ref MD_TIMER_SLAVEMODE_EXTERNALCLOCK + */ + +__STATIC_INLINE uint32_t md_timer_get_slave_mode_smods(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->SMCON, TIMER_SMCON_SMODS) >> TIMER_SMCON_SMODS_POSS); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group5 IER + * @{ + */ +/** + * @brief Timer IER setup. + * @param timx TIMER instance + * @param value (CH4OV | CH3OV | CH2OV | CH1OV | BRK | TRGI | COM | CH4 | CH3 | CH2 | CH1 | UPD) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_ier(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->IER, value); +} + +/** + * @brief Timer cpture/compare 4 overcapture interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_ch4ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_CH4OV); +} + +/** + * @brief Timer cpture/compare 3 overcapture interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_ch3ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_CH3OV); +} + +/** + * @brief Timer cpture/compare 2 overcapture interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_ch2ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_CH2OV); +} + +/** + * @brief Timer cpture/compare 1 overcapture interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_ch1ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_CH1OV); +} + +/** + * @brief Timer break interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_brk(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_BRK); +} + +/** + * @brief Timer trigger interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_trgi(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_TRGI); +} + +/** + * @brief Timer COM interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_com(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_COM); +} + +/** + * @brief Timer capture/compare 4 interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_ch4(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_CH4); +} + +/** + * @brief Timer capture/compare 3 interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_ch3(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_CH3); +} + +/** + * @brief Timer capture/compare 2 interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_ch2(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_CH2); +} + +/** + * @brief Timer capture/compare 1 interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_ch1(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_CH1); +} + +/** + * @brief Timer update interrupt enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_it_upd(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IER, TIMER_IER_UPD); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group6 IDR + * @{ + */ +/** + * @brief Timer IDR setup. + * @param timx TIMER instance + * @param value (CH4OV | CH3OV | CH2OV | CH1OV | BRK | TRGI | COM | CH4 | CH3 | CH2 | CH1 | UPD) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_idr(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->IDR, value); +} + +/** + * @brief Timer cpture/compare 4 overcapture interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_ch4ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_CH4OV); +} + +/** + * @brief Timer cpture/compare 3 overcapture interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_ch3ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_CH3OV); +} + +/** + * @brief Timer cpture/compare 2 overcapture interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_ch2ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_CH2OV); +} + +/** + * @brief Timer cpture/compare 1 overcapture interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_ch1ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_CH1OV); +} + +/** + * @brief Timer break interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_brk(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_BRK); +} + +/** + * @brief Timer trigger interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_trgi(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_TRGI); +} + +/** + * @brief Timer COM interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_com(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_COM); +} + +/** + * @brief Timer capture/compare 4 interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_ch4(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_CH4); +} + +/** + * @brief Timer capture/compare 3 interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_ch3(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_CH3); +} + +/** + * @brief Timer capture/compare 2 interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_ch2(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_CH2); +} + +/** + * @brief Timer capture/compare 1 interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_ch1(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_CH1); +} + +/** + * @brief Timer update interrupt disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_it_upd(TIMER_TypeDef *timx) +{ + SET_BIT(timx->IDR, TIMER_IDR_UPD); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group7 IVS + * @{ + */ +/** + * @brief Get timer IVS setup. + * @param timx TIMER instance + * @retval Timer IVS setup. + */ + +__STATIC_INLINE uint32_t md_timer_get_ivs(TIMER_TypeDef *timx) +{ + return (READ_REG(timx->IVS)); +} + +/** + * @brief Indicates whether the timer capture/compare 4 overcapture interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_ch4ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_CH4OV) == (TIMER_IVS_CH4OV)); +} + +/** + * @brief Indicates whether the timer capture/compare 3 overcapture interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_ch3ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_CH3OV) == (TIMER_IVS_CH3OV)); +} + +/** + * @brief Indicates whether the timer cpture/compare 2 overcapture interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_ch2ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_CH2OV) == (TIMER_IVS_CH2OV)); +} + +/** + * @brief Indicates whether the timer capture/compare 1 overcapture interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_ch1ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_CH1OV) == (TIMER_IVS_CH1OV)); +} + +/** + * @brief Indicates whether the timer break interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_brk(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_BRK) == (TIMER_IVS_BRK)); +} + +/** + * @brief Indicates whether the timer trigger interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_trgi(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_TRGI) == (TIMER_IVS_TRGI)); +} + +/** + * @brief Indicates whether the timer COM interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_com(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_COM) == (TIMER_IVS_COM)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 4 interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_ch4(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_CH4) == (TIMER_IVS_CH4)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_ch3(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_CH3) == (TIMER_IVS_CH3)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_ch2(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_CH2) == (TIMER_IVS_CH2)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_ch1(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_CH1) == (TIMER_IVS_CH1)); +} + +/** + * @brief Indicates whether the timer update interrupt is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_it_upd(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, TIMER_IVS_UPD) == (TIMER_IVS_UPD)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group8 RIF + * @{ + */ +/** + * @brief Get timer RIF flag. + * @param timx TIMER instance + * @retval Timer RIF flag. + */ + +__STATIC_INLINE uint32_t md_timer_get_rif(TIMER_TypeDef *timx) +{ + return (READ_REG(timx->RIF)); +} + +/** + * @brief Get timer capture/compare 4 overcapture interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_ch4ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_CH4OV) == (TIMER_RIF_CH4OV)); +} + +/** + * @brief Get timer capture/compare 3 overcapture interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_ch3ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_CH3OV) == (TIMER_RIF_CH3OV)); +} + +/** + * @brief Get timer capture/compare 2 overcapture interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_ch2ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_CH2OV) == (TIMER_RIF_CH2OV)); +} + +/** + * @brief Get timer capture/compare 1 overcapture interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_ch1ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_CH1OV) == (TIMER_RIF_CH1OV)); +} + +/** + * @brief Get timer break interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_brk(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_BRK) == (TIMER_RIF_BRK)); +} + +/** + * @brief Get timer trigger interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_trgi(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_TRGI) == (TIMER_RIF_TRGI)); +} + +/** + * @brief Get timer COM interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_com(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_COM) == (TIMER_RIF_COM)); +} + +/** + * @brief Get timer capture/compare 4 interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_ch4(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_CH4) == (TIMER_RIF_CH4)); +} + +/** + * @brief Get timer capture/compare 3 interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_ch3(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_CH3) == (TIMER_RIF_CH3)); +} + +/** + * @brief Get timer capture/compare 2 interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_ch2(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_CH2) == (TIMER_RIF_CH2)); +} + +/** + * @brief Get timer capture/compare 1 interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_ch1(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_CH1) == (TIMER_RIF_CH1)); +} + +/** + * @brief Get timer update interrupt flag. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_active_it_upd(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, TIMER_RIF_UPD) == (TIMER_RIF_UPD)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group9 IFM + * @{ + */ +/** + * @brief Get timer IFM flag. + * @param timx TIMER instance + * @retval Timer IFM flag. + */ + +__STATIC_INLINE uint32_t md_timer_get_ifm(TIMER_TypeDef *timx) +{ + return (READ_REG(timx->IFM)); +} + +/** + * @brief Get timer capture/compare 4 overcapture interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_ch4ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_CH4OV) == (TIMER_IFM_CH4OV)); +} + +/** + * @brief Get timer capture/compare 3 overcapture interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_ch3ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_CH3OV) == (TIMER_IFM_CH3OV)); +} + +/** + * @brief Get timer capture/compare 2 overcapture interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_ch2ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_CH2OV) == (TIMER_IFM_CH2OV)); +} + +/** + * @brief Get timer capture/compare 1 overcapture interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_ch1ov(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_CH1OV) == (TIMER_IFM_CH1OV)); +} + +/** + * @brief Get timer break interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_brk(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_BRK) == (TIMER_IFM_BRK)); +} + +/** + * @brief Get timer trigger interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_trgi(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_TRGI) == (TIMER_IFM_TRGI)); +} + +/** + * @brief Get timer COM interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_com(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_COM) == (TIMER_IFM_COM)); +} + +/** + * @brief Get timer capture/compare 4 interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_ch4(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_CH4) == (TIMER_IFM_CH4)); +} + +/** + * @brief Get timer capture/compare 3 interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_ch3(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_CH3) == (TIMER_IFM_CH3)); +} + +/** + * @brief Get timer capture/compare 2 interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_ch2(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_CH2) == (TIMER_IFM_CH2)); +} + +/** + * @brief Get timer capture/compare 1 interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_ch1(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_CH1) == (TIMER_IFM_CH1)); +} + +/** + * @brief Get timer update interrupt flag masked. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_timer_is_masked_it_upd(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, TIMER_IFM_UPD) == (TIMER_IFM_UPD)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group10 ICR + * @{ + */ +/** + * @brief Timer ICR setup. + * @param timx TIMER instance + * @param value (CH4OV | CH3OV | CH2OV | CH1OV | BRK | TRGI | COM | CH4 | CH3 | CH2 | CH1 | UPD) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_icr(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->ICR, value); +} + +/** + * @brief Clear timer cpture/compare 4 overcapture interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_ch4ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_CH4OV); +} + +/** + * @brief Clear timer cpture/compare 3 overcapture interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_ch3ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_CH3OV); +} + +/** + * @brief Clear timer cpture/compare 2 overcapture interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_ch2ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_CH2OV); +} + +/** + * @brief Clear timer cpture/compare 1 overcapture interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_ch1ov(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_CH1OV); +} + +/** + * @brief Clear timer break interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_brk(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_BRK); +} + +/** + * @brief Clear timer trigger interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_trgi(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_TRGI); +} + +/** + * @brief Clear timer COM interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_com(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_COM); +} + +/** + * @brief Clear timer capture/compare 4 interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_ch4(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_CH4); +} + +/** + * @brief Clear timer capture/compare 3 interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_ch3(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_CH3); +} + +/** + * @brief Clear timer capture/compare 2 interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_ch2(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_CH2); +} + +/** + * @brief Clear timer capture/compare 1 interrupt flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_ch1(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_CH1); +} + +/** + * @brief Clear timer upadte flag. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_clear_it_upd(TIMER_TypeDef *timx) +{ + SET_BIT(timx->ICR, TIMER_ICR_UPD); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group11 SGE + * @{ + */ +/** + * @brief Timer SGE setup. + * @param timx TIMER instance + * @param value (SGBRK | SGTRGI | SGCOM | SGCH4 | SGCH3 | SGCH2 | SGCH1 | SGUPD) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_sge(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->SGE, value); +} + +/** + * @brief Timer break generation. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_trigger_sgbrk(TIMER_TypeDef *timx) +{ + SET_BIT(timx->SGE, TIMER_SGE_SGBRK); +} + +/** + * @brief Timer trigger generation. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_trigger_sgtrgi(TIMER_TypeDef *timx) +{ + SET_BIT(timx->SGE, TIMER_SGE_SGTRGI); +} + +/** + * @brief Timer COM generation. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_trigger_sgcom(TIMER_TypeDef *timx) +{ + SET_BIT(timx->SGE, TIMER_SGE_SGCOM); +} + +/** + * @brief Timer Capture/Compare 4 generation. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_trigger_sgch4(TIMER_TypeDef *timx) +{ + SET_BIT(timx->SGE, TIMER_SGE_SGCH4); +} + +/** + * @brief Timer Capture/Compare 3 generation. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_trigger_sgch3(TIMER_TypeDef *timx) +{ + SET_BIT(timx->SGE, TIMER_SGE_SGCH3); +} + +/** + * @brief Timer Capture/Compare 2 generation. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_trigger_sgch2(TIMER_TypeDef *timx) +{ + SET_BIT(timx->SGE, TIMER_SGE_SGCH2); +} + +/** + * @brief Timer Capture/Compare 1 generation. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_trigger_sgch1(TIMER_TypeDef *timx) +{ + SET_BIT(timx->SGE, TIMER_SGE_SGCH1); +} + +/** + * @brief Timer update generation. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_trigger_sgupd(TIMER_TypeDef *timx) +{ + SET_BIT(timx->SGE, TIMER_SGE_SGUPD); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group12 CHMR1 + * @{ + */ +/** + * @brief Timer CHMR1 setup. + * @param timx TIMER instance + * @param value output (CH2OCLREN | CH2MOD | CH2PEN | CH2FEN | CC2SSEL | CH1OCLREN | CH1MOD | CH1PEN | CH1FEN | CC1SSEL) + * input (I2FLT | I2PRES | CC2SSEL | I1FLT | I1PRES | CC1SSEL) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_chmr1(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CHMR1, value); +} + +/** + * @brief GET Timer CHMR1 register value. + * @param timx TIMER instance + * @retval Timer CHMR1 register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_chmr1(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->CHMR1)); +} + +/** + * @brief Timer output compare 2 clear enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare2_clear_ch2oclren(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2OCLREN); +} + +/** + * @brief Timer output compare 2 clear disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare2_clear_ch2oclren(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2OCLREN); +} + +/** + * @brief Indicates whether the timer output compare 2 clear is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare2_clear_ch2oclren(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2OCLREN) == (TIMER_CHMR1_OUTPUT_CH2OCLREN)); +} + +/** + * @brief Timer output compare 2 mode setup. + * @param timx TIMER instance + * @param OutputMode Output compare mode + @arg @ref MD_TIMER_OUTPUTMODE_DISABLE + @arg @ref MD_TIMER_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_TOGGLE + @arg @ref MD_TIMER_OUTPUTMODE_FORCELOW + @arg @ref MD_TIMER_OUTPUTMODE_FORCEHIGH + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE1 + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_output_compare2_mode_ch2mod(TIMER_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2MOD, OutputMode << TIMER_CHMR1_OUTPUT_CH2MOD_POSS); +} + +/** + * @brief Get timer output compare 2 mode. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OUTPUTMODE_DISABLE + @arg @ref MD_TIMER_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_TOGGLE + @arg @ref MD_TIMER_OUTPUTMODE_FORCELOW + @arg @ref MD_TIMER_OUTPUTMODE_FORCEHIGH + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE1 + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE2 + */ + +__STATIC_INLINE uint32_t md_timer_get_output_compare2_mode_ch2mod(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2MOD) >> TIMER_CHMR1_OUTPUT_CH2MOD_POSS); +} + +/** + * @brief Timer output compare 2 preload enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare2_preload_ch2pen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2PEN); +} + +/** + * @brief Timer output compare 2 preload disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare2_preload_ch2pen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2PEN); +} + +/** + * @brief Indicates whether the timer output compare 2 preload is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare2_preload_ch2pen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2PEN) == (TIMER_CHMR1_OUTPUT_CH2PEN)); +} + +/** + * @brief Timer output compare 2 fast enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare2_fast_ch2fen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2FEN); +} + +/** + * @brief Timer output compare 2 fast disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare2_fast_ch2fen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2FEN); +} + +/** + * @brief Indicates whether the timer output compare 2 fast is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare2_fast_ch2fen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH2FEN) == (TIMER_CHMR1_OUTPUT_CH2FEN)); +} + +/** + * @brief Timer cpture/compare 2 selection setup. + * @param timx TIMER instance + * @param ChannelMode Channel mode selection + @arg @ref MD_TIMER_CHMODE_OUTPUT + @arg @ref MD_TIMER_CHMODE_INPUT_DIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_INDIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc2_func_cc2ssel(TIMER_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR1, TIMER_CHMR1_OUTPUT_CC2SSEL, (ChannelMode << TIMER_CHMR1_OUTPUT_CC2SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 2 selection. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_CHMODE_OUTPUT + @arg @ref MD_TIMER_CHMODE_INPUT_DIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_INDIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_TRC + */ + +__STATIC_INLINE uint32_t md_timer_get_cc2_func_cc2ssel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CC2SSEL) >> TIMER_CHMR1_OUTPUT_CC2SSEL_POSS); +} + + +/** + * @brief Timer output compare 1 clear enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare1_clear_ch1oclren(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1OCLREN); +} + +/** + * @brief Timer output compare 1 clear disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare1_clear_ch1oclren(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1OCLREN); +} + +/** + * @brief Indicates whether the timer output compare 1 clear is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare1_clear_ch1oclren(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1OCLREN) == (TIMER_CHMR1_OUTPUT_CH1OCLREN)); +} + +/** + * @brief Timer output compare 1 mode setup. + * @param timx TIMER instance + * @param OutputMode Output compare mode + @arg @ref MD_TIMER_OUTPUTMODE_DISABLE + @arg @ref MD_TIMER_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_TOGGLE + @arg @ref MD_TIMER_OUTPUTMODE_FORCELOW + @arg @ref MD_TIMER_OUTPUTMODE_FORCEHIGH + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE1 + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_output_compare1_mode_ch1mod(TIMER_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1MOD, OutputMode << TIMER_CHMR1_OUTPUT_CH1MOD_POSS); +} + +/** + * @brief Get timer output compare 1 mode. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OUTPUTMODE_DISABLE + @arg @ref MD_TIMER_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_TOGGLE + @arg @ref MD_TIMER_OUTPUTMODE_FORCELOW + @arg @ref MD_TIMER_OUTPUTMODE_FORCEHIGH + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE1 + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE2 + */ + +__STATIC_INLINE uint32_t md_timer_get_output_compare1_mode_ch1mod(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1MOD) >> TIMER_CHMR1_OUTPUT_CH1MOD_POSS); +} + +/** + * @brief Timer output compare 1 preload enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare1_preload_ch1pen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1PEN); +} + +/** + * @brief Timer output compare 1 preload disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare1_preload_ch1pen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1PEN); +} + +/** + * @brief Indicates whether the timer output compare 1 preload is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare1_preload_ch1pen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1PEN) == (TIMER_CHMR1_OUTPUT_CH1PEN)); +} + +/** + * @brief Timer output compare 1 fast enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare1_fast_ch1fen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1FEN); +} + +/** + * @brief Timer output compare 1 fast disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare1_fast_ch1fen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1FEN); +} + +/** + * @brief Indicates whether the timer output compare 1 fast is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare1_fast_ch1fen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CH1FEN) == (TIMER_CHMR1_OUTPUT_CH1FEN)); +} + +/** + * @brief Timer cpture/compare 1 selection setup. + * @param timx TIMER instance + * @param ChannelMode Channel mode selection + @arg @ref MD_TIMER_CHMODE_OUTPUT + @arg @ref MD_TIMER_CHMODE_INPUT_DIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_INDIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc1_func_cc1ssel(TIMER_TypeDef *timx, uint32_t sel) +{ + MODIFY_REG(timx->CHMR1, TIMER_CHMR1_OUTPUT_CC1SSEL, sel << TIMER_CHMR1_OUTPUT_CC1SSEL_POSS); +} + +/** + * @brief Get timer cpture/compare 1 selection. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_CHMODE_OUTPUT + @arg @ref MD_TIMER_CHMODE_INPUT_DIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_INDIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_TRC + */ + +__STATIC_INLINE uint32_t md_timer_get_cc1_func_cc1ssel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR1, TIMER_CHMR1_OUTPUT_CC1SSEL) >> TIMER_CHMR1_OUTPUT_CC1SSEL_POSS); +} + +/** + * @brief Timer input capture 2 filter setup. + * @param timx TIMER instance + * @param InputFliter Input capture filter + @arg @ref MD_TIMER_INPUTFILTER_FDIV1 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N2 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N4 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture2_filter_i2flt(TIMER_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR1, TIMER_CHMR1_INPUT_I2FLT, InputFliter << TIMER_CHMR1_INPUT_I2FLT_POSS); +} + +/** + * @brief Get timer input capture 2 filter. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_INPUTFILTER_FDIV1 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N2 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N4 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N8 + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture2_filter_i2flt(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR1, TIMER_CHMR1_INPUT_I2FLT) >> TIMER_CHMR1_INPUT_I2FLT_POSS); +} + +/** + * @brief Timer input capture 2 prescaler setup. + * @param timx TIMER instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_TIMER_INPUTPRESCALE_DIV1 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV2 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV4 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture2_prescaler_ic2pres(TIMER_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR1, TIMER_CHMR1_INPUT_I2PRES, InputPrescale << TIMER_CHMR1_INPUT_I2PRES_POSS); +} + +/** + * @brief Get timer input capture 2 prescaler. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_INPUTPRESCALE_DIV1 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV2 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV4 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV8 + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture2_prescaler_ic2pres(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR1, TIMER_CHMR1_INPUT_I2PRES) >> TIMER_CHMR1_INPUT_I2PRES_POSS); +} + +/** + * @brief Timer input capture 1 filter setup. + * @param timx TIMER instance + * @param InputFliter Input capture filter + @arg @ref MD_TIMER_INPUTFILTER_FDIV1 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N2 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N4 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture1_filter_i1flt(TIMER_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR1, TIMER_CHMR1_INPUT_I1FLT, InputFliter << TIMER_CHMR1_INPUT_I1FLT_POSS); +} + +/** + * @brief Get timer input capture 1 filter. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_INPUTFILTER_FDIV1 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N2 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N4 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N8 + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture1_filter_i1flt(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR1, TIMER_CHMR1_INPUT_I1FLT) >> TIMER_CHMR1_INPUT_I1FLT_POSS); +} + +/** + * @brief Timer input capture 1 prescaler setup. + * @param timx TIMER instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_TIMER_INPUTPRESCALE_DIV1 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV2 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV4 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture1_prescaler_ic1pres(TIMER_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR1, TIMER_CHMR1_INPUT_I1PRES, InputPrescale << TIMER_CHMR1_INPUT_I1PRES_POSS); +} + +/** + * @brief Get timer input capture 1 prescaler. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_INPUTPRESCALE_DIV1 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV2 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV4 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV8 + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture1_prescaler_ic1pres(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR1, TIMER_CHMR1_INPUT_I1PRES) >> TIMER_CHMR1_INPUT_I1PRES_POSS); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group13 CHMR2 + * @{ + */ +/** + * @brief Timer CHMR2 setup. + + * @param timx TIMER instance + * @param value output (CH4OCLREN | CH4MOD | CH4PEN | CH4FEN | CC4SSEL | CH3OCLREN | CH3MOD | CH3PEN | CH3FEN | CC3SSEL) + * input (I4FLT | I4PRES | CC4SSEL | I3FLT | I3PRES | CC3SSEL) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_chmr2(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CHMR2, value); +} + +/** + * @brief GET Timer CHMR2 register value. + * @param timx TIMER instance + * @retval Timer CHMR2 register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_chmr2(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->CHMR2)); +} + +/** + * @brief Timer output compare 4 clear enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare4_clear_ch4oclren(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4OCLREN); +} + +/** + * @brief Timer output compare 4 clear disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare4_clear_ch4oclren(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4OCLREN); +} + +/** + * @brief Indicates whether the timer output compare 4 clear is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare4_clear_ch4oclren(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4OCLREN) == (TIMER_CHMR2_OUTPUT_CH4OCLREN)); +} + +/** + * @brief Timer output compare 4 mode setup. + * @param timx TIMER instance + * @param OutputMode Output compare mode + @arg @ref MD_TIMER_OUTPUTMODE_DISABLE + @arg @ref MD_TIMER_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_TOGGLE + @arg @ref MD_TIMER_OUTPUTMODE_FORCELOW + @arg @ref MD_TIMER_OUTPUTMODE_FORCEHIGH + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE1 + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_output_compare4_mode_ch4mod(TIMER_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4MOD, OutputMode << TIMER_CHMR2_OUTPUT_CH4MOD_POSS); +} + +/** + * @brief Get timer output compare 4 mode. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OUTPUTMODE_DISABLE + @arg @ref MD_TIMER_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_TOGGLE + @arg @ref MD_TIMER_OUTPUTMODE_FORCELOW + @arg @ref MD_TIMER_OUTPUTMODE_FORCEHIGH + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE1 + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE2 + */ + +__STATIC_INLINE uint32_t md_timer_get_output_compare4_mode_ch4mod(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4MOD) >> TIMER_CHMR2_OUTPUT_CH4MOD_POSS); +} + +/** + * @brief Timer output compare 4 preload enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare4_preload_ch4pen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4PEN); +} + +/** + * @brief Timer output compare 4 preload disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare4_preload_ch4pen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4PEN); +} + +/** + * @brief Indicates whether the timer output compare 4 preload is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare4_preload_ch4pen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4PEN) == (TIMER_CHMR2_OUTPUT_CH4PEN)); +} + +/** + * @brief Timer output compare 4 fast enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare4_fast_ch4fen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4FEN); +} + +/** + * @brief Timer output compare 4 fast disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare4_fast_ch4fen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4FEN); +} + +/** + * @brief Indicates whether the timer output compare 4 fast is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare4_fast_ch4fen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH4FEN) == (TIMER_CHMR2_OUTPUT_CH4FEN)); +} + +/** + * @brief Timer cpture/compare 4 selection setup. + * @param timx TIMER instance + * @param ChannelMode Channel mode selection + @arg @ref MD_TIMER_CHMODE_OUTPUT + @arg @ref MD_TIMER_CHMODE_INPUT_DIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_INDIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc4_func_cc4ssel(TIMER_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR2, TIMER_CHMR2_OUTPUT_CC4SSEL, (ChannelMode << TIMER_CHMR2_OUTPUT_CC4SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 4 selection. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_CHMODE_OUTPUT + @arg @ref MD_TIMER_CHMODE_INPUT_DIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_INDIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_TRC + */ + +__STATIC_INLINE uint32_t md_timer_get_cc4_func_cc4ssel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CC4SSEL) >> TIMER_CHMR2_OUTPUT_CC4SSEL_POSS); +} + +/** + * @brief Timer output compare 3 clear enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare3_clear_ch3oclren(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3OCLREN); +} + +/** + * @brief Timer output compare 3 clear disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare3_clear_ch3oclren(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3OCLREN); +} + +/** + * @brief Indicates whether the timer output compare 3 clear is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare3_clear_ch3oclren(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3OCLREN) == (TIMER_CHMR2_OUTPUT_CH3OCLREN)); +} + +/** + * @brief Timer output compare 3 mode setup. + * @param timx TIMER instance + * @param OutputMode Output compare mode + @arg @ref MD_TIMER_OUTPUTMODE_DISABLE + @arg @ref MD_TIMER_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_TOGGLE + @arg @ref MD_TIMER_OUTPUTMODE_FORCELOW + @arg @ref MD_TIMER_OUTPUTMODE_FORCEHIGH + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE1 + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_output_compare3_mode_ch3mod(TIMER_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3MOD, OutputMode << TIMER_CHMR2_OUTPUT_CH3MOD_POSS); +} + +/** + * @brief Get timer output compare 3 mode. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_OUTPUTMODE_DISABLE + @arg @ref MD_TIMER_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_TIMER_OUTPUTMODE_TOGGLE + @arg @ref MD_TIMER_OUTPUTMODE_FORCELOW + @arg @ref MD_TIMER_OUTPUTMODE_FORCEHIGH + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE1 + @arg @ref MD_TIMER_OUTPUTMODE_PWMMODE2 + */ + +__STATIC_INLINE uint32_t md_timer_get_output_compare3_mode_ch3mod(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3MOD) >> TIMER_CHMR2_OUTPUT_CH3MOD_POSS); +} + +/** + * @brief Timer output compare 3 preload enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare3_preload_ch3pen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3PEN); +} + +/** + * @brief Timer output compare 3 preload disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare3_preload_ch3pen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3PEN); +} + +/** + * @brief Indicates whether the timer output compare 3 preload is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare3_preload_ch3pen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3PEN) == (TIMER_CHMR2_OUTPUT_CH3PEN)); +} + +/** + * @brief Timer output compare 3 fast enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_output_compare3_fast_ch3fen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3FEN); +} + +/** + * @brief Timer output compare 3 fast disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_output_compare3_fast_ch3fen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3FEN); +} + +/** + * @brief Indicates whether the timer output compare 3 fast is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_output_compare3_fast_ch3fen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CH3FEN) == (TIMER_CHMR2_OUTPUT_CH3FEN)); +} + +/** + * @brief Timer cpture/compare 3 selection setup. + * @param timx TIMER instance + * @param ChannelMode Channel mode selection + @arg @ref MD_TIMER_CHMODE_OUTPUT + @arg @ref MD_TIMER_CHMODE_INPUT_DIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_INDIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc3_func_cc3ssel(TIMER_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR2, TIMER_CHMR2_OUTPUT_CC3SSEL, (ChannelMode << TIMER_CHMR2_OUTPUT_CC3SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 3 selection. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_CHMODE_OUTPUT + @arg @ref MD_TIMER_CHMODE_INPUT_DIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_INDIRECT + @arg @ref MD_TIMER_CHMODE_INPUT_TRC + */ + +__STATIC_INLINE uint32_t md_timer_get_cc3_func_cc3ssel(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR2, TIMER_CHMR2_OUTPUT_CC3SSEL) >> TIMER_CHMR2_OUTPUT_CC3SSEL_POSS); +} + +/** + * @brief Timer input capture 4 filter setup. + * @param timx TIMER instance + * @param InputFliter Input capture filter + @arg @ref MD_TIMER_INPUTFILTER_FDIV1 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N2 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N4 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture4_filter_i4flt(TIMER_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR2, TIMER_CHMR2_INPUT_I4FLT, InputFliter << TIMER_CHMR2_INPUT_I4FLT_POSS); +} + +/** + * @brief Get timer input capture 4 filter. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_INPUTFILTER_FDIV1 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N2 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N4 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N8 + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture4_filter_i4flt(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR2, TIMER_CHMR2_INPUT_I4FLT) >> TIMER_CHMR2_INPUT_I4FLT_POSS); +} + +/** + * @brief Timer input capture 4 prescaler setup. + * @param timx TIMER instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_TIMER_INPUTPRESCALE_DIV1 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV2 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV4 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture4_prescaler_ic4pres(TIMER_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR2, TIMER_CHMR2_INPUT_I4PRES, InputPrescale << TIMER_CHMR2_INPUT_I4PRES_POSS); +} + +/** + * @brief Get timer input capture 4 prescaler. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_INPUTPRESCALE_DIV1 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV2 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV4 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV8 + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture4_prescaler_ic4pres(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR2, TIMER_CHMR2_INPUT_I4PRES) >> TIMER_CHMR2_INPUT_I4PRES_POSS); +} + + +/** + * @brief Timer input capture 3 filter setup. + * @param timx TIMER instance + * @param InputFliter Input capture filter + @arg @ref MD_TIMER_INPUTFILTER_FDIV1 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N2 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N4 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture3_filter_i3flt(TIMER_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR2, TIMER_CHMR2_INPUT_I3FLT, InputFliter << TIMER_CHMR2_INPUT_I3FLT_POSS); +} + +/** + * @brief Get timer input capture 3 filter. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_INPUTFILTER_FDIV1 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N2 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N4 + @arg @ref MD_TIMER_INPUTFILTER_FDIV1N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV2N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV4N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV8N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV16N8 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N5 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N6 + @arg @ref MD_TIMER_INPUTFILTER_FDIV32N8 + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture3_filter_i3flt(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR2, TIMER_CHMR2_INPUT_I3FLT) >> TIMER_CHMR2_INPUT_I3FLT_POSS); +} + +/** + * @brief Timer input capture 3 prescaler setup. + * @param timx TIMER instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_TIMER_INPUTPRESCALE_DIV1 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV2 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV4 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture3_prescaler_ic3pres(TIMER_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR2, TIMER_CHMR2_INPUT_I3PRES, InputPrescale << TIMER_CHMR2_INPUT_I3PRES_POSS); +} + +/** + * @brief Get timer input capture 3 prescaler. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_INPUTPRESCALE_DIV1 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV2 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV4 + @arg @ref MD_TIMER_INPUTPRESCALE_DIV8 + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture3_prescaler_ic3pres(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CHMR2, TIMER_CHMR2_INPUT_I3PRES) >> TIMER_CHMR2_INPUT_I3PRES_POSS); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group14 CCEP + * @{ + */ +/** + * @brief Timer CCEP setup. + * @param timx TIMER instance + * @param value (CC4NPOL | CC4POL | CC4EN | CC3NPOL | CC3NEN | CC3POL | CC3EN | CC2NPOL | + * CC2NEN | CC2POL | CC2EN | CC1NPOL | CC1NEN | CC1POL | CC1EN ) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_ccep(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCEP, value); +} + +/** + * @brief GET Timer CCEP register value. + * @param timx TIMER instance + * @retval Timer CCEP register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_ccep(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->CCEP)); +} + +/** + * @brief Timer capture/compare 4 complementary output polarity setup. + * @param timx TIMER instance + * @param OutputPolarity Output polarity + @arg @ref MD_TIMER_OUTPUTPOLARITY_HIGH + @arg @ref MD_TIMER_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc4_complementary_polarity_cc4npol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC4NPOL, (OutputPolarity << TIMER_CCEP_CC4NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 4 complementary output polarity. + * @param timx TIMER instance + * @retval Timer capture/compare 4 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_timer_get_cc4_complementary_polarity_cc4npol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC4NPOL)); +} + +/** + * @brief Timer capture/compare 4 output polarity setup. + * @param timx TIMER instance + * @param OutputPolarity Output polarity + @arg @ref MD_TIMER_OUTPUTPOLARITY_HIGH + @arg @ref MD_TIMER_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc4_output_polarity_cc4pol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC4POL, (OutputPolarity << TIMER_CCEP_CC4POL_POS)); +} + +__STATIC_INLINE void md_timer_set_cc4_input_edge_cc4pol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC4POL, (OutputPolarity << TIMER_CCEP_CC4POL_POS)); +} + +/** + * @brief Get timer capture/compare 4 output polarity. + * @param timx TIMER instance + * @retval Timer capture/compare 4 output polarity. + */ + +__STATIC_INLINE uint32_t md_timer_get_cc4_output_polarity_cc4pol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC4POL)); +} + +__STATIC_INLINE uint32_t md_timer_get_cc4_input_edge_cc4pol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC4POL)); +} + +/** + * @brief Timer Capture/Compare 4 output enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_cc4_output_cc4en(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC4EN); +} + +__STATIC_INLINE void md_timer_enable_cc4_input_cc4en(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC4EN); +} + +/** + * @brief Timer Capture/Compare 4 output disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_cc4_output_cc4en(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC4EN); +} + +__STATIC_INLINE void md_timer_disable_cc4_input_cc4en(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC4EN); +} + +/** + * @brief Indicates whether the timer Capture/Compare 4 output is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc4_output_cc4en(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC4EN) == (TIMER_CCEP_CC4EN)); +} + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc4_input_cc4en(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC4EN) == (TIMER_CCEP_CC4EN)); +} + +/** + * @brief Timer capture/compare 3 complementary output polarity setup. + * @param timx TIMER instance + * @param OutputPolarity Output polarity + @arg @ref MD_TIMER_OUTPUTPOLARITY_HIGH + @arg @ref MD_TIMER_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc3_complementary_polarity_cc3npol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC3NPOL, OutputPolarity << TIMER_CCEP_CC3NPOL_POS); +} + +/** + * @brief Get timer capture/compare 3 complementary output polarity. + * @param timx TIMER instance + * @retval Timer capture/compare 3 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_timer_get_cc3_complementary_polarity_cc3npol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC3NPOL) >> TIMER_CCEP_CC3NPOL_POS); +} + +/** + * @brief Timer Capture/Compare 3 complementary output enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_cc3_complementary_cc3nen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC3NEN); +} + +/** + * @brief Timer Capture/Compare 3 complementary output disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_cc3_complementary_cc3nen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC3NEN); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 complementary output is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc3_complementary_cc3nen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC3NEN) == (TIMER_CCEP_CC3NEN)); +} + +/** + * @brief Timer capture/compare 3 output polarity setup. + * @param timx TIMER instance + * @param OutputPolarity Output polarity + @arg @ref MD_TIMER_OUTPUTPOLARITY_HIGH + @arg @ref MD_TIMER_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc3_output_polarity_cc3pol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC3POL, (OutputPolarity << TIMER_CCEP_CC3POL_POS)); +} + +__STATIC_INLINE void md_timer_set_cc3_input_edge_cc3pol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC3POL, (OutputPolarity << TIMER_CCEP_CC3POL_POS)); +} + +/** + * @brief Get timer capture/compare 3 output polarity. + * @param timx TIMER instance + * @retval Timer capture/compare 3 output polarity. + */ + +__STATIC_INLINE uint32_t md_timer_get_cc3_output_polarity_cc3pol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC3POL)); +} + +__STATIC_INLINE uint32_t md_timer_get_cc3_input_edge_cc3pol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC3POL)); +} + +/** + * @brief Timer Capture/Compare 3 output enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_cc3_output_cc3en(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC3EN); +} + +__STATIC_INLINE void md_timer_enable_cc3_input_cc3en(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC3EN); +} + +/** + * @brief Timer Capture/Compare 3 output disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_cc3_output_cc3en(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC3EN); +} + +__STATIC_INLINE void md_timer_disable_cc3_input_cc3en(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC3EN); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 output is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc3_output_cc3en(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC3EN) == (TIMER_CCEP_CC3EN)); +} + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc3_input_cc3en(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC3EN) == (TIMER_CCEP_CC3EN)); +} + +/** + * @brief Timer capture/compare 2 complementary output polarity setup. + * @param timx TIMER instance + * @param OutputPolarity Output polarity + @arg @ref MD_TIMER_OUTPUTPOLARITY_HIGH + @arg @ref MD_TIMER_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc2_complementary_polarity_cc2npol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC2NPOL, (OutputPolarity << TIMER_CCEP_CC2NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 2 complementary output polarity. + * @param timx TIMER instance + * @retval Timer capture/compare 2 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_timer_get_cc2_complementary_polarity_cc2npol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC2NPOL)); +} + +/** + * @brief Timer Capture/Compare 2 complementary output enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_cc2_complementary_cc2nen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC2NEN); +} + +/** + * @brief Timer Capture/Compare 2 complementary output disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_cc2_complementary_cc2nen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC2NEN); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 complementary output is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc2_complementary_cc2nen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC2NEN) == (TIMER_CCEP_CC2NEN)); +} + +/** + * @brief Timer capture/compare 2 output polarity setup. + * @param timx TIMER instance + * @param OutputPolarity Output polarity + @arg @ref MD_TIMER_OUTPUTPOLARITY_HIGH + @arg @ref MD_TIMER_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc2_output_polarity_cc2pol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC2POL, (OutputPolarity << TIMER_CCEP_CC2POL_POS)); +} + +__STATIC_INLINE void md_timer_set_cc2_input_edge_cc2pol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC2POL, (OutputPolarity << TIMER_CCEP_CC2POL_POS)); +} + +/** + * @brief Get timer capture/compare 2 output polarity. + * @param timx TIMER instance + * @retval Timer capture/compare 2 output polarity. + */ + +__STATIC_INLINE uint32_t md_timer_get_cc2_output_polarity_cc2pol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC2POL) >> TIMER_CCEP_CC2POL_POS); +} + +__STATIC_INLINE uint32_t md_timer_get_cc2_input_edge_cc2pol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC2POL) >> TIMER_CCEP_CC2POL_POS); +} + +/** + * @brief Timer Capture/Compare 2 output enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_cc2_output_cc2en(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC2EN); +} + +__STATIC_INLINE void md_timer_enable_cc2_input_cc2en(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC2EN); +} + +/** + * @brief Timer Capture/Compare 2 output disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_cc2_output_cc2en(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC2EN); +} + +__STATIC_INLINE void md_timer_disable_cc2_input_cc2en(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC2EN); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 output is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc2_output_cc2en(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC2EN) == (TIMER_CCEP_CC2EN)); +} + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc2_input_cc2en(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC2EN) == (TIMER_CCEP_CC2EN)); +} + +/** + * @brief Timer capture/compare 1 complementary output polarity setup. + * @param timx TIMER instance + * @param OutputPolarity Output polarity + @arg @ref MD_TIMER_OUTPUTPOLARITY_HIGH + @arg @ref MD_TIMER_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc1_complementary_polarity_cc1npol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC1NPOL, (OutputPolarity << TIMER_CCEP_CC1NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 1 complementary output polarity. + * @param timx TIMER instance + * @retval Timer capture/compare 1 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_timer_get_cc1_complementary_polarity_cc1npol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC1NPOL)); +} + +/** + * @brief Timer Capture/Compare 1 complementary output enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_cc1_complementary_cc1nen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC1NEN); +} + +/** + * @brief Timer Capture/Compare 1 complementary output disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_cc1_complementary_cc1nen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC1NEN); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 complementary output is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc1_complementary_cc1nen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC1NEN) == (TIMER_CCEP_CC1NEN)); +} + +/** + * @brief Timer capture/compare 1 output polarity setup. + * @param timx TIMER instance + * @param OutputPolarity Output polarity + @arg @ref MD_TIMER_OUTPUTPOLARITY_HIGH + @arg @ref MD_TIMER_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_timer_set_cc1_output_polarity_cc1pol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC1POL, (OutputPolarity << TIMER_CCEP_CC1POL_POS)); +} + +__STATIC_INLINE void md_timer_set_cc1_input_edge_cc1pol(TIMER_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, TIMER_CCEP_CC1POL, (OutputPolarity << TIMER_CCEP_CC1POL_POS)); +} + +/** + * @brief Get timer capture/compare 1 output polarity. + * @param timx TIMER instance + * @retval Timer capture/compare 1 output polarity. + */ + +__STATIC_INLINE uint32_t md_timer_get_cc1_output_polarity_cc1pol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC1POL)); +} + +__STATIC_INLINE uint32_t md_timer_get_cc1_input_edge_cc1pol(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->CCEP, TIMER_CCEP_CC1POL)); +} + +/** + * @brief Timer Capture/Compare 1 output enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_cc1_output_cc1en(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC1EN); +} + +__STATIC_INLINE void md_timer_enable_cc1_input_cc1en(TIMER_TypeDef *timx) +{ + SET_BIT(timx->CCEP, TIMER_CCEP_CC1EN); +} + +/** + * @brief Timer Capture/Compare 1 output disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_cc1_output_cc1en(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC1EN); +} + +__STATIC_INLINE void md_timer_disable_cc1_input_cc1en(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, TIMER_CCEP_CC1EN); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 output is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc1_output_cc1en(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC1EN) == (TIMER_CCEP_CC1EN)); +} + +__STATIC_INLINE uint32_t md_timer_is_enabled_cc1_input_cc1en(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, TIMER_CCEP_CC1EN) == (TIMER_CCEP_CC1EN)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group15 COUNT + * @{ + */ +/** + * @brief Timer COUNT setup. + * @param timx TIMER instance + * @param value COUNT + * @retval None + */ + +__STATIC_INLINE void md_timer_set_counter_value_cntv(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->COUNT, value); +} + +/** + * @brief GET Timer COUNT register value. + * @param timx TIMER instance + * @retval Timer COUNT register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_counter_value_cntv(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->COUNT)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group16 PRES + * @{ + */ +/** + * @brief Timer PRES setup. + * @param timx TIMER instance + * @param value PRES + * @retval None + */ + +__STATIC_INLINE void md_timer_set_prescaler_value_pscv(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->PRES, value); +} + +/** + * @brief GET Timer PRES register value. + * @param timx TIMER instance + * @retval Timer PRES register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_prescaler_value_pscv(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->PRES)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group17 AR + * @{ + */ +/** + * @brief Timer AR setup. + * @param timx TIMER instance + * @param value AR + * @retval None + */ + +__STATIC_INLINE void md_timer_set_auto_reload_value_arrv(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->AR, value); +} + +/** + * @brief GET Timer AR register value. + * @param timx TIMER instance + * @retval Timer AR register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_auto_reload_value_arrv(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->AR)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group18 REPAR + * @{ + */ +/** + * @brief Timer REPAR setup. + * @param timx TIMER instance + * @param value REPAR + * @retval None + */ + +__STATIC_INLINE void md_timer_set_repetition_counter_value_repv(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->REPAR, value); +} + +/** + * @brief GET Timer REPAR register value. + * @param timx TIMER instance + * @retval Timer REPAR register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_repetition_counter_value_repv(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->REPAR)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group19 CCVAL1 + * @{ + */ +/** + * @brief Timer CCVAL1 setup. + * @param timx TIMER instance + * @param value CCVAL1 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_capture_compare1_value_ccrv1(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL1, value); +} + +/** + * @brief GET Timer CCVAL1 register value. + * @param timx TIMER instance + * @retval Timer CCVAL1 register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_capture_compare1_value_ccrv1(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->CCVAL1)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group20 CCVAL2 + * @{ + */ +/** + * @brief Timer CCVAL2 setup. + * @param timx TIMER instance + * @param value CCVAL2 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_capture_compare2_value_ccrv2(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL2, value); +} + +/** + * @brief GET Timer CCVAL2 register value. + * @param timx TIMER instance + * @retval Timer CCVAL2 register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_capture_compare2_value_ccrv2(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->CCVAL2)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group21 CCVAL3 + * @{ + */ +/** + * @brief Timer CCVAL3 setup. + * @param timx TIMER instance + * @param value CCVAL3 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_capture_compare3_value_ccrv3(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL3, value); +} + +/** + * @brief GET Timer CCVAL3 register value. + * @param timx TIMER instance + * @retval Timer CCVAL3 register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_capture_compare3_value_ccrv3(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->CCVAL3)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group22 CCVAL4 + * @{ + */ +/** + * @brief Timer CCVAL4 setup. + * @param timx TIMER instance + * @param value CCVAL4 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_capture_compare4_value_ccrv4(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL4, value); +} + +/** + * @brief GET Timer CCVAL4 register value. + * @param timx TIMER instance + * @retval Timer CCVAL4 register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_capture_compare4_value_ccrv4(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->CCVAL4)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group23 BDCFG + * @{ + */ +/** + * @brief Timer BDCFG setup. + * @param timx TIMER instance + * @param value (GOEN | AOEN | BRKP | BRKEN | OFFSSR | OFFSSI | LOCKLVL | DT) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_bdcfg(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->BDCFG, value); +} + +/** + * @brief GET Timer BDCFG register value. + * @param timx TIMER instance + * @retval Timer BDCFG register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_bdcfg(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->BDCFG)); +} + +/** + * @brief Timer main output enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_main_output_goen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->BDCFG, TIMER_BDCFG_GOEN); +} + +/** + * @brief Timer main output disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_main_output_goen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->BDCFG, TIMER_BDCFG_GOEN); +} + +/** + * @brief Indicates whether the timer main output is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_main_output_goen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, TIMER_BDCFG_GOEN) == (TIMER_BDCFG_GOEN)); +} + +/** + * @brief Timer automatic output enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_auto_output_aoen(TIMER_TypeDef *timx) +{ + SET_BIT(timx->BDCFG, TIMER_BDCFG_AOEN); +} + +/** + * @brief Timer automatic output disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_auto_output_aoen(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->BDCFG, TIMER_BDCFG_AOEN); +} + +/** + * @brief Indicates whether the timer automatic output is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_auto_output_aoen(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, TIMER_BDCFG_AOEN) == (TIMER_BDCFG_AOEN)); +} + +/** + * @brief Timer break polarity setup. + * @param timx TIMER instance + * @param BreakPolarity Break polarity + * @arg @ref MD_TIMER_BREAKPOLARITY_LOW + * @arg @ref MD_TIMER_BREAKPOLARITY_HIGH + * @retval None + */ + +__STATIC_INLINE void md_timer_set_break_polarity_brkp(TIMER_TypeDef *timx, uint32_t BreakPolarity) +{ + MODIFY_REG(timx->BDCFG, TIMER_BDCFG_BRKP, BreakPolarity << TIMER_BDCFG_BRKP_POS); +} + +/** + * @brief Get timer break polarity. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + * @arg @ref MD_TIMER_BREAKPOLARITY_LOW + * @arg @ref MD_TIMER_BREAKPOLARITY_HIGH + */ + +__STATIC_INLINE uint32_t md_timer_get_break_polarity_brkp(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->BDCFG, TIMER_BDCFG_BRKP) >> TIMER_BDCFG_BRKP_POS); +} + +/** + * @brief Timer break enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_break_brken(TIMER_TypeDef *timx) +{ + SET_BIT(timx->BDCFG, TIMER_BDCFG_BRKEN); +} + +/** + * @brief Timer break disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_break_brken(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->BDCFG, TIMER_BDCFG_BRKEN); +} + +/** + * @brief Indicates whether the timer break is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_break_brken(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, TIMER_BDCFG_BRKEN) == (TIMER_BDCFG_BRKEN)); +} + +/** + * @brief Timer off-state selection for run mode setup. + * @param timx TIMER instance + * @param OffStateRun Off-state selection for run mode + * @arg @ref MD_TIMER_OFFSTATERUN_DISABLE + * @arg @ref MD_TIMER_OFFSTATERUN_ENABLE + * @retval None + */ + +__STATIC_INLINE void md_timer_set_offstate_run_selection_offssr(TIMER_TypeDef *timx, uint32_t OffStateRun) +{ + MODIFY_REG(timx->BDCFG, TIMER_BDCFG_OFFSSR, OffStateRun << TIMER_BDCFG_OFFSSR_POS); +} + +/** + * @brief Get timer off-state selection for run mode. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + * @arg @ref MD_TIMER_OFFSTATERUN_DISABLE + * @arg @ref MD_TIMER_OFFSTATERUN_ENABLE + */ + +__STATIC_INLINE uint32_t md_timer_get_offstate_run_selection_offssr(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->BDCFG, TIMER_BDCFG_OFFSSR) >> TIMER_BDCFG_OFFSSR_POS); +} + +/** + * @brief Timer off-state selection for idle mode setup. + * @param timx TIMER instance + * @param OffStateIdle Off-state selection for idle mode + * @arg @ref MD_TIMER_OFFSTATEIDLE_DISABLE + * @arg @ref MD_TIMER_OFFSTATEIDLE_ENABLE + * @retval None + */ + +__STATIC_INLINE void md_timer_set_offstate_idle_selection_offssi(TIMER_TypeDef *timx, uint32_t OffStateIdle) +{ + MODIFY_REG(timx->BDCFG, TIMER_BDCFG_OFFSSI, OffStateIdle << TIMER_BDCFG_OFFSSI_POS); +} + +/** + * @brief Get timer off-state selection for idle mode. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + * @arg @ref MD_TIMER_OFFSTATEIDLE_DISABLE + * @arg @ref MD_TIMER_OFFSTATEIDLE_ENABLE + */ + +__STATIC_INLINE uint32_t md_timer_get_offstate_idle_selection_offssi(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->BDCFG, TIMER_BDCFG_OFFSSI) >> TIMER_BDCFG_OFFSSI_POS); +} + +/** + * @brief Timer lock configuration setup. + * @param timx TIMER instance + * @param LockLevel Lock configuration + * @arg @ref MD_TIMER_LOCKLEVEL_0 + * @arg @ref MD_TIMER_LOCKLEVEL_1 + * @arg @ref MD_TIMER_LOCKLEVEL_2 + * @arg @ref MD_TIMER_LOCKLEVEL_3 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_lock_config_locklvl(TIMER_TypeDef *timx, uint32_t LockLevel) +{ + MODIFY_REG(timx->BDCFG, TIMER_BDCFG_LOCKLVL, LockLevel << TIMER_BDCFG_LOCKLVL_POSS); +} + +/** + * @brief Get timer lock configuration. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + * @arg @ref MD_TIMER_LOCKLEVEL_0 + * @arg @ref MD_TIMER_LOCKLEVEL_1 + * @arg @ref MD_TIMER_LOCKLEVEL_2 + * @arg @ref MD_TIMER_LOCKLEVEL_3 + */ + +__STATIC_INLINE uint32_t md_timer_get_lock_config_locklvl(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->BDCFG, TIMER_BDCFG_LOCKLVL) >> TIMER_BDCFG_LOCKLVL_POSS); +} + +/** + * @brief Timer dead-time generator setup. + * @param timx TIMER instance + * @param DeadTime Dead-time generator (between Min_Data=0 and Max_Data=0xFF) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_dead_time_duration_dt(TIMER_TypeDef *timx, uint32_t DeadTime) +{ + MODIFY_REG(timx->BDCFG, TIMER_BDCFG_DT, DeadTime); +} + +/** + * @brief Get timer dead-time generator. + * @param timx TIMER instance + * @retval Timer dead-time generator. + */ + +__STATIC_INLINE uint32_t md_timer_get_dead_time_duration_dt(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->BDCFG, TIMER_BDCFG_DT)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group24 DMAEN + * @{ + */ +/** + * @brief Timer DMAEN setup. + * @param timx TIMER instance + * @param value (TRGI | COM | CH4 | CH3 | CH2 | CH1 | UPD) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_dmaen(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->DMAEN, value); +} + +/** + * @brief GET Timer DMAEN register value. + * @param timx TIMER instance + * @retval Timer DMAEN register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_dmaen(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->DMAEN)); +} + +/** + * @brief Timer trigger DMA request enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_dma_trgi(TIMER_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, TIMER_DMAEN_TRGI); +} + +/** + * @brief Timer trigger DMA request disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_dma_trgi(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, TIMER_DMAEN_TRGI); +} + +/** + * @brief Indicates whether the timer trigger DMA request is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_dma_trgi(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, TIMER_DMAEN_TRGI) == (TIMER_DMAEN_TRGI)); +} + +/** + * @brief Timer COM DMA request enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_dma_com(TIMER_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, TIMER_DMAEN_COM); +} + +/** + * @brief Timer COM DMA request disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_dma_com(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, TIMER_DMAEN_COM); +} + +/** + * @brief Indicates whether the timer trigger COM request is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_dma_com(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, TIMER_DMAEN_COM) == (TIMER_DMAEN_COM)); +} + +/** + * @brief Timer Capture/Compare 4 DMA request enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_dma_ch4(TIMER_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, TIMER_DMAEN_CH4); +} + +/** + * @brief Timer Capture/Compare 4 DMA request disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_dma_ch4(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, TIMER_DMAEN_CH4); +} + +/** + * @brief Indicates whether the timer Capture/Compare 4 DMA request is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_dma_ch4(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, TIMER_DMAEN_CH4) == (TIMER_DMAEN_CH4)); +} + +/** + * @brief Timer Capture/Compare 3 DMA request enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_dma_ch3(TIMER_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, TIMER_DMAEN_CH3); +} + +/** + * @brief Timer Capture/Compare 3 DMA request disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_dma_ch3(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, TIMER_DMAEN_CH3); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 DMA request is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_dma_ch3(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, TIMER_DMAEN_CH3) == (TIMER_DMAEN_CH3)); +} + +/** + * @brief Timer Capture/Compare 2 DMA request enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_dma_ch2(TIMER_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, TIMER_DMAEN_CH2); +} + +/** + * @brief Timer Capture/Compare 2 DMA request disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_dma_ch2(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, TIMER_DMAEN_CH2); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 DMA request is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_dma_ch2(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, TIMER_DMAEN_CH2) == (TIMER_DMAEN_CH2)); +} + +/** + * @brief Timer Capture/Compare 1 DMA request enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_dma_ch1(TIMER_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, TIMER_DMAEN_CH1); +} + +/** + * @brief Timer Capture/Compare 1 DMA request disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_dma_ch1(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, TIMER_DMAEN_CH1); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 DMA request is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_dma_ch1(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, TIMER_DMAEN_CH1) == (TIMER_DMAEN_CH1)); +} + +/** + * @brief Timer update DMA request enable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_enable_dma_upd(TIMER_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, TIMER_DMAEN_UPD); +} + +/** + * @brief Timer update DMA request disable. + * @param timx TIMER instance + * @retval None + */ + +__STATIC_INLINE void md_timer_disable_dma_upd(TIMER_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, TIMER_DMAEN_UPD); +} + +/** + * @brief Indicates whether the timer Capture/Compare update DMA request is enabled. + * @param timx TIMER instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_timer_is_enabled_dma_upd(TIMER_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, TIMER_DMAEN_UPD) == (TIMER_DMAEN_UPD)); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group25 OPTR + * @{ + */ +/** + * @brief Timer OPTR setup. + * @param timx TIMER instance + * @param value (ETR_RMP | CH4_RMP | CH3_RMP | CH2_RMP | CH1_RMP) + * @retval None + */ + +__STATIC_INLINE void md_timer_set_optr(TIMER_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->OPTR, value); +} + +/** + * @brief GET Timer OPTR register value. + * @param timx TIMER instance + * @retval Timer OPTR register value. + */ + +__STATIC_INLINE uint32_t md_timer_get_optr(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_REG(timx->OPTR)); +} + +/** + * @brief Timer ETR input remap setup. + * @param timx TIMER instance + * @param ETRInputSel ETR input selection + @arg @ref MD_TIMER_ETRRMP_ETR + @arg @ref MD_TIMER_ETRRMP_CMP1 + @arg @ref MD_TIMER_ETRRMP_CMP2 + @arg @ref MD_TIMER_ETRRMP_ADCAWD + * @retval None + */ + +__STATIC_INLINE void md_timer_set_external_trigger_select(TIMER_TypeDef *timx, uint32_t ETRInputSel) +{ + MODIFY_REG(timx->OPTR, TIMER_OPTR_ETR_RMP, ETRInputSel << TIMER_OPTR_ETR_RMP_POSS); +} + +/** + * @brief Get timer ETR input remap. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_ETRRMP_ETR + @arg @ref MD_TIMER_ETRRMP_CMP1 + @arg @ref MD_TIMER_ETRRMP_CMP2 + @arg @ref MD_TIMER_ETRRMP_ADCAWD + */ + +__STATIC_INLINE uint32_t md_timer_get_external_trigger_select(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->OPTR, TIMER_OPTR_ETR_RMP) >> TIMER_OPTR_ETR_RMP_POSS); +} + +/** + * @brief Timer channel 4 input remap setup. + * @param timx TIMER instance + * @param CH4InputSel channel 4 input selection + @arg @ref MD_TIMER_CH4RMP_CH4 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture4_select(TIMER_TypeDef *timx, uint32_t CH4InputSel) +{ + MODIFY_REG(timx->OPTR, TIMER_OPTR_CH4_RMP, CH4InputSel << TIMER_OPTR_CH4_RMP_POSS); +} + +/** + * @brief Get timer channel 4 input remap. + * @param timx TIMER instance + * @retval timer channel 4 input remap. + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture4_select(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->OPTR, TIMER_OPTR_CH4_RMP) >> TIMER_OPTR_CH4_RMP_POSS); +} + +/** + * @brief Timer channel 3 input remap setup. + * @param timx TIMER instance + * @param CH3InputSel channel 3 input selection + @arg @ref MD_TIMER_CH3RMP_CH3 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture3_select(TIMER_TypeDef *timx, uint32_t CH3InputSel) +{ + MODIFY_REG(timx->OPTR, TIMER_OPTR_CH3_RMP, CH3InputSel << TIMER_OPTR_CH3_RMP_POSS); +} + +/** + * @brief Get timer channel 3 input remap. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_CH3RMP_CH3 +*/ + +__STATIC_INLINE uint32_t md_timer_get_input_capture3_select(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->OPTR, TIMER_OPTR_CH3_RMP) >> TIMER_OPTR_CH3_RMP_POSS); +} + +/** + * @brief Timer channel 2 input remap setup. + * @param timx TIMER instance + * @param CH2InputSel channel 2 input selection + @arg @ref MD_TIMER_CH2RMP_CH2 + @arg @ref MD_TIMER_CH2RMP_CMP2 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture2_select(TIMER_TypeDef *timx, uint32_t CH2InputSel) +{ + MODIFY_REG(timx->OPTR, TIMER_OPTR_CH2_RMP, CH2InputSel << TIMER_OPTR_CH2_RMP_POSS); +} + +/** + * @brief Get timer channel 2 input remap. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_CH2RMP_CH2 + @arg @ref MD_TIMER_CH2RMP_CMP2 + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture2_select(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->OPTR, TIMER_OPTR_CH2_RMP) >> TIMER_OPTR_CH2_RMP_POSS); +} + +/** + * @brief Timer channel 1 input remap setup. + * @param timx TIMER instance + * @param CH1InputSel channel 1 input selection + @arg @ref MD_TIMER_CH1RMP_CH1 + @arg @ref MD_TIMER_CH1RMP_CMP1 + * @retval None + */ + +__STATIC_INLINE void md_timer_set_input_capture1_select(TIMER_TypeDef *timx, uint32_t CH1InputSel) +{ + MODIFY_REG(timx->OPTR, TIMER_OPTR_CH1_RMP, CH1InputSel << TIMER_OPTR_CH1_RMP_POSS); +} + +/** + * @brief Get timer channel 1 input remap. + * @param timx TIMER instance + * @retval The retval can be one of the following values: + @arg @ref MD_TIMER_CH1RMP_CH1 + @arg @ref MD_TIMER_CH1RMP_CMP1 + */ + +__STATIC_INLINE uint32_t md_timer_get_input_capture1_select(TIMER_TypeDef *timx) +{ + return (uint32_t)(READ_BIT(timx->OPTR, TIMER_OPTR_CH1_RMP) >> TIMER_OPTR_CH1_RMP_POSS); +} +/** + * @} + */ + +/** @defgroup MD_TIMER_Public_Functions_Group26 LL + * @{ + */ + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCEP CC1EN LL_TIMER_CC_EnableChannel\n + * CCEP CC1NEN LL_TIMER_CC_EnableChannel\n + * CCEP CC2EN LL_TIMER_CC_EnableChannel\n + * CCEP CC2NEN LL_TIMER_CC_EnableChannel\n + * CCEP CC3EN LL_TIMER_CC_EnableChannel\n + * CCEP CC3NEN LL_TIMER_CC_EnableChannel\n + * CCEP CC4EN LL_TIMER_CC_EnableChannel\n + * CCEP CC4NE LL_TIMER_CC_EnableChannel\n + * @param timx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH1N + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH2N + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH3N + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_CC_EnableChannel(TIMER_TypeDef *timx, uint32_t Channels) +{ + SET_BIT(timx->CCEP, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCEP CC1EN LL_TIMER_CC_DisableChannel\n + * CCEP CC1NEN LL_TIMER_CC_DisableChannel\n + * CCEP CC2EN LL_TIMER_CC_DisableChannel\n + * CCEP CC2NEN LL_TIMER_CC_DisableChannel\n + * CCEP CC3EN LL_TIMER_CC_DisableChannel\n + * CCEP CC3NEN LL_TIMER_CC_DisableChannel\n + * CCEP CC4EN LL_TIMER_CC_DisableChannel\n + * @param timx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH1N + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH2N + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH3N + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_CC_DisableChannel(TIMER_TypeDef *timx, uint32_t Channels) +{ + CLEAR_BIT(timx->CCEP, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCEP CC1EN LL_TIMER_CC_IsEnabledChannel\n + * CCEP CC1NEN LL_TIMER_CC_IsEnabledChannel\n + * CCEP CC2EN LL_TIMER_CC_IsEnabledChannel\n + * CCEP CC2NEN LL_TIMER_CC_IsEnabledChannel\n + * CCEP CC3EN LL_TIMER_CC_IsEnabledChannel\n + * CCEP CC3NEN LL_TIMER_CC_IsEnabledChannel\n + * CCEP CC4EN LL_TIMER_CC_IsEnabledChannel\n + * @param timx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH1N + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH2N + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH3N + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIMER_CC_IsEnabledChannel(TIMER_TypeDef *timx, uint32_t Channels) +{ + return ((READ_BIT(timx->CCEP, Channels) == (Channels)) ? 1UL : 0UL); +} + + +/** + * @brief Configure an output channel. + * @rmtoll CHMR1 CC1SSEL LL_TIMER_OC_ConfigOutput\n + * CHMR1 CC2SSEL LL_TIMER_OC_ConfigOutput\n + * CHMR2 CC3SSEL LL_TIMER_OC_ConfigOutput\n + * CHMR2 CC4SSEL LL_TIMER_OC_ConfigOutput\n + * CCEP CC1POL LL_TIMER_OC_ConfigOutput\n + * CCEP CC2POL LL_TIMER_OC_ConfigOutput\n + * CCEP CC3POL LL_TIMER_OC_ConfigOutput\n + * CCEP CC4POL LL_TIMER_OC_ConfigOutput\n + * CON2 OISS1 LL_TIMER_OC_ConfigOutput\n + * CON2 OISS2 LL_TIMER_OC_ConfigOutput\n + * CON2 OISS3 LL_TIMER_OC_ConfigOutput\n + * CON2 OISS4 LL_TIMER_OC_ConfigOutput\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIMER_OCPOLARITY_HIGH or @ref LL_TIMER_OCPOLARITY_LOW + * @arg @ref LL_TIMER_OCIDLESTATE_LOW or @ref LL_TIMER_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIMER_OC_ConfigOutput(TIMER_TypeDef *timx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + + CLEAR_BIT(*pReg, (TIMER_CHMR1_OUTPUT_CC1SSEL << SHIFT_TAB_OCxx[iChannel])); + + MODIFY_REG(timx->CCEP, (TIMER_CCEP_CC1POL << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIMER_CCEP_CC1POL) << SHIFT_TAB_CCxP[iChannel]); + + MODIFY_REG(timx->CON2, (TIMER_CON2_OISS1 << SHIFT_TAB_OISx[iChannel]), (Configuration & TIMER_CON2_OISS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CHMR1 CH1MOD LL_TIMER_OC_SetMode\n + * CHMR1 CH2MOD LL_TIMER_OC_SetMode\n + * CHMR2 CH3MOD LL_TIMER_OC_SetMode\n + * CHMR2 CH4MOD LL_TIMER_OC_SetMode\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIMER_OCMODE_FROZEN + * @arg @ref LL_TIMER_OCMODE_ACTIVE + * @arg @ref LL_TIMER_OCMODE_INACTIVE + * @arg @ref LL_TIMER_OCMODE_TOGGLE + * @arg @ref LL_TIMER_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIMER_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIMER_OCMODE_PWM1 + * @arg @ref LL_TIMER_OCMODE_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_OC_SetMode(TIMER_TypeDef *timx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + MODIFY_REG(*pReg, ((TIMER_CHMR1_OUTPUT_CH1MOD | TIMER_CHMR1_OUTPUT_CC1SSEL) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CHMR1 CH1MOD LL_TIMER_OC_GetMode\n + * CHMR1 CH2MOD LL_TIMER_OC_GetMode\n + * CHMR2 CH3MOD LL_TIMER_OC_GetMode\n + * CHMR2 CH4MOD LL_TIMER_OC_GetMode\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIMER_OCMODE_FROZEN + * @arg @ref LL_TIMER_OCMODE_ACTIVE + * @arg @ref LL_TIMER_OCMODE_INACTIVE + * @arg @ref LL_TIMER_OCMODE_TOGGLE + * @arg @ref LL_TIMER_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIMER_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIMER_OCMODE_PWM1 + * @arg @ref LL_TIMER_OCMODE_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIMER_OC_GetMode(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + return (READ_BIT(*pReg, ((TIMER_CHMR1_OUTPUT_CH1MOD | TIMER_CHMR1_OUTPUT_CC1SSEL) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCEP CC1POL LL_TIMER_OC_SetPolarity\n + * CCEP CC1NPOL LL_TIMER_OC_SetPolarity\n + * CCEP CC2POL LL_TIMER_OC_SetPolarity\n + * CCEP CC2NPOL LL_TIMER_OC_SetPolarity\n + * CCEP CC3POL LL_TIMER_OC_SetPolarity\n + * CCEP CC3NPOL LL_TIMER_OC_SetPolarity\n + * CCEP CC4POL LL_TIMER_OC_SetPolarity\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH1N + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH2N + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH3N + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIMER_OCPOLARITY_HIGH + * @arg @ref LL_TIMER_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIMER_OC_SetPolarity(TIMER_TypeDef *timx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(timx->CCEP, (TIMER_CCEP_CC1POL << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCEP CC1POL LL_TIMER_OC_GetPolarity\n + * CCEP CC1NPOL LL_TIMER_OC_GetPolarity\n + * CCEP CC2POL LL_TIMER_OC_GetPolarity\n + * CCEP CC2NPOL LL_TIMER_OC_GetPolarity\n + * CCEP CC3POL LL_TIMER_OC_GetPolarity\n + * CCEP CC3NPOL LL_TIMER_OC_GetPolarity\n + * CCEP CC4POL LL_TIMER_OC_GetPolarity\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH1N + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH2N + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH3N + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIMER_OCPOLARITY_HIGH + * @arg @ref LL_TIMER_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIMER_OC_GetPolarity(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(timx->CCEP, (TIMER_CCEP_CC1POL << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIMER_BREAK_INSTANCE(timx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CON2 OISS1 LL_TIMER_OC_SetIdleState\n + * CON2 OISS2N LL_TIMER_OC_SetIdleState\n + * CON2 OISS2 LL_TIMER_OC_SetIdleState\n + * CON2 OISS2N LL_TIMER_OC_SetIdleState\n + * CON2 OISS3 LL_TIMER_OC_SetIdleState\n + * CON2 OISS3N LL_TIMER_OC_SetIdleState\n + * CON2 OISS4 LL_TIMER_OC_SetIdleState\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH1N + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH2N + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH3N + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIMER_OCIDLESTATE_LOW + * @arg @ref LL_TIMER_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIMER_OC_SetIdleState(TIMER_TypeDef *timx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(timx->CON2, (TIMER_CON2_OISS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CON2 OISS1 LL_TIMER_OC_GetIdleState\n + * CON2 OISS2N LL_TIMER_OC_GetIdleState\n + * CON2 OISS2 LL_TIMER_OC_GetIdleState\n + * CON2 OISS2N LL_TIMER_OC_GetIdleState\n + * CON2 OISS3 LL_TIMER_OC_GetIdleState\n + * CON2 OISS3N LL_TIMER_OC_GetIdleState\n + * CON2 OISS4 LL_TIMER_OC_GetIdleState\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH1N + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH2N + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH3N + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIMER_OCIDLESTATE_LOW + * @arg @ref LL_TIMER_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIMER_OC_GetIdleState(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(timx->CON2, (TIMER_CON2_OISS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CHMR1 CH1FEN LL_TIMER_OC_EnableFast\n + * CHMR1 CH2FEN LL_TIMER_OC_EnableFast\n + * CHMR2 CH3FEN LL_TIMER_OC_EnableFast\n + * CHMR2 CH4FEN LL_TIMER_OC_EnableFast\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_OC_EnableFast(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + SET_BIT(*pReg, (TIMER_CHMR1_OUTPUT_CH1FEN << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CHMR1 CH1FEN LL_TIMER_OC_DisableFast\n + * CHMR1 CH2FEN LL_TIMER_OC_DisableFast\n + * CHMR2 CH3FEN LL_TIMER_OC_DisableFast\n + * CHMR2 CH4FEN LL_TIMER_OC_DisableFast\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_OC_DisableFast(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + CLEAR_BIT(*pReg, (TIMER_CHMR1_OUTPUT_CH1FEN << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CHMR1 CH1FEN LL_TIMER_OC_IsEnabledFast\n + * CHMR1 CH2FEN LL_TIMER_OC_IsEnabledFast\n + * CHMR2 CH3FEN LL_TIMER_OC_IsEnabledFast\n + * CHMR2 CH4FEN LL_TIMER_OC_IsEnabledFast\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIMER_OC_IsEnabledFast(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + uint32_t bitfield = TIMER_CHMR1_OUTPUT_CH1FEN << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (timx_CCRx) preload for the output channel. + * @rmtoll CHMR1 CH1PEN LL_TIMER_OC_EnablePreload\n + * CHMR1 CH2PEN LL_TIMER_OC_EnablePreload\n + * CHMR2 CH3PEN LL_TIMER_OC_EnablePreload\n + * CHMR2 CH4PEN LL_TIMER_OC_EnablePreload\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_OC_EnablePreload(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + SET_BIT(*pReg, (TIMER_CHMR1_OUTPUT_CH1PEN << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (timx_CCRx) preload for the output channel. + * @rmtoll CHMR1 CH1PEN LL_TIMER_OC_DisablePreload\n + * CHMR1 CH2PEN LL_TIMER_OC_DisablePreload\n + * CHMR2 CH3PEN LL_TIMER_OC_DisablePreload\n + * CHMR2 CH4PEN LL_TIMER_OC_DisablePreload\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_OC_DisablePreload(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + CLEAR_BIT(*pReg, (TIMER_CHMR1_OUTPUT_CH1PEN << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (timx_CCRx) preload is enabled for the output channel. + * @rmtoll CHMR1 CH1PEN LL_TIMER_OC_IsEnabledPreload\n + * CHMR1 CH2PEN LL_TIMER_OC_IsEnabledPreload\n + * CHMR2 CH3PEN LL_TIMER_OC_IsEnabledPreload\n + * CHMR2 CH4PEN LL_TIMER_OC_IsEnabledPreload\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIMER_OC_IsEnabledPreload(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + uint32_t bitfield = TIMER_CHMR1_OUTPUT_CH1PEN << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIMER_OCXREF_CLEAR_INSTANCE(timx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CHMR1 CH1OCLREN LL_TIMER_OC_EnableClear\n + * CHMR1 CH2OCLREN LL_TIMER_OC_EnableClear\n + * CHMR2 CH3OCLREN LL_TIMER_OC_EnableClear\n + * CHMR2 CH4OCLREN LL_TIMER_OC_EnableClear\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_OC_EnableClear(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + SET_BIT(*pReg, (TIMER_CHMR1_OUTPUT_CH1OCLREN << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIMER_OCXREF_CLEAR_INSTANCE(timx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CHMR1 CH1OCLREN LL_TIMER_OC_DisableClear\n + * CHMR1 CH2OCLREN LL_TIMER_OC_DisableClear\n + * CHMR2 CH3OCLREN LL_TIMER_OC_DisableClear\n + * CHMR2 CH4OCLREN LL_TIMER_OC_DisableClear\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_OC_DisableClear(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + CLEAR_BIT(*pReg, (TIMER_CHMR1_OUTPUT_CH1OCLREN << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIMER_OCXREF_CLEAR_INSTANCE(timx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CHMR1 CH1OCLREN LL_TIMER_OC_IsEnabledClear\n + * CHMR1 CH2OCLREN LL_TIMER_OC_IsEnabledClear\n + * CHMR2 CH3OCLREN LL_TIMER_OC_IsEnabledClear\n + * CHMR2 CH4OCLREN LL_TIMER_OC_IsEnabledClear\n + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIMER_OC_IsEnabledClear(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + uint32_t bitfield = TIMER_CHMR1_OUTPUT_CH1OCLREN << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Configure input channel. + * @rmtoll CHMR1 CC1SSEL LL_TIMER_IC_Config\n + * CHMR1 I1PRES LL_TIMER_IC_Config\n + * CHMR1 I1FLT LL_TIMER_IC_Config\n + * CHMR1 CC2SSEL LL_TIMER_IC_Config\n + * CHMR1 I2PRES LL_TIMER_IC_Config\n + * CHMR1 I2FLT LL_TIMER_IC_Config\n + * CHMR2 CC3SSEL LL_TIMER_IC_Config\n + * CHMR2 I3PRES LL_TIMER_IC_Config\n + * CHMR2 I3FLT LL_TIMER_IC_Config\n + * CHMR2 CC4SSEL LL_TIMER_IC_Config\n + * CHMR2 I4PRES LL_TIMER_IC_Config\n + * CHMR2 I4FLT LL_TIMER_IC_Config\n + * CCEP CC1POL LL_TIMER_IC_Config\n + * CCEP CC1NPOL LL_TIMER_IC_Config\n + * CCEP CC2POL LL_TIMER_IC_Config\n + * CCEP CC2NPOL LL_TIMER_IC_Config\n + * CCEP CC3POL LL_TIMER_IC_Config\n + * CCEP CC3NPOL LL_TIMER_IC_Config\n + * CCEP CC4POL LL_TIMER_IC_Config\n + * CCEP CC4NPOL LL_TIMER_IC_Config + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIMER_ACTIVEINPUT_DIRECTTI or @ref LL_TIMER_ACTIVEINPUT_INDIRECTTI or @ref LL_TIMER_ACTIVEINPUT_TRC + * @arg @ref LL_TIMER_ICPSC_DIV1 or ... or @ref LL_TIMER_ICPSC_DIV8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV1 or ... or @ref LL_TIMER_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIMER_IC_POLARITY_RISING or @ref LL_TIMER_IC_POLARITY_FALLING or @ref LL_TIMER_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIMER_IC_Config(TIMER_TypeDef *timx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + MODIFY_REG(*pReg, ((TIMER_CHMR1_INPUT_I1FLT | TIMER_CHMR1_INPUT_I1PRES | TIMER_CHMR1_INPUT_CC1SSEL) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIMER_CHMR1_INPUT_I1FLT | TIMER_CHMR1_INPUT_I1PRES | TIMER_CHMR1_INPUT_CC1SSEL)) << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(timx->CCEP, ((TIMER_CCEP_CC1NPOL | TIMER_CCEP_CC1POL) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIMER_CCEP_CC1NPOL | TIMER_CCEP_CC1POL)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CHMR1 CC1SSEL LL_TIMER_IC_SetActiveInput\n + * CHMR1 CC2SSEL LL_TIMER_IC_SetActiveInput\n + * CHMR2 CC3SSEL LL_TIMER_IC_SetActiveInput\n + * CHMR2 CC4SSEL LL_TIMER_IC_SetActiveInput + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIMER_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIMER_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIMER_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIMER_IC_SetActiveInput(TIMER_TypeDef *timx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + MODIFY_REG(*pReg, ((TIMER_CHMR1_INPUT_CC1SSEL) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CHMR1 CC1SSEL LL_TIMER_IC_GetActiveInput\n + * CHMR1 CC2SSEL LL_TIMER_IC_GetActiveInput\n + * CHMR2 CC3SSEL LL_TIMER_IC_GetActiveInput\n + * CHMR2 CC4SSEL LL_TIMER_IC_GetActiveInput + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIMER_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIMER_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIMER_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIMER_IC_GetActiveInput(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIMER_CHMR1_INPUT_CC1SSEL) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CHMR1 I1PRES LL_TIMER_IC_SetPrescaler\n + * CHMR1 I2PRES LL_TIMER_IC_SetPrescaler\n + * CHMR2 I3PRES LL_TIMER_IC_SetPrescaler\n + * CHMR2 I4PRES LL_TIMER_IC_SetPrescaler + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIMER_ICPSC_DIV1 + * @arg @ref LL_TIMER_ICPSC_DIV2 + * @arg @ref LL_TIMER_ICPSC_DIV4 + * @arg @ref LL_TIMER_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_IC_SetPrescaler(TIMER_TypeDef *timx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + MODIFY_REG(*pReg, ((TIMER_CHMR1_INPUT_I1PRES) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CHMR1 I1PRES LL_TIMER_IC_GetPrescaler\n + * CHMR1 I2PRES LL_TIMER_IC_GetPrescaler\n + * CHMR2 I3PRES LL_TIMER_IC_GetPrescaler\n + * CHMR2 I4PRES LL_TIMER_IC_GetPrescaler + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIMER_ICPSC_DIV1 + * @arg @ref LL_TIMER_ICPSC_DIV2 + * @arg @ref LL_TIMER_ICPSC_DIV4 + * @arg @ref LL_TIMER_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIMER_IC_GetPrescaler(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIMER_CHMR1_INPUT_I1PRES) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CHMR1 I1FLT LL_TIMER_IC_SetFilter\n + * CHMR1 I2FLT LL_TIMER_IC_SetFilter\n + * CHMR2 I3FLT LL_TIMER_IC_SetFilter\n + * CHMR2 I4FLT LL_TIMER_IC_SetFilter + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIMER_IC_FILTER_FDIV1 + * @arg @ref LL_TIMER_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIMER_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIMER_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIMER_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIMER_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIMER_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIMER_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIMER_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIMER_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIMER_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIMER_IC_SetFilter(TIMER_TypeDef *timx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + MODIFY_REG(*pReg, ((TIMER_CHMR1_INPUT_I1FLT) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CHMR1 I1FLT LL_TIMER_IC_GetFilter\n + * CHMR1 I2FLT LL_TIMER_IC_GetFilter\n + * CHMR2 I3FLT LL_TIMER_IC_GetFilter\n + * CHMR2 I4FLT LL_TIMER_IC_GetFilter + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIMER_IC_FILTER_FDIV1 + * @arg @ref LL_TIMER_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIMER_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIMER_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIMER_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIMER_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIMER_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIMER_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIMER_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIMER_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIMER_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIMER_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIMER_IC_GetFilter(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&timx->CHMR1) + OFFSET_TAB_CHMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIMER_CHMR1_INPUT_I1FLT) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCEP CC1POL LL_TIMER_IC_SetPolarity\n + * CCEP CC1NPOL LL_TIMER_IC_SetPolarity\n + * CCEP CC2POL LL_TIMER_IC_SetPolarity\n + * CCEP CC2NPOL LL_TIMER_IC_SetPolarity\n + * CCEP CC3POL LL_TIMER_IC_SetPolarity\n + * CCEP CC3NPOL LL_TIMER_IC_SetPolarity\n + * CCEP CC4POL LL_TIMER_IC_SetPolarity\n + * CCEP CC4NPOL LL_TIMER_IC_SetPolarity + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIMER_IC_POLARITY_RISING + * @arg @ref LL_TIMER_IC_POLARITY_FALLING + * @arg @ref LL_TIMER_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIMER_IC_SetPolarity(TIMER_TypeDef *timx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(timx->CCEP, ((TIMER_CCEP_CC1NPOL | TIMER_CCEP_CC1POL) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCEP CC1POL LL_TIMER_IC_GetPolarity\n + * CCEP CC1NPOL LL_TIMER_IC_GetPolarity\n + * CCEP CC2POL LL_TIMER_IC_GetPolarity\n + * CCEP CC2NPOL LL_TIMER_IC_GetPolarity\n + * CCEP CC3POL LL_TIMER_IC_GetPolarity\n + * CCEP CC3NPOL LL_TIMER_IC_GetPolarity\n + * CCEP CC4POL LL_TIMER_IC_GetPolarity\n + * CCEP CC4NPOL LL_TIMER_IC_GetPolarity + * @param timx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIMER_CHANNEL_CH1 + * @arg @ref LL_TIMER_CHANNEL_CH2 + * @arg @ref LL_TIMER_CHANNEL_CH3 + * @arg @ref LL_TIMER_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIMER_IC_POLARITY_RISING + * @arg @ref LL_TIMER_IC_POLARITY_FALLING + * @arg @ref LL_TIMER_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIMER_IC_GetPolarity(TIMER_TypeDef *timx, uint32_t Channel) +{ + uint8_t iChannel = TIMER_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(timx->CCEP, ((TIMER_CCEP_CC1NPOL | TIMER_CCEP_CC1POL) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ + diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_uart.c b/os/common/ext/CMSIS/ES32/FS026/md/md_uart.c new file mode 100644 index 00000000000..b481d6c57bf --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_uart.c @@ -0,0 +1,194 @@ +/********************************************************************************** + * + * @file md_uart.c + * @brief md_uart C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 27 Apr 2022 AE Team add function + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "system_fs026.h" +#include "md_uart.h" +#include + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief UART micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ + +/** @defgroup UART_PUB_FUNC UART Public Functions + * @brief UART Public Functions + * @{ + */ +/** + * @brief Set UARTx baudrate. + * @param UARTx UART Instance. + * @param Baudrate + * @retval None. + */ +void md_uart_setting_baudrate(UART_TypeDef *UARTx, uint32_t baudrate) +{ + uint32_t brr; + brr = ((SystemFrequency_APBClk + (baudrate >> 1)) / baudrate); + md_uart_set_baudrate(UARTx, brr); +} + +/** + * @brief UART Initialization + * @param UART Init Structure + * @retval None + */ +void md_uart_init(UART_TypeDef *UARTx, md_uart_init_typedef *UART_InitStruct) +{ + /* Check the UART_InitStruct */ + assert_param((UART_InitStruct != NULL)); + + md_uart_disable_tx(UARTx); + md_uart_disable_rx(UARTx); + md_uart_setting_baudrate(UARTx, UART_InitStruct->BaudRate); + + if (UART_InitStruct->BitOrder == MD_UART_LCON_MSB_FIRST) + md_uart_set_bitorder_msb(UARTx); + else + md_uart_set_bitorder_lsb(UARTx); + + md_uart_set_stop(UARTx, UART_InitStruct->StopBits); + md_uart_set_datawidth(UARTx, UART_InitStruct->DataWidth); + md_uart_set_parity(UARTx, UART_InitStruct->Parity); + + md_uart_enable_tx(UARTx); + md_uart_enable_rx(UARTx); +} + +/** + * @brief UARTx send character + * @param UART_TypeDef *UARTx. + * @param Character + * @retval None + */ +void md_uart_send(UART_TypeDef *UARTx, uint8_t data) +{ + while (!md_uart_is_active_flag_tfempty(UARTx)); // Tx FIFO empty + + md_uart_set_send_data8(UARTx, data); // Sent byte +} + + + +/** + * @brief UARTx send string + * @param UART_TypeDef *UARTx. + * @param Character address + * @param data length + * @retval None + */ +void md_uart_send_string(UART_TypeDef *UARTx, uint8_t *data, uint32_t len) +{ + int i = 0; + + for (i = 0; * (data + i) != '\0' && i < len; i++) + { + while (!md_uart_is_active_flag_tfempty(UARTx)); // Tx FIFO empty + + md_uart_set_send_data8(UARTx, *(data + i)); // Sent byte + } +} + + +/** + * @brief UARTx receive character. + * @param UART_TypeDef *UARTx. + * @retval unsigned char. + */ +uint8_t md_uart_receive(UART_TypeDef *UARTx) +{ + while (!md_uart_is_active_flag_rfnempty(UARTx)); // Rx FIFO not empty + + return (md_uart_get_recv_data8(UARTx)); +} + +/** + * @brief UARTx receive string. + * @param UART_TypeDef *UARTx. + * @param Character address + * @param data length + * @retval unsigned char. + */ +void md_uart_receive_string(UART_TypeDef *UARTx, uint8_t *data, uint32_t len) +{ + int i = 0; + + for (i = 0; i < len; i++) + { + while (!md_uart_is_active_flag_rfnempty(UARTx)); // Rx FIFO not empty + + *(data + i) = (md_uart_get_recv_data8(UARTx)); + } +} + + + +/** + * @brief Get UARTx baudrate. + * @param UART_TypeDef *UARTx. + * @retval Baudrate. + */ +uint32_t md_uart_getting_baudrate(UART_TypeDef *UARTx) +{ + uint32_t brr, baudrate; + + brr = md_uart_get_baudrate(UARTx); + baudrate = SystemFrequency_APBClk / brr; + return baudrate; +} + + +/** + * @} UART_PUB_FUNC UART Public Functions + */ + +/** + * @} UART + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_uart.h b/os/common/ext/CMSIS/ES32/FS026/md/md_uart.h new file mode 100644 index 00000000000..eed7674fa99 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_uart.h @@ -0,0 +1,2916 @@ +/********************************************************************************** + * + * @file md_uart.h + * @brief header file of md_uart.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 24 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_UART_H__ +#define __MD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "fs026.h" + + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_UART UART + * @brief UART micro driver + * @{ + */ + +/** @defgroup MD_UART_Pubulic_Types UART Pubulic Types + * @{ + */ + +/** + * @brief MD_UART_Public_Types UART Public Init Type + */ + +typedef struct +{ + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.*/ + + uint32_t BitOrder; /*!< Specifies the MSB of data bits will be transmitted or received first. + This parameter can be a value of @ref MD_UART_LCON_MSB_FIRST.*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref MD_UART_LCON_PS_EVEN.*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref MD_UART_LCON_STOP_1.*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref MD_UART_LCON_DLS_8.*/ + +} md_uart_init_typedef; + +/** + * @} + */ + +/** @defgroup MD_UART_Public_Macros UART Public Macros + * @{ + */ + +/** + * @brief UART_BAUDRATE UART Baudrate Definitation + */ +#define MD_UART_BAUDRATE_1200 (1200U) /* baud rate=1200 bps */ +#define MD_UART_BAUDRATE_2400 (2400U) /* baud rate=2400 bps */ +#define MD_UART_BAUDRATE_4800 (4800U) /* baud rate=4800 bps */ +#define MD_UART_BAUDRATE_9600 (9600U) /* baud rate=9600 bps */ +#define MD_UART_BAUDRATE_19200 (19200U) /* baud rate=19200 bps */ +#define MD_UART_BAUDRATE_38400 (38400U) /* baud rate=38400 bps */ +#define MD_UART_BAUDRATE_57600 (57600U) /* baud rate=57600 bps */ +#define MD_UART_BAUDRATE_115200 (115200U) /* baud rate=115200 bps */ +#define MD_UART_BAUDRATE_230400 (230400U) /* baud rate=230400 bps */ +#define MD_UART_BAUDRATE_460800 (460800U) /* baud rate=460800 bps */ +#define MD_UART_BAUDRATE_512000 (512000U) /* baud rate=512000 bps */ +#define MD_UART_BAUDRATE_921600 (921600U) /* baud rate=921600 bps */ + +/** + * @brief UART_LCON UART_LCON Register + */ +#define MD_UART_LCON_MSB_FIRST (1U) /** @brief data Most significant bit first */ +#define MD_UART_LCON_LSB_FIRST (0U) /** @brief data Least significant bit first */ + +#define MD_UART_LCON_PS_EVEN (3U) /** @brief data Even parity bit selection */ +#define MD_UART_LCON_PS_ODD (1U) /** @brief data Odd parity bit selection */ +#define MD_UART_LCON_PS_NONE (0U) /** @brief data No parity bit selection */ + +#define MD_UART_LCON_STOP_2 (1U) /** @brief data 2(1.5) Stop bit */ +#define MD_UART_LCON_STOP_1 (0U) /** @brief data 2(1.5) Stop bit */ +#define MD_UART_LCON_STOP_1P5 (1U) /** @brief data 2(1.5) Stop bit */ +#define MD_UART_LCON_STOP_0P5 (0U) + +#define MD_UART_LCON_DLS_8 (0U) /** @brief data Date length 8 */ +#define MD_UART_LCON_DLS_7 (1U) /** @brief data Date length 7 */ +#define MD_UART_LCON_DLS_6 (2U) /** @brief data Date length 6 */ +#define MD_UART_LCON_DLS_5 (3U) /** @brief data Date length 5 */ + +/** + * @brief UART_MCON UART_MCON Register + */ +#define MD_UART_MCON_TXFLOAT_HIGH (0) /** @brief When the transmitter is not transmitting, the TX pin outputs high level */ +#define MD_UART_MCON_TXFLOAT_FLOATING (1) /** @brief When the transmitter is not transmitting, the TX pin is floating */ + +#define MD_UART_MCON_ABRMOD_0 (0U) /** @brief data Receiver DMA disable */ +#define MD_UART_MCON_ABRMOD_1 (1U) /** @brief data Repeat auto-baud rate detection after timeout enable */ +#define MD_UART_MCON_ABRMOD_2 (2U) /** @brief data Repeat auto-baud rate detection after timeout disable */ + +#define MD_UART_MCON_RTSSET_HIGH (0U) /** @brief data RTSn set control bit RTSn level is 1 */ +#define MD_UART_MCON_RTSSET_LOW (1U) /** @brief data RTSn set control bit RTSn level is 0 */ + +/** + * @brief UART_RS485 UART_RS485 Register + */ +#define MD_UART_RS485_AADINV_LOW (0U) /** @brief data Low : Transfering data, High: Idle */ +#define MD_UART_RS485_AADINV_HIGH (1U) /** @brief data High: Transfering data, Low : Idle */ + +/** + * @brief UART_SCARD UART_SCARD Register + */ +#define MD_UART_SCARD_IRDA_AND_NORMAL_1_DIVIDE (1U) /** @brief 1 Divide, IRDA and NORMAL Mode*/ +#define MD_UART_SCARD_IRDA_AND_NORMAL_2_DIVIDE (2U) /** @brief 2 Divide, IRDA and NORMAL Mode*/ +#define MD_UART_SCARD_SMART_CARD_2_DIVIDE (1U) /** @brief 1 Divide, Smart Card Mode */ +#define MD_UART_SCARD_SMART_CARD_4_DIVIDE (2U) /** @brief 4 Divide, Smart Card Mode */ +#define MD_UART_SCARD_SMART_CARD_6_DIVIDE (3U) /** @brief 6 Divide, Smart Card Mode */ + +/** + * @brief UART_LIN UART_LIN Register + */ +#define MD_UART_LIN_LINBDL_10 (0) /** @brief 10-bit break character detection */ +#define MD_UART_LIN_LINBDL_11 (1) /** @brief 11-bit break character detection */ + +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions UART Public Functions + * @{ + */ + +/** @defgroup MD_UART_Public_Functions_Group2 RXDATA + * @{ + */ +/** + * @brief Read 8-Bits Receiver Buffer Register + * @note Contains the received data character. + * The RXBR register provides the parallel interface between the + * input shift register and the internal bus. + * When receiving with the parity enabled, the value read in the + * MSB bit is the received parity bit. + * @param UARTx UART Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t md_uart_get_recv_data8(UART_TypeDef *UARTx) +{ + return (uint8_t)(READ_REG(UARTx->RXDATA)); +} + +/** + * @brief Read 9-Bits Receiver Buffer Register + * @note Contains the received data character. + * The RXBR register provides the parallel interface between the + * input shift register and the internal bus. + * When receiving with the parity enabled, the value read in the + * MSB bit is the received parity bit. + * @param UARTx UART Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t md_uart_get_recv_data9(UART_TypeDef *UARTx) +{ + return (uint16_t)(READ_REG(UARTx->RXDATA)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group3 TXDATA + * @{ + */ +/** + * @brief Write 9-Bits Transmit buffer register + * @note Contains the data character to be transmitted. + * The TXBR register provides the parallel interface between the + * internal bus and the output shift register. + * When transmitting with the parity enabled the value written in + * the MSB (bit 7 or bit 8 depending on the data length) has no + * effect because it is replaced by the parity. + * @param UARTx UART Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void md_uart_set_send_data9(UART_TypeDef *UARTx, uint16_t TxData) +{ + WRITE_REG(UARTx->TXDATA, TxData); +} + +/** + * @brief Write 8-Bits Transmit buffer register + * @note Contains the data character to be transmitted. + * The TXBR register provides the parallel interface between the + * internal bus and the output shift register. + * When transmitting with the parity enabled the value written in + * the MSB (bit 7 or bit 8 depending on the data length) has no + * effect because it is replaced by the parity. + * @param UARTx UART Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void md_uart_set_send_data8(UART_TypeDef *UARTx, uint8_t TxData) +{ + WRITE_REG(UARTx->TXDATA, TxData); +} + +/** + * @brief Read 8-Bits Transmit buffer register + * @note Contains the data character to be transmitted. + * The TXBR register provides the parallel interface between the + * internal bus and the output shift register. + * When transmitting with the parity enabled the value written in + * the MSB (bit 7 or bit 8 depending on the data length) has no + * effect because it is replaced by the parity. + * @param UARTx UART Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE uint8_t md_uart_get_send_data8(UART_TypeDef *UARTx) +{ + return (uint8_t)(READ_REG(UARTx->TXDATA)); +} + +/** + * @brief Read 9-Bits Transmit buffer register + * @note Contains the data character to be transmitted. + * The TXBR register provides the parallel interface between the + * internal bus and the output shift register. + * When transmitting with the parity enabled the value written in + * the MSB (bit 7 or bit 8 depending on the data length) has no + * effect because it is replaced by the parity. + * @param UARTx UART Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE uint16_t md_uart_get_send_data9(UART_TypeDef *UARTx) +{ + return (uint16_t)(READ_REG(UARTx->TXDATA)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group4 BRR + * @{ + */ +/** + * @brief Set UARTx Baud rate register. + * @note This bits can only be written when the UART is disabled. + * (RXEN and TXEN=0 in the LCR register). + * @param UARTx UART Instance. + * @param UART buad rate value. + * @retval None + */ +__STATIC_INLINE void md_uart_set_baudrate(UART_TypeDef *UARTx, uint32_t baudrate) +{ + WRITE_REG(UARTx->BRR, baudrate); +} + +/** + * @brief Get UARTx baud rate. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval UARTx Baudrate. + */ +__STATIC_INLINE uint32_t md_uart_get_baudrate(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_REG(UARTx->BRR)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group5 LCON + * @{ + */ +/** + * @brief Set UART_LCON Register + * @param rcu RCU Instance + * @param lcon + */ +__STATIC_INLINE void md_uart_set_lcon(UART_TypeDef *UARTx, uint32_t lcon) +{ + WRITE_REG(UARTx->LCON, lcon); +} + +/** + * @brief Get UART_LCON Register + * @param rcu RCU Instance + * @retval UARTx LCON. + */ +__STATIC_INLINE uint32_t md_uart_get_lcon(UART_TypeDef *UARTx) +{ + return (uint32_t)READ_REG(UARTx->LCON); +} + +/** + * @brief UARTx Transmitter enable. + * @note This bit enables the transmitter. It is set and cleared by + * software. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_tx(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_TXEN); +} + +/** + * @brief UARTx Transmitter disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_tx(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_TXEN); +} + +/** + * @brief Check if UART Transmitter is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_tx(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_TXEN) == (UART_LCON_TXEN)); +} + +/** + * @brief UARTx Receiver enable + * @note This bit enables the receiver. It is set and cleared by software. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_rx(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_RXEN); +} + +/** + * @brief UARTx Receiver Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_rx(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_RXEN); +} + +/** + * @brief Check if UARTx Receiver is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rx(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_RXEN) == (UART_LCON_RXEN)); +} + +/** + * @brief UARTx Debounce Enable. + * @note This bit enables the debounce. It is set and cleared by software. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_dbcen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_DBCEN); +} + +/** + * @brief UART Debounce Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_dbcen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_DBCEN); +} + +/** + * @brief Check if UART Debounce is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_dbcen(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_DBCEN) == (UART_LCON_DBCEN)); +} + +/** + * @brief Enable UARTx Break control bit. + * @note This is used to cause a break condition to be transmitted to the + * receiving device. The serial data output (Tx) is forced to the + * Spacing State (logic 0). + * This bit can only be written when the UART is disabled. + * (RXENand TXEN=0). + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_break(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_BREAK); +} + +/** + * @brief Disable UARTx Break control bit. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_break(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_BREAK); +} + +/** + * @brief Check if UARTx Break control bit is enabled. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_break(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_BREAK) == (UART_LCON_BREAK)); +} + +/** + * @brief UARTx Swap TX/RX pins. + * @note This allows to work in the case of a cross-wired connection to another UART. + * This bit can only be written when the UART is disabled (RXEN and TXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_swap(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_SWAP); +} + +/** + * @brief UARTx Swap TX/RX pins disabl. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_disable_swap(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_SWAP); +} + +/** + * @brief Check if UART Swap TX/RX pins is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_swap(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_SWAP) == (UART_LCON_SWAP)); +} + +/** + * @brief UARTx TX pin active level inversion. + * @note This allows the use of an external inverter on the TX line. + * This bit can only be written when the UART is disabled (RXEN and TXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_txinv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_TXINV); +} + +/** + * @brief UARTx TX pin active level inversion disable. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_txinv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_TXINV); +} + +/** + * @brief Check if UARTx TX pin active level is inverted. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_txinv(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_TXINV) == (UART_LCON_TXINV)); +} + +/** + * @brief UARTx RX pin active level inversion. + * @note This allows the use of an external inverter on the RX line. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_rxinv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_RXINV); +} + +/** + * @brief UARTx RX pin active level inversion disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rxinv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_RXINV); +} + +/** + * @brief Check if UART RX pin active level is inverted. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rxinv(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_RXINV) == (UART_LCON_RXINV)); +} + +/** + * @brief UARTx Binary data inversion. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * The parity bit is also inverted. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_datainv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_DATAINV); +} + +/** + * @brief UARTx Binary data inverted disable. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_datainv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_DATAINV); +} + +/** + * @brief Check if UARTx Binary data is inverted. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_datainv(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_DATAINV) == (UART_LCON_DATAINV)); +} + +/** + * @brief Set UARTx Least significant bit first. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None + */ +__STATIC_INLINE void md_uart_set_bitorder_lsb(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_MSB); +} + +/** + * @brief Set UARTx Most significant bit first. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None + */ +__STATIC_INLINE void md_uart_set_bitorder_msb(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_MSB); +} + +/** + * @brief Get UARTx Most significant bit first bit. + * @param UARTx UART Instance + */ +__STATIC_INLINE uint32_t md_uart_get_bitorder(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_MSB) >> UART_LCON_MSB_POS); +} + +/** + * @brief UARTx Parity bit selection + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @param parity This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_PS_EVEN + * @arg @ref MD_UART_LCON_PS_ODD + * @arg @ref MD_UART_LCON_PS_NONE + * @retval None + */ +__STATIC_INLINE void md_uart_set_parity(UART_TypeDef *UARTx, uint32_t parity) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_PS | UART_LCON_PE, parity << UART_LCON_PE_POS); +} + +/** + * @brief Get UARTx Parity bit selection + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_UART_LCON_PS_EVEN + * @arg @ref MD_UART_LCON_PS_ODD + * @arg @ref MD_UART_LCON_PS_NONE + */ +__STATIC_INLINE uint32_t md_uart_get_parity(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_PS | UART_LCON_PE) >> UART_LCON_PE_POS); +} + +/** + * @brief Set UARTx Stop bit. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance. + * @param stop This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_STOP_1 (Nomal mode) + * @arg @ref MD_UART_LCON_STOP_2 (Nomal mode) + * @arg @ref MD_UART_LCON_STOP_1P5 (Smart card mode) + * @arg @ref MD_UART_LCON_STOP_0P5 (Smart card mode) + * @retval None + */ +__STATIC_INLINE void md_uart_set_stop(UART_TypeDef *UARTx, uint32_t stop) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_STOP, stop << UART_LCON_STOP_POS); +} + +/** + * @brief Get UARTx Stop bit. + * @param UARTx UART Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_UART_LCON_STOP_1 (Nomal mode) + * @arg @ref MD_UART_LCON_STOP_2 (Nomal mode) + * @arg @ref MD_UART_LCON_STOP_1P5 (Smart card mode) + * @arg @ref MD_UART_LCON_STOP_0P5 (Smart card mode) + */ +__STATIC_INLINE uint32_t md_uart_get_stop(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_STOP) >> UART_LCON_STOP_POS); +} + +/** + * @brief UARTx Date length selection. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @param width This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_DLS_8 + * @arg @ref MD_UART_LCON_DLS_7 + * @arg @ref MD_UART_LCON_DLS_6 + * @arg @ref MD_UART_LCON_DLS_5 + * @retval None + */ +__STATIC_INLINE void md_uart_set_datawidth(UART_TypeDef *UARTx, uint32_t width) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_DLS, width << UART_LCON_DLS_POSS); +} + +/** + * @brief Get UARTx data stop bit + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_UART_LCON_DLS_8 + * @arg @ref MD_UART_LCON_DLS_7 + * @arg @ref MD_UART_LCON_DLS_6 + * @arg @ref MD_UART_LCON_DLS_5 + */ +__STATIC_INLINE uint32_t md_uart_get_datawidth(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_DLS) >> UART_LCON_DLS_POSS); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group6 MCON + * @{ + */ +/** + * @brief Set UART_MCON Register + * @param rcu RCU Instance + * @param mcon + * @retval None + */ +__STATIC_INLINE void md_uart_set_mcon(UART_TypeDef *UARTx, uint32_t mcon) +{ + WRITE_REG(UARTx->MCON, mcon); +} + +/** + * @brief Get UART_MCON Register + * @param rcu RCU Instance + * @retval UART mode control + */ +__STATIC_INLINE uint32_t md_uart_get_mcon(UART_TypeDef *UARTx) +{ + return (uint32_t)READ_REG(UARTx->MCON); +} + +/** + * @brief Set Transmitter waits for sending status selection + * @param UARTx UART Instance. + * @param txfloat + @arg @ref MD_UART_MCON_TXFLOAT_HIGH + @arg @ref MD_UART_MCON_TXFLOAT_FLOATING + * @retval None + */ + +__STATIC_INLINE void md_uart_set_tx_floating(UART_TypeDef *UARTx, uint32_t txfloat) +{ + MODIFY_REG(UARTx->MCON, UART_MCON_TXFLOAT, txfloat << UART_MCON_TXFLOAT_POS); +} + +/** + * @brief Get Transmitter waits for sending status selection + * @param UARTx UART Instance + * @retval The retval can be one of the following values: + @arg @ref MD_UART_MCON_TXFLOAT_HIGH + @arg @ref MD_UART_MCON_TXFLOAT_FLOATING + */ +__STATIC_INLINE uint32_t md_uart_get_tx_floating(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_TXFLOAT >> UART_MCON_TXFLOAT_POS)); +} + +/** + * @brief UARTx Transmitter DMA enable. + * @note This bit is set and cleared by software. This bit enables the DMA transmitter. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_txdma(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_TXDMAEN); +} + +/** + * @brief UARTx Transmitter DMA enable disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_txdma(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_TXDMAEN); +} + +/** + * @brief Check if UARTx Transmitter DMA is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_txdma(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_TXDMAEN) == (UART_MCON_TXDMAEN)); +} + +/** + * @brief UARTx Receiver DMA enable. + * @note This bit is set and cleared by software. This bit enables the DMA Receiver. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_rxdma(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_RXDMAEN); +} + +/** + * @brief UARTx Receiver DMA disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rxdma(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_RXDMAEN); +} + +/** + * @brief Check if UARTx UARTx Receiver DMA is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rxdma(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_RXDMAEN) == (UART_MCON_RXDMAEN)); +} + +/** + * @brief UARTx Auto baud rate detection repeat enable. + * @note This bit is set to enable baud rate detection repeat one more time + * after the first failure of auto-baud rate detection. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_abrrept(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_ABRREPT); +} + +/** + * @brief UARTx Auto baud rate detection repeat disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_abrrept(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_ABRREPT); +} + +/** + * @brief Check if UARTx Auto baud rate detection repeat is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_abrrept(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_ABRREPT) == (UART_MCON_ABRREPT)); +} + +/** + * @brief Set UARTx Auto baud rate mode. + * @note MD_UART_MCON_ABRMOD_0: Mode 0 detect falling edge to second falling edge (detect 2 Bps). + * MD_UART_MCON_ABRMOD_1: Mode 1 detect falling edge to first rising edge (detect 1 Bps). + * MD_UART_MCON_ABRMOD_2: Mode 2 detect falling edge to first rising edge (detect 2 Bps). + * @param UARTx UART Instance. + * @param mode This parameter can be one of the following values: + * @arg @ref MD_UART_MCON_ABRMOD_0 + * @arg @ref MD_UART_MCON_ABRMOD_1 + * @arg @ref MD_UART_MCON_ABRMOD_2 + * @retval None + */ +__STATIC_INLINE void md_uart_set_abrmod(UART_TypeDef *UARTx, uint32_t mode) +{ + MODIFY_REG(UARTx->MCON, UART_MCON_ABRMOD, mode << UART_MCON_ABRMOD_POSS); +} + +/** + * @brief Get UARTx Auto baud rate mode. + * @param UARTx UART Instance. + * @retval The retval can be one of the following values: + * @arg @ref MD_UART_MCON_ABRMOD_0 + * @arg @ref MD_UART_MCON_ABRMOD_1 + * @arg @ref MD_UART_MCON_ABRMOD_2 + */ +__STATIC_INLINE uint32_t md_uart_get_abrmod(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_ABRMOD) >> UART_MCON_ABRMOD_POSS); +} + +/** + * @brief UARTx Auto baud rate enable. + * @note This bit is set by software and cleared by hardware after the + * auto-baud rate finish. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_abr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_ABREN); +} + +/** + * @brief UARTx Auto baud rate disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_abr(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_ABREN); +} + +/** + * @brief Check if UARTx Auto baud rate is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_abr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_ABREN) == (UART_MCON_ABREN)); +} + +/** + * @brief UARTx break request enable. + * @note This bit is set by software and automatically cleared by + * hardware in the next clock cycle. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_trigger_break_request(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_BKREQ); +} + +/** + * @brief UARTx Half-duplex enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_half_duplex(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_HDEN); +} + +/** + * @brief UARTx Half-duplex disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_half_duplex(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_HDEN); +} + +/** + * @brief Check if UARTx Half-duplex is enabled. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_half_duplex(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_HDEN) == (UART_MCON_HDEN)); +} + +/** + * @brief UARTx IrDA mode enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_irda(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_IREN); +} + +/** + * @brief UARTx IrDA mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_irda(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_IREN); +} + +/** + * @brief Check if UARTx IrDA mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_irda(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_IREN) == (UART_MCON_IREN)); +} + +/** + * @brief UARTx Auto flow control enable. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_auto_flow(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_AFCEN); +} + +/** + * @brief UARTx Auto flow control disable. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_auto_flow(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_AFCEN); +} + +/** + * @brief Check if Auto flow control is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_auto_flow(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_AFCEN) == (UART_MCON_AFCEN)); +} + +/** + * @brief Set UARTx RTSn set control bit. + * @note If Auto flow control disable, user can control RTSn output level by this bit. + * MD_UART_MCON_RTSSET_HIGH: RTSn level is 1 + * MD_UART_MCON_RTSSET_LOW : RTSn level is 0 + * @param UARTx UART Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_UART_MCON_RTSSET_HIGH + * @arg @ref MD_UART_MCON_RTSSET_LOW + * @retval None + */ +__STATIC_INLINE void md_uart_set_rtsset(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->MCON, UART_MCON_RTSSET, level >> UART_MCON_RTSSET_POS); +} + +/** + * @brief Get UARTx RTSn set control bit. + * @param UARTx UART Instance. + * @retval The retval can be one of the following values: + * @arg @ref MD_UART_MCON_RTSSET_HIGH + * @arg @ref MD_UART_MCON_RTSSET_LOW + */ +__STATIC_INLINE uint32_t md_uart_get_rtsset(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_RTSSET) >> UART_MCON_RTSSET_POS); +} + +/** + * @brief UARTx LoopBack enable. + * @note This is used to put the UART into a diagnostic mode for test purpose. + * If operating in UART mode, data on the TXD line is held high, + * while serial data output is looped back to the RXD line, internally. + * In this mode, all the interrupts are fully functional. + * If operating in infrared mode, data on the TXD with IrDA line is held low, + * while serial data output is inverted and looped back to the RXD line. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_loopback(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_LPBKEN); +} + +/** + * @brief UARTx LoopBack disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_loopback(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_LPBKEN); +} + +/** + * @brief Check if UARTx LoopBack is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_loopback(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_LPBKEN) == (UART_MCON_LPBKEN)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group7 RS485 + * @{ + */ +/** + * @brief Set UART_RS485 Register + * @param rcu RCU Instance + * @param rs485 + */ +__STATIC_INLINE void md_uart_set_rs485(UART_TypeDef *UARTx, uint32_t rs485) +{ + WRITE_REG(UARTx->RS485, rs485); +} + +/** + * @brief Get UART_RS485 Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_uart_get_rs485(UART_TypeDef *UARTx) +{ + return (uint32_t)READ_REG(UARTx->RS485); +} + +/** + * @brief Set UARTx Delay value. + * @note Contains a direction control RTSn Delay value. This register + * works in conjunction with an 8-bit counter in terms of number of + * DIVISOR bit duration. + * @param UARTx UART Instance. + * @param UARTx Delay value. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_rs485_dly(UART_TypeDef *UARTx, uint32_t delay) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_DLY, delay << UART_RS485_DLY_POSS); +} + +/** + * @brief Get UARTx Delay value. + * @param UARTx UART Instance. + * @retval UARTx Delay value. + */ +__STATIC_INLINE uint32_t md_uart_get_rs485_dly(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_DLY) >> UART_RS485_DLY_POSS); +} + +/** + * @brief Set UARTx Address match value. + * @param UARTx UART Instance. + * @param UARTx Address match value. + * @retval None + */ +__STATIC_INLINE void md_uart_set_rs485_addr(UART_TypeDef *UARTx, uint32_t address) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_ADDR, address << UART_RS485_ADDR_POSS); +} + +/** + * @brief Get UARTx Address match value. + * @param UARTx UART Instance. + * @retval UARTx Address match value. + */ +__STATIC_INLINE uint32_t md_uart_get_rs485_addr(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_ADDR) >> UART_RS485_ADDR_POSS); +} + +/** + * @brief Set UARTx Automatic address detection invert. + * @note This bit retains the DE(RTSn) polarity direction control signal on pin. + * @param UARTx UART Instance. + * @param aadinv can be one of the following value: + * @arg @ref MD_UART_RS485_AADINV_LOW (Low : Transfering data, High: Idle) + * @arg @ref MD_UART_RS485_AADINV_HIGH (High: Transfering data, Low : Idle) + * @retval None + */ +__STATIC_INLINE void md_uart_set_rs485_auto_addr_invert(UART_TypeDef *UARTx, uint32_t aadinv) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_AADINV, aadinv << UART_RS485_AADINV_POS); +} + +/** + * @brief Get UARTx Automatic address detection invert. + * @param UARTx UART Instance. + * @retval the retval can be one of the following value: + * @arg @ref MD_UART_RS485_AADINV_LOW (Low : Transfering data, High: Idle) + * @arg @ref MD_UART_RS485_AADINV_HIGH (High: Transfering data, Low : Idle) + */ +__STATIC_INLINE uint32_t md_uart_get_rs485_auto_addr_invert(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADINV) >> UART_RS485_AADINV_POS); +} + +/** + * @brief UARTx Automatic address detection auto-control enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_auto_dir_mode(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADACEN); +} + +/** + * @brief UARTx Automatic address detection auto-control disable + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_auto_dir_mode(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADACEN); +} + +/** + * @brief Check if UARTx Automatic address detection auto-control is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_auto_dir_mode(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RS485, UART_RS485_AADACEN) == (UART_RS485_AADACEN)); +} + +/** + * @brief UARTx Automatic address detection normal mode enable. + * @note Note that it can be active with RS-485 AAD operation mode. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_autoaddr_normal_mode(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADNEN); +} + +/** + * @brief UARTx Automatic address detection normal mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_autoaddr_normal_mode(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADNEN); +} + +/** + * @brief Check if Automatic address detection normal mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_autoaddr_normal_mode(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RS485, UART_RS485_AADNEN) == (UART_RS485_AADNEN)); +} + +/** + * @brief UARTx Automatic address detection operation mode enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_aaden(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADEN); +} + +/** + * @brief UARTx Automatic address detection operation mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_aaden(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADEN); +} + +/** + * @brief Check if UARTx Automatic address detection operation mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_aaden(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RS485, UART_RS485_AADEN) == (UART_RS485_AADEN)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group8 SCARD + * @{ + */ +/** + * @brief Set UART_SCARD Register + * @param rcu RCU Instance + * @param scard + */ +__STATIC_INLINE void md_uart_set_scard(UART_TypeDef *UARTx, uint32_t scard) +{ + WRITE_REG(UARTx->SCARD, scard); +} + +/** + * @brief Get UART_SCARD Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_uart_get_scard(UART_TypeDef *UARTx) +{ + return (uint32_t)READ_REG(UARTx->SCARD); +} + +/** + * @brief Set UARTx Block Length (Only UART). + * @note This bit-field gives the Block length in Smartcard T=1 + * Reception. Its value equals the number of information + * characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. + * This bit-field can be used also in other modes. In this case, the + * Block length counter is reset when RXEN=0 (receiver disabled). + * @param UARTx UART Instance. + * @param Block Length. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_rx_data_block_length(UART_TypeDef *UARTx, uint32_t blocklength) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_BLEN, blocklength << UART_SCARD_BLEN_POSS); +} + +/** + * @brief Get UARTx Block Length (Only UART). + * @param UARTx UART Instance. + * @retval Block Length. + */ +__STATIC_INLINE uint32_t md_uart_get_rx_data_block_length(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_BLEN) >> UART_SCARD_BLEN_POSS); +} + +/** + * @brief Set UARTx Guard time value(Only UART). + * @param UARTx UART Instance. + * @param Guard time value. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_scard_guardtime(UART_TypeDef *UARTx, uint32_t guardtime) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_GT, guardtime << UART_SCARD_GT_POSS); +} + +/** + * @brief Get UARTx Guard time value(Only UART). + * @param UARTx UART Instance. + * @retval Guard time value. + */ +__STATIC_INLINE uint32_t md_uart_get_scard_guardtime(UART_TypeDef *UARTx) +{ + return (uint32_t)((READ_BIT(UARTx->SCARD, UART_SCARD_GT)) >> UART_SCARD_GT_POSS); +} + +/** + * @brief Set UARTx Prescaler value (Only UART). + * @note In IrDA Low-power and normal IrDA mode: + * Used for programming the prescaler for dividing the UART + * source clock to achieve the low-power frequency. + * The source clock is divided by the value given in the register (8 + * significant bits) + * In Smartcard mode: + * Used for programming the prescaler for dividing the UART + * source clock to provide the Smartcard clock. + * The value given in the register (5 significant bits) is multiplied by + * 2 to give the division factor of the source clock frequency. + * @param UARTx UART Instance. + * @param Prescaler value. + @arg @ref MD_UART_SCARD_IRDA_AND_NORMAL_1_DIVIDE + @arg @ref MD_UART_SCARD_IRDA_AND_NORMAL_2_DIVIDE + @arg @ref MD_UART_SCARD_SMART_CARD_2_DIVIDE + @arg @ref MD_UART_SCARD_SMART_CARD_4_DIVIDE + @arg @ref MD_UART_SCARD_SMART_CARD_6_DIVIDE + * @retval None + */ +__STATIC_INLINE void md_uart_set_scard_psc(UART_TypeDef *UARTx, uint32_t prescaler) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_PSC, prescaler << UART_SCARD_PSC_POSS); +} + +/** + * @brief Get UARTx Prescaler value (Only UART). + * @param UARTx UART Instance. + * @retval The retval can be one of the following values: + @arg @ref MD_UART_SCARD_IRDA_AND_NORMAL_1_DIVIDE + @arg @ref MD_UART_SCARD_IRDA_AND_NORMAL_2_DIVIDE + @arg @ref MD_UART_SCARD_SMART_CARD_2_DIVIDE + @arg @ref MD_UART_SCARD_SMART_CARD_4_DIVIDE + @arg @ref MD_UART_SCARD_SMART_CARD_6_DIVIDE + */ +__STATIC_INLINE uint32_t md_uart_get_scard_psc(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_PSC) >> UART_SCARD_PSC_POSS); +} + +/** + * @brief Set UARTx Smartcard auto-retry count (Only UART). + * @note This bit-field specifies the number of retries in transmit and + * receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic + * retransmission retries, before generating a transmission error + * (FE bit set). + * In reception mode, it specifies the number or erroneous + * reception trials, before generating a reception error (RXNE and + * PE bits set). + * @param UARTx UART Instance. + * @param smartcard auto-retry count Min_Value=0x00 Max_Value=0x07. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_scard_sccnt(UART_TypeDef *UARTx, uint32_t count) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_SCCNT, count << UART_SCARD_SCCNT_POSS); +} + +/** + * @brief Get UARTx Smartcard auto-retry count (Only UART). + * @param UARTx UART Instance. + * @retval smartcard auto-retry count Min_Value=0x00 Max_Value=0x07 + */ +__STATIC_INLINE uint32_t md_uart_get_scard_sccnt(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCCNT) >> UART_SCARD_SCCNT_POSS); +} + +/** + * @brief Smartcard clock enable(Only UART). + * @note This bit allows the user to enable the SCK pin. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_scard_sclken(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCLKEN); +} + +/** + * @brief Smartcard clock disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_scard_sclken(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCLKEN); +} + +/** + * @brief Check if Smartcard clock is enable. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_sclken(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->SCARD, UART_SCARD_SCLKEN) == (UART_SCARD_SCLKEN)); +} + +/** + * @brief Smartcard NACK enable(Only UART). + * @note This bit allows the user to enable nack detection. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_scard_nack(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCNACK); +} + +/** + * @brief Smartcard NACK disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_scard_nack(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCNACK); +} + +/** + * @brief Check if Smartcard NACK is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_nack(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->SCARD, UART_SCARD_SCNACK) == (UART_SCARD_SCNACK)); +} + +/** + * @brief Smartcard mode enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_scard_mode(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCEN); +} + +/** + * @brief Smartcard mode disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_scard_mode(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCEN); +} + +/** + * @brief Check if Smartcard mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_mode(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->SCARD, UART_SCARD_SCEN) == (UART_SCARD_SCEN)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group9 LIN + * @{ + */ +/** + * @brief Set UART_LIN Register + * @param rcu RCU Instance + * @param lin + */ +__STATIC_INLINE void md_uart_set_lin(UART_TypeDef *UARTx, uint32_t lin) +{ + WRITE_REG(UARTx->LIN, lin); +} + +/** + * @brief Get UART_LIN Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_uart_get_lin(UART_TypeDef *UARTx) +{ + return (uint32_t)READ_REG(UARTx->LIN); +} + +/** + * @brief Enable LIN mode break request. + * @note This bit is set by software and automatically cleared by + * hardware in the next clock cycle. + * Writing 1 to this bit sets request to send a BREAK on the line, as + * soon as the transmit machine is available. + * It generates 13 bits rate low pulse in Lin mode. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_trigger_lin_break_request(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LIN, UART_LIN_LINBKREQ); +} + +/** + * @brief UARTx LIN mode disconnection word length + * @param UARTx UART Instance. + * @param linbdl LIN mode disconnection word length + @arg @ref MD_UART_LIN_LINBDL_10 + @arg @ref MD_UART_LIN_LINBDL_11 + * @retval None. + */ +__STATIC_INLINE void md_uart_set_lin_bk11(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LIN, UART_LIN_LINBDL); +} + +__STATIC_INLINE void md_uart_set_lin_bk10(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LIN, UART_LIN_LINBDL); +} + +/** + * @brief Get LIN mode disconnection word length + * @param UARTx UART Instance. + * @retval The retval can be one of the following values: + @arg @ref MD_UART_LIN_LINBDL_10 + @arg @ref MD_UART_LIN_LINBDL_11 + */ +__STATIC_INLINE uint32_t md_uart_get_lin_break_length(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LIN, UART_LIN_LINBDL) >> UART_LIN_LINBDL_POS); +} + +/** + * @brief UARTx LIN mode enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lin_mode(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LIN, UART_LIN_LINEN); +} + +/** + * @brief UART LIN mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lin_mode(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LIN, UART_LIN_LINEN); +} + +/** + * @brief Check if UARTx LIN mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lin_mode(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LIN, UART_LIN_LINEN) == (UART_LIN_LINEN)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group10 RTOR + * @{ + */ +/** + * @brief Set UART_RTOR Register + * @param rcu RCU Instance + * @param rtor + */ +__STATIC_INLINE void md_uart_set_rtor(UART_TypeDef *UARTx, uint32_t rtor) +{ + WRITE_REG(UARTx->RTOR, rtor); +} + +/** + * @brief Get UART_RTOR Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_uart_get_rtor(UART_TypeDef *UARTx) +{ + return (uint32_t)READ_REG(UARTx->RTOR); +} + +/** + * @brief UARTx receive timeout enable. + * @note When this feature is enabled, the RTOIF flag in the UART_RIF + * register is set if the RX line is idle (no reception) for the duration + * programmed in the RTOR (receiver timeout register). + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_rtoen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RTOR, UART_RTOR_RTOEN); +} + +/** + * @brief UARTx receive timeout disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rtoen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RTOR, UART_RTOR_RTOEN); +} + +/** + * @brief Check if UARTx receive timeout is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rtoen(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RTOR, UART_RTOR_RTOEN) == (UART_RTOR_RTOEN)); +} + +/** + * @brief Set UARTx receiver timeout value. + * @note This bit-field gives the Receiver timeout value in terms of number of bit duration. + * In standard mode: + * the RTOF flag is set if, after the last received character, + * no new start bit is detected for more than the RTO value. + * In Smartcard mode: + * this value is used to implement the CWT and BWT. See Smartcard section for more details. + * In this case, the timeout measurement is done starting from the Stop Bit of the last + * received character. + * @param UARTx UART Instance. + * @param timeout UART timeout value. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_rec_timeout(UART_TypeDef *UARTx, uint32_t timeout) +{ + MODIFY_REG(UARTx->RTOR, UART_RTOR_RTO, timeout); +} + +/** + * @brief Get UARTx receiver timeout value. + * @param UARTx UART Instance. + * @retval UART timeout value. + */ +__STATIC_INLINE uint32_t md_uart_get_rec_timeout(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RTOR, UART_RTOR_RTO)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group11 STAT + * @{ + */ +/** + * @brief Get UART_STAT Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_uart_get_stat(UART_TypeDef *UARTx) +{ + return READ_REG(UARTx->STAT); +} +/** + * @brief Check if Transmit FIFO overrun error. + * @note This bit is set and cleared by hardware Tx line start transmit + * data. An overrun error occurs when the FIFO is full and a new + * character write at the Transmit. The data in the FIFO is retained + * and the data in the TXBR register is lost. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_tfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFOERR) == (UART_STAT_TFOERR)); +} + +/** + * @brief Check if Transmit FIFO empty. + * @note This bit is set and cleared by hardware when the TX FIFO is no + * longer empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFEMPTY) == (UART_STAT_TFEMPTY)); +} + +/** + * @brief Check if Transmit shift register busy. + * @note This bit is cleared by hardware. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_tsbusy(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TSBUSY) == (UART_STAT_TSBUSY)); +} + +/** + * @brief Check if Receive FIFO underrun error. + * @note This bit is set and cleared by hardware when receive a new + * data. An underrun error occurs when the FIFO is empty at the + * receive. The data in the FIFO is read 0 in the RXBR register. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFUERR) == (UART_STAT_RFUERR)); +} + +/** + * @brief Check if Receive FIFO overrun error. + * @note This bit is set and cleared by hardware when read data in the + * RXBR register. An overrun error occurs when the FIFO is full + * and a new character arrives at the receiver. The data in the + * FIFO is retained and the data in the RXBR register is lost. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFOERR) == (UART_STAT_RFOERR)); +} + +/** + * @brief Check if Receive FIFO not empty. + * @note This bit is cleared when the RX FIFO is no longer not empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rfnempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFNEMPTY) == (UART_STAT_RFNEMPTY)); +} + +/** + * @brief Check if Receive shiftregister busy. + * @note This bit is set and cleared by hardware. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rsbusy(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RSBUSY) == (UART_STAT_RSBUSY)); +} + +/** + * @brief Get UARTx Clear to send status. + * @note This bit is the complement of CTSn. When CTSn is asserted, it + * is an indication that the modem or data set is ready to exchange + * data with UART. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ctssta(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_CTSSTA) >> UART_STAT_CTSSTA_POS); +} + +/** + * @brief Check if Break error. + * @note This bit is used to indicate the detection of a break sequence on + * the serial input data. + * This error is associated with the character at the top of the FIFO. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_bkerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_BKERR) == (UART_STAT_BKERR)); +} + +/** + * @brief Check if Framing Error. + * @note When the received characters stop bit is a logic 0(i.e. the + * receiver did not have a valid stop bit), a framing error occurs. + * This error is associated with the character at the top of the FIFO. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ferr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_FERR) == (UART_STAT_FERR)); +} + +/** + * @brief Check if Parity Error. + * @note When the receive character does not have correct parity + * information and is suspect, a parity error occurs. + * This error is associated with the character at the top of the FIFO. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_perr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_PERR) == (UART_STAT_PERR)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group12 IER + * @{ + */ +/** + * @brief Set UART_IER Register + * @param rcu RCU Instance + * @param ier + */ +__STATIC_INLINE void md_uart_set_ier(UART_TypeDef *UARTx, uint32_t ier) +{ + WRITE_REG(UARTx->IER, ier); +} + +/** + * @brief Transmit FIFO overrun interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_tfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TFOERR); +} + +/** + * @brief Transmit FIFO empty interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_tfempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TFEMPTY); +} + +/** + * @brief Transmission byte complete enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TBC); +} + +/** + * @brief Receive FIFO underrun interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFUERR); +} + +/** + * @brief Receive FIFO overrun interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFOERR); +} + +/** + * @brief Receive FIFO not empty interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_rfnempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFNEMPTY); +} + +/** + * @brief Bit Noise detection enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_NOISE); +} + +/** + * @brief End of block interrupt enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_EOB); +} + +/** + * @brief LINBK: LIN break detection interrupt enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_LINBK); +} + +/** + * @brief Address match interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ADDRM); +} + +/** + * @brief Receiver Timeout interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXTO); +} + +/** + * @brief Delta CTS status interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_DCTS); +} + +/** + * @brief Auto-Baud rate detection Timeout interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ABTO); +} + +/** + * @brief Auto-Baud rate detection End interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ABEND); +} + +/** + * @brief Receiver byte error interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXBERR); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group13 IDR + * @{ + */ +/** + * @brief Set UART_IDR Register + * @param rcu RCU Instance + * @param idr + */ +__STATIC_INLINE void md_uart_set_idr(UART_TypeDef *UARTx, uint32_t idr) +{ + WRITE_REG(UARTx->IDR, idr); +} +/** + * @brief Transmit FIFO overrun interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_tfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TFOERR); +} + +/** + * @brief Transmit FIFO empty interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_tfempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TFEMPTY); +} + +/** + * @brief Transmission byte complete interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TBC); +} + +/** + * @brief Receive FIFO underrun interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFUERR); +} + +/** + * @brief Receive FIFO overrun interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFOERR); +} + +/** + * @brief Receive FIFO not empty interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_rfnempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFNEMPTY); +} + +/** + * @brief Bit Noise detection disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_NOISE); +} + +/** + * @brief End of block interrupt disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_EOB); +} + +/** + * @brief LIN break detection interrupt disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_LINBK); +} + +/** + * @brief Address match interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ADDRM); +} + +/** + * @brief Receiver Timeout interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RXTO); +} + +/** + * @brief Delta CTS status interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_DCTS); +} + +/** + * @brief Auto-Baud rate detection Timeout interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ABTO); +} + +/** + * @brief Auto-Baud rate detection End interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ABEND); +} + +/** + * @brief Receiver byte error interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RXBERR); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group14 IVS + * @{ + */ +/** + * @brief Get UART_IVS Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_uart_get_ivs(UART_TypeDef *UARTx) +{ + return (uint32_t)READ_REG(UARTx->IVS); +} +/** + * @brief Check if Tx FIFO overrun interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_tfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TFOERR) == (UART_IVS_TFOERR)); +} + +/** + * @brief Check if Tx FIFO empty interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TFEMPTY) == (UART_IVS_TFEMPTY)); +} + +/** + * @brief Check if Tx complete interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TBC) == (UART_IVS_TBC)); +} + +/** + * @brief Check if Rx FIFO underrun interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFUERR) == (UART_IVS_RFUERR)); +} + +/** + * @brief Check if Rx FIFO overrun interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFOERR) == (UART_IVS_RFOERR)); +} + +/** + * @brief Check if Rx FIFO not empty interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_rfnempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFNEMPTY) == (UART_IVS_RFNEMPTY)); +} + +/** + * @brief Check if noise detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_NOISE) == (UART_IVS_NOISE)); +} + +/** + * @brief Check if end of block detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_EOB) == (UART_IVS_EOB)); +} + +/** + * @brief Check if LIN break detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_LINBK) == (UART_IVS_LINBK)); +} + +/** + * @brief Check if address match interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ADDRM) == (UART_IVS_ADDRM)); +} + +/** + * @brief Check if RX timeout interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RXTO) == (UART_IVS_RXTO)); +} + +/** + * @brief Check if delta CTS status interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_DCTS) == (UART_IVS_DCTS)); +} + +/** + * @brief Check if auto-baud rate detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ABTO) == (UART_IVS_ABTO)); +} + +/** + * @brief Check if auto-baud rate detection end interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ABEND) == (UART_IVS_ABEND)); +} + +/** + * @brief Check if RX byte error interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_it_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RXBERR) == (UART_IVS_RXBERR)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group15 RIF + * @{ + */ +/** + * @brief Set UART_RIF Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_uart_get_rif(UART_TypeDef *UARTx) +{ + return (uint32_t)READ_REG(UARTx->RIF); +} +/** + * @brief Get Transmit FIFO overrun interrupt flag. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character write at the Transmit. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_tfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TFOERR) == (UART_RIF_TFOERR)); +} + +/** + * @brief Get Transmit FIFO empty interrupt flag. + * @note This bit is set by hardware when transmit FIFO is empty from + * have data to empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TFEMPTY) == (UART_RIF_TFEMPTY)); +} + +/** + * @brief Get Transmission byte complete interrupt flag. + * @note This bit is set by hardware when transmission byte complete. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TBC) == (UART_RIF_TBC)); +} + +/** + * @brief Get Receive FIFO underrun interrupt flag + * @note This bit is set by hardware when an underrun error occurs that + * the FIFO is empty and a new character read at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFUERR) == (UART_RIF_RFUERR)); +} + +/** + * @brief Get Receive FIFO overrun interrupt flag. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character arrive at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFOERR) == (UART_RIF_RFOERR)); +} + +/** + * @brief Get Receive FIFO not empty interrupt flag. + * @note This bit is set by hardware when receive FIFO is full. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_rfnempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFNEMPTY) == (UART_RIF_RFNEMPTY)); +} + +/** + * @brief Get Bit Noise detection interrupt flag. + * @note This bit is set by hardware when START bit Noise is detected. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_NOISE) == (UART_RIF_NOISE)); +} + +/** + * @brief Get End of block interrupt flag(Only UART). + * @note This bit is set by hardware when blcok length value equals the + * number of data byte. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_EOB) == (UART_RIF_EOB)); +} + +/** + * @brief Get LIN break detection interrupt flag(Only UART). + * @note This bit is set by hardware when lin break is detected. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_LINBK) == (UART_RIF_LINBK)); +} + +/** + * @brief Get Address match interrupt flag. + * @note This bit is set by hardware when the data in the RXBR register + * defined by ADD[7:0] in the RS485 register is received. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ADDRM) == (UART_RIF_ADDRM)); +} + +/** + * @brief Get Receiver Timeout interrupt flag. + * @note This bit is set by hardware when the timeout value, + * programmed in the RTOR register has lapsed, without any + * communication. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RXTO) == (UART_RIF_RXTO)); +} + +/** + * @brief Get Delta CTS status interrupt flag. + * @note This bit is set by hardware when the CTS input toggles. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_DCTS) == (UART_RIF_DCTS)); +} + +/** + * @brief Get Auto-Baud rate detection timeout interrupt flag. + * @note This bit is set by hardware when the baud rate detection timeout. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ABTO) == (UART_RIF_ABTO)); +} + +/** + * @brief Get Auto-Baud rate detection end interrupt flag. + * @note This bit is set by hardware when the baud rate detection end. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ABEND) == (UART_RIF_ABEND)); +} + +/** + * @brief Get Receiver byte error flag. + * @note This bit is set by hardware when a parity error or frame error + * occurs in receiver. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RXBERR) == (UART_RIF_RXBERR)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group16 IFM + * @{ + */ +/** + * @brief Set UART_IFM Register + * @param rcu RCU Instance + */ +__STATIC_INLINE uint32_t md_uart_get_ifm(UART_TypeDef *UARTx) +{ + return (uint32_t)READ_REG(UARTx->IFM); +} +/** + * @brief Get Transmit FIFO overrun interrupt flag masked. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character write at the Transmit. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_tfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_TFOERR) == (UART_IFM_TFOERR)); +} + +/** + * @brief Get Transmit FIFO empty interrupt flag masked. + * @note This bit is set by hardware when transmit FIFO is empty from + * have data to empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_TFEMPTY) == (UART_IFM_TFEMPTY)); +} + +/** + * @brief Get Transmission byte complete interrupt flag masked. + * @note This bit is set by hardware when transmission byte complete. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_TBC) == (UART_IFM_TBC)); +} + +/** + * @brief Get Receive FIFO underrun interrupt flag masked. + * @note This bit is set by hardware when an underrun error occurs that + * the FIFO is empty and a new character read at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_RFUERR) == (UART_IFM_RFUERR)); +} + +/** + * @brief Get Receive FIFO overrun interrupt flag masked. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character arrive at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_RFOERR) == (UART_IFM_RFOERR)); +} + +/** + * @brief Get Receive FIFO not empty interrupt flag masked. + * @note This bit is set by hardware when receive FIFO is full. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_rfnempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_RFNEMPTY) == (UART_IFM_RFNEMPTY)); +} + +/** + * @brief Get Bit Noise detection interrupt flag masked. + * @note This bit is set by hardware when START bit Noise is detected. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_NOISE) == (UART_IFM_NOISE)); +} + +/** + * @brief Get End of block interrupt flag masked(Only UART). + * @note This bit is set by hardware when block length value equals the + * number of data byte. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_EOB) == (UART_IFM_EOB)); +} + +/** + * @brief Get LIN break detection interrupt flag masked(Only UART). + * @note This bit is set by hardware when lin break is detected. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_LINBK) == (UART_IFM_LINBK)); +} + +/** + * @brief Get Address match interrupt flag masked. + * @note This bit is set by hardware when the data in the RXBR register + * defined by ADD[7:0] in the RS485 register is received. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_ADDRM) == (UART_IFM_ADDRM)); +} + +/** + * @brief Get Receiver Timeout interrupt flag masked. + * @note This bit is set by hardware when the timeout value, + * programmed in the RTOR register has lapsed, without any + * communication. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_RXTO) == (UART_IFM_RXTO)); +} + +/** + * @brief Get Delta CTS status interrupt flag masked. + * @note This bit is set by hardware when the CTS input toggles. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_DCTS) == (UART_IFM_DCTS)); +} + +/** + * @brief Get Auto-Baud rate detection timeout interrupt flag masked. + * @note This bit is set by hardware when the baud rate detection timeout. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_ABTO) == (UART_IFM_ABTO)); +} + +/** + * @brief Get Auto-Baud rate detection end interrupt flag masked. + * @note This bit is set by hardware when the baud rate detection end. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_ABEND) == (UART_IFM_ABEND)); +} + +/** + * @brief Get Receiver byte error interrupt flag masked. + * @note This bit is set by hardware when a parity error, frame error or + * break error occurs in receiver. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_masked_it_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_RXBERR) == (UART_IFM_RXBERR)); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group17 ICR + * @{ + */ +/** + * @brief Set UART_ICR Register + * @param rcu RCU Instance + * @param icr + */ +__STATIC_INLINE void md_uart_set_icr(UART_TypeDef *UARTx, uint32_t icr) +{ + WRITE_REG(UARTx->ICR, icr); +} +/** + * @brief Transmit FIFO overrun interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_tfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TFOERR); +} + +/** + * @brief Transmit FIFO empty interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_tfempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TFEMPTY); +} + +/** + * @brief Transmission byte complete interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TBC); +} + +/** + * @brief Receive FIFO underrun interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFUERR); +} + +/** + * @brief Receive FIFO overrun interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFOERR); +} + +/** + * @brief Receive FIFO not empty interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_rfnempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFNEMPTY); +} + +/** + * @brief Bit Noise detection interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_NOISE); +} + +/** + * @brief End of block interrupt flag clear(Only UART). + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_EOB); +} + +/** + * @brief LIN break detection interrupt flag clear(Only UART). + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_LINBK); +} + +/** + * @brief Address match interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ADDRM); +} + +/** + * @brief Receiver Timeout interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RXTO); +} + +/** + * @brief Delta CTS status interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_DCTS); +} + +/** + * @brief Auto-Baud rate detection timeout interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ABTO); +} + +/** + * @brief Auto-Baud rate detection end interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ABEND); +} + +/** + * @brief Receiver byte error interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_it_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RXBERR); +} +/** + * @} + */ + +/** @defgroup MD_UART_Public_Functions_Group1 Initialization + * @{ + */ +/* Public functions -----------------------------------------------------------*/ +void md_uart_setting_baudrate(UART_TypeDef *UARTx, uint32_t baudrate); +void md_uart_init(UART_TypeDef *UARTx, md_uart_init_typedef *UART_InitStruct); +void md_uart_send(UART_TypeDef *UARTx, uint8_t ch); +void md_uart_send_string(UART_TypeDef *UARTx, uint8_t *data, uint32_t len); +void md_uart_receive_string(UART_TypeDef *UARTx, uint8_t *data, uint32_t len); +uint8_t md_uart_receive(UART_TypeDef *UARTx); +uint32_t md_uart_getting_baudrate(UART_TypeDef *UARTx); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_usb.h b/os/common/ext/CMSIS/ES32/FS026/md/md_usb.h new file mode 100644 index 00000000000..4138a22af4d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_usb.h @@ -0,0 +1,4365 @@ +/********************************************************************************** + * + * @file md_usb.h + * @brief header file of md_usb.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_USB_H__ +#define __MD_USB_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (USB) + +/** @defgroup USB USB + * @brief USB micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_USB_Public_Types USB Public Types + * @{ + */ + +/** + * @} MD_USB_Public_Types + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_USB_Public_Constants USB Public Constants + * @{ + */ + +#define MD_USB_DPDMCON_DPPUD_FLOATING (0x00) /** @brief DPDMCON DPPUD */ +#define MD_USB_DPDMCON_DPPUD_PULLUP (0x01) /** @brief DPDMCON DPPUD */ +#define MD_USB_DPDMCON_DPPUD_PULLDOWN (0x02) /** @brief DPDMCON DPPUD */ + +#define MD_USB_DPDMCON_DMPUD_FLOATING (0x00) /** @brief DPDMCON DMPUD */ +#define MD_USB_DPDMCON_DMPUD_PULLUP (0x01) /** @brief DPDMCON DMPUD */ +#define MD_USB_DPDMCON_DMPUD_PULLDOWN (0x02) /** @brief DPDMCON DMPPUD */ + +#define MD_USB_SWCID_HOST_HOST (0x00) /** @brief SWCID HOST */ +#define MD_USB_SWCID_HOST_DEVICE (0x01) /** @brief SWCID HOST */ + +#define MD_USB_SWCID_CIDCTRL_HARDWARE (0x00) /** @brief SWCID CIDCTRL */ +#define MD_USB_SWCID_CIDCTRL_SOFTWARE (0x01) /** @brief SWCID CIDCTRL */ + +#define MD_USB_SWVBUS_VALTH_LOWER_VBUS (0x00) /** @brief SWVBUS VALTH */ +#define MD_USB_SWVBUS_VALTH_HIGHER_VBUS (0x01) /** @brief SWVBUS VALTH */ + +#define MD_USB_SWVBUS_SESVALTH_LOWER_SESVAL (0x00) /** @brief SWVBUS SESVALTH */ +#define MD_USB_SWVBUS_SESVALTH_HIGHER_SESVAL (0x01) /** @brief SWVBUS SESVALTH */ + +#define MD_USB_SWVBUS_SESENDTH_LOWER_SESEND (0x00) /** @brief SWVBUS SESENDTH */ +#define MD_USB_SWVBUS_SESENDTH_HIGHER_SESEND (0x01) /** @brief SWVBUS SESENDTH */ + +#define MD_USB_SWVBUS_SIGCTRL_HARDWARE (0x00) /** @brief SWVBUS SIGCTRL */ +#define MD_USB_SWVBUS_SIGCTRL_SOFTWARE (0x01) /** @brief SWVBUS SIGCTRL */ + +#define MD_USB_TXTYPE_PROTOCOL_CONTROL (0x00) /** @brief TYPE PROTOCOL */ +#define MD_USB_TXTYPE_PROTOCOL_ISOCHRONOUS (0x01) /** @brief TYPE PROTOCOL */ +#define MD_USB_TXTYPE_PROTOCOL_BULK (0x02) /** @brief TYPE PROTOCOL */ +#define MD_USB_TXTYPE_PROTOCOL_INTERRUPT (0x03) /** @brief TYPE PROTOCOL */ + +#define MD_USB_RXTYPE_PROTOCOL_CONTROL (0x00) /** @brief TYPE PROTOCOL */ +#define MD_USB_RXTYPE_PROTOCOL_ISOCHRONOUS (0x01) /** @brief TYPE PROTOCOL */ +#define MD_USB_RXTYPE_PROTOCOL_BULK (0x02) /** @brief TYPE PROTOCOL */ +#define MD_USB_RXTYPE_PROTOCOL_INTERRUPT (0x03) /** @brief TYPE PROTOCOL */ + +#define MD_USB_TXFIFO2_MAXPKTSIZE_8 (0x00) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_TXFIFO2_MAXPKTSIZE_16 (0x01) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_TXFIFO2_MAXPKTSIZE_32 (0x02) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_TXFIFO2_MAXPKTSIZE_64 (0x03) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_TXFIFO2_MAXPKTSIZE_128 (0x04) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_TXFIFO2_MAXPKTSIZE_256 (0x05) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_TXFIFO2_MAXPKTSIZE_512 (0x06) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_TXFIFO2_MAXPKTSIZE_1024 (0x07) /** @brief FIFO MAXPKTSIZE */ + +#define MD_USB_RXFIFO2_MAXPKTSIZE_8 (0x00) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_RXFIFO2_MAXPKTSIZE_16 (0x01) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_RXFIFO2_MAXPKTSIZE_32 (0x02) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_RXFIFO2_MAXPKTSIZE_64 (0x03) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_RXFIFO2_MAXPKTSIZE_128 (0x04) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_RXFIFO2_MAXPKTSIZE_256 (0x05) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_RXFIFO2_MAXPKTSIZE_512 (0x06) /** @brief FIFO MAXPKTSIZE */ +#define MD_USB_RXFIFO2_MAXPKTSIZE_1024 (0x07) /** @brief FIFO MAXPKTSIZE */ + +#define MD_USB_TXCSRH_MODE_RX (0x00) /** @brief TXCSRH MODE */ +#define MD_USB_TXCSRH_MODE_TX (0x01) /** @brief TXCSRH MODE */ + +/** + * @} MD_USB_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_USB_Public_Macros USB Public Macros + * @{ + */ + +///** @defgroup MD_USB_PM_WRITE_READ Common write and read registers Macros +// * @{ +// */ + +///** +// * @brief Write a value in USB register +// * @param __INSTANCE__ USB Instance +// * @param __REG__ Register to be written +// * @param __VALUE__ Value to be written in the register +// * @retval None +// */ +//#define MD_USB_WRITEREG(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +///** +// * @brief Read a value in USB register +// * @param __INSTANCE__ USB Instance +// * @param __REG__ Register to be read +// * @retval Register value +// */ +//#define MD_USB_READREG(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +///** +// * @brief Modify value in USB register +// * @param __INSTANCE__ USB Instance +// * @param __REG__ Register to be written +// * @param __MASK__ Mask value to be written in the register +// * @param __VALUE__ Value to be written in the register +// * @retval None +// */ +//#define MD_USB_MODIFYREG(__INSTANCE__, __REG__, __MASK__, __VALUE__) MODIFY_REG(__INSTANCE__->__REG__, __MASK__, (__VALUE__)) + +///** +// * @brief Set bit value in USB register +// * @param __INSTANCE__ USB Instance +// * @param __REG__ Register to be written +// * @param __MASK__ Mask value to be set in the register +// * @retval None +// */ +//#define MD_USB_SET_BIT(__INSTANCE__, __REG__, __MASK__) SET_BIT(__INSTANCE__->__REG__, __MASK__) + +///** +// * @brief Clear bit value in USB register +// * @param __INSTANCE__ USB Instance +// * @param __REG__ Register to be written +// * @param __MASK__ Mask value to be cleared in the register +// * @retval None +// */ +//#define MD_USB_CLEAR_BIT(__INSTANCE__, __REG__, __MASK__) CLEAR_BIT(__INSTANCE__->__REG__, __MASK__) + +///** +// * @brief Read bit value in USB register +// * @param __INSTANCE__ USB Instance +// * @param __REG__ Register to be read +// * @param __MASK__ Mask value to be read in the register +// * @retval Register bit value +// */ +//#define MD_USB_READBIT(__INSTANCE__, __REG__, __MASK__) READ_BIT(__INSTANCE__->__REG__, __MASK__) +///** +// * @} MD_USB_PM_WRITE_READ +// */ + +/** @defgroup MD_USB_Macro_Drivers USB Public Macro Drivers + * @{ + */ + +/** + * @brief Set USB FADDR + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x7f + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_device_address(USB_TypeDef *usb, uint8_t Addr) +{ + MODIFY_REG(usb->FADDR, USB_FADDR_ADDR, Addr); +} + +/** + * @brief Get USB FADDR + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7f + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_device_address(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->FADDR, USB_FADDR_ADDR)); +} + +/** + * @brief Set USB POWER + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_power(USB_TypeDef *usb, uint8_t power) +{ + WRITE_REG(usb->POWER, power); +} + +/** + * @brief Get USB POWER + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_power(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->POWER)); +} + +/** + * @brief Enable USB POWER RESET + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_reset(USB_TypeDef *usb) +{ + SET_BIT(usb->POWER, USB_POWER_RESET); +} + +/** + * @brief Disable USB POWER RESET + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_reset(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->POWER, USB_POWER_RESET); +} + +/** + * @brief Is USB POWER RESET Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_reset(USB_TypeDef *usb) +{ + return (READ_BIT(usb->POWER, USB_POWER_RESET) == (USB_POWER_RESET)); +} + +/** + * @brief Enable USB POWER RESUME + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_resume(USB_TypeDef *usb) +{ + SET_BIT(usb->POWER, USB_POWER_RESUME); +} + +/** + * @brief Disable USB POWER RESUME + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_resume(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->POWER, USB_POWER_RESUME); +} + +/** + * @brief Is USB POWER RESUME Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_resume(USB_TypeDef *usb) +{ + return (READ_BIT(usb->POWER, USB_POWER_RESUME) == (USB_POWER_RESUME)); +} + +/** + * @brief Enable USB POWER SUSPEND + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_suspend(USB_TypeDef *usb) +{ + SET_BIT(usb->POWER, USB_POWER_SUSPEND); +} + +/** + * @brief Disable USB POWER SUSPEND + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_suspend(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->POWER, USB_POWER_SUSPEND); +} + +/** + * @brief Is USB POWER SUSPEND Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_suspend(USB_TypeDef *usb) +{ + return (READ_BIT(usb->POWER, USB_POWER_SUSPEND) == (USB_POWER_SUSPEND)); +} + +/** + * @brief Enable USB POWER ISOUDT + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_isochronous_update(USB_TypeDef *usb) +{ + SET_BIT(usb->POWER, USB_POWER_ISOUDT); +} + +/** + * @brief Disable USB POWER ISOUDT + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_isochronous_update(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->POWER, USB_POWER_ISOUDT); +} + +/** + * @brief Is USB POWER ISOUDT Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_isochronous_update(USB_TypeDef *usb) +{ + return (READ_BIT(usb->POWER, USB_POWER_ISOUDT) == (USB_POWER_ISOUDT)); +} + +/** + * @brief Enable USB POWER SUSPENDEN + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_entry_suspend_mode(USB_TypeDef *usb) +{ + SET_BIT(usb->POWER, USB_POWER_SUSPENDEN); +} + +/** + * @brief Disable USB POWER SUSPENDEN + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_entry_suspend_mode(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->POWER, USB_POWER_SUSPENDEN); +} + +/** + * @brief Is USB POWER SUSPENDEN Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_entry_suspend_mode(USB_TypeDef *usb) +{ + return (READ_BIT(usb->POWER, USB_POWER_SUSPENDEN) == (USB_POWER_SUSPENDEN)); +} + +/** + * @brief Set USB DPDMCON + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x1f + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_dpdmcon(USB_TypeDef *usb, uint8_t dpdmcon) +{ + WRITE_REG(usb->DPDMCON, dpdmcon); +} + +/** + * @brief Get USB DPDMCON + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x1f + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_dpdmcon(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->DPDMCON)); +} + +/** + * @brief Set USB DPDMCON DPPUD + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg @ref MD_USB_DPDMCON_DPPUD_FLOATING (0x00) : Floating + * @arg @ref MD_USB_DPDMCON_DPPUD_PULLUP (0x01) : Pull-Up + * @arg @ref MD_USB_DPDMCON_DPPUD_PULLDOWN (0x02) : Pull-Down + * @retval None + */ +__STATIC_INLINE void md_usb_set_dp_pull_up_pull_down(USB_TypeDef *usb, uint8_t Pud) +{ + MODIFY_REG(usb->DPDMCON, USB_DPDMCON_DPPUD, Pud << USB_DPDMCON_DPPUD_POSS); +} + +/** + * @brief Get USB DPDMCON DPPUD + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_USB_DPDMCON_DPPUD_FLOATING (0x00) : Floating + * @arg @ref MD_USB_DPDMCON_DPPUD_PULLUP (0x01) : Pull-Up + * @arg @ref MD_USB_DPDMCON_DPPUD_PULLDOWN (0x02) : Pull-Down + */ +__STATIC_INLINE uint8_t md_usb_get_dp_pull_up_pull_down(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->DPDMCON, USB_DPDMCON_DPPUD) >> USB_DPDMCON_DPPUD_POSS); +} + +/** + * @brief Set USB DPDMCON DMPUD + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg @ref MD_USB_DPDMCON_DMPUD_FLOATING (0x00) : Floating + * @arg @ref MD_USB_DPDMCON_DMPUD_PULLUP (0x01) : Pull-Up + * @arg @ref MD_USB_DPDMCON_DMPUD_PULLDOWN (0x02) : Pull-Down + * @retval None + */ +__STATIC_INLINE void md_usb_set_dm_pull_up_pull_down(USB_TypeDef *usb, uint8_t Pud) +{ + MODIFY_REG(usb->DPDMCON, USB_DPDMCON_DMPUD, Pud << USB_DPDMCON_DMPUD_POSS); +} + +/** + * @brief Get USB DPDMCON DMPUD + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_USB_DPDMCON_DMPUD_FLOATING (0x00) : Floating + * @arg @ref MD_USB_DPDMCON_DMPUD_PULLUP (0x01) : Pull-Up + * @arg @ref MD_USB_DPDMCON_DMPUD_PULLDOWN (0x02) : Pull-Down + */ +__STATIC_INLINE uint8_t md_usb_get_dm_pull_up_pull_down(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->DPDMCON, USB_DPDMCON_DMPUD) >> USB_DPDMCON_DMPUD_POSS); +} + +/** + * @brief Enable USB DPDMCON PHYPWREN + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_phy_power(USB_TypeDef *usb) +{ + SET_BIT(usb->DPDMCON, USB_DPDMCON_PHYPWREN); +} + +/** + * @brief Disable USB DPDMCON PHYPWREN + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_phy_power(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->DPDMCON, USB_DPDMCON_PHYPWREN); +} + +/** + * @brief Is USB DPDMCON PHYPWREN Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_phy_power(USB_TypeDef *usb) +{ + return (READ_BIT(usb->DPDMCON, USB_DPDMCON_PHYPWREN) == (USB_DPDMCON_PHYPWREN)); +} + +/** + * @brief Set USB SWCID + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x3 + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_swcid(USB_TypeDef *usb, uint8_t swcid) +{ + WRITE_REG(usb->SWCID, swcid); +} + +/** + * @brief Get USB SWCID + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x3 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_swcid(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->SWCID)); +} + +/** + * @brief Set USB SWCID HOST Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_set_software_control_host_mode(USB_TypeDef *usb) +{ + MODIFY_REG(usb->SWCID, USB_SWCID_HOST, MD_USB_SWCID_HOST_HOST << USB_SWCID_HOST_POS); +} + +/** + * @brief Set USB SWCID DEVICE Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_set_software_control_device_mode(USB_TypeDef *usb) +{ + MODIFY_REG(usb->SWCID, USB_SWCID_HOST, MD_USB_SWCID_HOST_DEVICE << USB_SWCID_HOST_POS); +} + +/** + * @brief Get USB SWCID HOST/DEVICE Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + @arg @ref MD_USB_SWCID_HOST_HOST + @arg @ref MD_USB_SWCID_HOST_DEVICE + */ +__STATIC_INLINE uint8_t md_usb_get_software_control_mode(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->SWCID, USB_SWCID_HOST) >> USB_SWCID_HOST_POS); +} + +/** + * @brief Set USB SWCID CIDCTRL + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_software_control_cid(USB_TypeDef *usb) +{ + MODIFY_REG(usb->SWCID, USB_SWCID_CIDCTRL, MD_USB_SWCID_CIDCTRL_SOFTWARE << USB_SWCID_CIDCTRL_POS); +} + +/** + * @brief Set USB SWCID CIDCTRL + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_software_control_cid(USB_TypeDef *usb) +{ + MODIFY_REG(usb->SWCID, USB_SWCID_CIDCTRL, MD_USB_SWCID_CIDCTRL_HARDWARE << USB_SWCID_CIDCTRL_POS); +} + +/** + * @brief Is USB SWCID CIDCTRL + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_software_control_cid(USB_TypeDef *usb) +{ + return (READ_BIT(usb->SWCID, USB_SWCID_CIDCTRL) == (USB_SWCID_CIDCTRL)); +} + +/** + * @brief Set USB SWVBUS + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xf + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_swvbus(USB_TypeDef *usb, uint8_t swvbus) +{ + WRITE_REG(usb->SWVBUS, swvbus); +} + +/** + * @brief Get USB SWVBUS + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xf + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_swvbus(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->SWVBUS)); +} + +/** + * @brief Set USB SWVBUS VALTH + * @param usb USB Instance + * @param valth + @arg @ref MD_USB_SWVBUS_VALTH_LOWER_VBUS + @arg @ref MD_USB_SWVBUS_VALTH_HIGHER_VBUS + * @retval None + */ +__STATIC_INLINE void md_usb_set_vbus_valid_threshold(USB_TypeDef *usb, uint8_t valth) +{ + MODIFY_REG(usb->SWVBUS, USB_SWVBUS_VALTH, valth << USB_SWVBUS_VALTH_POS); +} + +/** + * @brief Get USB SWVBUS VALTH + * @param usb USB Instance + * @retval The retval can be one of the following values: + @arg @ref MD_USB_SWVBUS_VALTH_LOWER_VBUS + @arg @ref MD_USB_SWVBUS_VALTH_HIGHER_VBUS + */ +__STATIC_INLINE uint8_t md_usb_get_vbus_valid_threshold(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->SWVBUS, USB_SWVBUS_VALTH) >> USB_SWVBUS_VALTH_POS); +} + +/** + * @brief Set USB SWVBUS SESVALTH + * @param usb USB Instance + * @param sesvalth + @arg @ref MD_USB_SWVBUS_SESVALTH_LOWER_SESVAL + @arg @ref MD_USB_SWVBUS_SESVALTH_HIGHER_SESVAL + * @retval None + */ +__STATIC_INLINE void md_usb_set_session_valid_threshold(USB_TypeDef *usb, uint8_t sesvalth) +{ + MODIFY_REG(usb->SWVBUS, USB_SWVBUS_SESVALTH, sesvalth << USB_SWVBUS_SESVALTH_POS); +} + +/** + * @brief Get USB SWVBUS SESVALTH + * @param usb USB Instance + * @retval The retval can be one of the following values: + @arg @ref MD_USB_SWVBUS_SESVALTH_LOWER_SESVAL + @arg @ref MD_USB_SWVBUS_SESVALTH_HIGHER_SESVAL + */ +__STATIC_INLINE uint8_t md_usb_get_session_valid_threshold(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->SWVBUS, USB_SWVBUS_SESVALTH) >> USB_SWVBUS_SESVALTH_POS); +} + +/** + * @brief Set USB SWVBUS SESENDTH + * @param usb USB Instance + * @param sesendth + @arg @ref MD_USB_SWVBUS_SESENDTH_LOWER_SESEND + @arg @ref MD_USB_SWVBUS_SESENDTH_HIGHER_SESEND + * @retval None + */ +__STATIC_INLINE void md_usb_set_session_end_threshold(USB_TypeDef *usb, uint8_t sesendth) +{ + MODIFY_REG(usb->SWVBUS, USB_SWVBUS_SESENDTH, sesendth << USB_SWVBUS_SESENDTH_POS); +} + +/** + * @brief Get USB SWVBUS SESENDTH + * @param usb USB Instance + * @retval The retval can be one of the following values: + @arg @ref MD_USB_SWVBUS_SESENDTH_LOWER_SESEND + @arg @ref MD_USB_SWVBUS_SESENDTH_HIGHER_SESEND + */ +__STATIC_INLINE uint8_t md_usb_get_session_end_threshold(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->SWVBUS, USB_SWVBUS_SESENDTH) >> USB_SWVBUS_SESENDTH_POS); +} + +/** + * @brief Set USB SWVBUS Hardware Control + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_set_vbus_hardware_control(USB_TypeDef *usb) +{ + MODIFY_REG(usb->SWVBUS, USB_SWVBUS_SIGCTRL, MD_USB_SWVBUS_SIGCTRL_HARDWARE << USB_SWVBUS_SIGCTRL_POS); +} + +/** + * @brief Set USB SWVBUS Software Control + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_set_vbus_software_control(USB_TypeDef *usb) +{ + MODIFY_REG(usb->SWVBUS, USB_SWVBUS_SIGCTRL, MD_USB_SWVBUS_SIGCTRL_SOFTWARE << USB_SWVBUS_SIGCTRL_POS); +} + +/** + * @brief Get USB SWVBUS SIGCTRL + * @param usb USB Instance + * @retval The retval can be one of the following values: + @arg @ref MD_USB_SWVBUS_SIGCTRL_HARDWARE + @arg @ref MD_USB_SWVBUS_SIGCTRL_SOFTWARE + */ +__STATIC_INLINE uint8_t md_usb_get_vbus_control_mode(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->SWVBUS, USB_SWVBUS_SIGCTRL) >> USB_SWVBUS_SIGCTRL_POS); +} + +/** + * @brief Get USB FRAME COUNTER + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7FF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint16_t md_usb_get_frame_number(USB_TypeDef *usb) +{ + return (uint16_t)((READ_BIT(usb->FRAME2, USB_FRAME2_UPFRAME) << 8) | (READ_BIT(usb->FRAME1, USB_FRAME1_LOWFRAME))); +} + +/** + * @brief Set USB EPTIDX + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xf + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_epx_index(USB_TypeDef *usb, uint8_t Index) +{ + MODIFY_REG(usb->INDEX, USB_INDEX_EPTIDX, Index); +} + +/** + * @brief Get USB EPTIDX + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xf + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_epx_index(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->INDEX, USB_INDEX_EPTIDX)); +} + +/** + * @brief Set USB DEVCON + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_devcon(USB_TypeDef *usb, uint8_t devcon) +{ + WRITE_REG(usb->DEVCON, devcon); +} + +/** + * @brief Get USB DEVCON + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_devcon(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->DEVCON)); +} + +/** + * @brief Is USB DEVCON CID A TYPE Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : True + * @arg 0x0 : False + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_cid_a_type(USB_TypeDef *usb) +{ + return (READ_BIT(usb->DEVCON, USB_DEVCON_CID) != (USB_DEVCON_CID)); +} + +/** + * @brief Is USB DEVCON CID B TYPE Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : True + * @arg 0x0 : False + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_cid_b_type(USB_TypeDef *usb) +{ + return (READ_BIT(usb->DEVCON, USB_DEVCON_CID) == (USB_DEVCON_CID)); +} + +/** + * @brief Is USB DEVCON FSDEV Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : True + * @arg 0x0 : False + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_full_speed_detected(USB_TypeDef *usb) +{ + return (READ_BIT(usb->DEVCON, USB_DEVCON_FSDEV) == (USB_DEVCON_FSDEV)); +} + +/** + * @brief Is USB DEVCON LSDEV Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : True + * @arg 0x0 : False + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_low_speed_detected(USB_TypeDef *usb) +{ + return (READ_BIT(usb->DEVCON, USB_DEVCON_LSDEV) == (USB_DEVCON_LSDEV)); +} + +/** + * @brief Is USB DEVCON HOST MODE Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : True + * @arg 0x0 : False + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_host_mode(USB_TypeDef *usb) +{ + return (READ_BIT(usb->DEVCON, USB_DEVCON_HOST) == (USB_DEVCON_HOST)); +} + +/** + * @brief Is USB DEVCON DEVICE MODE Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : True + * @arg 0x0 : False + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_device_mode(USB_TypeDef *usb) +{ + return (READ_BIT(usb->DEVCON, USB_DEVCON_HOST) != (USB_DEVCON_HOST)); +} + +/** + * @brief Enable USB DEVCON HOSTREQ + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_host_request(USB_TypeDef *usb) +{ + SET_BIT(usb->DEVCON, USB_DEVCON_HOSTREQ); +} + +/** + * @brief Disable USB DEVCON HOSTREQ + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_host_request(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->DEVCON, USB_DEVCON_HOSTREQ); +} + +/** + * @brief Is USB DEVCON HOSTREQ Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_host_request(USB_TypeDef *usb) +{ + return (READ_BIT(usb->DEVCON, USB_DEVCON_HOSTREQ) == (USB_DEVCON_HOSTREQ)); +} + +/** + * @brief Enable USB DEVCON SESSION + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_session(USB_TypeDef *usb) +{ + SET_BIT(usb->DEVCON, USB_DEVCON_SESSION); +} + +/** + * @brief Disable USB DEVCON SESSION + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_session(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->DEVCON, USB_DEVCON_SESSION); +} + +/** + * @brief Is USB DEVCON SESSION Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_session(USB_TypeDef *usb) +{ + return (READ_BIT(usb->DEVCON, USB_DEVCON_SESSION) == (USB_DEVCON_SESSION)); +} + +/** + * @brief Set USB TXMAXP MAXSIZE + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_tx_max_packet_size(USB_TypeDef *usb, uint8_t Maxsize) +{ + MODIFY_REG(usb->TXMAXP, USB_TXMAXP_MAXSIZE, Maxsize); +} + +/** + * @brief Get USB TXMAXP MAXSIZE + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_tx_max_packet_size(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->TXMAXP, USB_TXMAXP_MAXSIZE)); +} + +/** + * @brief Set USB CSR0L_TXCSRL + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_csr0l_txcsrl(USB_TypeDef *usb, uint8_t txcsrl) +{ + WRITE_REG(usb->CSR0L_TXCSRL, txcsrl); +} + +/** + * @brief Get USB CSR0L_TXCSRL + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_csr0l_txcsrl(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->CSR0L_TXCSRL)); +} + +/** + * @brief Clear USB CSR0L NAKTO + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_ep0_nak_timeout(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_NAKTO); +} + +/** + * @brief Is USB CSR0L NAKTO Active + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_ep0_nak_timeout(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_NAKTO) == (USB_CSR0L_NAKTO)); +} + +/** + * @brief Enable USB CSR0L STATUSPKT + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_ep0_send_status_packet(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_STATUSPKT); +} + +/** + * @brief Disable USB CSR0L STATUSPKT + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_ep0_send_status_packet(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_STATUSPKT); +} + +/** + * @brief Is USB CSR0L STATUSPKT Enabled + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_ep0_send_status_packet(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_STATUSPKT) == (USB_CSR0L_STATUSPKT)); +} + +/** + * @brief Enable USB CSR0L REQPKT + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_ep0_request_packet(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_REQPKT); +} + +/** + * @brief Disable USB CSR0L REQPKT + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_ep0_request_packet(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_REQPKT); +} + +/** + * @brief Is USB CSR0L REQPKT Enabled + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_ep0_request_packet(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_REQPKT) == (USB_CSR0L_REQPKT)); +} + +/** + * @brief Clear USB CSR0L ERROR + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_ep0_error(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_ERROR); +} + +/** + * @brief Is USB CSR0L ERROR Active + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Error + * @arg 0x0 : No error + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_ep0_error(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_ERROR) == (USB_CSR0L_ERROR)); +} + +/** + * @brief Enable USB CSR0L SETUPPKT + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_ep0_send_setup_packet(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_SETUPPKT); +} + +/** + * @brief Disable USB CSR0L SETUPPKT + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_ep0_send_setup_packet(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_SETUPPKT); +} + +/** + * @brief Is USB CSR0L SETUPPKT Enabled + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_ep0_send_setup_packet(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_SETUPPKT) == (USB_CSR0L_SETUPPKT)); +} + +/** + * @brief Clear USB CSR0L STALLED + * @note CSR0L_TXCSRL in Endpoint 0 Host/Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_ep0_stalled(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_STALLED); +} + +/** + * @brief Is USB CSR0L STALLED Active + * @note CSR0L_TXCSRL in Endpoint 0 Host/Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_ep0_stalled(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_STALLED) == (USB_CSR0L_STALLED)); +} + +/** + * @brief Enable USB CSR0L TXRDY + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_ep0_tx_ready(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_TXRDY); +} + +/** + * @brief Is USB CSR0L TXRDY Enabled + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_ep0_tx_ready(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_TXRDY) == (USB_CSR0L_TXRDY)); +} + +/** + * @brief Clear USB CSR0L RXRDY + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_host_ep0_rx_ready(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_RXRDY); +} + +/** + * @brief Is USB CSR0L RXRDY Active + * @note CSR0L_TXCSRL in Endpoint 0 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_host_ep0_rx_ready(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_RXRDY) == (USB_CSR0L_RXRDY)); +} + +/** + * @brief Clear USB CSR0L SETENDC + * @note CSR0L_TXCSRL in Endpoint 0 Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_ep0_setup_end(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_SETENDC); +} + +/** + * @brief Clear USB CSR0L RXRDYC + * @note CSR0L_TXCSRL in Endpoint 0 Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_device_ep0_rx_ready(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_RXRDYC); +} + +/** + * @brief Set USB CSR0L SEND STALL + * @note CSR0L_TXCSRL in Endpoint 0 Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_set_ep0_send_stall(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_STALL); +} + +/** + * @brief Is USB CSR0L SETEND Active + * @note CSR0L_TXCSRL in Endpoint 0 Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_ep0_setup_end(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_SETEND) == (USB_CSR0L_SETEND)); +} + +/** + * @brief Set CSR0L DATAEND + * @note CSR0L_TXCSRL in Endpoint 0 Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_set_ep0_data_end(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_DATAEND); +} + +/** + * @brief Is USB CSR0L RXRDY Active + * @note CSR0L_TXCSRL in Endpoint 0 Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_device_ep0_rx_ready(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_CSR0L_RXRDY) == (USB_CSR0L_RXRDY)); +} + +/** + * @brief Clear USB TXCSRL NAKTO + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_tx_nak_timeout(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_NAKTO); +} + +/** + * @brief Is USB TXCSRL NAKTO Active + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : NAK Timeout + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_tx_nak_timeout(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_NAKTO) == (USB_TXCSRL_NAKTO)); +} + +/** + * @brief Trigger USB TXCSRL CLRDT + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_trigger_epx_tx_clear_data_toggle(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_CLRDT); +} + +/** + * @brief Clear USB TXCSRL STALLED + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_tx_stalled(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_STALLED); +} + +/** + * @brief Is USB TXCSRL STALLED Active + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_tx_stalled(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_STALLED) == (USB_TXCSRL_STALLED)); +} + +/** + * @brief Trigger USB TXCSRL FLUSH + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_trigger_epx_tx_flush_fifo(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_FLUSH); +} + +/** + * @brief Clear USB TXCSRL ERROR + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_tx_error(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_ERROR); +} + +/** + * @brief Is USB TXCSRL ERROR Active + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_tx_error(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_ERROR) == (USB_TXCSRL_ERROR)); +} + +/** + * @brief Clear USB TXCSRL FIFONE + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_tx_fifo_not_empty(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_FIFONE); +} + +/** + * @brief Is USB TXCSRL FIFONE Active + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_tx_fifo_not_empty(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_FIFONE) == (USB_TXCSRL_FIFONE)); +} + +/** + * @brief Enable USB TXCSRL TXRDY + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_epx_tx_ready(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_TXRDY); +} + +/** + * @brief Is USB TXCSRL TXRDY Enabled + * @note CSR0L_TXCSRL in Endpoint 1~6 Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_epx_tx_ready(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_TXRDY) == (USB_TXCSRL_TXRDY)); +} + +/** + * @brief Enable USB TXCSRL STALL + * @note CSR0L_TXCSRL in Endpoint 1~6 Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_epx_tx_send_stall(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_STALL); +} + +/** + * @brief Disable USB CSR0L TXCSRL + * @note CSR0L_TXCSRL in Endpoint 1~6 Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_epx_tx_send_stall(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_STALL); +} + +/** + * @brief Is USB CSR0L TXCSRL Enabled + * @note CSR0L_TXCSRL in Endpoint 1~6 Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_epx_tx_send_stall(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_STALL) == (USB_TXCSRL_STALL)); +} + +/** + * @brief Clear USB TXCSRL UNDRUN + * @note CSR0L_TXCSRL in Endpoint 1~6 Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_tx_underrun(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_UNDRUN); +} + +/** + * @brief Is USB TXCSRL UNDRUN Active + * @note CSR0L_TXCSRL in Endpoint 1~6 Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_tx_underrun(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0L_TXCSRL, USB_TXCSRL_UNDRUN) == (USB_TXCSRL_UNDRUN)); +} + +/** + * @brief Set USB CSR0H_TXCSRH + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_csr0h_txcsrh(USB_TypeDef *usb, uint8_t txcsrh) +{ + WRITE_REG(usb->CSR0H_TXCSRH, txcsrh); +} + +/** + * @brief Get USB CSR0H_TXCSRH + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_csr0h_txcsrh(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->CSR0H_TXCSRH)); +} + +/** + * @brief Trigger USB CSR0H FLUSH + * @note CSR0H_TXCSRH in Endpoint 0 Host/Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_trigger_ep0_flush_fifo(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0H_TXCSRH, USB_CSR0H_FLUSH); +} + +/** + * @brief Enable USB TXCSRH AUTOSET + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_epx_autoset_tx_ready(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0H_TXCSRH, USB_TXCSRH_AUTOSET); +} + +/** + * @brief Disable USB TXCSRH AUTOSET + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_epx_autoset_tx_ready(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0H_TXCSRH, USB_TXCSRH_AUTOSET); +} + +/** + * @brief Is USB TXCSRH AUTOSET Enabled + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_epx_autoset_tx_ready(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0H_TXCSRH, USB_TXCSRH_AUTOSET) == (USB_TXCSRH_AUTOSET)); +} + +/** + * @brief Enable USB TXCSRH ISO + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_epx_tx_isochronous(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0H_TXCSRH, USB_TXCSRH_ISO); +} + +/** + * @brief Disbale USB TXCSRH ISO + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_epx_tx_isochronous(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0H_TXCSRH, USB_TXCSRH_ISO); +} + +/** + * @brief Is USB TXCSRH ISO Enabled + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_epx_tx_isochronous(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0H_TXCSRH, USB_TXCSRH_ISO) == (USB_TXCSRH_ISO)); +} + +/** + * @brief Set USB TXCSRH MODE + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @param mode + @arg @ref MD_USB_TXCSRH_MODE_RX + @arg @ref MD_USB_TXCSRH_MODE_TX + * @retval None + */ +__STATIC_INLINE void md_usb_set_epx_mode(USB_TypeDef *usb, uint8_t mode) +{ + MODIFY_REG(usb->CSR0H_TXCSRH, USB_TXCSRH_MODE, mode << USB_TXCSRH_MODE_POS); +} + +/** + * @brief Get USB TXCSRH MODE + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + @arg @ref MD_USB_TXCSRH_MODE_RX + @arg @ref MD_USB_TXCSRH_MODE_TX + */ +__STATIC_INLINE uint8_t md_usb_get_epx_mode(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->CSR0H_TXCSRH, USB_TXCSRH_MODE) >> USB_TXCSRH_MODE_POS); +} + +/** + * @brief Enable USB TXCSRH FDT + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_epx_tx_force_data_toggle(USB_TypeDef *usb) +{ + SET_BIT(usb->CSR0H_TXCSRH, USB_TXCSRH_FDT); +} + +/** + * @brief Disable USB TXCSRH FDT + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_epx_tx_force_data_toggle(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->CSR0H_TXCSRH, USB_TXCSRH_FDT); +} + +/** + * @brief Is USB TXCSRH FDT Enabled + * @note CSR0H_TXCSRH in Endpoint 1~6 Host/Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_epx_tx_force_data_toggle(USB_TypeDef *usb) +{ + return (READ_BIT(usb->CSR0H_TXCSRH, USB_TXCSRH_FDT) == (USB_TXCSRH_FDT)); +} + +/** + * @brief Set USB RXMAXP + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_rx_max_packet_size(USB_TypeDef *usb, uint8_t rxmaxp) +{ + WRITE_REG(usb->RXMAXP, rxmaxp); +} + +/** + * @brief Get USB RXMAXP + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_rx_max_packet_size(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->RXMAXP)); +} + +/** + * @brief Set USB RXCSRL + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_rxcsrl(USB_TypeDef *usb, uint8_t rxcsrl) +{ + WRITE_REG(usb->RXCSRL, rxcsrl); +} + +/** + * @brief Get USB RXCSRL + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_rxcsrl(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->RXCSRL)); +} + +/** + * @brief Trigger USB RXCSRL CLRDT + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_trigger_epx_rx_clear_data_toggle(USB_TypeDef *usb) +{ + SET_BIT(usb->RXCSRL, USB_RXCSRL_CLRDT); +} + +/** + * @brief Clear USB RXCSRL STALLED + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_rx_stalled(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRL, USB_RXCSRL_STALLED); +} + +/** + * @brief Is USB RXCSRL STALLED Active + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_rx_stalled(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRL, USB_RXCSRL_STALLED) == (USB_RXCSRL_STALLED)); +} + +/** + * @brief Enable USB RXCSRL REQPKT + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_epx_rx_request_packet(USB_TypeDef *usb) +{ + SET_BIT(usb->RXCSRL, USB_RXCSRL_REQPKT); +} + +/** + * @brief Disable USB RXCSRL REQPKT + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_epx_rx_request_packet(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRL, USB_RXCSRL_REQPKT); +} + +/** + * @brief Is USB RXCSRL REQPKT Enabled + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_epx_rx_request_packet(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRL, USB_RXCSRL_REQPKT) == (USB_RXCSRL_REQPKT)); +} + +/** + * @brief Trigger USB RXCSRL FLUSH + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_trigger_epx_rx_flush_fifo(USB_TypeDef *usb) +{ + SET_BIT(usb->RXCSRL, USB_RXCSRL_FLUSH); +} + +/** + * @brief Clear USB RXCSRL DATAERR + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_rx_data_error(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRL, USB_RXCSRL_DATAERR); +} + +/** + * @brief Is USB RXCSRL DATAERR Active + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_rx_data_error(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRL, USB_RXCSRL_DATAERR) == (USB_RXCSRL_DATAERR)); +} + +/** + * @brief Clear USB RXCSRL NAKTO + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_rx_nak_timeout(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRL, USB_RXCSRL_NAKTO); +} + +/** + * @brief Is USB RXCSRL NAKTO Active + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_rx_nak_timeout(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRL, USB_RXCSRL_NAKTO) == (USB_RXCSRL_NAKTO)); +} + +/** + * @brief Clear USB RXCSRL ERROR + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_rx_error(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRL, USB_RXCSRL_ERROR); +} + +/** + * @brief Is USB RXCSRL ERROR Active + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_rx_error(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRL, USB_RXCSRL_ERROR) == (USB_RXCSRL_ERROR)); +} + +/** + * @brief Is USB RXCSRL FULL Active + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_rx_fifo_full(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRL, USB_RXCSRL_FULL) == (USB_RXCSRL_FULL)); +} + +/** + * @brief Clear USB RXCSRL RXRDY + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_rx_ready(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRL, USB_RXCSRL_RXRDY); +} + +/** + * @brief Is USB RXCSRL RXRDY Active + * @note RXCSRL in Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_rx_ready(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRL, USB_RXCSRL_RXRDY) == (USB_RXCSRL_RXRDY)); +} + +/** + * @brief Enable USB RXCSRL STALL + * @note RXCSRL in Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_epx_rx_send_stall(USB_TypeDef *usb) +{ + SET_BIT(usb->RXCSRL, USB_RXCSRL_STALL); +} + +/** + * @brief Disable USB RXCSRL STALL + * @note RXCSRL in Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_epx_rx_send_stall(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRL, USB_RXCSRL_STALL); +} + +/** + * @brief Is USB RXCSRL STALL Enabled + * @note RXCSRL in Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_epx_rx_send_stall(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRL, USB_RXCSRL_STALL) == (USB_RXCSRL_STALL)); +} + +/** + * @brief Clear USB RXCSRL OVERRUN + * @note RXCSRL in Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_flag_epx_rx_overrun(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRL, USB_RXCSRL_OVERRUN); +} + +/** + * @brief Is USB RXCSRL OVERRUN Active + * @note RXCSRL in Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_flag_epx_rx_overrun(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRL, USB_RXCSRL_OVERRUN) == (USB_RXCSRL_OVERRUN)); +} + +/** + * @brief Set USB RXCSRH + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_rxcsrh(USB_TypeDef *usb, uint8_t rxcsrh) +{ + WRITE_REG(usb->RXCSRH, rxcsrh); +} + +/** + * @brief Get USB RXCSRH + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_rxcsrh(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->RXCSRH)); +} + +/** + * @brief Enable USB RXCSRH AUTOCLR + * @note RXCSRH in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_epx_auto_clear_rx_ready(USB_TypeDef *usb) +{ + SET_BIT(usb->RXCSRH, USB_RXCSRH_AUTOCLR); +} + +/** + * @brief Disable USB RXCSRH AUTOCLR + * @note RXCSRH in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_epx_auto_clear_rx_ready(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRH, USB_RXCSRH_AUTOCLR); +} + +/** + * @brief Is USB RXCSRH AUTOCLR Enabled + * @note RXCSRH in Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_epx_auto_clear_rx_ready(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRH, USB_RXCSRH_AUTOCLR) == (USB_RXCSRH_AUTOCLR)); +} + +/** + * @brief Enable USB RXCSRH AUTOREQ + * @note RXCSRH in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_epx_rx_auto_request(USB_TypeDef *usb) +{ + SET_BIT(usb->RXCSRH, USB_RXCSRH_AUTOREQ); +} + +/** + * @brief Disable USB RXCSRH AUTOREQ + * @note RXCSRH in Host Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_epx_rx_auto_request(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRH, USB_RXCSRH_AUTOREQ); +} + +/** + * @brief Is USB RXCSRH AUTOREQ Enabled + * @note RXCSRH in Host Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_epx_rx_auto_request(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRH, USB_RXCSRH_AUTOREQ) == (USB_RXCSRH_AUTOREQ)); +} + +/** + * @brief Enable USB RXCSRH ISO + * @note RXCSRH in Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_epx_rx_isochronous(USB_TypeDef *usb) +{ + SET_BIT(usb->RXCSRH, USB_RXCSRH_ISO); +} + +/** + * @brief Disable USB RXCSRH ISO + * @note RXCSRH in Device Mode + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_epx_rx_isochronous(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXCSRH, USB_RXCSRH_ISO); +} + +/** + * @brief Is USB RXCSRH ISO Enabled + * @note RXCSRH in Device Mode + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_epx_rx_isochronous(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXCSRH, USB_RXCSRH_ISO) == (USB_RXCSRH_ISO)); +} + +/** + * @brief Get USB COUNT0_RX1 COUNT + * @note COUNT0_RX1 in Endpoint 0 Host/Device Mode (Enapoint 0) + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ep0_data_count(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->COUNT0_RX1, USB_COUNT0_COUNT)); +} + +/** + * @brief Get USB COUNT0_RX1 PKT COUNT + * @note COUNT0_RX1 in Host/Device Mode (Enapoint 1~6) + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7FF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint16_t md_usb_get_epx_packet_count(USB_TypeDef *usb) +{ + return (uint16_t)((READ_BIT(usb->RXCOUNT2, USB_RXCOUNT2_PKTHIGH) << 8) | (READ_BIT(usb->COUNT0_RX1, USB_RX1_PKTLOW))); +} + +/** + * @brief Set USB TXTYPE PROTOCOL + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg @ref MD_USB_TXTYPE_PROTOCOL_CONTROL (0x00) : Control + * @arg @ref MD_USB_TXTYPE_PROTOCOL_ISOCHRONOUS (0x01) : Isochronous + * @arg @ref MD_USB_TXTYPE_PROTOCOL_BULK (0x02) : Bulk + * @arg @ref MD_USB_TXTYPE_PROTOCOL_INTERRUPT (0x03) : Interrupt + * @retval None + */ +__STATIC_INLINE void md_usb_set_tx_protocol(USB_TypeDef *usb, uint8_t Protocol) +{ + MODIFY_REG(usb->TXTYPE, USB_TXTYPE_PROTOCOL, Protocol << USB_TXTYPE_PROTOCOL_POSS); +} + +/** + * @brief Get USB TXTYPE PROTOCOL + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_USB_TXTYPE_PROTOCOL_CONTROL (0x00) : Control + * @arg @ref MD_USB_TXTYPE_PROTOCOL_ISOCHRONOUS (0x01) : Isochronous + * @arg @ref MD_USB_TXTYPE_PROTOCOL_BULK (0x02) : Bulk + * @arg @ref MD_USB_TXTYPE_PROTOCOL_INTERRUPT (0x03) : Interrupt + */ +__STATIC_INLINE uint8_t md_usb_get_tx_protocol(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->TXTYPE, USB_TXTYPE_PROTOCOL) >> USB_TXTYPE_PROTOCOL_POSS); +} + +/** + * @brief Set USB TXTYPE TEPN + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xf + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_tx_target_endpoint(USB_TypeDef *usb, uint8_t TEPn) +{ + MODIFY_REG(usb->TXTYPE, USB_TXTYPE_TEPN, TEPn); +} + +/** + * @brief Get USB TXTYPE TEPN + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xf + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_tx_target_endpoint(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->TXTYPE, USB_TXTYPE_TEPN)); +} + +/** + * @brief Set USB EP0 NAK LIMIT + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_ep0_nak_limit(USB_TypeDef *usb, uint8_t NAKLmt) +{ + MODIFY_REG(usb->NAKLIMIT0_TXINTERVAL, USB_NAKLIMIT0_NAKLMT, NAKLmt); +} + +/** + * @brief Get USB EP0 NAK LIMIT + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ep0_nak_limit(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->NAKLIMIT0_TXINTERVAL, USB_NAKLIMIT0_NAKLMT)); +} + +/** + * @brief Set USB EP1-6 NAK LIMIT + * @note NAK LIMIT in Control/BULK Transfer Type + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_epx_tx_nak_limit(USB_TypeDef *usb, uint8_t NAKLmt) +{ + MODIFY_REG(usb->NAKLIMIT0_TXINTERVAL, USB_TXINTERVAL_NAKLMT, NAKLmt); +} + +/** + * @brief Get USB EP1-6 NAK LIMIT + * @note NAK LIMIT in Control/Bulk Transfer Type + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_epx_tx_nak_limit(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->NAKLIMIT0_TXINTERVAL, USB_TXINTERVAL_NAKLMT)); +} + +/** + * @brief Set USB EP1-6 TX polling + * @note TX polling in Interrupt/Isochronous Transfer Type + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x1 + * @retval None + */ +__STATIC_INLINE void md_usb_set_epx_tx_polling_interval(USB_TypeDef *usb, uint8_t TxPoll) +{ + MODIFY_REG(usb->NAKLIMIT0_TXINTERVAL, USB_TXINTERVAL_TXPOLL, TxPoll); +} + +/** + * @brief Get USB EP1-6 TX polling + * @note TX polling in Interrupt/Isochronous Transfer Type + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x1 + */ +__STATIC_INLINE uint8_t md_usb_get_epx_tx_polling_interval(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->NAKLIMIT0_TXINTERVAL, USB_TXINTERVAL_TXPOLL)); +} + +/** + * @brief Set USB RXTYPE PROTOCOL + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg @ref MD_USB_RXTYPE_PROTOCOL_CONTROL (0x00) : Control + * @arg @ref MD_USB_RXTYPE_PROTOCOL_ISOCHRONOUS (0x01) : Isochronous + * @arg @ref MD_USB_RXTYPE_PROTOCOL_BULK (0x02) : Bulk + * @arg @ref MD_USB_RXTYPE_PROTOCOL_INTERRUPT (0x03) : Interrupt + * @retval None + */ +__STATIC_INLINE void md_usb_set_rx_protocol(USB_TypeDef *usb, uint8_t Protocol) +{ + MODIFY_REG(usb->RXTYPE, USB_RXTYPE_PROTOCOL, Protocol << USB_RXTYPE_PROTOCOL_POSS); +} + +/** + * @brief Get USB RXTYPE PROTOCOL + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_USB_RXTYPE_PROTOCOL_CONTROL (0x00) : Control + * @arg @ref MD_USB_RXTYPE_PROTOCOL_ISOCHRONOUS (0x01) : Isochronous + * @arg @ref MD_USB_RXTYPE_PROTOCOL_BULK (0x02) : Bulk + * @arg @ref MD_USB_RXTYPE_PROTOCOL_INTERRUPT (0x03) : Interrupt + */ +__STATIC_INLINE uint8_t md_usb_get_rx_protocol(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->RXTYPE, USB_RXTYPE_PROTOCOL) >> USB_RXTYPE_PROTOCOL_POSS); +} + +/** + * @brief Set USB RXTYPE TEPN + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xf + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_rx_target_endpoint(USB_TypeDef *usb, uint8_t TEPn) +{ + MODIFY_REG(usb->RXTYPE, USB_RXTYPE_TEPN, TEPn); +} + +/** + * @brief Get USB RXTYPE TEPN + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xf + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_rx_target_endpoint(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->RXTYPE, USB_RXTYPE_TEPN)); +} + +/** + * @brief Set USB RXINTERVAL NAKLMT + * @note RXINTERVAL in Bulk Transfer Type + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_rx_nak_limit(USB_TypeDef *usb, uint8_t NAKLmt) +{ + MODIFY_REG(usb->RXINTERVAL, USB_RXINTERVAL_NAKLMT, NAKLmt); +} + +/** + * @brief Get USB RXINTERVAL NAKLMT + * @note RXINTERVAL in Bulk Transfer Type + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_epx_rx_nak_limit(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->RXINTERVAL, USB_RXINTERVAL_NAKLMT)); +} + +/** + * @brief Set USB RXINTERVAL RXPOLL + * @note RXINTERVAL in Interrupt/Isochronous Transfer Type + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x1 + * @retval None + */ +__STATIC_INLINE void md_usb_set_rx_polling_interval(USB_TypeDef *usb, uint8_t RxPoll) +{ + MODIFY_REG(usb->RXINTERVAL, USB_RXINTERVAL_RXPOLL, RxPoll); +} + +/** + * @brief Get USB RXINTERVAL RXPOLL + * @note RXINTERVAL in Interrupt/Isochronous Transfer Type + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x1 + */ +__STATIC_INLINE uint8_t md_usb_get_epx_rx_polling_interval(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->RXINTERVAL, USB_RXINTERVAL_RXPOLL)); +} + +/** + * @brief Set USB TXFIFO1 START ADDRESS + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xfff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_tx_fifo_start_addr(USB_TypeDef *usb, uint16_t Addr) +{ + MODIFY_REG(usb->TXFIFO2, USB_TXFIFO2_ADDRH, (uint8_t)(Addr >> 8)); + MODIFY_REG(usb->TXFIFO1, USB_TXFIFO1_ADDRL, (uint8_t)(Addr & 0xff)); +} + +/** + * @brief Get USB TXFIFO1 START ADDRESS + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xfff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint16_t md_usb_get_tx_fifo_start_addr(USB_TypeDef *usb) +{ + return (uint16_t)((READ_BIT(usb->TXFIFO2, USB_TXFIFO2_ADDRH) << 8) | (READ_BIT(usb->TXFIFO1, USB_TXFIFO1_ADDRL))); +} + +/** + * @brief Set USB TXFIFO2 MAXPKTSIZE + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_8 (0x00) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_16 (0x01) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_32 (0x02) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_64 (0x03) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_128 (0x04) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_256 (0x05) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_512 (0x06) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_1024 (0x07) + * @retval None + */ +__STATIC_INLINE void md_usb_set_tx_max_fifo_packet_size(USB_TypeDef *usb, uint8_t MaxPktSize) +{ + MODIFY_REG(usb->TXFIFO2, USB_TXFIFO2_MAXPKTSIZE, MaxPktSize << USB_TXFIFO2_MAXPKTSIZE_POSS); +} + +/** + * @brief Get USB TXFIFO2 MAXPKTSIZE + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_8 (0x00) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_16 (0x01) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_32 (0x02) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_64 (0x03) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_128 (0x04) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_256 (0x05) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_512 (0x06) + * @arg @ref MD_USB_TXFIFO2_MAXPKTSIZE_1024 (0x07) + */ +__STATIC_INLINE uint8_t md_usb_get_tx_max_fifo_packet_size(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->TXFIFO2, USB_TXFIFO2_MAXPKTSIZE) >> USB_TXFIFO2_MAXPKTSIZE_POSS); +} + +/** + * @brief Enable USB TXFIFO2 DPB + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_tx_double_packet(USB_TypeDef *usb) +{ + SET_BIT(usb->TXFIFO2, USB_TXFIFO2_DPB); +} + +/** + * @brief Disable USB TXFIFO2 DPB + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_tx_double_packet(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->TXFIFO2, USB_TXFIFO2_DPB); +} + +/** + * @brief Is USB TXFIFO2 DPB Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_tx_double_packet(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXFIFO2, USB_TXFIFO2_DPB) == (USB_TXFIFO2_DPB)); +} + +/** + * @brief Set USB RXFIFO1 START ADDRESS + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xfff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_rx_fifo_start_addr(USB_TypeDef *usb, uint16_t Addr) +{ + MODIFY_REG(usb->RXFIFO2, USB_RXFIFO2_ADDRH, (uint8_t)(Addr >> 8)); + MODIFY_REG(usb->RXFIFO1, USB_RXFIFO1_ADDRL, (uint8_t)(Addr & 0xff)); +} + +/** + * @brief Get USB RXFIFO1 START ADDRESS + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xfff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint16_t md_usb_get_rx_fifo_start_addr(USB_TypeDef *usb) +{ + return (uint16_t)((READ_BIT(usb->RXFIFO2, USB_RXFIFO2_ADDRH) << 8) | (READ_BIT(usb->RXFIFO1, USB_RXFIFO1_ADDRL))); +} + +/** + * @brief Set USB RXFIFO2 MAXPKTSIZE + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_8 (0x00) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_16 (0x01) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_32 (0x02) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_64 (0x03) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_128 (0x04) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_256 (0x05) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_512 (0x06) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_1024 (0x07) + * @retval None + */ +__STATIC_INLINE void md_usb_set_rx_max_fifo_packet_size(USB_TypeDef *usb, uint8_t MaxPktSize) +{ + MODIFY_REG(usb->RXFIFO2, USB_RXFIFO2_MAXPKTSIZE, MaxPktSize << USB_RXFIFO2_MAXPKTSIZE_POSS); +} + +/** + * @brief Get USB RXFIFO2 MAXPKTSIZE + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_8 (0x00) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_16 (0x01) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_32 (0x02) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_64 (0x03) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_128 (0x04) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_256 (0x05) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_512 (0x06) + * @arg @ref MD_USB_RXFIFO2_MAXPKTSIZE_1024 (0x07) + */ +__STATIC_INLINE uint8_t md_usb_get_rx_max_fifo_packet_size(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->RXFIFO2, USB_RXFIFO2_MAXPKTSIZE) >> USB_RXFIFO2_MAXPKTSIZE_POSS); +} + +/** + * @brief Enable USB RXFIFO2 DPB + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_rx_double_packet(USB_TypeDef *usb) +{ + SET_BIT(usb->RXFIFO2, USB_RXFIFO2_DPB); +} + +/** + * @brief Disable USB RXFIFO2 DPB + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disble_rx_double_packet(USB_TypeDef *usb) +{ + CLEAR_BIT(usb->RXFIFO2, USB_RXFIFO2_DPB); +} + +/** + * @brief Is USB RXFIFO2 DPB Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_rx_double_packet(USB_TypeDef *usb) +{ + return (uint8_t)(READ_BIT(usb->RXFIFO2, USB_RXFIFO2_DPB) == (USB_RXFIFO2_DPB)); +} + +/** + * @brief Set USB EP0FIFO + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_ep0_fifo(USB_TypeDef *usb, uint8_t ep0fifo) +{ + WRITE_REG(usb->EP0FIFO, ep0fifo); +} + +/** + * @brief Get USB EP0FIFO + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ep0_fifo(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->EP0FIFO)); +} + +/** + * @brief Set USB EP1FIFO + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_ep1_fifo(USB_TypeDef *usb, uint8_t ep1fifo) +{ + WRITE_REG(usb->EP1FIFO, ep1fifo); +} + +/** + * @brief Get USB EP1FIFO + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ep1_fifo(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->EP1FIFO)); +} + +/** + * @brief Set USB EP2FIFO + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_ep2_fifo(USB_TypeDef *usb, uint8_t ep2fifo) +{ + WRITE_REG(usb->EP2FIFO, ep2fifo); +} + +/** + * @brief Get USB EP2FIFO + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ep2_fifo(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->EP2FIFO)); +} + +/** + * @brief Set USB EP3FIFO + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_ep3_fifo(USB_TypeDef *usb, uint8_t ep3fifo) +{ + WRITE_REG(usb->EP3FIFO, ep3fifo); +} + +/** + * @brief Get USB EP3FIFO + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ep3_fifo(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->EP3FIFO)); +} + +/** + * @brief Set USB EP4FIFO + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_ep4_fifo(USB_TypeDef *usb, uint8_t ep4fifo) +{ + WRITE_REG(usb->EP4FIFO, ep4fifo); +} + +/** + * @brief Get USB EP4FIFO + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ep4_fifo(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->EP4FIFO)); +} + +/** + * @brief Set USB EP5FIFO + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_ep5_fifo(USB_TypeDef *usb, uint8_t ep5fifo) +{ + WRITE_REG(usb->EP5FIFO, ep5fifo); +} + +/** + * @brief Get USB EP5FIFO + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ep5_fifo(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->EP5FIFO)); +} + +/** + * @brief Set USB EP6FIFO + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_ep6_fifo(USB_TypeDef *usb, uint8_t ep6fifo) +{ + WRITE_REG(usb->EP6FIFO, ep6fifo); +} + +/** + * @brief Get USB EP6FIFO + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ep6_fifo(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->EP6FIFO)); +} + +/** + * @brief Set USB TXIER + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x7f + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_txier(USB_TypeDef *usb, uint8_t txier) +{ + WRITE_REG(usb->TXIER, txier); +} + +/** + * @brief Enable USB TXIER EP6IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep6_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIER, USB_TXIER_EP6IE); +} + +/** + * @brief Enable USB TXIER EP5IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep5_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIER, USB_TXIER_EP5IE); +} + +/** + * @brief Enable USB TXIER EP4IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep4_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIER, USB_TXIER_EP4IE); +} + +/** + * @brief Enable USB TXIER EP3IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep3_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIER, USB_TXIER_EP3IE); +} + +/** + * @brief Enable USB TXIER EP2IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep2_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIER, USB_TXIER_EP2IE); +} + +/** + * @brief Enable USB TXIER EP1IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep1_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIER, USB_TXIER_EP1IE); +} + +/** + * @brief Enable USB TXIER EP0IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep0(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIER, USB_TXIER_EP0IE); +} + +/** + * @brief Set USB RXIER + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_rxier(USB_TypeDef *usb, uint8_t rxier) +{ + WRITE_REG(usb->RXIER, rxier); +} + +/** + * @brief Enable USB RXIER EP6IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep6_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIER, USB_RXIER_EP6IE); +} + +/** + * @brief Enable USB RXIER EP5IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep5_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIER, USB_RXIER_EP5IE); +} + +/** + * @brief Enable USB RXIER EP4IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep4_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIER, USB_RXIER_EP4IE); +} + +/** + * @brief Enable USB RXIER EP3IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep3_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIER, USB_RXIER_EP3IE); +} + +/** + * @brief Enable USB RXIER EP2IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep2_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIER, USB_RXIER_EP2IE); +} + +/** + * @brief Enable USB RXIER EP1IE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_ep1_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIER, USB_RXIER_EP1IE); +} + +/** + * @brief Set USB TXIDR + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x7f + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_txidr(USB_TypeDef *usb, uint8_t txidr) +{ + WRITE_REG(usb->TXIDR, txidr); +} + +/** + * @brief Enable USB TXIDR EP6ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep6_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIDR, USB_TXIDR_EP6ID); +} + +/** + * @brief Enable USB TXIDR EP5ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep5_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIDR, USB_TXIDR_EP5ID); +} + +/** + * @brief Enable USB TXIDR EP4ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep4_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIDR, USB_TXIDR_EP4ID); +} + +/** + * @brief Enable USB TXIDR EP3ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep3_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIDR, USB_TXIDR_EP3ID); +} + +/** + * @brief Enable USB TXIDR EP2ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep2_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIDR, USB_TXIDR_EP2ID); +} + +/** + * @brief Enable USB TXIDR EP1ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep1_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIDR, USB_TXIDR_EP1ID); +} + +/** + * @brief Enable USB TXIDR EP0ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep0(USB_TypeDef *usb) +{ + SET_BIT(usb->TXIDR, USB_TXIDR_EP0ID); +} + +/** + * @brief Set USB RXIDR + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_rxidr(USB_TypeDef *usb, uint8_t rxidr) +{ + WRITE_REG(usb->RXIDR, rxidr); +} + +/** + * @brief Enable USB RXIDR EP6ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep6_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIDR, USB_RXIDR_EP6ID); +} + +/** + * @brief Enable USB RXIDR EP5ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep5_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIDR, USB_RXIDR_EP5ID); +} + +/** + * @brief Enable USB RXIDR EP4ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep4_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIDR, USB_RXIDR_EP4ID); +} + +/** + * @brief Enable USB RXIDR EP3ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep3_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIDR, USB_RXIDR_EP3ID); +} + +/** + * @brief Enable USB RXIDR EP2ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep2_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIDR, USB_RXIDR_EP2ID); +} + +/** + * @brief Enable USB RXIDR EP1ID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_ep1_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXIDR, USB_RXIDR_EP1ID); +} + +/** + * @brief Get USB TXIVS + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7f + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_txivs(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->TXIVS)); +} + +/** + * @brief Is USB TXIVS EP6IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep6_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIVS, USB_TXIVS_EP6IVS) == (USB_TXIVS_EP6IVS)); +} + +/** + * @brief Is USB TXIVS EP5IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep5_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIVS, USB_TXIVS_EP5IVS) == (USB_TXIVS_EP5IVS)); +} + +/** + * @brief Is USB TXIVS EP4IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep4_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIVS, USB_TXIVS_EP4IVS) == (USB_TXIVS_EP4IVS)); +} + +/** + * @brief Is USB TXIVS EP3IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep3_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIVS, USB_TXIVS_EP3IVS) == (USB_TXIVS_EP3IVS)); +} + +/** + * @brief Is USB TXIVS EP2IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep2_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIVS, USB_TXIVS_EP2IVS) == (USB_TXIVS_EP2IVS)); +} + +/** + * @brief Is USB TXIVS EP1IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep1_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIVS, USB_TXIVS_EP1IVS) == (USB_TXIVS_EP1IVS)); +} + +/** + * @brief Is USB TXIVS EP0IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep0(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIVS, USB_TXIVS_EP0IVS) == (USB_TXIVS_EP0IVS)); +} + +/** + * @brief Get USB RXIVS + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_rxivs(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->RXIVS)); +} + +/** + * @brief Is USB RXIVS EP6IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep6_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIVS, USB_RXIVS_EP6IVS) == (USB_RXIVS_EP6IVS)); +} + +/** + * @brief Is USB RXIVS EP5IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep5_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIVS, USB_RXIVS_EP5IVS) == (USB_RXIVS_EP5IVS)); +} + +/** + * @brief Is USB RXIVS EP4IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep4_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIVS, USB_RXIVS_EP4IVS) == (USB_RXIVS_EP4IVS)); +} + +/** + * @brief Is USB RXIVS EP3IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep3_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIVS, USB_RXIVS_EP3IVS) == (USB_RXIVS_EP3IVS)); +} + +/** + * @brief Is USB RXIVS EP2IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep2_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIVS, USB_RXIVS_EP2IVS) == (USB_RXIVS_EP2IVS)); +} + +/** + * @brief Is USB RXIVS EP1IVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_ep1_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIVS, USB_RXIVS_EP1IVS) == (USB_RXIVS_EP1IVS)); +} + +/** + * @brief Get USB TXRIF + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7f + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_txrif(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->TXRIF)); +} + +/** + * @brief Is USB TXRIF EP6RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep6_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXRIF, USB_TXRIF_EP6RIF) == (USB_TXRIF_EP6RIF)); +} + +/** + * @brief Is USB TXRIF EP5RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep5_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXRIF, USB_TXRIF_EP5RIF) == (USB_TXRIF_EP5RIF)); +} + +/** + * @brief Is USB TXRIF EP4RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep4_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXRIF, USB_TXRIF_EP4RIF) == (USB_TXRIF_EP4RIF)); +} + +/** + * @brief Is USB TXRIF EP3RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep3_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXRIF, USB_TXRIF_EP3RIF) == (USB_TXRIF_EP3RIF)); +} + +/** + * @brief Is USB TXRIF EP2RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep2_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXRIF, USB_TXRIF_EP2RIF) == (USB_TXRIF_EP2RIF)); +} + +/** + * @brief Is USB TXRIF EP1RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep1_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXRIF, USB_TXRIF_EP1RIF) == (USB_TXRIF_EP1RIF)); +} + +/** + * @brief Is USB TXRIF EP0RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep0(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXRIF, USB_TXRIF_EP0RIF) == (USB_TXRIF_EP0RIF)); +} + +/** + * @brief Get USB RXRIF + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_rxrif(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->RXRIF)); +} + +/** + * @brief Is USB RXRIF EP6RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep6_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXRIF, USB_RXRIF_EP6RIF) == (USB_RXRIF_EP6RIF)); +} + +/** + * @brief Is USB RXRIF EP5RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep5_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXRIF, USB_RXRIF_EP5RIF) == (USB_RXRIF_EP5RIF)); +} + +/** + * @brief Is USB RXRIF EP4RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep4_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXRIF, USB_RXRIF_EP4RIF) == (USB_RXRIF_EP4RIF)); +} + +/** + * @brief Is USB RXRIF EP3RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep3_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXRIF, USB_RXRIF_EP3RIF) == (USB_RXRIF_EP3RIF)); +} + +/** + * @brief Is USB RXRIF EP2RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep2_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXRIF, USB_RXRIF_EP2RIF) == (USB_RXRIF_EP2RIF)); +} + +/** + * @brief Is USB RXRIF EP1RIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_ep1_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXRIF, USB_RXRIF_EP1RIF) == (USB_RXRIF_EP1RIF)); +} + +/** + * @brief Get USB TXIFM + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7f + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_txifm(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->TXIFM)); +} + +/** + * @brief Is USB TXIFM EP6IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep6_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIFM, USB_TXIFM_EP6IFM) == (USB_TXIFM_EP6IFM)); +} + +/** + * @brief Is USB TXIFM EP5IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep5_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIFM, USB_TXIFM_EP5IFM) == (USB_TXIFM_EP5IFM)); +} + +/** + * @brief Is USB TXIFM EP4IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep4_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIFM, USB_TXIFM_EP4IFM) == (USB_TXIFM_EP4IFM)); +} + +/** + * @brief Is USB TXIFM EP3IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep3_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIFM, USB_TXIFM_EP3IFM) == (USB_TXIFM_EP3IFM)); +} + +/** + * @brief Is USB TXIFM EP2IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep2_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIFM, USB_TXIFM_EP2IFM) == (USB_TXIFM_EP2IFM)); +} + +/** + * @brief Is USB TXIFM EP1IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep1_tx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIFM, USB_TXIFM_EP1IFM) == (USB_TXIFM_EP1IFM)); +} + +/** + * @brief Is USB TXIFM EP0IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep0(USB_TypeDef *usb) +{ + return (READ_BIT(usb->TXIFM, USB_TXIFM_EP0IFM) == (USB_TXIFM_EP0IFM)); +} + +/** + * @brief Get USB RXIFM + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_rxifm(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->RXIFM)); +} + +/** + * @brief Is USB RXRIF EP6IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep6_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIFM, USB_RXIFM_EP6IFM) == (USB_RXIFM_EP6IFM)); +} + +/** + * @brief Is USB RXRIF EP5IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep5_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIFM, USB_RXIFM_EP5IFM) == (USB_RXIFM_EP5IFM)); +} + +/** + * @brief Is USB RXRIF EP4IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep4_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIFM, USB_RXIFM_EP4IFM) == (USB_RXIFM_EP4IFM)); +} + +/** + * @brief Is USB RXRIF EP3IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep3_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIFM, USB_RXIFM_EP3IFM) == (USB_RXIFM_EP3IFM)); +} + +/** + * @brief Is USB RXRIF EP2IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep2_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIFM, USB_RXIFM_EP2IFM) == (USB_RXIFM_EP2IFM)); +} + +/** + * @brief Is USB RXRIF EP1IFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_ep1_rx(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RXIFM, USB_RXIFM_EP1IFM) == (USB_RXIFM_EP1IFM)); +} + +/** + * @brief Set USB TXICR + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x7f + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_txicr(USB_TypeDef *usb, uint8_t txicr) +{ + WRITE_REG(usb->TXICR, txicr); +} + +/** + * @brief Enable USB TXICR EP6ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep6_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXICR, USB_TXICR_EP6ICR); +} + +/** + * @brief Enable USB TXICR EP5ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep5_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXICR, USB_TXICR_EP5ICR); +} + +/** + * @brief Enable USB TXICR EP4ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep4_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXICR, USB_TXICR_EP4ICR); +} + +/** + * @brief Enable USB TXICR EP3ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep3_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXICR, USB_TXICR_EP3ICR); +} + +/** + * @brief Enable USB TXICR EP2ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep2_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXICR, USB_TXICR_EP6ICR); +} + +/** + * @brief Enable USB TXICR EP1ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep1_tx(USB_TypeDef *usb) +{ + SET_BIT(usb->TXICR, USB_TXICR_EP1ICR); +} + +/** + * @brief Enable USB TXICR EP0ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep0(USB_TypeDef *usb) +{ + SET_BIT(usb->TXICR, USB_TXICR_EP0ICR); +} + +/** + * @brief Set USB RXICR + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_rxicr(USB_TypeDef *usb, uint8_t U8) +{ + WRITE_REG(usb->RXICR, U8); +} + +/** + * @brief Enable USB RXICR EP6ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep6_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXICR, USB_RXICR_EP6ICR); +} + +/** + * @brief Enable USB RXICR EP5ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep5_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXICR, USB_RXICR_EP5ICR); +} + +/** + * @brief Enable USB RXICR EP4ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep4_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXICR, USB_RXICR_EP4ICR); +} + +/** + * @brief Enable USB RXICR EP3ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep3_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXICR, USB_RXICR_EP3ICR); +} + +/** + * @brief Enable USB RXICR EP2ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep2_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXICR, USB_RXICR_EP2ICR); +} + +/** + * @brief Enable USB RXICR EP1ICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_ep1_rx(USB_TypeDef *usb) +{ + SET_BIT(usb->RXICR, USB_RXICR_EP1ICR); +} + +/** + * @brief Set USB IER + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_ier(USB_TypeDef *usb, uint8_t ier) +{ + WRITE_REG(usb->IER, ier); +} + +/** + * @brief Enable USB IER SESREQIE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_session_request(USB_TypeDef *usb) +{ + SET_BIT(usb->IER, USB_IER_SESREQIE); +} + +/** + * @brief Enable USB IER DISCONIE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_disconnect(USB_TypeDef *usb) +{ + SET_BIT(usb->IER, USB_IER_DISCONIE); +} + +/** + * @brief Enable USB IER CONIE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_connection(USB_TypeDef *usb) +{ + SET_BIT(usb->IER, USB_IER_CONIE); +} + +/** + * @brief Enable USB IER SOFIE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_sof(USB_TypeDef *usb) +{ + SET_BIT(usb->IER, USB_IER_SOFIE); +} + +/** + * @brief Enable USB IER BABIE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_babble(USB_TypeDef *usb) +{ + SET_BIT(usb->IER, USB_IER_BABIE); +} + +/** + * @brief Enable USB IER RESIE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_resume(USB_TypeDef *usb) +{ + SET_BIT(usb->IER, USB_IER_RESIE); +} + +/** + * @brief Enable USB IER RESTIE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_reset(USB_TypeDef *usb) +{ + SET_BIT(usb->IER, USB_IER_RESTIE); +} + +/** + * @brief Enable USB IER SUSPDIE + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_enable_it_suspend(USB_TypeDef *usb) +{ + SET_BIT(usb->IER, USB_IER_SUSPDIE); +} + +/** + * @brief Set USB IDR + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_idr(USB_TypeDef *usb, uint8_t idr) +{ + WRITE_REG(usb->IDR, idr); +} + +/** + * @brief Enable USB IDR SESREQID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_session_request(USB_TypeDef *usb) +{ + SET_BIT(usb->IDR, USB_IDR_SESREQID); +} + +/** + * @brief Enable USB IDR DISCONID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_disconnect(USB_TypeDef *usb) +{ + SET_BIT(usb->IDR, USB_IDR_DISCONID); +} + +/** + * @brief Enable USB IDR CONID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_connection(USB_TypeDef *usb) +{ + SET_BIT(usb->IDR, USB_IDR_CONID); +} + +/** + * @brief Enable USB IDR SOFID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_sof(USB_TypeDef *usb) +{ + SET_BIT(usb->IDR, USB_IDR_SOFID); +} + +/** + * @brief Enable USB IDR BABID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_babble(USB_TypeDef *usb) +{ + SET_BIT(usb->IDR, USB_IDR_BABID); +} + +/** + * @brief Enable USB IDR RESID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_resume(USB_TypeDef *usb) +{ + SET_BIT(usb->IDR, USB_IDR_RESID); +} + +/** + * @brief Enable USB IDR RESTID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_reset(USB_TypeDef *usb) +{ + SET_BIT(usb->IDR, USB_IDR_RESTID); +} + +/** + * @brief Enable USB IDR SUSPDID + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_disable_it_suspend(USB_TypeDef *usb) +{ + SET_BIT(usb->IDR, USB_IDR_SUSPDID); +} + +/** + * @brief Get USB IVS + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ivs(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->IVS)); +} + +/** + * @brief Is USB IVS SESREQIVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_session_request(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IVS, USB_IVS_SESREQIVS) == (USB_IVS_SESREQIVS)); +} + +/** + * @brief Is USB IVS DISCONIVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_disconnect(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IVS, USB_IVS_DISCONIVS) == (USB_IVS_DISCONIVS)); +} + +/** + * @brief Is USB IVS CONIVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_connection(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IVS, USB_IVS_CONIVS) == (USB_IVS_CONIVS)); +} + +/** + * @brief Is USB IVS SOFIVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_sof(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IVS, USB_IVS_SOFIVS) == (USB_IVS_SOFIVS)); +} + +/** + * @brief Is USB IVS BABIVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_babble(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IVS, USB_IVS_BABIVS) == (USB_IVS_BABIVS)); +} + +/** + * @brief Is USB IVS RESIVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_resume(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IVS, USB_IVS_RESIVS) == (USB_IVS_RESIVS)); +} + +/** + * @brief Is USB IVS RESTIVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_reset(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IVS, USB_IVS_RESTIVS) == (USB_IVS_RESTIVS)); +} + +/** + * @brief Is USB IVS SUSPDIVS Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_enabled_it_suspend(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IVS, USB_IVS_SUSPDIVS) == (USB_IVS_SUSPDIVS)); +} + +/** + * @brief Get USB RIF + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_rif(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->RIF)); +} + +/** + * @brief Is USB RIF SESREQRIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_session_request(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RIF, USB_RIF_SESREQRIF) == (USB_RIF_SESREQRIF)); +} + +/** + * @brief Is USB RIF DISCONRIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_disconnect(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RIF, USB_RIF_DISCONRIF) == (USB_RIF_DISCONRIF)); +} + +/** + * @brief Is USB RIF CONRIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_connection(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RIF, USB_RIF_CONRIF) == (USB_RIF_CONRIF)); +} + +/** + * @brief Is USB RIF SOFRIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_sof(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RIF, USB_RIF_SOFRIF) == (USB_RIF_SOFRIF)); +} + +/** + * @brief Is USB RIF BABRIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_babble(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RIF, USB_RIF_BABRIF) == (USB_RIF_BABRIF)); +} + +/** + * @brief Is USB RIF RESRIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_resume(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RIF, USB_RIF_RESRIF) == (USB_RIF_RESRIF)); +} + +/** + * @brief Is USB RIF RESTRIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_reset(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RIF, USB_RIF_RESTRIF) == (USB_RIF_RESTRIF)); +} + +/** + * @brief Is USB RIF SUSPDRIF Active + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Active + * @arg 0x0 : Not active + */ +__STATIC_INLINE uint8_t md_usb_is_active_it_suspend(USB_TypeDef *usb) +{ + return (READ_BIT(usb->RIF, USB_RIF_SUSPDRIF) == (USB_RIF_SUSPDRIF)); +} + +/** + * @brief Get USB IFM + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_usb_get_ifm(USB_TypeDef *usb) +{ + return (uint8_t)(READ_REG(usb->IFM)); +} + +/** + * @brief Is USB IFM SESREQIFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_session_request(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IFM, USB_IFM_SESREQIFM) == (USB_IFM_SESREQIFM)); +} + +/** + * @brief Is USB IFM DISCONIFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_disconnect(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IFM, USB_IFM_DISCONIFM) == (USB_IFM_DISCONIFM)); +} + +/** + * @brief Is USB IFM CONIFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_connection(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IFM, USB_IFM_CONIFM) == (USB_IFM_CONIFM)); +} + +/** + * @brief Is USB IFM SOFIFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_sof(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IFM, USB_IFM_SOFIFM) == (USB_IFM_SOFIFM)); +} + +/** + * @brief Is USB IFM BABIFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_babble(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IFM, USB_IFM_BABIFM) == (USB_IFM_BABIFM)); +} + +/** + * @brief Is USB IFM RESIFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_resume(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IFM, USB_IFM_RESIFM) == (USB_IFM_RESIFM)); +} + +/** + * @brief Is USB IFM RESTIFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_reset(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IFM, USB_IFM_RESTIFM) == (USB_IFM_RESTIFM)); +} + +/** + * @brief Is USB IFM SUSPDIFM Enabled + * @param usb USB Instance + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_usb_is_masked_it_suspend(USB_TypeDef *usb) +{ + return (READ_BIT(usb->IFM, USB_IFM_SUSPDIFM) == (USB_IFM_SUSPDIFM)); +} + +/** + * @brief Set USB ICR + * @param usb USB Instance + * @param The param can be one of the following values: + * @arg Max Value 0x7e + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_usb_set_icr(USB_TypeDef *usb, uint8_t icr) +{ + WRITE_REG(usb->ICR, icr); +} + +/** + * @brief Enable USB ICR SESREQICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_session_request(USB_TypeDef *usb) +{ + SET_BIT(usb->ICR, USB_ICR_SESREQICR); +} + +/** + * @brief Enable USB ICR DISCONICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_disconnect(USB_TypeDef *usb) +{ + SET_BIT(usb->ICR, USB_ICR_DISCONICR); +} + +/** + * @brief Enable USB ICR CONICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_connection(USB_TypeDef *usb) +{ + SET_BIT(usb->ICR, USB_ICR_CONICR); +} + +/** + * @brief Enable USB ICR SOFICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_sof(USB_TypeDef *usb) +{ + SET_BIT(usb->ICR, USB_ICR_SOFICR); +} + +/** + * @brief Enable USB ICR BABICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_babble(USB_TypeDef *usb) +{ + SET_BIT(usb->ICR, USB_ICR_BABICR); +} + +/** + * @brief Enable USB ICR RESICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_resume(USB_TypeDef *usb) +{ + SET_BIT(usb->ICR, USB_ICR_RESICR); +} + +/** + * @brief Enable USB ICR RESTICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_reset(USB_TypeDef *usb) +{ + SET_BIT(usb->ICR, USB_ICR_RESTICR); +} + +/** + * @brief Enable USB ICR SUSPDICR + * @param usb USB Instance + * @retval None + */ +__STATIC_INLINE void md_usb_clear_it_suspend(USB_TypeDef *usb) +{ + SET_BIT(usb->ICR, USB_ICR_SUSPDICR); +} + +/** + * @} MD_USB_Macro_Drivers + */ + +/** + * @} MD_USB_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_USB_Public_Functions USB Public Functions + * @{ + */ + +/** + * @} MD_USB_Public_Functions + */ + +#endif + +/** + * @} USB + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ + + diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_utils.c b/os/common/ext/CMSIS/ES32/FS026/md/md_utils.c new file mode 100644 index 00000000000..7ce370bfd62 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_utils.c @@ -0,0 +1,207 @@ +/********************************************************************************** + * + * @file md_utils.c + * @brief UTILS module driver. + * + * @date 30 Apri 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Apri 2021 yanght the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include +#include "md_utils.h" +#include "md_rcu.h" +#include "md_tick.h" + +/** @defgroup Micro_Driver EASTSOFT Micro Driver + * @{ + */ + +/** @defgroup MD_UTILS Utils + * @brief Utils module driver + * @{ + */ +/** @defgroup MD_UTILS_Private_Variables Private Variables + * @{ + */ +static __IO uint32_t __md_tick = 0; +/** + * @} + */ + +/** @defgroup MD_UTILS_Public_Functions UTILS Public Functions + * @{ + */ +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @retval None + */ +void md_init_1ms_tick(void) +{ + /* Configure the SysTick IRQ */ + md_tick_waitms(1, 1); + NVIC_SetPriority(SysTick_IRQn, 3); + return; +} + +/** + * @brief This function invoked by Systick ISR. + * @note This function is declared as __weak to be overwritten in case of + * other implementations in user file. + * @retval None + */ +__WEAK void md_systick_irq_cbk(void) +{ + /* do nothing */ + return; +} + +/** + * @brief This function invoked by Systick ISR each 1ms. + * @retval None + */ +__isr__ void md_inc_tick(void) +{ + ++__md_tick; + md_systick_irq_cbk(); + return; +} + +/** + * @brief Provides a tick value in millisecond. + * @retval tick value + */ +uint32_t md_get_tick(void) +{ + return __md_tick; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @param delay: specifies the delay time length, in milliseconds. + * @retval None + */ +void md_delay_1ms(__IO uint32_t delay) +{ + uint32_t tick; + + tick = md_get_tick(); + delay = delay == 0 ? 1 : delay; + + while ((md_get_tick() - tick) < delay) + ; +} +/** + * @brief This function provides accurate delay (in microsecond) based + * on variable incremented. + * @param delay: specifies the delay time length, in microsecond. + * @retval None + */ +void md_delay_1us(__IO uint32_t delay) +{ + unsigned int start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemFrequency_SysClk / 1000000UL; + + do + { + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while (delta < (us_tick * delay)); +} +/** + * @brief Configure interrupt. + * @param irq: Interrunpt type. + * @param prio: preempt priority(0-3). + * @param status: Status. + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void md_mcu_irq_config(IRQn_Type irq, uint8_t prio, TypeFunc status) +{ + if (status == ENABLE) + { + NVIC_SetPriority(irq, prio); + NVIC_EnableIRQ(irq); + } + else + { + NVIC_DisableIRQ(irq); + } + + return; +} + +/** + * @brief Get the CPU ID. + * @retval CPU ID. + */ +uint32_t md_mcu_get_cpu_id(void) +{ + return SCB->CPUID; +} + +/** + * @brief Get the UID. + * @param buf: Pointer to UID, len: 12Bytes(96-bits) + * @retval None + */ +void md_mcu_get_uid(uint8_t *buf) +{ + memcpy(&buf[0], (void *)MD_MCU_UID0_ADDR, 4); + memcpy(&buf[4], (void *)MD_MCU_UID1_ADDR, 4); + memcpy(&buf[8], (void *)MD_MCU_UID2_ADDR, 4); + + return; +} + +/** + * @brief Get the CHIPID + * @retval CHPID + */ +uint32_t md_mcu_get_chipid(void) +{ + return (uint32_t) * (uint32_t *)MD_MCU_CHIPID_ADDR; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_utils.h b/os/common/ext/CMSIS/ES32/FS026/md/md_utils.h new file mode 100644 index 00000000000..95de312a28f --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_utils.h @@ -0,0 +1,108 @@ +/********************************************************************************** + * + * @file md_utils.h + * @brief Header file of UTILS module driver. + * + * @date 30 Apri 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Apri 2021 yanght the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + + +#ifndef __MD_UTILS_H__ +#define __MD_UTILS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------ */ +#include +//#include "md_conf.h" +#include "type.h" +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_UTILS + * @{ + */ + +/** @defgroup MD_UTILS_Public_Types UTILS Public Types + * @{ + */ +/** + * @brief MD Status structures definition + */ +typedef enum +{ + MD_OK = 0x0U, /**< Status: OK */ + MD_ERROR = 0x1U, /**< Status: ERROR */ + MD_BUSY = 0x2U, /**< Status: BUSY */ + MD_TIMEOUT = 0x3U, /**< Status: TIMEOUT */ +} md_status_t; +/** + * @} + */ +/** @defgroup MD_Private_Macros Public Macros + * @{ + */ +#define MD_MCU_UID0_ADDR 0x000109E0U +#define MD_MCU_UID1_ADDR 0x000109E8U +#define MD_MCU_UID2_ADDR 0x000109F0U +#define MD_MCU_CHIPID_ADDR 0x00010BF8U +/** + * @} + */ +/** @addtogroup MD_UTILS_Public_Functions + * @{ + */ +void md_init_1ms_tick(void); +void md_inc_tick(void); +__WEAK void md_systick_irq_cbk(void); +uint32_t md_get_tick(void); +void md_delay_1ms(__IO uint32_t delay); +void md_delay_1us(__IO uint32_t delay); +void md_mcu_irq_config(IRQn_Type irq, uint8_t prio, TypeFunc status); +uint32_t md_mcu_get_cpu_id(void); +void md_mcu_get_uid(uint8_t *buf); +uint32_t md_mcu_get_chipid(void); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.c b/os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.c new file mode 100644 index 00000000000..c6eaf41b000 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.c @@ -0,0 +1,94 @@ +/********************************************************************************** + * + * @file md_wwdt.c + * @brief md_wwdt C file + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_wwdt.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (WWDT) + +/** @defgroup WWDT WWDT + * @brief WWDT micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_WWDT_Public_Functions WWDT Public Functions + * @{ + */ +/** + * @brief WWDT Initialization + * @param WWDT Init Structure + * @retval None + */ +void md_wwdt_init(WWDT_TypeDef *WWD, md_wwdt_inittypedef *WWDT_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_MD_WWDT_ALL_INSTANCE(WWDT)); + assert_param(IS_MD_WWDT_PRESCALER(WWDT_InitStruct->Prescaler)); + assert_param(IS_MD_WWDT_WINDOW(WWDT_InitStruct->Window)); + assert_param(IS_MD_WWDT_COUNTER(WWDT_InitStruct->Counter)); + assert_param(IS_MD_WWDT_EWI_MODE(WWDT_InitStruct->EWIMode)); + + if (WWDT_InitStruct->EWIMode == WWDT_EWI_ENABLE) + md_wwdt_enable_it_ewi(WWD); + else + md_wwdt_disable_it_ewi(WWD); + + md_wwdt_set_count_value(WWD, WWDT_InitStruct->Counter); + md_wwdt_set_prescaler(WWD, WWDT_InitStruct->Prescaler); + md_wwdt_set_window(WWD, WWDT_InitStruct->Window); + md_wwdt_enable(WWD); +} + +/** + * @} WWDT_PUB_FUNC WWDT Public Functions + */ + +/** + * @} GPIO + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.h b/os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.h new file mode 100644 index 00000000000..7bfabf386fd --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.h @@ -0,0 +1,500 @@ +/********************************************************************************** + * + * @file md_wwdt.h + * @brief header file of md_wwdt.c + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * 24 Mar 2022 AE Team Modify MD Driver + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_WWDT_H__ +#define __MD_WWDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "fs026.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_WWDT WWDT + * @brief WWDT micro driver + * @{ + */ + +/** @defgroup MD_WWDT_Pubulic_Types WWDT Pubulic Types + * @{ + */ + +/** + * @brief WWDT Init Structure. + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDT. + This parameter can be a value of @ref WWDT_Prescaler */ + + uint32_t Window; /*!< Specifies the WWDT window value to be compared to the downcounter. + This parameter must be a number a minimum, 0x40 and a maximum, 0x7F */ + + uint32_t Counter; /*!< Specifies the WWDT free-running downcounter value. + This parameter must be a number between a minimum, 0x40 and a maximum, 0x7F */ + + uint32_t EWIMode ; /*!< Specifies if WWDT Early Wakeup Interupt is enable or not. + This parameter can be a value of @ref WWDT_EWI_Mode */ + +} md_wwdt_inittypedef; +/** + * @} + */ + +/** @defgroup MD_WWDT_Public_Macros WWDT Public Macros + * @{ + */ + +/** + * @brief MD_WWDT_Prescaler WWDT Prescaler + */ +#define WWDT_PRESCALER_1 0x00000000U /*!< WWDT counter clock = (PCLK1/4096)/1 */ +#define WWDT_PRESCALER_2 0x00000001U /*!< WWDT counter clock = (PCLK1/4096)/2, WWDT_CFG_WDGTB_POSS = 7 */ +#define WWDT_PRESCALER_4 0x00000002U /*!< WWDT counter clock = (PCLK1/4096)/4, WWDT_CFG_WDGTB_POSS = 7 */ +#define WWDT_PRESCALER_8 0x00000003U /*!< WWDT counter clock = (PCLK1/4096)/8, WWDT_CFG_WDGTB = 3<<7 */ + +/** + * @brief WWDT_EWI_Mode WWDT Early Wakeup Interrupt Mode + */ +#define WWDT_EWI_DISABLE 0x00000000U /*!< EWI Disable */ +#define WWDT_EWI_ENABLE 0x00000001U /*!< EWI Enable, WWDT_CON_WDGA = 1<<7 */ + +/** + * @} + */ + +/** @defgroup MD_WWDT_Public_Functions WWDT Public Functions + * @{ + */ + +/** @defgroup MD_WWDT_Public_Functions_Group2 CON + * @{ + */ +/** + * @brief Set the WWDT_CON value + * @note A write of 0 in bit 7 has no effect. + * @param wwdt WWDT Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_con(WWDT_TypeDef *wwdt, uint32_t Reg_Value) +{ + WRITE_REG(wwdt->CON, Reg_Value); +} + +/** + * @brief Get the WWDT_CON value + * @note None. + * @param wwdt WWDT Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_wwdt_get_con(WWDT_TypeDef *wwdt) +{ + return (uint32_t)(READ_REG(wwdt->CON)); +} + +/** + * @brief WWDT WDGA Enable + * @note This bit is set by software and only cleared by hardware after a reset. + * A write of 0 has no effect. When WDGA=1, the watchdog can generate a reset. + * @param wwdt WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_enable(WWDT_TypeDef *wwdt) +{ + SET_BIT(wwdt->CON, WWDT_CON_WDGA); +} + +/** + * @brief Indicate if WWDT WDGA is enabled + * @note This bit is set by software and only cleared by hardware after a reset. + * A write of 0 has no effect. When WDGA=1, the watchdog can generate a reset. + * @param wwdt WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_enabled(WWDT_TypeDef *wwdt) +{ + return (READ_BIT(wwdt->CON, WWDT_CON_WDGA) == (WWDT_CON_WDGA)); +} + +/** + * @brief Set WWDT T 7-bit counter + * @note These bits contain the value of the watchdog counter. + * It is decremented every (4096 x 2^WDGTB[1:0]) PCLK cycles. + * A reset is produced when it is decremented from 0x40 to 0x3F(T6 becomes cleared), + * and when it is renewed on the condition the value is more than the window value and the WDGA bit is enabled. + * @param wwdt WWDT Instance + * @param counter is a 7-bit number + * @arg Max Value 0x7F + * @arg Min Value 0x40 + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_count_value(WWDT_TypeDef *wwdt, uint32_t counter) +{ + MODIFY_REG(wwdt->CON, WWDT_CON_T, counter); +} + +/** + * @brief Get WWDT T 7-bit counter + * @note These bits contain the value of the watchdog counter. + * It is decremented every (4096 x 2^WDGTB[1:0]) PCLK cycles. + * A reset is produced when it is decremented from 0x40 to 0x3F(T6 becomes cleared), + * and when it is renewed on the condition the value is more than the window value and the WDGA bit is enabled. + * @param wwdt WWDT Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x7F + * @arg Min Value 0x40 + */ +__STATIC_INLINE uint32_t md_wwdt_get_count_value(WWDT_TypeDef *wwdt) +{ + return (uint32_t)(READ_BIT(wwdt->CON, WWDT_CON_T) >> WWDT_CON_T_POSS); +} +/** + * @} + */ + +/** @defgroup MD_WWDT_Public_Functions_Group3 CFG + * @{ + */ +/** + * @brief Set the WWDT_CFG value + * @note None. + * @param wwdt WWDT Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_cfg(WWDT_TypeDef *wwdt, uint32_t Reg_Value) +{ + WRITE_REG(wwdt->CFG, Reg_Value); +} + +/** + * @brief Get the WWDT_CFG value + * @note None. + * @param wwdt WWDT Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_wwdt_get_cfg(WWDT_TypeDef *wwdt) +{ + return (uint32_t)(READ_REG(wwdt->CFG)); +} + +/** + * @brief Set WWDT WDGTB 2-bit prescaler value + * @note The time base of the prescaler can be modified as follows: + * 00: CK Counter Clock (PCLK div 4096) div 1 + * 01: CK Counter Clock (PCLK div 4096) div 2 + * 10: CK Counter Clock (PCLK div 4096) div 4 + * 11: CK Counter Clock (PCLK div 4096) div 8 + * @param wwdt WWDT Instance + * @param prescaler is a 2-bit number + * @arg @ref WWDT_PRESCALER_1 + * @arg @ref WWDT_PRESCALER_2 + * @arg @ref WWDT_PRESCALER_4 + * @arg @ref WWDT_PRESCALER_8 + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_prescaler(WWDT_TypeDef *wwdt, uint32_t prescaler) +{ + MODIFY_REG(wwdt->CFG, WWDT_CFG_WDGTB, prescaler << WWDT_CFG_WDGTB_POSS); +} + +/** + * @brief Get WWDT WDGTB 2-bit prescaler value + * @note The time base of the prescaler can be modified as follows: + 00: CK Counter Clock (PCLK div 4096) div 1 + 01: CK Counter Clock (PCLK div 4096) div 2 + 10: CK Counter Clock (PCLK div 4096) div 4 + 11: CK Counter Clock (PCLK div 4096) div 8 + * @param wwdt WWDT Instance + * @retval The retval can be one of the following values: + * @arg @ref WWDT_PRESCALER_1 + * @arg @ref WWDT_PRESCALER_2 + * @arg @ref WWDT_PRESCALER_4 + * @arg @ref WWDT_PRESCALER_8 + */ +__STATIC_INLINE uint32_t md_wwdt_get_prescaler(WWDT_TypeDef *wwdt) +{ + return (uint32_t)(READ_BIT(wwdt->CFG, WWDT_CFG_WDGTB) >> WWDT_CFG_WDGTB_POSS); +} + +/** + * @brief Set WWDT W 7-bit window + * @note These bits contain the window value to be compared to the downcounter. + * @param wwdt WWDT Instance + * @param window is a 7-bit number + * @arg Max Value 0x7F + * @arg Min Value 0x40 + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_window(WWDT_TypeDef *wwdt, uint32_t window) +{ + MODIFY_REG(wwdt->CFG, WWDT_CFG_W, window); +} + +/** + * @brief Get WWDT W 7-bit window + * @note These bits contain the window value to be compared to the downcounter. + * @param wwdt WWDT Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x7F + * @arg Min Value 0x40 + */ +__STATIC_INLINE uint32_t md_wwdt_get_window(WWDT_TypeDef *wwdt) +{ + return (uint32_t)(READ_BIT(wwdt->CFG, WWDT_CFG_W) >> WWDT_CFG_W_POSS); +} +/** + * @} + */ + +/** @defgroup MD_WWDT_Public_Functions_Group4 IER + * @{ + */ +/** + * @brief Set WWDT IER Register + * @param wwdt WWDT Instance + * @param ier + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_ier(WWDT_TypeDef *wwdt, uint32_t ier) +{ + WRITE_REG(wwdt->IER, ier); +} + +/** + * @brief WWDT Early wakeup interrupt Enable + * @note A write of 1 in IER to enable this interrupt. + * @param wwdt WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_enable_it_ewi(WWDT_TypeDef *wwdt) +{ + SET_BIT(wwdt->IER, WWDT_IER_EWI); +} +/** + * @} + */ + +/** @defgroup MD_WWDT_Public_Functions_Group5 IDR + * @{ + */ +/** + * @brief Set WWDT IDR Register + * @param wwdt WWDT Instance + * @param idr + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_idr(WWDT_TypeDef *wwdt, uint32_t idr) +{ + WRITE_REG(wwdt->IDR, idr); +} + +/** + * @brief WWDT Early wakeup interrupt Disable + * @note A write of 1 in IDR to disable this interrupt. + * @param wwdt WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_disable_it_ewi(WWDT_TypeDef *wwdt) +{ + SET_BIT(wwdt->IDR, WWDT_IDR_EWI); +} +/** + * @} + */ + +/** @defgroup MD_WWDT_Public_Functions_Group6 IVS + * @{ + */ +/** + * @brief Get WWDT IVS Register + * @param wwdt WWDT Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_wwdt_get_ivs(WWDT_TypeDef *wwdt) +{ + return (uint32_t)(READ_REG(wwdt->IVS)); +} + +/** + * @brief Indicate if WWDT EWI is enabled + * @note To check EWI enable or not. + * @param wwdt WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_enabled_it_ewi(WWDT_TypeDef *wwdt) +{ + return (READ_BIT(wwdt->IVS, WWDT_IVS_EWI) == (WWDT_IVS_EWI)); +} +/** + * @} + */ + +/** @defgroup MD_WWDT_Public_Functions_Group7 RIF + * @{ + */ +/** + * @brief Get WWDT RIF Register + * @param wwdt WWDT Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_wwdt_get_rif(WWDT_TypeDef *wwdt) +{ + return (uint32_t)(READ_REG(wwdt->RIF)); +} + +/** + * @brief Get the early wakeup interrupt flag status + * @note This bit is set by hardware when the counter has reached the value 0x40. + It can be cleared by software by writing 1 in WWDT_ICR. This bit is + also set if the interrupt is not enabled. + * @param wwdt WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_active_it_ewi(WWDT_TypeDef *wwdt) +{ + return (READ_BIT(wwdt->RIF, WWDT_RIF_EWI) == (WWDT_RIF_EWI)); +} +/** + * @} + */ + +/** @defgroup MD_WWDT_Public_Functions_Group8 IFM + * @{ + */ +/** + * @brief Get WWDT IFM Register + * @param wwdt WWDT Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_wwdt_get_ifm(WWDT_TypeDef *wwdt) +{ + return (uint32_t)(READ_REG(wwdt->IFM)); +} + +/** + * @brief Get the early wakeup interrupt flag masked status + * @note This bit is set by hardware when the counter has reached the value 0x40 + and the interrupt is enabled. + * @param wwdt WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_masked_it_ewi(WWDT_TypeDef *wwdt) +{ + return (READ_BIT(wwdt->IFM, WWDT_IFM_EWI) == (WWDT_IFM_EWI)); +} +/** + * @} + */ + +/** @defgroup MD_WWDT_Public_Functions_Group9 ICR + * @{ + */ +/** + * @brief Set WWDT ICR Register + * @param wwdt WWDT Instance + * @param icr + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_icr(WWDT_TypeDef *wwdt, uint32_t icr) +{ + WRITE_REG(wwdt->ICR, icr); +} + +/** + * @brief Clear the early wakeup interrupt flag + * @param wwdt WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_clear_it_ewi(WWDT_TypeDef *wwdt) +{ + SET_BIT(wwdt->ICR, WWDT_ICR_EWI); +} +/** + * @} + */ + +/** @defgroup MD_WWDT_Public_Functions_Group1 Initialization + * @{ + */ +void md_wwdt_init(WWDT_TypeDef *wwdt, md_wwdt_inittypedef *WWDT_InitStruct); +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MD_WWDT_Private_Macros WWDT Private Macros + * @{ + */ +#define IS_MD_WWDT_ALL_INSTANCE(__INSTANCE__) (__INSTANCE__ == WWDT) + +#define IS_MD_WWDT_PRESCALER(__VALUE__) (((__VALUE__) == WWDT_PRESCALER_1) \ + || ((__VALUE__) == WWDT_PRESCALER_2) \ + || ((__VALUE__) == WWDT_PRESCALER_4) \ + || ((__VALUE__) == WWDT_PRESCALER_8)) + +#define IS_MD_WWDT_WINDOW(__VALUE__) (((__VALUE__) >= 0x40) && ((__VALUE__) <= 0x7F)) + +#define IS_MD_WWDT_COUNTER(__VALUE__) (((__VALUE__) >= 0x40) && ((__VALUE__) <= 0x7F)) + +#define IS_MD_WWDT_EWI_MODE(__VALUE__) (((__VALUE__) == WWDT_EWI_ENABLE) \ + || ((__VALUE__) == WWDT_EWI_DISABLE)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/md/type.h b/os/common/ext/CMSIS/ES32/FS026/md/type.h new file mode 100644 index 00000000000..95db1bc1441 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/md/type.h @@ -0,0 +1,144 @@ +/********************************************************************************** + * + * @file type.h + * @brief define type + * + * @date 30 Apri 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Apri 2021 yanght the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __TYPE_H__ +#define __TYPE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------ */ +#include + + +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#define __INLINE__ __inline +#define __STATIC_INLINE__ static __inline +#else +#define __INLINE__ inline +#define __STATIC_INLINE__ static inline +#endif + +#define __isr__ + +//typedef enum +//{ +// RESET = 0x0U, +// SET = 0x1U, +//} flag_status_t, it_status_t; + +//typedef enum +//{ +// BIT_RESET = 0x0U, +// BIT_SET = 0x1U, +//} bit_status_t; + +//typedef enum +//{ +// DISABLE = 0x0U, +// ENABLE = 0x1U, +//} type_func_t, TypeFunc; +//#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) + +//typedef enum +//{ +// FALSE = 0x0U, +// TRUE = 0x1U, +//} type_bool_t; + +//typedef enum +//{ +// UNLOCK = 0x0U, +// LOCK = 0x1U, +//} lock_state_t; +//#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + + +//#define BIT(x) ((1U << (x))) +//#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e)))) +//#define SET_BIT(reg, bit) ((reg) |= (bit)) +//#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) +//#define READ_BIT(reg, bit) ((reg) & (bit)) +//#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) +//#define CLEAR_REG(reg) ((reg) = (0x0)) +//#define WRITE_REG(reg, val) ((reg) = (val)) +//#define READ_REG(reg) ((reg)) +//#define MODIFY_REG(reg, clearmask, setmask) WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) +//#define UNUSED(x) ((void)(x)) + +#ifdef USE_ASSERT +#define assert_param(x) \ + do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ + } while (0) +#else +#define assert_param(x) +#endif + + +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ + +__INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +__INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +#if (defined(__GNUC__) && !(defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TYPE_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/FS026/startup_fs026.s b/os/common/ext/CMSIS/ES32/FS026/startup_fs026.s new file mode 100644 index 00000000000..d079443baba --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/startup_fs026.s @@ -0,0 +1,260 @@ +;********************************************************************************* +; +; @file startup_es32f0283.s +; @brief ES32F0283 Device Startup File +; +; @date 24 Feb 2021 +; @author AE Team +; @note +; Change Logs: +; Date Author Notes +; 28 Mar 2023 AE Team the first version +; +; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;********************************************************************************* + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + ; External Interrupts + DCD Reset_Handler ;1, Reset Handler + DCD NMI_Handler ;2, NMI Handler + DCD HardFault_Handler ;3, HardFault Handler + DCD 0 ;4, Reserved + DCD 0 ;5, Reserved + DCD 0 ;6, Reserved + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, SVC Handler + DCD 0 ;12, Reserved + DCD 0 ;13, Reserved + DCD PendSV_Handler ;14, PENDSV Handler + DCD SysTick_Handler ;15, SysTick Handler + DCD WWDT_IRQHandler ;16, WWDT IRQHandler + DCD PVD_IRQHandler ;17, PVD IRQHandler + DCD RTC_IRQHandler ;18, RTC IRQHandler + DCD WAKEUP_IRQHandler ;19, WAKEUP IRQHandler + DCD RCU_CSU_IRQHandler ;20, RCU_CSU IRQHandler + DCD EXTI_0to1_IRQHandler ;21, EXTI_0to1 IRQHandler + DCD EXTI_2to3_IRQHandler ;22, EXTI_2to3 IRQHandler + DCD EXTI_4to15_IRQHandler ;23, EXTI_4to15 IRQHandler + DCD SPI3_IRQHandler ;24, SPI3 IRQHandler + DCD DMA1_CH0_IRQHandler ;25, DMA1_CH0 IRQHandler + DCD DMA1_CH12_IRQHandler ;26, DMA1_CH12 IRQHandler + DCD DMA1_CH345_IRQHandler ;27, DMA1_CH345 IRQHandler + DCD ADC_COMP_IRQHandler ;28, ADC_COMP IRQHandler + DCD AD16C4T1_IRQHandler ;29, AD16C4T1 IRQHandler + DCD BS16T1_IRQHandler ;30, BS16T1 IRQHandler + DCD GP32C4T1_IRQHandler ;31, GP32C4T1 IRQHandler + DCD GP16C4T1_IRQHandler ;32, GP16C4T1 IRQHandler + DCD GP16C4T2_IRQHandler ;33, GP16C4T2 IRQHandler + DCD GP16C4T3_IRQHandler ;34, GP16C4T3 IRQHandler + DCD GP16C2T1_IRQHandler ;35, GP16C2T1 IRQHandler + DCD GP16C2T2_IRQHandler ;36, GP16C2T2 IRQHandler + DCD GP16C2T3_IRQHandler ;37, GP16C2T3 IRQHandler + DCD GP16C2T4_IRQHandler ;38, GP16C2T4 IRQHandler + DCD I2C1_IRQHandler ;39, I2C1 IRQHandler + DCD I2C2_IRQHandler ;40, I2C2 IRQHandler + DCD SPI1_IRQHandler ;41, SPI1 IRQHandler + DCD SPI2_IRQHandler ;42, SPI2 IRQHandler + DCD UART1_IRQHandler ;43, UART1 IRQHandler + DCD UART2_IRQHandler ;44, UART2 IRQHandler + DCD UART3_AES_IRQHandler ;45, UART3_AES IRQHandler + DCD UART4_KBCU_IRQHandler ;46, UART4_KBCU IRQHandler + DCD USB_IRQHandler ;47, USB IRQHandler + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception IRQHandlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT WAKEUP_IRQHandler [WEAK] + EXPORT RCU_CSU_IRQHandler [WEAK] + EXPORT EXTI_0to1_IRQHandler [WEAK] + EXPORT EXTI_2to3_IRQHandler [WEAK] + EXPORT EXTI_4to15_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA1_CH0_IRQHandler [WEAK] + EXPORT DMA1_CH12_IRQHandler [WEAK] + EXPORT DMA1_CH345_IRQHandler [WEAK] + EXPORT ADC_COMP_IRQHandler [WEAK] + EXPORT AD16C4T1_IRQHandler [WEAK] + EXPORT BS16T1_IRQHandler [WEAK] + EXPORT GP32C4T1_IRQHandler [WEAK] + EXPORT GP16C4T1_IRQHandler [WEAK] + EXPORT GP16C4T2_IRQHandler [WEAK] + EXPORT GP16C4T3_IRQHandler [WEAK] + EXPORT GP16C2T1_IRQHandler [WEAK] + EXPORT GP16C2T2_IRQHandler [WEAK] + EXPORT GP16C2T3_IRQHandler [WEAK] + EXPORT GP16C2T4_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_AES_IRQHandler [WEAK] + EXPORT UART4_KBCU_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + + +WWDT_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +WAKEUP_IRQHandler +RCU_CSU_IRQHandler +EXTI_0to1_IRQHandler +EXTI_2to3_IRQHandler +EXTI_4to15_IRQHandler +SPI3_IRQHandler +DMA1_CH0_IRQHandler +DMA1_CH12_IRQHandler +DMA1_CH345_IRQHandler +ADC_COMP_IRQHandler +AD16C4T1_IRQHandler +BS16T1_IRQHandler +GP32C4T1_IRQHandler +GP16C4T1_IRQHandler +GP16C4T2_IRQHandler +GP16C4T3_IRQHandler +GP16C2T1_IRQHandler +GP16C2T2_IRQHandler +GP16C2T3_IRQHandler +GP16C2T4_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_AES_IRQHandler +UART4_KBCU_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + + diff --git a/os/common/ext/CMSIS/ES32/FS026/system_fs026.c b/os/common/ext/CMSIS/ES32/FS026/system_fs026.c new file mode 100644 index 00000000000..fa0e0c99f23 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/system_fs026.c @@ -0,0 +1,85 @@ +/********************************************************************************** + * + * @file system_es32f0283.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Incudes--------------------------------------------------------*/ +#include "system_fs026.h" + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup system_es32f0283 + * @{ + */ + +/* Public Functions -----------------------------------------------------------*/ +/* Public Init Structure ------------------------------------------------------*/ +/* Public Macros --------------------------------------------------------------*/ +/* Public Constants -----------------------------------------------------------*/ +/* Private Macros -------------------------------------------------------------*/ +/* Private Constants-----------------------------------------------------------*/ + +/* Private Variables ----------------------------------------------------------*/ +/** @addtogroup Private_Variables + * @{ + */ + +/** + * @} Private_Variables + */ + +/* Private Functions ----------------------------------------------------------*/ +/** @addtogroup Private_Functions + * @{ + */ + +/** + * @brief:SystemInit. + * @param:none + * @retval:none + */ +void SystemInit (void) +{ +} + +/** + * @} Private_Functions + */ + +/** + * @} system_es32f0283 + */ + +/** + * @} CMSIS + */ +/********** (C) COPYRIGHT Eastsoft Microelectronics END OF FILE **********/ + diff --git a/os/common/ext/CMSIS/ES32/FS026/system_fs026.h b/os/common/ext/CMSIS/ES32/FS026/system_fs026.h new file mode 100644 index 00000000000..03dbc42627d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/FS026/system_fs026.h @@ -0,0 +1,99 @@ +/********************************************************************************** + * + * @file system_es32f0283.h + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer + * + * @date 23 Nov 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Nov 2021 Ginger the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __SYSTEM_FS026_H__ +#define __SYSTEM_ES32F0283_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes -------------------------------------------------------*/ +#include + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup system_es32f0283 + * @{ + */ + +/* Public Functions -----------------------------------------------------------*/ +/* Public Init Structure ------------------------------------------------------*/ +/* Public Macros --------------------------------------------------------------*/ +/* Public Constants -----------------------------------------------------------*/ +/* Private Variables ----------------------------------------------------------*/ +/* Private Macros -------------------------------------------------------------*/ +/* Private Constants-----------------------------------------------------------*/ + +/* Public Types ---------------------------------------------------------------*/ +/** @addtogroup Public_Types + * @{ + */ +extern unsigned int SystemCoreClock; +extern unsigned int SystemFrequency_SysClk; +extern unsigned int SystemFrequency_AHBClk; +extern unsigned int SystemFrequency_APBClk; +extern unsigned int HRC48Frequency; +extern unsigned int PLL0Frequency; + +/* Exported function -------------------------------------------------*/ +/** @addtogroup Public_Functions + * @{ + */ + +extern void SystemInit (void); + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @} Public_Functions + */ + +/** + * @} Public_Types + */ + +/** + * @} system_es32f0283 + */ + +/** + * @} CMSIS + */ +/********** (C) COPYRIGHT Eastsoft Microelectronics END OF FILE **********/ diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/FS026.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/FS026.ld new file mode 100644 index 00000000000..efeb40c1704 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/FS026.ld @@ -0,0 +1,85 @@ +/* + Copyright (C) 2021 essemi + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + *memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 128k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 16k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_FS026.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_FS026.mk new file mode 100644 index 00000000000..00335d09a42 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_FS026.mk @@ -0,0 +1,30 @@ +# List of the ChibiOS generic FS026 startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_utils.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_tick.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_fc.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_gpio.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_uart.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/FS026 \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026 \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/ald \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/FS026 + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) \ No newline at end of file diff --git a/os/common/startup/ARMCMx/devices/FS026/cmparams.h b/os/common/startup/ARMCMx/devices/FS026/cmparams.h new file mode 100644 index 00000000000..274e4a841af --- /dev/null +++ b/os/common/startup/ARMCMx/devices/FS026/cmparams.h @@ -0,0 +1,85 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file cmparams.h + * @brief ARM Cortex-M0 parameters for mcu. + * + * @defgroup ARMCMx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * MCU platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 0 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 0 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +/* If the device type is not externally defined, for example from the Makefile, + then a file named board.h is included. This file must contain a device + definition compatible with the vendor include file.*/ +#if 1 + +#include "board.h" +#endif + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 32 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "fs026.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/os/hal/boards/FS026/board.c b/os/hal/boards/FS026/board.c new file mode 100644 index 00000000000..162df14f365 --- /dev/null +++ b/os/hal/boards/FS026/board.c @@ -0,0 +1,54 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "board.h" + +static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555; +extern void enter_bootloader_mode_if_requested(void); + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +#ifdef ES_INCLUDE_INFO_CONFIG_FILE +void __chibios_override___early_init(void) +#else +void __early_init(void) +#endif +{ + +} + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ + +#ifdef ES_INCLUDE_INFO_CONFIG_FILE +void __chibios_override_boardInit(void) +#else +void boardInit(void) +#endif +{ + +} diff --git a/os/hal/boards/FS026/board.h b/os/hal/boards/FS026/board.h new file mode 100644 index 00000000000..caa6dac4b1a --- /dev/null +++ b/os/hal/boards/FS026/board.h @@ -0,0 +1,58 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + +#include "fs026.h" +#include "md_tick.h" +#include "md_rcu.h" +#include "md_syscfg.h" +#include "md_fc.h" +#include "md_gpio.h" +#include "md_dma.h" +#include "md_csu.h" +#include "md_rtc.h" +#include "md_exti.h" +#include "md_uart.h" +#include "md_spi.h" +#include "md_i2c.h" +#include "md_timer.h" +#include "md_wwdt.h" +#include "md_iwdt.h" +#include "md_adc.h" +#include "md_utils.h" +#include "ald_usb.h" + +#define ES32_HAS_GPIOA 1 +#define ES32_HAS_GPIOB 1 +#define ES32_HAS_GPIOC 1 +#define ES32_HAS_GPIOD 1 + + + void boardInit(void); + +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/FS026/board.mk b/os/hal/boards/FS026/board.mk new file mode 100644 index 00000000000..24e75990127 --- /dev/null +++ b/os/hal/boards/FS026/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/FS026/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/FS026 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) \ No newline at end of file diff --git a/os/hal/ports/ES32/FS026/es32_registry.h b/os/hal/ports/ES32/FS026/es32_registry.h new file mode 100644 index 00000000000..a7e0ba31dd4 --- /dev/null +++ b/os/hal/ports/ES32/FS026/es32_registry.h @@ -0,0 +1,120 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ES32_registry.h + * @brief capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef ES32_REGISTRY_H +#define ES32_REGISTRY_H + +/** + * @brief Sub-family identifier. + */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @brief Maximum system and core clock (f_SYS) frequency. + */ +#define ES32_SYSCLK_MAX 72000000L + +/** + * @brief Maximum bus clock (f_BUS) frequency. + */ +#define ES32_BUSCLK_MAX 72000000L + +/** + * @brief Maximum flash clock (f_FLASH) frequency. + */ +#define ES32_FLASHCLK_MAX 72000000L + +/** + * @name attributes + * @{ + */ + +/* GPIO attributes.*/ +#define ES32_NUM_GPIO 5 + +#define ES32_GPIO_INDEX_BITS 13 +#define ES32_CCR_PAEN CKCU_AHBCCR_PAEN + +/* EXTI attributes */ +#define ES32_HAS_EXTI TRUE +#define ES32_NUM_EXTI 16 +#define ES32_EVWUP_IRQ_VECTOR Vector58 +#define ES32_EXTI0_IRQ_VECTOR Vector60 +#define ES32_EXTI1_IRQ_VECTOR Vector64 +#define ES32_EXTI2_IRQ_VECTOR Vector68 +#define ES32_EXTI3_IRQ_VECTOR Vector6C +#define ES32_EXTI4_IRQ_VECTOR Vector70 +#define ES32_EXTI5_IRQ_VECTOR Vector74 +#define ES32_EXTI6_IRQ_VECTOR Vector78 +#define ES32_EXTI7_IRQ_VECTOR Vector7C +#define ES32_EXTI8_IRQ_VECTOR Vector80 +#define ES32_EXTI9_IRQ_VECTOR Vector84 +#define ES32_EXTI10_IRQ_VECTOR Vector88 +#define ES32_EXTI11_IRQ_VECTOR Vector8C +#define ES32_EXTI12_IRQ_VECTOR Vector90 +#define ES32_EXTI13_IRQ_VECTOR Vector94 +#define ES32_EXTI14_IRQ_VECTOR Vector98 +#define ES32_EXTI15_IRQ_VECTOR Vector9C + +/* I2C attributes.*/ +#define ES32_HAS_I2C0 TRUE +#define ES32_I2C0_IRQ_VECTOR VectorEC +#define ES32_HAS_I2C1 TRUE +#define ES32_I2C1_IRQ_VECTOR VectorF0 + +/* SPI attributes.*/ +#define ES32_HAS_SPI0 TRUE +#define ES32_SPI0_IRQ_VECTOR VectorF4 +#define ES32_HAS_SPI1 TRUE +#define ES32_SPI1_IRQ_VECTOR VectorF8 + +/* UART attributes.*/ +#define ES32_HAS_USART0 TRUE +#define ES32_USART0_IRQ_VECTOR VectorFC +#define ES32_HAS_USART1 TRUE +#define ES32_USART1_IRQ_VECTOR Vector100 +#define ES32_HAS_UART0 TRUE +#define ES32_UART0_IRQ_VECTOR Vector104 +#define ES32_HAS_UART1 TRUE +#define ES32_UART1_IRQ_VECTOR Vector108 + +/* USB attributes.*/ +#define ES32_HAS_USB TRUE +#define ES32_USB_IRQ_VECTOR Vector114 +#define ES32_USB0_IS_USBOTG FALSE +#define ES32_HAS_USB_CLOCK_RECOVERY FALSE + +/* BFTM attributes. */ +#define ES32_BFTM0_IRQ_VECTOR VectorE4 +#define ES32_BFTM1_IRQ_VECTOR VectorE8 + +/** @} */ + +#endif /* ES32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/FS026/hal_lld.c b/os/hal/ports/ES32/FS026/hal_lld.c new file mode 100644 index 00000000000..a0cea4cc504 --- /dev/null +++ b/os/hal/ports/ES32/FS026/hal_lld.c @@ -0,0 +1,152 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief update the value of SystemCoreClock after changing the system clock. + */ +unsigned int SystemCoreClock; +unsigned int SystemFrequency_SysClk; +unsigned int SystemFrequency_AHBClk; +unsigned int SystemFrequency_APBClk; +unsigned int HRC48Frequency; +unsigned int PLL0Frequency; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void HardFault_Handler(void) +{ + while(1); +} + +uint32_t g_es_systick_time = 0U; + +int es_test_printf(char *pBuffer, int size) +{ + for (int i = 0; i < size; i++) + { + while (!((UART1->STAT) & (UART_STAT_TFEMPTY))); // Tx FIFO empty + UART1->TXDATA = pBuffer[i]; // Sent byte + } + + return size; +} + +void gpio_config(void){ + md_gpio_inittypedef gpiox; + /* config gpiob pin6 (Tx) */ + gpiox.Pin = MD_GPIO_PIN_6; + gpiox.Mode = MD_GPIO_MODE_FUNCTION; + gpiox.OutputType = MD_GPIO_OUTPUT_PUSHPULL; + gpiox.Pull = MD_GPIO_PULL_FLOATING; + gpiox.OutDrive = MD_GPIO_DRIVING_8MA; + gpiox.Function = MD_GPIO_AF2; + md_gpio_init(GPIOB, &gpiox); + /* config gpiob pin7 (Rx) */ + gpiox.Pin = MD_GPIO_PIN_7; + gpiox.Mode = MD_GPIO_MODE_FUNCTION; + gpiox.OutputType = MD_GPIO_OUTPUT_PUSHPULL; + gpiox.Pull = MD_GPIO_PULL_UP; + gpiox.OutDrive = MD_GPIO_DRIVING_8MA; + gpiox.Function = MD_GPIO_AF2; + md_gpio_init(GPIOB, &gpiox); +} + +md_rcu_init_typedef rcu_initStruct = /**< RCU init structure */ +{ + MD_RCU_MPRE_MCO_DIV1, + MD_RCU_MSW_MCO_DISABLE, + MD_RCU_PLLSRC_HRC48, + MD_RCU_PLLCLK_72M, + MD_RCU_PPRE_HCLK_DIV_1, + MD_RCU_HPRE_SYSCLK_DIV_1, + MD_RCU_SW_SYSCLK_PLL0, + (RCU_CON_HRCON | RCU_CON_PLL0ON | RCU_CON_HRC48ON_MSK), +}; + +md_uart_init_typedef uart_initStruct = /**< UART init structure */ +{ + (921600U), + MD_UART_LCON_LSB_FIRST, + MD_UART_LCON_PS_NONE, + MD_UART_LCON_STOP_1, + MD_UART_LCON_DLS_8, +}; + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) +{ + __disable_irq(); + md_rcu_pll0_init(RCU, &rcu_initStruct); + md_rcu_sys_init(RCU, &rcu_initStruct); + md_rcu_enable_gpioa(RCU); + md_rcu_enable_gpiob(RCU); + md_rcu_enable_gpioc(RCU); + md_rcu_enable_gpiod(RCU); + md_rcu_enable_uart1(RCU); + md_rcu_enable_usb(RCU); + gpio_config(); + +// NVIC->ICER[0] = 0xFFFFFFFFUL; +// md_tick_init(MD_SYSTICK_CLKSRC_HCLK); +// md_mcu_irq_config(UART1_IRQn, 2, ENABLE); + md_uart_init(UART1, &uart_initStruct); +// md_uart_enable_it_rfnempty(UART1); + + __enable_irq(); + + es_test_printf("hal_lld_init ok\r\n",sizeof("hal_lld_init ok\r\n")); + +} + +/** @} */ diff --git a/os/hal/ports/ES32/FS026/hal_lld.h b/os/hal/ports/ES32/FS026/hal_lld.h new file mode 100644 index 00000000000..dc4fa2a6cd5 --- /dev/null +++ b/os/hal/ports/ES32/FS026/hal_lld.h @@ -0,0 +1,80 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.h + * @brief ES32 HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "es32_registry.h" +#include "nvic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "ES32" +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +void hal_lld_init(void); +void ht32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/ES32/FS026/platform.mk b/os/hal/ports/ES32/FS026/platform.mk new file mode 100644 index 00000000000..52ede035ccb --- /dev/null +++ b/os/hal/ports/ES32/FS026/platform.mk @@ -0,0 +1,38 @@ +# List of all the platform files. +PLATFORMSRC = $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/FS026/hal_lld.c + + +# Required include directories +PLATFORMINC = $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/FS026 + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif +endif + +HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) +endif #ifeq ($(USE_SMART_BUILD), yes) + +# Drivers compatible with the platform. +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/ADCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/I2Cv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/SPIv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/GPIOv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/USBv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/UARTv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/WDTv1/driver.mk + + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/ES32/LLD/ADCv1/driver.mk b/os/hal/ports/ES32/LLD/ADCv1/driver.mk new file mode 100644 index 00000000000..06a6cf91ca4 --- /dev/null +++ b/os/hal/ports/ES32/LLD/ADCv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/ADCv1 diff --git a/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c b/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c new file mode 100644 index 00000000000..63e0dfff906 --- /dev/null +++ b/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c @@ -0,0 +1,149 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ADCv1/hal_adc_lld.c + * @brief ES32 ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if ES32_ADC_USE_ADC1 || defined(__DOXYGEN__) + ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if ES32_ADC_USE_ADC1 || defined(__DOXYGEN__) +#if !defined(ES32_ADC1_HANDLER) + #error "ES32_ADC1_HANDLER not defined" +#endif +/** + * @brief ADC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(ES32_ADC1_HANDLER) +{ + + OSAL_IRQ_PROLOGUE(); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) +{ + +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) +{ + + +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) +{ + +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) +{ + +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) +{ + +} + +/** + * @brief ISR code. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_serve_interrupt(ADCDriver *adcp) +{ + +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.h b/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.h new file mode 100644 index 00000000000..634cdbee1da --- /dev/null +++ b/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.h @@ -0,0 +1,130 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ADCv1/hal_adc_lld.h + * @brief ES32 ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef HAL_ADC_LLD_H +#define HAL_ADC_LLD_H + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Type of an ADC error mask. + */ +typedef uint32_t adcerror_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the ADC driver structure. + */ +#define adc_lld_driver_fields \ + /* Pointer to the ADCx registers block.*/ \ + ADC_TypeDef *adc; \ + /* Pointer to associated DMA channel.*/ \ + const void *dmastp; \ + /* DMA mode bit mask.*/ \ + uint32_t dmamode + +/** + * @brief Low level fields of the ADC configuration structure. + */ +#define adc_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ + uint32_t dummy + +/** + * @brief Low level fields of the ADC configuration structure. + */ +#define adc_lld_configuration_group_fields \ + /* ADC CFGR1 register initialization data. \ + NOTE: The bits DMAEN and DMACFG are enforced internally \ + to the driver, keep them to zero. \ + NOTE: The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be \ + specified in continuous more or if the buffer depth is \ + greater than one.*/ \ + uint32_t cfgr1; \ + /* ADC TR register initialization data.*/ \ + uint32_t tr; \ + /* ADC SMPR register initialization data.*/ \ + uint32_t smpr; \ + /* ADC CHSELR register initialization data. \ + NOTE: The number of bits at logic level one in this register must \ + be equal to the number in the @p num_channels field.*/ \ + uint32_t chselr + + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if ES32_ADC_USE_ADC1 && !defined(__DOXYGEN__) + +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void adc_lld_init(void); +void adc_lld_start(ADCDriver *adcp); +void adc_lld_stop(ADCDriver *adcp); +void adc_lld_start_conversion(ADCDriver *adcp); +void adc_lld_stop_conversion(ADCDriver *adcp); +void adc_lld_serve_interrupt(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* HAL_ADC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/ADCv1/notes.txt b/os/hal/ports/ES32/LLD/ADCv1/notes.txt new file mode 100644 index 00000000000..f376706fca3 --- /dev/null +++ b/os/hal/ports/ES32/LLD/ADCv1/notes.txt @@ -0,0 +1,16 @@ +ES32 ADCv1 driver. + +Driver capability: + +- Supports the ES32 "simple" ADC, the one found on small devices (F0, L0). + +The file registry must export: + +ES32_HAS_ADC1 - ADC1 presence flag. +ES32_ADC_SUPPORTS_PRESCALER - Support of CCR PRESC field. +ES32_ADC_SUPPORTS_OVERSAMPLING - Support of oversampling-related fields. +ES32_ADC1_IRQ_SHARED_WITH_EXTI - TRUE if the IRQ is shared with EXTI. +ES32_ADC1_HANDLER - IRQ vector name. +ES32_ADC1_NUMBER - IRQ vector number. +ES32_ADC1_DMA_MSK - Mask of the compatible DMA channels. +ES32_ADC1_DMA_CHN - Mask of the channels mapping. diff --git a/os/hal/ports/ES32/LLD/GPIOv1/driver.mk b/os/hal/ports/ES32/LLD/GPIOv1/driver.mk new file mode 100644 index 00000000000..e15ab9d4363 --- /dev/null +++ b/os/hal/ports/ES32/LLD/GPIOv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/GPIOv1 diff --git a/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.c new file mode 100644 index 00000000000..66590676ec9 --- /dev/null +++ b/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.c @@ -0,0 +1,232 @@ +/* + Copyright (C) 2020 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_pal_lld.c + * @brief ES32 PAL subsystem low level driver source. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) || defined(__DOXYGEN__) +/** + * @brief Event records for the 16 GPIO EXTI channels. + */ +palevent_t _pal_events[16]; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief PAL driver initialization. + * + * @notapi + */ +void _pal_lld_init(void) { + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) + unsigned i; + + for (i = 0; i < 16; i++) { + _pal_init_event(i); + } +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum + * speed. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) +{ + + uint32_t mod = (mode & PAL_ES32_MODE_MASK) >> 0; + uint32_t ot = (mode & PAL_ES32_OT_MASK) >> 2; + uint32_t ds = (mode & PAL_ES32_DS_MASK) >> 3; + uint32_t pud = (mode & PAL_ES32_PUD_MASK) >> 5; + uint32_t altr = (mode & PAL_ES32_ALTERNATE_MASK) >> 7; + uint32_t bit = 0; + while (true) { + if ((mask & 1) != 0) { + uint32_t altrmask, m1, m2, m4; + + altrmask = altr << ((bit & 7) * 4); + m1 = 1 << bit; + m2 = 3 << (bit * 2); + m4 = 15 << ((bit & 7) * 4); + port->OT = (port->OT & ~m1) | ot; + port->DS = (port->DS & ~m1) | ds; + port->PUD = (port->PUD & ~m2) | pud; + if ((mode & PAL_ES32_MODE_MASK) == PAL_ES32_MODE_ALTERNATE) { + /* If going in alternate mode then the alternate number is set + before switching mode in order to avoid glitches.*/ + if (bit < 8) + port->AFL = (port->AFL & ~m4) | altrmask; + else + port->AFH = (port->AFH & ~m4) | altrmask; + port->MOD = (port->MOD & ~m2) | mod; + } + else { + /* If going into a non-alternate mode then the mode is switched + before setting the alternate mode in order to avoid glitches.*/ + port->MOD = (port->MOD & ~m2) | mod; + if (bit < 8) + port->AFL = (port->AFL & ~m4) | altrmask; + else + port->AFH = (port->AFH & ~m4) | altrmask; + } + } + mask >>= 1; + if (!mask) + return; + ot <<= 1; + ds <<= 1; + pud <<= 2; + mod <<= 2; + bit++; + } +} + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode) { + + uint32_t padmask, cridx, croff, crmask, portidx; + + /* Mask of the pad.*/ + padmask = 1U << (uint32_t)pad; + + if (pad & 3U) + NVIC_EnableIRQ((IRQn_Type) EXTI_0to1_IRQn); /* EXTI_0to1_IRQn interrupt */ + else if (pad & 0xCU) + NVIC_EnableIRQ((IRQn_Type) EXTI_2to3_IRQn); /* EXTI_2to3_IRQn interrupt */ + else if (pad & 0xFFF0U) + NVIC_EnableIRQ((IRQn_Type) EXTI_4to15_IRQn); /* EXTI_4to15_IRQn interrupt */ + + /* Clear pending interrupt flag before enable interrupt event */ + EXTI->ICR = EXTI_IFM; + + /* Programming edge registers.*/ + if (mode & PAL_EVENT_MODE_RISING_EDGE) + EXTI->RTS |= padmask; + else + EXTI->RTS &= ~padmask; + if (mode & PAL_EVENT_MODE_FALLING_EDGE) + EXTI->FTS |= padmask; + else + EXTI->FTS &= ~padmask; + + portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0x3U; + if (padmask < 8) + EXTI_ICFG1 = (uint32_t)portidx << (pad * 4U); + else + EXTI_ICFG2 = (uint32_t)portidx << (pad * 4U); + + EXTI_IER = padmask; +} + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { + uint32_t padmask, rtsr1, ftsr1; + + rts = EXTI->RTS; + fts = EXTI->FTS; + + /* Mask of the pad.*/ + padmask = 1U << (uint32_t)pad; + + /* Clear pending interrupt flag before enable interrupt event */ + EXTI->ICR = EXTI_IFM; + EXTI->IDR = padmask; + + if (((pad & 3U) | (EXTI_IER & 3U)) == 0) + NVIC_DisableIRQ((IRQn_Type) EXTI_0to1_IRQn); /* EXTI_0to1_IRQn interrupt */ + else if (((pad & 0xCU) | (EXTI_IER & 0xCU)) == 0) + NVIC_DisableIRQ((IRQn_Type) EXTI_2to3_IRQn); /* EXTI_2to3_IRQn interrupt */ + else if ((pad & 0xFFF0U) | (EXTI_IER & 0xFFF0U) == 0) + NVIC_DisableIRQ((IRQn_Type) EXTI_4to15_IRQn); /* EXTI_4to15_IRQn interrupt */ + + /* Disabling channel.*/ + EXTI->RTS = rts & ~padmask; + EXTI->FTS = fts & ~padmask; + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + /* Callback cleared and/or thread reset.*/ + _pal_clear_event(pad); +#endif + } +} +#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */ +#endif /* HAL_USE_PAL == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h new file mode 100644 index 00000000000..ffe0107f5b1 --- /dev/null +++ b/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h @@ -0,0 +1,440 @@ +/* + Copyright (C) 2020 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_pal_lld.h + * @brief ES32 PAL low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +/* Specifies palInit() without parameter, required until all platforms will + be updated to the new style.*/ +#define PAL_NEW_INIT + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name ES32-specific I/O mode flags + * @{ + */ +#define PAL_ES32_MODE_MASK (3U << 0U) +#define PAL_ES32_MODE_INPUT (0U << 0U) +#define PAL_ES32_MODE_OUTPUT (1U << 0U) +#define PAL_ES32_MODE_ALTERNATE (2U << 0U) +#define PAL_ES32_MODE_ANALOG (3U << 0U) + +#define PAL_ES32_OT_MASK (1U << 2U) +#define PAL_ES32_OT_PUSHPULL (0U << 2U) +#define PAL_ES32_OT_OPENDRAIN (1U << 2U) + +#define PAL_ES32_DS_MASK (1U << 3U) +#define PAL_ES32_DS_8MA (0U << 3U) +#define PAL_ES32_DS_16MA (1U << 3U) + +#define PAL_ES32_PUD_MASK (3U << 5U) +#define PAL_ES32_PUD_FLOATING (0U << 5U) +#define PAL_ES32_PUD_PULLUP (1U << 5U) +#define PAL_ES32_PUD_PULLDOWN (2U << 5U) + +#define PAL_ES32_ALTERNATE_MASK (15U << 7U) +#define PAL_ES32_ALTERNATE(n) ((n) << 7U) + +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) (PAL_ES32_MODE_ALTERNATE | \ + PAL_ES32_ALTERNATE(n)) +/** @} */ + +/** + * @name Standard I/O mode flags + * @{ + */ +/** + * @brief Implemented as input. + */ +#define PAL_MODE_RESET PAL_ES32_MODE_ANALOG + +/** + * @brief Implemented as input with pull-up. + */ +#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT PAL_ES32_MODE_INPUT + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_ES32_MODE_INPUT | \ + PAL_ES32_PUD_PULLUP) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_ES32_MODE_INPUT | \ + PAL_ES32_PUPDR_PULLDOWN) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG PAL_ES32_MODE_ANALOG + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_ES32_MODE_OUTPUT | \ + PAL_ES32_OT_PUSHPULL) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_ES32_MODE_OUTPUT | \ + PAL_ES32_OT_OPENDRAIN) +/** @} */ +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16U + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFU) +/** @} */ + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((GPIO_TypeDef *)(((uint32_t)(line)) & 0xFFFFFFF0U)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief Type of digital I/O port sized unsigned integer. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Type of digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Type of an event mode. + */ +typedef uint32_t ioeventmode_t; + +/** + * @brief Type of a port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef GPIO_TypeDef * ioportid_t; + +/** + * @brief Type of an pad identifier. + */ +typedef uint32_t iopadid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the ES32 */ +/* firmware library. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init() _pal_lld_init() + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the GPIO ID register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((ioportmask_t)((port)->ID)) + + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the GPIO OD register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((ioportmask_t)((port)->OD)) + +/** + * @brief Writes on a I/O port. + * @details This function is implemented by writing the GPIO OD register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) \ + do { \ + (port)->OD = (uint32_t)(bits); \ + } while (false) + + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) \ + do { \ + (port)->BSBR = (uint32_t)(bits); \ + } while (false) + + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) \ + do { \ + (port)->BSBR = (uint32_t)(bits << 16); \ + } while (false) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits){ \ + uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \ + ((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \ + (port)->BSBR = w; \ +} + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +#define pal_lld_enablepadevent(port, pad, mode) \ + _pal_lld_enablepadevent(port, pad, mode) + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_disablepadevent(port, pad) \ + _pal_lld_disablepadevent(port, pad) + +/** + * @brief Returns a PAL event structure associated to a pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_get_pad_event(port, pad) \ + &_pal_events[pad]; (void)(port) + +/** + * @brief Returns a PAL event structure associated to a line. + * + * @param[in] line line identifier + * + * @notapi + */ +#define pal_lld_get_line_event(line) \ + &_pal_events[PAL_PAD(line)] + +/** + * @brief Pad event enable check. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return Pad event status. + * @retval false if the pad event is disabled. + * @retval true if the pad event is enabled. + * + * @notapi + */ +#define pal_lld_ispadeventenabled(port, pad) \ + (bool)((EXTI->IFM & (1U << (uint32_t)pad)) != 0U) + +#if !defined(__DOXYGEN__) +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) +extern palevent_t _pal_events[16]; +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(void); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); + void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode); + void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL == TRUE */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/I2Cv1/driver.mk b/os/hal/ports/ES32/LLD/I2Cv1/driver.mk new file mode 100644 index 00000000000..4af286c2220 --- /dev/null +++ b/os/hal/ports/ES32/LLD/I2Cv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/I2Cv1 diff --git a/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c new file mode 100644 index 00000000000..d987a957a59 --- /dev/null +++ b/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c @@ -0,0 +1,248 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file I2Cv1/hal_i2c_lld.c + * @brief ES32 I2C subsystem low level driver source. + * + * @addtogroup I2C + * @{ + */ + +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if ES32_I2C_USE_I2C1 || defined(__DOXYGEN__) +/** + * @brief I2C1 event interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(ES32_I2C1_EVENT_HANDLER) +{ + + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief I2C1 error interrupt handler. + */ +OSAL_IRQ_HANDLER(ES32_I2C1_ERROR_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* ES32_I2C_USE_I2C1 */ + +#if ES32_I2C_USE_I2C2 || defined(__DOXYGEN__) +/** + * @brief I2C2 event interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(ES32_I2C2_EVENT_HANDLER) +{ + + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief I2C2 error interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(ES32_I2C2_ERROR_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* ES32_I2C_USE_I2C2 */ + +#if ES32_I2C_USE_I2C3 || defined(__DOXYGEN__) +/** + * @brief I2C3 event interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(ES32_I2C3_EVENT_HANDLER) +{ + + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_event_interrupt(&I2CD3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief I2C3 error interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(ES32_I2C3_ERROR_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* ES32_I2C_USE_I2C3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) +{ + +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) +{ + +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) +{ + +} + +/** + * @brief Receives data via the I2C bus as master. + * @details Number of receiving bytes must be more than 1 on ES32F1x. This is + * hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout) +{ + + return MSG_OK; +} + +/** + * @brief Transmits data via the I2C bus as master. + * @details Number of receiving bytes must be 0 or more than 1 on ES32F1x. + * This is hardware restriction. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout) +{ + + return MSG_OK; + +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.h b/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.h new file mode 100644 index 00000000000..7bc24fef352 --- /dev/null +++ b/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.h @@ -0,0 +1,195 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file I2Cv1/hal_i2c_lld.h + * @brief ES32 I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef HAL_I2C_LLD_H +#define HAL_I2C_LLD_H + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing an I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief Type of I2C driver condition flags. + */ +typedef uint32_t i2cflags_t; + +/** + * @brief Supported modes for the I2C bus. + */ +typedef enum { + OPMODE_I2C = 1, + OPMODE_SMBUS_DEVICE = 2, + OPMODE_SMBUS_HOST = 3, +} i2copmode_t; + +/** + * @brief Supported duty cycle modes for the I2C bus. + */ +typedef enum { + STD_DUTY_CYCLE = 1, + FAST_DUTY_CYCLE_2 = 2, + FAST_DUTY_CYCLE_16_9 = 3, +} i2cdutycycle_t; + +/** + * @brief I2C driver configuration structure. + */ +struct hal_i2c_config { + /* End of the mandatory fields.*/ + i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */ + uint32_t clock_speed; /**< @brief Specifies the clock frequency. + @note Must be set to a value lower + than 400kHz. */ + i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode + duty cycle. */ +}; + +/** + * @brief Type of a structure representing an I2C configuration. + */ +typedef struct hal_i2c_config I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct hal_i2c_driver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct hal_i2c_driver { + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion. + */ + thread_reference_t thread; + /** + * @brief Current slave address without R/W bit. + */ + i2caddr_t addr; + /** + * @brief RX DMA mode bit mask. + */ + uint32_t rxdmamode; + /** + * @brief TX DMA mode bit mask. + */ + uint32_t txdmamode; + /** + * @brief Receive DMA channel. + */ + const void *dmarx; + /** + * @brief Transmit DMA channel. + */ + const void *dmatx; + /** + * @brief Pointer to the I2Cx registers block. + */ + I2C_TypeDef *i2c; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +void i2c_lld_init(void); +void i2c_lld_start(I2CDriver *i2cp); +void i2c_lld_stop(I2CDriver *i2cp); +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout); +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + sysinterval_t timeout); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* HAL_I2C_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/SPIv1/driver.mk b/os/hal/ports/ES32/LLD/SPIv1/driver.mk new file mode 100644 index 00000000000..738b7bcf35b --- /dev/null +++ b/os/hal/ports/ES32/LLD/SPIv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/SPIv1 diff --git a/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c new file mode 100644 index 00000000000..c3db92cac76 --- /dev/null +++ b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c @@ -0,0 +1,374 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_spi_lld.c + * @brief ES32 SPI subsystem low level driver source. + * + * @addtogroup SPI + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_SPI == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SPI0 driver identifier. + */ +#if (ES32_SPI_USE_SPI0 == TRUE) || defined(__DOXYGEN__) + SPIDriver SPID0; +#endif +#if (ES32_SPI_USE_SPI1 == TRUE) || defined(__DOXYGEN__) + SPIDriver SPID1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if (ES32_SPI_USE_SPI0 == TRUE) || (ES32_SPI_USE_SPI1 == TRUE) || defined(__DOXYGEN__) +static void spi_lld_rx(SPIDriver *const spip) +{ + uint32_t fd; + uint32_t sr; + + while (spip->rxcnt) + { + sr = spip->SPI->SR; + + if ((sr & SPI_SR_RXBNE) == 0) + return; + + fd = spip->SPI->DR; + + if (spip->rxptr) + { + *spip->rxptr++ = fd & 0xff; + } + + spip->rxcnt--; + } +} + +static void spi_lld_tx(SPIDriver *const spip) +{ + uint32_t fd; + uint32_t sr; + + while (spip->txcnt) + { + sr = spip->SPI->SR; + + // avoid write collision + if (spip->SPI->FCR & SPI_FCR_FIFOEN) + { + if ((sr & SPI_SR_TXBE) == 0) + return; + } + else + { + if ((sr & SPI_SR_TXE) == 0) + return; + } + + if (spip->txptr) + { + fd = *spip->txptr++; + } + else + { + fd = '\xff'; + } + + spip->SPI->DR = fd; + spip->txcnt--; + } +} + +static void spi_lld_handler(SPIDriver *const spip) +{ + //uint32_t sr = spip->SPI->SR; // & ((1U<<8)|spip->SPI->IER); + spi_lld_rx(spip); + spi_lld_tx(spip); + + if (spip->rxcnt == 0) + { + spip->SPI->IER = 0; + _spi_isr_code(spip); + } +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (ES32_SPI_USE_SPI0 == TRUE) || defined(__DOXYGEN__) +OSAL_IRQ_HANDLER(ES32_SPI0_IRQ_VECTOR) +{ + OSAL_IRQ_PROLOGUE(); + spi_lld_handler(&SPID0); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if (ES32_SPI_USE_SPI1 == TRUE) || defined(__DOXYGEN__) +OSAL_IRQ_HANDLER(ES32_SPI1_IRQ_VECTOR) +{ + OSAL_IRQ_PROLOGUE(); + spi_lld_handler(&SPID1); + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) +{ + /* Driver initialization.*/ +#if ES32_SPI_USE_SPI0 == TRUE + spiObjectInit(&SPID0); + SPID0.SPI = SPI0; +// CKCU->APBCCR0 |= CKCU_APBCCR0_SPI0EN; +#endif +#if ES32_SPI_USE_SPI1 == TRUE + spiObjectInit(&SPID1); + SPID1.SPI = SPI1; +// CKCU->APBCCR0 |= CKCU_APBCCR0_SPI1EN; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) +{ + if (spip->state == SPI_STOP) + { + /* Enables the peripheral.*/ +#if ES32_SPI_USE_SPI0 == TRUE + if (&SPID0 == spip) + { + CKCU->APBCCR0 |= CKCU_APBCCR0_SPI0EN; + nvicEnableVector(SPI0_IRQn, ES32_SPI0_IRQ_PRIORITY); + } + +#endif +#if ES32_SPI_USE_SPI1 == TRUE + + if (&SPID1 == spip) + { + CKCU->APBCCR0 |= CKCU_APBCCR0_SPI1EN; + nvicEnableVector(SPI1_IRQn, ES32_SPI1_IRQ_PRIORITY); + } + +#endif + } + + /* Configures the peripheral.*/ + spip->SPI->CR0 = spip->config->cr0; + spip->SPI->CR1 = spip->config->cr1; + spip->SPI->CPR = spip->config->cpr; + //spip->SPI->FCR = 0; //SPI_FCR_FIFOEN | (1U << 4) | (1U << 0); + spip->SPI->FCR = spip->config->fcr; + spip->SPI->CR0 |= SPI_CR0_SPIEN; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) +{ + if (spip->state == SPI_READY) + { + /* Disables the peripheral.*/ +#if ES32_SPI_USE_SPI0 == TRUE + if (&SPID0 == spip) + { + RSTCU->APBPRSTR0 = RSTCU_APBPRSTR0_SPI0RST; + CKCU->APBCCR0 &= ~CKCU_APBCCR0_SPI0EN; + nvicDisableVector(SPI0_IRQn); + } + +#endif +#if ES32_SPI_USE_SPI1 == TRUE + + if (&SPID1 == spip) + { + RSTCU->APBPRSTR0 = RSTCU_APBPRSTR0_SPI1RST; + CKCU->APBCCR0 &= ~CKCU_APBCCR0_SPI1EN; + nvicDisableVector(SPI1_IRQn); + } + +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) +{ + spip->SPI->CR0 |= SPI_CR0_SSELC; +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) +{ + spip->SPI->CR0 &= ~SPI_CR0_SSELC; +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) +{ + spi_lld_exchange(spip, n, NULL, NULL); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) +{ + spip->txptr = txbuf; + spip->rxptr = rxbuf; + spip->rxcnt = spip->txcnt = n; + spip->SPI->IER = SPI_IER_RXBNEIEN | SPI_IER_TXBEIEN | SPI_IER_TXEIEN; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) +{ + spi_lld_exchange(spip, n, txbuf, NULL); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) +{ + spi_lld_exchange(spip, n, NULL, rxbuf); +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) +{ + spip->SPI->DR = frame; + + while ((spip->SPI->SR & SPI_SR_RXBNE) == 0) + ; + + return (spip->SPI->DR & 0xffff); +} + +#endif /* HAL_USE_SPI == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h new file mode 100644 index 00000000000..2dcab582cab --- /dev/null +++ b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h @@ -0,0 +1,120 @@ +/* + Copyright (C) 2020 Yaotian Feng + + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_spi_lld.h + * @brief ES32 SPI subsystem low level driver header. + * + * @addtogroup SPI + * @{ + */ +#ifndef HAL_SPI_LLD_H +#define HAL_SPI_LLD_H + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name ES32 configuration options + * @{ + */ +/** + * @brief SPI0 driver enable switch. + * @details If set to @p TRUE the support for SPI0 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_SPI_USE_SPI0) || defined(__DOXYGEN__) + #define ES32_SPI_USE_SPI0 FALSE +#endif +#if !defined(ES32_SPI_USE_SPI1) || defined(__DOXYGEN__) + #define ES32_SPI_USE_SPI1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + + +/** + * @brief Low Level fields of the SPI driver structure. + */ +#define spi_lld_driver_fields \ + SPI_TypeDef *SPI; \ + uint8_t *rxptr; \ + const uint8_t *txptr; \ + size_t rxcnt; \ + size_t txcnt; \ + + /** + * @brief Low Level fields of the SPI configuration structure. + */ +#define spi_lld_config_fields \ + uint32_t cr0; \ + uint32_t cr1; \ + uint32_t cpr; \ + uint32_t fcr; + + /*===========================================================================*/ + /* Driver macros. */ + /*===========================================================================*/ + + /*===========================================================================*/ + /* External declarations. */ + /*===========================================================================*/ + +#if (ES32_SPI_USE_SPI0 == TRUE) && !defined(__DOXYGEN__) + extern SPIDriver SPID0; +#endif +#if (ES32_SPI_USE_SPI1 == TRUE) && !defined(__DOXYGEN__) + extern SPIDriver SPID1; +#endif + +#ifdef __cplusplus + extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus + } +#endif + +#endif /* HAL_USE_SPI == TRUE */ + +#endif /* HAL_SPI_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv1/driver.mk b/os/hal/ports/ES32/LLD/TIMv1/driver.mk new file mode 100644 index 00000000000..1b5036f9a6f --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv1/driver.mk @@ -0,0 +1,15 @@ +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.c + +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.c +endif +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv1 diff --git a/os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.c b/os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.c new file mode 100644 index 00000000000..efb325057d9 --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.c @@ -0,0 +1,238 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_gpt_lld.c + * @brief PLATFORM GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPTD1 driver identifier. + */ +#if (ES32_GPT_USE_BFTM0 == TRUE) || defined(__DOXYGEN__) + GPTDriver GPTD_BFTM0; +#endif + +#if (ES32_GPT_USE_BFTM1 == TRUE) || defined(__DOXYGEN__) + GPTDriver GPTD_BFTM1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpt_lld_handler(GPTDriver *gptp) +{ + if (gptp->BFTM->SR & BFTM_SR_MIF) + { + gptp->BFTM->SR = 0; + + if (gptp->config->callback) + gptp->config->callback(gptp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (ES32_GPT_USE_BFTM0 == TRUE) || defined(__DOXYGEN__) +#ifndef ES32_BFTM0_IRQ_VECTOR + #error "ES32_BFTM0_IRQ_VECTOR is not defined" +#endif +OSAL_IRQ_HANDLER(ES32_BFTM0_IRQ_VECTOR) +{ + OSAL_IRQ_PROLOGUE(); + gpt_lld_handler(&GPTD_BFTM0); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if (ES32_GPT_USE_BFTM1 == TRUE) || defined(__DOXYGEN__) +OSAL_IRQ_HANDLER(ES32_BFTM1_IRQ_VECTOR) +{ + OSAL_IRQ_PROLOGUE(); + gpt_lld_handler(&GPTD_BFTM1); + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) +{ + /* Driver initialization.*/ +#if ES32_GPT_USE_BFTM0 == TRUE + gptObjectInit(&GPTD_BFTM0); + GPTD_BFTM0.BFTM = BFTM0; +#endif +#if ES32_GPT_USE_BFTM1 == TRUE + gptObjectInit(&GPTD_BFTM1); + GPTD_BFTM1.BFTM = BFTM1; +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) +{ + if (gptp->state == GPT_STOP) + { + /* Enables the peripheral.*/ +#if ES32_GPT_USE_BFTM0 == TRUE + if (&GPTD_BFTM0 == gptp) + { + CKCU->APBCCR1 |= CKCU_APBCCR1_BFTM0EN; + nvicEnableVector(BFTM0_IRQn, ES32_GPT_BFTM0_IRQ_PRIORITY); + } + +#endif +#if ES32_GPT_USE_BFTM1 == TRUE + + if (&GPTD_BFTM1 == gptp) + { + CKCU->APBCCR1 |= CKCU_APBCCR1_BFTM1EN; + nvicEnableVector(BFTM1_IRQn, ES32_GPT_BFTM1_IRQ_PRIORITY); + } + +#endif + } + + /* Configures the peripheral.*/ + gptp->BFTM->CR = 0; + // counter frequency depends on the AHB clock, we can't + // change anything here +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) +{ + if (gptp->state == GPT_READY) + { + /* Resets the peripheral.*/ + /* Disables the peripheral.*/ +#if ES32_GPT_USE_BFTM0 == TRUE + if (&GPTD_BFTM0 == gptp) + { + RSTCU->APBPRSTR1 = RSTCU_APBPRSTR1_BFTM0RST; + CKCU->APBCCR1 &= ~CKCU_APBCCR1_BFTM0EN; + nvicDisableVector(BFTM0_IRQn); + } + +#endif +#if ES32_GPT_USE_BFTM1 == TRUE + + if (&GPTD_BFTM1 == gptp) + { + RSTCU->APBPRSTR1 = RSTCU_APBPRSTR1_BFTM1RST; + CKCU->APBCCR1 &= ~CKCU_APBCCR1_BFTM1EN; + nvicDisableVector(BFTM1_IRQn); + } + +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) +{ + gptp->BFTM->SR = 0; + gptp->BFTM->CNTR = 0; + gptp->BFTM->CMP = (ES32_CK_AHB_FREQUENCY / gptp->config->frequency) * interval; + gptp->BFTM->CR = BFTM_CR_CEN | BFTM_CR_MIEN; +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) +{ + gptp->BFTM->CR = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) +{ + gptp->BFTM->SR = 0; + gptp->BFTM->CNTR = 0; + gptp->BFTM->CMP = (ES32_CK_AHB_FREQUENCY / gptp->config->frequency) * interval; + gptp->BFTM->CR = BFTM_CR_CEN | BFTM_CR_OSM; + + while (!(gptp->BFTM->SR & BFTM_SR_MIF)) + ; +} + +#endif /* HAL_USE_GPT == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.h b/os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.h new file mode 100644 index 00000000000..16676d44cb0 --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv1/hal_gpt_lld.h @@ -0,0 +1,197 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_gpt_lld.h + * @brief PLATFORM GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef HAL_GPT_LLD_H +#define HAL_GPT_LLD_H + +#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief GPTD1 driver enable switch. + * @details If set to @p TRUE the support for GPTD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_GPT_USE_BFTM0) || defined(__DOXYGEN__) + #define ES32_GPT_USE_BFTM0 FALSE +#endif + +#if !defined(ES32_GPT_USE_BFTM1) || defined(__DOXYGEN__) + #define ES32_GPT_USE_BFTM1 FALSE +#endif + +/** + * @brief GPTD1 interrupt priority level setting. + */ +#if !defined(ES32_GPT_BFTM0_IRQ_PRIORITY) || defined(__DOXYGEN__) + #define ES32_GPT_BFTM0_IRQ_PRIORITY 7 +#endif + +#if !defined(ES32_GPT_BFTM1_IRQ_PRIORITY) || defined(__DOXYGEN__) + #define ES32_GPT_BFTM1_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint16_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct +{ + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver +{ + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; +#if defined(GPT_DRIVER_EXT_FIELDS) + GPT_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + BFTM_TypeDef *BFTM; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must have been activated using @p gptStart(). + * @pre The GPT unit must have been running in continuous mode using + * @p gptStartContinuous(). + * @post The GPT unit interval is changed to the new value. + * @note The function has effect at the next cycle start. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + * @notapi + */ +#define gpt_lld_change_interval(gptp, interval) \ + ((gptp)->BFTM->CMP = (ES32_CK_AHB_FREQUENCY / (gptp)->config->frequency) * (interval)) + +/** + * @brief Returns the interval of GPT peripheral. + * @pre The GPT unit must be running in continuous mode. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @return The current interval. + * @notapi + */ +#define gpt_lld_get_interval(gptp) \ + ((gptcnt_t)(gptp)->BFTM->CMP / (ES32_CK_AHB_FREQUENCY / (gptp)->config->frequency)) + +/** + * @brief Returns the counter value of GPT peripheral. + * @pre The GPT unit must be running in continuous mode. + * @note The nature of the counter is not defined, it may count upward + * or downward, it could be continuously running or not. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @return The current counter value. + * @notapi + */ +#define gpt_lld_get_counter(gptp) \ + ((gptcnt_t)((gptp)->BFTM->CNTR / (ES32_CK_AHB_FREQUENCY / (gptp)->config->frequency))) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (ES32_GPT_USE_BFTM0 == TRUE) && !defined(__DOXYGEN__) + extern GPTDriver GPTD_BFTM0; +#endif +#if (ES32_GPT_USE_BFTM1 == TRUE) && !defined(__DOXYGEN__) + extern GPTDriver GPTD_BFTM1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void gpt_lld_init(void); +void gpt_lld_start(GPTDriver *gptp); +void gpt_lld_stop(GPTDriver *gptp); +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval); +void gpt_lld_stop_timer(GPTDriver *gptp); +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT == TRUE */ + +#endif /* HAL_GPT_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.c b/os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.c new file mode 100644 index 00000000000..c5f91996598 --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.c @@ -0,0 +1,673 @@ +/* + Copyright (C) 2020 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_pwm_lld.c + * @brief ES32 PWM subsystem low level driver source. + * + * @addtogroup PWM + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWM_AD16C4T1 driver identifier. + * @note The driver PWM_AD16C4T1 allocates the complex timer AD16C4T1 when enabled. + */ +#if ES32_PWM_USE_AD16C4T1 || defined(__DOXYGEN__) +PWMDriver PWM_AD16C4T1; +#endif + +/** + * @brief PWM_GP32C4T1 driver identifier. + * @note The driver PWM_GP32C4T1 allocates the timer GP32C4T1 when enabled. + */ +#if ES32_PWM_USE_GP32C4T1 || defined(__DOXYGEN__) +PWMDriver PWM_GP32C4T1; +#endif + +/** + * @brief PWM_GP16C4T1 driver identifier. + * @note The driver PWM_GP16C4T1 allocates the timer GP16C4T1 when enabled. + */ +#if ES32_PWM_USE_GP16C4T1 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C4T1; +#endif + +/** + * @brief PWM_GP16C4T2 driver identifier. + * @note The driver PWM_GP16C4T2 allocates the timer GP16C4T2 when enabled. + */ +#if ES32_PWM_USE_GP16C4T2 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C4T2; +#endif + +/** + * @brief PWM_GP16C4T3 driver identifier. + * @note The driver PWM_GP16C4T3 allocates the timer GP16C4T3 when enabled. + */ +#if ES32_PWM_USE_GP16C4T3 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C4T3; +#endif + +/** + * @brief PWM_GP16C2T1 driver identifier. + * @note The driver PWM_GP16C2T1 allocates the timer GP16C2T1 when enabled. + */ +#if ES32_PWM_USE_GP16C2T1 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C2T1; +#endif + +/** + * @brief PWM_GP16C2T2 driver identifier. + * @note The driver PWM_GP16C2T2 allocates the timer GP16C2T2 when enabled. + */ +#if ES32_PWM_USE_GP16C2T2 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C2T2; +#endif + +/** + * @brief PWM_GP16C2T3 driver identifier. + * @note The driver PWM_GP16C2T3 allocates the timer GP16C2T3 when enabled. + */ +#if ES32_PWM_USE_GP16C2T3 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C2T3; +#endif + +/** + * @brief PWM_GP16C2T4 driver identifier. + * @note The driver PWM_GP16C2T4 allocates the timer GP16C2T4 when enabled. + */ +#if ES32_PWM_USE_GP16C2T4 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C2T4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +#if ES32_PWM_USE_AD16C4T1 + /* Driver initialization.*/ + pwmObjectInit(&PWM_AD16C4T1); + PWM_AD16C4T1.channels = 4; + PWM_AD16C4T1.tim = AD16C4T1; + PWM_AD16C4T1.has_bdcfg = true; +#endif + +#if ES32_PWM_USE_GP32C4T1 + /* Driver initialization.*/ + pwmObjectInit(&PWM_GP32C4T1); + PWM_GP32C4T1.channels = 4; + PWM_GP32C4T1.tim = GP32C4T1; + PWM_GP32C4T1.has_bdcfg = false; +#endif + +#if ES32_PWM_USE_GP16C4T1 + /* Driver initialization.*/ + pwmObjectInit(&PWM_GP16C4T1); + PWM_GP16C4T1.channels = 4; + PWM_GP16C4T1.tim = GP16C4T1; + PWM_GP16C4T1.has_bdcfg = false; +#endif + +#if ES32_PWM_USE_GP16C4T2 + /* Driver initialization.*/ + pwmObjectInit(&PWM_GP16C4T2); + PWM_GP16C4T2.channels = 4; + PWM_GP16C4T2.tim = GP16C4T2; + PWM_GP16C4T2.has_bdcfg = false; +#endif + +#if ES32_PWM_USE_GP16C4T3 + /* Driver initialization.*/ + pwmObjectInit(&PWM_GP16C4T3); + PWM_GP16C4T3.channels = 4; + PWM_GP16C4T3.tim = GP16C4T3; + PWM_GP16C4T3.has_bdcfg = false; +#endif + +#if ES32_PWM_USE_GP16C2T1 + /* Driver initialization.*/ + pwmObjectInit(&PWM_GP16C2T1); + PWM_GP16C2T1.channels = 2; + PWM_GP16C2T1.tim = GP16C2T1; + PWM_GP16C2T1.has_bdcfg = true; +#endif + +#if ES32_PWM_USE_GP16C2T2 + /* Driver initialization.*/ + pwmObjectInit(&PWM_GP16C2T2); + PWM_GP16C2T2.channels = 2; + PWM_GP16C2T2.tim = GP16C2T2; + PWM_GP16C2T2.has_bdcfg = true; +#endif + +#if ES32_PWM_USE_GP16C2T3 + /* Driver initialization.*/ + pwmObjectInit(&PWM_GP16C2T3); + PWM_GP16C2T3.channels = 2; + PWM_GP16C2T3.tim = GP16C2T3; + PWM_GP16C2T3.has_bdcfg = true; +#endif + +#if ES32_PWM_USE_GP16C2T4 + /* Driver initialization.*/ + pwmObjectInit(&PWM_GP16C2T4); + PWM_GP16C2T4.channels = 2; + PWM_GP16C2T4.tim = GP16C2T4; + PWM_GP16C2T4.has_bdcfg = true; +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + uint32_t psc; + uint32_t ccer; + + if (pwmp->state == PWM_STOP) { + /* Clock activation and timer reset.*/ +#if ES32_PWM_USE_AD16C4T1 + if (&PWM_AD16C4T1 == pwmp) { + RCU->APB2EN |= RCU_APB2EN_AD16C4T1EN; + RCU->APB2RST |= RCU_APB2RST_AD16C4T1EN; + RCU->APB2RST &= ~RCU_APB2RST_AD16C4T1EN; + } +#endif + +#if ES32_PWM_USE_GP32C4T1 + if (&PWM_GP32C4T1 == pwmp) { + RCU->APB1EN |= RCU_APB1EN_GP32C4T1EN; + RCU->APB1RST |= RCU_APB1RST_GP32C4T1EN; + RCU->APB1RST &= ~RCU_APB1RST_GP32C4T1EN; + } +#endif + +#if ES32_PWM_USE_GP16C4T1 + if (&PWM_GP16C4T1 == pwmp) { + RCU->APB1EN |= RCU_APB1EN_GP16C4T1EN; + RCU->APB1RST |= RCU_APB1RST_GP16C4T1EN; + RCU->APB1RST &= ~RCU_APB1RST_GP16C4T1EN; + } +#endif + +#if ES32_PWM_USE_GP16C4T2 + if (&PWM_GP16C4T2 == pwmp) { + RCU->APB1EN |= RCU_APB1EN_GP16C4T2EN; + RCU->APB1RST |= RCU_APB1RST_GP16C4T2EN; + RCU->APB1RST &= ~RCU_APB1RST_GP16C4T2EN; + } +#endif + +#if ES32_PWM_USE_GP16C4T3 + if (&PWM_GP16C4T3 == pwmp) { + RCU->APB1EN |= RCU_APB1EN_GP16C4T3EN; + RCU->APB1RST |= RCU_APB1RST_GP16C4T3EN; + RCU->APB1RST &= ~RCU_APB1RST_GP16C4T3EN; + } +#endif + +#if ES32_PWM_USE_GP16C2T1 + if (&PWM_GP16C2T1 == pwmp) { + RCU->APB2EN |= RCU_APB2EN_GP16C2T1EN; + RCU->APB2RST |= RCU_APB2RST_GP16C2T1EN; + RCU->APB2RST &= ~RCU_APB2RST_GP16C2T1EN; + } +#endif + +#if ES32_PWM_USE_GP16C2T2 + if (&PWM_GP16C2T2 == pwmp) { + RCU->APB2EN |= RCU_APB2EN_GP16C2T2EN; + RCU->APB2RST |= RCU_APB2RST_GP16C2T2EN; + RCU->APB2RST &= ~RCU_APB2RST_GP16C2T2EN; + } +#endif + +#if ES32_PWM_USE_GP16C2T3 + if (&PWM_GP16C2T3 == pwmp) { + RCU->APB2EN |= RCU_APB2EN_GP16C2T3EN; + RCU->APB2RST |= RCU_APB2RST_GP16C2T3EN; + RCU->APB2RST &= ~RCU_APB2RST_GP16C2T3EN; + } +#endif + +#if ES32_PWM_USE_GP16C2T4 + if (&PWM_GP16C2T4 == pwmp) { + RCU->APB2EN |= RCU_APB2EN_GP16C2T4EN; + RCU->APB2RST |= RCU_APB2RST_GP16C2T4EN; + RCU->APB2RST &= ~RCU_APB2RST_GP16C2T4EN; + } +#endif + + /* All channels configured in PWM1 mode with preload enabled and will + stay that way until the driver is stopped.*/ + md_timer_set_output_compare1_mode_ch1mod(pwmp->tim, MD_TIMER_OUTPUTMODE_PWMMODE1); + md_timer_set_output_compare2_mode_ch2mod(pwmp->tim, MD_TIMER_OUTPUTMODE_PWMMODE1); + md_timer_set_output_compare3_mode_ch3mod(pwmp->tim, MD_TIMER_OUTPUTMODE_PWMMODE1); + md_timer_set_output_compare4_mode_ch4mod(pwmp->tim, MD_TIMER_OUTPUTMODE_PWMMODE1); + md_timer_enable_output_compare1_preload_ch1pen(pwmp->tim); + md_timer_enable_output_compare2_preload_ch2pen(pwmp->tim); + md_timer_enable_output_compare3_preload_ch3pen(pwmp->tim); + md_timer_enable_output_compare4_preload_ch4pen(pwmp->tim); + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + md_timer_set_con1(pwmp->tim, DISABLE); /* Timer disabled. */ + md_timer_set_capture_compare1_value_ccrv1(pwmp->tim, DISABLE); /* Comparator 1 disabled. */ + md_timer_set_capture_compare2_value_ccrv2(pwmp->tim, DISABLE); /* Comparator 2 disabled. */ + md_timer_set_capture_compare3_value_ccrv3(pwmp->tim, DISABLE); /* Comparator 3 disabled. */ + md_timer_set_capture_compare4_value_ccrv4(pwmp->tim, DISABLE); /* Comparator 4 disabled. */ + md_timer_set_counter_value_cntv(pwmp->tim, DISABLE); /* Counter reset to zero. */ + } + + /* Timer configuration.*/ + psc = (SystemFrequency_APBClk / pwmp->config->frequency) - 1; + md_timer_set_prescaler_value_pscv(pwmp->tim, psc); + md_timer_set_auto_reload_value_arrv(pwmp->tim, pwmp->period - 1); + md_timer_set_con2(pwmp->tim, pwmp->config->con2); + + /* Output enables and polarities setup.*/ + ccer = 0; + switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIMER_CCEP_CC1POL; + /* Falls through.*/ + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIMER_CCEP_CC1EN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIMER_CCEP_CC2POL; + /* Falls through.*/ + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIMER_CCEP_CC2EN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIMER_CCEP_CC3POL; + /* Falls through.*/ + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIMER_CCEP_CC3EN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + ccer |= TIMER_CCEP_CC4POL; + /* Falls through.*/ + case PWM_OUTPUT_ACTIVE_HIGH: + ccer |= TIMER_CCEP_CC4EN; + /* Falls through.*/ + default: + ; + } + if (pwmp->has_bdcfg) { + switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + ccer |= TIMER_CCEP_CC1NPOL; + /* Falls through.*/ + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + ccer |= TIMER_CCEP_CC1NEN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + ccer |= TIMER_CCEP_CC2NPOL; + /* Falls through.*/ + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + ccer |= TIMER_CCEP_CC2NEN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[2].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + ccer |= TIMER_CCEP_CC3NPOL; + /* Falls through.*/ + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH: + ccer |= TIMER_CCEP_CC3NEN; + /* Falls through.*/ + default: + ; + } + switch (pwmp->config->channels[3].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) { + case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW: + ccer |= TIMER_CCEP_CC4NPOL; + /* Falls through.*/ + default: + ; + } + } + + md_timer_set_ccep(pwmp->tim, ccer); + md_timer_set_sge(pwmp->tim, TIMER_SGE_SGUPD); /* Update event. */ + md_timer_set_icr(pwmp->tim, PWM_COMPLEMENTARY_INTERRUPT_MASK); /* Clear pending IRQs. */ + md_timer_set_dmaen(pwmp->tim, pwmp->config->dmaen); + + if (pwmp->has_bdcfg) { + md_timer_set_bdcfg(pwmp->tim, pwmp->config->bdcfg | TIMER_BDCFG_GOEN); + } + /* Timer configured and started.*/ + md_timer_set_con1(pwmp->tim, TIMER_CON1_ARPEN | TIMER_CON1_UERSEL | + TIMER_CON1_CNTEN); +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { + md_timer_set_con1(pwmp->tim, DISABLE); /* Timer disabled. */ + md_timer_set_idr(pwmp->tim, PWM_COMPLEMENTARY_INTERRUPT_MASK); /* All IRQs disabled. */ + md_timer_set_icr(pwmp->tim, PWM_COMPLEMENTARY_INTERRUPT_MASK); /* Clear eventual pending IRQs. */ + if (pwmp->has_bdcfg) { + md_timer_set_bdcfg(pwmp->tim, DISABLE); + } + +#if ES32_PWM_USE_AD16C4T1 + if (&PWM_AD16C4T1 == pwmp) { + RCU->APB2EN &= ~RCU_APB2EN_AD16C4T1EN; + } +#endif + +#if ES32_PWM_USE_GP32C4T1 + if (&PWM_GP32C4T1 == pwmp) { + RCU->APB1EN &= ~RCU_APB1EN_GP32C4T1EN; + } +#endif + +#if ES32_PWM_USE_GP16C4T1 + if (&PWM_GP16C4T1 == pwmp) { + RCU->APB1EN &= ~RCU_APB1EN_GP16C4T1EN; + } +#endif + +#if ES32_PWM_USE_GP16C4T2 + if (&PWM_GP16C4T2 == pwmp) { + RCU->APB1EN &= ~RCU_APB1EN_GP16C4T2EN; + } +#endif + +#if ES32_PWM_USE_GP16C4T3 + if (&PWM_GP16C4T3 == pwmp) { + RCU->APB1EN &= ~RCU_APB1EN_GP16C4T3EN; + } +#endif + +#if ES32_PWM_USE_GP16C2T1 + if (&PWM_GP16C2T1 == pwmp) { + RCU->APB2EN &= ~RCU_APB2EN_GP16C2T1EN; + } +#endif + +#if ES32_PWM_USE_GP16C2T2 + if (&PWM_GP16C2T2 == pwmp) { + RCU->APB2EN &= ~RCU_APB2EN_GP16C2T2EN; + } +#endif + +#if ES32_PWM_USE_GP16C2T3 + if (&PWM_GP16C2T3 == pwmp) { + RCU->APB2EN &= ~RCU_APB2EN_GP16C2T3EN; + } +#endif + +#if ES32_PWM_USE_GP16C2T4 + if (&PWM_GP16C2T4 == pwmp) { + RCU->APB2EN &= ~RCU_APB2EN_GP16C2T4EN; + } +#endif + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * @note Channel notification is not enabled. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + /* Changing channel duty cycle on the fly.*/ +#if PWM_CHANNELS <= 4 + switch(channel) + { + case 0: + md_timer_set_capture_compare1_value_ccrv1(pwmp->tim, width); + break; + case 1: + md_timer_set_capture_compare2_value_ccrv2(pwmp->tim, width); + break; + case 2: + md_timer_set_capture_compare3_value_ccrv3(pwmp->tim, width); + break; + case 3: + md_timer_set_capture_compare4_value_ccrv4(pwmp->tim, width); + break; + default: + break; + } +#endif +} + +/** + * @brief Disables a PWM channel and its notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + +#if PWM_CHANNELS <= 4 + switch(channel) + { + case 0: + md_timer_set_capture_compare1_value_ccrv1(pwmp->tim, DISABLE); + md_timer_disable_it_ch1(pwmp->tim); + break; + case 1: + md_timer_set_capture_compare2_value_ccrv2(pwmp->tim, DISABLE); + md_timer_disable_it_ch2(pwmp->tim); + break; + case 2: + md_timer_set_capture_compare3_value_ccrv3(pwmp->tim, DISABLE); + md_timer_disable_it_ch3(pwmp->tim); + break; + case 3: + md_timer_set_capture_compare4_value_ccrv4(pwmp->tim, DISABLE); + md_timer_disable_it_ch4(pwmp->tim); + break; + default: + break; + } +#endif +} + +/** + * @brief Enables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { + uint32_t intr_flag = md_timer_get_ivs(pwmp->tim); + + /* If the IRQ is not already enabled care must be taken to clear it, + it is probably already pending because the timer is running.*/ + if ((intr_flag & TIMER_IVS_UPD) == 0) { + md_timer_clear_it_upd(pwmp->tim); + md_timer_enable_it_upd(pwmp->tim); + } +} + +/** + * @brief Disables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { + + md_timer_disable_it_upd(pwmp->tim); +} + +/** + * @brief Enables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + uint32_t intr_flag = md_timer_get_ivs(pwmp->tim); + + /* If the IRQ is not already enabled care must be taken to clear it, + it is probably already pending because the timer is running.*/ + if ((intr_flag & (2 << channel)) == 0) { + md_timer_set_icr(pwmp->tim, 2 << channel); + md_timer_set_ier(pwmp->tim, intr_flag | (2 << channel)); + } +} + +/** + * @brief Disables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + + md_timer_set_idr(pwmp->tim, 2 << channel); +} + +/** + * @brief Common TIM2...TIM5,TIM9 IRQ handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + uint32_t intr_flag; + + intr_flag = md_timer_get_ifm(pwmp->tim); + md_timer_set_icr(pwmp->tim, intr_flag); + if (((intr_flag & TIMER_IFM_CH1) != 0) && + (pwmp->config->channels[0].callback != NULL)) + pwmp->config->channels[0].callback(pwmp); + if (((intr_flag & TIMER_IFM_CH2) != 0) && + (pwmp->config->channels[1].callback != NULL)) + pwmp->config->channels[1].callback(pwmp); + if (((intr_flag & TIMER_IFM_CH3) != 0) && + (pwmp->config->channels[2].callback != NULL)) + pwmp->config->channels[2].callback(pwmp); + if (((intr_flag & TIMER_IFM_CH4) != 0) && + (pwmp->config->channels[3].callback != NULL)) + pwmp->config->channels[3].callback(pwmp); + if (((intr_flag & TIMER_IFM_UPD) != 0) && (pwmp->config->callback != NULL)) + pwmp->config->callback(pwmp); +} + +#endif /* HAL_USE_PWM == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.h b/os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.h new file mode 100644 index 00000000000..9f10a4d1aaa --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv1/hal_pwm_lld.h @@ -0,0 +1,609 @@ +/* + Copyright (C) 2020 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_pwm_lld.h + * @brief ES32 PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef HAL_PWM_LLD_H +#define HAL_PWM_LLD_H + +#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__) + + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 4 + +/** + * @name ES32-specific PWM complementary output mode macros + * @{ + */ +/** + * @brief Complementary output modes mask. + * @note This is an ES32-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 + +/** + * @brief Complementary output not driven. + * @note This is an ES32-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 + +/** + * @brief Complementary output, active is logic level one. + * @note This is an ES32-specific setting. + * @note This setting is only available if the timer supports the + * BDTR register. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 + +/** + * @brief Complementary output, active is logic level zero. + * @note This is an ES32-specific setting. + * @note This setting is only available if the timer supports the + * BDTR register. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 + + +#define PWM_COMPLEMENTARY_INTERRUPT_MASK (TIMER_IFM_UPD | TIMER_IFM_CH1 | \ + TIMER_IFM_CH2 | TIMER_IFM_CH3 | \ + TIMER_IFM_CH4 | TIMER_IFM_COM | \ + TIMER_IFM_TRGI | TIMER_IFM_BRK | \ + TIMER_IFM_CH1OV| TIMER_IFM_CH2OV| \ + TIMER_IFM_CH3OV| TIMER_IFM_CH4OV) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief PWM_AD16C4T1 driver enable switch. + * @details If set to @p TRUE the support for PWM_AD16C4T1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_AD16C4T1) || defined(__DOXYGEN__) +#define ES32_PWM_USE_AD16C4T1 FALSE +#endif + +/** + * @brief PWM_GP32C4T1 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP32C4T1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP32C4T1) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP32C4T1 FALSE +#endif + +/** + * @brief PWM_GP16C4T1 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C4T1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C4T1) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C4T1 FALSE +#endif + +/** + * @brief PWM_GP16C4T2 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C4T2 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C4T2) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C4T2 FALSE +#endif + +/** + * @brief PWM_GP16C4T3 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C4T3 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C4T3) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C4T3 FALSE +#endif + +/** + * @brief PWM_GP16C2T1 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C2T1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C2T1) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C2T1 FALSE +#endif + +/** + * @brief PWM_GP16C2T2 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C2T2 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C2T2) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C2T2 FALSE +#endif + +/** + * @brief PWM_GP16C2T3 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C2T3 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C2T3) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C2T3 FALSE +#endif + +/** + * @brief PWM_GP16C2T4 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C2T4 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C2T4) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C2T4 FALSE +#endif + +/** + * @brief PWM_AD16C4T1 interrupt priority level setting. + */ +#if !defined(ES32_PWM_AD16C4T1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_AD16C4T1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP32C4T1 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP32C4T1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP32C4T1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C4T1 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C4T1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C4T1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C4T2 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C4T2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C4T2_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C4T3 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C4T3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C4T3_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C2T1 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C2T1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C2T1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C2T2 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C2T2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C2T2_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C2T3 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C2T3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C2T3_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C2T4 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C2T4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C2T4_IRQ_PRIORITY 7 +#endif + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + +#if !defined(ES32_HAS_AD16C4T1) +#define ES32_HAS_AD16C4T1 TRUE +#endif + +#if !defined(ES32_HAS_GP32C4T1) +#define ES32_HAS_GP32C4T1 TRUE +#endif + +#if !defined(ES32_HAS_GP16C4T1) +#define ES32_HAS_GP16C4T1 TRUE +#endif + +#if !defined(ES32_HAS_GP16C4T2) +#define ES32_HAS_GP16C4T2 TRUE +#endif + +#if !defined(ES32_HAS_GP16C4T3) +#define ES32_HAS_GP16C4T3 TRUE +#endif + +#if !defined(ES32_HAS_GP16C2T1) +#define ES32_HAS_GP16C2T1 TRUE +#endif + +#if !defined(ES32_HAS_GP16C2T2) +#define ES32_HAS_GP16C2T2 TRUE +#endif + +#if !defined(ES32_HAS_GP16C2T3) +#define ES32_HAS_GP16C2T3 TRUE +#endif + +#if !defined(ES32_HAS_GP16C2T4) +#define ES32_HAS_GP16C2T4 TRUE +#endif + +#if ES32_PWM_USE_AD16C4T1 && !ES32_HAS_AD16C4T1 +#error "AD16C4T1 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP32C4T1 && !ES32_HAS_GP32C4T1 +#error "GP32C4T1 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C4T1 && !ES32_HAS_GP16C4T1 +#error "GP16C4T1 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C4T2 && !ES32_HAS_GP16C4T2 +#error "GP16C4T2 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C4T3 && !ES32_HAS_GP16C4T3 +#error "GP16C4T3 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C2T1 && !ES32_HAS_GP16C2T1 +#error "GP16C2T1 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C2T2 && !ES32_HAS_GP16C2T2 +#error "GP16C2T2 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C2T3 && !ES32_HAS_GP16C2T3 +#error "GP16C2T3 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C2T4 && !ES32_HAS_GP16C2T4 +#error "GP16C2T4 not present in the selected device" +#endif + +#if !ES32_PWM_USE_AD16C4T1 && !ES32_PWM_USE_GP32C4T1 && \ + !ES32_PWM_USE_GP16C4T1 && !ES32_PWM_USE_GP16C4T2 && \ + !ES32_PWM_USE_GP16C4T3 && !ES32_PWM_USE_GP16C2T1 && \ + !ES32_PWM_USE_GP16C2T2 && !ES32_PWM_USE_GP16C2T3 && \ + !ES32_PWM_USE_GP16C2T4 +#error "PWM driver activated but no TIM peripheral assigned" +#endif + +/* Checks on allocation of TIMx units.*/ +#if ES32_PWM_USE_AD16C4T1 +#if defined(ES32_AD16C4T1_IS_USED) +#error "PWM_AD16C4T1 requires AD16C4T1 but the timer is already used" +#else +#define ES32_AD16C4T1_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP32C4T1 +#if defined(ES32_GP32C4T1_IS_USED) +#error "PWM_GP32C4T1 requires GP32C4T1 but the timer is already used" +#else +#define ES32_GP32C4T1_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C4T1 +#if defined(ES32_GP16C4T1_IS_USED) +#error "PWM_GP16C4T1 requires GP16C4T1 but the timer is already used" +#else +#define ES32_GP16C4T1_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C4T2 +#if defined(ES32_GP16C4T2_IS_USED) +#error "PWM_GP16C4T2 requires GP16C4T2 but the timer is already used" +#else +#define ES32_GP16C4T2_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C4T3 +#if defined(ES32_GP16C4T3_IS_USED) +#error "PWM_GP16C4T3 requires GP16C4T3 but the timer is already used" +#else +#define ES32_GP16C4T3_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C2T1 +#if defined(ES32_GP16C2T1_IS_USED) +#error "PWM_GP16C2T1 requires GP16C2T1 but the timer is already used" +#else +#define ES32_GP16C2T1_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C2T2 +#if defined(ES32_GP16C2T2_IS_USED) +#error "PWM_GP16C2T2 requires GP16C2T2 but the timer is already used" +#else +#define ES32_GP16C2T2_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C2T3 +#if defined(ES32_GP16C2T3_IS_USED) +#error "PWM_GP16C2T3 requires GP16C2T3 but the timer is already used" +#else +#define ES32_GP16C2T3_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C2T4 +#if defined(ES32_GP16C2T4_IS_USED) +#error "PWM_GP16C2T4 requires GP16C2T4 but the timer is already used" +#else +#define ES32_GP16C2T4_IS_USED +#endif +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a PWM mode. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief Type of a PWM channel. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief Type of a channels mask. + */ +typedef uint32_t pwmchnmsk_t; + +/** + * @brief Type of a PWM counter. + */ +typedef uint32_t pwmcnt_t; + +/** + * @brief Type of a PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Type of a PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief TIM CON2 register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint32_t con2; + /** + * @brief TIM BDCFG (break & dead-time) register initialization data. + * @note The value of this field should normally be equal to zero. + */ \ + uint32_t bdcfg; + /** + * @brief TIM DMAEN register initialization data. + * @note The value of this field should normally be equal to zero. + * @note Only the DMA-related bits can be specified in this field. + */ + uint32_t dmaen; +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; + /** + * @brief Mask of the enabled channels. + */ + pwmchnmsk_t enabled; + /** + * @brief Number of channels in this instance. + */ + pwmchannel_t channels; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + /* + uint32_t clock; + */ + /** + * @brief Presence of BDCFG register. + */ + bool has_bdcfg; + /** + * @brief Pointer to the TIMx registers block. + */ + TIMER_TypeDef *tim; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->tim->AR = ((period) - 1)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if ES32_PWM_USE_AD16C4T1 && !defined(__DOXYGEN__) +extern PWMDriver PWM_AD16C4T1; +#endif + +#if ES32_PWM_USE_GP32C4T1 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP32C4T1; +#endif + +#if ES32_PWM_USE_GP16C4T1 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C4T1; +#endif + +#if ES32_PWM_USE_GP16C4T2 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C4T2; +#endif + +#if ES32_PWM_USE_GP16C4T3 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C4T3; +#endif + +#if ES32_PWM_USE_GP16C2T1 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C2T1; +#endif + +#if ES32_PWM_USE_GP16C2T2 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C2T2; +#endif + +#if ES32_PWM_USE_GP16C2T3 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C2T3; +#endif + +#if ES32_PWM_USE_GP16C2T4 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C2T4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); + void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_serve_interrupt(PWMDriver *pwmp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM == TRUE */ + +#endif /* HAL_PWM_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.c b/os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.c new file mode 100644 index 00000000000..7e31a2a8e19 --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.c @@ -0,0 +1,92 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.c + * @brief PLATFORM ST subsystem low level driver source. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) +/** + * @brief System Timer vector. + * @details This interrupt is used for system tick in periodic mode. + * + * @isr + */ +OSAL_IRQ_HANDLER(SysTick_Handler) +{ + OSAL_IRQ_PROLOGUE(); + + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) +{ +#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) + SysTick->LOAD = 72000 - 1; + SysTick->CTRL = 0x10007; + +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.h b/os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.h new file mode 100644 index 00000000000..7ad6aaa86c8 --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv1/hal_st_lld.h @@ -0,0 +1,151 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under SYST_RVRthe License. +*/ + +/** + * @file hal_st_lld.h + * @brief PLATFORM ST subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +#include "mcuconf.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +void st_lld_init(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +#define SYST_CSR (*((volatile uint32_t*)0xE000E010)) +#define SYST_RVR (*((volatile uint32_t*)0xE000E014)) +#define SYST_CVR (*((volatile uint32_t*)0xE000E018)) +#define SYST_CALIB (*((volatile uint32_t*)0xE000E01C)) + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) +{ + return 0;//(systime_t) SYST_CVR; +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] abstime the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t abstime) +{ +// SYST_RVR = (uint32_t)abstime; +// SYST_CSR = 0b111; +// SYST_CVR = 0; // Trigger reload +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) +{ +// SYST_CVR &= ~((uint32_t)0b10); +} + +/** + * @brief Sets the alarm time. + * + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t abstime) +{ +// SYST_RVR = (uint32_t)abstime; +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) +{ + return 0;//(systime_t)SYST_RVR; +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) +{ + return 0;//((SYST_CVR & 0b10) != 0); +} + +#endif /* HAL_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/UARTv1/driver.mk b/os/hal/ports/ES32/LLD/UARTv1/driver.mk new file mode 100644 index 00000000000..fa61d5589da --- /dev/null +++ b/os/hal/ports/ES32/LLD/UARTv1/driver.mk @@ -0,0 +1,13 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c +endif +ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/UARTv1 diff --git a/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c b/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c new file mode 100644 index 00000000000..1a22d76c1ec --- /dev/null +++ b/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c @@ -0,0 +1,116 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_serial_lld.c + * @brief ES32 serial subsystem low level driver source. + * + * @addtogroup SERIAL + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = {SERIAL_DEFAULT_BITRATE}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void load(SerialDriver *sdp) +{ + (void)sdp; +} + +static void serialInterrupt(SerialDriver *pSd) +{ + (void)pSd; +} + +static void usartInit(SerialDriver *sdp, const SerialConfig *config) +{ + (void)sdp; + (void)config; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) +{ + +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) +{ + (void)sdp; + (void)config; +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) +{ + (void)sdp; +} + +#endif /* HAL_USE_SERIAL == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.h b/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.h new file mode 100644 index 00000000000..6ff1a2525fd --- /dev/null +++ b/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.h @@ -0,0 +1,128 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_serial_lld.h + * @brief PLATFORM serial subsystem low level driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef HAL_SERIAL_LLD_H +#define HAL_SERIAL_LLD_H + +#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief USART0 driver enable switch. + * @details If set to @p TRUE the support for USART0 is included. + * @note The default is @p FALSE. + */ +#if !defined(PLATFORM_SERIAL_USE_USART0) || defined(__DOXYGEN__) + #define PLATFORM_SERIAL_USE_USART0 FALSE +#endif + +#if !defined(PLATFORM_SERIAL_USE_USART1) || defined(__DOXYGEN__) + #define PLATFORM_SERIAL_USE_USART1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief PLATFORM Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct +{ + /** + * @brief Bit rate. + */ + uint32_t speed; + /* End of the mandatory fields.*/ +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + input_queue_t iqueue; \ + /* Output queue.*/ \ + output_queue_t oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + UART_TypeDef *usart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (ES32_SERIAL_USE_USART0 == TRUE) && !defined(__DOXYGEN__) + extern SerialDriver SD0; +#endif +#if (ES32_SERIAL_USE_USART1 == TRUE) && !defined(__DOXYGEN__) + extern SerialDriver SD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void sd_lld_init(void); +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); +void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL == TRUE */ + +#endif /* HAL_SERIAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.c b/os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.c new file mode 100644 index 00000000000..379446c94b5 --- /dev/null +++ b/os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.c @@ -0,0 +1,173 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_uart_lld.c + * @brief PLATFORM UART subsystem low level driver source. + * + * @addtogroup UART + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void uart_lld_handler(UARTDriver *uartp) +{ + +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) +{ + +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) +{ + + (void)uartp; + +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) +{ + (void)uartp; +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) +{ + + (void)uartp; + (void)n; + (void)txbuf; +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) +{ + + (void)uartp; + + return 0; +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) +{ + + (void)uartp; + (void)n; + (void)rxbuf; + +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) +{ + + (void)uartp; + + return 0; +} + +#endif /* HAL_USE_UART == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.h b/os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.h new file mode 100644 index 00000000000..7abfecc765a --- /dev/null +++ b/os/hal/ports/ES32/LLD/UARTv1/hal_uart_lld.h @@ -0,0 +1,231 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_uart_lld.h + * @brief PLATFORM UART subsystem low level driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef HAL_UART_LLD_H +#define HAL_UART_LLD_H + +#if (HAL_USE_UART == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief UART driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_UART_USE_UART0) || defined(__DOXYGEN__) + #define ES32_UART_USE_UART0 FALSE +#endif +#if !defined(ES32_UART_USE_UART1) || defined(__DOXYGEN__) + #define ES32_UART_USE_UART1 FALSE +#endif +#if !defined(ES32_UART_USE_USART0) || defined(__DOXYGEN__) + #define ES32_UART_USE_USART0 FALSE +#endif +#if !defined(ES32_UART_USE_USART1) || defined(__DOXYGEN__) + #define ES32_UART_USE_USART1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Type of structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object triggering the + * callback + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object triggering the + * callback + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct +{ + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + uint32_t fcr; + uint32_t lcr; + uint32_t mdr; + + /** + * @brief Baud rate. + */ + uint32_t baud; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +struct UARTDriver +{ + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Synchronization flag for transmit operations. + */ + bool early; + /** + * @brief Waiting thread on RX. + */ + thread_reference_t threadrx; + /** + * @brief Waiting thread on TX. + */ + thread_reference_t threadtx; +#endif /* UART_USE_WAIT */ +#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif /* UART_USE_MUTUAL_EXCLUSION */ +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + UART_TypeDef *UART; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (ES32_UART_USE_UART0 == TRUE) && !defined(__DOXYGEN__) + extern UARTDriver UARTD0; +#endif +#if (ES32_UART_USE_UART1 == TRUE) && !defined(__DOXYGEN__) + extern UARTDriver UARTD1; +#endif +#if (ES32_UART_USE_USART0 == TRUE) && !defined(__DOXYGEN__) + extern UARTDriver USARTD0; +#endif +#if (ES32_UART_USE_USART1 == TRUE) && !defined(__DOXYGEN__) + extern UARTDriver USARTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void uart_lld_init(void); +void uart_lld_start(UARTDriver *uartp); +void uart_lld_stop(UARTDriver *uartp); +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); +size_t uart_lld_stop_send(UARTDriver *uartp); +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); +size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART == TRUE */ + +#endif /* HAL_UART_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/USBv1/driver.mk b/os/hal/ports/ES32/LLD/USBv1/driver.mk new file mode 100644 index 00000000000..a6ede0b180f --- /dev/null +++ b/os/hal/ports/ES32/LLD/USBv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/USBv1 diff --git a/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c b/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c new file mode 100644 index 00000000000..20e24bea307 --- /dev/null +++ b/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c @@ -0,0 +1,1186 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_usb_lld.c + * @brief ES32 USB subsystem low level driver source. + * + * @addtogroup USB + * @{ + */ + +#include "hal.h" +#include "ald_usb.h" +#include "md_utils.h" + +#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) + +#define ES_USB_PERH_EP_MAX_INDEX (6U) + +#define USB_CTRL_EP_MPS 64 + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#define USB_EP_DIR_MASK 0x80U +#define USB_EP_DIR_IN 0x80U +#define USB_EP_DIR_OUT 0x00U + +/** Get endpoint index (number) from endpoint address */ +#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) +/** Get direction from endpoint address */ +#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) +/** Get endpoint address from endpoint index and direction */ +#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) +/** True if the endpoint is an IN endpoint */ +#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) +/** True if the endpoint is an OUT endpoint */ +#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) + + +extern char g_num_to_char_tx_buf[32]; +extern const char g_num_to_char_table[16]; +extern void ffffff(uint32_t data); + +/** + * @brief EP0 state. + * @note It is an union because IN and OUT endpoints are never used at the + * same time for EP0. + */ +static union { + /** + * @brief IN EP0 state. + */ + USBInEndpointState in; + /** + * @brief OUT EP0 state. + */ + USBOutEndpointState out; +} ep0_state; + +/** + * @brief Buffer for the EP0 setup packets. + */ +static uint8_t ep0setup_buffer[8]; + +/** + * @brief EP0 initialization structure. + */ +static const USBEndpointConfig ep0config = { + .ep_mode = USB_EP_MODE_TYPE_CTRL, + .setup_cb = _usb_ep0setup, + .in_cb = _usb_ep0in, + .out_cb = _usb_ep0out, + .in_maxsize = 0x40U, + .out_maxsize = 0x40U, + .in_state = &ep0_state.in, + .out_state = &ep0_state.out, + .ep_buffers = 1U, + .setup_buf = ep0setup_buffer +}; + +typedef enum { + USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */ + USB_EP0_STATE_IN_DATA = 0x1, /**< IN DATA */ + USB_EP0_STATE_OUT_DATA = 0x3, /**< OUT DATA */ + USB_EP0_STATE_IN_STATUS = 0x4, /**< IN status */ + USB_EP0_STATE_OUT_STATUS = 0x5, /**< OUT status */ + USB_EP0_STATE_IN_ZLP = 0x6, /**< OUT status */ + USB_EP0_STATE_STALL = 0x7, /**< STALL status */ +} ep0_state_t; + +/* Endpoint state */ +struct musb_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Setup packet definition used to read raw data from USB line */ +struct usb_setup_packet { + /** Request type. Bits 0:4 determine recipient, see + * \ref usb_request_recipient. Bits 5:6 determine type, see + * \ref usb_request_type. Bit 7 determines data transfer direction, see + * \ref usb_endpoint_direction. + */ + uint8_t bmRequestType; + + /** Request. If the type bits of bmRequestType are equal to + * \ref usb_request_type::LIBUSB_REQUEST_TYPE_STANDARD + * "USB_REQUEST_TYPE_STANDARD" then this field refers to + * \ref usb_standard_request. For other cases, use of this field is + * application-specific. */ + uint8_t bRequest; + + /** Value. Varies according to request */ + uint16_t wValue; + + /** Index. Varies according to request, typically used to pass an index + * or offset */ + uint16_t wIndex; + + /** Number of bytes to transfer */ + uint16_t wLength; +}; + +/* Driver state */ +struct musb_udc { + volatile uint8_t dev_addr; + volatile uint32_t fifo_size_offset; + __attribute__((aligned(32))) struct usb_setup_packet setup; + struct musb_ep_state in_ep[ES_USB_PERH_EP_MAX_INDEX + 1]; /*!< IN endpoint parameters*/ + struct musb_ep_state out_ep[ES_USB_PERH_EP_MAX_INDEX + 1]; /*!< OUT endpoint parameters */ +} g_musb_udc; + +struct musb_udc g_musb_udc; +static volatile uint8_t usb_ep0_state = USB_EP0_STATE_SETUP; +volatile bool zlp_flag = 0; + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief USB1 driver identifier. + */ + +USBDriver USBD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static uint32_t es_usbd_get_fifo_size16_log2_min8(uint16_t need_size, uint16_t *used) +{ + uint16_t size; + uint8_t i; + + for (i = 3; i <= 15; i++) + { + size = (1U << i); + if (need_size <= size) + { + *used = size; + return i; + } + } + + *used = 0; + return 0; +} + +static void es_usbd_ep_write_packet_8bit(uint8_t ep_idx, uint8_t *buffer, uint16_t len) +{ + uint32_t i; + uint8_t* buf8 = (uint8_t*)(((uint32_t)(&(USB->EP0FIFO))) + ((ep_idx) << 2)); + + for(i = 0;i < len;i++) + *buf8 = buffer[i]; +} + +static void es_usbd_ep_read_packet_8bit(uint8_t ep_idx, uint8_t *buffer, uint16_t len) +{ + uint32_t i; + uint8_t* buf8 = (uint8_t*)(((uint32_t)(&(USB->EP0FIFO))) + ((ep_idx) << 2)); + + for(i = 0;i < len;i++) + buffer[i] = *buf8; +} + +/* get current active ep */ +static inline uint8_t musb_get_active_ep(void) +{ + return USB->INDEX; +} + +/* set the active ep */ +static inline void musb_set_active_ep(uint8_t ep_index) +{ + USB->INDEX = ep_index; +} + +void ald_usb_fifo_config_set_no_assert(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags) +{ + USB->INDEX = ep_idx; + + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) { + USB->TXFIFO1 = (uint8_t)((addr & 0xFFFF) >> 3); + USB->TXFIFO2 |= (uint8_t)((((addr & 0xFFFF) >> 3) >> 8) & 0x0F); + USB->TXFIFO2 |= (uint8_t)(size << USB_TXFIFO2_MAXPKTSIZE_POSS); + + USB->CSR0L_TXCSRL |= (uint8_t)ALD_USB_TXCSRL_FLUSH; + } + else { + USB->RXFIFO1 = (uint8_t)((addr & 0xFFFF) >> 3); + USB->RXFIFO2 |= (uint8_t)((((addr & 0xFFFF) >> 3) >> 8) & 0x0F); + USB->RXFIFO2 |= (uint8_t)(size << USB_RXFIFO2_MAXPKTSIZE_POSS); + + USB->RXCSRL |= (uint8_t)ALD_USB_RXCSRL_FLUSH; + } + + return; +} + +int usbd_ep_set_stall(const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (ep_idx == 0x00) + usb_ep0_state = USB_EP0_STATE_STALL; + + if (USB_EP_DIR_IS_OUT(ep)) + ald_usb_dev_ep_stall(ep_idx,ALD_USB_EP_DEV_OUT); + else + ald_usb_dev_ep_stall(ep_idx,ALD_USB_EP_DEV_IN); + + musb_set_active_ep(old_ep_idx); + return 0; +} + +int usbd_ep_clear_stall(const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (USB_EP_DIR_IS_OUT(ep)) + ald_usb_dev_ep_stall_clear(ep_idx,ALD_USB_EP_DEV_OUT); + else + ald_usb_dev_ep_stall_clear(ep_idx,ALD_USB_EP_DEV_IN); + + musb_set_active_ep(old_ep_idx); + return 0; +} + +int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled) +{ + return 0; +} + +int es_usb_ep_out_data_avail(uint8_t ep_addr) +{ + return ald_usb_ep_data_avail(USB_EP_GET_IDX(ep_addr)); +} + +int usb_ep_out_data_avail(uint8_t ep_addr) +{ + uint16_t conut; + uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + conut = ald_usb_ep_data_avail(USB_EP_GET_IDX(ep_idx)); + + musb_set_active_ep(old_ep_idx); + + return conut; +} + +static inline uint32_t es_usbd_ep_tx_ready_state(uint8_t ep_addr) +{ + if (ep_addr == 0U) + { + if (USB->CSR0L_TXCSRL & ALD_USB_CSR0L_TXRDY) + return 1; + } + else + { + if (USB->CSR0L_TXCSRL & ALD_USB_TXCSRL_TXRDY) + return 2; + } + + return 0; +} + +int usb_ep_in_data_avail(uint8_t ep_addr) +{ + uint16_t old_ep_idx, length; + uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if(es_usbd_ep_tx_ready_state(ep_idx)) + length = 0; + else + { + if(ep_idx == 0) + length = 64; + else + length = USB->TXMAXP; + } + + musb_set_active_ep(old_ep_idx); + return length; +} + +int usb_ep_wait_in_data_avail(uint8_t ep_addr) +{ + uint32_t cnt; + + for (cnt = 0; cnt < 3000; cnt++){ + if (usb_ep_in_data_avail(ep_addr)) + return cnt; + } + return 0; +} + +int usbd_read_packet(uint8_t ep_addr, uint8_t *buffer, uint16_t len) +{ + uint16_t old_ep_idx, cnt; + uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + cnt = es_usb_ep_out_data_avail(ep_idx); + if (cnt) + { + cnt = MIN(cnt,len); + es_usbd_ep_read_packet_8bit(ep_idx, buffer, cnt); + USB->RXCSRL &= ~(ALD_USB_RXCSRL_OVERRUN | ALD_USB_RXCSRL_DATAERR | ALD_USB_RXCSRL_STALL| ALD_USB_RXCSRL_STALLED); + USB->RXCSRL &= ~(ALD_USB_RXCSRL_RXRDY); + } + + musb_set_active_ep(old_ep_idx); + return cnt; +} + +int usbd_write_packet(uint8_t ep_addr, uint8_t *buffer, uint16_t len) +{ + uint16_t old_ep_idx, cnt; + uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); + + if (!buffer && len){ + return -2; + } + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if((USB->CSR0L_TXCSRL) & USB_TXCSRL_UNDRUN_MSK) + USB->CSR0L_TXCSRL &= ~USB_TXCSRL_UNDRUN_MSK; + + if((USB->CSR0L_TXCSRL) & USB_TXCSRL_TXRDY_MSK) + { + musb_set_active_ep(old_ep_idx); + return -1; + } + + if (!len) + { + USB->CSR0L_TXCSRL |= USB_TXCSRL_TXRDY_MSK; + musb_set_active_ep(old_ep_idx); + return 0; + } + + cnt = usb_ep_in_data_avail(ep_idx); + if (cnt) + { + cnt = MIN(cnt, len); + es_usbd_ep_write_packet_8bit(ep_idx, buffer, cnt); + } + + USB->CSR0L_TXCSRL |= USB_TXCSRL_TXRDY_MSK; + + musb_set_active_ep(old_ep_idx); + return cnt; +} + +int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; +// uint32_t wait_cnt; + +// if(ep_idx == 1) +// { +// ep_idx = 1; +// } + + if (!g_musb_udc.in_ep[ep_idx].ep_enable) + return -2; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if((USB->CSR0L_TXCSRL) & USB_TXCSRL_TXRDY_MSK) + { + musb_set_active_ep(old_ep_idx); + return -3; + } + + g_musb_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_musb_udc.in_ep[ep_idx].xfer_len = data_len; + g_musb_udc.in_ep[ep_idx].actual_xfer_len = 0; + + USB->TXIER = 1U << ep_idx; + + if (data_len == 0) + { + if (ep_idx == 0x00) + { + if (g_musb_udc.setup.wLength == 0) + usb_ep0_state = USB_EP0_STATE_IN_STATUS; + else + usb_ep0_state = USB_EP0_STATE_IN_ZLP; + + USB->CSR0L_TXCSRL = (ALD_USB_CSR0L_TXRDY | ALD_USB_CSR0L_DATAEND); + } + else + { + USB->CSR0L_TXCSRL = ALD_USB_TXCSRL_TXRDY; + } + musb_set_active_ep(old_ep_idx); + return 0; + } + + if (!data) + return -1; + + data_len = MIN(data_len, g_musb_udc.in_ep[ep_idx].ep_mps); + + usbd_write_packet(ep_idx, (uint8_t *)data, data_len); + + if (ep_idx == 0x00) + { + usb_ep0_state = USB_EP0_STATE_IN_DATA; + + if (data_len < g_musb_udc.in_ep[ep_idx].ep_mps) + USB->CSR0L_TXCSRL = (ALD_USB_CSR0L_TXRDY | ALD_USB_CSR0L_DATAEND); + else + USB->CSR0L_TXCSRL = ALD_USB_CSR0L_TXRDY; + } + else + USB->CSR0L_TXCSRL = ALD_USB_TXCSRL_TXRDY; + + musb_set_active_ep(old_ep_idx); + + return 0; +} + +int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + if (!g_musb_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (data_len == 0) { + if (ep_idx == 0) { + usb_ep0_state = USB_EP0_STATE_SETUP; + } + musb_set_active_ep(old_ep_idx); + return 0; + } + + if (!data) { + return -1; + } + + g_musb_udc.out_ep[ep_idx].xfer_buf = data; + g_musb_udc.out_ep[ep_idx].xfer_len = data_len; + g_musb_udc.out_ep[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + usb_ep0_state = USB_EP0_STATE_OUT_DATA; + } else { + USB->RXIER = 1U << ep_idx; + } + musb_set_active_ep(old_ep_idx); + return 0; +} + +void handle_ep0(void) +{ + uint8_t ep0_status = USB->CSR0L_TXCSRL; + uint16_t read_count; + + if (ep0_status & ALD_USB_CSR0L_STALLED) { + USB->CSR0L_TXCSRL &= ~ALD_USB_CSR0L_STALLED; + usb_ep0_state = USB_EP0_STATE_SETUP; + return; + } + + if (ep0_status & ALD_USB_CSR0L_SETEND) { + USB->CSR0L_TXCSRL = ALD_USB_CSR0L_SETENDC; + } + + switch (usb_ep0_state) { + case USB_EP0_STATE_SETUP: + if (ep0_status & ALD_USB_CSR0L_RXRDY) { + read_count = es_usb_ep_out_data_avail(0x0); + + if (read_count != 8) { + return; + } + + usbd_read_packet(0, (uint8_t *)&g_musb_udc.setup, 8); + if (g_musb_udc.setup.wLength) { + USB->CSR0L_TXCSRL = ALD_USB_CSR0L_RXRDYC; + } else { + USB->CSR0L_TXCSRL = (ALD_USB_CSR0L_RXRDYC | ALD_USB_CSR0L_DATAEND); + } + + _usb_ep0setup(&USBD1, 0); + } + break; + + case USB_EP0_STATE_IN_DATA: + if (g_musb_udc.in_ep[0].xfer_len > g_musb_udc.in_ep[0].ep_mps) { + g_musb_udc.in_ep[0].actual_xfer_len += g_musb_udc.in_ep[0].ep_mps; + g_musb_udc.in_ep[0].xfer_len -= g_musb_udc.in_ep[0].ep_mps; + g_musb_udc.in_ep[0].xfer_buf += g_musb_udc.in_ep[0].ep_mps; + + usbd_ep_start_write(0, g_musb_udc.in_ep[0].xfer_buf, g_musb_udc.in_ep[0].xfer_len); + + } else { + g_musb_udc.in_ep[0].actual_xfer_len += g_musb_udc.in_ep[0].xfer_len; + g_musb_udc.in_ep[0].xfer_len = 0; + + _usb_ep0in(&USBD1, 0); + } + + break; + case USB_EP0_STATE_OUT_DATA: + if (ep0_status & ALD_USB_CSR0L_RXRDY) { + read_count = es_usb_ep_out_data_avail(0x0); + + usbd_read_packet(0, g_musb_udc.out_ep[0].xfer_buf, read_count); + g_musb_udc.out_ep[0].xfer_buf += read_count; + g_musb_udc.out_ep[0].actual_xfer_len += read_count; + + if (read_count < g_musb_udc.out_ep[0].ep_mps) { + + _usb_ep0out(&USBD1, 0); + + USB->CSR0L_TXCSRL = (ALD_USB_CSR0L_RXRDYC | ALD_USB_CSR0L_DATAEND); + usb_ep0_state = USB_EP0_STATE_IN_STATUS; + } else { + USB->CSR0L_TXCSRL = ALD_USB_CSR0L_RXRDYC; + } + } + break; + case USB_EP0_STATE_IN_STATUS: + case USB_EP0_STATE_IN_ZLP: + usb_ep0_state = USB_EP0_STATE_SETUP; + + _usb_ep0in(&USBD1, 0); + + break; + } +} + +const uint8_t __lowest_bit_bitmap[] = +{ + /* 00 */ 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 10 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 20 */ 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 30 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 40 */ 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 50 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 60 */ 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 70 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 80 */ 7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* 90 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* A0 */ 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* B0 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* C0 */ 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* D0 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* E0 */ 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, + /* F0 */ 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0 +}; + +/*===========================================================================*/ +/* Driver interrupt handlers and threads. */ +/*===========================================================================*/ + +/** + * @brief USB interrupt handler. + * @isr + */ +OSAL_IRQ_HANDLER(VectorBC) +{ + volatile uint32_t i; + uint8_t old_ep_idx; + uint8_t ep_idx; + uint16_t write_count, read_count; + uint8_t status; + + USBDriver *usbp = &USBD1; + + OSAL_IRQ_PROLOGUE(); + + status = USB->IFM & 0x7F; + USB->ICR = status; + + old_ep_idx = musb_get_active_ep(); + + /* Receive a reset signal from the USB bus */ + if (status & USB_IFM_RESTIFM_MSK) + { + for(i = 0;i < 9999;i++){} + + //md_delay_1us(20); + + memset(&g_musb_udc, 0, sizeof(struct musb_udc)); + g_musb_udc.fifo_size_offset = USB_CTRL_EP_MPS; + + usb_ep0_state = USB_EP0_STATE_SETUP; + + USBD1.epc[0] = &ep0config; + g_musb_udc.in_ep[0].ep_enable = 1; + g_musb_udc.out_ep[0].ep_enable = 1; + g_musb_udc.in_ep[0].ep_mps = 64; ; + g_musb_udc.out_ep[0].ep_mps = 64; + + _usb_reset(usbp); + } + + if (status & (USB_IFM_SOFIFM_MSK)) + { +// _usb_isr_invoke_sof_cb(usbp); + } + + if (status & USB_IFM_RESIFM_MSK) + { + } + + if (status & USB_IFM_SESREQIFM_MSK) + { + } + + if (status & USB_IFM_DISCONIFM_MSK) + { + } + + if (status & USB_IFM_SUSPDIFM_MSK) + { +// _usb_suspend(usbp); + } + + while (USB->TXIFM) + { + ep_idx = __lowest_bit_bitmap[USB->TXIFM]; + USB->TXICR = 1U << ep_idx; + musb_set_active_ep(ep_idx); + + if(ep_idx == 0U) + handle_ep0(); + else + { + if((USB->CSR0L_TXCSRL) & USB_TXCSRL_UNDRUN_MSK) + USB->CSR0L_TXCSRL &= ~USB_TXCSRL_UNDRUN_MSK; + + if(g_musb_udc.in_ep[ep_idx].xfer_len) + { + if (g_musb_udc.in_ep[ep_idx].xfer_len > g_musb_udc.in_ep[ep_idx].ep_mps) + { + g_musb_udc.in_ep[ep_idx].xfer_buf += g_musb_udc.in_ep[ep_idx].ep_mps; + g_musb_udc.in_ep[ep_idx].actual_xfer_len += g_musb_udc.in_ep[ep_idx].ep_mps; + g_musb_udc.in_ep[ep_idx].xfer_len -= g_musb_udc.in_ep[ep_idx].ep_mps; + } + else + { + g_musb_udc.in_ep[ep_idx].xfer_buf += g_musb_udc.in_ep[ep_idx].xfer_len; + g_musb_udc.in_ep[ep_idx].actual_xfer_len += g_musb_udc.in_ep[ep_idx].xfer_len; + g_musb_udc.in_ep[ep_idx].xfer_len = 0; + } + } + + if (g_musb_udc.in_ep[ep_idx].xfer_len == 0) + { + USB->TXIDR = 1U << ep_idx; + + /* Transfer completed, invokes the callback.*/ + usbp->epc[ep_idx]->in_state->txcnt = g_musb_udc.in_ep[ep_idx].actual_xfer_len; + _usb_isr_invoke_in_cb(usbp, ep_idx); + } + else + { + write_count = MIN(g_musb_udc.in_ep[ep_idx].xfer_len, g_musb_udc.in_ep[ep_idx].ep_mps); + + usbd_write_packet(ep_idx, g_musb_udc.in_ep[ep_idx].xfer_buf, write_count); + } + } + } + + while (USB->RXIFM) + { + ep_idx = __lowest_bit_bitmap[USB->RXIFM]; + USB->RXICR = 1U << ep_idx; + musb_set_active_ep(ep_idx); + + if((USB->RXCSRL) & USB_RXCSRL_RXRDY_MSK) + { + read_count = es_usb_ep_out_data_avail(ep_idx); + + if(read_count <= g_musb_udc.out_ep[ep_idx].xfer_len) + { + es_usbd_ep_read_packet_8bit(ep_idx, g_musb_udc.out_ep[ep_idx].xfer_buf, read_count); + + g_musb_udc.out_ep[ep_idx].xfer_buf += read_count; + g_musb_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_musb_udc.out_ep[ep_idx].xfer_len -= read_count; + + + USB->RXCSRL &= ~(ALD_USB_RXCSRL_OVERRUN | ALD_USB_RXCSRL_DATAERR | ALD_USB_RXCSRL_STALL| ALD_USB_RXCSRL_STALLED); + USB->RXCSRL &= ~USB_RXCSRL_RXRDY_MSK; + } + /*else + USB_LOG_ERR("[ep %d]read_count(%d) > xfer_len(%d)\r\n",ep_idx,read_count,g_musb_udc.out_ep[ep_idx].xfer_len);*/ + + + if ((read_count < g_musb_udc.out_ep[ep_idx].ep_mps) || (g_musb_udc.out_ep[ep_idx].xfer_len < g_musb_udc.out_ep[ep_idx].ep_mps)) + { + USB->RXIDR = 1U << ep_idx; + /* Transfer complete, invokes the callback.*/ + usbp->epc[ep_idx]->out_state->rxcnt = g_musb_udc.out_ep[ep_idx].actual_xfer_len; + _usb_isr_invoke_out_cb(usbp, ep_idx); + } + } + } + + musb_set_active_ep(old_ep_idx); + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level USB driver initialization. + * + * @notapi + */ +void usb_lld_init(void) +{ + /* Driver initialization.*/ + usbObjectInit(&USBD1); + g_musb_udc.in_ep[0].ep_enable = 1; + g_musb_udc.out_ep[0].ep_enable = 1; + g_musb_udc.in_ep[0].ep_mps = 64; ; + g_musb_udc.out_ep[0].ep_mps = 64; + + USBD1.epc[0] = &ep0config; +} + +/** + * @brief Configures and activates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_start(USBDriver *usbp) +{ + volatile uint32_t i; + + if (usbp->state == USB_STOP) + { + ald_usb_device_components_init(); + + for(i = 0;i < 9999;i++){} + + ald_usb_int_status_get(); + ald_usb_int_status_ep_get(); + + /* Enable software connect */ + for(i = 0;i < 9999;i++){} + + + /* Enable USB interrupts */ + ald_usb_int_enable(ALD_USB_INTCTRL_RESET | ALD_USB_INTCTRL_DISCONNECT | ALD_USB_INTCTRL_RESUME |ALD_USB_INTCTRL_SUSPEND);/*未开启SOF中断*/ + ald_usb_int_enable_ep(ALD_USB_INTEP_ALL); + ald_usb_int_register(); + } + +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_stop(USBDriver *usbp) +{ + if (usbp->state != USB_STOP) + { + ald_usb_int_unregister(); + } +} + +/** + * @brief USB low level reset routine. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_reset(USBDriver *usbp) +{ + /* EP0 initialization.*/ + usbp->epc[0] = &ep0config; + g_musb_udc.in_ep[0].ep_enable = 1; + g_musb_udc.out_ep[0].ep_enable = 1; + g_musb_udc.in_ep[0].ep_mps = 64; ; + g_musb_udc.out_ep[0].ep_mps = 64; +} + +/** + * @brief Sets the USB address. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_set_address(USBDriver *usbp) +{ + volatile uint32_t i; + + for(i = 0;i < 9999;i++){} + + USB->FADDR = usbp->address; +} + +/** + * @brief Enables an endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) +{ + const USBEndpointConfig *epcp = usbp->epc[ep]; + + uint16_t used = 0; + uint16_t fifo_index = 0; + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + uint32_t ep_conf_flags = 0; + + if (ep == 0) { + g_musb_udc.out_ep[0].ep_mps = USB_CTRL_EP_MPS; + g_musb_udc.out_ep[0].ep_type = 0x00; + g_musb_udc.out_ep[0].ep_enable = true; + g_musb_udc.in_ep[0].ep_mps = USB_CTRL_EP_MPS; + g_musb_udc.in_ep[0].ep_type = 0x00; + g_musb_udc.in_ep[0].ep_enable = true; + return; + } + + if (ep_idx > (ES_USB_PERH_EP_MAX_INDEX)) { + es_test_printf("Ep addr overflow\r\n",sizeof("Ep addr overflow\r\n")); + return; + } + + switch (epcp->ep_mode & USB_EP_MODE_TYPE) +{ + case USB_EP_MODE_TYPE_BULK: + ep_conf_flags |= ALD_USB_EP_MODE_BULK; + break; + case USB_EP_MODE_TYPE_INTR: + ep_conf_flags |= ALD_USB_EP_MODE_INT; + break; + case USB_EP_MODE_TYPE_ISOC: + ep_conf_flags |= ALD_USB_EP_MODE_ISOC; + break; + default: + ep_conf_flags |= ALD_USB_EP_MODE_CTRL; + break; + } + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (epcp->out_state != NULL) + { + g_musb_udc.out_ep[ep_idx].ep_mps = epcp->out_maxsize; + g_musb_udc.out_ep[ep_idx].ep_type = (epcp->ep_mode) & USB_EP_MODE_TYPE; + g_musb_udc.out_ep[ep_idx].ep_enable = true; + + ep_conf_flags |= ALD_USB_EP_DEV_OUT; + + ald_usb_dev_ep_config(ep_idx , epcp->out_maxsize , ep_conf_flags); + fifo_index = es_usbd_get_fifo_size16_log2_min8(epcp->out_maxsize , &used); + } + + if (epcp->in_state != NULL) + { + g_musb_udc.in_ep[ep_idx].ep_mps = epcp->in_maxsize; + g_musb_udc.in_ep[ep_idx].ep_type = (epcp->ep_mode) & USB_EP_MODE_TYPE; + g_musb_udc.in_ep[ep_idx].ep_enable = true; + + ep_conf_flags |= ALD_USB_EP_DEV_IN; + + ald_usb_dev_ep_config(ep_idx , epcp->in_maxsize , ep_conf_flags); + fifo_index = es_usbd_get_fifo_size16_log2_min8(epcp->in_maxsize , &used); + } + + if((10 >= fifo_index)) + { + fifo_index -= 3; + + if (epcp->out_state != NULL) + ald_usb_fifo_config_set_no_assert(ep_idx , g_musb_udc.fifo_size_offset , fifo_index , ALD_USB_EP_DEV_OUT); + + if (epcp->in_state != NULL) + ald_usb_fifo_config_set_no_assert(ep_idx , g_musb_udc.fifo_size_offset , fifo_index , ALD_USB_EP_DEV_IN); + } + + g_musb_udc.fifo_size_offset += used; + + musb_set_active_ep(old_ep_idx); +} + +/** + * @brief Disables all the active endpoints except the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_disable_endpoints(USBDriver *usbp) +{ + es_test_printf("usb_lld_disable_endpoints\r\n",sizeof("usb_lld_disable_endpoints\r\n")); +} + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) +{ + + es_test_printf("usb_lld_get_status_out\r\n",sizeof("usb_lld_get_status_out\r\n")); + + return EP_STATUS_ACTIVE; +} + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) +{ + es_test_printf("usb_lld_get_status_in\r\n",sizeof("usb_lld_get_status_in\r\n")); + + return EP_STATUS_ACTIVE; +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @notapi + */ +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) +{ + uint8_t i,*setup_buf; + + setup_buf = (uint8_t *)(&g_musb_udc.setup); + + for(i = 0;i < 8;i++) + buf[i] = setup_buf[i]; +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep) +{ + USBOutEndpointState *osp = usbp->epc[ep]->out_state; + usbd_ep_start_read(ep,osp->rxbuf,osp->rxsize); +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep) +{ + USBInEndpointState *isp = usbp->epc[ep]->in_state; + usbd_ep_start_write(ep,isp->txbuf,isp->txsize); +} + +/** + * @brief Brings an OUT endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (ep_idx == 0x00) + usb_ep0_state = USB_EP0_STATE_STALL; + + ald_usb_dev_ep_stall(ep_idx,ALD_USB_EP_DEV_OUT); + + musb_set_active_ep(old_ep_idx); +} + +/** + * @brief Brings an IN endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (ep_idx == 0x00) + usb_ep0_state = USB_EP0_STATE_STALL; + + ald_usb_dev_ep_stall(ep_idx,ALD_USB_EP_DEV_IN); + + musb_set_active_ep(old_ep_idx); +} + +/** + * @brief Brings an OUT endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + ald_usb_dev_ep_stall_clear(ep_idx,ALD_USB_EP_DEV_OUT); + + musb_set_active_ep(old_ep_idx); +} + +/** + * @brief Brings an IN endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + ald_usb_dev_ep_stall_clear(ep_idx,ALD_USB_EP_DEV_IN); + + musb_set_active_ep(old_ep_idx); +} + +void usb_lld_end_setup(USBDriver *usbp, usbep_t ep) +{ + +} + +#endif /* HAL_USE_USB == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.h b/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.h new file mode 100644 index 00000000000..6bc3988e0e9 --- /dev/null +++ b/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.h @@ -0,0 +1,398 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_usb_lld.h + * @brief ES32 USB subsystem low level driver header. + * + * @addtogroup USB + * @{ + */ + +#ifndef HAL_USB_LLD_H +#define HAL_USB_LLD_H + +#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Maximum endpoint address. + */ +#define USB_MAX_ENDPOINTS 7 + +/** + * @brief Status stage handling method. + */ +#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW + +/** + * @brief The address can be changed immediately upon packet reception. + */ +#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS + +/** + * @brief Method for set address acknowledge. + */ +#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW + +extern int es_test_printf(char *pBuffer, int size); +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an IN endpoint state structure. + */ +typedef struct +{ + /** + * @brief Requested transmit transfer size. + */ + uint32_t txsize; + /** + * @brief Transmitted bytes so far. + */ + uint32_t txcnt; + /** + * @brief Pointer to the transmission linear buffer. + */ + const uint8_t *txbuf; +#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif + /* End of the mandatory fields.*/ + uint16_t txlastpktlen; +} USBInEndpointState; + +/** + * @brief Type of an OUT endpoint state structure. + */ +typedef struct +{ + /** + * @brief Requested receive transfer size. + */ + size_t rxsize; + /** + * @brief Received bytes so far. + */ + size_t rxcnt; + /** + * @brief Pointer to the receive linear buffer. + */ + uint8_t *rxbuf; +#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif + /* End of the mandatory fields.*/ + uint16_t rxpkts; +} USBOutEndpointState; + +/** + * @brief Type of an USB endpoint configuration structure. + * @note Platform specific restrictions may apply to endpoints. + */ +typedef struct +{ + /** + * @brief Type and mode of the endpoint. + */ + uint32_t ep_mode; + /** + * @brief Setup packet notification callback. + * @details This callback is invoked when a setup packet has been + * received. + * @post The application must immediately call @p usbReadPacket() in + * order to access the received packet. + * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL + * endpoints, it should be set to @p NULL for other endpoint + * types. + */ + usbepcallback_t setup_cb; + /** + * @brief IN endpoint notification callback. + * @details This field must be set to @p NULL if the IN endpoint is not + * used. + */ + usbepcallback_t in_cb; + /** + * @brief OUT endpoint notification callback. + * @details This field must be set to @p NULL if the OUT endpoint is not + * used. + */ + usbepcallback_t out_cb; + /** + * @brief IN endpoint maximum packet size. + * @details This field must be set to zero if the IN endpoint is not + * used. + */ + uint16_t in_maxsize; + /** + * @brief OUT endpoint maximum packet size. + * @details This field must be set to zero if the OUT endpoint is not + * used. + */ + uint16_t out_maxsize; + /** + * @brief @p USBEndpointState associated to the IN endpoint. + * @details This structure maintains the state of the IN endpoint. + */ + USBInEndpointState *in_state; + /** + * @brief @p USBEndpointState associated to the OUT endpoint. + * @details This structure maintains the state of the OUT endpoint. + */ + USBOutEndpointState *out_state; + /* End of the mandatory fields.*/ + /** + * @brief Reserved field, not currently used. + * @note Initialize this field to 1 in order to be forward compatible. + */ + uint16_t ep_buffers; + /** + * @brief Pointer to a buffer for setup packets. + * @details Setup packets require a dedicated 8-bytes buffer, set this + * field to @p NULL for non-control endpoints. + */ + uint8_t *setup_buf; +} USBEndpointConfig; + +/** + * @brief Type of an USB driver configuration structure. + */ +typedef struct +{ + /** + * @brief USB events callback. + * @details This callback is invoked when an USB driver event is registered. + */ + usbeventcb_t event_cb; + /** + * @brief Device GET_DESCRIPTOR request callback. + * @note This callback is mandatory and cannot be set to @p NULL. + */ + usbgetdescriptor_t get_descriptor_cb; + /** + * @brief Requests hook callback. + * @details This hook allows to be notified of standard requests or to + * handle non standard requests. + */ + usbreqhandler_t requests_hook_cb; + /** + * @brief Start Of Frame callback. + */ + usbcallback_t sof_cb; + /* End of the mandatory fields.*/ +} USBConfig; + +/** + * @brief Structure representing an USB driver. + */ +struct USBDriver +{ + /** + * @brief Driver state. + */ + usbstate_t state; + /** + * @brief Current configuration data. + */ + const USBConfig *config; + /** + * @brief Bit map of the transmitting IN endpoints. + */ + uint16_t transmitting; + /** + * @brief Bit map of the receiving OUT endpoints. + */ + uint16_t receiving; + /** + * @brief Active endpoints configurations. + */ + const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an IN endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *in_params[USB_MAX_ENDPOINTS]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an OUT endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *out_params[USB_MAX_ENDPOINTS]; + /** + * @brief Endpoint 0 state. + */ + usbep0state_t ep0state; + /** + * @brief Next position in the buffer to be transferred through endpoint 0. + */ + uint8_t *ep0next; + /** + * @brief Number of bytes yet to be transferred through endpoint 0. + */ + size_t ep0n; + /** + * @brief Endpoint 0 end transaction callback. + */ + usbcallback_t ep0endcb; + /** + * @brief Setup packet buffer. + */ + uint8_t setup[8]; + /** + * @brief Current USB device status. + */ + uint16_t status; + /** + * @brief Assigned USB address. + */ + uint8_t address; + /** + * @brief Current USB device configuration. + */ + uint8_t configuration; + /** + * @brief State of the driver when a suspend happened. + */ + usbstate_t saved_state; +#if defined(USB_DRIVER_EXT_FIELDS) + USB_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + uint16_t epmem_next; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current frame number. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The current frame number. + * + * @notapi + */ +#define usb_lld_get_frame_number(usbp) ( ) + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_transaction_size(usbp, ep) \ + ((usbp)->epc[ep]->out_state->rxcnt) + +/** + * @brief Connects the USB device. + * + * @api + */ +#define usb_lld_connect_bus(usbp) \ + do { \ + ald_usb_dev_connect(); \ + } while (FALSE) + +/** + * @brief Disconnect the USB device. + * + * @api + */ +#define usb_lld_disconnect_bus(usbp) \ + do { \ + ald_usb_dev_disconnect(); \ + } while (FALSE) + +/** + * @brief Start of host wake-up procedure. + * + * @notapi + */ +#define usb_lld_wakeup_host(usbp) \ + do { \ + \ + } while (FALSE) + + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + + +extern USBDriver USBD1; + + +#ifdef __cplusplus +extern "C" { +#endif +void usb_lld_init(void); +void usb_lld_start(USBDriver *usbp); +void usb_lld_stop(USBDriver *usbp); +void usb_lld_reset(USBDriver *usbp); +void usb_lld_set_address(USBDriver *usbp); +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); +void usb_lld_disable_endpoints(USBDriver *usbp); +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); +void usb_lld_start_out(USBDriver *usbp, usbep_t ep); +void usb_lld_start_in(USBDriver *usbp, usbep_t ep); +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB == TRUE */ + +#endif /* HAL_USB_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/WDTv1/driver.mk b/os/hal/ports/ES32/LLD/WDTv1/driver.mk new file mode 100644 index 00000000000..f8dac9f39e2 --- /dev/null +++ b/os/hal/ports/ES32/LLD/WDTv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/WDTv1 diff --git a/os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.c b/os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.c new file mode 100644 index 00000000000..0cce53804eb --- /dev/null +++ b/os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.c @@ -0,0 +1,137 @@ +/* + Copyright (C) 2022 Hansem Ro + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file WDT/hal_wdg_lld.c + * @brief WDG Driver subsystem low level driver source. + * + * @addtogroup WDG + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if ES32_WDG_USE_WDT || defined(__DOXYGEN__) + WDGDriver WDGD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level WDG driver initialization. + * + * @notapi + */ +void wdg_lld_init(void) +{ +#if ES32_WDG_USE_WDT + WDGD1.state = WDG_STOP; + WDGD1.wdg = WDT; +#endif +} + +/** + * @brief Configures and activates the WDG peripheral. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_start(WDGDriver *wdgp) +{ + if (~(wdgp->wdg->CSR & WDT_CSR_WDTLOCK)) + { + /* Enable WDT clock and disable write protect lock.*/ + CKCU->APBCCR1 |= CKCU_APBCCR1_WDTREN; + wdgp->wdg->PR = WDT_DISABLE_PROTECT_KEY; + + /* Write configuration.*/ + wdgp->wdg->MR0 = wdgp->config->mr0 & ~WDT_MR0_WDTEN; + wdgp->wdg->MR1 = wdgp->config->mr1; +#if ES32_WDG_USE_LSE == TRUE + wdgp->wdg->CSR = WDT_CSR_WDTSRC_LSE; +#else + wdgp->wdg->CSR = WDT_CSR_WDTSRC_LSI; +#endif + CKCU->MCUDBGCR &= ~CKCU_MCUDBGCR_DBWDT; + CKCU->MCUDBGCR |= wdgp->config->dbwdt; + + /* Start.*/ + wdgp->wdg->MR0 |= WDT_MR0_WDTEN; + + /* Enable write protect lock.*/ + wdgp->wdg->PR = 0; + } +} + +/** + * @brief Deactivates the WDG peripheral. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_stop(WDGDriver *wdgp) +{ + if (wdgp->state == WDG_READY) + { + /* Disable write protect lock and stop WDT.*/ + wdgp->wdg->PR = WDT_DISABLE_PROTECT_KEY; + wdgp->wdg->MR0 &= ~WDT_MR0_WDTEN; + /* Enable write protect lock.*/ + wdgp->wdg->PR = 0; + } +} + +/** + * @brief Reloads WDG's counter. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_reset(WDGDriver *wdgp) +{ + wdgp->wdg->CR = (WDT_RELOAD_KEY | WDT_CR_WDTRS); +} + +#endif /* HAL_USE_WDG == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.h b/os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.h new file mode 100644 index 00000000000..ff67fb22902 --- /dev/null +++ b/os/hal/ports/ES32/LLD/WDTv1/hal_wdg_lld.h @@ -0,0 +1,150 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + - Copyright (C) 2022 Hansem Ro + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file WDT/hal_wdg_lld.h + * @brief WDG Driver subsystem low level driver header. + * + * @addtogroup WDG + * @{ + */ + +#ifndef HAL_WDG_LLD_H +#define HAL_WDG_LLD_H + +#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +//Watchdog register keys +#define WDT_RELOAD_KEY (0x5af0U << 16) +#define WDT_DISABLE_PROTECT_KEY 0x35ca + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief WDT driver enable switch. + * @details If set to @p TRUE the support for WDT is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_WDG_USE_WDT) || defined(__DOXYGEN__) + #define ES32_WDG_USE_WDT FALSE +#endif + +#if ES32_WDG_USE_LSE != TRUE + #define ES32_WDG_USE_LSI TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !ES32_WDG_USE_WDT + #error "WDG driver activated but no WDT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an WDG driver. + */ +typedef struct WDGDriver WDGDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct +{ + /** + * @brief Configuration of the WDTMR0 register. + * @details See the ES32 reference manual for details. + */ + uint32_t mr0; + /** + * @brief Configuration of the WDTMR1 register. + * @details See the ES32 reference manual for details. + */ + uint32_t mr1; + /** + * @brief Configuration of the DBWDT bit in CKCU:MCUDBGCR register. + * @details See the ES32 reference manual for details. + */ + bool dbwdt; +} WDGConfig; + +/** + * @brief Structure representing an WDG driver. + */ +struct WDGDriver +{ + /** + * @brief Driver state. + */ + wdgstate_t state; + /** + * @brief Current configuration data. + */ + const WDGConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the WDT registers block. + */ + WDT_TypeDef *wdg; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if ES32_WDG_USE_WDT && !defined(__DOXYGEN__) + extern WDGDriver WDGD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void wdg_lld_init(void); +void wdg_lld_start(WDGDriver *wdgp); +void wdg_lld_stop(WDGDriver *wdgp); +void wdg_lld_reset(WDGDriver *wdgp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_WDG == TRUE */ + +#endif /* HAL_WDG_LLD_H */ + +/** @} */ diff --git a/testhal/ES32/.keep b/testhal/ES32/.keep new file mode 100644 index 00000000000..e69de29bb2d