From cd91c87a7d78270236b9a4fdfc28c2e8c39f0c84 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Tue, 13 Feb 2024 15:29:52 +0700 Subject: [PATCH] Added test HAL and added missing IOMUX define * Added missing define register for IOMUX REMAP2/3/4/5/6/7/8 * Added USB_CDC for testing HAL * Update years on copyright * Change Systick Resolution from 16 to 32 on USB_CDC test * Added PWM-ICU for testing HAL * Missing Pin A0 for User key button --- {testhal => demos}/AT32/.keep | 0 .../ext/CMSIS/ArteryTek/AT32F415/at32f415.h | 2 +- .../ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h | 269 ++++-- .../ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h | 245 ++++-- .../ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h | 274 ++++-- .../ArteryTek/AT32F415/system_at32f415.h | 2 +- .../ARMCMx/compilers/GCC/ld/AT32F415x8.ld | 5 +- .../ARMCMx/compilers/GCC/ld/AT32F415xB.ld | 5 +- .../ARMCMx/compilers/GCC/ld/AT32F415xC.ld | 5 +- .../ARMCMx/devices/AT32F415/cmparams.h | 6 +- os/hal/boards/AT_START_F415/board.c | 4 +- os/hal/boards/AT_START_F415/board.h | 14 +- os/hal/boards/AT_START_F415/board.mk | 4 +- os/hal/ports/AT32/AT32F415/at32_crm.h | 4 +- os/hal/ports/AT32/AT32F415/at32_dmamux.h | 4 +- os/hal/ports/AT32/AT32F415/at32_isr.c | 4 +- os/hal/ports/AT32/AT32F415/at32_isr.h | 4 +- os/hal/ports/AT32/AT32F415/at32_registry.h | 4 +- os/hal/ports/AT32/AT32F415/hal_efl_lld.c | 4 +- os/hal/ports/AT32/AT32F415/hal_efl_lld.h | 4 +- os/hal/ports/AT32/AT32F415/hal_lld.c | 4 +- os/hal/ports/AT32/AT32F415/hal_lld.h | 4 +- os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c | 4 +- os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h | 4 +- os/hal/ports/AT32/LLD/DMAv1/at32_dma.c | 4 +- os/hal/ports/AT32/LLD/DMAv1/at32_dma.h | 4 +- os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c | 4 +- os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h | 4 +- os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc | 4 +- os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc | 4 +- .../AT32/LLD/EXINTv1/at32_exint10_15.inc | 4 +- .../ports/AT32/LLD/EXINTv1/at32_exint16.inc | 4 +- .../ports/AT32/LLD/EXINTv1/at32_exint17.inc | 4 +- .../ports/AT32/LLD/EXINTv1/at32_exint18.inc | 4 +- .../ports/AT32/LLD/EXINTv1/at32_exint19.inc | 4 +- os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc | 4 +- .../ports/AT32/LLD/EXINTv1/at32_exint20.inc | 4 +- .../ports/AT32/LLD/EXINTv1/at32_exint21.inc | 4 +- .../ports/AT32/LLD/EXINTv1/at32_exint22.inc | 4 +- os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc | 4 +- os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc | 4 +- .../ports/AT32/LLD/EXINTv1/at32_exint5_9.inc | 4 +- os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c | 4 +- os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h | 4 +- os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c | 4 +- os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h | 4 +- os/hal/ports/AT32/LLD/OTGv1/at32_otg.h | 4 +- os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c | 4 +- os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h | 4 +- os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c | 4 +- os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h | 4 +- os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c | 4 +- os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h | 4 +- os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c | 4 +- os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h | 4 +- os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h | 4 +- .../AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc | 4 +- os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc | 4 +- os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc | 4 +- os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc | 4 +- os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc | 4 +- os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c | 4 +- os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h | 4 +- os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c | 4 +- os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h | 4 +- os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c | 4 +- os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h | 4 +- os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc | 4 +- os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc | 4 +- os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc | 4 +- os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc | 4 +- os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc | 4 +- .../ports/AT32/LLD/USARTv1/hal_serial_lld.c | 4 +- .../ports/AT32/LLD/USARTv1/hal_serial_lld.h | 4 +- os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c | 4 +- os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h | 4 +- os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c | 4 +- os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h | 4 +- testhal/AT32/AT32F415/PWM-ICU/.cproject | 49 ++ testhal/AT32/AT32F415/PWM-ICU/.project | 33 + testhal/AT32/AT32F415/PWM-ICU/Makefile | 236 +++++ testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h | 819 ++++++++++++++++++ testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h | 555 ++++++++++++ testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h | 222 +++++ testhal/AT32/AT32F415/PWM-ICU/main.c | 145 ++++ testhal/AT32/AT32F415/PWM-ICU/readme.txt | 28 + testhal/AT32/AT32F415/USB_CDC/.cproject | 56 ++ testhal/AT32/AT32F415/USB_CDC/.project | 49 ++ testhal/AT32/AT32F415/USB_CDC/Makefile | 238 +++++ testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h | 819 ++++++++++++++++++ testhal/AT32/AT32F415/USB_CDC/cfg/halconf.h | 555 ++++++++++++ testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h | 222 +++++ testhal/AT32/AT32F415/USB_CDC/main.c | 160 ++++ testhal/AT32/AT32F415/USB_CDC/readme.txt | 26 + testhal/AT32/AT32F415/USB_CDC/usbcfg.c | 344 ++++++++ testhal/AT32/AT32F415/USB_CDC/usbcfg.h | 28 + 96 files changed, 5284 insertions(+), 395 deletions(-) rename {testhal => demos}/AT32/.keep (100%) create mode 100644 testhal/AT32/AT32F415/PWM-ICU/.cproject create mode 100644 testhal/AT32/AT32F415/PWM-ICU/.project create mode 100644 testhal/AT32/AT32F415/PWM-ICU/Makefile create mode 100644 testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h create mode 100644 testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h create mode 100644 testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h create mode 100644 testhal/AT32/AT32F415/PWM-ICU/main.c create mode 100644 testhal/AT32/AT32F415/PWM-ICU/readme.txt create mode 100644 testhal/AT32/AT32F415/USB_CDC/.cproject create mode 100644 testhal/AT32/AT32F415/USB_CDC/.project create mode 100644 testhal/AT32/AT32F415/USB_CDC/Makefile create mode 100644 testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h create mode 100644 testhal/AT32/AT32F415/USB_CDC/cfg/halconf.h create mode 100644 testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h create mode 100644 testhal/AT32/AT32F415/USB_CDC/main.c create mode 100644 testhal/AT32/AT32F415/USB_CDC/readme.txt create mode 100644 testhal/AT32/AT32F415/USB_CDC/usbcfg.c create mode 100644 testhal/AT32/AT32F415/USB_CDC/usbcfg.h diff --git a/testhal/AT32/.keep b/demos/AT32/.keep similarity index 100% rename from testhal/AT32/.keep rename to demos/AT32/.keep diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h index 151f63498ec..61a32585682 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h @@ -1,7 +1,7 @@ /** ****************************************************************************** * @file at32f415.h - * @author Artery Technology & HorrorTroll + * @author Artery Technology & HorrorTroll & Zhaqian * @brief AT32F415 header file * ****************************************************************************** diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h index 0935ff257f3..a1609cf0dd0 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h @@ -1,7 +1,7 @@ /** ****************************************************************************** * @file at32f415cx.h - * @author Artery Technology & HorrorTroll + * @author Artery Technology & HorrorTroll & Zhaqian * @version v2.1.1 * @date 26-October-2023 * @brief AT32F415Cx header file. @@ -2541,13 +2541,13 @@ typedef struct #define IOMUX_REMAP_USART3_MUX_0 (0x1U << IOMUX_REMAP_USART3_MUX_Pos) /*!< 0x00000010 */ #define IOMUX_REMAP_USART3_MUX_1 (0x2U << IOMUX_REMAP_USART3_MUX_Pos) /*!< 0x00000020 */ -#define IOMUX_REMAP_USART3_MUX_MUX1 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ -#define IOMUX_REMAP_USART3_MUX_MUX2_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP_USART3_MUX_MUX0 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP_USART3_MUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP_USART3_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_USART3_MUX_MUX1_Pos) +#define IOMUX_REMAP_USART3_MUX_MUX1 IOMUX_REMAP_USART3_MUX_MUX1_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP_USART3_MUX_MUX2_Pos (5U) /*!< 0x00000020 */ #define IOMUX_REMAP_USART3_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_USART3_MUX_MUX2_Pos) -#define IOMUX_REMAP_USART3_MUX_MUX2 IOMUX_REMAP_USART3_MUX_MUX2_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ -#define IOMUX_REMAP_USART3_MUX_MUX3_Pos (5U) /*!< 0x00000020 */ -#define IOMUX_REMAP_USART3_MUX_MUX3_Msk (0x1U << IOMUX_REMAP_USART3_MUX_MUX3_Pos) -#define IOMUX_REMAP_USART3_MUX_MUX3 IOMUX_REMAP_USART3_MUX_MUX3_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ +#define IOMUX_REMAP_USART3_MUX_MUX2 IOMUX_REMAP_USART3_MUX_MUX2_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ /*!< TMR1_MUX configuration */ #define IOMUX_REMAP_TMR1_MUX_Pos (6U) @@ -2556,10 +2556,10 @@ typedef struct #define IOMUX_REMAP_TMR1_MUX_0 (0x1U << IOMUX_REMAP_TMR1_MUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP_TMR1_MUX_1 (0x2U << IOMUX_REMAP_TMR1_MUX_Pos /*!< 0x00000080 */ -#define IOMUX_REMAP_TMR1_MUX_MUX1 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ -#define IOMUX_REMAP_TMR1_MUX_MUX2_Pos (6U) -#define IOMUX_REMAP_TMR1_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR1_MUX_MUX2_Pos) /*!< 0x00000040 */ -#define IOMUX_REMAP_TMR1_MUX_MUX2 IOMUX_REMAP_TMR1_MUX_MUX2_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP_TMR1_MUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1_Pos (6U) +#define IOMUX_REMAP_TMR1_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR1_MUX_MUX1_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1 IOMUX_REMAP_TMR1_MUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ /*!< TMR2_MUX configuration */ #define IOMUX_REMAP_TMR2_MUX_Pos (8U) @@ -2568,16 +2568,16 @@ typedef struct #define IOMUX_REMAP_TMR2_MUX_0 (0x1U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000100 */ #define IOMUX_REMAP_TMR2_MUX_1 (0x2U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000200 */ -#define IOMUX_REMAP_TMR2_MUX_MUX1 0x00000000U /*!< CH1/EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP_TMR2_MUX_MUX2_Pos (8U) -#define IOMUX_REMAP_TMR2_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX2_Pos) /*!< 0x00000100 */ -#define IOMUX_REMAP_TMR2_MUX_MUX2 IOMUX_REMAP_TMR2_MUX_MUX2_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP_TMR2_MUX_MUX3_Pos (9U) -#define IOMUX_REMAP_TMR2_MUX_MUX3_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX3_Pos) /*!< 0x00000200 */ -#define IOMUX_REMAP_TMR2_MUX_MUX3 IOMUX_REMAP_TMR2_MUX_MUX3_Msk /*!< CH1/EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ -#define IOMUX_REMAP_TMR2_MUX_MUX4_Pos (8U) -#define IOMUX_REMAP_TMR2_MUX_MUX4_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_MUX4_Pos) /*!< 0x00000300 */ -#define IOMUX_REMAP_TMR2_MUX_MUX4 IOMUX_REMAP_TMR2_MUX_MUX4_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP_TMR2_MUX_MUX0 0x00000000U /*!< CH1/EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX1_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1 IOMUX_REMAP_TMR2_MUX_MUX1_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2_Pos (9U) +#define IOMUX_REMAP_TMR2_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX2_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2 IOMUX_REMAP_TMR2_MUX_MUX2_Msk /*!< CH1/EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX3_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_MUX3_Pos) /*!< 0x00000300 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3 IOMUX_REMAP_TMR2_MUX_MUX3_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ /*!< TMR3_MUX configuration */ #define IOMUX_REMAP_TMR3_MUX_Pos (10U) @@ -2586,7 +2586,7 @@ typedef struct #define IOMUX_REMAP_TMR3_MUX_0 (0x1U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP_TMR3_MUX_1 (0x2U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000800 */ -#define IOMUX_REMAP_TMR3_MUX_MUX1 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP_TMR3_MUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ #define IOMUX_REMAP_TMR3_MUX_MUX2_Pos (11U) #define IOMUX_REMAP_TMR3_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR3_MUX_MUX2_Pos) /*!< 0x00000800 */ #define IOMUX_REMAP_TMR3_MUX_MUX2 IOMUX_REMAP_TMR3_MUX_MUX2_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ @@ -2601,7 +2601,7 @@ typedef struct #define IOMUX_REMAP_CAN1_MUX_0 (0x1U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00002000 */ #define IOMUX_REMAP_CAN1_MUX_1 (0x2U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00004000 */ -#define IOMUX_REMAP_CAN1_MUX_MUX1 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP_CAN1_MUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ #define IOMUX_REMAP_CAN1_MUX_MUX2_Pos (14U) #define IOMUX_REMAP_CAN1_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_CAN1_MUX_MUX2_Pos) /*!< 0x00004000 */ #define IOMUX_REMAP_CAN1_MUX_MUX2 IOMUX_REMAP_CAN1_MUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ @@ -2949,10 +2949,18 @@ typedef struct /***************** Bit definition for IOMUX_REMAP2 register *****************/ /*!< CMP_MUX configuration */ #define IOMUX_REMAP2_CMP_MUX_Pos (26U) -#define IOMUX_REMAP2_CMP_MUX_Msk (0x3U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x0C000000 */ -#define IOMUX_REMAP2_CMP_MUX IOMUX_REMAP2_CMP_MUX_Msk /*!< CMP_MUX[1:0] bits (CMP internal remap) */ -#define IOMUX_REMAP2_CMP_MUX_0 (0x1U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x04000000 */ -#define IOMUX_REMAP2_CMP_MUX_1 (0x2U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x08000000 */ +#define IOMUX_REMAP2_CMP_MUX_Msk (0x3U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x0C000000 */ +#define IOMUX_REMAP2_CMP_MUX IOMUX_REMAP2_CMP_MUX_Msk /*!< CMP_MUX[1:0] bits (CMP internal remap) */ +#define IOMUX_REMAP2_CMP_MUX_0 (0x1U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_1 (0x2U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x08000000 */ + +#define IOMUX_REMAP2_CMP_MUX_MUX0 0x00000000U /*!< CMP1_OUT is connected to PA0, CMP2_OUT is connected to PA2 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1_Pos (26U) +#define IOMUX_REMAP2_CMP_MUX_MUX1_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX1_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1 IOMUX_REMAP2_CMP_MUX_MUX1_Msk /*!< CMP1_OUT is connected to PA6, CMP2_OUT is connected to PA7 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2_Pos (27U) +#define IOMUX_REMAP2_CMP_MUX_MUX2_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX2_Pos) /*!< 0x08000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2 IOMUX_REMAP2_CMP_MUX_MUX2_Msk /*!< CMP1_OUT is connected to PA11, CMP2_OUT is connected to PA12 */ /***************** Bit definition for IOMUX_REMAP3 register *****************/ /*!< TMR9_GMUX configuration */ @@ -2964,6 +2972,11 @@ typedef struct #define IOMUX_REMAP3_TMR9_GMUX_2 (0x4U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP3_TMR9_GMUX_3 (0x8U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000008 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX0 0x00000000U /*!< CH1/PA2, CH2/PA3 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR9_GMUX_MUX2 IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk /*!< CH1/PB14, CH2/PB15 */ + /*!< TMR10_GMUX configuration */ #define IOMUX_REMAP3_TMR10_GMUX_Pos (4U) #define IOMUX_REMAP3_TMR10_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x000000F0 */ @@ -2973,6 +2986,11 @@ typedef struct #define IOMUX_REMAP3_TMR10_GMUX_2 (0x4U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP3_TMR10_GMUX_3 (0x8U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000080 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX0 0x00000000U /*!< CH1/PB8 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR10_GMUX_MUX2 IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk /*!< CH1/PA6 */ + /*!< TMR11_GMUX configuration */ #define IOMUX_REMAP3_TMR11_GMUX_Pos (8U) #define IOMUX_REMAP3_TMR11_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000F00 */ @@ -2982,6 +3000,11 @@ typedef struct #define IOMUX_REMAP3_TMR11_GMUX_2 (0x4U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP3_TMR11_GMUX_3 (0x8U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000800 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX0 0x00000000U /*!< CH1/PB9 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR11_GMUX_MUX2 IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk /*!< CH1/PA7 */ + /***************** Bit definition for IOMUX_REMAP4 register *****************/ /*!< TMR1_GMUX configuration */ #define IOMUX_REMAP4_TMR1_GMUX_Pos (0U) @@ -2992,13 +3015,13 @@ typedef struct #define IOMUX_REMAP4_TMR1_GMUX_2 (0x4U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP4_TMR1_GMUX_3 (0x8U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000008 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX1 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR1_GMUX_MUX1 IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ #define IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos) -#define IOMUX_REMAP4_TMR1_GMUX_MUX2 IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX3_Pos (1U) /*!< 0x00000002 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX3_Pos) -#define IOMUX_REMAP4_TMR1_GMUX_MUX3 IOMUX_REMAP4_TMR1_GMUX_MUX3_Msk /*!< EXT/PA0, CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2 IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk /*!< EXT/PA0, CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ /*!< TMR2_GMUX configuration */ #define IOMUX_REMAP4_TMR2_GMUX_Pos (4U) @@ -3008,16 +3031,16 @@ typedef struct #define IOMUX_REMAP4_TMR2_GMUX_1 (0x2U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000020 */ #define IOMUX_REMAP4_TMR2_GMUX_2 (0x4U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000040 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX1 0x00000000U /*!< CH1_EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX0 0x00000000U /*!< CH1_EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX1 IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ #define IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos) -#define IOMUX_REMAP4_TMR2_GMUX_MUX2 IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos (5U) /*!< 0x00000020 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos) -#define IOMUX_REMAP4_TMR2_GMUX_MUX3 IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk /*!< CH1_EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX4_Pos (4U) /*!< 0x00000030 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX4_Msk (0x3U << IOMUX_REMAP4_TMR2_GMUX_MUX4_Pos) -#define IOMUX_REMAP4_TMR2_GMUX_MUX4 IOMUX_REMAP4_TMR2_GMUX_MUX4_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2 IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk /*!< CH1_EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX3 IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ /*!< TMR3_GMUX configuration */ #define IOMUX_REMAP4_TMR3_GMUX_Pos (8U) @@ -3028,6 +3051,11 @@ typedef struct #define IOMUX_REMAP4_TMR3_GMUX_2 (0x4U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP4_TMR3_GMUX_3 (0x8U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000800 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR3_GMUX_MUX1 IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ + /*!< TMR5_GMUX configuration */ #define IOMUX_REMAP4_TMR5_GMUX_Pos (16U) #define IOMUX_REMAP4_TMR5_GMUX_Msk (0x7U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00070000 */ @@ -3036,6 +3064,11 @@ typedef struct #define IOMUX_REMAP4_TMR5_GMUX_1 (0x2U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00020000 */ #define IOMUX_REMAP4_TMR5_GMUX_2 (0x4U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX0 0x00000000U /*!< CH1/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR5_GMUX_MUX1 IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk /*!< CH1/PF4, CH2/PF5, CH3/PA2, CH4/PA3 */ + #define IOMUX_REMAP4_TMR5CH4_GMUX_Pos (19U) #define IOMUX_REMAP4_TMR5CH4_GMUX_Msk (0x1U << IOMUX_REMAP4_TMR5CH4_GMUX_Pos) /*!< 0x00080000 */ #define IOMUX_REMAP4_TMR5CH4_GMUX IOMUX_REMAP4_TMR5CH4_GMUX_Msk /*!< TMR5 channel 4 general multiplexing */ @@ -3050,13 +3083,13 @@ typedef struct #define IOMUX_REMAP5_I2C1_GMUX_2 (0x4U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP5_I2C1_GMUX_3 (0x8U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000080 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX1 0x00000000U /*!< SCL/PB6, SDA/PB7, SMBA/PB5 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX0 0x00000000U /*!< SCL/PB6, SDA/PB7, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C1_GMUX_MUX1 IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk /*!< SCL/PB8, SDA/PB9, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ #define IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos) -#define IOMUX_REMAP5_I2C1_GMUX_MUX2 IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk /*!< SCL/PB8, SDA/PB9, SMBA/PB5 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX3_Pos (5U) /*!< 0x00000020 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX3_Pos) -#define IOMUX_REMAP5_I2C1_GMUX_MUX3 IOMUX_REMAP5_I2C1_GMUX_MUX3_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2 IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PB5 */ /*!< I2C2_GMUX configuration */ #define IOMUX_REMAP5_I2C2_GMUX_Pos (8U) @@ -3067,16 +3100,16 @@ typedef struct #define IOMUX_REMAP5_I2C2_GMUX_2 (0x4U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP5_I2C2_GMUX_3 (0x8U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000800 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX1 0x00000000U /*!< SCL/PB10, SDA/PB11, SMBA/PB12 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX0 0x00000000U /*!< SCL/PB10, SDA/PB11, SMBA/PB12 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX1 IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk /*!< SCL/PA8, SDA/PC9, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos (9U) /*!< 0x00000200 */ #define IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos) -#define IOMUX_REMAP5_I2C2_GMUX_MUX2 IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk /*!< SCL/PA8, SDA/PC9, SMBA/PA9 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos (9U) /*!< 0x00000200 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos) -#define IOMUX_REMAP5_I2C2_GMUX_MUX3 IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk /*!< SCL/PA8, SDA/PB4, SMBA/PA9 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX4_Pos (8U) /*!< 0x00000300 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX4_Msk (0x3U << IOMUX_REMAP5_I2C2_GMUX_MUX4_Pos) -#define IOMUX_REMAP5_I2C2_GMUX_MUX4 IOMUX_REMAP5_I2C2_GMUX_MUX4_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2 IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk /*!< SCL/PA8, SDA/PB4, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos (8U) /*!< 0x00000300 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX3 IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PA9 */ /*!< SPI1_GMUX configuration */ #define IOMUX_REMAP5_SPI1_GMUX_Pos (16U) @@ -3087,6 +3120,11 @@ typedef struct #define IOMUX_REMAP5_SPI1_GMUX_2 (0x4U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00040000 */ #define IOMUX_REMAP5_SPI1_GMUX_3 (0x8U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00080000 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX0 0x00000000U /*!< CS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7, MCK/PB0 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI1_GMUX_MUX1 IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PB6 */ + /*!< SPI2_GMUX configuration */ #define IOMUX_REMAP5_SPI2_GMUX_Pos (20U) #define IOMUX_REMAP5_SPI2_GMUX_Msk (0xFU << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00F00000 */ @@ -3096,6 +3134,11 @@ typedef struct #define IOMUX_REMAP5_SPI2_GMUX_2 (0x4U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00400000 */ #define IOMUX_REMAP5_SPI2_GMUX_3 (0x8U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00800000 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX0 0x00000000U /*!< CS/PB12, SCK/PB13, MISO/PB14, MOSI/PB15, MCK/PC6 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos (20U) /*!< 0x00100000 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI2_GMUX_MUX1 IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PC7 */ + /***************** Bit definition for IOMUX_REMAP6 register *****************/ /*!< CAN1_GMUX configuration */ #define IOMUX_REMAP6_CAN1_GMUX_Pos (0U) @@ -3106,6 +3149,11 @@ typedef struct #define IOMUX_REMAP6_CAN1_GMUX_2 (0x4U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP6_CAN1_GMUX_3 (0x8U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000008 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos) +#define IOMUX_REMAP6_CAN1_GMUX_MUX2 IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ + /*!< SDIO_GMUX configuration */ #define IOMUX_REMAP6_SDIO_GMUX_Pos (8U) #define IOMUX_REMAP6_SDIO_GMUX_Msk (0xFU << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000F00 */ @@ -3115,19 +3163,19 @@ typedef struct #define IOMUX_REMAP6_SDIO_GMUX_2 (0x4U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP6_SDIO_GMUX_3 (0x8U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000800 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX1 0x00000000U /*!< D0/PC8, D1/PC9, D2/PC10, D3/PC11, D4/PB8, D5/PB9, D6/PC6, D7/PC7, CK/PC12, CMD/PD2 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX2_Pos (10U) /*!< 0x00000400 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_SDIO_GMUX_MUX2_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX2 IOMUX_REMAP6_SDIO_GMUX_MUX2_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PC4, CMD/PC5 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX3_Pos (8U) /*!< 0x00000500 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX3_Msk (0x5U << IOMUX_REMAP6_SDIO_GMUX_MUX3_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX3 IOMUX_REMAP6_SDIO_GMUX_MUX3_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PC4, CMD/PC5 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos (9U) /*!< 0x00000600 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk (0x3U << IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX4 IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PA2, CMD/PA3 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos (8U) /*!< 0x00000700 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk (0x7U << IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX5 IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PA2, CMD/PA3 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX0 0x00000000U /*!< D0/PC8, D1/PC9, D2/PC10, D3/PC11, D4/PB8, D5/PB9, D6/PC6, D7/PC7, CK/PC12, CMD/PD2 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos (10U) /*!< 0x00000400 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk (0x1U << IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX4 IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos (8U) /*!< 0x00000500 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk (0x5U << IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX5 IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos (9U) /*!< 0x00000600 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk (0x3U << IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX6 IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PA2, CMD/PA3 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos (8U) /*!< 0x00000700 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk (0x7U << IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX7 IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PA2, CMD/PA3 */ /*!< USART1_GMUX configuration */ #define IOMUX_REMAP6_USART1_GMUX_Pos (16U) @@ -3138,6 +3186,11 @@ typedef struct #define IOMUX_REMAP6_USART1_GMUX_2 (0x4U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00040000 */ #define IOMUX_REMAP6_USART1_GMUX_3 (0x8U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00080000 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX0 0x00000000U /*!< TX/PA9, RX/PA10 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_USART1_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_USART1_GMUX_MUX1 IOMUX_REMAP6_USART1_GMUX_MUX1_Msk /*!< TX/PB6, RX/PB7 */ + /*!< USART3_GMUX configuration */ #define IOMUX_REMAP6_USART3_GMUX_Pos (24U) #define IOMUX_REMAP6_USART3_GMUX_Msk (0xFU << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x0F000000 */ @@ -3147,13 +3200,13 @@ typedef struct #define IOMUX_REMAP6_USART3_GMUX_2 (0x4U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x04000000 */ #define IOMUX_REMAP6_USART3_GMUX_3 (0x8U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x08000000 */ -#define IOMUX_REMAP6_USART3_GMUX_MUX1 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ -#define IOMUX_REMAP6_USART3_GMUX_MUX2_Pos (24U) /*!< 0x01000000 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX0 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX1_Pos (24U) /*!< 0x01000000 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_USART3_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_USART3_GMUX_MUX1 IOMUX_REMAP6_USART3_GMUX_MUX1_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX2_Pos (25U) /*!< 0x02000000 */ #define IOMUX_REMAP6_USART3_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_USART3_GMUX_MUX2_Pos) -#define IOMUX_REMAP6_USART3_GMUX_MUX2 IOMUX_REMAP6_USART3_GMUX_MUX2_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ -#define IOMUX_REMAP6_USART3_GMUX_MUX3_Pos (25U) /*!< 0x02000000 */ -#define IOMUX_REMAP6_USART3_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP6_USART3_GMUX_MUX3_Pos) -#define IOMUX_REMAP6_USART3_GMUX_MUX3 IOMUX_REMAP6_USART3_GMUX_MUX3_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX2 IOMUX_REMAP6_USART3_GMUX_MUX2_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ /***************** Bit definition for IOMUX_REMAP7 register *****************/ #define IOMUX_REMAP7_ADC1_ETP_GMUX_Pos (4U) /*!< 0x00000010 */ @@ -3171,16 +3224,16 @@ typedef struct #define IOMUX_REMAP7_SWJTAG_GMUX_1 (0x2U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00020000 */ #define IOMUX_REMAP7_SWJTAG_GMUX_2 (0x4U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00040000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX1 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIO */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Pos (16U) /*!< 0x00010000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Pos) -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX2 IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Pos (17U) /*!< 0x00020000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Pos) -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX3 IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Msk /*!< Supports SWD. But JTAG is disabled. PA15/PB3/PB4 can be used as GPIO */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Pos (18U) /*!< 0x00040000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Pos) -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX4 IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_RESET 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos (17U) /*!< 0x00020000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk /*!< Supports SWD. But JTAG is disabled. PA15/PB3/PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos (18U) /*!< 0x00040000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIO */ #define IOMUX_REMAP7_PD01_GMUX_Pos (20U) #define IOMUX_REMAP7_PD01_GMUX_Msk (0x1U << IOMUX_REMAP7_PD01_GMUX_Pos) /*!< 0x00100000 */ @@ -3194,6 +3247,17 @@ typedef struct #define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000001 */ #define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos (0U) /*!< 0x00000003 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ + /*!< TMR1_CH1_CMP_GMUX configuration */ #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos (2U) /*!< 0x0000000C */ #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) @@ -3201,6 +3265,17 @@ typedef struct #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000008 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos (2U) /*!< 0x00000004 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos (3U) /*!< 0x00000008 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos (2U) /*!< 0x0000000C */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 channel 1 */ + /*!< TMR2_CH4_CMP_GMUX configuration */ #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos (4U) /*!< 0x00000030 */ #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) @@ -3208,6 +3283,17 @@ typedef struct #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000010 */ #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX0 0x00000000U /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR2_GMUX IO signal is connected to TMR2 channel 4 */ + /*!< TMR3_CH1_CMP_GMUX configuration */ #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos (6U) /*!< 0x000000C0 */ #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) @@ -3215,6 +3301,17 @@ typedef struct #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000080 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos (6U) /*!< 0x00000040 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos (7U) /*!< 0x00000080 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos (6U) /*!< 0x000000C0 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR3_GMUX IO signal is connected to TMR3 channel 1 */ + /******************************************************************************/ /* */ /* External interrupt/Event controller (EXINT) */ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h index 6669f4d1212..cbf383d983a 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h @@ -1,7 +1,7 @@ /** ****************************************************************************** * @file at32f415kx.h - * @author Artery Technology & HorrorTroll + * @author Artery Technology & HorrorTroll & Zhaqian * @version v2.1.1 * @date 26-October-2023 * @brief AT32F415Kx header file. @@ -2532,10 +2532,10 @@ typedef struct #define IOMUX_REMAP_TMR1_MUX_0 (0x1U << IOMUX_REMAP_TMR1_MUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP_TMR1_MUX_1 (0x2U << IOMUX_REMAP_TMR1_MUX_Pos /*!< 0x00000080 */ -#define IOMUX_REMAP_TMR1_MUX_MUX1 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ -#define IOMUX_REMAP_TMR1_MUX_MUX2_Pos (6U) -#define IOMUX_REMAP_TMR1_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR1_MUX_MUX2_Pos) /*!< 0x00000040 */ -#define IOMUX_REMAP_TMR1_MUX_MUX2 IOMUX_REMAP_TMR1_MUX_MUX2_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP_TMR1_MUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1_Pos (6U) +#define IOMUX_REMAP_TMR1_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR1_MUX_MUX1_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1 IOMUX_REMAP_TMR1_MUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ /*!< TMR2_MUX configuration */ #define IOMUX_REMAP_TMR2_MUX_Pos (8U) @@ -2544,16 +2544,16 @@ typedef struct #define IOMUX_REMAP_TMR2_MUX_0 (0x1U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000100 */ #define IOMUX_REMAP_TMR2_MUX_1 (0x2U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000200 */ -#define IOMUX_REMAP_TMR2_MUX_MUX1 0x00000000U /*!< CH1/EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP_TMR2_MUX_MUX2_Pos (8U) -#define IOMUX_REMAP_TMR2_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX2_Pos) /*!< 0x00000100 */ -#define IOMUX_REMAP_TMR2_MUX_MUX2 IOMUX_REMAP_TMR2_MUX_MUX2_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP_TMR2_MUX_MUX3_Pos (9U) -#define IOMUX_REMAP_TMR2_MUX_MUX3_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX3_Pos) /*!< 0x00000200 */ -#define IOMUX_REMAP_TMR2_MUX_MUX3 IOMUX_REMAP_TMR2_MUX_MUX3_Msk /*!< CH1/EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ -#define IOMUX_REMAP_TMR2_MUX_MUX4_Pos (8U) -#define IOMUX_REMAP_TMR2_MUX_MUX4_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_MUX4_Pos) /*!< 0x00000300 */ -#define IOMUX_REMAP_TMR2_MUX_MUX4 IOMUX_REMAP_TMR2_MUX_MUX4_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP_TMR2_MUX_MUX0 0x00000000U /*!< CH1/EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX1_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1 IOMUX_REMAP_TMR2_MUX_MUX1_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2_Pos (9U) +#define IOMUX_REMAP_TMR2_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX2_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2 IOMUX_REMAP_TMR2_MUX_MUX2_Msk /*!< CH1/EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX3_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_MUX3_Pos) /*!< 0x00000300 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3 IOMUX_REMAP_TMR2_MUX_MUX3_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ /*!< TMR3_MUX configuration */ #define IOMUX_REMAP_TMR3_MUX_Pos (10U) @@ -2562,7 +2562,7 @@ typedef struct #define IOMUX_REMAP_TMR3_MUX_0 (0x1U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP_TMR3_MUX_1 (0x2U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000800 */ -#define IOMUX_REMAP_TMR3_MUX_MUX1 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP_TMR3_MUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ #define IOMUX_REMAP_TMR3_MUX_MUX2_Pos (11U) #define IOMUX_REMAP_TMR3_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR3_MUX_MUX2_Pos) /*!< 0x00000800 */ #define IOMUX_REMAP_TMR3_MUX_MUX2 IOMUX_REMAP_TMR3_MUX_MUX2_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ @@ -2577,7 +2577,7 @@ typedef struct #define IOMUX_REMAP_CAN1_MUX_0 (0x1U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00002000 */ #define IOMUX_REMAP_CAN1_MUX_1 (0x2U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00004000 */ -#define IOMUX_REMAP_CAN1_MUX_MUX1 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP_CAN1_MUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ #define IOMUX_REMAP_CAN1_MUX_MUX2_Pos (14U) #define IOMUX_REMAP_CAN1_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_CAN1_MUX_MUX2_Pos) /*!< 0x00004000 */ #define IOMUX_REMAP_CAN1_MUX_MUX2 IOMUX_REMAP_CAN1_MUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ @@ -2925,10 +2925,18 @@ typedef struct /***************** Bit definition for IOMUX_REMAP2 register *****************/ /*!< CMP_MUX configuration */ #define IOMUX_REMAP2_CMP_MUX_Pos (26U) -#define IOMUX_REMAP2_CMP_MUX_Msk (0x3U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x0C000000 */ -#define IOMUX_REMAP2_CMP_MUX IOMUX_REMAP2_CMP_MUX_Msk /*!< CMP_MUX[1:0] bits (CMP internal remap) */ -#define IOMUX_REMAP2_CMP_MUX_0 (0x1U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x04000000 */ -#define IOMUX_REMAP2_CMP_MUX_1 (0x2U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x08000000 */ +#define IOMUX_REMAP2_CMP_MUX_Msk (0x3U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x0C000000 */ +#define IOMUX_REMAP2_CMP_MUX IOMUX_REMAP2_CMP_MUX_Msk /*!< CMP_MUX[1:0] bits (CMP internal remap) */ +#define IOMUX_REMAP2_CMP_MUX_0 (0x1U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_1 (0x2U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x08000000 */ + +#define IOMUX_REMAP2_CMP_MUX_MUX0 0x00000000U /*!< CMP1_OUT is connected to PA0, CMP2_OUT is connected to PA2 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1_Pos (26U) +#define IOMUX_REMAP2_CMP_MUX_MUX1_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX1_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1 IOMUX_REMAP2_CMP_MUX_MUX1_Msk /*!< CMP1_OUT is connected to PA6, CMP2_OUT is connected to PA7 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2_Pos (27U) +#define IOMUX_REMAP2_CMP_MUX_MUX2_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX2_Pos) /*!< 0x08000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2 IOMUX_REMAP2_CMP_MUX_MUX2_Msk /*!< CMP1_OUT is connected to PA11, CMP2_OUT is connected to PA12 */ /***************** Bit definition for IOMUX_REMAP3 register *****************/ /*!< TMR9_GMUX configuration */ @@ -2940,6 +2948,11 @@ typedef struct #define IOMUX_REMAP3_TMR9_GMUX_2 (0x4U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP3_TMR9_GMUX_3 (0x8U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000008 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX0 0x00000000U /*!< CH1/PA2, CH2/PA3 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR9_GMUX_MUX2 IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk /*!< CH1/PB14, CH2/PB15 */ + /*!< TMR10_GMUX configuration */ #define IOMUX_REMAP3_TMR10_GMUX_Pos (4U) #define IOMUX_REMAP3_TMR10_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x000000F0 */ @@ -2949,6 +2962,11 @@ typedef struct #define IOMUX_REMAP3_TMR10_GMUX_2 (0x4U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP3_TMR10_GMUX_3 (0x8U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000080 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX0 0x00000000U /*!< CH1/PB8 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR10_GMUX_MUX2 IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk /*!< CH1/PA6 */ + /*!< TMR11_GMUX configuration */ #define IOMUX_REMAP3_TMR11_GMUX_Pos (8U) #define IOMUX_REMAP3_TMR11_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000F00 */ @@ -2958,6 +2976,11 @@ typedef struct #define IOMUX_REMAP3_TMR11_GMUX_2 (0x4U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP3_TMR11_GMUX_3 (0x8U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000800 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX0 0x00000000U /*!< CH1/PB9 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR11_GMUX_MUX2 IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk /*!< CH1/PA7 */ + /***************** Bit definition for IOMUX_REMAP4 register *****************/ /*!< TMR1_GMUX configuration */ #define IOMUX_REMAP4_TMR1_GMUX_Pos (0U) @@ -2968,13 +2991,13 @@ typedef struct #define IOMUX_REMAP4_TMR1_GMUX_2 (0x4U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP4_TMR1_GMUX_3 (0x8U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000008 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX1 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR1_GMUX_MUX1 IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ #define IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos) -#define IOMUX_REMAP4_TMR1_GMUX_MUX2 IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX3_Pos (1U) /*!< 0x00000002 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX3_Pos) -#define IOMUX_REMAP4_TMR1_GMUX_MUX3 IOMUX_REMAP4_TMR1_GMUX_MUX3_Msk /*!< EXT/PA0, CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2 IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk /*!< EXT/PA0, CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ /*!< TMR2_GMUX configuration */ #define IOMUX_REMAP4_TMR2_GMUX_Pos (4U) @@ -2984,16 +3007,16 @@ typedef struct #define IOMUX_REMAP4_TMR2_GMUX_1 (0x2U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000020 */ #define IOMUX_REMAP4_TMR2_GMUX_2 (0x4U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000040 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX1 0x00000000U /*!< CH1_EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX0 0x00000000U /*!< CH1_EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX1 IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ #define IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos) -#define IOMUX_REMAP4_TMR2_GMUX_MUX2 IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos (5U) /*!< 0x00000020 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos) -#define IOMUX_REMAP4_TMR2_GMUX_MUX3 IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk /*!< CH1_EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX4_Pos (4U) /*!< 0x00000030 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX4_Msk (0x3U << IOMUX_REMAP4_TMR2_GMUX_MUX4_Pos) -#define IOMUX_REMAP4_TMR2_GMUX_MUX4 IOMUX_REMAP4_TMR2_GMUX_MUX4_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2 IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk /*!< CH1_EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX3 IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ /*!< TMR3_GMUX configuration */ #define IOMUX_REMAP4_TMR3_GMUX_Pos (8U) @@ -3004,6 +3027,11 @@ typedef struct #define IOMUX_REMAP4_TMR3_GMUX_2 (0x4U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP4_TMR3_GMUX_3 (0x8U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000800 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR3_GMUX_MUX1 IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ + /*!< TMR5_GMUX configuration */ #define IOMUX_REMAP4_TMR5_GMUX_Pos (16U) #define IOMUX_REMAP4_TMR5_GMUX_Msk (0x7U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00070000 */ @@ -3012,6 +3040,11 @@ typedef struct #define IOMUX_REMAP4_TMR5_GMUX_1 (0x2U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00020000 */ #define IOMUX_REMAP4_TMR5_GMUX_2 (0x4U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX0 0x00000000U /*!< CH1/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR5_GMUX_MUX1 IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk /*!< CH1/PF4, CH2/PF5, CH3/PA2, CH4/PA3 */ + #define IOMUX_REMAP4_TMR5CH4_GMUX_Pos (19U) #define IOMUX_REMAP4_TMR5CH4_GMUX_Msk (0x1U << IOMUX_REMAP4_TMR5CH4_GMUX_Pos) /*!< 0x00080000 */ #define IOMUX_REMAP4_TMR5CH4_GMUX IOMUX_REMAP4_TMR5CH4_GMUX_Msk /*!< TMR5 channel 4 general multiplexing */ @@ -3026,13 +3059,13 @@ typedef struct #define IOMUX_REMAP5_I2C1_GMUX_2 (0x4U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP5_I2C1_GMUX_3 (0x8U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000080 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX1 0x00000000U /*!< SCL/PB6, SDA/PB7, SMBA/PB5 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX0 0x00000000U /*!< SCL/PB6, SDA/PB7, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C1_GMUX_MUX1 IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk /*!< SCL/PB8, SDA/PB9, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ #define IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos) -#define IOMUX_REMAP5_I2C1_GMUX_MUX2 IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk /*!< SCL/PB8, SDA/PB9, SMBA/PB5 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX3_Pos (5U) /*!< 0x00000020 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX3_Pos) -#define IOMUX_REMAP5_I2C1_GMUX_MUX3 IOMUX_REMAP5_I2C1_GMUX_MUX3_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2 IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PB5 */ /*!< I2C2_GMUX configuration */ #define IOMUX_REMAP5_I2C2_GMUX_Pos (8U) @@ -3043,16 +3076,16 @@ typedef struct #define IOMUX_REMAP5_I2C2_GMUX_2 (0x4U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP5_I2C2_GMUX_3 (0x8U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000800 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX1 0x00000000U /*!< SCL/PB10, SDA/PB11, SMBA/PB12 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX0 0x00000000U /*!< SCL/PB10, SDA/PB11, SMBA/PB12 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX1 IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk /*!< SCL/PA8, SDA/PC9, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos (9U) /*!< 0x00000200 */ #define IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos) -#define IOMUX_REMAP5_I2C2_GMUX_MUX2 IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk /*!< SCL/PA8, SDA/PC9, SMBA/PA9 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos (9U) /*!< 0x00000200 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos) -#define IOMUX_REMAP5_I2C2_GMUX_MUX3 IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk /*!< SCL/PA8, SDA/PB4, SMBA/PA9 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX4_Pos (8U) /*!< 0x00000300 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX4_Msk (0x3U << IOMUX_REMAP5_I2C2_GMUX_MUX4_Pos) -#define IOMUX_REMAP5_I2C2_GMUX_MUX4 IOMUX_REMAP5_I2C2_GMUX_MUX4_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2 IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk /*!< SCL/PA8, SDA/PB4, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos (8U) /*!< 0x00000300 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX3 IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PA9 */ /*!< SPI1_GMUX configuration */ #define IOMUX_REMAP5_SPI1_GMUX_Pos (16U) @@ -3063,6 +3096,11 @@ typedef struct #define IOMUX_REMAP5_SPI1_GMUX_2 (0x4U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00040000 */ #define IOMUX_REMAP5_SPI1_GMUX_3 (0x8U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00080000 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX0 0x00000000U /*!< CS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7, MCK/PB0 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI1_GMUX_MUX1 IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PB6 */ + /*!< SPI2_GMUX configuration */ #define IOMUX_REMAP5_SPI2_GMUX_Pos (20U) #define IOMUX_REMAP5_SPI2_GMUX_Msk (0xFU << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00F00000 */ @@ -3072,6 +3110,11 @@ typedef struct #define IOMUX_REMAP5_SPI2_GMUX_2 (0x4U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00400000 */ #define IOMUX_REMAP5_SPI2_GMUX_3 (0x8U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00800000 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX0 0x00000000U /*!< CS/PB12, SCK/PB13, MISO/PB14, MOSI/PB15, MCK/PC6 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos (20U) /*!< 0x00100000 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI2_GMUX_MUX1 IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PC7 */ + /***************** Bit definition for IOMUX_REMAP6 register *****************/ /*!< CAN1_GMUX configuration */ #define IOMUX_REMAP6_CAN1_GMUX_Pos (0U) @@ -3082,6 +3125,11 @@ typedef struct #define IOMUX_REMAP6_CAN1_GMUX_2 (0x4U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP6_CAN1_GMUX_3 (0x8U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000008 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos) +#define IOMUX_REMAP6_CAN1_GMUX_MUX2 IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ + /*!< SDIO_GMUX configuration */ #define IOMUX_REMAP6_SDIO_GMUX_Pos (8U) #define IOMUX_REMAP6_SDIO_GMUX_Msk (0xFU << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000F00 */ @@ -3091,19 +3139,19 @@ typedef struct #define IOMUX_REMAP6_SDIO_GMUX_2 (0x4U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP6_SDIO_GMUX_3 (0x8U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000800 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX1 0x00000000U /*!< D0/PC8, D1/PC9, D2/PC10, D3/PC11, D4/PB8, D5/PB9, D6/PC6, D7/PC7, CK/PC12, CMD/PD2 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX2_Pos (10U) /*!< 0x00000400 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_SDIO_GMUX_MUX2_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX2 IOMUX_REMAP6_SDIO_GMUX_MUX2_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PC4, CMD/PC5 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX3_Pos (8U) /*!< 0x00000500 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX3_Msk (0x5U << IOMUX_REMAP6_SDIO_GMUX_MUX3_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX3 IOMUX_REMAP6_SDIO_GMUX_MUX3_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PC4, CMD/PC5 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos (9U) /*!< 0x00000600 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk (0x3U << IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX4 IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PA2, CMD/PA3 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos (8U) /*!< 0x00000700 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk (0x7U << IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX5 IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PA2, CMD/PA3 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX0 0x00000000U /*!< D0/PC8, D1/PC9, D2/PC10, D3/PC11, D4/PB8, D5/PB9, D6/PC6, D7/PC7, CK/PC12, CMD/PD2 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos (10U) /*!< 0x00000400 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk (0x1U << IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX4 IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos (8U) /*!< 0x00000500 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk (0x5U << IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX5 IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos (9U) /*!< 0x00000600 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk (0x3U << IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX6 IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PA2, CMD/PA3 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos (8U) /*!< 0x00000700 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk (0x7U << IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX7 IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PA2, CMD/PA3 */ /*!< USART1_GMUX configuration */ #define IOMUX_REMAP6_USART1_GMUX_Pos (16U) @@ -3114,6 +3162,11 @@ typedef struct #define IOMUX_REMAP6_USART1_GMUX_2 (0x4U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00040000 */ #define IOMUX_REMAP6_USART1_GMUX_3 (0x8U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00080000 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX0 0x00000000U /*!< TX/PA9, RX/PA10 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_USART1_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_USART1_GMUX_MUX1 IOMUX_REMAP6_USART1_GMUX_MUX1_Msk /*!< TX/PB6, RX/PB7 */ + /***************** Bit definition for IOMUX_REMAP7 register *****************/ #define IOMUX_REMAP7_ADC1_ETP_GMUX_Pos (4U) /*!< 0x00000010 */ #define IOMUX_REMAP7_ADC1_ETP_GMUX_Msk (0x1U << IOMUX_REMAP7_ADC1_ETP_GMUX_Pos) @@ -3130,16 +3183,16 @@ typedef struct #define IOMUX_REMAP7_SWJTAG_GMUX_1 (0x2U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00020000 */ #define IOMUX_REMAP7_SWJTAG_GMUX_2 (0x4U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00040000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX1 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIO */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Pos (16U) /*!< 0x00010000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Pos) -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX2 IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Pos (17U) /*!< 0x00020000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Pos) -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX3 IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Msk /*!< Supports SWD. But JTAG is disabled. PA15/PB3/PB4 can be used as GPIO */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Pos (18U) /*!< 0x00040000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Pos) -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX4 IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_RESET 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos (17U) /*!< 0x00020000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk /*!< Supports SWD. But JTAG is disabled. PA15/PB3/PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos (18U) /*!< 0x00040000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIO */ #define IOMUX_REMAP7_PD01_GMUX_Pos (20U) #define IOMUX_REMAP7_PD01_GMUX_Msk (0x1U << IOMUX_REMAP7_PD01_GMUX_Pos) /*!< 0x00100000 */ @@ -3153,6 +3206,17 @@ typedef struct #define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000001 */ #define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos (0U) /*!< 0x00000003 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ + /*!< TMR1_CH1_CMP_GMUX configuration */ #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos (2U) /*!< 0x0000000C */ #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) @@ -3160,6 +3224,17 @@ typedef struct #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000008 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos (2U) /*!< 0x00000004 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos (3U) /*!< 0x00000008 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos (2U) /*!< 0x0000000C */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 channel 1 */ + /*!< TMR2_CH4_CMP_GMUX configuration */ #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos (4U) /*!< 0x00000030 */ #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) @@ -3167,6 +3242,17 @@ typedef struct #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000010 */ #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX0 0x00000000U /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR2_GMUX IO signal is connected to TMR2 channel 4 */ + /*!< TMR3_CH1_CMP_GMUX configuration */ #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos (6U) /*!< 0x000000C0 */ #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) @@ -3174,6 +3260,17 @@ typedef struct #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000080 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos (6U) /*!< 0x00000040 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos (7U) /*!< 0x00000080 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos (6U) /*!< 0x000000C0 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR3_GMUX IO signal is connected to TMR3 channel 1 */ + /******************************************************************************/ /* */ /* External interrupt/Event controller (EXINT) */ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h index d4be36ca467..73392962610 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h @@ -1,7 +1,7 @@ /** ****************************************************************************** * @file at32f415rx.h - * @author Artery Technology & HorrorTroll + * @author Artery Technology & HorrorTroll & Zhaqian * @version v2.1.1 * @date 26-October-2023 * @brief AT32F415Rx header file. @@ -2559,13 +2559,13 @@ typedef struct #define IOMUX_REMAP_USART3_MUX_0 (0x1U << IOMUX_REMAP_USART3_MUX_Pos) /*!< 0x00000010 */ #define IOMUX_REMAP_USART3_MUX_1 (0x2U << IOMUX_REMAP_USART3_MUX_Pos) /*!< 0x00000020 */ -#define IOMUX_REMAP_USART3_MUX_MUX1 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ -#define IOMUX_REMAP_USART3_MUX_MUX2_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP_USART3_MUX_MUX0 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP_USART3_MUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP_USART3_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_USART3_MUX_MUX1_Pos) +#define IOMUX_REMAP_USART3_MUX_MUX1 IOMUX_REMAP_USART3_MUX_MUX1_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP_USART3_MUX_MUX2_Pos (5U) /*!< 0x00000020 */ #define IOMUX_REMAP_USART3_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_USART3_MUX_MUX2_Pos) -#define IOMUX_REMAP_USART3_MUX_MUX2 IOMUX_REMAP_USART3_MUX_MUX2_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ -#define IOMUX_REMAP_USART3_MUX_MUX3_Pos (5U) /*!< 0x00000020 */ -#define IOMUX_REMAP_USART3_MUX_MUX3_Msk (0x1U << IOMUX_REMAP_USART3_MUX_MUX3_Pos) -#define IOMUX_REMAP_USART3_MUX_MUX3 IOMUX_REMAP_USART3_MUX_MUX3_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ +#define IOMUX_REMAP_USART3_MUX_MUX2 IOMUX_REMAP_USART3_MUX_MUX2_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ /*!< TMR1_MUX configuration */ #define IOMUX_REMAP_TMR1_MUX_Pos (6U) @@ -2574,10 +2574,10 @@ typedef struct #define IOMUX_REMAP_TMR1_MUX_0 (0x1U << IOMUX_REMAP_TMR1_MUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP_TMR1_MUX_1 (0x2U << IOMUX_REMAP_TMR1_MUX_Pos /*!< 0x00000080 */ -#define IOMUX_REMAP_TMR1_MUX_MUX1 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ -#define IOMUX_REMAP_TMR1_MUX_MUX2_Pos (6U) -#define IOMUX_REMAP_TMR1_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR1_MUX_MUX2_Pos) /*!< 0x00000040 */ -#define IOMUX_REMAP_TMR1_MUX_MUX2 IOMUX_REMAP_TMR1_MUX_MUX2_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP_TMR1_MUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1_Pos (6U) +#define IOMUX_REMAP_TMR1_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR1_MUX_MUX1_Pos) /*!< 0x00000040 */ +#define IOMUX_REMAP_TMR1_MUX_MUX1 IOMUX_REMAP_TMR1_MUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ /*!< TMR2_MUX configuration */ #define IOMUX_REMAP_TMR2_MUX_Pos (8U) @@ -2586,16 +2586,16 @@ typedef struct #define IOMUX_REMAP_TMR2_MUX_0 (0x1U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000100 */ #define IOMUX_REMAP_TMR2_MUX_1 (0x2U << IOMUX_REMAP_TMR2_MUX_Pos) /*!< 0x00000200 */ -#define IOMUX_REMAP_TMR2_MUX_MUX1 0x00000000U /*!< CH1/EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP_TMR2_MUX_MUX2_Pos (8U) -#define IOMUX_REMAP_TMR2_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX2_Pos) /*!< 0x00000100 */ -#define IOMUX_REMAP_TMR2_MUX_MUX2 IOMUX_REMAP_TMR2_MUX_MUX2_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP_TMR2_MUX_MUX3_Pos (9U) -#define IOMUX_REMAP_TMR2_MUX_MUX3_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX3_Pos) /*!< 0x00000200 */ -#define IOMUX_REMAP_TMR2_MUX_MUX3 IOMUX_REMAP_TMR2_MUX_MUX3_Msk /*!< CH1/EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ -#define IOMUX_REMAP_TMR2_MUX_MUX4_Pos (8U) -#define IOMUX_REMAP_TMR2_MUX_MUX4_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_MUX4_Pos) /*!< 0x00000300 */ -#define IOMUX_REMAP_TMR2_MUX_MUX4 IOMUX_REMAP_TMR2_MUX_MUX4_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP_TMR2_MUX_MUX0 0x00000000U /*!< CH1/EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX1_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX1_Pos) /*!< 0x00000100 */ +#define IOMUX_REMAP_TMR2_MUX_MUX1 IOMUX_REMAP_TMR2_MUX_MUX1_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2_Pos (9U) +#define IOMUX_REMAP_TMR2_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR2_MUX_MUX2_Pos) /*!< 0x00000200 */ +#define IOMUX_REMAP_TMR2_MUX_MUX2 IOMUX_REMAP_TMR2_MUX_MUX2_Msk /*!< CH1/EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3_Pos (8U) +#define IOMUX_REMAP_TMR2_MUX_MUX3_Msk (0x3U << IOMUX_REMAP_TMR2_MUX_MUX3_Pos) /*!< 0x00000300 */ +#define IOMUX_REMAP_TMR2_MUX_MUX3 IOMUX_REMAP_TMR2_MUX_MUX3_Msk /*!< CH1/EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ /*!< TMR3_MUX configuration */ #define IOMUX_REMAP_TMR3_MUX_Pos (10U) @@ -2604,7 +2604,7 @@ typedef struct #define IOMUX_REMAP_TMR3_MUX_0 (0x1U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP_TMR3_MUX_1 (0x2U << IOMUX_REMAP_TMR3_MUX_Pos) /*!< 0x00000800 */ -#define IOMUX_REMAP_TMR3_MUX_MUX1 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP_TMR3_MUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ #define IOMUX_REMAP_TMR3_MUX_MUX2_Pos (11U) #define IOMUX_REMAP_TMR3_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_TMR3_MUX_MUX2_Pos) /*!< 0x00000800 */ #define IOMUX_REMAP_TMR3_MUX_MUX2 IOMUX_REMAP_TMR3_MUX_MUX2_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ @@ -2619,7 +2619,7 @@ typedef struct #define IOMUX_REMAP_CAN1_MUX_0 (0x1U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00002000 */ #define IOMUX_REMAP_CAN1_MUX_1 (0x2U << IOMUX_REMAP_CAN1_MUX_Pos) /*!< 0x00004000 */ -#define IOMUX_REMAP_CAN1_MUX_MUX1 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP_CAN1_MUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ #define IOMUX_REMAP_CAN1_MUX_MUX2_Pos (14U) #define IOMUX_REMAP_CAN1_MUX_MUX2_Msk (0x1U << IOMUX_REMAP_CAN1_MUX_MUX2_Pos) /*!< 0x00004000 */ #define IOMUX_REMAP_CAN1_MUX_MUX2 IOMUX_REMAP_CAN1_MUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ @@ -2967,10 +2967,18 @@ typedef struct /***************** Bit definition for IOMUX_REMAP2 register *****************/ /*!< CMP_MUX configuration */ #define IOMUX_REMAP2_CMP_MUX_Pos (26U) -#define IOMUX_REMAP2_CMP_MUX_Msk (0x3U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x0C000000 */ -#define IOMUX_REMAP2_CMP_MUX IOMUX_REMAP2_CMP_MUX_Msk /*!< CMP_MUX[1:0] bits (CMP internal remap) */ -#define IOMUX_REMAP2_CMP_MUX_0 (0x1U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x04000000 */ -#define IOMUX_REMAP2_CMP_MUX_1 (0x2U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x08000000 */ +#define IOMUX_REMAP2_CMP_MUX_Msk (0x3U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x0C000000 */ +#define IOMUX_REMAP2_CMP_MUX IOMUX_REMAP2_CMP_MUX_Msk /*!< CMP_MUX[1:0] bits (CMP internal remap) */ +#define IOMUX_REMAP2_CMP_MUX_0 (0x1U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_1 (0x2U << IOMUX_REMAP2_CMP_MUX_Pos) /*!< 0x08000000 */ + +#define IOMUX_REMAP2_CMP_MUX_MUX0 0x00000000U /*!< CMP1_OUT is connected to PA0, CMP2_OUT is connected to PA2 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1_Pos (26U) +#define IOMUX_REMAP2_CMP_MUX_MUX1_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX1_Pos) /*!< 0x04000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX1 IOMUX_REMAP2_CMP_MUX_MUX1_Msk /*!< CMP1_OUT is connected to PA6, CMP2_OUT is connected to PA7 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2_Pos (27U) +#define IOMUX_REMAP2_CMP_MUX_MUX2_Msk (0x1U << IOMUX_REMAP2_CMP_MUX_MUX2_Pos) /*!< 0x08000000 */ +#define IOMUX_REMAP2_CMP_MUX_MUX2 IOMUX_REMAP2_CMP_MUX_MUX2_Msk /*!< CMP1_OUT is connected to PA11, CMP2_OUT is connected to PA12 */ /***************** Bit definition for IOMUX_REMAP3 register *****************/ /*!< TMR9_GMUX configuration */ @@ -2982,6 +2990,11 @@ typedef struct #define IOMUX_REMAP3_TMR9_GMUX_2 (0x4U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP3_TMR9_GMUX_3 (0x8U << IOMUX_REMAP3_TMR9_GMUX_Pos) /*!< 0x00000008 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX0 0x00000000U /*!< CH1/PA2, CH2/PA3 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR9_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR9_GMUX_MUX2 IOMUX_REMAP3_TMR9_GMUX_MUX2_Msk /*!< CH1/PB14, CH2/PB15 */ + /*!< TMR10_GMUX configuration */ #define IOMUX_REMAP3_TMR10_GMUX_Pos (4U) #define IOMUX_REMAP3_TMR10_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x000000F0 */ @@ -2991,6 +3004,11 @@ typedef struct #define IOMUX_REMAP3_TMR10_GMUX_2 (0x4U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP3_TMR10_GMUX_3 (0x8U << IOMUX_REMAP3_TMR10_GMUX_Pos) /*!< 0x00000080 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX0 0x00000000U /*!< CH1/PB8 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR10_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR10_GMUX_MUX2 IOMUX_REMAP3_TMR10_GMUX_MUX2_Msk /*!< CH1/PA6 */ + /*!< TMR11_GMUX configuration */ #define IOMUX_REMAP3_TMR11_GMUX_Pos (8U) #define IOMUX_REMAP3_TMR11_GMUX_Msk (0xFU << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000F00 */ @@ -3000,6 +3018,11 @@ typedef struct #define IOMUX_REMAP3_TMR11_GMUX_2 (0x4U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP3_TMR11_GMUX_3 (0x8U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000800 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX0 0x00000000U /*!< CH1/PB9 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000002 */ +#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos) +#define IOMUX_REMAP3_TMR11_GMUX_MUX2 IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk /*!< CH1/PA7 */ + /***************** Bit definition for IOMUX_REMAP4 register *****************/ /*!< TMR1_GMUX configuration */ #define IOMUX_REMAP4_TMR1_GMUX_Pos (0U) @@ -3010,13 +3033,13 @@ typedef struct #define IOMUX_REMAP4_TMR1_GMUX_2 (0x4U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP4_TMR1_GMUX_3 (0x8U << IOMUX_REMAP4_TMR1_GMUX_Pos) /*!< 0x00000008 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX1 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX0 0x00000000U /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PB12, CH1C/PB13, CH2C/PB14, CH3C/PB15 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR1_GMUX_MUX1 IOMUX_REMAP4_TMR1_GMUX_MUX1_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ #define IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX2_Pos) -#define IOMUX_REMAP4_TMR1_GMUX_MUX2 IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk /*!< EXT/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX3_Pos (1U) /*!< 0x00000002 */ -#define IOMUX_REMAP4_TMR1_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP4_TMR1_GMUX_MUX3_Pos) -#define IOMUX_REMAP4_TMR1_GMUX_MUX3 IOMUX_REMAP4_TMR1_GMUX_MUX3_Msk /*!< EXT/PA0, CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ +#define IOMUX_REMAP4_TMR1_GMUX_MUX2 IOMUX_REMAP4_TMR1_GMUX_MUX2_Msk /*!< EXT/PA0, CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9, BRK/PA6, CH1C/PA7, CH2C/PB0, CH3C/PB1 */ /*!< TMR2_GMUX configuration */ #define IOMUX_REMAP4_TMR2_GMUX_Pos (4U) @@ -3026,16 +3049,16 @@ typedef struct #define IOMUX_REMAP4_TMR2_GMUX_1 (0x2U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000020 */ #define IOMUX_REMAP4_TMR2_GMUX_2 (0x4U << IOMUX_REMAP4_TMR2_GMUX_Pos) /*!< 0x00000040 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX1 0x00000000U /*!< CH1_EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX0 0x00000000U /*!< CH1_EXT/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX1 IOMUX_REMAP4_TMR2_GMUX_MUX1_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ #define IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX2_Pos) -#define IOMUX_REMAP4_TMR2_GMUX_MUX2 IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PA2, CH4/PA3 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos (5U) /*!< 0x00000020 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos) -#define IOMUX_REMAP4_TMR2_GMUX_MUX3 IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk /*!< CH1_EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX4_Pos (4U) /*!< 0x00000030 */ -#define IOMUX_REMAP4_TMR2_GMUX_MUX4_Msk (0x3U << IOMUX_REMAP4_TMR2_GMUX_MUX4_Pos) -#define IOMUX_REMAP4_TMR2_GMUX_MUX4 IOMUX_REMAP4_TMR2_GMUX_MUX4_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX2 IOMUX_REMAP4_TMR2_GMUX_MUX2_Msk /*!< CH1_EXT/PA0, CH2/PA1, CH3/PB10, CH4/PB11 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP4_TMR2_GMUX_MUX3_Pos) +#define IOMUX_REMAP4_TMR2_GMUX_MUX3 IOMUX_REMAP4_TMR2_GMUX_MUX3_Msk /*!< CH1_EXT/PA15, CH2/PB3, CH3/PB10, CH4/PB11 */ /*!< TMR3_GMUX configuration */ #define IOMUX_REMAP4_TMR3_GMUX_Pos (8U) @@ -3046,6 +3069,11 @@ typedef struct #define IOMUX_REMAP4_TMR3_GMUX_2 (0x4U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP4_TMR3_GMUX_3 (0x8U << IOMUX_REMAP4_TMR3_GMUX_Pos) /*!< 0x00000800 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX0 0x00000000U /*!< CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR3_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR3_GMUX_MUX1 IOMUX_REMAP4_TMR3_GMUX_MUX1_Msk /*!< CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1 */ + /*!< TMR5_GMUX configuration */ #define IOMUX_REMAP4_TMR5_GMUX_Pos (16U) #define IOMUX_REMAP4_TMR5_GMUX_Msk (0x7U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00070000 */ @@ -3054,6 +3082,11 @@ typedef struct #define IOMUX_REMAP4_TMR5_GMUX_1 (0x2U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00020000 */ #define IOMUX_REMAP4_TMR5_GMUX_2 (0x4U << IOMUX_REMAP4_TMR5_GMUX_Pos) /*!< 0x00040000 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX0 0x00000000U /*!< CH1/PA0, CH2/PA1, CH3/PA2, CH4/PA3 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP4_TMR5_GMUX_MUX1_Pos) +#define IOMUX_REMAP4_TMR5_GMUX_MUX1 IOMUX_REMAP4_TMR5_GMUX_MUX1_Msk /*!< CH1/PF4, CH2/PF5, CH3/PA2, CH4/PA3 */ + #define IOMUX_REMAP4_TMR5CH4_GMUX_Pos (19U) #define IOMUX_REMAP4_TMR5CH4_GMUX_Msk (0x1U << IOMUX_REMAP4_TMR5CH4_GMUX_Pos) /*!< 0x00080000 */ #define IOMUX_REMAP4_TMR5CH4_GMUX IOMUX_REMAP4_TMR5CH4_GMUX_Msk /*!< TMR5 channel 4 general multiplexing */ @@ -3068,13 +3101,13 @@ typedef struct #define IOMUX_REMAP5_I2C1_GMUX_2 (0x4U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP5_I2C1_GMUX_3 (0x8U << IOMUX_REMAP5_I2C1_GMUX_Pos) /*!< 0x00000080 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX1 0x00000000U /*!< SCL/PB6, SDA/PB7, SMBA/PB5 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX0 0x00000000U /*!< SCL/PB6, SDA/PB7, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C1_GMUX_MUX1 IOMUX_REMAP5_I2C1_GMUX_MUX1_Msk /*!< SCL/PB8, SDA/PB9, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ #define IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX2_Pos) -#define IOMUX_REMAP5_I2C1_GMUX_MUX2 IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk /*!< SCL/PB8, SDA/PB9, SMBA/PB5 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX3_Pos (5U) /*!< 0x00000020 */ -#define IOMUX_REMAP5_I2C1_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP5_I2C1_GMUX_MUX3_Pos) -#define IOMUX_REMAP5_I2C1_GMUX_MUX3 IOMUX_REMAP5_I2C1_GMUX_MUX3_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PB5 */ +#define IOMUX_REMAP5_I2C1_GMUX_MUX2 IOMUX_REMAP5_I2C1_GMUX_MUX2_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PB5 */ /*!< I2C2_GMUX configuration */ #define IOMUX_REMAP5_I2C2_GMUX_Pos (8U) @@ -3085,16 +3118,16 @@ typedef struct #define IOMUX_REMAP5_I2C2_GMUX_2 (0x4U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP5_I2C2_GMUX_3 (0x8U << IOMUX_REMAP5_I2C2_GMUX_Pos) /*!< 0x00000800 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX1 0x00000000U /*!< SCL/PB10, SDA/PB11, SMBA/PB12 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX0 0x00000000U /*!< SCL/PB10, SDA/PB11, SMBA/PB12 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos (8U) /*!< 0x00000100 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX1 IOMUX_REMAP5_I2C2_GMUX_MUX1_Msk /*!< SCL/PA8, SDA/PC9, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos (9U) /*!< 0x00000200 */ #define IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX2_Pos) -#define IOMUX_REMAP5_I2C2_GMUX_MUX2 IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk /*!< SCL/PA8, SDA/PC9, SMBA/PA9 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos (9U) /*!< 0x00000200 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos) -#define IOMUX_REMAP5_I2C2_GMUX_MUX3 IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk /*!< SCL/PA8, SDA/PB4, SMBA/PA9 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX4_Pos (8U) /*!< 0x00000300 */ -#define IOMUX_REMAP5_I2C2_GMUX_MUX4_Msk (0x3U << IOMUX_REMAP5_I2C2_GMUX_MUX4_Pos) -#define IOMUX_REMAP5_I2C2_GMUX_MUX4 IOMUX_REMAP5_I2C2_GMUX_MUX4_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX2 IOMUX_REMAP5_I2C2_GMUX_MUX2_Msk /*!< SCL/PA8, SDA/PB4, SMBA/PA9 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos (8U) /*!< 0x00000300 */ +#define IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP5_I2C2_GMUX_MUX3_Pos) +#define IOMUX_REMAP5_I2C2_GMUX_MUX3 IOMUX_REMAP5_I2C2_GMUX_MUX3_Msk /*!< SCL/PF6, SDA/PF7, SMBA/PA9 */ /*!< SPI1_GMUX configuration */ #define IOMUX_REMAP5_SPI1_GMUX_Pos (16U) @@ -3105,6 +3138,11 @@ typedef struct #define IOMUX_REMAP5_SPI1_GMUX_2 (0x4U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00040000 */ #define IOMUX_REMAP5_SPI1_GMUX_3 (0x8U << IOMUX_REMAP5_SPI1_GMUX_Pos) /*!< 0x00080000 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX0 0x00000000U /*!< CS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7, MCK/PB0 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI1_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI1_GMUX_MUX1 IOMUX_REMAP5_SPI1_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PB6 */ + /*!< SPI2_GMUX configuration */ #define IOMUX_REMAP5_SPI2_GMUX_Pos (20U) #define IOMUX_REMAP5_SPI2_GMUX_Msk (0xFU << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00F00000 */ @@ -3114,6 +3152,11 @@ typedef struct #define IOMUX_REMAP5_SPI2_GMUX_2 (0x4U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00400000 */ #define IOMUX_REMAP5_SPI2_GMUX_3 (0x8U << IOMUX_REMAP5_SPI2_GMUX_Pos) /*!< 0x00800000 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX0 0x00000000U /*!< CS/PB12, SCK/PB13, MISO/PB14, MOSI/PB15, MCK/PC6 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos (20U) /*!< 0x00100000 */ +#define IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP5_SPI2_GMUX_MUX1_Pos) +#define IOMUX_REMAP5_SPI2_GMUX_MUX1 IOMUX_REMAP5_SPI2_GMUX_MUX1_Msk /*!< CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5, MCK/PC7 */ + /***************** Bit definition for IOMUX_REMAP6 register *****************/ /*!< CAN1_GMUX configuration */ #define IOMUX_REMAP6_CAN1_GMUX_Pos (0U) @@ -3124,6 +3167,11 @@ typedef struct #define IOMUX_REMAP6_CAN1_GMUX_2 (0x4U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP6_CAN1_GMUX_3 (0x8U << IOMUX_REMAP6_CAN1_GMUX_Pos) /*!< 0x00000008 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX0 0x00000000U /*!< RX/PA11, TX/PA12 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_CAN1_GMUX_MUX2_Pos) +#define IOMUX_REMAP6_CAN1_GMUX_MUX2 IOMUX_REMAP6_CAN1_GMUX_MUX2_Msk /*!< RX/PB8, TX/PB9 */ + /*!< SDIO_GMUX configuration */ #define IOMUX_REMAP6_SDIO_GMUX_Pos (8U) #define IOMUX_REMAP6_SDIO_GMUX_Msk (0xFU << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000F00 */ @@ -3133,19 +3181,19 @@ typedef struct #define IOMUX_REMAP6_SDIO_GMUX_2 (0x4U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000400 */ #define IOMUX_REMAP6_SDIO_GMUX_3 (0x8U << IOMUX_REMAP6_SDIO_GMUX_Pos) /*!< 0x00000800 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX1 0x00000000U /*!< D0/PC8, D1/PC9, D2/PC10, D3/PC11, D4/PB8, D5/PB9, D6/PC6, D7/PC7, CK/PC12, CMD/PD2 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX2_Pos (10U) /*!< 0x00000400 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_SDIO_GMUX_MUX2_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX2 IOMUX_REMAP6_SDIO_GMUX_MUX2_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PC4, CMD/PC5 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX3_Pos (8U) /*!< 0x00000500 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX3_Msk (0x5U << IOMUX_REMAP6_SDIO_GMUX_MUX3_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX3 IOMUX_REMAP6_SDIO_GMUX_MUX3_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PC4, CMD/PC5 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos (9U) /*!< 0x00000600 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk (0x3U << IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX4 IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PA2, CMD/PA3 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos (8U) /*!< 0x00000700 */ -#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk (0x7U << IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos) -#define IOMUX_REMAP6_SDIO_GMUX_MUX5 IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PA2, CMD/PA3 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX0 0x00000000U /*!< D0/PC8, D1/PC9, D2/PC10, D3/PC11, D4/PB8, D5/PB9, D6/PC6, D7/PC7, CK/PC12, CMD/PD2 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos (10U) /*!< 0x00000400 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk (0x1U << IOMUX_REMAP6_SDIO_GMUX_MUX4_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX4 IOMUX_REMAP6_SDIO_GMUX_MUX4_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos (8U) /*!< 0x00000500 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk (0x5U << IOMUX_REMAP6_SDIO_GMUX_MUX5_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX5 IOMUX_REMAP6_SDIO_GMUX_MUX5_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PC4, CMD/PC5 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos (9U) /*!< 0x00000600 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk (0x3U << IOMUX_REMAP6_SDIO_GMUX_MUX6_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX6 IOMUX_REMAP6_SDIO_GMUX_MUX6_Msk /*!< D0/PC0, D1/PC1, D2/PC2, D3/PC3, D4/PA4, D5/PA5, D6/PA6, D7/PA7, CK/PA2, CMD/PA3 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos (8U) /*!< 0x00000700 */ +#define IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk (0x7U << IOMUX_REMAP6_SDIO_GMUX_MUX7_Pos) +#define IOMUX_REMAP6_SDIO_GMUX_MUX7 IOMUX_REMAP6_SDIO_GMUX_MUX7_Msk /*!< D0/PA4, D1/PA5, D2/PA6, D3/PA7, CK/PA2, CMD/PA3 */ /*!< USART1_GMUX configuration */ #define IOMUX_REMAP6_USART1_GMUX_Pos (16U) @@ -3156,6 +3204,11 @@ typedef struct #define IOMUX_REMAP6_USART1_GMUX_2 (0x4U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00040000 */ #define IOMUX_REMAP6_USART1_GMUX_3 (0x8U << IOMUX_REMAP6_USART1_GMUX_Pos) /*!< 0x00080000 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX0 0x00000000U /*!< TX/PA9, RX/PA10 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP6_USART1_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_USART1_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_USART1_GMUX_MUX1 IOMUX_REMAP6_USART1_GMUX_MUX1_Msk /*!< TX/PB6, RX/PB7 */ + /*!< USART3_GMUX configuration */ #define IOMUX_REMAP6_USART3_GMUX_Pos (24U) #define IOMUX_REMAP6_USART3_GMUX_Msk (0xFU << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x0F000000 */ @@ -3165,13 +3218,13 @@ typedef struct #define IOMUX_REMAP6_USART3_GMUX_2 (0x4U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x04000000 */ #define IOMUX_REMAP6_USART3_GMUX_3 (0x8U << IOMUX_REMAP6_USART3_GMUX_Pos) /*!< 0x08000000 */ -#define IOMUX_REMAP6_USART3_GMUX_MUX1 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ -#define IOMUX_REMAP6_USART3_GMUX_MUX2_Pos (24U) /*!< 0x01000000 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX0 0x00000000U /*!< TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX1_Pos (24U) /*!< 0x01000000 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_USART3_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_USART3_GMUX_MUX1 IOMUX_REMAP6_USART3_GMUX_MUX1_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX2_Pos (25U) /*!< 0x02000000 */ #define IOMUX_REMAP6_USART3_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP6_USART3_GMUX_MUX2_Pos) -#define IOMUX_REMAP6_USART3_GMUX_MUX2 IOMUX_REMAP6_USART3_GMUX_MUX2_Msk /*!< TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 */ -#define IOMUX_REMAP6_USART3_GMUX_MUX3_Pos (25U) /*!< 0x02000000 */ -#define IOMUX_REMAP6_USART3_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP6_USART3_GMUX_MUX3_Pos) -#define IOMUX_REMAP6_USART3_GMUX_MUX3 IOMUX_REMAP6_USART3_GMUX_MUX3_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ +#define IOMUX_REMAP6_USART3_GMUX_MUX2 IOMUX_REMAP6_USART3_GMUX_MUX2_Msk /*!< TX/PA7, RX/PA6, CK/PA5, CTS/PB1, RTS/PB0 */ /*!< UART4_GMUX configuration */ #define IOMUX_REMAP6_UART4_GMUX_Pos (28U) @@ -3182,6 +3235,11 @@ typedef struct #define IOMUX_REMAP6_UART4_GMUX_2 (0x4U << IOMUX_REMAP6_UART4_GMUX_Pos) /*!< 0x40000000 */ #define IOMUX_REMAP6_UART4_GMUX_3 (0x8U << IOMUX_REMAP6_UART4_GMUX_Pos) /*!< 0x80000000 */ +#define IOMUX_REMAP6_UART4_GMUX_MUX0 0x00000000U /*!< TX/PC10, RX/PC11 */ +#define IOMUX_REMAP6_UART4_GMUX_MUX1_Pos (28U) /*!< 0x10000000 */ +#define IOMUX_REMAP6_UART4_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP6_UART4_GMUX_MUX1_Pos) +#define IOMUX_REMAP6_UART4_GMUX_MUX1 IOMUX_REMAP6_UART4_GMUX_MUX1_Msk /*!< TX/PF4, RX/PF5 */ + /***************** Bit definition for IOMUX_REMAP7 register *****************/ #define IOMUX_REMAP7_ADC1_ETP_GMUX_Pos (4U) /*!< 0x00000010 */ #define IOMUX_REMAP7_ADC1_ETP_GMUX_Msk (0x1U << IOMUX_REMAP7_ADC1_ETP_GMUX_Pos) @@ -3198,16 +3256,16 @@ typedef struct #define IOMUX_REMAP7_SWJTAG_GMUX_1 (0x2U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00020000 */ #define IOMUX_REMAP7_SWJTAG_GMUX_2 (0x4U << IOMUX_REMAP7_SWJTAG_GMUX_Pos) /*!< 0x00040000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX1 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIO */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Pos (16U) /*!< 0x00010000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Pos) -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX2 IOMUX_REMAP7_SWJTAG_GMUX_MUX2_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Pos (17U) /*!< 0x00020000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Pos) -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX3 IOMUX_REMAP7_SWJTAG_GMUX_MUX3_Msk /*!< Supports SWD. But JTAG is disabled. PA15/PB3/PB4 can be used as GPIO */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Pos (18U) /*!< 0x00040000 */ -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Pos) -#define IOMUX_REMAP7_SWJTAG_GMUX_MUX4 IOMUX_REMAP7_SWJTAG_GMUX_MUX4_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_RESET 0x00000000U /*!< Supports SWD and JTAG. All SWJTAG pins cannot be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos (16U) /*!< 0x00010000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST IOMUX_REMAP7_SWJTAG_GMUX_NONJTRST_Msk /*!< Supports SWD and JTAG. NJTRST is disabled. PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos (17U) /*!< 0x00020000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS IOMUX_REMAP7_SWJTAG_GMUX_JTAGDIS_Msk /*!< Supports SWD. But JTAG is disabled. PA15/PB3/PB4 can be used as GPIO */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos (18U) /*!< 0x00040000 */ +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk (0x1U << IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Pos) +#define IOMUX_REMAP7_SWJTAG_GMUX_DISABLE IOMUX_REMAP7_SWJTAG_GMUX_DISABLE_Msk /*!< SWD and JTAG are disabled. All SWJTAG pins can be used as GPIO */ #define IOMUX_REMAP7_PD01_GMUX_Pos (20U) #define IOMUX_REMAP7_PD01_GMUX_Msk (0x1U << IOMUX_REMAP7_PD01_GMUX_Pos) /*!< 0x00100000 */ @@ -3221,6 +3279,17 @@ typedef struct #define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000001 */ #define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000002 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 BRK channel 1 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos (0U) /*!< 0x00000003 */ +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */ + /*!< TMR1_CH1_CMP_GMUX configuration */ #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos (2U) /*!< 0x0000000C */ #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) @@ -3228,6 +3297,17 @@ typedef struct #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000004 */ #define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000008 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos (2U) /*!< 0x00000004 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos (3U) /*!< 0x00000008 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 channel 1 */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos (2U) /*!< 0x0000000C */ +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR1_GMUX IO signal is connected to TMR1 channel 1 */ + /*!< TMR2_CH4_CMP_GMUX configuration */ #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos (4U) /*!< 0x00000030 */ #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) @@ -3235,6 +3315,17 @@ typedef struct #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000010 */ #define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000020 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX0 0x00000000U /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR2 channel 4 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos (4U) /*!< 0x00000030 */ +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR2_GMUX IO signal is connected to TMR2 channel 4 */ + /*!< TMR3_CH1_CMP_GMUX configuration */ #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos (6U) /*!< 0x000000C0 */ #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) @@ -3242,6 +3333,17 @@ typedef struct #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_0 (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000040 */ #define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000080 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos (6U) /*!< 0x00000040 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos (7U) /*!< 0x00000080 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR3 channel 1 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos (6U) /*!< 0x000000C0 */ +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk (0x3U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Pos) +#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX3_Msk /*!< Either CMP output signal or TMR3_GMUX IO signal is connected to TMR3 channel 1 */ + /******************************************************************************/ /* */ /* External interrupt/Event controller (EXINT) */ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h index 6e452d5d7e7..e6a798bae52 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h @@ -1,7 +1,7 @@ /** ************************************************************************** * @file system_at32f415.h - * @author Artery Technology & HorrorTroll + * @author Artery Technology & HorrorTroll & Zhaqian * @brief CMSIS AT32F415 system header file * ************************************************************************** diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld index 96fa2d3d763..f42f326a338 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld @@ -1,6 +1,7 @@ /* - Copyright (C) 2023 Artery Technology - Copyright (C) 2023 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2024 Artery Technology + Copyright (C) 2023..2024 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2024 Zhaqian (https://github.com/zhaqian12) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld index 8b6567a88ac..5ddf72c8f73 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld @@ -1,6 +1,7 @@ /* - Copyright (C) 2023 Artery Technology - Copyright (C) 2023 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2024 Artery Technology + Copyright (C) 2023..2024 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2024 Zhaqian (https://github.com/zhaqian12) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld index 7de8ff4f2ba..4625d97aa9e 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld @@ -1,6 +1,7 @@ /* - Copyright (C) 2023 Artery Technology - Copyright (C) 2023 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2024 Artery Technology + Copyright (C) 2023..2024 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2024 Zhaqian (https://github.com/zhaqian12) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h b/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h index a8b76f1bce1..0e45ffc6168 100644 --- a/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h +++ b/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h @@ -1,8 +1,8 @@ /* ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio. - (C) 2015 RedoX https://github.com/RedoXyde - (C) 2023 HorrorTroll (https://github.com/HorrorTroll) - (C) 2023 Zhaqian (https://github.com/zhaqian12) + (C) 2015 RedoX (https://github.com/RedoXyde) + (C) 2023-2024 HorrorTroll (https://github.com/HorrorTroll) + (C) 2023-2024 Zhaqian (https://github.com/zhaqian12) This file is part of ChibiOS/RT. diff --git a/os/hal/boards/AT_START_F415/board.c b/os/hal/boards/AT_START_F415/board.c index fac67529781..ef92f8d7691 100644 --- a/os/hal/boards/AT_START_F415/board.c +++ b/os/hal/boards/AT_START_F415/board.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/boards/AT_START_F415/board.h b/os/hal/boards/AT_START_F415/board.h index c74e912d668..ae3de31e480 100644 --- a/os/hal/boards/AT_START_F415/board.h +++ b/os/hal/boards/AT_START_F415/board.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -45,6 +45,7 @@ */ #define GPIOA_ARD_A0 0U #define GPIOA_ADC1_IN0 0U +#define GPIOA_BUTTON 0U #define GPIOA_ARD_A1 1U #define GPIOA_ADC1_IN1 1U #define GPIOA_ARD_D1 2U @@ -106,7 +107,9 @@ #define GPIOC_PIN14 14U #define GPIOC_PIN15 15U +#define GPIOD_OSC_IN 0U #define GPIOD_PIN0 0U +#define GPIOD_OSC_OUT 1U #define GPIOD_PIN1 1U #define GPIOD_PIN2 2U #define GPIOD_PIN3 3U @@ -167,12 +170,13 @@ /* * Port A setup. * Everything input with pull-up except: + * PA0 - Normal input (GPIOA_BUTTON) * PA2 - Alternate output (GPIOA_ARD_D1, GPIOA_USART2_TX) * PA3 - Normal input (GPIOA_ARD_D0, GPIOA_USART2_RX) * PA13 - Pull-up input (GPIOA_SWDIO) * PA14 - Pull-down input (GPIOA_SWCLK) */ -#define VAL_GPIOACFGLR 0x88884B88 /* PA7...PA0 */ +#define VAL_GPIOACFGLR 0x88884B84 /* PA7...PA0 */ #define VAL_GPIOACFGHR 0x88888888 /* PA15...PA8 */ #define VAL_GPIOAODT 0xFFFFFFFF @@ -199,8 +203,10 @@ /* * Port D setup. + * PD0 - Normal input (GPIOD_OSC_IN). + * PD1 - Normal input (GPIOD_OSC_OUT). */ -#define VAL_GPIODCFGLR 0x88888888 /* PD7...PD0 */ +#define VAL_GPIODCFGLR 0x88888844 /* PD7...PD0 */ #define VAL_GPIODCFGHR 0x88888888 /* PD15...PD8 */ #define VAL_GPIODODT 0xFFFFFFFF diff --git a/os/hal/boards/AT_START_F415/board.mk b/os/hal/boards/AT_START_F415/board.mk index 60673b374e7..ae0eab3ba70 100644 --- a/os/hal/boards/AT_START_F415/board.mk +++ b/os/hal/boards/AT_START_F415/board.mk @@ -1,8 +1,8 @@ # List of all the board related files. -BOARDSRC = $(BOARDDIR)/board.c +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.c # Required include directories -BOARDINC = $(BOARDDIR) +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/AT_START_F415 # Shared variables ALLCSRC += $(BOARDSRC) diff --git a/os/hal/ports/AT32/AT32F415/at32_crm.h b/os/hal/ports/AT32/AT32F415/at32_crm.h index 6682e3d09f0..0c42907f635 100644 --- a/os/hal/ports/AT32/AT32F415/at32_crm.h +++ b/os/hal/ports/AT32/AT32F415/at32_crm.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/at32_dmamux.h b/os/hal/ports/AT32/AT32F415/at32_dmamux.h index d037875c35c..a584394b20b 100644 --- a/os/hal/ports/AT32/AT32F415/at32_dmamux.h +++ b/os/hal/ports/AT32/AT32F415/at32_dmamux.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/at32_isr.c b/os/hal/ports/AT32/AT32F415/at32_isr.c index e09d9987bc3..0ffb9991404 100644 --- a/os/hal/ports/AT32/AT32F415/at32_isr.c +++ b/os/hal/ports/AT32/AT32F415/at32_isr.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/at32_isr.h b/os/hal/ports/AT32/AT32F415/at32_isr.h index 743d772ddaf..239867cc1a9 100644 --- a/os/hal/ports/AT32/AT32F415/at32_isr.h +++ b/os/hal/ports/AT32/AT32F415/at32_isr.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/at32_registry.h b/os/hal/ports/AT32/AT32F415/at32_registry.h index 5df65aa8ca2..859e24d829c 100644 --- a/os/hal/ports/AT32/AT32F415/at32_registry.h +++ b/os/hal/ports/AT32/AT32F415/at32_registry.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/hal_efl_lld.c b/os/hal/ports/AT32/AT32F415/hal_efl_lld.c index c11392df734..f14e0b1ca3f 100644 --- a/os/hal/ports/AT32/AT32F415/hal_efl_lld.c +++ b/os/hal/ports/AT32/AT32F415/hal_efl_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/hal_efl_lld.h b/os/hal/ports/AT32/AT32F415/hal_efl_lld.h index 4e0ee81cdba..327d3cfb37f 100644 --- a/os/hal/ports/AT32/AT32F415/hal_efl_lld.h +++ b/os/hal/ports/AT32/AT32F415/hal_efl_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/hal_lld.c b/os/hal/ports/AT32/AT32F415/hal_lld.c index f2ea0ecc8f2..40bacd1d27e 100644 --- a/os/hal/ports/AT32/AT32F415/hal_lld.c +++ b/os/hal/ports/AT32/AT32F415/hal_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/hal_lld.h b/os/hal/ports/AT32/AT32F415/hal_lld.h index 2bc994b5142..d1c8375fb28 100644 --- a/os/hal/ports/AT32/AT32F415/hal_lld.h +++ b/os/hal/ports/AT32/AT32F415/hal_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c index a9ec8d45b84..0f42b0a5edf 100644 --- a/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c +++ b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h index ef9aa436419..a54d9b8988f 100644 --- a/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h +++ b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c index 6bd23bad5e5..be862b066be 100644 --- a/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c +++ b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h index 70fb7b0dea9..c09aecee36c 100644 --- a/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h +++ b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c index be2403bf71c..562d860d334 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h index f8c0dd51e06..138f14fdbc9 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc index e629cc20ffa..8b66e3fa467 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc index 735ad42d2af..e33a9e57b87 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc index 36796f3cef0..222415d5102 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc index 333e01153bb..9c0b7db12f7 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc index 9dd3eaa8e68..9d6d39e6bb4 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc index c8fed0c1c9c..644488de5bd 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc index ba5f251164b..f6ccd700637 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc index 64e7729ab58..43caec1e481 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc index ff822700ba2..6eaef171749 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc index bbbec9f4701..2f3e1ee21b9 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc index 0cf865ded07..b202b57e575 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc index 185f056e87c..883d82bc7b6 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc index f3cf03627be..3388a97493e 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc index 280d3557c27..56cc2b499bd 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c index 03269419094..ee967c7cff8 100644 --- a/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c +++ b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h index 2d2646435f5..8cc3136781d 100644 --- a/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h +++ b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c index 119951b91c4..6e6482301ad 100644 --- a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c +++ b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h index 38ba737d608..ca73059d073 100644 --- a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h +++ b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h b/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h index 654b3cb5167..5f670e430d4 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h +++ b/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c index e2605d5719a..1801e04f4e4 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c +++ b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h index 22189fa392c..d205b2be5ad 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h +++ b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c index c362f261c8a..e9e0c193583 100644 --- a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c +++ b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h index 546ac56b63b..f7bcdda1cde 100644 --- a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h +++ b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c index bf96e26ac4c..5a1398ef2db 100644 --- a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c +++ b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h index 8b8d0197e98..d2abef7203d 100644 --- a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h +++ b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c index 61ad5ac9f0f..fd23d1d6f6b 100644 --- a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c +++ b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h index 729ae013000..d53329abc64 100644 --- a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h +++ b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023 HorrorTroll - ChibiOS - Copyright (C) 2023 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h index 325c8b7f11f..18411700c03 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc index 313960903b5..d4d536d15b1 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc index 8fcb0cc7d49..6198264c286 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc index 9ae8bdd9fcd..5c2ea3954e6 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc index b6f2d5df087..dbecd46685a 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc index 4af53092ec7..1f860cf0070 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c index cbb077b1b71..c10cc749e39 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h index eb0dbfe446e..d3ba5ffb65e 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c index ce8e0b2cd05..06ad33b8475 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h index 08c775a6350..b101125433e 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c index d6d258bbef4..f894318dfd9 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h index 509d2e1dc9a..5a40b54841b 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc index 6d680ca460e..c07c8ff8c6f 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc +++ b/os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc index 11873729acb..fff0dadae38 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc +++ b/os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc index b782fa7936d..f215b4f7c76 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc +++ b/os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc index c30500e1984..1652352b72e 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc +++ b/os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc index 705aaf3cdcf..a00a1a09ada 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc +++ b/os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c index 96b5b47194a..bbb1d2dd6fa 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h index f0b0e43271d..41da42389e3 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c index fcecd4f163b..a64e692c25f 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h index 9a9e400b60a..e47ae7c1c57 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c index 832b134f9ec..79181e464d6 100644 --- a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c +++ b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h index 6870d2057c4..ffd40da6954 100644 --- a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h +++ b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 HorrorTroll - ChibiOS - Copyright (C) 2024 Zhaqian + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/AT32F415/PWM-ICU/.cproject b/testhal/AT32/AT32F415/PWM-ICU/.cproject new file mode 100644 index 00000000000..6caf490fe75 --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/.cproject @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/AT32F415/PWM-ICU/.project b/testhal/AT32/AT32F415/PWM-ICU/.project new file mode 100644 index 00000000000..a94f918b024 --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/.project @@ -0,0 +1,33 @@ + + + AT32F415-PWM-ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/AT32/AT32F415/PWM-ICU/Makefile b/testhal/AT32/AT32F415/PWM-ICU/Makefile new file mode 100644 index 00000000000..a00e20a67fc --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/Makefile @@ -0,0 +1,236 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../../ +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h b/testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h new file mode 100644 index 00000000000..6ae2a5be1bd --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h @@ -0,0 +1,819 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h b/testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h new file mode 100644 index 00000000000..099dca49dad --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h b/testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h new file mode 100644 index 00000000000..a8222ec6349 --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h @@ -0,0 +1,222 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define AT32F415_MCUCONF + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define AT32_NO_INIT FALSE +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 TRUE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 TRUE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_HOST_WAKEUP_DURATION 2 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/AT32F415/PWM-ICU/main.c b/testhal/AT32/AT32F415/PWM-ICU/main.c new file mode 100644 index 00000000000..4f22f79cec5 --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/main.c @@ -0,0 +1,145 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static void pwmpcb(PWMDriver *pwmp) { + + (void)pwmp; + palSetPad(IOPORT3, GPIOC_LED_GREEN); +} + +static void pwmc1cb(PWMDriver *pwmp) { + + (void)pwmp; + palClearPad(IOPORT3, GPIOC_LED_GREEN); +} + +static PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, + 0, + 0 +}; + +icucnt_t last_width, last_period; + +static void icuwidthcb(ICUDriver *icup) { + + last_width = icuGetWidthX(icup); +} + +static void icuperiodcb(ICUDriver *icup) { + + last_period = icuGetPeriodX(icup); +} + +static ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + NULL, + ICU_CHANNEL_1, + 0U, + 0xFFFFFFFFU +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * LED initially off. + */ + palSetPad(IOPORT3, GPIOC_LED_GREEN); + + /* + * Initializes the PWM driver 1 and ICU driver 4. + */ + pwmStart(&PWMD1, &pwmcfg); + pwmEnablePeriodicNotification(&PWMD1); + palSetPadMode(IOPORT1, 8, PAL_MODE_AT32_ALTERNATE_PUSHPULL); + icuStart(&ICUD4, &icucfg); + icuStartCapture(&ICUD4); + icuEnableNotifications(&ICUD4); + chThdSleepMilliseconds(2000); + + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500)); + pwmEnableChannelNotification(&PWMD1, 0); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PWMD1, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0 and stops the drivers. + */ + pwmDisableChannel(&PWMD1, 0); + pwmStop(&PWMD1); + icuStopCapture(&ICUD4); + icuStop(&ICUD4); + palSetPad(IOPORT3, GPIOC_LED_GREEN); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (true) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/AT32/AT32F415/PWM-ICU/readme.txt b/testhal/AT32/AT32F415/PWM-ICU/readme.txt new file mode 100644 index 00000000000..831073bf7df --- /dev/null +++ b/testhal/AT32/AT32F415/PWM-ICU/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/HAL - PWM/ICU driver demo for AT32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an AT-START-F415 board. + +** The Demo ** + +The application demonstrates the use of the AT32 PWM and ICU drivers. Pins +PA8 and PB6 must be connected in order to trigger the ICU input with the +PWM output. The ICU unit will measure the generated PWM. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +Artery Technology and are licensed under a different license. +Also note that not all the files present in the AT library are distributed +with ChibiOS/RT, you can find the whole library on the AT web site: + + https://www.arterychip.com/en diff --git a/testhal/AT32/AT32F415/USB_CDC/.cproject b/testhal/AT32/AT32F415/USB_CDC/.cproject new file mode 100644 index 00000000000..7e9524dabe8 --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/AT32F415/USB_CDC/.project b/testhal/AT32/AT32F415/USB_CDC/.project new file mode 100644 index 00000000000..d38abd8218e --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/.project @@ -0,0 +1,49 @@ + + + AT32F415-USB_CDC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS_CONTRIB/os/hal/boards/AT_START_F415 + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + + + CHIBIOS_CONTRIB + file:/E:/Duc/Secrets/QMK_custom_mcu/at32_test_qmk/lib/chibios-contrib + + + diff --git a/testhal/AT32/AT32F415/USB_CDC/Makefile b/testhal/AT32/AT32F415/USB_CDC/Makefile new file mode 100644 index 00000000000..cd0e85a6dda --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/Makefile @@ -0,0 +1,238 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../../ +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + usbcfg.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h b/testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h new file mode 100644 index 00000000000..6ae2a5be1bd --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h @@ -0,0 +1,819 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/AT32F415/USB_CDC/cfg/halconf.h b/testhal/AT32/AT32F415/USB_CDC/cfg/halconf.h new file mode 100644 index 00000000000..54dcee08771 --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/cfg/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h b/testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h new file mode 100644 index 00000000000..cdc11f27bfe --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h @@ -0,0 +1,222 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define AT32F415_MCUCONF + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define AT32_NO_INIT FALSE +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 TRUE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_HOST_WAKEUP_DURATION 2 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/AT32F415/USB_CDC/main.c b/testhal/AT32/AT32F415/USB_CDC/main.c new file mode 100644 index 00000000000..6bf5791d5a3 --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/main.c @@ -0,0 +1,160 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" + +#include "shell.h" +#include "chprintf.h" + +#include "usbcfg.h" + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) + +/* Can be measured using dd if=/dev/xxxx of=/dev/null bs=512 count=10000.*/ +static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { + static uint8_t buf[] = + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: write\r\n"); + return; + } + + while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) { +#if 1 + /* Writing in channel mode.*/ + chnWrite(&SDU1, buf, sizeof buf - 1); +#else + /* Writing in buffer mode.*/ + (void) obqGetEmptyBufferTimeout(&SDU1.obqueue, TIME_INFINITE); + memcpy(SDU1.obqueue.ptr, buf, SERIAL_USB_BUFFERS_SIZE); + obqPostFullBuffer(&SDU1.obqueue, SERIAL_USB_BUFFERS_SIZE); +#endif + } + chprintf(chp, "\r\n\nstopped\r\n"); +} + +static const ShellCommand commands[] = { + {"write", cmd_write}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&SDU1, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Green LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + systime_t time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500; + palClearPad(IOPORT3, GPIOC_LED_GREEN); + chThdSleepMilliseconds(time); + palSetPad(IOPORT3, GPIOC_LED_GREEN); + chThdSleepMilliseconds(time); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Initializes a serial-over-USB CDC driver. + */ + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1000); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, spawning shells. + */ + while (true) { + if (SDU1.config->usbp->state == USB_ACTIVE) { + thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, + "shell", NORMALPRIO + 1, + shellThread, (void *)&shell_cfg1); + chThdWait(shelltp); /* Waiting termination. */ + } + chThdSleepMilliseconds(1000); + } +} diff --git a/testhal/AT32/AT32F415/USB_CDC/readme.txt b/testhal/AT32/AT32F415/USB_CDC/readme.txt new file mode 100644 index 00000000000..a016a1945e2 --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/HAL - USB-CDC driver demo for AT32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an AT-START-F415 board. + +** The Demo ** + +The application demonstrates the use of the AT32 USB (OTG) driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +Artery Technology and are licensed under a different license. +Also note that not all the files present in the AT library are distributed +with ChibiOS/RT, you can find the whole library on the AT web site: + + https://www.arterychip.com/en diff --git a/testhal/AT32/AT32F415/USB_CDC/usbcfg.c b/testhal/AT32/AT32F415/USB_CDC/usbcfg.c new file mode 100644 index 00000000000..b1afb386b44 --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/usbcfg.c @@ -0,0 +1,344 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x2E3C, /* idVendor (AT). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'A', 0, 'r', 0, 't', 0, 'e', 0, 'r', 0, 'y', 0, ' ', 0, 'T', 0, + 'e', 0, 'c', 0, 'h', 0, 'n', 0, 'o', 0, 'l', 0, 'o', 0, 'g', 0, + 'y', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(56), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, + 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, + 'o', 0, 'r', 0, 't', 0 +}; + +/* + * Serial Number string. + */ +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(8), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Connection event on wakeup.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; diff --git a/testhal/AT32/AT32F415/USB_CDC/usbcfg.h b/testhal/AT32/AT32F415/USB_CDC/usbcfg.h new file mode 100644 index 00000000000..036a822f31b --- /dev/null +++ b/testhal/AT32/AT32F415/USB_CDC/usbcfg.h @@ -0,0 +1,28 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */