diff --git a/demos/WB32/RT-WB32FQ95-GENERIC/cfg/halconf.h b/demos/WB32/RT-WB32FQ95-GENERIC/cfg/halconf.h
index d340d98276..7bc2798c8f 100644
--- a/demos/WB32/RT-WB32FQ95-GENERIC/cfg/halconf.h
+++ b/demos/WB32/RT-WB32FQ95-GENERIC/cfg/halconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -29,7 +29,7 @@
#define HALCONF_H
#define _CHIBIOS_HAL_CONF_
-#define _CHIBIOS_HAL_CONF_VER_8_0_
+#define _CHIBIOS_HAL_CONF_VER_8_4_
#include "mcuconf.h"
diff --git a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx
index 654ac15692..9adafd96d1 100644
--- a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx
+++ b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx
@@ -73,7 +73,7 @@
0
- 1
+ 0
0
1
@@ -101,9 +101,7 @@
0
0
1
- 0
- 0
- 4
+ 3
@@ -148,24 +146,7 @@
UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)
-
-
- 0
- 0
- 47
- 1
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- ..\main.c
-
-
-
-
+
0
@@ -204,10 +185,6 @@
-
-
-
-
diff --git a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx
index 805d2597cd..7947c2040b 100644
--- a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx
+++ b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx
@@ -10,13 +10,12 @@
Demo
0x4
ARM-ADS
- 5060960::V5.06 update 7 (build 960)::.\ARMCC
- 0
+ 5060422::V5.06 update 4 (build 422)::ARMCC
ARMCM3
ARM
- ARM.CMSIS.5.8.0
+ ARM.CMSIS.5.6.0
http://www.keil.com/pack/
IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE
@@ -184,8 +183,6 @@
0
0
0
- 0
- 0
0
0
8
@@ -326,7 +323,6 @@
0
0
1
- 0
0
0
0
@@ -339,7 +335,7 @@
-UWB32FQ95xx
CORTEX_USE_FPU=0 TEST_CFG_SIZE_REPORT=0 __heap_base__=Image$$$$RW_IRAM1$$$$ZI$$$$Limit __heap_end__=Image$$$$RW_IRAM1$$$$Base
- ..\;..\cfg;..\..\..\..\..\ChibiOS\os\license;..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\ext\ARM\CMSIS\Core\Include;..\..\..\..\..\ChibiOS-Contrib\os\common\ext\CMSIS\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\portability\Keil;..\..\..\..\..\ChibiOS\os\common\ports\ARM-common;..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M;..\..\..\..\..\ChibiOS\os\rt\include;..\..\..\..\..\ChibiOS\os\oslib\include;..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil;..\..\..\..\..\ChibiOS\os\hal\include;..\board;..\..\..\..\..\ChibiOS\os\hal\ports\common\ARMCMx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\LLD\GPIOv1;..\..\..\..\os\hal\ports\WB32\LLD\TIMv1;..\..\..\..\..\ChibiOS\os\test\include;..\..\..\..\..\ChibiOS\test\rt\source\test;..\..\..\..\..\ChibiOS\test\oslib\source\test
+ ..\;..\cfg;..\..\..\..\..\ChibiOS\os\license;..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\ext\ARM\CMSIS\Core\Include;..\..\..\..\..\ChibiOS-Contrib\os\common\ext\CMSIS\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\portability\Keil;..\..\..\..\..\ChibiOS\os\common\ports\ARM-common;..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M;..\..\..\..\..\ChibiOS\os\rt\include;..\..\..\..\..\ChibiOS\os\oslib\include;..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil;..\..\..\..\..\ChibiOS\os\hal\include;..\board;..\..\..\..\..\ChibiOS\os\hal\ports\common\ARMCMx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\LLD\GPIOv1;..\..\..\..\os\hal\ports\WB32\LLD\DMAv1;..\..\..\..\os\hal\ports\WB32\LLD\TIMv1;..\..\..\..\..\ChibiOS\os\test\include;..\..\..\..\..\ChibiOS\test\rt\source\test;..\..\..\..\..\ChibiOS\test\oslib\source\test
@@ -352,7 +348,7 @@
0
0
0
- 4
+ 0
--cpreproc --cpreproc_opts=-DCORTEX_USE_FPU=0
diff --git a/os/hal/ports/WB32/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/WB32/LLD/GPIOv1/hal_pal_lld.c
index 2dcb3faa06..2c1843d00f 100644
--- a/os/hal/ports/WB32/LLD/GPIOv1/hal_pal_lld.c
+++ b/os/hal/ports/WB32/LLD/GPIOv1/hal_pal_lld.c
@@ -159,6 +159,8 @@ void _pal_lld_enablepadevent(ioportid_t port,
else
EXTI->FTSR &= ~padmask;
+ EXTI->PR = padmask;
+
/* Programming interrupt and event registers.*/
EXTI->IMR |= padmask;
EXTI->EMR &= ~padmask;
@@ -204,8 +206,10 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
EXTI->FTSR = ftsr1 & ~padmask;
EXTI->PR = padmask;
- /* Disable EXTI clock.*/
- rccDisableEXTI();
+ if ((!EXTI->IMR) && (!EXTI->EMR)) {
+ /* Disable EXTI clock.*/
+ rccDisableEXTI();
+ }
#if PAL_USE_CALLBACKS || PAL_USE_WAIT
/* Callback cleared and/or thread reset.*/
diff --git a/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c b/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c
index 9a9bf10a2c..740f943887 100644
--- a/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c
+++ b/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c
@@ -354,6 +354,12 @@ static void usb_serve_epin_handler(USBDriver *usbp, usbep_t ep) {
/* IN endpoint, transmission.*/
USBInEndpointState *isp = epcp->in_state;
+ if (isp->txcnt >= isp->txsize) {
+ /* Transfer completed, invokes the callback.*/
+ _usb_isr_invoke_in_cb(usbp, ep);
+ return;
+ }
+
WB32_USB->INDEX = ep;
isp->txcnt += isp->txlast;
diff --git a/os/hal/ports/WB32/WB32F3G71xx/hal_efl_lld.c b/os/hal/ports/WB32/WB32F3G71xx/hal_efl_lld.c
index 9474e4a1da..3a68d4e081 100644
--- a/os/hal/ports/WB32/WB32F3G71xx/hal_efl_lld.c
+++ b/os/hal/ports/WB32/WB32F3G71xx/hal_efl_lld.c
@@ -21,7 +21,7 @@
* @addtogroup HAL_EFL
* @{
*/
-
+
#include
#include "hal.h"
@@ -308,13 +308,27 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
memcpy((void *)&line.b[0], (const void *)address, WB32_FLASH_PAGE_SIZE);
+ /* Copying data inside the prepared page.*/
+ do {
+ line.b[offset & WB32_FLASH_PAGE_MASK] = *pp;
+ offset++;
+ n--;
+ pp++;
+ } while ((n > 0U) & ((offset & WB32_FLASH_PAGE_MASK) != 0U));
+
#ifndef WB32_FLASH_PROGRAM_NO_ERASE
+ bool ferase = true;
+#else
+ bool ferase = false;
+to_erase:
+#endif
/* Erase page. */
- err = wb32_flash_erase_page(devp, (uint32_t)address);
- if (err != FLASH_NO_ERROR) {
- break;
+ if (ferase) {
+ err = wb32_flash_erase_page(devp, (uint32_t)address);
+ if (err != FLASH_NO_ERROR) {
+ break;
+ }
}
-#endif
/* Clear page latch. */
err = wb32_flash_clear_page_latch(devp);
@@ -322,15 +336,6 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
break;
}
- /* Copying data inside the prepared page.*/
- do {
- line.b[offset & WB32_FLASH_PAGE_MASK] = *pp;
- offset++;
- n--;
- pp++;
- }
- while ((n > 0U) & ((offset & WB32_FLASH_PAGE_MASK) != 0U));
-
for (int i = 0; i < (WB32_FLASH_PAGE_SIZE / sizeof(uint32_t)); i++) {
devp->flash->BUF[i] = line.w[i];
}
@@ -340,8 +345,15 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
if (err != FLASH_NO_ERROR) {
break;
}
+
/* Check for flash error.*/
- if (address[0] != line.w[0]) {
+ if (memcmp(&line.w[0], (void *)address, WB32_FLASH_PAGE_SIZE) != 0) {
+#ifdef WB32_FLASH_PROGRAM_NO_ERASE
+ if (!ferase) {
+ ferase = true;
+ goto to_erase;
+ }
+#endif
err = FLASH_ERROR_PROGRAM;
break;
}
diff --git a/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c b/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c
index 5b3eeaa3ee..e67e4dae35 100644
--- a/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c
+++ b/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c
@@ -1,394 +1,397 @@
-/*
- Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file WB32F3G71xx/hal_lld.c
- * @brief WB32F3G71xx HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief System Clock Frequency (Core Clock)
- */
-uint32_t SystemCoreClock = WB32_MAINCLK;
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
- void SystemCoreClockUpdate(void);
- SystemCoreClockUpdate();
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- * @param None
- * @return None
- */
-void SystemCoreClockUpdate(void) {
-
- uint32_t ahbprediv, pllprediv, pllmul, mainclk;
-
- switch (RCC->MAINCLKSRC) {
- case 0x00: /* MHSI used as main clock */
- mainclk = 8000000;
- break;
- case 0x01: /* FHSI used as main clock */
- mainclk = 48000000;
- break;
- case 0x03: /* HSE used as main clock */
- mainclk = WB32_HSECLK;
- break;
- case 0x02: /* PLL used as main clock */
- pllprediv =
- (((RCC->PLLPRE & (RCC_PLLPRE_RATIO_Msk | RCC_PLLPRE_DIVEN)) + 1) >> 1) + 1;
- pllmul = (0x03 - ((ANCTL->PLLCR >> 6) & 0x03)) * 4 + 12;
- if (RCC->PLLSRC == RCC_PLLSRC_HSE) {
- mainclk = WB32_HSECLK * pllmul / pllprediv;
- }
- else {
- mainclk = 8000000 * pllmul / pllprediv;
- }
- break;
- default:
- mainclk = 8000000;
- break;
- }
-
- ahbprediv =
- (((RCC->AHBPRE & (RCC_AHBPRE_RATIO_Msk | RCC_AHBPRE_DIVEN)) + 1) >> 1) + 1;
- SystemCoreClock = mainclk / ahbprediv;
-}
-
-#if defined(WB32F3G71xx)
-
-/**
- * @brief Configures the main clock frequency, AHBCLK, APB1CLK and APB2CLK prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @return None
- */
-static void SetSysClock(void) {
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* Unlocks write to ANCTL registers */
- PWR->ANAKEY1 = 0x03;
- PWR->ANAKEY2 = 0x0C;
-
- /* APB1CLK = MAINCLK / WB32_PPRE1*/
- RCC->APB1PRE = RCC_APB1PRE_SRCEN;
-#if WB32_PPRE1 == 1
- RCC->APB1PRE |= 0x00;
-#else
- RCC->APB1PRE |= (WB32_PPRE1 - 2);
- RCC->APB1PRE |= 0x01;
-#endif /* WB32_PPRE1 == 1 */
-
-#if WB32_HSE_ENABLED == TRUE
- /* Configure PD0 and PD1 to analog mode */
- RCC->APB1ENR = RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIODEN;
-
- /* Enable HSE */
-#if WB32_HSE_STATE == ANCTL_HSECR0_BYPASS
- GPIOD->CFGMSK = 0xFFFE;
- GPIOD->MODER = 0x03;
- ANCTL->HSECR1 = 0x00;
- ANCTL->HSECR0 = ANCTL_HSECR0_BYPASS;
-#else
- GPIOD->CFGMSK = 0xFFFC;
- GPIOD->MODER = 0x0F;
- ANCTL->HSECR1 = ANCTL_HSECR1_PADOEN;
- ANCTL->HSECR0 = ANCTL_HSECR0_HSEON;
-#endif
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do {
- HSEStatus = ANCTL->HSESR & ANCTL_HSESR_HSERDY;
- StartUpCounter++;
- } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if (HSEStatus == 0) {
- /* If HSE fails to start-up, the application will have wrong clock
- * configuration. User can add here some code to deal with this error */
- while (1)
- ;
- }
-#endif /* WB32_HSE_ENABLED == TRUE */
- /* Configure Flash prefetch, Cache and wait state */
-#if WB32_MAINCLK <= 32000000
- CACHE->CR = CACHE_CR_LATENCY_0WS;
-#elif WB32_MAINCLK <= 48000000
- CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_1WS;
-#elif WB32_MAINCLK <= 72000000
- CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_2WS;
-#else
- CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_3WS;
-#endif
-
- /* AHBCLK = WB32_HPRE */
-#if WB32_HPRE == 1
- RCC->AHBPRE = 0x00;
-#else
- RCC->AHBPRE = (WB32_HPRE - 2);
- RCC->AHBPRE |= 0x01;
-#endif /* WB32_HPRE == 1 */
-
- /* APB2CLK = MAINCLK / WB32_PPRE2 */
- RCC->APB2PRE = RCC_APB2PRE_SRCEN;
-#if WB32_PPRE2 == 1
- RCC->APB2PRE |= 0x00;
-#else
- RCC->APB2PRE |= (WB32_PPRE2 - 2);
- RCC->APB2PRE |= 0x01;
-#endif /* WB32_PPRE2 == 1 */
-
-#if WB32_PLL_ENABLED == TRUE
- /* PLL configuration:
- PLLCLK = WB32_HSECLK / WB32_PLLDIV_VALUE * WB32_PLLMUL_VALUE*/
- RCC->PLLSRC = WB32_PLLSRC;
- RCC->PLLPRE = RCC_PLLPRE_SRCEN;
-
-#if WB32_PLLDIV_VALUE == 1
- RCC->PLLPRE |= 0x00;
-#else
- RCC->PLLPRE |= (WB32_PLLDIV_VALUE - 2);
- RCC->PLLPRE |= 0x01;
-#endif /* WB32_PLLDIV_VALUE == 1 */
-
-#if WB32_PLLMUL_VALUE == 12
- ANCTL->PLLCR = (0x3U << 6);
-#elif WB32_PLLMUL_VALUE == 16
- ANCTL->PLLCR = (0x2U << 6);
-#elif WB32_PLLMUL_VALUE == 20
- ANCTL->PLLCR = (0x1U << 6);
-#elif WB32_PLLMUL_VALUE == 24
- ANCTL->PLLCR = (0x0U << 6);
-#endif
-
- /* Enable PLL */
- ANCTL->PLLENR = ANCTL_PLLENR_PLLON;
- /* Wait till PLL is ready */
- while (ANCTL->PLLSR != 0x03) {
- }
-#endif /* WB32_PLL_ENABLED == TRUE */
-
- /* Select WB32_MAINCLKSRC as system clock source */
- RCC->MAINCLKSRC = WB32_MAINCLKSRC;
- RCC->MAINCLKUEN = RCC_MAINCLKUEN_ENA;
-
- /* Locks write to ANCTL registers */
- PWR->ANAKEY1 = 0x00;
- PWR->ANAKEY2 = 0x00;
-}
-
-/**
- * @brief Clocks initialization.
- * @note None
- * @param None
- * @return None
- */
-void wb32_clock_init(void) {
-
-#if WB32_NO_INIT == FALSE
- /* Unlocks write to ANCTL registers */
- PWR->ANAKEY1 = 0x03;
- PWR->ANAKEY2 = 0x0C;
-
- /* Turn off POR */
- ANCTL->PORCR = 0x7BE;
-
- /* Locks write to ANCTL registers */
- PWR->ANAKEY1 = 0x00;
- PWR->ANAKEY2 = 0x00;
-
- SetSysClock();
-
- rccEnableAPB1(RCC_APB1ENR_BMX1EN);
- rccEnableAPB2(RCC_APB2ENR_BMX2EN);
-
- SCB->VTOR = FLASH_BASE; /* Vector Table Relocation in Internal FLASH. */
-
-#endif /* WB32_NO_INIT == FALSE */
-}
-
-#if HAL_USE_USB || defined(__DOXYGEN__)
-
-/**
- * @brief wb32 usb initialization.
- * @param[in] usbp pointer to the @p USBDriver object
- * @return None
- */
-void wb32_usb_init(USBDriver *usbp) {
-
- /* Clock activation.*/
-#if WB32_USB_USE_USB1
- if (&USBD1 == usbp) {
- RCC->AHBENR1 |= RCC_AHBENR1_CRCSFMEN;
-
- /* Enable USB peripheral clock */
- RCC->AHBENR1 |= RCC_AHBENR1_USBEN;
-
- /* Configure USB FIFO clock source */
- RCC->USBFIFOCLKSRC = RCC_USBFIFOCLKSRC_USBCLK;
-
- /* Enable USB FIFO clock */
- RCC->USBFIFOCLKENR = RCC_USBFIFOCLKENR_CLKEN;
-
- /* Configure and enable USB PHY */
- SFM->USBPCON = 0x02;
-
- /* Configure and enable USBCLK */
-#if (WB32_USBPRE == WB32_USBPRE_DIV1P5)
- RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
- RCC->USBPRE = RCC_USBPRE_SRCEN;
- RCC->USBPRE |= RCC_USBPRE_RATIO_1_5;
- RCC->USBPRE |= RCC_USBPRE_DIVEN;
-#elif (WB32_USBPRE == WB32_USBPRE_DIV1)
- RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
- RCC->USBPRE = RCC_USBPRE_SRCEN;
- RCC->USBPRE |= 0x00;
-#elif (WB32_USBPRE == WB32_USBPRE_DIV2)
- RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
- RCC->USBPRE = RCC_USBPRE_SRCEN;
- RCC->USBPRE |= RCC_USBPRE_RATIO_2;
- RCC->USBPRE |= RCC_USBPRE_DIVEN;
-#elif (WB32_USBPRE == WB32_USBPRE_DIV3)
- RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
- RCC->USBPRE = RCC_USBPRE_SRCEN;
- RCC->USBPRE |= RCC_USBPRE_RATIO_3;
- RCC->USBPRE |= RCC_USBPRE_DIVEN;
-#else
-#error "invalid WB32_USBPRE value specified"
-#endif
- }
-#endif
-}
-
-/**
- * @brief wb32 usb deinitialization.
- * @param[in] usbp pointer to the @p USBDriver object
- * @return None
- */
-void wb32_usb_deinit(USBDriver *usbp) {
-
-#if WB32_USB_USE_USB1
- if (&USBD1 == usbp) {
- /* Disable USBCLK */
- RCC->USBPRE &= RCC_USBPRE_SRCEN;
- RCC->USBPRE = 0x00;
- RCC->USBCLKENR = 0x00;
-
- /* Disable USB FIFO clock */
- RCC->USBFIFOCLKENR = 0x0000;
-
- /* Disable USB peripheral clock */
- RCC->AHBENR1 &= ~RCC_AHBENR1_USBEN;
- }
-#endif
-}
-
-/**
- * @brief wb32 usb connect.
- * @param[in] usbp pointer to the @p USBDriver object
- * @return None
- */
-void wb32_usb_connect(USBDriver *usbp) {
-
- /* Enable BMX1, GPIOA clock */
- RCC->APB1ENR |= RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIOAEN;
-
- GPIOA->CFGMSK = (~(GPIO_CFGMSK_CFGMSK11 | GPIO_CFGMSK_CFGMSK12));
- /* Configure the drive current of PA11 and PA12 */
- GPIOA->CURRENT = (0x3 << 22) | (0x3 << 24);
- /* Configure PA11 and PA12 as Alternate function mode */
- GPIOA->MODER = (0x2 << 22) | (0x2 << 24);
- GPIOA->OTYPER = 0x00;
- GPIOA->OSPEEDR = 0x00;
- GPIOA->PUPDR = 0x00;
- GPIOA->AFRH = (3 << 12) | (3 << 16);
-
- USB->POWER = USB_POWER_SUSEN;
- USB->INTRUSBE = USB_INTRUSBE_RSTIE | USB_INTRUSBE_RSUIE | USB_INTRUSBE_SUSIE;
-}
-
-/**
- * @brief wb32 usb disconnect.
- * @param[in] usbp pointer to the @p USBDriver object
- * @return None
- */
-void wb32_usb_disconnect(USBDriver *usbp) {
-
- /* Enable BMX1, GPIOA clock */
- RCC->APB1ENR |= RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIOAEN;
-
- GPIOA->CFGMSK = (~(GPIO_CFGMSK_CFGMSK11 | GPIO_CFGMSK_CFGMSK12));
- /* Configure PA11 and PA12 as input mode */
- GPIOA->MODER = 0x00;
- GPIOA->OSPEEDR = 0x00;
- GPIOA->PUPDR = 0x00;
- /* Configure PA12(D+) as open-drain output mode and output low level */
- GPIOA->CFGMSK = (~GPIO_CFGMSK_CFGMSK12);
- GPIOA->MODER = (0x1 << 24);
- GPIOA->OTYPER = (0x1 << 12);
- GPIOA->AFRH = 0x00;
- GPIOA->BSRR = (0x1000 << 16);
-}
-#endif
-
-#else
-
-#error "not defined wb32_clock_init"
-
-#endif
-
-/** @} */
+/*
+ Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file WB32F3G71xx/hal_lld.c
+ * @brief WB32F3G71xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief System Clock Frequency (Core Clock)
+ */
+uint32_t SystemCoreClock = WB32_MAINCLK;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ void SystemCoreClockUpdate(void);
+ SystemCoreClockUpdate();
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ * @param None
+ * @return None
+ */
+void SystemCoreClockUpdate(void) {
+
+ uint32_t ahbprediv, pllprediv, pllmul, mainclk;
+
+ switch (RCC->MAINCLKSRC) {
+ case 0x00: /* MHSI used as main clock */
+ mainclk = 8000000;
+ break;
+ case 0x01: /* FHSI used as main clock */
+ mainclk = 48000000;
+ break;
+ case 0x03: /* HSE used as main clock */
+ mainclk = WB32_HSECLK;
+ break;
+ case 0x02: /* PLL used as main clock */
+ pllprediv =
+ (((RCC->PLLPRE & (RCC_PLLPRE_RATIO_Msk | RCC_PLLPRE_DIVEN)) + 1) >> 1) + 1;
+ pllmul = (0x03 - ((ANCTL->PLLCR >> 6) & 0x03)) * 4 + 12;
+ if (RCC->PLLSRC == RCC_PLLSRC_HSE) {
+ mainclk = WB32_HSECLK * pllmul / pllprediv;
+ }
+ else {
+ mainclk = 8000000 * pllmul / pllprediv;
+ }
+ break;
+ default:
+ mainclk = 8000000;
+ break;
+ }
+
+ ahbprediv =
+ (((RCC->AHBPRE & (RCC_AHBPRE_RATIO_Msk | RCC_AHBPRE_DIVEN)) + 1) >> 1) + 1;
+ SystemCoreClock = mainclk / ahbprediv;
+}
+
+#if defined(WB32F3G71xx)
+
+/**
+ * @brief Configures the main clock frequency, AHBCLK, APB1CLK and APB2CLK prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @return None
+ */
+static void SetSysClock(void) {
+
+ /* Unlocks write to ANCTL registers */
+ PWR->ANAKEY1 = 0x03;
+ PWR->ANAKEY2 = 0x0C;
+
+ /* APB1CLK = MAINCLK / WB32_PPRE1*/
+ RCC->APB1PRE = RCC_APB1PRE_SRCEN;
+#if WB32_PPRE1 == 1
+ RCC->APB1PRE |= 0x00;
+#else
+ RCC->APB1PRE |= (WB32_PPRE1 - 2);
+ RCC->APB1PRE |= 0x01;
+#endif /* WB32_PPRE1 == 1 */
+
+#if WB32_HSE_ENABLED == TRUE
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* Configure PD0 and PD1 to analog mode */
+ RCC->APB1ENR = RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIODEN;
+
+ /* Enable HSE */
+#if WB32_HSE_STATE == ANCTL_HSECR0_BYPASS
+ GPIOD->CFGMSK = 0xFFFE;
+ GPIOD->MODER = 0x03;
+ ANCTL->HSECR1 = 0x00;
+ ANCTL->HSECR0 = ANCTL_HSECR0_BYPASS;
+#else
+ GPIOD->CFGMSK = 0xFFFC;
+ GPIOD->MODER = 0x0F;
+ ANCTL->HSECR1 = ANCTL_HSECR1_PADOEN;
+ ANCTL->HSECR0 = ANCTL_HSECR0_HSEON;
+#endif
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do {
+ HSEStatus = ANCTL->HSESR & ANCTL_HSESR_HSERDY;
+ StartUpCounter++;
+ } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if (HSEStatus == 0) {
+ /* If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error */
+ while (1)
+ ;
+ }
+#endif /* WB32_HSE_ENABLED == TRUE */
+ /* Configure Flash prefetch, Cache and wait state */
+#if WB32_MAINCLK <= 32000000
+ CACHE->CR = CACHE_CR_LATENCY_0WS;
+#elif WB32_MAINCLK <= 48000000
+ CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_1WS;
+#elif WB32_MAINCLK <= 72000000
+ CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_2WS;
+#else
+ CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_3WS;
+#endif
+
+ /* AHBCLK = WB32_HPRE */
+#if WB32_HPRE == 1
+ RCC->AHBPRE = 0x00;
+#else
+ RCC->AHBPRE = (WB32_HPRE - 2);
+ RCC->AHBPRE |= 0x01;
+#endif /* WB32_HPRE == 1 */
+
+ /* APB2CLK = MAINCLK / WB32_PPRE2 */
+ RCC->APB2PRE = RCC_APB2PRE_SRCEN;
+#if WB32_PPRE2 == 1
+ RCC->APB2PRE |= 0x00;
+#else
+ RCC->APB2PRE |= (WB32_PPRE2 - 2);
+ RCC->APB2PRE |= 0x01;
+#endif /* WB32_PPRE2 == 1 */
+
+#if WB32_PLL_ENABLED == TRUE
+ /* PLL configuration:
+ PLLCLK = WB32_HSECLK / WB32_PLLDIV_VALUE * WB32_PLLMUL_VALUE*/
+ RCC->PLLSRC = WB32_PLLSRC;
+ RCC->PLLPRE = RCC_PLLPRE_SRCEN;
+
+#if WB32_PLLDIV_VALUE == 1
+ RCC->PLLPRE |= 0x00;
+#else
+ RCC->PLLPRE |= (WB32_PLLDIV_VALUE - 2);
+ RCC->PLLPRE |= 0x01;
+#endif /* WB32_PLLDIV_VALUE == 1 */
+
+#if WB32_PLLMUL_VALUE == 12
+ ANCTL->PLLCR = (0x3U << 6);
+#elif WB32_PLLMUL_VALUE == 16
+ ANCTL->PLLCR = (0x2U << 6);
+#elif WB32_PLLMUL_VALUE == 20
+ ANCTL->PLLCR = (0x1U << 6);
+#elif WB32_PLLMUL_VALUE == 24
+ ANCTL->PLLCR = (0x0U << 6);
+#endif
+
+ /* Enable PLL */
+ ANCTL->PLLENR = ANCTL_PLLENR_PLLON;
+ /* Wait till PLL is ready */
+ while (ANCTL->PLLSR != 0x03) {
+ }
+#endif /* WB32_PLL_ENABLED == TRUE */
+
+ /* Select WB32_MAINCLKSRC as system clock source */
+ RCC->MAINCLKSRC = WB32_MAINCLKSRC;
+ RCC->MAINCLKUEN = RCC_MAINCLKUEN_ENA;
+
+ /* Locks write to ANCTL registers */
+ PWR->ANAKEY1 = 0x00;
+ PWR->ANAKEY2 = 0x00;
+}
+
+/**
+ * @brief Clocks initialization.
+ * @note None
+ * @param None
+ * @return None
+ */
+void wb32_clock_init(void) {
+
+#if WB32_NO_INIT == FALSE
+ /* Unlocks write to ANCTL registers */
+ PWR->ANAKEY1 = 0x03;
+ PWR->ANAKEY2 = 0x0C;
+
+ /* Turn off POR */
+ ANCTL->PORCR = 0x7BE;
+
+ /* Locks write to ANCTL registers */
+ PWR->ANAKEY1 = 0x00;
+ PWR->ANAKEY2 = 0x00;
+
+ SetSysClock();
+
+ rccEnableAPB1(RCC_APB1ENR_BMX1EN);
+ rccEnableAPB2(RCC_APB2ENR_BMX2EN);
+
+#endif /* WB32_NO_INIT == FALSE */
+}
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+/**
+ * @brief wb32 usb initialization.
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @return None
+ */
+void wb32_usb_init(USBDriver *usbp) {
+
+ /* Clock activation.*/
+#if WB32_USB_USE_USB1
+ if (&USBD1 == usbp) {
+ RCC->AHBENR1 |= RCC_AHBENR1_CRCSFMEN;
+
+ /* Enable USB peripheral clock */
+ RCC->AHBENR1 |= RCC_AHBENR1_USBEN;
+
+ /* Reset USB peripheral */
+ RCC->AHBRSTR1 |= (RCC_AHBRSTR1_USBRST);
+ RCC->AHBRSTR1 &= ~(RCC_AHBRSTR1_USBRST);
+
+ /* Configure USB FIFO clock source */
+ RCC->USBFIFOCLKSRC = RCC_USBFIFOCLKSRC_USBCLK;
+
+ /* Enable USB FIFO clock */
+ RCC->USBFIFOCLKENR = RCC_USBFIFOCLKENR_CLKEN;
+
+ /* Configure and enable USB PHY */
+ SFM->USBPCON = 0x02;
+
+ /* Configure and enable USBCLK */
+#if (WB32_USBPRE == WB32_USBPRE_DIV1P5)
+ RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
+ RCC->USBPRE = RCC_USBPRE_SRCEN;
+ RCC->USBPRE |= RCC_USBPRE_RATIO_1_5;
+ RCC->USBPRE |= RCC_USBPRE_DIVEN;
+#elif (WB32_USBPRE == WB32_USBPRE_DIV1)
+ RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
+ RCC->USBPRE = RCC_USBPRE_SRCEN;
+ RCC->USBPRE |= 0x00;
+#elif (WB32_USBPRE == WB32_USBPRE_DIV2)
+ RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
+ RCC->USBPRE = RCC_USBPRE_SRCEN;
+ RCC->USBPRE |= RCC_USBPRE_RATIO_2;
+ RCC->USBPRE |= RCC_USBPRE_DIVEN;
+#elif (WB32_USBPRE == WB32_USBPRE_DIV3)
+ RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
+ RCC->USBPRE = RCC_USBPRE_SRCEN;
+ RCC->USBPRE |= RCC_USBPRE_RATIO_3;
+ RCC->USBPRE |= RCC_USBPRE_DIVEN;
+#else
+#error "invalid WB32_USBPRE value specified"
+#endif
+ }
+#endif
+}
+
+/**
+ * @brief wb32 usb deinitialization.
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @return None
+ */
+void wb32_usb_deinit(USBDriver *usbp) {
+
+#if WB32_USB_USE_USB1
+ if (&USBD1 == usbp) {
+ /* Disable USBCLK */
+ RCC->USBPRE &= RCC_USBPRE_SRCEN;
+ RCC->USBPRE = 0x00;
+ RCC->USBCLKENR = 0x00;
+
+ /* Disable USB FIFO clock */
+ RCC->USBFIFOCLKENR = 0x0000;
+
+ /* Disable USB peripheral clock */
+ RCC->AHBENR1 &= ~RCC_AHBENR1_USBEN;
+ }
+#endif
+}
+
+/**
+ * @brief wb32 usb connect.
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @return None
+ */
+void wb32_usb_connect(USBDriver *usbp) {
+
+ /* Enable BMX1, GPIOA clock */
+ RCC->APB1ENR |= RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIOAEN;
+
+ GPIOA->CFGMSK = (~(GPIO_CFGMSK_CFGMSK11 | GPIO_CFGMSK_CFGMSK12));
+ /* Configure the drive current of PA11 and PA12 */
+ GPIOA->CURRENT = (0x3 << 22) | (0x3 << 24);
+ /* Configure PA11 and PA12 as Alternate function mode */
+ GPIOA->MODER = (0x2 << 22) | (0x2 << 24);
+ GPIOA->OTYPER = 0x00;
+ GPIOA->OSPEEDR = 0x00;
+ GPIOA->PUPDR = 0x00;
+ GPIOA->AFRH = (3 << 12) | (3 << 16);
+
+ USB->POWER = USB_POWER_SUSEN;
+ USB->INTRUSBE = USB_INTRUSBE_RSTIE | USB_INTRUSBE_RSUIE | USB_INTRUSBE_SUSIE;
+}
+
+/**
+ * @brief wb32 usb disconnect.
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @return None
+ */
+void wb32_usb_disconnect(USBDriver *usbp) {
+
+ /* Enable BMX1, GPIOA clock */
+ RCC->APB1ENR |= RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIOAEN;
+
+ GPIOA->CFGMSK = (~(GPIO_CFGMSK_CFGMSK11 | GPIO_CFGMSK_CFGMSK12));
+ /* Configure PA11 and PA12 as input mode */
+ GPIOA->MODER = 0x00;
+ GPIOA->OSPEEDR = 0x00;
+ GPIOA->PUPDR = 0x00;
+ /* Configure PA12(D+) as open-drain output mode and output low level */
+ GPIOA->CFGMSK = (~GPIO_CFGMSK_CFGMSK12);
+ GPIOA->MODER = (0x1 << 24);
+ GPIOA->OTYPER = (0x1 << 12);
+ GPIOA->AFRH = 0x00;
+ GPIOA->BSRR = (0x1000 << 16);
+}
+#endif
+
+#else
+
+#error "not defined wb32_clock_init"
+
+#endif
+
+/** @} */
diff --git a/os/hal/ports/WB32/WB32F3G71xx/wb32_isr.c b/os/hal/ports/WB32/WB32F3G71xx/wb32_isr.c
index f5fecad29c..cba88e67b5 100644
--- a/os/hal/ports/WB32/WB32F3G71xx/wb32_isr.c
+++ b/os/hal/ports/WB32/WB32F3G71xx/wb32_isr.c
@@ -62,8 +62,7 @@ OSAL_IRQ_HANDLER(WB32_EXTI0_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & EXTI_IMR_MR0;
+ pr = EXTI->PR & EXTI_PR_PR0;
EXTI->PR = pr;
exti_serve_irq(pr, 0);
@@ -83,8 +82,7 @@ OSAL_IRQ_HANDLER(WB32_EXTI1_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & EXTI_IMR_MR1;
+ pr = EXTI->PR & EXTI_PR_PR1;
EXTI->PR = pr;
exti_serve_irq(pr, 1);
@@ -104,8 +102,7 @@ OSAL_IRQ_HANDLER(WB32_EXTI2_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & EXTI_IMR_MR2;
+ pr = EXTI->PR & EXTI_PR_PR2;
EXTI->PR = pr;
exti_serve_irq(pr, 2);
@@ -125,8 +122,7 @@ OSAL_IRQ_HANDLER(WB32_EXTI3_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & EXTI_IMR_MR3;
+ pr = EXTI->PR & EXTI_PR_PR3;
EXTI->PR = pr;
exti_serve_irq(pr, 3);
@@ -146,8 +142,7 @@ OSAL_IRQ_HANDLER(WB32_EXTI4_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & EXTI_IMR_MR4;
+ pr = EXTI->PR & EXTI_PR_PR4;
EXTI->PR = pr;
exti_serve_irq(pr, 4);
@@ -167,9 +162,8 @@ OSAL_IRQ_HANDLER(WB32_EXTI9_5_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & (EXTI_IMR_MR5 | EXTI_IMR_MR6 | EXTI_IMR_MR7 | EXTI_IMR_MR8 |
- EXTI_IMR_MR9);
+ pr = EXTI->PR & (EXTI_PR_PR5 | EXTI_PR_PR6 | EXTI_PR_PR7 |
+ EXTI_PR_PR8 | EXTI_PR_PR9);
EXTI->PR = pr;
exti_serve_irq(pr, 5);
@@ -193,9 +187,8 @@ OSAL_IRQ_HANDLER(WB32_EXTI15_10_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & (EXTI_IMR_MR10 | EXTI_IMR_MR11 | EXTI_IMR_MR12 |
- EXTI_IMR_MR13 | EXTI_IMR_MR14 | EXTI_IMR_MR15);
+ pr = EXTI->PR & (EXTI_PR_PR10 | EXTI_PR_PR11 | EXTI_PR_PR12 |
+ EXTI_PR_PR13 | EXTI_PR_PR14 | EXTI_PR_PR15);
EXTI->PR = pr;
exti_serve_irq(pr, 10);
diff --git a/os/hal/ports/WB32/WB32FQ95xx/hal_efl_lld.c b/os/hal/ports/WB32/WB32FQ95xx/hal_efl_lld.c
index 9474e4a1da..3a68d4e081 100644
--- a/os/hal/ports/WB32/WB32FQ95xx/hal_efl_lld.c
+++ b/os/hal/ports/WB32/WB32FQ95xx/hal_efl_lld.c
@@ -21,7 +21,7 @@
* @addtogroup HAL_EFL
* @{
*/
-
+
#include
#include "hal.h"
@@ -308,13 +308,27 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
memcpy((void *)&line.b[0], (const void *)address, WB32_FLASH_PAGE_SIZE);
+ /* Copying data inside the prepared page.*/
+ do {
+ line.b[offset & WB32_FLASH_PAGE_MASK] = *pp;
+ offset++;
+ n--;
+ pp++;
+ } while ((n > 0U) & ((offset & WB32_FLASH_PAGE_MASK) != 0U));
+
#ifndef WB32_FLASH_PROGRAM_NO_ERASE
+ bool ferase = true;
+#else
+ bool ferase = false;
+to_erase:
+#endif
/* Erase page. */
- err = wb32_flash_erase_page(devp, (uint32_t)address);
- if (err != FLASH_NO_ERROR) {
- break;
+ if (ferase) {
+ err = wb32_flash_erase_page(devp, (uint32_t)address);
+ if (err != FLASH_NO_ERROR) {
+ break;
+ }
}
-#endif
/* Clear page latch. */
err = wb32_flash_clear_page_latch(devp);
@@ -322,15 +336,6 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
break;
}
- /* Copying data inside the prepared page.*/
- do {
- line.b[offset & WB32_FLASH_PAGE_MASK] = *pp;
- offset++;
- n--;
- pp++;
- }
- while ((n > 0U) & ((offset & WB32_FLASH_PAGE_MASK) != 0U));
-
for (int i = 0; i < (WB32_FLASH_PAGE_SIZE / sizeof(uint32_t)); i++) {
devp->flash->BUF[i] = line.w[i];
}
@@ -340,8 +345,15 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
if (err != FLASH_NO_ERROR) {
break;
}
+
/* Check for flash error.*/
- if (address[0] != line.w[0]) {
+ if (memcmp(&line.w[0], (void *)address, WB32_FLASH_PAGE_SIZE) != 0) {
+#ifdef WB32_FLASH_PROGRAM_NO_ERASE
+ if (!ferase) {
+ ferase = true;
+ goto to_erase;
+ }
+#endif
err = FLASH_ERROR_PROGRAM;
break;
}
diff --git a/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c b/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c
index 2b1a94f9e7..62a3ca74e5 100644
--- a/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c
+++ b/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c
@@ -119,7 +119,6 @@ void SystemCoreClockUpdate(void) {
* @return None
*/
static void SetSysClock(void) {
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Unlocks write to ANCTL registers */
PWR->ANAKEY1 = 0x03;
@@ -135,6 +134,8 @@ static void SetSysClock(void) {
#endif /* WB32_PPRE1 == 1 */
#if WB32_HSE_ENABLED == TRUE
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
/* Configure PD0 and PD1 to analog mode */
RCC->APB1ENR = RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIODEN;
@@ -256,8 +257,6 @@ void wb32_clock_init(void) {
rccEnableAPB1(RCC_APB1ENR_BMX1EN);
rccEnableAPB2(RCC_APB2ENR_BMX2EN);
- SCB->VTOR = FLASH_BASE; /* Vector Table Relocation in Internal FLASH. */
-
#endif /* WB32_NO_INIT == FALSE */
}
@@ -278,6 +277,10 @@ void wb32_usb_init(USBDriver *usbp) {
/* Enable USB peripheral clock */
RCC->AHBENR1 |= RCC_AHBENR1_USBEN;
+ /* Reset USB peripheral */
+ RCC->AHBRSTR1 |= (RCC_AHBRSTR1_USBRST);
+ RCC->AHBRSTR1 &= ~(RCC_AHBRSTR1_USBRST);
+
/* Configure USB FIFO clock source */
RCC->USBFIFOCLKSRC = RCC_USBFIFOCLKSRC_USBCLK;
diff --git a/os/hal/ports/WB32/WB32FQ95xx/wb32_isr.c b/os/hal/ports/WB32/WB32FQ95xx/wb32_isr.c
index 38e227d820..1533e3123e 100644
--- a/os/hal/ports/WB32/WB32FQ95xx/wb32_isr.c
+++ b/os/hal/ports/WB32/WB32FQ95xx/wb32_isr.c
@@ -62,8 +62,7 @@ OSAL_IRQ_HANDLER(WB32_EXTI0_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & EXTI_IMR_MR0;
+ pr = EXTI->PR & EXTI_PR_PR0;
EXTI->PR = pr;
exti_serve_irq(pr, 0);
@@ -83,8 +82,7 @@ OSAL_IRQ_HANDLER(WB32_EXTI1_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & EXTI_IMR_MR1;
+ pr = EXTI->PR & EXTI_PR_PR1;
EXTI->PR = pr;
exti_serve_irq(pr, 1);
@@ -104,8 +102,7 @@ OSAL_IRQ_HANDLER(WB32_EXTI2_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & EXTI_IMR_MR2;
+ pr = EXTI->PR & EXTI_PR_PR2;
EXTI->PR = pr;
exti_serve_irq(pr, 2);
@@ -125,8 +122,7 @@ OSAL_IRQ_HANDLER(WB32_EXTI3_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & EXTI_IMR_MR3;
+ pr = EXTI->PR & EXTI_PR_PR3;
EXTI->PR = pr;
exti_serve_irq(pr, 3);
@@ -146,8 +142,7 @@ OSAL_IRQ_HANDLER(WB32_EXTI4_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & EXTI_IMR_MR4;
+ pr = EXTI->PR & EXTI_PR_PR4;
EXTI->PR = pr;
exti_serve_irq(pr, 4);
@@ -167,9 +162,8 @@ OSAL_IRQ_HANDLER(WB32_EXTI9_5_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & (EXTI_IMR_MR5 | EXTI_IMR_MR6 | EXTI_IMR_MR7 | EXTI_IMR_MR8 |
- EXTI_IMR_MR9);
+ pr = EXTI->PR & (EXTI_PR_PR5 | EXTI_PR_PR6 | EXTI_PR_PR7 |
+ EXTI_PR_PR8 | EXTI_PR_PR9);
EXTI->PR = pr;
exti_serve_irq(pr, 5);
@@ -193,9 +187,8 @@ OSAL_IRQ_HANDLER(WB32_EXTI15_10_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & (EXTI_IMR_MR10 | EXTI_IMR_MR11 | EXTI_IMR_MR12 |
- EXTI_IMR_MR13 | EXTI_IMR_MR14 | EXTI_IMR_MR15);
+ pr = EXTI->PR & (EXTI_PR_PR10 | EXTI_PR_PR11 | EXTI_PR_PR12 |
+ EXTI_PR_PR13 | EXTI_PR_PR14 | EXTI_PR_PR15);
EXTI->PR = pr;
exti_serve_irq(pr, 10);