From 6bbcbcda67e17ee7c831fa853386693d1f385dae Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Sun, 5 May 2024 10:18:02 +0700 Subject: [PATCH 01/18] Patch update and cleanup CMSIS AT32F415 files --- .../ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h | 991 +++++++--------- .../ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h | 980 +++++++--------- .../ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h | 1006 +++++++---------- .../ArteryTek/AT32F415/system_at32f415.h | 4 + os/hal/ports/AT32/AT32F415/at32_isr.h | 4 +- 5 files changed, 1195 insertions(+), 1790 deletions(-) diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h index 5812f76baa..1cd3e4e0f7 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file at32f415cx.h * @author Artery Technology & HorrorTroll & Zhaqian - * @version v2.1.1 - * @date 26-October-2023 + * @version v2.1.2 + * @date 05-January-2024 * @brief AT32F415Cx header file. * ****************************************************************************** @@ -42,11 +42,11 @@ #endif /** - * @brief CMSIS Device version number V2.1.1 + * @brief CMSIS Device version number V2.1.2 */ #define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ #define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ -#define __AT32F415_LIBRARY_VERSION_MINOR (0x01) /*!< [15:8] minor version */ +#define __AT32F415_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */ #define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\ |(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\ @@ -102,7 +102,7 @@ typedef enum WWDT_IRQn = 0, /*!< Window WatchDog Timer Interrupt */ PVM_IRQn = 1, /*!< PVM Interrupt linked to EXINT16 */ TAMPER_IRQn = 2, /*!< Tamper Interrupt linked to EXINT21 */ - ERTC_IRQn = 3, /*!< ERTC Interrupt linked to EXINT22 */ + ERTC_WKUP_IRQn = 3, /*!< ERTC Wake Up Interrupt linked to EXINT22 */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ CRM_IRQn = 5, /*!< CRM global Interrupt */ EXINT0_IRQn = 6, /*!< EXINT Line 0 Interrupt */ @@ -179,8 +179,8 @@ typedef struct __IO uint32_t SPT2; /*!< ADC sampling time register 2, Address offset: 0x10 */ __IO uint32_t PCDTO1; /*!< ADC preempted channel data offset reg 1, Address offset: 0x14 */ __IO uint32_t PCDTO2; /*!< ADC preempted channel data offset reg 2, Address offset: 0x18 */ - __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3 Address offset: 0x1C */ - __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4 Address offset: 0x20 */ + __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3, Address offset: 0x1C */ + __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4, Address offset: 0x20 */ __IO uint32_t VMHB; /*!< ADC voltage monitor high threshold register, Address offset: 0x24 */ __IO uint32_t VMLB; /*!< ADC voltage monitor low threshold register, Address offset: 0x28 */ __IO uint32_t OSQ1; /*!< ADC ordinary sequence register 1, Address offset: 0x2C */ @@ -242,10 +242,10 @@ typedef struct __IO uint32_t INTEN; /*!< CAN interrupt enable register, Address offset: 0x014 */ __IO uint32_t ESTS; /*!< CAN error status register, Address offset: 0x018 */ __IO uint32_t BTMG; /*!< CAN bit timing register, Address offset: 0x01C */ - uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17F */ + uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17C */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN TX Mailbox registers, Address offset: 0x180 ~ 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO Mailbox registers, Address offset: 0x1B0 ~ 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FF */ + uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FC */ __IO uint32_t FCTRL; /*!< CAN filter control register, Address offset: 0x200 */ __IO uint32_t FMCFG; /*!< CAN filter mode configuration register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x208 */ @@ -254,7 +254,7 @@ typedef struct __IO uint32_t FRF; /*!< CAN filter FIFO association register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x218 */ __IO uint32_t FACFG; /*!< CAN filter activation control register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23F */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23C */ CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN filter registers, Address offset: 0x240 ~ 0x2AC */ } CAN_TypeDef; @@ -269,7 +269,7 @@ typedef struct } CMP_TypeDef; /** - * @brief CRC calculation unit + * @brief CRC Calculation Unit */ typedef struct @@ -322,10 +322,10 @@ typedef struct typedef struct { - __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x08 + 20 * (x - 1) x = 1 ... 7 */ - __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x0C + 20 * (x - 1) x = 1 ... 7 */ - __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + 20 * (x - 1) x = 1 ... 7 */ - __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x14 + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x08 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x0C + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x14 + 20 * (x - 1) (x = 1 ... 7) */ } DMA_Channel_TypeDef; typedef struct @@ -406,7 +406,7 @@ typedef struct typedef struct { __IO uint32_t PSR; /*!< FLASH performance select register, Address offset: 0x00 */ - __IO uint32_t UNLOCK; /*!< FLASH unlock register 1, Address offset: 0x04 */ + __IO uint32_t UNLOCK; /*!< FLASH unlock register, Address offset: 0x04 */ __IO uint32_t USD_UNLOCK; /*!< FLASH user system data unlock register, Address offset: 0x08 */ __IO uint32_t STS; /*!< FLASH status register, Address offset: 0x0C */ __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x10 */ @@ -426,7 +426,7 @@ typedef struct __IO uint32_t SLIB_SET_PWD; /*!< FLASH security library password setting reg, Address offset: 0x160 */ __IO uint32_t SLIB_SET_RANGE; /*!< FLASH security library address setting reg, Address offset: 0x164 */ __IO uint32_t EM_SLIB_SET; /*!< FLASH extension mem security lib set reg, Address offset: 0x168 */ - __IO uint32_t BTM_MODE_SET; /*!< FLASH boot mode setting register, Address offset: 0x16C */ + __IO uint32_t BTM_MODE_SET; /*!< FLASH boot memory mode setting register, Address offset: 0x16C */ __IO uint32_t SLIB_UNLOCK; /*!< FLASH security library unlock register, Address offset: 0x170 */ } FLASH_TypeDef; @@ -436,15 +436,15 @@ typedef struct typedef struct { - __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ - __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ - __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ - __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ - __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ - __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ - __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ - __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ - __IO uint16_t DATA[504]; /*!< USD User data 2 ~ 505, Address offset: 0x1FFF_F810 ~ 0x1FFF_FBFC */ + __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ + __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ + __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ + __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ + __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ + __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ + __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ + __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ + __IO uint16_t DATA[504]; /*!< USD User data 2 ~ 505, Address offset: 0x1FFF_F810 ~ 0x1FFF_FBFC */ } USD_TypeDef; /** @@ -453,13 +453,13 @@ typedef struct typedef struct { - __IO uint32_t CFGLR; /*!< GPIO configuration register low, Address offset: 0x00 */ - __IO uint32_t CFGHR; /*!< GPIO configuration register high, Address offset: 0x04 */ - __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x08 */ - __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x0C */ - __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x10 */ - __IO uint32_t CLR; /*!< GPIO clear register, Address offset: 0x14 */ - __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x18 */ + __IO uint32_t CFGLR; /*!< GPIO configuration register low, Address offset: 0x00 */ + __IO uint32_t CFGHR; /*!< GPIO configuration register high, Address offset: 0x04 */ + __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x08 */ + __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x0C */ + __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x10 */ + __IO uint32_t CLR; /*!< GPIO clear register, Address offset: 0x14 */ + __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x18 */ } GPIO_TypeDef; /** @@ -468,17 +468,17 @@ typedef struct typedef struct { - __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ - __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ - __IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ - __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ - __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ - __IO uint32_t REMAP4; /*!< IOMUX remap register 4, Address offset: 0x24 */ - __IO uint32_t REMAP5; /*!< IOMUX remap register 5, Address offset: 0x28 */ - __IO uint32_t REMAP6; /*!< IOMUX remap register 6, Address offset: 0x2C */ - __IO uint32_t REMAP7; /*!< IOMUX remap register 7, Address offset: 0x30 */ - __IO uint32_t REMAP8; /*!< IOMUX remap register 8, Address offset: 0x34 */ + __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ + __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ + __IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register x, Address offset: 0x08 ~ 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ + __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ + __IO uint32_t REMAP4; /*!< IOMUX remap register 4, Address offset: 0x24 */ + __IO uint32_t REMAP5; /*!< IOMUX remap register 5, Address offset: 0x28 */ + __IO uint32_t REMAP6; /*!< IOMUX remap register 6, Address offset: 0x2C */ + __IO uint32_t REMAP7; /*!< IOMUX remap register 7, Address offset: 0x30 */ + __IO uint32_t REMAP8; /*!< IOMUX remap register 8, Address offset: 0x34 */ } IOMUX_TypeDef; /** @@ -547,9 +547,9 @@ typedef struct __IO uint32_t STS; /*!< SPI status register, Address offset: 0x08 */ __IO uint32_t DT; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CPOLY; /*!< SPI CRC register, Address offset: 0x10 */ - __IO uint32_t RCRC; /*!< SPI RX CRC register, Address offset: 0x14 */ - __IO uint32_t TCRC; /*!< SPI TX CRC register, Address offset: 0x18 */ - __IO uint32_t I2SCTRL; /*!< SPI_I2S register, Address offset: 0x1C */ + __IO uint32_t RCRC; /*!< SPI receive CRC register, Address offset: 0x14 */ + __IO uint32_t TCRC; /*!< SPI transmit CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCTRL; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SCLKP; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; @@ -567,9 +567,9 @@ typedef struct __IO uint32_t SWEVT; /*!< TMR software event register, Address offset: 0x14 */ __IO uint32_t CM1; /*!< TMR channel mode register 1, Address offset: 0x18 */ __IO uint32_t CM2; /*!< TMR channel mode register 2, Address offset: 0x1C */ - __IO uint32_t CCTRL; /*!< TMR Channel control register, Address offset: 0x20 */ - __IO uint32_t CVAL; /*!< TMR counter value, Address offset: 0x24 */ - __IO uint32_t DIV; /*!< TMR division value, Address offset: 0x28 */ + __IO uint32_t CCTRL; /*!< TMR channel control register, Address offset: 0x20 */ + __IO uint32_t CVAL; /*!< TMR counter value register, Address offset: 0x24 */ + __IO uint32_t DIV; /*!< TMR division value register, Address offset: 0x28 */ __IO uint32_t PR; /*!< TMR period register, Address offset: 0x2C */ __IO uint32_t RPR; /*!< TMR repetition period register, Address offset: 0x30 */ __IO uint32_t C1DT; /*!< TMR channel 1 data register, Address offset: 0x34 */ @@ -655,6 +655,7 @@ typedef struct #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /*!< I2C2 base address */ #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) /*!< CAN1 base address */ #define PWC_BASE (APB1PERIPH_BASE + 0x00007000U) /*!< PWC base address */ + #define IOMUX_BASE (APB2PERIPH_BASE + 0x00000000U) /*!< IOMUX base address */ #define EXINT_BASE (APB2PERIPH_BASE + 0x00000400U) /*!< EXINT base address */ #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) /*!< GPIOA base address */ @@ -698,8 +699,8 @@ typedef struct #define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ -/* USB OTG device FS */ -#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG Peripheral Registers base address */ +/* USB OTG FS */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG FS Peripheral Registers base address */ #define USB_OTG_GLOBAL_BASE 0x00000000U /*!< USB OTG Global Registers base address */ #define USB_OTG_DEVICE_BASE 0x00000800U /*!< USB OTG Device ModeRegisters base address */ @@ -710,9 +711,7 @@ typedef struct #define USB_OTG_HOST_PORT_BASE 0x00000440U /*!< USB OTG Host Port Registers base address */ #define USB_OTG_HOST_CHANNEL_BASE 0x00000500U /*!< USB OTG Host Channel Registers base address */ #define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U /*!< USB OTG Host Channel Registers size address */ -#define USB_OTG_DEP3RMPEN_BASE 0x00000D0CU /*!< USB OTG DEP3RMPEN Registers base address */ #define USB_OTG_PCGCCTL_BASE 0x00000E00U /*!< USB OTG Power and Ctrl Registers base address */ -#define USB_OTG_USBDIVRST_BASE 0x00000E10U /*!< USB OTG USBDIVRST Registers base address */ #define USB_OTG_FIFO_BASE 0x00001000U /*!< USB OTG FIFO Registers base address */ #define USB_OTG_FIFO_SIZE 0x00001000U /*!< USB OTG FIFO Registers size address */ @@ -724,57 +723,57 @@ typedef struct * @{ */ -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define CAN1 ((CAN_TypeDef *)CAN1_BASE) -#define CMP ((CMP_TypeDef *)CMP_BASE) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define CRM ((CRM_TypeDef *)CRM_BASE) -#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define DMA2 ((DMA_TypeDef *)DMA2_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) -#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) -#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) -#define ERTC ((ERTC_TypeDef *)ERTC_BASE) -#define EXINT ((EXINT_TypeDef *)EXINT_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define USD ((USD_TypeDef *)USD_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) -#define IOMUX ((IOMUX_TypeDef *)IOMUX_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define I2C2 ((I2C_TypeDef *)I2C2_BASE) -#define PWC ((PWC_TypeDef *)PWC_BASE) -#define SDIO ((SDIO_TypeDef *)SDIO_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) -#define TMR1 ((TMR_TypeDef *)TMR1_BASE) -#define TMR2 ((TMR_TypeDef *)TMR2_BASE) -#define TMR3 ((TMR_TypeDef *)TMR3_BASE) -#define TMR4 ((TMR_TypeDef *)TMR4_BASE) -#define TMR5 ((TMR_TypeDef *)TMR5_BASE) -#define TMR9 ((TMR_TypeDef *)TMR9_BASE) -#define TMR10 ((TMR_TypeDef *)TMR10_BASE) -#define TMR11 ((TMR_TypeDef *)TMR11_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define USART3 ((USART_TypeDef *)USART3_BASE) -#define WDT ((WDT_TypeDef *)WDT_BASE) -#define WWDT ((WWDT_TypeDef *)WWDT_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CMP ((CMP_TypeDef *)CMP_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CRM ((CRM_TypeDef *)CRM_BASE) +#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) +#define ERTC ((ERTC_TypeDef *)ERTC_BASE) +#define EXINT ((EXINT_TypeDef *)EXINT_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USD ((USD_TypeDef *)USD_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define IOMUX ((IOMUX_TypeDef *)IOMUX_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define PWC ((PWC_TypeDef *)PWC_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define TMR1 ((TMR_TypeDef *)TMR1_BASE) +#define TMR2 ((TMR_TypeDef *)TMR2_BASE) +#define TMR3 ((TMR_TypeDef *)TMR3_BASE) +#define TMR4 ((TMR_TypeDef *)TMR4_BASE) +#define TMR5 ((TMR_TypeDef *)TMR5_BASE) +#define TMR9 ((TMR_TypeDef *)TMR9_BASE) +#define TMR10 ((TMR_TypeDef *)TMR10_BASE) +#define TMR11 ((TMR_TypeDef *)TMR11_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) /** * @} @@ -804,7 +803,7 @@ typedef struct #define PWC_CTRL_VRSEL PWC_CTRL_VRSEL_Msk /*!< LDO state select in deep sleep mode */ #define PWC_CTRL_LPSEL_Pos (1U) #define PWC_CTRL_LPSEL_Msk (0x1U << PWC_CTRL_LPSEL_Pos) /*!< 0x00000002 */ -#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep */ +#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep mode */ #define PWC_CTRL_CLSWEF_Pos (2U) #define PWC_CTRL_CLSWEF_Msk (0x1U << PWC_CTRL_CLSWEF_Pos) /*!< 0x00000004 */ #define PWC_CTRL_CLSWEF PWC_CTRL_CLSWEF_Msk /*!< Clear SWEF flag */ @@ -1158,7 +1157,7 @@ typedef struct #define CRM_CLKINT_PLLSTBLF CRM_CLKINT_PLLSTBLF_Msk /*!< PLL stable flag */ #define CRM_CLKINT_CFDF_Pos (7U) #define CRM_CLKINT_CFDF_Msk (0x1U << CRM_CLKINT_CFDF_Pos) /*!< 0x00000080 */ -#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock Failure Detection flag */ +#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock failure detection flag */ #define CRM_CLKINT_LICKSTBLIEN_Pos (8U) #define CRM_CLKINT_LICKSTBLIEN_Msk (0x1U << CRM_CLKINT_LICKSTBLIEN_Pos) /*!< 0x00000100 */ #define CRM_CLKINT_LICKSTBLIEN CRM_CLKINT_LICKSTBLIEN_Msk /*!< LICK stable interrupt enable */ @@ -1389,10 +1388,10 @@ typedef struct #define CRM_BPDC_LEXTEN CRM_BPDC_LEXTEN_Msk /*!< External low-speed oscillator enable */ #define CRM_BPDC_LEXTSTBL_Pos (1U) #define CRM_BPDC_LEXTSTBL_Msk (0x1U << CRM_BPDC_LEXTSTBL_Pos) /*!< 0x00000002 */ -#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< Low speed external oscillator stable */ +#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< External low-speed oscillator stable */ #define CRM_BPDC_LEXTBYPS_Pos (2U) #define CRM_BPDC_LEXTBYPS_Msk (0x1U << CRM_BPDC_LEXTBYPS_Pos) /*!< 0x00000004 */ -#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< Low speed external crystal bypass */ +#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< External low-speed crystal bypass */ /*!< ERTCSEL congiguration */ #define CRM_BPDC_ERTCSEL_Pos (8U) @@ -1503,7 +1502,7 @@ typedef struct #define CRM_MISC1_HICKCAL_KEY_Msk (0xFFU << CRM_MISC1_HICKCAL_KEY_Pos) /*!< 0x000000FF */ #define CRM_MISC1_HICKCAL_KEY CRM_MISC1_HICKCAL_KEY_Msk /*!< HICK calibration key */ #define CRM_MISC1_CLKOUT_SEL_Pos (16U) -#define CRM_MISC1_CLKOUT_SEL_Msk (0x1U << CRN_MISC1_CLKOUT_SEL_Pos) /*!< 0x00010000 */ +#define CRM_MISC1_CLKOUT_SEL_Msk (0x1U << CRM_MISC1_CLKOUT_SEL_Pos) /*!< 0x00010000 */ #define CRM_MISC1_CLKOUT_SEL CRM_MISC1_CLKOUT_SEL_Msk /*!< Clock output selection */ #define CRM_MISC1_CLKFMC_SRC_Pos (20U) #define CRM_MISC1_CLKFMC_SRC_Msk (0x1U << CRM_MISC1_CLKFMC_SRC_Pos) /*!< 0x00100000 */ @@ -1515,7 +1514,7 @@ typedef struct /*!< CLKOUTDIV congiguration */ #define CRM_MISC1_CLKOUTDIV_Pos (28U) #define CRM_MISC1_CLKOUTDIV_Msk (0xFU << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0xF0000000 */ -#define CRM_MISC1_CLKOUTDIV CRM_MISC1_CLKOUTDIV_Msk /*!< CLKOUTDIV[3:0] bits (Clock output division */ +#define CRM_MISC1_CLKOUTDIV CRM_MISC1_CLKOUTDIV_Msk /*!< CLKOUTDIV[3:0] bits (Clock output division) */ #define CRM_MISC1_CLKOUTDIV_0 (0x1U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x10000000 */ #define CRM_MISC1_CLKOUTDIV_1 (0x2U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x20000000 */ #define CRM_MISC1_CLKOUTDIV_2 (0x4U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x40000000 */ @@ -1543,7 +1542,7 @@ typedef struct /*!< AUTO_STEP_EN congiguration */ #define CRM_MISC2_AUTO_STEP_EN_Pos (4U) #define CRM_MISC2_AUTO_STEP_EN_Msk (0x3U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000030 */ -#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] Auto step-by-step SCLK switch enable */ +#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] bits (Auto step-by-step SCLK switch enable) */ #define CRM_MISC2_AUTO_STEP_EN_0 (0x1U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000010 */ #define CRM_MISC2_AUTO_STEP_EN_1 (0x2U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000020 */ @@ -1561,7 +1560,7 @@ typedef struct /*!< WTCYC congiguration */ #define FLASH_PSR_WTCYC_Pos (0U) #define FLASH_PSR_WTCYC_Msk (0x7U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000007 */ -#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] Wait states */ +#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] bits (Wait cycle) */ #define FLASH_PSR_WTCYC_0 (0x1U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000001 */ #define FLASH_PSR_WTCYC_1 (0x2U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000002 */ #define FLASH_PSR_WTCYC_2 (0x4U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000004 */ @@ -1602,7 +1601,7 @@ typedef struct /****************** Bit definition for FLASH_STS register *******************/ #define FLASH_STS_OBF_Pos (0U) #define FLASH_STS_OBF_Msk (0x1U << FLASH_STS_OBF_Pos) /*!< 0x00000001 */ -#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation done flag */ +#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation busy flag */ #define FLASH_STS_PRGMERR_Pos (2U) #define FLASH_STS_PRGMERR_Msk (0x1U << FLASH_STS_PRGMERR_Pos) /*!< 0x00000004 */ #define FLASH_STS_PRGMERR FLASH_STS_PRGMERR_Msk /*!< Programming error */ @@ -1709,10 +1708,10 @@ typedef struct #define SLIB_STS1_SLIB_SS_Msk (0x7FFU << SLIB_STS1_SLIB_SS_Pos) /*!< 0x000007FF */ #define SLIB_STS1_SLIB_SS SLIB_STS1_SLIB_SS_Msk /*!< Security library start page */ #define SLIB_STS1_SLIB_DAT_SS_Pos (11U) -#define SLIB_STS1_SLIB_DAT_SS_Msk (0x3FF8U << SLIB_STS1_SLIB_DAT_SS_Pos) /*!< 0x003FF800 */ +#define SLIB_STS1_SLIB_DAT_SS_Msk (0x7FFU << SLIB_STS1_SLIB_DAT_SS_Pos) /*!< 0x003FF800 */ #define SLIB_STS1_SLIB_DAT_SS SLIB_STS1_SLIB_DAT_SS_Msk /*!< Security library data start page */ #define SLIB_STS1_SLIB_ES_Pos (22U) -#define SLIB_STS1_SLIB_ES_Msk (0xFFCU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ +#define SLIB_STS1_SLIB_ES_Msk (0x3FFU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ #define SLIB_STS1_SLIB_ES SLIB_STS1_SLIB_ES_Msk /*!< Security library end page */ /***************** Bit definition for SLIB_PWD_CLR register ******************/ @@ -1731,10 +1730,10 @@ typedef struct #define SLIB_MISC_STS_SLIB_ULKF_Msk (0x1U << SLIB_MISC_STS_SLIB_ULKF_Pos) /*!< 0x00000004 */ #define SLIB_MISC_STS_SLIB_ULKF SLIB_MISC_STS_SLIB_ULKF_Msk /*!< Security library unlock flag */ -/***************** Bit definition for FLASH_CRC_ARR register *****************/ -#define FLASH_CRC_ARR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ -#define FLASH_CRC_ARR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ARR_CRC_ADDR_Pos) -#define FLASH_CRC_ARR_CRC_ADDR FLASH_CRC_ARR_CRC_ADDR_Msk /*!< CRC address */ +/**************** Bit definition for FLASH_CRC_ADDR register *****************/ +#define FLASH_CRC_ADDR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_ADDR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ADDR_CRC_ADDR_Pos) +#define FLASH_CRC_ADDR_CRC_ADDR FLASH_CRC_ADDR_CRC_ADDR_Msk /*!< CRC address */ /**************** Bit definition for FLASH_CRC_CTRL register *****************/ #define FLASH_CRC_CTRL_CRC_SN_Pos (0U) @@ -1752,7 +1751,7 @@ typedef struct /***************** Bit definition for SLIB_SET_PWD register ******************/ #define SLIB_SET_PWD_SLIB_PSET_VAL_Pos (0U) /*!< 0xFFFFFFFF */ #define SLIB_SET_PWD_SLIB_PSET_VAL_Msk (0xFFFFFFFFU << SLIB_SET_PWD_SLIB_PSET_VAL_Pos) -#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< sLib password setting value */ +#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< Security library password setting value */ /**************** Bit definition for SLIB_SET_RANGE register *****************/ #define SLIB_SET_RANGE_SLIB_SS_SET_Pos (0U) /*!< 0x000007FF */ @@ -1771,7 +1770,7 @@ typedef struct #define EM_SLIB_SET_EM_SLIB_SET EM_SLIB_SET_EM_SLIB_SET_Msk /*!< Extension memory sLib setting */ #define EM_SLIB_SET_EM_SLIB_ISS_SET_Pos (16U) /*!< 0x00FF0000 */ #define EM_SLIB_SET_EM_SLIB_ISS_SET_Msk (0xFFU << EM_SLIB_SET_EM_SLIB_ISS_SET_Pos) -#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page setting */ /***************** Bit definition for BTM_MODE_SET register ******************/ #define BTM_MODE_SET_BTM_MODE_SET_Pos (0U) /*!< 0x000000FF */ @@ -1783,9 +1782,9 @@ typedef struct #define SLIB_UNLOCK_SLIB_UKVAL_Msk (0xFFFFFFFFU << SLIB_UNLOCK_SLIB_UKVAL_Pos) #define SLIB_UNLOCK_SLIB_UKVAL SLIB_UNLOCK_SLIB_UKVAL_Msk /*!< Security library unlock key value */ -#define SLIB_KEY_Pos (0U) +#define SLIB_KEY_Pos (0U) #define SLIB_KEY_Msk (0xA35F6D24U << SLIB_KEY_Pos) /*!< 0xA35F6D24 */ -#define SLIB_KEY SLIB_KEY_Msk +#define SLIB_KEY SLIB_KEY_Msk /*!< Security library key */ /*----------------------------------------------------------------------------*/ @@ -1805,7 +1804,7 @@ typedef struct #define FLASH_SSB_nSSB_Msk (0xFFU << FLASH_SSB_nSSB_Pos) /*!< 0xFF000000 */ #define FLASH_SSB_nSSB FLASH_SSB_nSSB_Msk /*!< Inverse code of system configuration byte */ -/****************** Bit definition for FLASH_DATA0 register *****************/ +/***************** Bit definition for FLASH_DATA0 register ******************/ #define FLASH_DATA0_DATA0_Pos (0U) #define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data 0 */ @@ -1813,7 +1812,7 @@ typedef struct #define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< Inverse code of user data 0 */ -/****************** Bit definition for FLASH_DATA1 register *****************/ +/***************** Bit definition for FLASH_DATA1 register ******************/ #define FLASH_DATA1_DATA1_Pos (16U) #define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data 1 */ @@ -1853,15 +1852,7 @@ typedef struct #define FLASH_EPP3_nEPP3_Msk (0xFFU << FLASH_EPP3_nEPP3_Pos) /*!< 0xFF000000 */ #define FLASH_EPP3_nEPP3 FLASH_EPP3_nEPP3_Msk /*!< Inverse code of flash erase/write protection byte 3 */ -/***************** Bit definition for FLASH_EOPB0 register ******************/ -#define FLASH_EOPB0_EOPB0_Pos (0U) -#define FLASH_EOPB0_EOPB0_Msk (0xFFU << FLASH_EOPB0_EOPB0_Pos) /*!< 0x000000FF */ -#define FLASH_EOPB0_EOPB0 FLASH_EOPB0_EOPB0_Msk /*!< Extended system options */ -#define FLASH_EOPB0_nEOPB0_Pos (8U) -#define FLASH_EOPB0_nEOPB0_Msk (0xFFU << FLASH_EOPB0_nEOPB0_Pos) /*!< 0x0000FF00 */ -#define FLASH_EOPB0_nEOPB0 FLASH_EOPB0_nEOPB0_Msk /*!< Inverse code of extended system options */ - -/****************** Bit definition for FLASH_DATA2 register *****************/ +/***************** Bit definition for FLASH_DATA2 register ******************/ #define FLASH_DATA2_DATA2_Pos (0U) #define FLASH_DATA2_DATA2_Msk (0xFFU << FLASH_DATA2_DATA2_Pos) /*!< 0x000000FF */ #define FLASH_DATA2_DATA2 FLASH_DATA2_DATA2_Msk /*!< User data 2 */ @@ -1869,7 +1860,7 @@ typedef struct #define FLASH_DATA2_nDATA2_Msk (0xFFU << FLASH_DATA2_nDATA2_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA2_nDATA2 FLASH_DATA2_nDATA2_Msk /*!< Inverse code of user data 2 */ -/****************** Bit definition for FLASH_DATA3 register *****************/ +/***************** Bit definition for FLASH_DATA3 register ******************/ #define FLASH_DATA3_DATA3_Pos (16U) #define FLASH_DATA3_DATA3_Msk (0xFFU << FLASH_DATA3_DATA3_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA3_DATA3 FLASH_DATA3_DATA3_Msk /*!< User data 3 */ @@ -1877,7 +1868,7 @@ typedef struct #define FLASH_DATA3_nDATA3_Msk (0xFFU << FLASH_DATA3_nDATA3_Pos) /*!< 0xFF000000 */ #define FLASH_DATA3_nDATA3 FLASH_DATA3_nDATA3_Msk /*!< Inverse code of user data 3 */ -/****************** Bit definition for FLASH_DATA4 register *****************/ +/***************** Bit definition for FLASH_DATA4 register ******************/ #define FLASH_DATA4_DATA4_Pos (0U) #define FLASH_DATA4_DATA4_Msk (0xFFU << FLASH_DATA4_DATA4_Pos) /*!< 0x000000FF */ #define FLASH_DATA4_DATA4 FLASH_DATA4_DATA4_Msk /*!< User data 4 */ @@ -1885,7 +1876,7 @@ typedef struct #define FLASH_DATA4_nDATA4_Msk (0xFFU << FLASH_DATA4_nDATA4_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA4_nDATA4 FLASH_DATA4_nDATA4_Msk /*!< Inverse code of user data 4 */ -/****************** Bit definition for FLASH_DATA5 register *****************/ +/***************** Bit definition for FLASH_DATA5 register ******************/ #define FLASH_DATA5_DATA5_Pos (16U) #define FLASH_DATA5_DATA5_Msk (0xFFU << FLASH_DATA5_DATA5_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA5_DATA5 FLASH_DATA5_DATA5_Msk /*!< User data 5 */ @@ -1893,7 +1884,7 @@ typedef struct #define FLASH_DATA5_nDATA5_Msk (0xFFU << FLASH_DATA5_nDATA5_Pos) /*!< 0xFF000000 */ #define FLASH_DATA5_nDATA5 FLASH_DATA5_nDATA5_Msk /*!< Inverse code of user data 5 */ -/****************** Bit definition for FLASH_DATA6 register *****************/ +/***************** Bit definition for FLASH_DATA6 register ******************/ #define FLASH_DATA6_DATA6_Pos (0U) #define FLASH_DATA6_DATA6_Msk (0xFFU << FLASH_DATA6_DATA6_Pos) /*!< 0x000000FF */ #define FLASH_DATA6_DATA6 FLASH_DATA6_DATA6_Msk /*!< User data 6 */ @@ -1901,7 +1892,7 @@ typedef struct #define FLASH_DATA6_nDATA6_Msk (0xFFU << FLASH_DATA6_nDATA6_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA6_nDATA6 FLASH_DATA6_nDATA6_Msk /*!< Inverse code of user data 6 */ -/****************** Bit definition for FLASH_DATA7 register *****************/ +/***************** Bit definition for FLASH_DATA7 register ******************/ #define FLASH_DATA7_DATA7_Pos (16U) #define FLASH_DATA7_DATA7_Msk (0xFFU << FLASH_DATA7_DATA7_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA7_DATA7 FLASH_DATA7_DATA7_Msk /*!< User data 7 */ @@ -1922,48 +1913,56 @@ typedef struct #define GPIO_CFGLR_IOMC_Msk (0x33333333U << GPIO_CFGLR_IOMC_Pos) /*!< 0x33333333 */ #define GPIO_CFGLR_IOMC GPIO_CFGLR_IOMC_Msk /*!< GPIO x mode configuration */ +/*!< IOMC0 configuration */ #define GPIO_CFGLR_IOMC0_Pos (0U) #define GPIO_CFGLR_IOMC0_Msk (0x3U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000003 */ #define GPIO_CFGLR_IOMC0 GPIO_CFGLR_IOMC0_Msk /*!< IOMC0[1:0] bits (GPIO x mode configuration, pin 0) */ #define GPIO_CFGLR_IOMC0_0 (0x1U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000001 */ #define GPIO_CFGLR_IOMC0_1 (0x2U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000002 */ +/*!< IOMC1 configuration */ #define GPIO_CFGLR_IOMC1_Pos (4U) #define GPIO_CFGLR_IOMC1_Msk (0x3U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000030 */ #define GPIO_CFGLR_IOMC1 GPIO_CFGLR_IOMC1_Msk /*!< IOMC1[1:0] bits (GPIO x mode configuration, pin 1) */ #define GPIO_CFGLR_IOMC1_0 (0x1U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000010 */ #define GPIO_CFGLR_IOMC1_1 (0x2U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000020 */ +/*!< IOMC2 configuration */ #define GPIO_CFGLR_IOMC2_Pos (8U) #define GPIO_CFGLR_IOMC2_Msk (0x3U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000300 */ #define GPIO_CFGLR_IOMC2 GPIO_CFGLR_IOMC2_Msk /*!< IOMC2[1:0] bits (GPIO x mode configuration, pin 2) */ #define GPIO_CFGLR_IOMC2_0 (0x1U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000100 */ #define GPIO_CFGLR_IOMC2_1 (0x2U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000200 */ +/*!< IOMC3 configuration */ #define GPIO_CFGLR_IOMC3_Pos (12U) #define GPIO_CFGLR_IOMC3_Msk (0x3U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00003000 */ #define GPIO_CFGLR_IOMC3 GPIO_CFGLR_IOMC3_Msk /*!< IOMC3[1:0] bits (GPIO x mode configuration, pin 3) */ #define GPIO_CFGLR_IOMC3_0 (0x1U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00001000 */ #define GPIO_CFGLR_IOMC3_1 (0x2U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00002000 */ +/*!< IOMC4 configuration */ #define GPIO_CFGLR_IOMC4_Pos (16U) #define GPIO_CFGLR_IOMC4_Msk (0x3U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00030000 */ #define GPIO_CFGLR_IOMC4 GPIO_CFGLR_IOMC4_Msk /*!< IOMC4[1:0] bits (GPIO x mode configuration, pin 4) */ #define GPIO_CFGLR_IOMC4_0 (0x1U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00010000 */ #define GPIO_CFGLR_IOMC4_1 (0x2U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00020000 */ +/*!< IOMC5 configuration */ #define GPIO_CFGLR_IOMC5_Pos (20U) #define GPIO_CFGLR_IOMC5_Msk (0x3U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00300000 */ #define GPIO_CFGLR_IOMC5 GPIO_CFGLR_IOMC5_Msk /*!< IOMC5[1:0] bits (GPIO x mode configuration, pin 5) */ #define GPIO_CFGLR_IOMC5_0 (0x1U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00100000 */ #define GPIO_CFGLR_IOMC5_1 (0x2U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00200000 */ +/*!< IOMC6 configuration */ #define GPIO_CFGLR_IOMC6_Pos (24U) #define GPIO_CFGLR_IOMC6_Msk (0x3U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x03000000 */ #define GPIO_CFGLR_IOMC6 GPIO_CFGLR_IOMC6_Msk /*!< IOMC6[1:0] bits (GPIO x mode configuration, pin 6) */ #define GPIO_CFGLR_IOMC6_0 (0x1U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x01000000 */ #define GPIO_CFGLR_IOMC6_1 (0x2U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x02000000 */ +/*!< IOMC7 configuration */ #define GPIO_CFGLR_IOMC7_Pos (28U) #define GPIO_CFGLR_IOMC7_Msk (0x3U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x30000000 */ #define GPIO_CFGLR_IOMC7 GPIO_CFGLR_IOMC7_Msk /*!< IOMC7[1:0] bits (GPIO x mode configuration, pin 7) */ @@ -1974,48 +1973,56 @@ typedef struct #define GPIO_CFGLR_IOFC_Msk (0x33333333U << GPIO_CFGLR_IOFC_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CFGLR_IOFC GPIO_CFGLR_IOFC_Msk /*!< GPIO x function configuration */ +/*!< IOFC0 configuration */ #define GPIO_CFGLR_IOFC0_Pos (2U) #define GPIO_CFGLR_IOFC0_Msk (0x3U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x0000000C */ #define GPIO_CFGLR_IOFC0 GPIO_CFGLR_IOFC0_Msk /*!< IOFC0[1:0] bits (GPIO x function configuration, pin 0) */ #define GPIO_CFGLR_IOFC0_0 (0x1U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000004 */ #define GPIO_CFGLR_IOFC0_1 (0x2U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000008 */ +/*!< IOFC1 configuration */ #define GPIO_CFGLR_IOFC1_Pos (6U) #define GPIO_CFGLR_IOFC1_Msk (0x3U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x000000C0 */ #define GPIO_CFGLR_IOFC1 GPIO_CFGLR_IOFC1_Msk /*!< IOFC1[1:0] bits (GPIO x function configuration, pin 1) */ #define GPIO_CFGLR_IOFC1_0 (0x1U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000040 */ #define GPIO_CFGLR_IOFC1_1 (0x2U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000080 */ +/*!< IOFC2 configuration */ #define GPIO_CFGLR_IOFC2_Pos (10U) #define GPIO_CFGLR_IOFC2_Msk (0x3U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000C00 */ #define GPIO_CFGLR_IOFC2 GPIO_CFGLR_IOFC2_Msk /*!< IOFC2[1:0] bits (GPIO x function configuration, pin 2) */ #define GPIO_CFGLR_IOFC2_0 (0x1U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000400 */ #define GPIO_CFGLR_IOFC2_1 (0x2U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000800 */ +/*!< IOFC3 configuration */ #define GPIO_CFGLR_IOFC3_Pos (14U) #define GPIO_CFGLR_IOFC3_Msk (0x3U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x0000C000 */ #define GPIO_CFGLR_IOFC3 GPIO_CFGLR_IOFC3_Msk /*!< IOFC3[1:0] bits (GPIO x function configuration, pin 3) */ #define GPIO_CFGLR_IOFC3_0 (0x1U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00004000 */ #define GPIO_CFGLR_IOFC3_1 (0x2U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00008000 */ +/*!< IOFC4 configuration */ #define GPIO_CFGLR_IOFC4_Pos (18U) #define GPIO_CFGLR_IOFC4_Msk (0x3U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x000C0000 */ #define GPIO_CFGLR_IOFC4 GPIO_CFGLR_IOFC4_Msk /*!< IOFC4[1:0] bits (GPIO x function configuration, pin 4) */ #define GPIO_CFGLR_IOFC4_0 (0x1U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00040000 */ #define GPIO_CFGLR_IOFC4_1 (0x2U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00080000 */ +/*!< IOFC5 configuration */ #define GPIO_CFGLR_IOFC5_Pos (22U) #define GPIO_CFGLR_IOFC5_Msk (0x3U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00C00000 */ #define GPIO_CFGLR_IOFC5 GPIO_CFGLR_IOFC5_Msk /*!< IOFC5[1:0] bits (GPIO x function configuration, pin 5) */ #define GPIO_CFGLR_IOFC5_0 (0x1U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00400000 */ #define GPIO_CFGLR_IOFC5_1 (0x2U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00800000 */ +/*!< IOFC6 configuration */ #define GPIO_CFGLR_IOFC6_Pos (26U) #define GPIO_CFGLR_IOFC6_Msk (0x3U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x0C000000 */ #define GPIO_CFGLR_IOFC6 GPIO_CFGLR_IOFC6_Msk /*!< IOFC6[1:0] bits (GPIO x function configuration, pin 6) */ #define GPIO_CFGLR_IOFC6_0 (0x1U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x04000000 */ #define GPIO_CFGLR_IOFC6_1 (0x2U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x08000000 */ +/*!< IOFC7 configuration */ #define GPIO_CFGLR_IOFC7_Pos (30U) #define GPIO_CFGLR_IOFC7_Msk (0x3U << GPIO_CFGLR_IOFC7_Pos) /*!< 0xC0000000 */ #define GPIO_CFGLR_IOFC7 GPIO_CFGLR_IOFC7_Msk /*!< IOFC7[1:0] bits (GPIO x function configuration, pin 7) */ @@ -2027,48 +2034,56 @@ typedef struct #define GPIO_CFGHR_IOMC_Msk (0x33333333U << GPIO_CFGHR_IOMC_Pos) /*!< 0x33333333 */ #define GPIO_CFGHR_IOMC GPIO_CFGHR_IOMC_Msk /*!< GPIO x mode configuration */ +/*!< IOMC8 configuration */ #define GPIO_CFGHR_IOMC8_Pos (0U) #define GPIO_CFGHR_IOMC8_Msk (0x3U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000003 */ #define GPIO_CFGHR_IOMC8 GPIO_CFGHR_IOMC8_Msk /*!< IOMC8[1:0] bits (GPIO x mode configuration, pin 8) */ #define GPIO_CFGHR_IOMC8_0 (0x1U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000001 */ #define GPIO_CFGHR_IOMC8_1 (0x2U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000002 */ +/*!< IOMC9 configuration */ #define GPIO_CFGHR_IOMC9_Pos (4U) #define GPIO_CFGHR_IOMC9_Msk (0x3U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000030 */ #define GPIO_CFGHR_IOMC9 GPIO_CFGHR_IOMC9_Msk /*!< IOMC9[1:0] bits (GPIO x mode configuration, pin 9) */ #define GPIO_CFGHR_IOMC9_0 (0x1U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000010 */ #define GPIO_CFGHR_IOMC9_1 (0x2U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000020 */ +/*!< IOMC10 configuration */ #define GPIO_CFGHR_IOMC10_Pos (8U) #define GPIO_CFGHR_IOMC10_Msk (0x3U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000300 */ #define GPIO_CFGHR_IOMC10 GPIO_CFGHR_IOMC10_Msk /*!< IOMC10[1:0] bits (GPIO x mode configuration, pin 10) */ #define GPIO_CFGHR_IOMC10_0 (0x1U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000100 */ #define GPIO_CFGHR_IOMC10_1 (0x2U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000200 */ +/*!< IOMC11 configuration */ #define GPIO_CFGHR_IOMC11_Pos (12U) #define GPIO_CFGHR_IOMC11_Msk (0x3U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00003000 */ #define GPIO_CFGHR_IOMC11 GPIO_CFGHR_IOMC11_Msk /*!< IOMC11[1:0] bits (GPIO x mode configuration, pin 11) */ #define GPIO_CFGHR_IOMC11_0 (0x1U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00001000 */ #define GPIO_CFGHR_IOMC11_1 (0x2U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00002000 */ +/*!< IOMC12 configuration */ #define GPIO_CFGHR_IOMC12_Pos (16U) #define GPIO_CFGHR_IOMC12_Msk (0x3U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00030000 */ #define GPIO_CFGHR_IOMC12 GPIO_CFGHR_IOMC12_Msk /*!< IOMC12[1:0] bits (GPIO x mode configuration, pin 12) */ #define GPIO_CFGHR_IOMC12_0 (0x1U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00010000 */ #define GPIO_CFGHR_IOMC12_1 (0x2U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00020000 */ +/*!< IOMC13 configuration */ #define GPIO_CFGHR_IOMC13_Pos (20U) #define GPIO_CFGHR_IOMC13_Msk (0x3U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00300000 */ #define GPIO_CFGHR_IOMC13 GPIO_CFGHR_IOMC13_Msk /*!< IOMC13[1:0] bits (GPIO x mode configuration, pin 13) */ #define GPIO_CFGHR_IOMC13_0 (0x1U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00100000 */ #define GPIO_CFGHR_IOMC13_1 (0x2U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00200000 */ +/*!< IOMC14 configuration */ #define GPIO_CFGHR_IOMC14_Pos (24U) #define GPIO_CFGHR_IOMC14_Msk (0x3U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x03000000 */ #define GPIO_CFGHR_IOMC14 GPIO_CFGHR_IOMC14_Msk /*!< IOMC14[1:0] bits (GPIO x mode configuration, pin 14) */ #define GPIO_CFGHR_IOMC14_0 (0x1U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x01000000 */ #define GPIO_CFGHR_IOMC14_1 (0x2U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x02000000 */ +/*!< IOMC15 configuration */ #define GPIO_CFGHR_IOMC15_Pos (28U) #define GPIO_CFGHR_IOMC15_Msk (0x3U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x30000000 */ #define GPIO_CFGHR_IOMC15 GPIO_CFGHR_IOMC15_Msk /*!< IOMC15[1:0] bits (GPIO x mode configuration, pin 15) */ @@ -2079,48 +2094,56 @@ typedef struct #define GPIO_CFGHR_IOFC_Msk (0x33333333U << GPIO_CFGHR_IOFC_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CFGHR_IOFC GPIO_CFGHR_IOFC_Msk /*!< GPIO x function configuration */ +/*!< IOFC8 configuration */ #define GPIO_CFGHR_IOFC8_Pos (2U) #define GPIO_CFGHR_IOFC8_Msk (0x3U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x0000000C */ #define GPIO_CFGHR_IOFC8 GPIO_CFGHR_IOFC8_Msk /*!< IOFC8[1:0] bits (GPIO x function configuration, pin 8) */ #define GPIO_CFGHR_IOFC8_0 (0x1U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000004 */ #define GPIO_CFGHR_IOFC8_1 (0x2U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000008 */ +/*!< IOFC9 configuration */ #define GPIO_CFGHR_IOFC9_Pos (6U) #define GPIO_CFGHR_IOFC9_Msk (0x3U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x000000C0 */ #define GPIO_CFGHR_IOFC9 GPIO_CFGHR_IOFC9_Msk /*!< IOFC9[1:0] bits (GPIO x function configuration, pin 9) */ #define GPIO_CFGHR_IOFC9_0 (0x1U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000040 */ #define GPIO_CFGHR_IOFC9_1 (0x2U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000080 */ +/*!< IOFC10 configuration */ #define GPIO_CFGHR_IOFC10_Pos (10U) #define GPIO_CFGHR_IOFC10_Msk (0x3U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000C00 */ #define GPIO_CFGHR_IOFC10 GPIO_CFGHR_IOFC10_Msk /*!< IOFC10[1:0] bits (GPIO x function configuration, pin 10) */ #define GPIO_CFGHR_IOFC10_0 (0x1U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000400 */ #define GPIO_CFGHR_IOFC10_1 (0x2U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000800 */ +/*!< IOFC11 configuration */ #define GPIO_CFGHR_IOFC11_Pos (14U) #define GPIO_CFGHR_IOFC11_Msk (0x3U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x0000C000 */ #define GPIO_CFGHR_IOFC11 GPIO_CFGHR_IOFC11_Msk /*!< IOFC11[1:0] bits (GPIO x function configuration, pin 11) */ #define GPIO_CFGHR_IOFC11_0 (0x1U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00004000 */ #define GPIO_CFGHR_IOFC11_1 (0x2U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00008000 */ +/*!< IOFC12 configuration */ #define GPIO_CFGHR_IOFC12_Pos (18U) #define GPIO_CFGHR_IOFC12_Msk (0x3U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x000C0000 */ #define GPIO_CFGHR_IOFC12 GPIO_CFGHR_IOFC12_Msk /*!< IOFC12[1:0] bits (GPIO x function configuration, pin 12) */ #define GPIO_CFGHR_IOFC12_0 (0x1U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00040000 */ #define GPIO_CFGHR_IOFC12_1 (0x2U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00080000 */ +/*!< IOFC13 configuration */ #define GPIO_CFGHR_IOFC13_Pos (22U) #define GPIO_CFGHR_IOFC13_Msk (0x3U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00C00000 */ #define GPIO_CFGHR_IOFC13 GPIO_CFGHR_IOFC13_Msk /*!< IOFC13[1:0] bits (GPIO x function configuration, pin 13) */ #define GPIO_CFGHR_IOFC13_0 (0x1U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00400000 */ #define GPIO_CFGHR_IOFC13_1 (0x2U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00800000 */ +/*!< IOFC14 configuration */ #define GPIO_CFGHR_IOFC14_Pos (26U) #define GPIO_CFGHR_IOFC14_Msk (0x3U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x0C000000 */ #define GPIO_CFGHR_IOFC14 GPIO_CFGHR_IOFC14_Msk /*!< IOFC14[1:0] bits (GPIO x function configuration, pin 14) */ #define GPIO_CFGHR_IOFC14_0 (0x1U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x04000000 */ #define GPIO_CFGHR_IOFC14_1 (0x2U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x08000000 */ +/*!< IOFC15 configuration */ #define GPIO_CFGHR_IOFC15_Pos (30U) #define GPIO_CFGHR_IOFC15_Msk (0x3U << GPIO_CFGHR_IOFC15_Pos) /*!< 0xC0000000 */ #define GPIO_CFGHR_IOFC15 GPIO_CFGHR_IOFC15_Msk /*!< IOFC15[1:0] bits (GPIO x function configuration, pin 15) */ @@ -2130,300 +2153,300 @@ typedef struct /*!<**************** Bit definition for GPIO_IDT register *******************/ #define GPIO_IDT_IDT0_Pos (0U) #define GPIO_IDT_IDT0_Msk (0x1U << GPIO_IDT_IDT0_Pos) /*!< 0x00000001 */ -#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, bit 0 */ +#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, pin 0 */ #define GPIO_IDT_IDT1_Pos (1U) #define GPIO_IDT_IDT1_Msk (0x1U << GPIO_IDT_IDT1_Pos) /*!< 0x00000002 */ -#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, bit 1 */ +#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, pin 1 */ #define GPIO_IDT_IDT2_Pos (2U) #define GPIO_IDT_IDT2_Msk (0x1U << GPIO_IDT_IDT2_Pos) /*!< 0x00000004 */ -#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, bit 2 */ +#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, pin 2 */ #define GPIO_IDT_IDT3_Pos (3U) #define GPIO_IDT_IDT3_Msk (0x1U << GPIO_IDT_IDT3_Pos) /*!< 0x00000008 */ -#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, bit 3 */ +#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, pin 3 */ #define GPIO_IDT_IDT4_Pos (4U) #define GPIO_IDT_IDT4_Msk (0x1U << GPIO_IDT_IDT4_Pos) /*!< 0x00000010 */ -#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, bit 4 */ +#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, pin 4 */ #define GPIO_IDT_IDT5_Pos (5U) #define GPIO_IDT_IDT5_Msk (0x1U << GPIO_IDT_IDT5_Pos) /*!< 0x00000020 */ -#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, bit 5 */ +#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, pin 5 */ #define GPIO_IDT_IDT6_Pos (6U) #define GPIO_IDT_IDT6_Msk (0x1U << GPIO_IDT_IDT6_Pos) /*!< 0x00000040 */ -#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, bit 6 */ +#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, pin 6 */ #define GPIO_IDT_IDT7_Pos (7U) #define GPIO_IDT_IDT7_Msk (0x1U << GPIO_IDT_IDT7_Pos) /*!< 0x00000080 */ -#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, bit 7 */ +#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, pin 7 */ #define GPIO_IDT_IDT8_Pos (8U) #define GPIO_IDT_IDT8_Msk (0x1U << GPIO_IDT_IDT8_Pos) /*!< 0x00000100 */ -#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, bit 8 */ +#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, pin 8 */ #define GPIO_IDT_IDT9_Pos (9U) #define GPIO_IDT_IDT9_Msk (0x1U << GPIO_IDT_IDT9_Pos) /*!< 0x00000200 */ -#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, bit 9 */ +#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, pin 9 */ #define GPIO_IDT_IDT10_Pos (10U) #define GPIO_IDT_IDT10_Msk (0x1U << GPIO_IDT_IDT10_Pos) /*!< 0x00000400 */ -#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, bit 10 */ +#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, pin 10 */ #define GPIO_IDT_IDT11_Pos (11U) #define GPIO_IDT_IDT11_Msk (0x1U << GPIO_IDT_IDT11_Pos) /*!< 0x00000800 */ -#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, bit 11 */ +#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, pin 11 */ #define GPIO_IDT_IDT12_Pos (12U) #define GPIO_IDT_IDT12_Msk (0x1U << GPIO_IDT_IDT12_Pos) /*!< 0x00001000 */ -#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, bit 12 */ +#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, pin 12 */ #define GPIO_IDT_IDT13_Pos (13U) #define GPIO_IDT_IDT13_Msk (0x1U << GPIO_IDT_IDT13_Pos) /*!< 0x00002000 */ -#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, bit 13 */ +#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, pin 13 */ #define GPIO_IDT_IDT14_Pos (14U) #define GPIO_IDT_IDT14_Msk (0x1U << GPIO_IDT_IDT14_Pos) /*!< 0x00004000 */ -#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, bit 14 */ +#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, pin 14 */ #define GPIO_IDT_IDT15_Pos (15U) #define GPIO_IDT_IDT15_Msk (0x1U << GPIO_IDT_IDT15_Pos) /*!< 0x00008000 */ -#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, bit 15 */ +#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, pin 15 */ /******************* Bit definition for GPIO_ODT register *******************/ #define GPIO_ODT_ODT0_Pos (0U) #define GPIO_ODT_ODT0_Msk (0x1U << GPIO_ODT_ODT0_Pos) /*!< 0x00000001 */ -#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, bit 0 */ +#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, pin 0 */ #define GPIO_ODT_ODT1_Pos (1U) #define GPIO_ODT_ODT1_Msk (0x1U << GPIO_ODT_ODT1_Pos) /*!< 0x00000002 */ -#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, bit 1 */ +#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, pin 1 */ #define GPIO_ODT_ODT2_Pos (2U) #define GPIO_ODT_ODT2_Msk (0x1U << GPIO_ODT_ODT2_Pos) /*!< 0x00000004 */ -#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, bit 2 */ +#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, pin 2 */ #define GPIO_ODT_ODT3_Pos (3U) #define GPIO_ODT_ODT3_Msk (0x1U << GPIO_ODT_ODT3_Pos) /*!< 0x00000008 */ -#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, bit 3 */ +#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, pin 3 */ #define GPIO_ODT_ODT4_Pos (4U) #define GPIO_ODT_ODT4_Msk (0x1U << GPIO_ODT_ODT4_Pos) /*!< 0x00000010 */ -#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, bit 4 */ +#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, pin 4 */ #define GPIO_ODT_ODT5_Pos (5U) #define GPIO_ODT_ODT5_Msk (0x1U << GPIO_ODT_ODT5_Pos) /*!< 0x00000020 */ -#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, bit 5 */ +#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, pin 5 */ #define GPIO_ODT_ODT6_Pos (6U) #define GPIO_ODT_ODT6_Msk (0x1U << GPIO_ODT_ODT6_Pos) /*!< 0x00000040 */ -#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, bit 6 */ +#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, pin 6 */ #define GPIO_ODT_ODT7_Pos (7U) #define GPIO_ODT_ODT7_Msk (0x1U << GPIO_ODT_ODT7_Pos) /*!< 0x00000080 */ -#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, bit 7 */ +#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, pin 7 */ #define GPIO_ODT_ODT8_Pos (8U) #define GPIO_ODT_ODT8_Msk (0x1U << GPIO_ODT_ODT8_Pos) /*!< 0x00000100 */ -#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, bit 8 */ +#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, pin 8 */ #define GPIO_ODT_ODT9_Pos (9U) #define GPIO_ODT_ODT9_Msk (0x1U << GPIO_ODT_ODT9_Pos) /*!< 0x00000200 */ -#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, bit 9 */ +#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, pin 9 */ #define GPIO_ODT_ODT10_Pos (10U) #define GPIO_ODT_ODT10_Msk (0x1U << GPIO_ODT_ODT10_Pos) /*!< 0x00000400 */ -#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, bit 10 */ +#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, pin 10 */ #define GPIO_ODT_ODT11_Pos (11U) #define GPIO_ODT_ODT11_Msk (0x1U << GPIO_ODT_ODT11_Pos) /*!< 0x00000800 */ -#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, bit 11 */ +#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, pin 11 */ #define GPIO_ODT_ODT12_Pos (12U) #define GPIO_ODT_ODT12_Msk (0x1U << GPIO_ODT_ODT12_Pos) /*!< 0x00001000 */ -#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, bit 12 */ +#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, pin 12 */ #define GPIO_ODT_ODT13_Pos (13U) #define GPIO_ODT_ODT13_Msk (0x1U << GPIO_ODT_ODT13_Pos) /*!< 0x00002000 */ -#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, bit 13 */ +#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, pin 13 */ #define GPIO_ODT_ODT14_Pos (14U) #define GPIO_ODT_ODT14_Msk (0x1U << GPIO_ODT_ODT14_Pos) /*!< 0x00004000 */ -#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, bit 14 */ +#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, pin 14 */ #define GPIO_ODT_ODT15_Pos (15U) #define GPIO_ODT_ODT15_Msk (0x1U << GPIO_ODT_ODT15_Pos) /*!< 0x00008000 */ -#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, bit 15 */ +#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, pin 15 */ /******************* Bit definition for GPIO_SCR register *******************/ #define GPIO_SCR_IOSB0_Pos (0U) #define GPIO_SCR_IOSB0_Msk (0x1U << GPIO_SCR_IOSB0_Pos) /*!< 0x00000001 */ -#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit 0 */ +#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit, pin 0 */ #define GPIO_SCR_IOSB1_Pos (1U) #define GPIO_SCR_IOSB1_Msk (0x1U << GPIO_SCR_IOSB1_Pos) /*!< 0x00000002 */ -#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit 1 */ +#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit, pin 1 */ #define GPIO_SCR_IOSB2_Pos (2U) #define GPIO_SCR_IOSB2_Msk (0x1U << GPIO_SCR_IOSB2_Pos) /*!< 0x00000004 */ -#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit 2 */ +#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit, pin 2 */ #define GPIO_SCR_IOSB3_Pos (3U) #define GPIO_SCR_IOSB3_Msk (0x1U << GPIO_SCR_IOSB3_Pos) /*!< 0x00000008 */ -#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit 3 */ +#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit, pin 3 */ #define GPIO_SCR_IOSB4_Pos (4U) #define GPIO_SCR_IOSB4_Msk (0x1U << GPIO_SCR_IOSB4_Pos) /*!< 0x00000010 */ -#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit 4 */ +#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit, pin 4 */ #define GPIO_SCR_IOSB5_Pos (5U) #define GPIO_SCR_IOSB5_Msk (0x1U << GPIO_SCR_IOSB5_Pos) /*!< 0x00000020 */ -#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit 5 */ +#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit, pin 5 */ #define GPIO_SCR_IOSB6_Pos (6U) #define GPIO_SCR_IOSB6_Msk (0x1U << GPIO_SCR_IOSB6_Pos) /*!< 0x00000040 */ -#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit 6 */ +#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit, pin 6 */ #define GPIO_SCR_IOSB7_Pos (7U) #define GPIO_SCR_IOSB7_Msk (0x1U << GPIO_SCR_IOSB7_Pos) /*!< 0x00000080 */ -#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit 7 */ +#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit, pin 7 */ #define GPIO_SCR_IOSB8_Pos (8U) #define GPIO_SCR_IOSB8_Msk (0x1U << GPIO_SCR_IOSB8_Pos) /*!< 0x00000100 */ -#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit 8 */ +#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit, pin 8 */ #define GPIO_SCR_IOSB9_Pos (9U) #define GPIO_SCR_IOSB9_Msk (0x1U << GPIO_SCR_IOSB9_Pos) /*!< 0x00000200 */ -#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit 9 */ +#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit, pin 9 */ #define GPIO_SCR_IOSB10_Pos (10U) #define GPIO_SCR_IOSB10_Msk (0x1U << GPIO_SCR_IOSB10_Pos) /*!< 0x00000400 */ -#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit 10 */ +#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit, pin 10 */ #define GPIO_SCR_IOSB11_Pos (11U) #define GPIO_SCR_IOSB11_Msk (0x1U << GPIO_SCR_IOSB11_Pos) /*!< 0x00000800 */ -#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit 11 */ +#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit, pin 11 */ #define GPIO_SCR_IOSB12_Pos (12U) #define GPIO_SCR_IOSB12_Msk (0x1U << GPIO_SCR_IOSB12_Pos) /*!< 0x00001000 */ -#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit 12 */ +#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit, pin 12 */ #define GPIO_SCR_IOSB13_Pos (13U) #define GPIO_SCR_IOSB13_Msk (0x1U << GPIO_SCR_IOSB13_Pos) /*!< 0x00002000 */ -#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit 13 */ +#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit, pin 13 */ #define GPIO_SCR_IOSB14_Pos (14U) #define GPIO_SCR_IOSB14_Msk (0x1U << GPIO_SCR_IOSB14_Pos) /*!< 0x00004000 */ -#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit 14 */ +#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit, pin 14 */ #define GPIO_SCR_IOSB15_Pos (15U) #define GPIO_SCR_IOSB15_Msk (0x1U << GPIO_SCR_IOSB15_Pos) /*!< 0x00008000 */ -#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit 15 */ +#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit, pin 15 */ #define GPIO_SCR_IOCB0_Pos (16U) #define GPIO_SCR_IOCB0_Msk (0x1U << GPIO_SCR_IOCB0_Pos) /*!< 0x00010000 */ -#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ #define GPIO_SCR_IOCB1_Pos (17U) #define GPIO_SCR_IOCB1_Msk (0x1U << GPIO_SCR_IOCB1_Pos) /*!< 0x00020000 */ -#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ #define GPIO_SCR_IOCB2_Pos (18U) #define GPIO_SCR_IOCB2_Msk (0x1U << GPIO_SCR_IOCB2_Pos) /*!< 0x00040000 */ -#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ #define GPIO_SCR_IOCB3_Pos (19U) #define GPIO_SCR_IOCB3_Msk (0x1U << GPIO_SCR_IOCB3_Pos) /*!< 0x00080000 */ -#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ #define GPIO_SCR_IOCB4_Pos (20U) #define GPIO_SCR_IOCB4_Msk (0x1U << GPIO_SCR_IOCB4_Pos) /*!< 0x00100000 */ -#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ #define GPIO_SCR_IOCB5_Pos (21U) #define GPIO_SCR_IOCB5_Msk (0x1U << GPIO_SCR_IOCB5_Pos) /*!< 0x00200000 */ -#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ #define GPIO_SCR_IOCB6_Pos (22U) #define GPIO_SCR_IOCB6_Msk (0x1U << GPIO_SCR_IOCB6_Pos) /*!< 0x00400000 */ -#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ #define GPIO_SCR_IOCB7_Pos (23U) #define GPIO_SCR_IOCB7_Msk (0x1U << GPIO_SCR_IOCB7_Pos) /*!< 0x00800000 */ -#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ #define GPIO_SCR_IOCB8_Pos (24U) #define GPIO_SCR_IOCB8_Msk (0x1U << GPIO_SCR_IOCB8_Pos) /*!< 0x01000000 */ -#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ #define GPIO_SCR_IOCB9_Pos (25U) #define GPIO_SCR_IOCB9_Msk (0x1U << GPIO_SCR_IOCB9_Pos) /*!< 0x02000000 */ -#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ #define GPIO_SCR_IOCB10_Pos (26U) #define GPIO_SCR_IOCB10_Msk (0x1U << GPIO_SCR_IOCB10_Pos) /*!< 0x04000000 */ -#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ #define GPIO_SCR_IOCB11_Pos (27U) #define GPIO_SCR_IOCB11_Msk (0x1U << GPIO_SCR_IOCB11_Pos) /*!< 0x08000000 */ -#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ #define GPIO_SCR_IOCB12_Pos (28U) #define GPIO_SCR_IOCB12_Msk (0x1U << GPIO_SCR_IOCB12_Pos) /*!< 0x10000000 */ -#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ #define GPIO_SCR_IOCB13_Pos (29U) #define GPIO_SCR_IOCB13_Msk (0x1U << GPIO_SCR_IOCB13_Pos) /*!< 0x20000000 */ -#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ #define GPIO_SCR_IOCB14_Pos (30U) #define GPIO_SCR_IOCB14_Msk (0x1U << GPIO_SCR_IOCB14_Pos) /*!< 0x40000000 */ -#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ #define GPIO_SCR_IOCB15_Pos (31U) #define GPIO_SCR_IOCB15_Msk (0x1U << GPIO_SCR_IOCB15_Pos) /*!< 0x80000000 */ -#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit 15 */ +#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ /******************* Bit definition for GPIO_CLR register *******************/ #define GPIO_CLR_IOCB0_Pos (0U) #define GPIO_CLR_IOCB0_Msk (0x1U << GPIO_CLR_IOCB0_Pos) /*!< 0x00000001 */ -#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ #define GPIO_CLR_IOCB1_Pos (1U) #define GPIO_CLR_IOCB1_Msk (0x1U << GPIO_CLR_IOCB1_Pos) /*!< 0x00000002 */ -#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ #define GPIO_CLR_IOCB2_Pos (2U) #define GPIO_CLR_IOCB2_Msk (0x1U << GPIO_CLR_IOCB2_Pos) /*!< 0x00000004 */ -#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ #define GPIO_CLR_IOCB3_Pos (3U) #define GPIO_CLR_IOCB3_Msk (0x1U << GPIO_CLR_IOCB3_Pos) /*!< 0x00000008 */ -#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ #define GPIO_CLR_IOCB4_Pos (4U) #define GPIO_CLR_IOCB4_Msk (0x1U << GPIO_CLR_IOCB4_Pos) /*!< 0x00000010 */ -#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ #define GPIO_CLR_IOCB5_Pos (5U) #define GPIO_CLR_IOCB5_Msk (0x1U << GPIO_CLR_IOCB5_Pos) /*!< 0x00000020 */ -#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ #define GPIO_CLR_IOCB6_Pos (6U) #define GPIO_CLR_IOCB6_Msk (0x1U << GPIO_CLR_IOCB6_Pos) /*!< 0x00000040 */ -#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ #define GPIO_CLR_IOCB7_Pos (7U) #define GPIO_CLR_IOCB7_Msk (0x1U << GPIO_CLR_IOCB7_Pos) /*!< 0x00000080 */ -#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ #define GPIO_CLR_IOCB8_Pos (8U) #define GPIO_CLR_IOCB8_Msk (0x1U << GPIO_CLR_IOCB8_Pos) /*!< 0x00000100 */ -#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ #define GPIO_CLR_IOCB9_Pos (9U) #define GPIO_CLR_IOCB9_Msk (0x1U << GPIO_CLR_IOCB9_Pos) /*!< 0x00000200 */ -#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ #define GPIO_CLR_IOCB10_Pos (10U) #define GPIO_CLR_IOCB10_Msk (0x1U << GPIO_CLR_IOCB10_Pos) /*!< 0x00000400 */ -#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ #define GPIO_CLR_IOCB11_Pos (11U) #define GPIO_CLR_IOCB11_Msk (0x1U << GPIO_CLR_IOCB11_Pos) /*!< 0x00000800 */ -#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ #define GPIO_CLR_IOCB12_Pos (12U) #define GPIO_CLR_IOCB12_Msk (0x1U << GPIO_CLR_IOCB12_Pos) /*!< 0x00001000 */ -#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ #define GPIO_CLR_IOCB13_Pos (13U) #define GPIO_CLR_IOCB13_Msk (0x1U << GPIO_CLR_IOCB13_Pos) /*!< 0x00002000 */ -#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ #define GPIO_CLR_IOCB14_Pos (14U) #define GPIO_CLR_IOCB14_Msk (0x1U << GPIO_CLR_IOCB14_Pos) /*!< 0x00004000 */ -#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ #define GPIO_CLR_IOCB15_Pos (15U) #define GPIO_CLR_IOCB15_Msk (0x1U << GPIO_CLR_IOCB15_Pos) /*!< 0x00008000 */ -#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit 15 */ +#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ /******************* Bit definition for GPIO_WPR register *******************/ #define GPIO_WPR_WPEN0_Pos (0U) #define GPIO_WPR_WPEN0_Msk (0x1U << GPIO_WPR_WPEN0_Pos) /*!< 0x00000001 */ -#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable bit 0 */ +#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable, pin 0 */ #define GPIO_WPR_WPEN1_Pos (1U) #define GPIO_WPR_WPEN1_Msk (0x1U << GPIO_WPR_WPEN1_Pos) /*!< 0x00000002 */ -#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable bit 1 */ +#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable, pin 1 */ #define GPIO_WPR_WPEN2_Pos (2U) #define GPIO_WPR_WPEN2_Msk (0x1U << GPIO_WPR_WPEN2_Pos) /*!< 0x00000004 */ -#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable bit 2 */ +#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable, pin 2 */ #define GPIO_WPR_WPEN3_Pos (3U) #define GPIO_WPR_WPEN3_Msk (0x1U << GPIO_WPR_WPEN3_Pos) /*!< 0x00000008 */ -#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable bit 3 */ +#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable, pin 3 */ #define GPIO_WPR_WPEN4_Pos (4U) #define GPIO_WPR_WPEN4_Msk (0x1U << GPIO_WPR_WPEN4_Pos) /*!< 0x00000010 */ -#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable bit 4 */ +#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable, pin 4 */ #define GPIO_WPR_WPEN5_Pos (5U) #define GPIO_WPR_WPEN5_Msk (0x1U << GPIO_WPR_WPEN5_Pos) /*!< 0x00000020 */ -#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable bit 5 */ +#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable, pin 5 */ #define GPIO_WPR_WPEN6_Pos (6U) #define GPIO_WPR_WPEN6_Msk (0x1U << GPIO_WPR_WPEN6_Pos) /*!< 0x00000040 */ -#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable bit 6 */ +#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable, pin 6 */ #define GPIO_WPR_WPEN7_Pos (7U) #define GPIO_WPR_WPEN7_Msk (0x1U << GPIO_WPR_WPEN7_Pos) /*!< 0x00000080 */ -#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable bit 7 */ +#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable, pin 7 */ #define GPIO_WPR_WPEN8_Pos (8U) #define GPIO_WPR_WPEN8_Msk (0x1U << GPIO_WPR_WPEN8_Pos) /*!< 0x00000100 */ -#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable bit 8 */ +#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable, pin 8 */ #define GPIO_WPR_WPEN9_Pos (9U) #define GPIO_WPR_WPEN9_Msk (0x1U << GPIO_WPR_WPEN9_Pos) /*!< 0x00000200 */ -#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable bit 9 */ +#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable, pin 9 */ #define GPIO_WPR_WPEN10_Pos (10U) #define GPIO_WPR_WPEN10_Msk (0x1U << GPIO_WPR_WPEN10_Pos) /*!< 0x00000400 */ -#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable bit 10 */ +#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable, pin 10 */ #define GPIO_WPR_WPEN11_Pos (11U) #define GPIO_WPR_WPEN11_Msk (0x1U << GPIO_WPR_WPEN11_Pos) /*!< 0x00000800 */ -#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable bit 11 */ +#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable, pin 11 */ #define GPIO_WPR_WPEN12_Pos (12U) #define GPIO_WPR_WPEN12_Msk (0x1U << GPIO_WPR_WPEN12_Pos) /*!< 0x00001000 */ -#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable bit 12 */ +#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable, pin 12 */ #define GPIO_WPR_WPEN13_Pos (13U) #define GPIO_WPR_WPEN13_Msk (0x1U << GPIO_WPR_WPEN13_Pos) /*!< 0x00002000 */ -#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable bit 13 */ +#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable, pin 13 */ #define GPIO_WPR_WPEN14_Pos (14U) #define GPIO_WPR_WPEN14_Msk (0x1U << GPIO_WPR_WPEN14_Pos) /*!< 0x00004000 */ -#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable bit 14 */ +#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable, pin 14 */ #define GPIO_WPR_WPEN15_Pos (15U) #define GPIO_WPR_WPEN15_Msk (0x1U << GPIO_WPR_WPEN15_Pos) /*!< 0x00008000 */ -#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable bit 15 */ +#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable, pin 15 */ #define GPIO_WPR_WPSEQ_Pos (16U) #define GPIO_WPR_WPSEQ_Msk (0x1U << GPIO_WPR_WPSEQ_Pos) /*!< 0x00010000 */ #define GPIO_WPR_WPSEQ GPIO_WPR_WPSEQ_Msk /*!< Write protect sequence */ @@ -2518,7 +2541,6 @@ typedef struct #define IOMUX_EVTOUT_EVOEN IOMUX_EVTOUT_EVOEN_Msk /*!< Event output enable */ /***************** Bit definition for IOMUX_REMAP register ******************/ -/*!< SPI1_MUX configuration */ #define IOMUX_REMAP_SPI1_MUX_Pos (0U) #define IOMUX_REMAP_SPI1_MUX_Msk (0x1U << IOMUX_REMAP_SPI1_MUX_Pos) /*!< 0x00000001 */ #define IOMUX_REMAP_SPI1_MUX IOMUX_REMAP_SPI1_MUX_Msk /*!< SPI1 IO multiplexing */ @@ -4094,18 +4116,21 @@ typedef struct #define DMA_CCTRL_MINCM_Msk (0x1U << DMA_CCTRL_MINCM_Pos) /*!< 0x00000080 */ #define DMA_CCTRL_MINCM DMA_CCTRL_MINCM_Msk /*!< Memory address increment mode */ +/*!< PWIDTH configuration */ #define DMA_CCTRL_PWIDTH_Pos (8U) #define DMA_CCTRL_PWIDTH_Msk (0x3U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000300 */ #define DMA_CCTRL_PWIDTH DMA_CCTRL_PWIDTH_Msk /*!< PWIDTH[1:0] bits (Peripheral data bit width) */ #define DMA_CCTRL_PWIDTH_0 (0x1U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000100 */ #define DMA_CCTRL_PWIDTH_1 (0x2U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000200 */ +/*!< MWIDTH configuration */ #define DMA_CCTRL_MWIDTH_Pos (10U) #define DMA_CCTRL_MWIDTH_Msk (0x3U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000C00 */ #define DMA_CCTRL_MWIDTH DMA_CCTRL_MWIDTH_Msk /*!< MWIDTH[1:0] bits (Memory data bit width) */ #define DMA_CCTRL_MWIDTH_0 (0x1U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000400 */ #define DMA_CCTRL_MWIDTH_1 (0x2U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000800 */ +/*!< CHPL configuration */ #define DMA_CCTRL_CHPL_Pos (12U) #define DMA_CCTRL_CHPL_Msk (0x3U << DMA_CCTRL_CHPL_Pos) /*!< 0x00003000 */ #define DMA_CCTRL_CHPL DMA_CCTRL_CHPL_Msk /*!< CHPL[1:0] bits(Channel priority level) */ @@ -4292,34 +4317,34 @@ typedef struct #define I2C_OADDR1_ADDR1_1_7 0x000000FEU /*!< Interface Address */ #define I2C_OADDR1_ADDR1_8_9 0x00000300U /*!< Interface Address */ -#define I2C_OADDR1_ADDR1_0_Pos (0U) +#define I2C_OADDR1_ADDR1_0_Pos (0U) #define I2C_OADDR1_ADDR1_0_Msk (0x1U << I2C_OADDR1_ADDR1_0_Pos) /*!< 0x00000001 */ #define I2C_OADDR1_ADDR1_0 I2C_OADDR1_ADDR1_0_Msk /*!< Bit 0 */ -#define I2C_OADDR1_ADDR1_1_Pos (1U) +#define I2C_OADDR1_ADDR1_1_Pos (1U) #define I2C_OADDR1_ADDR1_1_Msk (0x1U << I2C_OADDR1_ADDR1_1_Pos) /*!< 0x00000002 */ #define I2C_OADDR1_ADDR1_1 I2C_OADDR1_ADDR1_1_Msk /*!< Bit 1 */ -#define I2C_OADDR1_ADDR1_2_Pos (2U) +#define I2C_OADDR1_ADDR1_2_Pos (2U) #define I2C_OADDR1_ADDR1_2_Msk (0x1U << I2C_OADDR1_ADDR1_2_Pos) /*!< 0x00000004 */ #define I2C_OADDR1_ADDR1_2 I2C_OADDR1_ADDR1_2_Msk /*!< Bit 2 */ -#define I2C_OADDR1_ADDR1_3_Pos (3U) +#define I2C_OADDR1_ADDR1_3_Pos (3U) #define I2C_OADDR1_ADDR1_3_Msk (0x1U << I2C_OADDR1_ADDR1_3_Pos) /*!< 0x00000008 */ #define I2C_OADDR1_ADDR1_3 I2C_OADDR1_ADDR1_3_Msk /*!< Bit 3 */ -#define I2C_OADDR1_ADDR1_4_Pos (4U) +#define I2C_OADDR1_ADDR1_4_Pos (4U) #define I2C_OADDR1_ADDR1_4_Msk (0x1U << I2C_OADDR1_ADDR1_4_Pos) /*!< 0x00000010 */ #define I2C_OADDR1_ADDR1_4 I2C_OADDR1_ADDR1_4_Msk /*!< Bit 4 */ -#define I2C_OADDR1_ADDR1_5_Pos (5U) +#define I2C_OADDR1_ADDR1_5_Pos (5U) #define I2C_OADDR1_ADDR1_5_Msk (0x1U << I2C_OADDR1_ADDR1_5_Pos) /*!< 0x00000020 */ #define I2C_OADDR1_ADDR1_5 I2C_OADDR1_ADDR1_5_Msk /*!< Bit 5 */ -#define I2C_OADDR1_ADDR1_6_Pos (6U) +#define I2C_OADDR1_ADDR1_6_Pos (6U) #define I2C_OADDR1_ADDR1_6_Msk (0x1U << I2C_OADDR1_ADDR1_6_Pos) /*!< 0x00000040 */ #define I2C_OADDR1_ADDR1_6 I2C_OADDR1_ADDR1_6_Msk /*!< Bit 6 */ -#define I2C_OADDR1_ADDR1_7_Pos (7U) +#define I2C_OADDR1_ADDR1_7_Pos (7U) #define I2C_OADDR1_ADDR1_7_Msk (0x1U << I2C_OADDR1_ADDR1_7_Pos) /*!< 0x00000080 */ #define I2C_OADDR1_ADDR1_7 I2C_OADDR1_ADDR1_7_Msk /*!< Bit 7 */ -#define I2C_OADDR1_ADDR1_8_Pos (8U) +#define I2C_OADDR1_ADDR1_8_Pos (8U) #define I2C_OADDR1_ADDR1_8_Msk (0x1U << I2C_OADDR1_ADDR1_8_Pos) /*!< 0x00000100 */ #define I2C_OADDR1_ADDR1_8 I2C_OADDR1_ADDR1_8_Msk /*!< Bit 8 */ -#define I2C_OADDR1_ADDR1_9_Pos (9U) +#define I2C_OADDR1_ADDR1_9_Pos (9U) #define I2C_OADDR1_ADDR1_9_Msk (0x1U << I2C_OADDR1_ADDR1_9_Pos) /*!< 0x00000200 */ #define I2C_OADDR1_ADDR1_9 I2C_OADDR1_ADDR1_9_Msk /*!< Bit 9 */ @@ -4541,6 +4566,7 @@ typedef struct #define USART_CTRL2_CLKEN_Msk (0x1U << USART_CTRL2_CLKEN_Pos) /*!< 0x00000800 */ #define USART_CTRL2_CLKEN USART_CTRL2_CLKEN_Msk /*!< Clock enable */ +/*!< STOPBN configuration */ #define USART_CTRL2_STOPBN_Pos (12U) #define USART_CTRL2_STOPBN_Msk (0x3U << USART_CTRL2_STOPBN_Pos) /*!< 0x00003000 */ #define USART_CTRL2_STOPBN USART_CTRL2_STOPBN_Msk /*!< STOPBN[1:0] bits (STOP bit num) */ @@ -4587,6 +4613,7 @@ typedef struct #define USART_CTRL3_CTSCFIEN USART_CTRL3_CTSCFIEN_Msk /*!< CTSCF interrupt enable */ /****************** Bit definition for USART_GDIV register ******************/ +/*!< ISDIV configuration */ #define USART_GDIV_ISDIV_Pos (0U) #define USART_GDIV_ISDIV_Msk (0xFFU << USART_GDIV_ISDIV_Pos) /*!< 0x000000FF */ #define USART_GDIV_ISDIV USART_GDIV_ISDIV_Msk /*!< ISDIV[7:0] bits (IrDA/Smart Card division) */ @@ -4733,6 +4760,7 @@ typedef struct #define SPI_I2SCTRL_I2SCBN_Msk (0x1U << SPI_I2SCTRL_I2SCBN_Pos) /*!< 0x00000001 */ #define SPI_I2SCTRL_I2SCBN SPI_I2SCTRL_I2SCBN_Msk /*!< Channel length (I2S channel bit num) */ +/*!< I2SDBN configuration */ #define SPI_I2SCTRL_I2SDBN_Pos (1U) #define SPI_I2SCTRL_I2SDBN_Msk (0x3U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000006 */ #define SPI_I2SCTRL_I2SDBN SPI_I2SCTRL_I2SDBN_Msk /*!< I2SDBN[1:0] bits (I2S data bit num) */ @@ -4743,6 +4771,7 @@ typedef struct #define SPI_I2SCTRL_I2SCLKPOL_Msk (0x1U << SPI_I2SCTRL_I2SCLKPOL_Pos) /*!< 0x00000008 */ #define SPI_I2SCTRL_I2SCLKPOL SPI_I2SCTRL_I2SCLKPOL_Msk /*!< I2S clock polarity */ +/*!< STDSEL configuration */ #define SPI_I2SCTRL_STDSEL_Pos (4U) #define SPI_I2SCTRL_STDSEL_Msk (0x3U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000030 */ #define SPI_I2SCTRL_STDSEL SPI_I2SCTRL_STDSEL_Msk /*!< STDSEL[1:0] bits (I2S standard select) */ @@ -4753,6 +4782,7 @@ typedef struct #define SPI_I2SCTRL_PCMFSSEL_Msk (0x1U << SPI_I2SCTRL_PCMFSSEL_Pos) /*!< 0x00000080 */ #define SPI_I2SCTRL_PCMFSSEL SPI_I2SCTRL_PCMFSSEL_Msk /*!< PCM frame synchronization */ +/*!< OPERSEL configuration */ #define SPI_I2SCTRL_OPERSEL_Pos (8U) #define SPI_I2SCTRL_OPERSEL_Msk (0x3U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000300 */ #define SPI_I2SCTRL_OPERSEL SPI_I2SCTRL_OPERSEL_Msk /*!< OPERSEL[1:0] bits (I2S operation mode select) */ @@ -4783,6 +4813,7 @@ typedef struct /******************************************************************************/ /****************** Bit definition for WWDT_CTRL register *******************/ +/*!< CNT configuration */ #define WWDT_CTRL_CNT_Pos (0U) #define WWDT_CTRL_CNT_Msk (0x7FU << WWDT_CTRL_CNT_Pos) /*!< 0x0000007F */ #define WWDT_CTRL_CNT WWDT_CTRL_CNT_Msk /*!< CNT[6:0] bits (Down counter) */ @@ -4808,6 +4839,7 @@ typedef struct #define WWDT_CTRL_WWDTEN WWDT_CTRL_WWDTEN_Msk /*!< Window watchdog enable */ /******************* Bit definition for WWDT_CFG register *******************/ +/*!< WIN configuration */ #define WWDT_CFG_WIN_Pos (0U) #define WWDT_CFG_WIN_Msk (0x7FU << WWDT_CFG_WIN_Pos) /*!< 0x0000007F */ #define WWDT_CFG_WIN WWDT_CFG_WIN_Msk /*!< WIN[6:0] bits (Window value) */ @@ -4828,6 +4860,7 @@ typedef struct #define WWDT_CFG_WIN5 WWDT_CFG_WIN_5 #define WWDT_CFG_WIN6 WWDT_CFG_WIN_6 +/*!< DIV configuration */ #define WWDT_CFG_DIV_Pos (7U) #define WWDT_CFG_DIV_Msk (0x3U << WWDT_CFG_DIV_Pos) /*!< 0x00000180 */ #define WWDT_CFG_DIV WWDT_CFG_DIV_Msk /*!< DIV[1:0] bits (Clock division value) */ @@ -4859,6 +4892,7 @@ typedef struct #define WDT_CMD_CMD WDT_CMD_CMD_Msk /*!< Command register */ /******************* Bit definition for WDT_DIV register ********************/ +/*!< DIV configuration */ #define WDT_DIV_DIV_Pos (0U) #define WDT_DIV_DIV_Msk (0x7U << WDT_DIV_DIV_Pos) /*!< 0x00000007 */ #define WDT_DIV_DIV WDT_DIV_DIV_Msk /*!< DIV[2:0] (Clock division value) */ @@ -4886,6 +4920,7 @@ typedef struct /******************************************************************************/ /****************** Bit definition for ERTC_TIME register *******************/ +/*!< SU configuration */ #define ERTC_TIME_SU_Pos (0U) #define ERTC_TIME_SU_Msk (0xFU << ERTC_TIME_SU_Pos) /*!< 0x0000000F */ #define ERTC_TIME_SU ERTC_TIME_SU_Msk /*!< SU[3:0] (Second units) */ @@ -4894,6 +4929,7 @@ typedef struct #define ERTC_TIME_SU_2 (0x4U << ERTC_TIME_SU_Pos) /*!< 0x00000004 */ #define ERTC_TIME_SU_3 (0x8U << ERTC_TIME_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_TIME_ST_Pos (4U) #define ERTC_TIME_ST_Msk (0x7U << ERTC_TIME_ST_Pos) /*!< 0x00000070 */ #define ERTC_TIME_ST ERTC_TIME_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -4901,6 +4937,7 @@ typedef struct #define ERTC_TIME_ST_1 (0x2U << ERTC_TIME_ST_Pos) /*!< 0x00000020 */ #define ERTC_TIME_ST_2 (0x4U << ERTC_TIME_ST_Pos) /*!< 0x00000040 */ +/*!< MU configuration */ #define ERTC_TIME_MU_Pos (8U) #define ERTC_TIME_MU_Msk (0xFU << ERTC_TIME_MU_Pos) /*!< 0x00000F00 */ #define ERTC_TIME_MU ERTC_TIME_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -4909,6 +4946,7 @@ typedef struct #define ERTC_TIME_MU_2 (0x4U << ERTC_TIME_MU_Pos) /*!< 0x00000400 */ #define ERTC_TIME_MU_3 (0x8U << ERTC_TIME_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_TIME_MT_Pos (12U) #define ERTC_TIME_MT_Msk (0x7U << ERTC_TIME_MT_Pos) /*!< 0x00007000 */ #define ERTC_TIME_MT ERTC_TIME_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -4916,6 +4954,7 @@ typedef struct #define ERTC_TIME_MT_1 (0x2U << ERTC_TIME_MT_Pos) /*!< 0x00002000 */ #define ERTC_TIME_MT_2 (0x4U << ERTC_TIME_MT_Pos) /*!< 0x00004000 */ +/*!< HU configuration */ #define ERTC_TIME_HU_Pos (16U) #define ERTC_TIME_HU_Msk (0xFU << ERTC_TIME_HU_Pos) /*!< 0x000F0000 */ #define ERTC_TIME_HU ERTC_TIME_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -4924,6 +4963,7 @@ typedef struct #define ERTC_TIME_HU_2 (0x4U << ERTC_TIME_HU_Pos) /*!< 0x00040000 */ #define ERTC_TIME_HU_3 (0x8U << ERTC_TIME_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_TIME_HT_Pos (20U) #define ERTC_TIME_HT_Msk (0x3U << ERTC_TIME_HT_Pos) /*!< 0x00300000 */ #define ERTC_TIME_HT ERTC_TIME_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -4935,6 +4975,7 @@ typedef struct #define ERTC_TIME_AMPM ERTC_TIME_AMPM_Msk /*!< AM/PM */ /****************** Bit definition for ERTC_DATE register *******************/ +/*!< DU configuration */ #define ERTC_DATE_DU_Pos (0U) #define ERTC_DATE_DU_Msk (0xFU << ERTC_DATE_DU_Pos) /*!< 0x0000000F */ #define ERTC_DATE_DU ERTC_DATE_DU_Msk /*!< DU[3:0] (Date units) */ @@ -4943,12 +4984,14 @@ typedef struct #define ERTC_DATE_DU_2 (0x4U << ERTC_DATE_DU_Pos) /*!< 0x00000004 */ #define ERTC_DATE_DU_3 (0x8U << ERTC_DATE_DU_Pos) /*!< 0x00000008 */ +/*!< DT configuration */ #define ERTC_DATE_DT_Pos (4U) #define ERTC_DATE_DT_Msk (0x3U << ERTC_DATE_DT_Pos) /*!< 0x00300000 */ #define ERTC_DATE_DT ERTC_DATE_DT_Msk /*!< DT[1:0] (Date tens) */ #define ERTC_DATE_DT_0 (0x1U << ERTC_DATE_DT_Pos) /*!< 0x00000010 */ #define ERTC_DATE_DT_1 (0x2U << ERTC_DATE_DT_Pos) /*!< 0x00000020 */ +/*!< MU configuration */ #define ERTC_DATE_MU_Pos (8U) #define ERTC_DATE_MU_Msk (0xFU << ERTC_DATE_MU_Pos) /*!< 0x00000F00 */ #define ERTC_DATE_MU ERTC_DATE_MU_Msk /*!< MU[3:0] (Month units) */ @@ -4961,6 +5004,7 @@ typedef struct #define ERTC_DATE_MT_Msk (0x1U << ERTC_DATE_MT_Pos) /*!< 0x00001000 */ #define ERTC_DATE_MT ERTC_DATE_MT_Msk /*!< Month tens */ +/*!< WK configuration */ #define ERTC_DATE_WK_Pos (13U) #define ERTC_DATE_WK_Msk (0x7U << ERTC_DATE_WK_Pos) /*!< 0x0000E000 */ #define ERTC_DATE_WK ERTC_DATE_WK_Msk /*!< WK[2:0] (Week day) */ @@ -4968,6 +5012,7 @@ typedef struct #define ERTC_DATE_WK_1 (0x2U << ERTC_DATE_WK_Pos) /*!< 0x00004000 */ #define ERTC_DATE_WK_2 (0x4U << ERTC_DATE_WK_Pos) /*!< 0x00008000 */ +/*!< YU configuration */ #define ERTC_DATE_YU_Pos (16U) #define ERTC_DATE_YU_Msk (0xFU << ERTC_DATE_YU_Pos) /*!< 0x000F0000 */ #define ERTC_DATE_YU ERTC_DATE_YU_Msk /*!< YU[3:0] (Year units) */ @@ -4976,6 +5021,7 @@ typedef struct #define ERTC_DATE_YU_2 (0x4U << ERTC_DATE_YU_Pos) /*!< 0x00040000 */ #define ERTC_DATE_YU_3 (0x8U << ERTC_DATE_YU_Pos) /*!< 0x00080000 */ +/*!< YT configuration */ #define ERTC_DATE_YT_Pos (20U) #define ERTC_DATE_YT_Msk (0xFU << ERTC_DATE_YT_Pos) /*!< 0x00F00000 */ #define ERTC_DATE_YT ERTC_DATE_YT_Msk /*!< YT[3:0] (Year tens) */ @@ -4985,6 +5031,7 @@ typedef struct #define ERTC_DATE_YT_3 (0x8U << ERTC_DATE_YT_Pos) /*!< 0x00800000 */ /****************** Bit definition for ERTC_CTRL register *******************/ +/*!< WATCLK configuration */ #define ERTC_CTRL_WATCLK_Pos (0U) #define ERTC_CTRL_WATCLK_Msk (0x7U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000007 */ #define ERTC_CTRL_WATCLK ERTC_CTRL_WATCLK_Msk /*!< WATCLK[2:0] (Wakeup timer clock selection) */ @@ -5047,9 +5094,10 @@ typedef struct #define ERTC_CTRL_OUTP_Msk (0x1U << ERTC_CTRL_OUTP_Pos) /*!< 0x00100000 */ #define ERTC_CTRL_OUTP ERTC_CTRL_OUTP_Msk /*!< Output polarity */ +/*!< OUTSEL configuration */ #define ERTC_CTRL_OUTSEL_Pos (21U) #define ERTC_CTRL_OUTSEL_Msk (0x3U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00600000 */ -#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< WATCLK[1:0] (Output source selection) */ +#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< OUTSEL[1:0] (Output source selection) */ #define ERTC_CTRL_OUTSEL_0 (0x1U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00200000 */ #define ERTC_CTRL_OUTSEL_1 (0x2U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00400000 */ @@ -5118,6 +5166,7 @@ typedef struct #define ERTC_WAT_VAL ERTC_WAT_VAL_Msk /*!< Wakeup timer reload value */ /****************** Bit definition for ERTC_CCAL register *******************/ +/*!< CALVAL configuration */ #define ERTC_CCAL_CALVAL_Pos (0U) #define ERTC_CCAL_CALVAL_Msk (0x1FU << ERTC_CCAL_CALVAL_Pos) /*!< 0x0000001F */ #define ERTC_CCAL_CALVAL ERTC_CCAL_CALVAL_Msk /*!< CALVAL[4:0] (Calibration value) */ @@ -5132,6 +5181,7 @@ typedef struct #define ERTC_CCAL_CALDIR ERTC_CCAL_CALDIR_Msk /*!< Calibration direction */ /******************* Bit definition for ERTC_ALA register *******************/ +/*!< SU configuration */ #define ERTC_ALA_SU_Pos (0U) #define ERTC_ALA_SU_Msk (0xFU << ERTC_ALA_SU_Pos) /*!< 0x0000000F */ #define ERTC_ALA_SU ERTC_ALA_SU_Msk /*!< SU[3:0] (Second units) */ @@ -5140,6 +5190,7 @@ typedef struct #define ERTC_ALA_SU_2 (0x4U << ERTC_ALA_SU_Pos) /*!< 0x00000004 */ #define ERTC_ALA_SU_3 (0x8U << ERTC_ALA_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_ALA_ST_Pos (4U) #define ERTC_ALA_ST_Msk (0x7U << ERTC_ALA_ST_Pos) /*!< 0x00000070 */ #define ERTC_ALA_ST ERTC_ALA_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -5151,6 +5202,7 @@ typedef struct #define ERTC_ALA_MASK1_Msk (0x1U << ERTC_ALA_MASK1_Pos) /*!< 0x00000080 */ #define ERTC_ALA_MASK1 ERTC_ALA_MASK1_Msk /*!< Second mask */ +/*!< MU configuration */ #define ERTC_ALA_MU_Pos (8U) #define ERTC_ALA_MU_Msk (0xFU << ERTC_ALA_MU_Pos) /*!< 0x00000F00 */ #define ERTC_ALA_MU ERTC_ALA_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -5159,6 +5211,7 @@ typedef struct #define ERTC_ALA_MU_2 (0x4U << ERTC_ALA_MU_Pos) /*!< 0x00000400 */ #define ERTC_ALA_MU_3 (0x8U << ERTC_ALA_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_ALA_MT_Pos (12U) #define ERTC_ALA_MT_Msk (0x7U << ERTC_ALA_MT_Pos) /*!< 0x00007000 */ #define ERTC_ALA_MT ERTC_ALA_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -5170,6 +5223,7 @@ typedef struct #define ERTC_ALA_MASK2_Msk (0x1U << ERTC_ALA_MASK2_Pos) /*!< 0x00008000 */ #define ERTC_ALA_MASK2 ERTC_ALA_MASK2_Msk /*!< Minute mask */ +/*!< HU configuration */ #define ERTC_ALA_HU_Pos (16U) #define ERTC_ALA_HU_Msk (0xFU << ERTC_ALA_HU_Pos) /*!< 0x000F0000 */ #define ERTC_ALA_HU ERTC_ALA_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -5178,6 +5232,7 @@ typedef struct #define ERTC_ALA_HU_2 (0x4U << ERTC_ALA_HU_Pos) /*!< 0x00040000 */ #define ERTC_ALA_HU_3 (0x8U << ERTC_ALA_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_ALA_HT_Pos (20U) #define ERTC_ALA_HT_Msk (0x3U << ERTC_ALA_HT_Pos) /*!< 0x00300000 */ #define ERTC_ALA_HT ERTC_ALA_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -5191,6 +5246,7 @@ typedef struct #define ERTC_ALA_MASK3_Msk (0x1U << ERTC_ALA_MASK3_Pos) /*!< 0x00800000 */ #define ERTC_ALA_MASK3 ERTC_ALA_MASK3_Msk /*!< Hour mask */ +/*!< DU configuration */ #define ERTC_ALA_DU_Pos (24U) #define ERTC_ALA_DU_Msk (0xFU << ERTC_ALA_DU_Pos) /*!< 0x0F000000 */ #define ERTC_ALA_DU ERTC_ALA_DU_Msk /*!< DU[3:0] (Date/week day units) */ @@ -5199,6 +5255,7 @@ typedef struct #define ERTC_ALA_DU_2 (0x4U << ERTC_ALA_DU_Pos) /*!< 0x04000000 */ #define ERTC_ALA_DU_3 (0x8U << ERTC_ALA_DU_Pos) /*!< 0x08000000 */ +/*!< DT configuration */ #define ERTC_ALA_DT_Pos (28U) #define ERTC_ALA_DT_Msk (0x3U << ERTC_ALA_DT_Pos) /*!< 0x30000000 */ #define ERTC_ALA_DT ERTC_ALA_DT_Msk /*!< DT[1:0] (Date/week day tens) */ @@ -5213,6 +5270,7 @@ typedef struct #define ERTC_ALA_MASK4 ERTC_ALA_MASK4_Msk /*!< Date/week day mask */ /******************* Bit definition for ERTC_ALB register *******************/ +/*!< SU configuration */ #define ERTC_ALB_SU_Pos (0U) #define ERTC_ALB_SU_Msk (0xFU << ERTC_ALB_SU_Pos) /*!< 0x0000000F */ #define ERTC_ALB_SU ERTC_ALB_SU_Msk /*!< SU[3:0] (Second units) */ @@ -5221,6 +5279,7 @@ typedef struct #define ERTC_ALB_SU_2 (0x4U << ERTC_ALB_SU_Pos) /*!< 0x00000004 */ #define ERTC_ALB_SU_3 (0x8U << ERTC_ALB_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_ALB_ST_Pos (4U) #define ERTC_ALB_ST_Msk (0x7U << ERTC_ALB_ST_Pos) /*!< 0x00000070 */ #define ERTC_ALB_ST ERTC_ALB_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -5232,6 +5291,7 @@ typedef struct #define ERTC_ALB_MASK1_Msk (0x1U << ERTC_ALB_MASK1_Pos) /*!< 0x00000080 */ #define ERTC_ALB_MASK1 ERTC_ALB_MASK1_Msk /*!< Second mask */ +/*!< MU configuration */ #define ERTC_ALB_MU_Pos (8U) #define ERTC_ALB_MU_Msk (0xFU << ERTC_ALB_MU_Pos) /*!< 0x00000F00 */ #define ERTC_ALB_MU ERTC_ALB_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -5240,6 +5300,7 @@ typedef struct #define ERTC_ALB_MU_2 (0x4U << ERTC_ALB_MU_Pos) /*!< 0x00000400 */ #define ERTC_ALB_MU_3 (0x8U << ERTC_ALB_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_ALB_MT_Pos (12U) #define ERTC_ALB_MT_Msk (0x7U << ERTC_ALB_MT_Pos) /*!< 0x00007000 */ #define ERTC_ALB_MT ERTC_ALB_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -5251,6 +5312,7 @@ typedef struct #define ERTC_ALB_MASK2_Msk (0x1U << ERTC_ALB_MASK2_Pos) /*!< 0x00008000 */ #define ERTC_ALB_MASK2 ERTC_ALB_MASK2_Msk /*!< Minute mask */ +/*!< HU configuration */ #define ERTC_ALB_HU_Pos (16U) #define ERTC_ALB_HU_Msk (0xFU << ERTC_ALB_HU_Pos) /*!< 0x000F0000 */ #define ERTC_ALB_HU ERTC_ALB_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -5259,6 +5321,7 @@ typedef struct #define ERTC_ALB_HU_2 (0x4U << ERTC_ALB_HU_Pos) /*!< 0x00040000 */ #define ERTC_ALB_HU_3 (0x8U << ERTC_ALB_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_ALB_HT_Pos (20U) #define ERTC_ALB_HT_Msk (0x3U << ERTC_ALB_HT_Pos) /*!< 0x00300000 */ #define ERTC_ALB_HT ERTC_ALB_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -5272,6 +5335,7 @@ typedef struct #define ERTC_ALB_MASK3_Msk (0x1U << ERTC_ALB_MASK3_Pos) /*!< 0x00800000 */ #define ERTC_ALB_MASK3 ERTC_ALB_MASK3_Msk /*!< Hour mask */ +/*!< DU configuration */ #define ERTC_ALB_DU_Pos (24U) #define ERTC_ALB_DU_Msk (0xFU << ERTC_ALB_DU_Pos) /*!< 0x0F000000 */ #define ERTC_ALB_DU ERTC_ALB_DU_Msk /*!< DU[3:0] (Date/week day units) */ @@ -5280,6 +5344,7 @@ typedef struct #define ERTC_ALB_DU_2 (0x4U << ERTC_ALB_DU_Pos) /*!< 0x04000000 */ #define ERTC_ALB_DU_3 (0x8U << ERTC_ALB_DU_Pos) /*!< 0x08000000 */ +/*!< DT configuration */ #define ERTC_ALB_DT_Pos (28U) #define ERTC_ALB_DT_Msk (0x3U << ERTC_ALB_DT_Pos) /*!< 0x30000000 */ #define ERTC_ALB_DT ERTC_ALB_DT_Msk /*!< DT[1:0] (Date/week day tens) */ @@ -5312,6 +5377,7 @@ typedef struct #define ERTC_TADJ_ADD1S ERTC_TADJ_ADD1S_Msk /*!< Add 1 second */ /****************** Bit definition for ERTC_TSTM register *******************/ +/*!< SU configuration */ #define ERTC_TSTM_SU_Pos (0U) #define ERTC_TSTM_SU_Msk (0xFU << ERTC_TSTM_SU_Pos) /*!< 0x0000000F */ #define ERTC_TSTM_SU ERTC_TSTM_SU_Msk /*!< SU[3:0] (Second units) */ @@ -5320,6 +5386,7 @@ typedef struct #define ERTC_TSTM_SU_2 (0x4U << ERTC_TSTM_SU_Pos) /*!< 0x00000004 */ #define ERTC_TSTM_SU_3 (0x8U << ERTC_TSTM_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_TSTM_ST_Pos (4U) #define ERTC_TSTM_ST_Msk (0x7U << ERTC_TSTM_ST_Pos) /*!< 0x00000070 */ #define ERTC_TSTM_ST ERTC_TSTM_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -5327,6 +5394,7 @@ typedef struct #define ERTC_TSTM_ST_1 (0x2U << ERTC_TSTM_ST_Pos) /*!< 0x00000020 */ #define ERTC_TSTM_ST_2 (0x4U << ERTC_TSTM_ST_Pos) /*!< 0x00000040 */ +/*!< MU configuration */ #define ERTC_TSTM_MU_Pos (8U) #define ERTC_TSTM_MU_Msk (0xFU << ERTC_TSTM_MU_Pos) /*!< 0x00000F00 */ #define ERTC_TSTM_MU ERTC_TSTM_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -5335,6 +5403,7 @@ typedef struct #define ERTC_TSTM_MU_2 (0x4U << ERTC_TSTM_MU_Pos) /*!< 0x00000400 */ #define ERTC_TSTM_MU_3 (0x8U << ERTC_TSTM_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_TSTM_MT_Pos (12U) #define ERTC_TSTM_MT_Msk (0x7U << ERTC_TSTM_MT_Pos) /*!< 0x00007000 */ #define ERTC_TSTM_MT ERTC_TSTM_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -5342,6 +5411,7 @@ typedef struct #define ERTC_TSTM_MT_1 (0x2U << ERTC_TSTM_MT_Pos) /*!< 0x00002000 */ #define ERTC_TSTM_MT_2 (0x4U << ERTC_TSTM_MT_Pos) /*!< 0x00004000 */ +/*!< HU configuration */ #define ERTC_TSTM_HU_Pos (16U) #define ERTC_TSTM_HU_Msk (0xFU << ERTC_TSTM_HU_Pos) /*!< 0x000F0000 */ #define ERTC_TSTM_HU ERTC_TSTM_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -5350,6 +5420,7 @@ typedef struct #define ERTC_TSTM_HU_2 (0x4U << ERTC_TSTM_HU_Pos) /*!< 0x00040000 */ #define ERTC_TSTM_HU_3 (0x8U << ERTC_TSTM_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_TSTM_HT_Pos (20U) #define ERTC_TSTM_HT_Msk (0x3U << ERTC_TSTM_HT_Pos) /*!< 0x00300000 */ #define ERTC_TSTM_HT ERTC_TSTM_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -5361,6 +5432,7 @@ typedef struct #define ERTC_TSTM_AMPM ERTC_TSTM_AMPM_Msk /*!< AM/PM */ /****************** Bit definition for ERTC_TSDT register *******************/ +/*!< DU configuration */ #define ERTC_TSDT_DU_Pos (0U) #define ERTC_TSDT_DU_Msk (0xFU << ERTC_TSDT_DU_Pos) /*!< 0x0000000F */ #define ERTC_TSDT_DU ERTC_TSDT_DU_Msk /*!< DU[3:0] (Date units) */ @@ -5369,12 +5441,14 @@ typedef struct #define ERTC_TSDT_DU_2 (0x4U << ERTC_TSDT_DU_Pos) /*!< 0x00000004 */ #define ERTC_TSDT_DU_3 (0x8U << ERTC_TSDT_DU_Pos) /*!< 0x00000008 */ +/*!< DT configuration */ #define ERTC_TSDT_DT_Pos (4U) #define ERTC_TSDT_DT_Msk (0x3U << ERTC_TSDT_DT_Pos) /*!< 0x00000030 */ #define ERTC_TSDT_DT ERTC_TSDT_DT_Msk /*!< DT[1:0] (Date tens) */ #define ERTC_TSDT_DT_0 (0x1U << ERTC_TSDT_DT_Pos) /*!< 0x00000010 */ #define ERTC_TSDT_DT_1 (0x2U << ERTC_TSDT_DT_Pos) /*!< 0x00000020 */ +/*!< MU configuration */ #define ERTC_TSDT_MU_Pos (8U) #define ERTC_TSDT_MU_Msk (0xFU << ERTC_TSDT_MU_Pos) /*!< 0x00000F00 */ #define ERTC_TSDT_MU ERTC_TSDT_MU_Msk /*!< MU[3:0] (Month units) */ @@ -5387,6 +5461,7 @@ typedef struct #define ERTC_TSDT_MT_Msk (0x1U << ERTC_TSDT_MT_Pos) /*!< 0x00001000 */ #define ERTC_TSDT_MT ERTC_TSDT_MT_Msk /*!< Month tens */ +/*!< WK configuration */ #define ERTC_TSDT_WK_Pos (13U) #define ERTC_TSDT_WK_Msk (0x7U << ERTC_TSDT_WK_Pos) /*!< 0x0000E000 */ #define ERTC_TSDT_WK ERTC_TSDT_WK_Msk /*!< WK[2:0] (Week day) */ @@ -5427,6 +5502,7 @@ typedef struct #define ERTC_TAMP_TPTSEN_Msk (0x1U << ERTC_TAMP_TPTSEN_Pos) /*!< 0x00000080 */ #define ERTC_TAMP_TPTSEN ERTC_TAMP_TPTSEN_Msk /*!< Tamper detection timestamp enable */ +/*!< TPFREQ configuration */ #define ERTC_TAMP_TPFREQ_Pos (8U) #define ERTC_TAMP_TPFREQ_Msk (0x7U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000700 */ #define ERTC_TAMP_TPFREQ ERTC_TAMP_TPFREQ_Msk /*!< TPFREQ[2:0] (Tamper detection frequency) */ @@ -5434,12 +5510,14 @@ typedef struct #define ERTC_TAMP_TPFREQ_1 (0x2U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000200 */ #define ERTC_TAMP_TPFREQ_2 (0x4U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000400 */ +/*!< TPFLT configuration */ #define ERTC_TAMP_TPFLT_Pos (11U) #define ERTC_TAMP_TPFLT_Msk (0x3U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001800 */ #define ERTC_TAMP_TPFLT ERTC_TAMP_TPFLT_Msk /*!< TPFLT[1:0] (Tamper detection filter time) */ #define ERTC_TAMP_TPFLT_0 (0x1U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00000800 */ #define ERTC_TAMP_TPFLT_1 (0x2U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001000 */ +/*!< TPPR configuration */ #define ERTC_TAMP_TPPR_Pos (13U) #define ERTC_TAMP_TPPR_Msk (0x3U << ERTC_TAMP_TPPR_Pos) /*!< 0x00006000 */ #define ERTC_TAMP_TPPR ERTC_TAMP_TPPR_Msk /*!< TPPR[1:0] (Tamper detection pre-charge time) */ @@ -5458,9 +5536,10 @@ typedef struct #define ERTC_ALASBS_SBS_Msk (0x7FFFU << ERTC_ALASBS_SBS_Pos) /*!< 0x00007FFF */ #define ERTC_ALASBS_SBS ERTC_ALASBS_SBS_Msk /*!< Sub-second value */ +/*!< SBSMSK configuration */ #define ERTC_ALASBS_SBSMSK_Pos (24U) #define ERTC_ALASBS_SBSMSK_Msk (0xFU << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x0F000000 */ -#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ #define ERTC_ALASBS_SBSMSK_0 (0x1U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x01000000 */ #define ERTC_ALASBS_SBSMSK_1 (0x2U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x02000000 */ #define ERTC_ALASBS_SBSMSK_2 (0x4U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x04000000 */ @@ -5471,9 +5550,10 @@ typedef struct #define ERTC_ALBSBS_SBS_Msk (0x7FFFU << ERTC_ALBSBS_SBS_Pos) /*!< 0x00007FFF */ #define ERTC_ALBSBS_SBS ERTC_ALBSBS_SBS_Msk /*!< Sub-second value */ +/*!< SBSMSK configuration */ #define ERTC_ALBSBS_SBSMSK_Pos (24U) #define ERTC_ALBSBS_SBSMSK_Msk (0xFU << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x0F000000 */ -#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ #define ERTC_ALBSBS_SBSMSK_0 (0x1U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x01000000 */ #define ERTC_ALBSBS_SBSMSK_1 (0x2U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x02000000 */ #define ERTC_ALBSBS_SBSMSK_2 (0x4U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x04000000 */ @@ -5610,6 +5690,7 @@ typedef struct #define ADC_STS_PCCE (ADC_STS_PCCC) /****************** Bit definition for ADC_CTRL1 register *******************/ +/*!< VMCSEL configuration */ #define ADC_CTRL1_VMCSEL_Pos (0U) #define ADC_CTRL1_VMCSEL_Msk (0x1FU << ADC_CTRL1_VMCSEL_Pos) /*!< 0x0000001F */ #define ADC_CTRL1_VMCSEL ADC_CTRL1_VMCSEL_Msk /*!< VMCSEL[4:0] bits (Voltage monitoring channel select) */ @@ -5644,6 +5725,7 @@ typedef struct #define ADC_CTRL1_PCPEN_Msk (0x1U << ADC_CTRL1_PCPEN_Pos) /*!< 0x00001000 */ #define ADC_CTRL1_PCPEN ADC_CTRL1_PCPEN_Msk /*!< Partitioned mode enable on preempted channels */ +/*!< OCPCNT configuration */ #define ADC_CTRL1_OCPCNT_Pos (13U) #define ADC_CTRL1_OCPCNT_Msk (0x7U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x0000E000 */ #define ADC_CTRL1_OCPCNT ADC_CTRL1_OCPCNT_Msk /*!< OCPCNT[2:0] bits (Partitioned mode conversion count of ordinary channels) */ @@ -5668,7 +5750,7 @@ typedef struct #define ADC_CTRL2_ADCEN ADC_CTRL2_ADCEN_Msk /*!< A/D converter enable */ #define ADC_CTRL2_RPEN_Pos (1U) #define ADC_CTRL2_RPEN_Msk (0x1U << ADC_CTRL2_RPEN_Pos) /*!< 0x00000002 */ -#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repition mode enable */ +#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repetition mode enable */ #define ADC_CTRL2_ADCAL_Pos (2U) #define ADC_CTRL2_ADCAL_Msk (0x1U << ADC_CTRL2_ADCAL_Pos) /*!< 0x00000004 */ #define ADC_CTRL2_ADCAL ADC_CTRL2_ADCAL_Msk /*!< A/D calibration */ @@ -5716,6 +5798,7 @@ typedef struct #define ADC_CTRL2_ITSRVEN ADC_CTRL2_ITSRVEN_Msk /*!< Internal temperature sensor and VINTRV enable */ /******************* Bit definition for ADC_SPT1 register *******************/ +/*!< CSPT10 configuration */ #define ADC_SPT1_CSPT10_Pos (0U) #define ADC_SPT1_CSPT10_Msk (0x7U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000007 */ #define ADC_SPT1_CSPT10 ADC_SPT1_CSPT10_Msk /*!< CSPT10[2:0] bits (Sample time selection of channel ADC_IN10) */ @@ -5723,6 +5806,7 @@ typedef struct #define ADC_SPT1_CSPT10_1 (0x2U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000002 */ #define ADC_SPT1_CSPT10_2 (0x4U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000004 */ +/*!< CSPT11 configuration */ #define ADC_SPT1_CSPT11_Pos (3U) #define ADC_SPT1_CSPT11_Msk (0x7U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000038 */ #define ADC_SPT1_CSPT11 ADC_SPT1_CSPT11_Msk /*!< CSPT11[2:0] bits (Sample time selection of channel ADC_IN11) */ @@ -5730,6 +5814,7 @@ typedef struct #define ADC_SPT1_CSPT11_1 (0x2U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000010 */ #define ADC_SPT1_CSPT11_2 (0x4U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000020 */ +/*!< CSPT12 configuration */ #define ADC_SPT1_CSPT12_Pos (6U) #define ADC_SPT1_CSPT12_Msk (0x7U << ADC_SPT1_CSPT12_Pos) /*!< 0x000001C0 */ #define ADC_SPT1_CSPT12 ADC_SPT1_CSPT12_Msk /*!< CSPT12[2:0] bits (Sample time selection of channel ADC_IN12) */ @@ -5737,6 +5822,7 @@ typedef struct #define ADC_SPT1_CSPT12_1 (0x2U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000080 */ #define ADC_SPT1_CSPT12_2 (0x4U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000100 */ +/*!< CSPT13 configuration */ #define ADC_SPT1_CSPT13_Pos (9U) #define ADC_SPT1_CSPT13_Msk (0x7U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000E00 */ #define ADC_SPT1_CSPT13 ADC_SPT1_CSPT13_Msk /*!< CSPT13[2:0] bits (Sample time selection of channel ADC_IN13) */ @@ -5744,6 +5830,7 @@ typedef struct #define ADC_SPT1_CSPT13_1 (0x2U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000400 */ #define ADC_SPT1_CSPT13_2 (0x4U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000800 */ +/*!< CSPT14 configuration */ #define ADC_SPT1_CSPT14_Pos (12U) #define ADC_SPT1_CSPT14_Msk (0x7U << ADC_SPT1_CSPT14_Pos) /*!< 0x00007000 */ #define ADC_SPT1_CSPT14 ADC_SPT1_CSPT14_Msk /*!< CSPT14[2:0] bits (Sample time selection of channel ADC_IN14) */ @@ -5751,6 +5838,7 @@ typedef struct #define ADC_SPT1_CSPT14_1 (0x2U << ADC_SPT1_CSPT14_Pos) /*!< 0x00002000 */ #define ADC_SPT1_CSPT14_2 (0x4U << ADC_SPT1_CSPT14_Pos) /*!< 0x00004000 */ +/*!< CSPT15 configuration */ #define ADC_SPT1_CSPT15_Pos (15U) #define ADC_SPT1_CSPT15_Msk (0x7U << ADC_SPT1_CSPT15_Pos) /*!< 0x00038000 */ #define ADC_SPT1_CSPT15 ADC_SPT1_CSPT15_Msk /*!< CSPT15[2:0] bits (Sample time selection of channel ADC_IN15) */ @@ -5758,6 +5846,7 @@ typedef struct #define ADC_SPT1_CSPT15_1 (0x2U << ADC_SPT1_CSPT15_Pos) /*!< 0x00010000 */ #define ADC_SPT1_CSPT15_2 (0x4U << ADC_SPT1_CSPT15_Pos) /*!< 0x00020000 */ +/*!< CSPT16 configuration */ #define ADC_SPT1_CSPT16_Pos (18U) #define ADC_SPT1_CSPT16_Msk (0x7U << ADC_SPT1_CSPT16_Pos) /*!< 0x001C0000 */ #define ADC_SPT1_CSPT16 ADC_SPT1_CSPT16_Msk /*!< CSPT16[2:0] bits (Sample time selection of channel ADC_IN16) */ @@ -5765,6 +5854,7 @@ typedef struct #define ADC_SPT1_CSPT16_1 (0x2U << ADC_SPT1_CSPT16_Pos) /*!< 0x00080000 */ #define ADC_SPT1_CSPT16_2 (0x4U << ADC_SPT1_CSPT16_Pos) /*!< 0x00100000 */ +/*!< CSPT17 configuration */ #define ADC_SPT1_CSPT17_Pos (21U) #define ADC_SPT1_CSPT17_Msk (0x7U << ADC_SPT1_CSPT17_Pos) /*!< 0x00E00000 */ #define ADC_SPT1_CSPT17 ADC_SPT1_CSPT17_Msk /*!< CSPT17[2:0] bits (Sample time selection of channel ADC_IN17) */ @@ -5773,6 +5863,7 @@ typedef struct #define ADC_SPT1_CSPT17_2 (0x4U << ADC_SPT1_CSPT17_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_SPT2 register *******************/ +/*!< CSPT0 configuration */ #define ADC_SPT2_CSPT0_Pos (0U) #define ADC_SPT2_CSPT0_Msk (0x7U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000007 */ #define ADC_SPT2_CSPT0 ADC_SPT2_CSPT0_Msk /*!< CSPT0[2:0] bits (Sample time selection of channel ADC_IN0) */ @@ -5780,6 +5871,7 @@ typedef struct #define ADC_SPT2_CSPT0_1 (0x2U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000002 */ #define ADC_SPT2_CSPT0_2 (0x4U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000004 */ +/*!< CSPT1 configuration */ #define ADC_SPT2_CSPT1_Pos (3U) #define ADC_SPT2_CSPT1_Msk (0x7U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000038 */ #define ADC_SPT2_CSPT1 ADC_SPT2_CSPT1_Msk /*!< CSPT1[2:0] bits (Sample time selection of channel ADC_IN1) */ @@ -5787,6 +5879,7 @@ typedef struct #define ADC_SPT2_CSPT1_1 (0x2U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000010 */ #define ADC_SPT2_CSPT1_2 (0x4U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000020 */ +/*!< CSPT2 configuration */ #define ADC_SPT2_CSPT2_Pos (6U) #define ADC_SPT2_CSPT2_Msk (0x7U << ADC_SPT2_CSPT2_Pos) /*!< 0x000001C0 */ #define ADC_SPT2_CSPT2 ADC_SPT2_CSPT2_Msk /*!< CSPT2[2:0] bits (Sample time selection of channel ADC_IN2) */ @@ -5794,6 +5887,7 @@ typedef struct #define ADC_SPT2_CSPT2_1 (0x2U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000080 */ #define ADC_SPT2_CSPT2_2 (0x4U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000100 */ +/*!< CSPT3 configuration */ #define ADC_SPT2_CSPT3_Pos (9U) #define ADC_SPT2_CSPT3_Msk (0x7U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000E00 */ #define ADC_SPT2_CSPT3 ADC_SPT2_CSPT3_Msk /*!< CSPT3[2:0] bits (Sample time selection of channel ADC_IN3) */ @@ -5801,6 +5895,7 @@ typedef struct #define ADC_SPT2_CSPT3_1 (0x2U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000400 */ #define ADC_SPT2_CSPT3_2 (0x4U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000800 */ +/*!< CSPT4 configuration */ #define ADC_SPT2_CSPT4_Pos (12U) #define ADC_SPT2_CSPT4_Msk (0x7U << ADC_SPT2_CSPT4_Pos) /*!< 0x00007000 */ #define ADC_SPT2_CSPT4 ADC_SPT2_CSPT4_Msk /*!< CSPT4[2:0] bits (Sample time selection of channel ADC_IN4) */ @@ -5808,6 +5903,7 @@ typedef struct #define ADC_SPT2_CSPT4_1 (0x2U << ADC_SPT2_CSPT4_Pos) /*!< 0x00002000 */ #define ADC_SPT2_CSPT4_2 (0x4U << ADC_SPT2_CSPT4_Pos) /*!< 0x00004000 */ +/*!< CSPT5 configuration */ #define ADC_SPT2_CSPT5_Pos (15U) #define ADC_SPT2_CSPT5_Msk (0x7U << ADC_SPT2_CSPT5_Pos) /*!< 0x00038000 */ #define ADC_SPT2_CSPT5 ADC_SPT2_CSPT5_Msk /*!< CSPT5[2:0] bits (Sample time selection of channel ADC_IN5) */ @@ -5815,6 +5911,7 @@ typedef struct #define ADC_SPT2_CSPT5_1 (0x2U << ADC_SPT2_CSPT5_Pos) /*!< 0x00010000 */ #define ADC_SPT2_CSPT5_2 (0x4U << ADC_SPT2_CSPT5_Pos) /*!< 0x00020000 */ +/*!< CSPT6 configuration */ #define ADC_SPT2_CSPT6_Pos (18U) #define ADC_SPT2_CSPT6_Msk (0x7U << ADC_SPT2_CSPT6_Pos) /*!< 0x001C0000 */ #define ADC_SPT2_CSPT6 ADC_SPT2_CSPT6_Msk /*!< CSPT6[2:0] bits (Sample time selection of channel ADC_IN6) */ @@ -5822,6 +5919,7 @@ typedef struct #define ADC_SPT2_CSPT6_1 (0x2U << ADC_SPT2_CSPT6_Pos) /*!< 0x00080000 */ #define ADC_SPT2_CSPT6_2 (0x4U << ADC_SPT2_CSPT6_Pos) /*!< 0x00100000 */ +/*!< CSPT7 configuration */ #define ADC_SPT2_CSPT7_Pos (21U) #define ADC_SPT2_CSPT7_Msk (0x7U << ADC_SPT2_CSPT7_Pos) /*!< 0x00E00000 */ #define ADC_SPT2_CSPT7 ADC_SPT2_CSPT7_Msk /*!< CSPT7[2:0] bits (Sample time selection of channel ADC_IN7) */ @@ -5829,6 +5927,7 @@ typedef struct #define ADC_SPT2_CSPT7_1 (0x2U << ADC_SPT2_CSPT7_Pos) /*!< 0x00400000 */ #define ADC_SPT2_CSPT7_2 (0x4U << ADC_SPT2_CSPT7_Pos) /*!< 0x00800000 */ +/*!< CSPT8 configuration */ #define ADC_SPT2_CSPT8_Pos (24U) #define ADC_SPT2_CSPT8_Msk (0x7U << ADC_SPT2_CSPT8_Pos) /*!< 0x07000000 */ #define ADC_SPT2_CSPT8 ADC_SPT2_CSPT8_Msk /*!< CSPT8[2:0] bits (Sample time selection of channel ADC_IN8) */ @@ -5836,6 +5935,7 @@ typedef struct #define ADC_SPT2_CSPT8_1 (0x2U << ADC_SPT2_CSPT8_Pos) /*!< 0x02000000 */ #define ADC_SPT2_CSPT8_2 (0x4U << ADC_SPT2_CSPT8_Pos) /*!< 0x04000000 */ +/*!< CSPT9 configuration */ #define ADC_SPT2_CSPT9_Pos (27U) #define ADC_SPT2_CSPT9_Msk (0x7U << ADC_SPT2_CSPT9_Pos) /*!< 0x38000000 */ #define ADC_SPT2_CSPT9 ADC_SPT2_CSPT9_Msk /*!< CSPT9[2:0] bits (Sample time selection of channel ADC_IN9) */ @@ -5874,6 +5974,7 @@ typedef struct #define ADC_VMLB_VMLB ADC_VMLB_VMLB_Msk /*!< Voltage monitoring low boundary */ /******************* Bit definition for ADC_OSQ1 register *******************/ +/*!< OSN13 configuration */ #define ADC_OSQ1_OSN13_Pos (0U) #define ADC_OSQ1_OSN13_Msk (0x1FU << ADC_OSQ1_OSN13_Pos) /*!< 0x0000001F */ #define ADC_OSQ1_OSN13 ADC_OSQ1_OSN13_Msk /*!< OSN13[4:0] bits (Number of 13th conversion in ordinary sequence) */ @@ -5883,6 +5984,7 @@ typedef struct #define ADC_OSQ1_OSN13_3 (0x08U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000008 */ #define ADC_OSQ1_OSN13_4 (0x10U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000010 */ +/*!< OSN14 configuration */ #define ADC_OSQ1_OSN14_Pos (5U) #define ADC_OSQ1_OSN14_Msk (0x1FU << ADC_OSQ1_OSN14_Pos) /*!< 0x000003E0 */ #define ADC_OSQ1_OSN14 ADC_OSQ1_OSN14_Msk /*!< OSN14[4:0] bits (Number of 14th conversion in ordinary sequence) */ @@ -5892,6 +5994,7 @@ typedef struct #define ADC_OSQ1_OSN14_3 (0x08U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000100 */ #define ADC_OSQ1_OSN14_4 (0x10U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000200 */ +/*!< OSN15 configuration */ #define ADC_OSQ1_OSN15_Pos (10U) #define ADC_OSQ1_OSN15_Msk (0x1FU << ADC_OSQ1_OSN15_Pos) /*!< 0x00007C00 */ #define ADC_OSQ1_OSN15 ADC_OSQ1_OSN15_Msk /*!< OSN15[4:0] bits (Number of 15th conversion in ordinary sequence) */ @@ -5901,6 +6004,7 @@ typedef struct #define ADC_OSQ1_OSN15_3 (0x08U << ADC_OSQ1_OSN15_Pos) /*!< 0x00002000 */ #define ADC_OSQ1_OSN15_4 (0x10U << ADC_OSQ1_OSN15_Pos) /*!< 0x00004000 */ +/*!< OSN16 configuration */ #define ADC_OSQ1_OSN16_Pos (15U) #define ADC_OSQ1_OSN16_Msk (0x1FU << ADC_OSQ1_OSN16_Pos) /*!< 0x000F8000 */ #define ADC_OSQ1_OSN16 ADC_OSQ1_OSN16_Msk /*!< OSN16[4:0] bits (Number of 16th conversion in ordinary sequence) */ @@ -5910,6 +6014,7 @@ typedef struct #define ADC_OSQ1_OSN16_3 (0x08U << ADC_OSQ1_OSN16_Pos) /*!< 0x00040000 */ #define ADC_OSQ1_OSN16_4 (0x10U << ADC_OSQ1_OSN16_Pos) /*!< 0x00080000 */ +/*!< OCLEN configuration */ #define ADC_OSQ1_OCLEN_Pos (20U) #define ADC_OSQ1_OCLEN_Msk (0xFU << ADC_OSQ1_OCLEN_Pos) /*!< 0x00F00000 */ #define ADC_OSQ1_OCLEN ADC_OSQ1_OCLEN_Msk /*!< OCLEN[3:0] bits (Ordinary conversion sequence length) */ @@ -5919,6 +6024,7 @@ typedef struct #define ADC_OSQ1_OCLEN_3 (0x8U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_OSQ2 register *******************/ +/*!< OSN7 configuration */ #define ADC_OSQ2_OSN7_Pos (0U) #define ADC_OSQ2_OSN7_Msk (0x1FU << ADC_OSQ2_OSN7_Pos) /*!< 0x0000001F */ #define ADC_OSQ2_OSN7 ADC_OSQ2_OSN7_Msk /*!< OSN7[4:0] bits (Number of 7th conversion in ordinary sequence) */ @@ -5928,6 +6034,7 @@ typedef struct #define ADC_OSQ2_OSN7_3 (0x08U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000008 */ #define ADC_OSQ2_OSN7_4 (0x10U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000010 */ +/*!< OSN8 configuration */ #define ADC_OSQ2_OSN8_Pos (5U) #define ADC_OSQ2_OSN8_Msk (0x1FU << ADC_OSQ2_OSN8_Pos) /*!< 0x000003E0 */ #define ADC_OSQ2_OSN8 ADC_OSQ2_OSN8_Msk /*!< OSN8[4:0] bits (Number of 8th conversion in ordinary sequence) */ @@ -5937,6 +6044,7 @@ typedef struct #define ADC_OSQ2_OSN8_3 (0x08U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000100 */ #define ADC_OSQ2_OSN8_4 (0x10U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000200 */ +/*!< OSN9 configuration */ #define ADC_OSQ2_OSN9_Pos (10U) #define ADC_OSQ2_OSN9_Msk (0x1FU << ADC_OSQ2_OSN9_Pos) /*!< 0x00007C00 */ #define ADC_OSQ2_OSN9 ADC_OSQ2_OSN9_Msk /*!< OSN9[4:0] bits (Number of 9th conversion in ordinary sequence) */ @@ -5946,6 +6054,7 @@ typedef struct #define ADC_OSQ2_OSN9_3 (0x08U << ADC_OSQ2_OSN9_Pos) /*!< 0x00002000 */ #define ADC_OSQ2_OSN9_4 (0x10U << ADC_OSQ2_OSN9_Pos) /*!< 0x00004000 */ +/*!< OSN10 configuration */ #define ADC_OSQ2_OSN10_Pos (15U) #define ADC_OSQ2_OSN10_Msk (0x1FU << ADC_OSQ2_OSN10_Pos) /*!< 0x000F8000 */ #define ADC_OSQ2_OSN10 ADC_OSQ2_OSN10_Msk /*!< OSN10[4:0] bits (Number of 10th conversion in ordinary sequence) */ @@ -5955,6 +6064,7 @@ typedef struct #define ADC_OSQ2_OSN10_3 (0x08U << ADC_OSQ2_OSN10_Pos) /*!< 0x00040000 */ #define ADC_OSQ2_OSN10_4 (0x10U << ADC_OSQ2_OSN10_Pos) /*!< 0x00080000 */ +/*!< OSN11 configuration */ #define ADC_OSQ2_OSN11_Pos (20U) #define ADC_OSQ2_OSN11_Msk (0x1FU << ADC_OSQ2_OSN11_Pos) /*!< 0x01F00000 */ #define ADC_OSQ2_OSN11 ADC_OSQ2_OSN11_Msk /*!< OSN11[4:0] bits (Number of 11th conversion in ordinary sequence) */ @@ -5964,6 +6074,7 @@ typedef struct #define ADC_OSQ2_OSN11_3 (0x08U << ADC_OSQ2_OSN11_Pos) /*!< 0x00800000 */ #define ADC_OSQ2_OSN11_4 (0x10U << ADC_OSQ2_OSN11_Pos) /*!< 0x01000000 */ +/*!< OSN12 configuration */ #define ADC_OSQ2_OSN12_Pos (25U) #define ADC_OSQ2_OSN12_Msk (0x1FU << ADC_OSQ2_OSN12_Pos) /*!< 0x3E000000 */ #define ADC_OSQ2_OSN12 ADC_OSQ2_OSN12_Msk /*!< OSN12[4:0] bits (Number of 12th conversion in ordinary sequence) */ @@ -5974,6 +6085,7 @@ typedef struct #define ADC_OSQ2_OSN12_4 (0x10U << ADC_OSQ2_OSN12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_OSQ3 register *******************/ +/*!< OSN1 configuration */ #define ADC_OSQ3_OSN1_Pos (0U) #define ADC_OSQ3_OSN1_Msk (0x1FU << ADC_OSQ3_OSN1_Pos) /*!< 0x0000001F */ #define ADC_OSQ3_OSN1 ADC_OSQ3_OSN1_Msk /*!< OSN1[4:0] bits (Number of 1st conversion in ordinary sequence) */ @@ -5983,6 +6095,7 @@ typedef struct #define ADC_OSQ3_OSN1_3 (0x08U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000008 */ #define ADC_OSQ3_OSN1_4 (0x10U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000010 */ +/*!< OSN2 configuration */ #define ADC_OSQ3_OSN2_Pos (5U) #define ADC_OSQ3_OSN2_Msk (0x1FU << ADC_OSQ3_OSN2_Pos) /*!< 0x000003E0 */ #define ADC_OSQ3_OSN2 ADC_OSQ3_OSN2_Msk /*!< OSN2[4:0] bits (Number of 2nd conversion in ordinary sequence) */ @@ -5992,6 +6105,7 @@ typedef struct #define ADC_OSQ3_OSN2_3 (0x08U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000100 */ #define ADC_OSQ3_OSN2_4 (0x10U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000200 */ +/*!< OSN3 configuration */ #define ADC_OSQ3_OSN3_Pos (10U) #define ADC_OSQ3_OSN3_Msk (0x1FU << ADC_OSQ3_OSN3_Pos) /*!< 0x00007C00 */ #define ADC_OSQ3_OSN3 ADC_OSQ3_OSN3_Msk /*!< OSN3[4:0] bits (Number of 3rd conversion in ordinary sequence) */ @@ -6001,6 +6115,7 @@ typedef struct #define ADC_OSQ3_OSN3_3 (0x08U << ADC_OSQ3_OSN3_Pos) /*!< 0x00002000 */ #define ADC_OSQ3_OSN3_4 (0x10U << ADC_OSQ3_OSN3_Pos) /*!< 0x00004000 */ +/*!< OSN4 configuration */ #define ADC_OSQ3_OSN4_Pos (15U) #define ADC_OSQ3_OSN4_Msk (0x1FU << ADC_OSQ3_OSN4_Pos) /*!< 0x000F8000 */ #define ADC_OSQ3_OSN4 ADC_OSQ3_OSN4_Msk /*!< OSN4[4:0] bits (Number of 4th conversion in ordinary sequence) */ @@ -6010,6 +6125,7 @@ typedef struct #define ADC_OSQ3_OSN4_3 (0x08U << ADC_OSQ3_OSN4_Pos) /*!< 0x00040000 */ #define ADC_OSQ3_OSN4_4 (0x10U << ADC_OSQ3_OSN4_Pos) /*!< 0x00080000 */ +/*!< OSN5 configuration */ #define ADC_OSQ3_OSN5_Pos (20U) #define ADC_OSQ3_OSN5_Msk (0x1FU << ADC_OSQ3_OSN5_Pos) /*!< 0x01F00000 */ #define ADC_OSQ3_OSN5 ADC_OSQ3_OSN5_Msk /*!< OSN5[4:0] bits (Number of 5th conversion in ordinary sequence) */ @@ -6019,6 +6135,7 @@ typedef struct #define ADC_OSQ3_OSN5_3 (0x08U << ADC_OSQ3_OSN5_Pos) /*!< 0x00800000 */ #define ADC_OSQ3_OSN5_4 (0x10U << ADC_OSQ3_OSN5_Pos) /*!< 0x01000000 */ +/*!< OSN6 configuration */ #define ADC_OSQ3_OSN6_Pos (25U) #define ADC_OSQ3_OSN6_Msk (0x1FU << ADC_OSQ3_OSN6_Pos) /*!< 0x3E000000 */ #define ADC_OSQ3_OSN6 ADC_OSQ3_OSN6_Msk /*!< OSN6[4:0] bits (Number of 6th conversion in ordinary sequence) */ @@ -6029,6 +6146,7 @@ typedef struct #define ADC_OSQ3_OSN6_4 (0x10U << ADC_OSQ3_OSN6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_PSQ register ********************/ +/*!< PSN1 configuration */ #define ADC_PSQ_PSN1_Pos (0U) #define ADC_PSQ_PSN1_Msk (0x1FU << ADC_PSQ_PSN1_Pos) /*!< 0x0000001F */ #define ADC_PSQ_PSN1 ADC_PSQ_PSN1_Msk /*!< PSN1[4:0] bits (Number of 1st conversion in preempted sequence) */ @@ -6038,6 +6156,7 @@ typedef struct #define ADC_PSQ_PSN1_3 (0x08U << ADC_PSQ_PSN1_Pos) /*!< 0x00000008 */ #define ADC_PSQ_PSN1_4 (0x10U << ADC_PSQ_PSN1_Pos) /*!< 0x00000010 */ +/*!< PSN2 configuration */ #define ADC_PSQ_PSN2_Pos (5U) #define ADC_PSQ_PSN2_Msk (0x1FU << ADC_PSQ_PSN2_Pos) /*!< 0x000003E0 */ #define ADC_PSQ_PSN2 ADC_PSQ_PSN2_Msk /*!< PSN2[4:0] bits (Number of 2nd conversion in preempted sequence) */ @@ -6047,6 +6166,7 @@ typedef struct #define ADC_PSQ_PSN2_3 (0x08U << ADC_PSQ_PSN2_Pos) /*!< 0x00000100 */ #define ADC_PSQ_PSN2_4 (0x10U << ADC_PSQ_PSN2_Pos) /*!< 0x00000200 */ +/*!< PSN3 configuration */ #define ADC_PSQ_PSN3_Pos (10U) #define ADC_PSQ_PSN3_Msk (0x1FU << ADC_PSQ_PSN3_Pos) /*!< 0x00007C00 */ #define ADC_PSQ_PSN3 ADC_PSQ_PSN3_Msk /*!< PSN3[4:0] bits (Number of 3rd conversion in preempted sequence) */ @@ -6056,6 +6176,7 @@ typedef struct #define ADC_PSQ_PSN3_3 (0x08U << ADC_PSQ_PSN3_Pos) /*!< 0x00002000 */ #define ADC_PSQ_PSN3_4 (0x10U << ADC_PSQ_PSN3_Pos) /*!< 0x00004000 */ +/*!< PSN4 configuration */ #define ADC_PSQ_PSN4_Pos (15U) #define ADC_PSQ_PSN4_Msk (0x1FU << ADC_PSQ_PSN4_Pos) /*!< 0x000F8000 */ #define ADC_PSQ_PSN4 ADC_PSQ_PSN4_Msk /*!< PSN4[4:0] bits (Number of 4th conversion in preempted sequence) */ @@ -6065,6 +6186,7 @@ typedef struct #define ADC_PSQ_PSN4_3 (0x08U << ADC_PSQ_PSN4_Pos) /*!< 0x00040000 */ #define ADC_PSQ_PSN4_4 (0x10U << ADC_PSQ_PSN4_Pos) /*!< 0x00080000 */ +/*!< PCLEN configuration */ #define ADC_PSQ_PCLEN_Pos (20U) #define ADC_PSQ_PCLEN_Msk (0x3U << ADC_PSQ_PCLEN_Pos) /*!< 0x00300000 */ #define ADC_PSQ_PCLEN ADC_PSQ_PCLEN_Msk /*!< PCLEN[1:0] bits (Preempted conversion sequence length) */ @@ -6095,9 +6217,6 @@ typedef struct #define ADC_ODT_ODT_Pos (0U) #define ADC_ODT_ODT_Msk (0xFFFFU << ADC_ODT_ODT_Pos) /*!< 0x0000FFFF */ #define ADC_ODT_ODT ADC_ODT_ODT_Msk /*!< Conversion data of ordinary channel */ -#define ADC_ODT_ADC2ODT_Pos (16U) -#define ADC_ODT_ADC2ODT_Msk (0xFFFFU << ADC_ODT_ADC2ODT_Pos) /*!< 0xFFFF0000 */ -#define ADC_ODT_ADC2ODT ADC_ODT_ADC2ODT_Msk /*!< ADC2 conversion data of ordinary channel */ /******************************************************************************/ /* */ @@ -6217,6 +6336,7 @@ typedef struct #define CAN_TSTS_TMNR_Msk (0x3U << CAN_TSTS_TMNR_Pos) /*!< 0x03000000 */ #define CAN_TSTS_TMNR CAN_TSTS_TMNR_Msk /*!< TMNR[1:0] bits (Transmit mailbox number record) */ +/*!< TMEF congiguration */ #define CAN_TSTS_TMEF_Pos (26U) #define CAN_TSTS_TMEF_Msk (0x7U << CAN_TSTS_TMEF_Pos) /*!< 0x1C000000 */ #define CAN_TSTS_TMEF CAN_TSTS_TMEF_Msk /*!< TMEF[2:0] bits (Transmit mailbox empty flag) */ @@ -6230,6 +6350,7 @@ typedef struct #define CAN_TSTS_TM2EF_Msk (0x1U << CAN_TSTS_TM2EF_Pos) /*!< 0x10000000 */ #define CAN_TSTS_TM2EF CAN_TSTS_TM2EF_Msk /*!< Transmit mailbox 2 empty flag */ +/*!< TMLPF congiguration */ #define CAN_TSTS_TMLPF_Pos (29U) #define CAN_TSTS_TMLPF_Msk (0x7U << CAN_TSTS_TMLPF_Pos) /*!< 0xE0000000 */ #define CAN_TSTS_TMLPF CAN_TSTS_TMLPF_Msk /*!< TMLPF[2:0] bits (Transmit mailbox lowest priority flag) */ @@ -6326,6 +6447,7 @@ typedef struct #define CAN_ESTS_BOF_Msk (0x1U << CAN_ESTS_BOF_Pos) /*!< 0x00000004 */ #define CAN_ESTS_BOF CAN_ESTS_BOF_Msk /*!< Bus-off flag */ +/*!< ETR congiguration */ #define CAN_ESTS_ETR_Pos (4U) #define CAN_ESTS_ETR_Msk (0x7U << CAN_ESTS_ETR_Pos) /*!< 0x00000070 */ #define CAN_ESTS_ETR CAN_ESTS_ETR_Msk /*!< ETR[2:0] bits (Error type record) */ @@ -6345,6 +6467,7 @@ typedef struct #define CAN_BTMG_BRDIV_Msk (0xFFFU << CAN_BTMG_BRDIV_Pos) /*!< 0x00000FFF */ #define CAN_BTMG_BRDIV CAN_BTMG_BRDIV_Msk /*!< Baud rate division */ +/*!< BTS1 congiguration */ #define CAN_BTMG_BTS1_Pos (16U) #define CAN_BTMG_BTS1_Msk (0xFU << CAN_BTMG_BTS1_Pos) /*!< 0x000F0000 */ #define CAN_BTMG_BTS1 CAN_BTMG_BTS1_Msk /*!< BTS1[3:0] bits (Bit time segment 1) */ @@ -6353,6 +6476,7 @@ typedef struct #define CAN_BTMG_BTS1_2 (0x4U << CAN_BTMG_BTS1_Pos) /*!< 0x00040000 */ #define CAN_BTMG_BTS1_3 (0x8U << CAN_BTMG_BTS1_Pos) /*!< 0x00080000 */ +/*!< BTS2 congiguration */ #define CAN_BTMG_BTS2_Pos (20U) #define CAN_BTMG_BTS2_Msk (0x7U << CAN_BTMG_BTS2_Pos) /*!< 0x00700000 */ #define CAN_BTMG_BTS2 CAN_BTMG_BTS2_Msk /*!< BTS2[2:0] bits (Bit time segment 2) */ @@ -6360,6 +6484,7 @@ typedef struct #define CAN_BTMG_BTS2_1 (0x2U << CAN_BTMG_BTS2_Pos) /*!< 0x00200000 */ #define CAN_BTMG_BTS2_2 (0x4U << CAN_BTMG_BTS2_Pos) /*!< 0x00400000 */ +/*!< RSAW congiguration */ #define CAN_BTMG_RSAW_Pos (24U) #define CAN_BTMG_RSAW_Msk (0x3U << CAN_BTMG_RSAW_Pos) /*!< 0x03000000 */ #define CAN_BTMG_RSAW CAN_BTMG_RSAW_Msk /*!< RSAW[1:0] bits (Resynchronization width) */ @@ -9593,6 +9718,7 @@ typedef struct /******************************************************************************/ /***************** Bit definition for SDIO_PWRCTRL register *****************/ +/*!< PS congiguration */ #define SDIO_PWRCTRL_PS_Pos (0U) #define SDIO_PWRCTRL_PS_Msk (0x3U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000003 */ #define SDIO_PWRCTRL_PS SDIO_PWRCTRL_PS_Msk /*!< PS[1:0] bits (Power switch) */ @@ -9612,6 +9738,7 @@ typedef struct #define SDIO_CLKCTRL_BYPSEN_Msk (0x1U << SDIO_CLKCTRL_BYPSEN_Pos) /*!< 0x00000400 */ #define SDIO_CLKCTRL_BYPSEN SDIO_CLKCTRL_BYPSEN_Msk /*!< Clock divider bypass enable bit */ +/*!< BUSWS congiguration */ #define SDIO_CLKCTRL_BUSWS_Pos (11U) #define SDIO_CLKCTRL_BUSWS_Msk (0x3U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00001800 */ #define SDIO_CLKCTRL_BUSWS SDIO_CLKCTRL_BUSWS_Msk /*!< BUSWS[1:0] bits (Bus width selection) */ @@ -9635,6 +9762,7 @@ typedef struct #define SDIO_CMD_CMDIDX_Msk (0x3FU << SDIO_CMD_CMDIDX_Pos) /*!< 0x0000003F */ #define SDIO_CMD_CMDIDX SDIO_CMD_CMDIDX_Msk /*!< Command index */ +/*!< RSPWT congiguration */ #define SDIO_CMD_RSPWT_Pos (6U) #define SDIO_CMD_RSPWT_Msk (0x3U << SDIO_CMD_RSPWT_Pos) /*!< 0x000000C0 */ #define SDIO_CMD_RSPWT SDIO_CMD_RSPWT_Msk /*!< RSPWT[1:0] bits (Wait for response bits) */ @@ -9685,7 +9813,7 @@ typedef struct #define SDIO_DTTMR_TIMEOUT SDIO_DTTMR_TIMEOUT_Msk /*!< Data timeout period */ /****************** Bit definition for SDIO_DTLEN register ******************/ -#define SDIO_DTLEN_DTLEN_Pos (0U) +#define SDIO_DTLEN_DTLEN_Pos (0U) #define SDIO_DTLEN_DTLEN_Msk (0x1FFFFFFU << SDIO_DTLEN_DTLEN_Pos) /*!< 0x01FFFFFF */ #define SDIO_DTLEN_DTLEN SDIO_DTLEN_DTLEN_Msk /*!< Data length value */ @@ -9703,6 +9831,7 @@ typedef struct #define SDIO_DTCTRL_DMAEN_Msk (0x1U << SDIO_DTCTRL_DMAEN_Pos) /*!< 0x00000008 */ #define SDIO_DTCTRL_DMAEN SDIO_DTCTRL_DMAEN_Msk /*!< DMA enable bit */ +/*!< BLKSIZE congiguration */ #define SDIO_DTCTRL_BLKSIZE_Pos (4U) #define SDIO_DTCTRL_BLKSIZE_Msk (0xFU << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x000000F0 */ #define SDIO_DTCTRL_BLKSIZE SDIO_DTCTRL_BLKSIZE_Msk /*!< BLKSIZE[3:0] bits (Data block size) */ @@ -9936,6 +10065,7 @@ typedef struct #define CMP_CTRLSTS1_CMP1SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP1SSEL_Pos) /*!< 0x00000004 */ #define CMP_CTRLSTS1_CMP1SSEL CMP_CTRLSTS1_CMP1SSEL_Msk /*!< Comparator 1 speed selection */ +/*!< CMP1INVSEL congiguration */ #define CMP_CTRLSTS1_CMP1INVSEL_Pos (4U) #define CMP_CTRLSTS1_CMP1INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000070 */ #define CMP_CTRLSTS1_CMP1INVSEL CMP_CTRLSTS1_CMP1INVSEL_Msk /*!< CMP1INVSEL[2:0] bits (Comparator 1 inverting selection) */ @@ -9943,6 +10073,7 @@ typedef struct #define CMP_CTRLSTS1_CMP1INVSEL_1 (0x2U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000020 */ #define CMP_CTRLSTS1_CMP1INVSEL_2 (0x4U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000040 */ +/*!< CMP1TAG congiguration */ #define CMP_CTRLSTS1_CMP1TAG_Pos (8U) #define CMP_CTRLSTS1_CMP1TAG_Msk (0x7U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000700 */ #define CMP_CTRLSTS1_CMP1TAG CMP_CTRLSTS1_CMP1TAG_Msk /*!< CMP1TAG[2:0] bits (Comparator 1 output target) */ @@ -9954,6 +10085,7 @@ typedef struct #define CMP_CTRLSTS1_CMP1P_Msk (0x1U << CMP_CTRLSTS1_CMP1P_Pos) /*!< 0x00000800 */ #define CMP_CTRLSTS1_CMP1P CMP_CTRLSTS1_CMP1P_Msk /*!< Comparator 1 polarity */ +/*!< CMP1HYST congiguration */ #define CMP_CTRLSTS1_CMP1HYST_Pos (12U) #define CMP_CTRLSTS1_CMP1HYST_Msk (0x3U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00003000 */ #define CMP_CTRLSTS1_CMP1HYST CMP_CTRLSTS1_CMP1HYST_Msk /*!< CMP1HYST[1:0] bits (Comparator 1 hysteresis) */ @@ -9973,6 +10105,7 @@ typedef struct #define CMP_CTRLSTS1_CMP2SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP2SSEL_Pos) /*!< 0x00040000 */ #define CMP_CTRLSTS1_CMP2SSEL CMP_CTRLSTS1_CMP2SSEL_Msk /*!< Comparator 2 speed selection */ +/*!< CMP2INVSEL congiguration */ #define CMP_CTRLSTS1_CMP2INVSEL_Pos (20U) #define CMP_CTRLSTS1_CMP2INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00700000 */ #define CMP_CTRLSTS1_CMP2INVSEL CMP_CTRLSTS1_CMP2INVSEL_Msk /*!< CMP2INVSEL[2:0] bits (Comparator 2 inverting selection) */ @@ -9984,6 +10117,7 @@ typedef struct #define CMP_CTRLSTS1_DCMPEN_Msk (0x1U << CMP_CTRLSTS1_DCMPEN_Pos) /*!< 0x00800000 */ #define CMP_CTRLSTS1_DCMPEN CMP_CTRLSTS1_DCMPEN_Msk /*!< Double comparator mode enable */ +/*!< CMP2TAG congiguration */ #define CMP_CTRLSTS1_CMP2TAG_Pos (24U) #define CMP_CTRLSTS1_CMP2TAG_Msk (0x7U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x07000000 */ #define CMP_CTRLSTS1_CMP2TAG CMP_CTRLSTS1_CMP2TAG_Msk /*!< CMP2TAG[2:0] bits (Comparator 2 output target) */ @@ -9995,6 +10129,7 @@ typedef struct #define CMP_CTRLSTS1_CMP2P_Msk (0x1U << CMP_CTRLSTS1_CMP2P_Pos) /*!< 0x08000000 */ #define CMP_CTRLSTS1_CMP2P CMP_CTRLSTS1_CMP2P_Msk /*!< Comparator 2 polarity */ +/*!< CMP2HYST congiguration */ #define CMP_CTRLSTS1_CMP2HYST_Pos (28U) #define CMP_CTRLSTS1_CMP2HYST_Msk (0x3U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x30000000 */ #define CMP_CTRLSTS1_CMP2HYST CMP_CTRLSTS1_CMP2HYST_Msk /*!< CMP2HYST[1:0] bits (Comparator 2 hysteresis) */ @@ -10009,15 +10144,17 @@ typedef struct #define CMP_CTRLSTS1_CMP2WP CMP_CTRLSTS1_CMP2WP_Msk /*!< Comparator 2 write protect */ /***************** Bit definition for CMP_CTRLSTS2 register *****************/ +/*!< CMP1NINVSEL congiguration */ #define CMP_CTRLSTS2_CMP1NINVSEL_Pos (0U) #define CMP_CTRLSTS2_CMP1NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000003 */ -#define CMP_CTRLSTS2_CMP1NINVSEL CMP_CTRLSTS2_CMP1NINVSEL_Msk /*!< Comparator 1 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP1NINVSEL CMP_CTRLSTS2_CMP1NINVSEL_Msk /*!< CMP1NINVSEL[1:0] bits (Comparator 1 non-inverting input selection) */ #define CMP_CTRLSTS2_CMP1NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000001 */ #define CMP_CTRLSTS2_CMP1NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000002 */ +/*!< CMP2NINVSEL congiguration */ #define CMP_CTRLSTS2_CMP2NINVSEL_Pos (16U) #define CMP_CTRLSTS2_CMP2NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00030000 */ -#define CMP_CTRLSTS2_CMP2NINVSEL CMP_CTRLSTS2_CMP2NINVSEL_Msk /*!< Comparator 2 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP2NINVSEL CMP_CTRLSTS2_CMP2NINVSEL_Msk /*!< CMP2NINVSEL[1:0] bits (Comparator 2 non-inverting input selection) */ #define CMP_CTRLSTS2_CMP2NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00010000 */ #define CMP_CTRLSTS2_CMP2NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00020000 */ @@ -10028,6 +10165,7 @@ typedef struct /******************************************************************************/ /***************** Bit definition for DEBUG_IDCODE register *****************/ +/*!< PID congiguration */ #define DEBUG_IDCODE_PID_Pos (0U) #define DEBUG_IDCODE_PID_Msk (0xFFFFFFFFU << DEBUG_IDCODE_PID_Pos) /*!< 0xFFFFFFFF */ #define DEBUG_IDCODE_PID DEBUG_IDCODE_PID_Msk /*!< PID[31:0] bits (PID information) */ @@ -10078,6 +10216,7 @@ typedef struct #define DEBUG_CTRL_TRACE_IOEN_Msk (0x1U << DEBUG_CTRL_TRACE_IOEN_Pos) /*!< 0x00000020 */ #define DEBUG_CTRL_TRACE_IOEN DEBUG_CTRL_TRACE_IOEN_Msk /*!< Trace pin assignment enable */ +/*!< TRACE_MODE congiguration */ #define DEBUG_CTRL_TRACE_MODE_Pos (6U) #define DEBUG_CTRL_TRACE_MODE_Msk (0x3U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x000000C0 */ #define DEBUG_CTRL_TRACE_MODE DEBUG_CTRL_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace pin assignment control) */ @@ -10136,344 +10275,6 @@ typedef struct * @{ */ -/******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) - -#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) - -#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) - -/******************************* CAN Instances ********************************/ -#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) - -/******************************* CRC Instances ********************************/ -#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) - -/******************************* DMA Instances ********************************/ -#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ - ((INSTANCE) == DMA1_Channel2) || \ - ((INSTANCE) == DMA1_Channel3) || \ - ((INSTANCE) == DMA1_Channel4) || \ - ((INSTANCE) == DMA1_Channel5) || \ - ((INSTANCE) == DMA1_Channel6) || \ - ((INSTANCE) == DMA1_Channel7) || \ - ((INSTANCE) == DMA2_Channel1) || \ - ((INSTANCE) == DMA2_Channel2) || \ - ((INSTANCE) == DMA2_Channel3) || \ - ((INSTANCE) == DMA2_Channel4) || \ - ((INSTANCE) == DMA2_Channel5) || \ - ((INSTANCE) == DMA2_Channel6) || \ - ((INSTANCE) == DMA2_Channel7)) - -/******************************* GPIO Instances *******************************/ -#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ - ((INSTANCE) == GPIOB) || \ - ((INSTANCE) == GPIOC) || \ - ((INSTANCE) == GPIOD) || \ - ((INSTANCE) == GPIOF)) - -/********************* IOMUX Multiplex Function Instances *********************/ -#define IS_IOMUX_ALL_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) - -/**************************** GPIO Lock Instances *****************************/ -#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) - -/******************************* I2C Instances ********************************/ -#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ - ((INSTANCE) == I2C2)) - -/****************************** SMBUS Instances *******************************/ -#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE - -/******************************* I2S Instances ********************************/ -#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ - ((INSTANCE) == SPI2)) - -/******************************* WDT Instances ********************************/ -#define IS_WDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WDT) - -/******************************* SDIO Instances *******************************/ -#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) - -/******************************* SPI Instances ********************************/ -#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ - ((INSTANCE) == SPI2)) - -/**************************** START TMR Instances *****************************/ -/******************************* TMR Instances ********************************/ -#define IS_TMR_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9) || \ - ((INSTANCE) == TMR10) || \ - ((INSTANCE) == TMR11)) - -#define IS_TMR_ADVANCED_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1) - -#define IS_TMR_C1_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9) || \ - ((INSTANCE) == TMR10) || \ - ((INSTANCE) == TMR11)) - -#define IS_TMR_C2_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_C3_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_C4_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_CLOCKSOURCE_EXTMODE1_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_CLOCKSOURCE_EXTMODE2_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_CLOCKSOURCE_TRGIN_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_CLOCKSOURCE_ISX_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_OCXREF_CLEAR_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_XOR_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_MASTER_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_SLAVE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_DMABURST_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_BREAK_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1) - -#define IS_TMR_CX_INSTANCE(INSTANCE, CHANNEL) \ - ((((INSTANCE) == TMR1) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR2) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR3) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR4) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR5) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR9) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2))) \ - || \ - (((INSTANCE) == TMR10) && \ - (((CHANNEL) == TMR_CHANNEL_1))) \ - || \ - (((INSTANCE) == TMR11) && \ - (((CHANNEL) == TMR_CHANNEL_1)))) - -#define IS_TMR_CXN_INSTANCE(INSTANCE, CHANNEL) \ - (((INSTANCE) == TMR1) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3))) - -#define IS_TMR_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_REPETITION_COUNTER_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1) - -#define IS_TMR_CLOCK_DIVISION_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9) || \ - ((INSTANCE) == TMR10) || \ - ((INSTANCE) == TMR11)) - -#define IS_TMR_DMA_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_DMA_CC_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1)) - -#define IS_TMR_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_32B_COUNTER_INSTANCE(INSTANCE) 0U - -/***************************** END TMR Instances ******************************/ - -/********************* USART Instances : Synchronous mode *********************/ -#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/********************* UART Instances : Asynchronous mode *********************/ -#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/********************* UART Instances : Half-Duplex mode **********************/ -#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/************************* UART Instances : LIN mode **************************/ -#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/******************* UART Instances : Hardware Flow control *******************/ -#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/********************* UART Instances : Smard card mode ***********************/ -#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/************************* UART Instances : IRDA mode *************************/ -#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/******************* UART Instances : Multi-Processor mode ********************/ -#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/******************** UART Instances : DMA mode available *********************/ -#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/******************************* ERTC Instances *******************************/ -#define IS_ERTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ERTC) - -/******************************* WWDT Instances *******************************/ -#define IS_WWDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDT) - #define CRM_HEXT_MIN 4000000U #define CRM_HEXT_MAX 25000000U diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h index 77ea395899..2bc82557c5 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file at32f415kx.h * @author Artery Technology & HorrorTroll & Zhaqian - * @version v2.1.1 - * @date 26-October-2023 + * @version v2.1.2 + * @date 05-January-2024 * @brief AT32F415Kx header file. * ****************************************************************************** @@ -42,11 +42,11 @@ #endif /** - * @brief CMSIS Device version number V2.1.1 + * @brief CMSIS Device version number V2.1.2 */ #define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ #define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ -#define __AT32F415_LIBRARY_VERSION_MINOR (0x01) /*!< [15:8] minor version */ +#define __AT32F415_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */ #define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\ |(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\ @@ -102,7 +102,7 @@ typedef enum WWDT_IRQn = 0, /*!< Window WatchDog Timer Interrupt */ PVM_IRQn = 1, /*!< PVM Interrupt linked to EXINT16 */ TAMPER_IRQn = 2, /*!< Tamper Interrupt linked to EXINT21 */ - ERTC_IRQn = 3, /*!< ERTC Interrupt linked to EXINT22 */ + ERTC_WKUP_IRQn = 3, /*!< ERTC Wake Up Interrupt linked to EXINT22 */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ CRM_IRQn = 5, /*!< CRM global Interrupt */ EXINT0_IRQn = 6, /*!< EXINT Line 0 Interrupt */ @@ -178,8 +178,8 @@ typedef struct __IO uint32_t SPT2; /*!< ADC sampling time register 2, Address offset: 0x10 */ __IO uint32_t PCDTO1; /*!< ADC preempted channel data offset reg 1, Address offset: 0x14 */ __IO uint32_t PCDTO2; /*!< ADC preempted channel data offset reg 2, Address offset: 0x18 */ - __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3 Address offset: 0x1C */ - __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4 Address offset: 0x20 */ + __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3, Address offset: 0x1C */ + __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4, Address offset: 0x20 */ __IO uint32_t VMHB; /*!< ADC voltage monitor high threshold register, Address offset: 0x24 */ __IO uint32_t VMLB; /*!< ADC voltage monitor low threshold register, Address offset: 0x28 */ __IO uint32_t OSQ1; /*!< ADC ordinary sequence register 1, Address offset: 0x2C */ @@ -241,10 +241,10 @@ typedef struct __IO uint32_t INTEN; /*!< CAN interrupt enable register, Address offset: 0x014 */ __IO uint32_t ESTS; /*!< CAN error status register, Address offset: 0x018 */ __IO uint32_t BTMG; /*!< CAN bit timing register, Address offset: 0x01C */ - uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17F */ + uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17C */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN TX Mailbox registers, Address offset: 0x180 ~ 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO Mailbox registers, Address offset: 0x1B0 ~ 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FF */ + uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FC */ __IO uint32_t FCTRL; /*!< CAN filter control register, Address offset: 0x200 */ __IO uint32_t FMCFG; /*!< CAN filter mode configuration register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x208 */ @@ -253,7 +253,7 @@ typedef struct __IO uint32_t FRF; /*!< CAN filter FIFO association register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x218 */ __IO uint32_t FACFG; /*!< CAN filter activation control register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23F */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23C */ CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN filter registers, Address offset: 0x240 ~ 0x2AC */ } CAN_TypeDef; @@ -268,7 +268,7 @@ typedef struct } CMP_TypeDef; /** - * @brief CRC calculation unit + * @brief CRC Calculation Unit */ typedef struct @@ -321,10 +321,10 @@ typedef struct typedef struct { - __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x08 + 20 * (x - 1) x = 1 ... 7 */ - __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x0C + 20 * (x - 1) x = 1 ... 7 */ - __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + 20 * (x - 1) x = 1 ... 7 */ - __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x14 + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x08 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x0C + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x14 + 20 * (x - 1) (x = 1 ... 7) */ } DMA_Channel_TypeDef; typedef struct @@ -405,7 +405,7 @@ typedef struct typedef struct { __IO uint32_t PSR; /*!< FLASH performance select register, Address offset: 0x00 */ - __IO uint32_t UNLOCK; /*!< FLASH unlock register 1, Address offset: 0x04 */ + __IO uint32_t UNLOCK; /*!< FLASH unlock register, Address offset: 0x04 */ __IO uint32_t USD_UNLOCK; /*!< FLASH user system data unlock register, Address offset: 0x08 */ __IO uint32_t STS; /*!< FLASH status register, Address offset: 0x0C */ __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x10 */ @@ -425,7 +425,7 @@ typedef struct __IO uint32_t SLIB_SET_PWD; /*!< FLASH security library password setting reg, Address offset: 0x160 */ __IO uint32_t SLIB_SET_RANGE; /*!< FLASH security library address setting reg, Address offset: 0x164 */ __IO uint32_t EM_SLIB_SET; /*!< FLASH extension mem security lib set reg, Address offset: 0x168 */ - __IO uint32_t BTM_MODE_SET; /*!< FLASH boot mode setting register, Address offset: 0x16C */ + __IO uint32_t BTM_MODE_SET; /*!< FLASH boot memory mode setting register, Address offset: 0x16C */ __IO uint32_t SLIB_UNLOCK; /*!< FLASH security library unlock register, Address offset: 0x170 */ } FLASH_TypeDef; @@ -435,15 +435,15 @@ typedef struct typedef struct { - __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ - __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ - __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ - __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ - __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ - __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ - __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ - __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ - __IO uint16_t DATA[504]; /*!< USD User data 2 ~ 505, Address offset: 0x1FFF_F810 ~ 0x1FFF_FBFC */ + __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ + __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ + __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ + __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ + __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ + __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ + __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ + __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ + __IO uint16_t DATA[504]; /*!< USD User data 2 ~ 505, Address offset: 0x1FFF_F810 ~ 0x1FFF_FBFC */ } USD_TypeDef; /** @@ -452,13 +452,13 @@ typedef struct typedef struct { - __IO uint32_t CFGLR; /*!< GPIO configuration register low, Address offset: 0x00 */ - __IO uint32_t CFGHR; /*!< GPIO configuration register high, Address offset: 0x04 */ - __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x08 */ - __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x0C */ - __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x10 */ - __IO uint32_t CLR; /*!< GPIO clear register, Address offset: 0x14 */ - __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x18 */ + __IO uint32_t CFGLR; /*!< GPIO configuration register low, Address offset: 0x00 */ + __IO uint32_t CFGHR; /*!< GPIO configuration register high, Address offset: 0x04 */ + __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x08 */ + __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x0C */ + __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x10 */ + __IO uint32_t CLR; /*!< GPIO clear register, Address offset: 0x14 */ + __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x18 */ } GPIO_TypeDef; /** @@ -467,17 +467,17 @@ typedef struct typedef struct { - __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ - __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ - __IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ - __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ - __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ - __IO uint32_t REMAP4; /*!< IOMUX remap register 4, Address offset: 0x24 */ - __IO uint32_t REMAP5; /*!< IOMUX remap register 5, Address offset: 0x28 */ - __IO uint32_t REMAP6; /*!< IOMUX remap register 6, Address offset: 0x2C */ - __IO uint32_t REMAP7; /*!< IOMUX remap register 7, Address offset: 0x30 */ - __IO uint32_t REMAP8; /*!< IOMUX remap register 8, Address offset: 0x34 */ + __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ + __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ + __IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register x, Address offset: 0x08 ~ 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ + __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ + __IO uint32_t REMAP4; /*!< IOMUX remap register 4, Address offset: 0x24 */ + __IO uint32_t REMAP5; /*!< IOMUX remap register 5, Address offset: 0x28 */ + __IO uint32_t REMAP6; /*!< IOMUX remap register 6, Address offset: 0x2C */ + __IO uint32_t REMAP7; /*!< IOMUX remap register 7, Address offset: 0x30 */ + __IO uint32_t REMAP8; /*!< IOMUX remap register 8, Address offset: 0x34 */ } IOMUX_TypeDef; /** @@ -546,9 +546,9 @@ typedef struct __IO uint32_t STS; /*!< SPI status register, Address offset: 0x08 */ __IO uint32_t DT; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CPOLY; /*!< SPI CRC register, Address offset: 0x10 */ - __IO uint32_t RCRC; /*!< SPI RX CRC register, Address offset: 0x14 */ - __IO uint32_t TCRC; /*!< SPI TX CRC register, Address offset: 0x18 */ - __IO uint32_t I2SCTRL; /*!< SPI_I2S register, Address offset: 0x1C */ + __IO uint32_t RCRC; /*!< SPI receive CRC register, Address offset: 0x14 */ + __IO uint32_t TCRC; /*!< SPI transmit CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCTRL; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SCLKP; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; @@ -566,9 +566,9 @@ typedef struct __IO uint32_t SWEVT; /*!< TMR software event register, Address offset: 0x14 */ __IO uint32_t CM1; /*!< TMR channel mode register 1, Address offset: 0x18 */ __IO uint32_t CM2; /*!< TMR channel mode register 2, Address offset: 0x1C */ - __IO uint32_t CCTRL; /*!< TMR Channel control register, Address offset: 0x20 */ - __IO uint32_t CVAL; /*!< TMR counter value, Address offset: 0x24 */ - __IO uint32_t DIV; /*!< TMR division value, Address offset: 0x28 */ + __IO uint32_t CCTRL; /*!< TMR channel control register, Address offset: 0x20 */ + __IO uint32_t CVAL; /*!< TMR counter value register, Address offset: 0x24 */ + __IO uint32_t DIV; /*!< TMR division value register, Address offset: 0x28 */ __IO uint32_t PR; /*!< TMR period register, Address offset: 0x2C */ __IO uint32_t RPR; /*!< TMR repetition period register, Address offset: 0x30 */ __IO uint32_t C1DT; /*!< TMR channel 1 data register, Address offset: 0x34 */ @@ -653,6 +653,7 @@ typedef struct #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /*!< I2C2 base address */ #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) /*!< CAN1 base address */ #define PWC_BASE (APB1PERIPH_BASE + 0x00007000U) /*!< PWC base address */ + #define IOMUX_BASE (APB2PERIPH_BASE + 0x00000000U) /*!< IOMUX base address */ #define EXINT_BASE (APB2PERIPH_BASE + 0x00000400U) /*!< EXINT base address */ #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) /*!< GPIOA base address */ @@ -696,8 +697,8 @@ typedef struct #define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ -/* USB OTG device FS */ -#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG Peripheral Registers base address */ +/* USB OTG FS */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG FS Peripheral Registers base address */ #define USB_OTG_GLOBAL_BASE 0x00000000U /*!< USB OTG Global Registers base address */ #define USB_OTG_DEVICE_BASE 0x00000800U /*!< USB OTG Device ModeRegisters base address */ @@ -708,9 +709,7 @@ typedef struct #define USB_OTG_HOST_PORT_BASE 0x00000440U /*!< USB OTG Host Port Registers base address */ #define USB_OTG_HOST_CHANNEL_BASE 0x00000500U /*!< USB OTG Host Channel Registers base address */ #define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U /*!< USB OTG Host Channel Registers size address */ -#define USB_OTG_DEP3RMPEN_BASE 0x00000D0CU /*!< USB OTG DEP3RMPEN Registers base address */ #define USB_OTG_PCGCCTL_BASE 0x00000E00U /*!< USB OTG Power and Ctrl Registers base address */ -#define USB_OTG_USBDIVRST_BASE 0x00000E10U /*!< USB OTG USBDIVRST Registers base address */ #define USB_OTG_FIFO_BASE 0x00001000U /*!< USB OTG FIFO Registers base address */ #define USB_OTG_FIFO_SIZE 0x00001000U /*!< USB OTG FIFO Registers size address */ @@ -722,56 +721,56 @@ typedef struct * @{ */ -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define CAN1 ((CAN_TypeDef *)CAN1_BASE) -#define CMP ((CMP_TypeDef *)CMP_BASE) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define CRM ((CRM_TypeDef *)CRM_BASE) -#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define DMA2 ((DMA_TypeDef *)DMA2_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) -#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) -#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) -#define ERTC ((ERTC_TypeDef *)ERTC_BASE) -#define EXINT ((EXINT_TypeDef *)EXINT_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define USD ((USD_TypeDef *)USD_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) -#define IOMUX ((IOMUX_TypeDef *)IOMUX_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define I2C2 ((I2C_TypeDef *)I2C2_BASE) -#define PWC ((PWC_TypeDef *)PWC_BASE) -#define SDIO ((SDIO_TypeDef *)SDIO_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) -#define TMR1 ((TMR_TypeDef *)TMR1_BASE) -#define TMR2 ((TMR_TypeDef *)TMR2_BASE) -#define TMR3 ((TMR_TypeDef *)TMR3_BASE) -#define TMR4 ((TMR_TypeDef *)TMR4_BASE) -#define TMR5 ((TMR_TypeDef *)TMR5_BASE) -#define TMR9 ((TMR_TypeDef *)TMR9_BASE) -#define TMR10 ((TMR_TypeDef *)TMR10_BASE) -#define TMR11 ((TMR_TypeDef *)TMR11_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define WDT ((WDT_TypeDef *)WDT_BASE) -#define WWDT ((WWDT_TypeDef *)WWDT_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CMP ((CMP_TypeDef *)CMP_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CRM ((CRM_TypeDef *)CRM_BASE) +#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) +#define ERTC ((ERTC_TypeDef *)ERTC_BASE) +#define EXINT ((EXINT_TypeDef *)EXINT_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USD ((USD_TypeDef *)USD_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define IOMUX ((IOMUX_TypeDef *)IOMUX_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define PWC ((PWC_TypeDef *)PWC_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define TMR1 ((TMR_TypeDef *)TMR1_BASE) +#define TMR2 ((TMR_TypeDef *)TMR2_BASE) +#define TMR3 ((TMR_TypeDef *)TMR3_BASE) +#define TMR4 ((TMR_TypeDef *)TMR4_BASE) +#define TMR5 ((TMR_TypeDef *)TMR5_BASE) +#define TMR9 ((TMR_TypeDef *)TMR9_BASE) +#define TMR10 ((TMR_TypeDef *)TMR10_BASE) +#define TMR11 ((TMR_TypeDef *)TMR11_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) /** * @} @@ -801,7 +800,7 @@ typedef struct #define PWC_CTRL_VRSEL PWC_CTRL_VRSEL_Msk /*!< LDO state select in deep sleep mode */ #define PWC_CTRL_LPSEL_Pos (1U) #define PWC_CTRL_LPSEL_Msk (0x1U << PWC_CTRL_LPSEL_Pos) /*!< 0x00000002 */ -#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep */ +#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep mode */ #define PWC_CTRL_CLSWEF_Pos (2U) #define PWC_CTRL_CLSWEF_Msk (0x1U << PWC_CTRL_CLSWEF_Pos) /*!< 0x00000004 */ #define PWC_CTRL_CLSWEF PWC_CTRL_CLSWEF_Msk /*!< Clear SWEF flag */ @@ -1155,7 +1154,7 @@ typedef struct #define CRM_CLKINT_PLLSTBLF CRM_CLKINT_PLLSTBLF_Msk /*!< PLL stable flag */ #define CRM_CLKINT_CFDF_Pos (7U) #define CRM_CLKINT_CFDF_Msk (0x1U << CRM_CLKINT_CFDF_Pos) /*!< 0x00000080 */ -#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock Failure Detection flag */ +#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock failure detection flag */ #define CRM_CLKINT_LICKSTBLIEN_Pos (8U) #define CRM_CLKINT_LICKSTBLIEN_Msk (0x1U << CRM_CLKINT_LICKSTBLIEN_Pos) /*!< 0x00000100 */ #define CRM_CLKINT_LICKSTBLIEN CRM_CLKINT_LICKSTBLIEN_Msk /*!< LICK stable interrupt enable */ @@ -1380,10 +1379,10 @@ typedef struct #define CRM_BPDC_LEXTEN CRM_BPDC_LEXTEN_Msk /*!< External low-speed oscillator enable */ #define CRM_BPDC_LEXTSTBL_Pos (1U) #define CRM_BPDC_LEXTSTBL_Msk (0x1U << CRM_BPDC_LEXTSTBL_Pos) /*!< 0x00000002 */ -#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< Low speed external oscillator stable */ +#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< External low-speed oscillator stable */ #define CRM_BPDC_LEXTBYPS_Pos (2U) #define CRM_BPDC_LEXTBYPS_Msk (0x1U << CRM_BPDC_LEXTBYPS_Pos) /*!< 0x00000004 */ -#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< Low speed external crystal bypass */ +#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< External low-speed crystal bypass */ /*!< ERTCSEL congiguration */ #define CRM_BPDC_ERTCSEL_Pos (8U) @@ -1494,7 +1493,7 @@ typedef struct #define CRM_MISC1_HICKCAL_KEY_Msk (0xFFU << CRM_MISC1_HICKCAL_KEY_Pos) /*!< 0x000000FF */ #define CRM_MISC1_HICKCAL_KEY CRM_MISC1_HICKCAL_KEY_Msk /*!< HICK calibration key */ #define CRM_MISC1_CLKOUT_SEL_Pos (16U) -#define CRM_MISC1_CLKOUT_SEL_Msk (0x1U << CRN_MISC1_CLKOUT_SEL_Pos) /*!< 0x00010000 */ +#define CRM_MISC1_CLKOUT_SEL_Msk (0x1U << CRM_MISC1_CLKOUT_SEL_Pos) /*!< 0x00010000 */ #define CRM_MISC1_CLKOUT_SEL CRM_MISC1_CLKOUT_SEL_Msk /*!< Clock output selection */ #define CRM_MISC1_CLKFMC_SRC_Pos (20U) #define CRM_MISC1_CLKFMC_SRC_Msk (0x1U << CRM_MISC1_CLKFMC_SRC_Pos) /*!< 0x00100000 */ @@ -1506,7 +1505,7 @@ typedef struct /*!< CLKOUTDIV congiguration */ #define CRM_MISC1_CLKOUTDIV_Pos (28U) #define CRM_MISC1_CLKOUTDIV_Msk (0xFU << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0xF0000000 */ -#define CRM_MISC1_CLKOUTDIV CRM_MISC1_CLKOUTDIV_Msk /*!< CLKOUTDIV[3:0] bits (Clock output division */ +#define CRM_MISC1_CLKOUTDIV CRM_MISC1_CLKOUTDIV_Msk /*!< CLKOUTDIV[3:0] bits (Clock output division) */ #define CRM_MISC1_CLKOUTDIV_0 (0x1U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x10000000 */ #define CRM_MISC1_CLKOUTDIV_1 (0x2U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x20000000 */ #define CRM_MISC1_CLKOUTDIV_2 (0x4U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x40000000 */ @@ -1534,7 +1533,7 @@ typedef struct /*!< AUTO_STEP_EN congiguration */ #define CRM_MISC2_AUTO_STEP_EN_Pos (4U) #define CRM_MISC2_AUTO_STEP_EN_Msk (0x3U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000030 */ -#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] Auto step-by-step SCLK switch enable */ +#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] bits (Auto step-by-step SCLK switch enable) */ #define CRM_MISC2_AUTO_STEP_EN_0 (0x1U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000010 */ #define CRM_MISC2_AUTO_STEP_EN_1 (0x2U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000020 */ @@ -1552,7 +1551,7 @@ typedef struct /*!< WTCYC congiguration */ #define FLASH_PSR_WTCYC_Pos (0U) #define FLASH_PSR_WTCYC_Msk (0x7U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000007 */ -#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] Wait states */ +#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] bits (Wait cycle) */ #define FLASH_PSR_WTCYC_0 (0x1U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000001 */ #define FLASH_PSR_WTCYC_1 (0x2U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000002 */ #define FLASH_PSR_WTCYC_2 (0x4U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000004 */ @@ -1593,7 +1592,7 @@ typedef struct /****************** Bit definition for FLASH_STS register *******************/ #define FLASH_STS_OBF_Pos (0U) #define FLASH_STS_OBF_Msk (0x1U << FLASH_STS_OBF_Pos) /*!< 0x00000001 */ -#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation done flag */ +#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation busy flag */ #define FLASH_STS_PRGMERR_Pos (2U) #define FLASH_STS_PRGMERR_Msk (0x1U << FLASH_STS_PRGMERR_Pos) /*!< 0x00000004 */ #define FLASH_STS_PRGMERR FLASH_STS_PRGMERR_Msk /*!< Programming error */ @@ -1700,10 +1699,10 @@ typedef struct #define SLIB_STS1_SLIB_SS_Msk (0x7FFU << SLIB_STS1_SLIB_SS_Pos) /*!< 0x000007FF */ #define SLIB_STS1_SLIB_SS SLIB_STS1_SLIB_SS_Msk /*!< Security library start page */ #define SLIB_STS1_SLIB_DAT_SS_Pos (11U) -#define SLIB_STS1_SLIB_DAT_SS_Msk (0x3FF8U << SLIB_STS1_SLIB_DAT_SS_Pos) /*!< 0x003FF800 */ +#define SLIB_STS1_SLIB_DAT_SS_Msk (0x7FFU << SLIB_STS1_SLIB_DAT_SS_Pos) /*!< 0x003FF800 */ #define SLIB_STS1_SLIB_DAT_SS SLIB_STS1_SLIB_DAT_SS_Msk /*!< Security library data start page */ #define SLIB_STS1_SLIB_ES_Pos (22U) -#define SLIB_STS1_SLIB_ES_Msk (0xFFCU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ +#define SLIB_STS1_SLIB_ES_Msk (0x3FFU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ #define SLIB_STS1_SLIB_ES SLIB_STS1_SLIB_ES_Msk /*!< Security library end page */ /***************** Bit definition for SLIB_PWD_CLR register ******************/ @@ -1722,10 +1721,10 @@ typedef struct #define SLIB_MISC_STS_SLIB_ULKF_Msk (0x1U << SLIB_MISC_STS_SLIB_ULKF_Pos) /*!< 0x00000004 */ #define SLIB_MISC_STS_SLIB_ULKF SLIB_MISC_STS_SLIB_ULKF_Msk /*!< Security library unlock flag */ -/***************** Bit definition for FLASH_CRC_ARR register *****************/ -#define FLASH_CRC_ARR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ -#define FLASH_CRC_ARR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ARR_CRC_ADDR_Pos) -#define FLASH_CRC_ARR_CRC_ADDR FLASH_CRC_ARR_CRC_ADDR_Msk /*!< CRC address */ +/**************** Bit definition for FLASH_CRC_ADDR register *****************/ +#define FLASH_CRC_ADDR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_ADDR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ADDR_CRC_ADDR_Pos) +#define FLASH_CRC_ADDR_CRC_ADDR FLASH_CRC_ADDR_CRC_ADDR_Msk /*!< CRC address */ /**************** Bit definition for FLASH_CRC_CTRL register *****************/ #define FLASH_CRC_CTRL_CRC_SN_Pos (0U) @@ -1743,7 +1742,7 @@ typedef struct /***************** Bit definition for SLIB_SET_PWD register ******************/ #define SLIB_SET_PWD_SLIB_PSET_VAL_Pos (0U) /*!< 0xFFFFFFFF */ #define SLIB_SET_PWD_SLIB_PSET_VAL_Msk (0xFFFFFFFFU << SLIB_SET_PWD_SLIB_PSET_VAL_Pos) -#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< sLib password setting value */ +#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< Security library password setting value */ /**************** Bit definition for SLIB_SET_RANGE register *****************/ #define SLIB_SET_RANGE_SLIB_SS_SET_Pos (0U) /*!< 0x000007FF */ @@ -1762,7 +1761,7 @@ typedef struct #define EM_SLIB_SET_EM_SLIB_SET EM_SLIB_SET_EM_SLIB_SET_Msk /*!< Extension memory sLib setting */ #define EM_SLIB_SET_EM_SLIB_ISS_SET_Pos (16U) /*!< 0x00FF0000 */ #define EM_SLIB_SET_EM_SLIB_ISS_SET_Msk (0xFFU << EM_SLIB_SET_EM_SLIB_ISS_SET_Pos) -#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page setting */ /***************** Bit definition for BTM_MODE_SET register ******************/ #define BTM_MODE_SET_BTM_MODE_SET_Pos (0U) /*!< 0x000000FF */ @@ -1774,9 +1773,9 @@ typedef struct #define SLIB_UNLOCK_SLIB_UKVAL_Msk (0xFFFFFFFFU << SLIB_UNLOCK_SLIB_UKVAL_Pos) #define SLIB_UNLOCK_SLIB_UKVAL SLIB_UNLOCK_SLIB_UKVAL_Msk /*!< Security library unlock key value */ -#define SLIB_KEY_Pos (0U) +#define SLIB_KEY_Pos (0U) #define SLIB_KEY_Msk (0xA35F6D24U << SLIB_KEY_Pos) /*!< 0xA35F6D24 */ -#define SLIB_KEY SLIB_KEY_Msk +#define SLIB_KEY SLIB_KEY_Msk /*!< Security library key */ /*----------------------------------------------------------------------------*/ @@ -1796,7 +1795,7 @@ typedef struct #define FLASH_SSB_nSSB_Msk (0xFFU << FLASH_SSB_nSSB_Pos) /*!< 0xFF000000 */ #define FLASH_SSB_nSSB FLASH_SSB_nSSB_Msk /*!< Inverse code of system configuration byte */ -/****************** Bit definition for FLASH_DATA0 register *****************/ +/***************** Bit definition for FLASH_DATA0 register ******************/ #define FLASH_DATA0_DATA0_Pos (0U) #define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data 0 */ @@ -1804,7 +1803,7 @@ typedef struct #define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< Inverse code of user data 0 */ -/****************** Bit definition for FLASH_DATA1 register *****************/ +/***************** Bit definition for FLASH_DATA1 register ******************/ #define FLASH_DATA1_DATA1_Pos (16U) #define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data 1 */ @@ -1844,15 +1843,7 @@ typedef struct #define FLASH_EPP3_nEPP3_Msk (0xFFU << FLASH_EPP3_nEPP3_Pos) /*!< 0xFF000000 */ #define FLASH_EPP3_nEPP3 FLASH_EPP3_nEPP3_Msk /*!< Inverse code of flash erase/write protection byte 3 */ -/***************** Bit definition for FLASH_EOPB0 register ******************/ -#define FLASH_EOPB0_EOPB0_Pos (0U) -#define FLASH_EOPB0_EOPB0_Msk (0xFFU << FLASH_EOPB0_EOPB0_Pos) /*!< 0x000000FF */ -#define FLASH_EOPB0_EOPB0 FLASH_EOPB0_EOPB0_Msk /*!< Extended system options */ -#define FLASH_EOPB0_nEOPB0_Pos (8U) -#define FLASH_EOPB0_nEOPB0_Msk (0xFFU << FLASH_EOPB0_nEOPB0_Pos) /*!< 0x0000FF00 */ -#define FLASH_EOPB0_nEOPB0 FLASH_EOPB0_nEOPB0_Msk /*!< Inverse code of extended system options */ - -/****************** Bit definition for FLASH_DATA2 register *****************/ +/***************** Bit definition for FLASH_DATA2 register ******************/ #define FLASH_DATA2_DATA2_Pos (0U) #define FLASH_DATA2_DATA2_Msk (0xFFU << FLASH_DATA2_DATA2_Pos) /*!< 0x000000FF */ #define FLASH_DATA2_DATA2 FLASH_DATA2_DATA2_Msk /*!< User data 2 */ @@ -1860,7 +1851,7 @@ typedef struct #define FLASH_DATA2_nDATA2_Msk (0xFFU << FLASH_DATA2_nDATA2_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA2_nDATA2 FLASH_DATA2_nDATA2_Msk /*!< Inverse code of user data 2 */ -/****************** Bit definition for FLASH_DATA3 register *****************/ +/***************** Bit definition for FLASH_DATA3 register ******************/ #define FLASH_DATA3_DATA3_Pos (16U) #define FLASH_DATA3_DATA3_Msk (0xFFU << FLASH_DATA3_DATA3_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA3_DATA3 FLASH_DATA3_DATA3_Msk /*!< User data 3 */ @@ -1868,7 +1859,7 @@ typedef struct #define FLASH_DATA3_nDATA3_Msk (0xFFU << FLASH_DATA3_nDATA3_Pos) /*!< 0xFF000000 */ #define FLASH_DATA3_nDATA3 FLASH_DATA3_nDATA3_Msk /*!< Inverse code of user data 3 */ -/****************** Bit definition for FLASH_DATA4 register *****************/ +/***************** Bit definition for FLASH_DATA4 register ******************/ #define FLASH_DATA4_DATA4_Pos (0U) #define FLASH_DATA4_DATA4_Msk (0xFFU << FLASH_DATA4_DATA4_Pos) /*!< 0x000000FF */ #define FLASH_DATA4_DATA4 FLASH_DATA4_DATA4_Msk /*!< User data 4 */ @@ -1876,7 +1867,7 @@ typedef struct #define FLASH_DATA4_nDATA4_Msk (0xFFU << FLASH_DATA4_nDATA4_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA4_nDATA4 FLASH_DATA4_nDATA4_Msk /*!< Inverse code of user data 4 */ -/****************** Bit definition for FLASH_DATA5 register *****************/ +/***************** Bit definition for FLASH_DATA5 register ******************/ #define FLASH_DATA5_DATA5_Pos (16U) #define FLASH_DATA5_DATA5_Msk (0xFFU << FLASH_DATA5_DATA5_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA5_DATA5 FLASH_DATA5_DATA5_Msk /*!< User data 5 */ @@ -1884,7 +1875,7 @@ typedef struct #define FLASH_DATA5_nDATA5_Msk (0xFFU << FLASH_DATA5_nDATA5_Pos) /*!< 0xFF000000 */ #define FLASH_DATA5_nDATA5 FLASH_DATA5_nDATA5_Msk /*!< Inverse code of user data 5 */ -/****************** Bit definition for FLASH_DATA6 register *****************/ +/***************** Bit definition for FLASH_DATA6 register ******************/ #define FLASH_DATA6_DATA6_Pos (0U) #define FLASH_DATA6_DATA6_Msk (0xFFU << FLASH_DATA6_DATA6_Pos) /*!< 0x000000FF */ #define FLASH_DATA6_DATA6 FLASH_DATA6_DATA6_Msk /*!< User data 6 */ @@ -1892,7 +1883,7 @@ typedef struct #define FLASH_DATA6_nDATA6_Msk (0xFFU << FLASH_DATA6_nDATA6_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA6_nDATA6 FLASH_DATA6_nDATA6_Msk /*!< Inverse code of user data 6 */ -/****************** Bit definition for FLASH_DATA7 register *****************/ +/***************** Bit definition for FLASH_DATA7 register ******************/ #define FLASH_DATA7_DATA7_Pos (16U) #define FLASH_DATA7_DATA7_Msk (0xFFU << FLASH_DATA7_DATA7_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA7_DATA7 FLASH_DATA7_DATA7_Msk /*!< User data 7 */ @@ -1913,48 +1904,56 @@ typedef struct #define GPIO_CFGLR_IOMC_Msk (0x33333333U << GPIO_CFGLR_IOMC_Pos) /*!< 0x33333333 */ #define GPIO_CFGLR_IOMC GPIO_CFGLR_IOMC_Msk /*!< GPIO x mode configuration */ +/*!< IOMC0 configuration */ #define GPIO_CFGLR_IOMC0_Pos (0U) #define GPIO_CFGLR_IOMC0_Msk (0x3U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000003 */ #define GPIO_CFGLR_IOMC0 GPIO_CFGLR_IOMC0_Msk /*!< IOMC0[1:0] bits (GPIO x mode configuration, pin 0) */ #define GPIO_CFGLR_IOMC0_0 (0x1U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000001 */ #define GPIO_CFGLR_IOMC0_1 (0x2U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000002 */ +/*!< IOMC1 configuration */ #define GPIO_CFGLR_IOMC1_Pos (4U) #define GPIO_CFGLR_IOMC1_Msk (0x3U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000030 */ #define GPIO_CFGLR_IOMC1 GPIO_CFGLR_IOMC1_Msk /*!< IOMC1[1:0] bits (GPIO x mode configuration, pin 1) */ #define GPIO_CFGLR_IOMC1_0 (0x1U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000010 */ #define GPIO_CFGLR_IOMC1_1 (0x2U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000020 */ +/*!< IOMC2 configuration */ #define GPIO_CFGLR_IOMC2_Pos (8U) #define GPIO_CFGLR_IOMC2_Msk (0x3U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000300 */ #define GPIO_CFGLR_IOMC2 GPIO_CFGLR_IOMC2_Msk /*!< IOMC2[1:0] bits (GPIO x mode configuration, pin 2) */ #define GPIO_CFGLR_IOMC2_0 (0x1U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000100 */ #define GPIO_CFGLR_IOMC2_1 (0x2U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000200 */ +/*!< IOMC3 configuration */ #define GPIO_CFGLR_IOMC3_Pos (12U) #define GPIO_CFGLR_IOMC3_Msk (0x3U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00003000 */ #define GPIO_CFGLR_IOMC3 GPIO_CFGLR_IOMC3_Msk /*!< IOMC3[1:0] bits (GPIO x mode configuration, pin 3) */ #define GPIO_CFGLR_IOMC3_0 (0x1U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00001000 */ #define GPIO_CFGLR_IOMC3_1 (0x2U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00002000 */ +/*!< IOMC4 configuration */ #define GPIO_CFGLR_IOMC4_Pos (16U) #define GPIO_CFGLR_IOMC4_Msk (0x3U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00030000 */ #define GPIO_CFGLR_IOMC4 GPIO_CFGLR_IOMC4_Msk /*!< IOMC4[1:0] bits (GPIO x mode configuration, pin 4) */ #define GPIO_CFGLR_IOMC4_0 (0x1U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00010000 */ #define GPIO_CFGLR_IOMC4_1 (0x2U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00020000 */ +/*!< IOMC5 configuration */ #define GPIO_CFGLR_IOMC5_Pos (20U) #define GPIO_CFGLR_IOMC5_Msk (0x3U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00300000 */ #define GPIO_CFGLR_IOMC5 GPIO_CFGLR_IOMC5_Msk /*!< IOMC5[1:0] bits (GPIO x mode configuration, pin 5) */ #define GPIO_CFGLR_IOMC5_0 (0x1U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00100000 */ #define GPIO_CFGLR_IOMC5_1 (0x2U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00200000 */ +/*!< IOMC6 configuration */ #define GPIO_CFGLR_IOMC6_Pos (24U) #define GPIO_CFGLR_IOMC6_Msk (0x3U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x03000000 */ #define GPIO_CFGLR_IOMC6 GPIO_CFGLR_IOMC6_Msk /*!< IOMC6[1:0] bits (GPIO x mode configuration, pin 6) */ #define GPIO_CFGLR_IOMC6_0 (0x1U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x01000000 */ #define GPIO_CFGLR_IOMC6_1 (0x2U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x02000000 */ +/*!< IOMC7 configuration */ #define GPIO_CFGLR_IOMC7_Pos (28U) #define GPIO_CFGLR_IOMC7_Msk (0x3U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x30000000 */ #define GPIO_CFGLR_IOMC7 GPIO_CFGLR_IOMC7_Msk /*!< IOMC7[1:0] bits (GPIO x mode configuration, pin 7) */ @@ -1965,48 +1964,56 @@ typedef struct #define GPIO_CFGLR_IOFC_Msk (0x33333333U << GPIO_CFGLR_IOFC_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CFGLR_IOFC GPIO_CFGLR_IOFC_Msk /*!< GPIO x function configuration */ +/*!< IOFC0 configuration */ #define GPIO_CFGLR_IOFC0_Pos (2U) #define GPIO_CFGLR_IOFC0_Msk (0x3U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x0000000C */ #define GPIO_CFGLR_IOFC0 GPIO_CFGLR_IOFC0_Msk /*!< IOFC0[1:0] bits (GPIO x function configuration, pin 0) */ #define GPIO_CFGLR_IOFC0_0 (0x1U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000004 */ #define GPIO_CFGLR_IOFC0_1 (0x2U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000008 */ +/*!< IOFC1 configuration */ #define GPIO_CFGLR_IOFC1_Pos (6U) #define GPIO_CFGLR_IOFC1_Msk (0x3U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x000000C0 */ #define GPIO_CFGLR_IOFC1 GPIO_CFGLR_IOFC1_Msk /*!< IOFC1[1:0] bits (GPIO x function configuration, pin 1) */ #define GPIO_CFGLR_IOFC1_0 (0x1U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000040 */ #define GPIO_CFGLR_IOFC1_1 (0x2U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000080 */ +/*!< IOFC2 configuration */ #define GPIO_CFGLR_IOFC2_Pos (10U) #define GPIO_CFGLR_IOFC2_Msk (0x3U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000C00 */ #define GPIO_CFGLR_IOFC2 GPIO_CFGLR_IOFC2_Msk /*!< IOFC2[1:0] bits (GPIO x function configuration, pin 2) */ #define GPIO_CFGLR_IOFC2_0 (0x1U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000400 */ #define GPIO_CFGLR_IOFC2_1 (0x2U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000800 */ +/*!< IOFC3 configuration */ #define GPIO_CFGLR_IOFC3_Pos (14U) #define GPIO_CFGLR_IOFC3_Msk (0x3U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x0000C000 */ #define GPIO_CFGLR_IOFC3 GPIO_CFGLR_IOFC3_Msk /*!< IOFC3[1:0] bits (GPIO x function configuration, pin 3) */ #define GPIO_CFGLR_IOFC3_0 (0x1U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00004000 */ #define GPIO_CFGLR_IOFC3_1 (0x2U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00008000 */ +/*!< IOFC4 configuration */ #define GPIO_CFGLR_IOFC4_Pos (18U) #define GPIO_CFGLR_IOFC4_Msk (0x3U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x000C0000 */ #define GPIO_CFGLR_IOFC4 GPIO_CFGLR_IOFC4_Msk /*!< IOFC4[1:0] bits (GPIO x function configuration, pin 4) */ #define GPIO_CFGLR_IOFC4_0 (0x1U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00040000 */ #define GPIO_CFGLR_IOFC4_1 (0x2U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00080000 */ +/*!< IOFC5 configuration */ #define GPIO_CFGLR_IOFC5_Pos (22U) #define GPIO_CFGLR_IOFC5_Msk (0x3U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00C00000 */ #define GPIO_CFGLR_IOFC5 GPIO_CFGLR_IOFC5_Msk /*!< IOFC5[1:0] bits (GPIO x function configuration, pin 5) */ #define GPIO_CFGLR_IOFC5_0 (0x1U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00400000 */ #define GPIO_CFGLR_IOFC5_1 (0x2U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00800000 */ +/*!< IOFC6 configuration */ #define GPIO_CFGLR_IOFC6_Pos (26U) #define GPIO_CFGLR_IOFC6_Msk (0x3U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x0C000000 */ #define GPIO_CFGLR_IOFC6 GPIO_CFGLR_IOFC6_Msk /*!< IOFC6[1:0] bits (GPIO x function configuration, pin 6) */ #define GPIO_CFGLR_IOFC6_0 (0x1U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x04000000 */ #define GPIO_CFGLR_IOFC6_1 (0x2U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x08000000 */ +/*!< IOFC7 configuration */ #define GPIO_CFGLR_IOFC7_Pos (30U) #define GPIO_CFGLR_IOFC7_Msk (0x3U << GPIO_CFGLR_IOFC7_Pos) /*!< 0xC0000000 */ #define GPIO_CFGLR_IOFC7 GPIO_CFGLR_IOFC7_Msk /*!< IOFC7[1:0] bits (GPIO x function configuration, pin 7) */ @@ -2018,48 +2025,56 @@ typedef struct #define GPIO_CFGHR_IOMC_Msk (0x33333333U << GPIO_CFGHR_IOMC_Pos) /*!< 0x33333333 */ #define GPIO_CFGHR_IOMC GPIO_CFGHR_IOMC_Msk /*!< GPIO x mode configuration */ +/*!< IOMC8 configuration */ #define GPIO_CFGHR_IOMC8_Pos (0U) #define GPIO_CFGHR_IOMC8_Msk (0x3U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000003 */ #define GPIO_CFGHR_IOMC8 GPIO_CFGHR_IOMC8_Msk /*!< IOMC8[1:0] bits (GPIO x mode configuration, pin 8) */ #define GPIO_CFGHR_IOMC8_0 (0x1U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000001 */ #define GPIO_CFGHR_IOMC8_1 (0x2U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000002 */ +/*!< IOMC9 configuration */ #define GPIO_CFGHR_IOMC9_Pos (4U) #define GPIO_CFGHR_IOMC9_Msk (0x3U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000030 */ #define GPIO_CFGHR_IOMC9 GPIO_CFGHR_IOMC9_Msk /*!< IOMC9[1:0] bits (GPIO x mode configuration, pin 9) */ #define GPIO_CFGHR_IOMC9_0 (0x1U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000010 */ #define GPIO_CFGHR_IOMC9_1 (0x2U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000020 */ +/*!< IOMC10 configuration */ #define GPIO_CFGHR_IOMC10_Pos (8U) #define GPIO_CFGHR_IOMC10_Msk (0x3U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000300 */ #define GPIO_CFGHR_IOMC10 GPIO_CFGHR_IOMC10_Msk /*!< IOMC10[1:0] bits (GPIO x mode configuration, pin 10) */ #define GPIO_CFGHR_IOMC10_0 (0x1U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000100 */ #define GPIO_CFGHR_IOMC10_1 (0x2U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000200 */ +/*!< IOMC11 configuration */ #define GPIO_CFGHR_IOMC11_Pos (12U) #define GPIO_CFGHR_IOMC11_Msk (0x3U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00003000 */ #define GPIO_CFGHR_IOMC11 GPIO_CFGHR_IOMC11_Msk /*!< IOMC11[1:0] bits (GPIO x mode configuration, pin 11) */ #define GPIO_CFGHR_IOMC11_0 (0x1U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00001000 */ #define GPIO_CFGHR_IOMC11_1 (0x2U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00002000 */ +/*!< IOMC12 configuration */ #define GPIO_CFGHR_IOMC12_Pos (16U) #define GPIO_CFGHR_IOMC12_Msk (0x3U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00030000 */ #define GPIO_CFGHR_IOMC12 GPIO_CFGHR_IOMC12_Msk /*!< IOMC12[1:0] bits (GPIO x mode configuration, pin 12) */ #define GPIO_CFGHR_IOMC12_0 (0x1U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00010000 */ #define GPIO_CFGHR_IOMC12_1 (0x2U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00020000 */ +/*!< IOMC13 configuration */ #define GPIO_CFGHR_IOMC13_Pos (20U) #define GPIO_CFGHR_IOMC13_Msk (0x3U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00300000 */ #define GPIO_CFGHR_IOMC13 GPIO_CFGHR_IOMC13_Msk /*!< IOMC13[1:0] bits (GPIO x mode configuration, pin 13) */ #define GPIO_CFGHR_IOMC13_0 (0x1U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00100000 */ #define GPIO_CFGHR_IOMC13_1 (0x2U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00200000 */ +/*!< IOMC14 configuration */ #define GPIO_CFGHR_IOMC14_Pos (24U) #define GPIO_CFGHR_IOMC14_Msk (0x3U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x03000000 */ #define GPIO_CFGHR_IOMC14 GPIO_CFGHR_IOMC14_Msk /*!< IOMC14[1:0] bits (GPIO x mode configuration, pin 14) */ #define GPIO_CFGHR_IOMC14_0 (0x1U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x01000000 */ #define GPIO_CFGHR_IOMC14_1 (0x2U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x02000000 */ +/*!< IOMC15 configuration */ #define GPIO_CFGHR_IOMC15_Pos (28U) #define GPIO_CFGHR_IOMC15_Msk (0x3U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x30000000 */ #define GPIO_CFGHR_IOMC15 GPIO_CFGHR_IOMC15_Msk /*!< IOMC15[1:0] bits (GPIO x mode configuration, pin 15) */ @@ -2070,48 +2085,56 @@ typedef struct #define GPIO_CFGHR_IOFC_Msk (0x33333333U << GPIO_CFGHR_IOFC_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CFGHR_IOFC GPIO_CFGHR_IOFC_Msk /*!< GPIO x function configuration */ +/*!< IOFC8 configuration */ #define GPIO_CFGHR_IOFC8_Pos (2U) #define GPIO_CFGHR_IOFC8_Msk (0x3U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x0000000C */ #define GPIO_CFGHR_IOFC8 GPIO_CFGHR_IOFC8_Msk /*!< IOFC8[1:0] bits (GPIO x function configuration, pin 8) */ #define GPIO_CFGHR_IOFC8_0 (0x1U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000004 */ #define GPIO_CFGHR_IOFC8_1 (0x2U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000008 */ +/*!< IOFC9 configuration */ #define GPIO_CFGHR_IOFC9_Pos (6U) #define GPIO_CFGHR_IOFC9_Msk (0x3U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x000000C0 */ #define GPIO_CFGHR_IOFC9 GPIO_CFGHR_IOFC9_Msk /*!< IOFC9[1:0] bits (GPIO x function configuration, pin 9) */ #define GPIO_CFGHR_IOFC9_0 (0x1U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000040 */ #define GPIO_CFGHR_IOFC9_1 (0x2U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000080 */ +/*!< IOFC10 configuration */ #define GPIO_CFGHR_IOFC10_Pos (10U) #define GPIO_CFGHR_IOFC10_Msk (0x3U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000C00 */ #define GPIO_CFGHR_IOFC10 GPIO_CFGHR_IOFC10_Msk /*!< IOFC10[1:0] bits (GPIO x function configuration, pin 10) */ #define GPIO_CFGHR_IOFC10_0 (0x1U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000400 */ #define GPIO_CFGHR_IOFC10_1 (0x2U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000800 */ +/*!< IOFC11 configuration */ #define GPIO_CFGHR_IOFC11_Pos (14U) #define GPIO_CFGHR_IOFC11_Msk (0x3U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x0000C000 */ #define GPIO_CFGHR_IOFC11 GPIO_CFGHR_IOFC11_Msk /*!< IOFC11[1:0] bits (GPIO x function configuration, pin 11) */ #define GPIO_CFGHR_IOFC11_0 (0x1U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00004000 */ #define GPIO_CFGHR_IOFC11_1 (0x2U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00008000 */ +/*!< IOFC12 configuration */ #define GPIO_CFGHR_IOFC12_Pos (18U) #define GPIO_CFGHR_IOFC12_Msk (0x3U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x000C0000 */ #define GPIO_CFGHR_IOFC12 GPIO_CFGHR_IOFC12_Msk /*!< IOFC12[1:0] bits (GPIO x function configuration, pin 12) */ #define GPIO_CFGHR_IOFC12_0 (0x1U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00040000 */ #define GPIO_CFGHR_IOFC12_1 (0x2U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00080000 */ +/*!< IOFC13 configuration */ #define GPIO_CFGHR_IOFC13_Pos (22U) #define GPIO_CFGHR_IOFC13_Msk (0x3U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00C00000 */ #define GPIO_CFGHR_IOFC13 GPIO_CFGHR_IOFC13_Msk /*!< IOFC13[1:0] bits (GPIO x function configuration, pin 13) */ #define GPIO_CFGHR_IOFC13_0 (0x1U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00400000 */ #define GPIO_CFGHR_IOFC13_1 (0x2U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00800000 */ +/*!< IOFC14 configuration */ #define GPIO_CFGHR_IOFC14_Pos (26U) #define GPIO_CFGHR_IOFC14_Msk (0x3U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x0C000000 */ #define GPIO_CFGHR_IOFC14 GPIO_CFGHR_IOFC14_Msk /*!< IOFC14[1:0] bits (GPIO x function configuration, pin 14) */ #define GPIO_CFGHR_IOFC14_0 (0x1U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x04000000 */ #define GPIO_CFGHR_IOFC14_1 (0x2U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x08000000 */ +/*!< IOFC15 configuration */ #define GPIO_CFGHR_IOFC15_Pos (30U) #define GPIO_CFGHR_IOFC15_Msk (0x3U << GPIO_CFGHR_IOFC15_Pos) /*!< 0xC0000000 */ #define GPIO_CFGHR_IOFC15 GPIO_CFGHR_IOFC15_Msk /*!< IOFC15[1:0] bits (GPIO x function configuration, pin 15) */ @@ -2121,300 +2144,300 @@ typedef struct /*!<**************** Bit definition for GPIO_IDT register *******************/ #define GPIO_IDT_IDT0_Pos (0U) #define GPIO_IDT_IDT0_Msk (0x1U << GPIO_IDT_IDT0_Pos) /*!< 0x00000001 */ -#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, bit 0 */ +#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, pin 0 */ #define GPIO_IDT_IDT1_Pos (1U) #define GPIO_IDT_IDT1_Msk (0x1U << GPIO_IDT_IDT1_Pos) /*!< 0x00000002 */ -#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, bit 1 */ +#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, pin 1 */ #define GPIO_IDT_IDT2_Pos (2U) #define GPIO_IDT_IDT2_Msk (0x1U << GPIO_IDT_IDT2_Pos) /*!< 0x00000004 */ -#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, bit 2 */ +#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, pin 2 */ #define GPIO_IDT_IDT3_Pos (3U) #define GPIO_IDT_IDT3_Msk (0x1U << GPIO_IDT_IDT3_Pos) /*!< 0x00000008 */ -#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, bit 3 */ +#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, pin 3 */ #define GPIO_IDT_IDT4_Pos (4U) #define GPIO_IDT_IDT4_Msk (0x1U << GPIO_IDT_IDT4_Pos) /*!< 0x00000010 */ -#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, bit 4 */ +#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, pin 4 */ #define GPIO_IDT_IDT5_Pos (5U) #define GPIO_IDT_IDT5_Msk (0x1U << GPIO_IDT_IDT5_Pos) /*!< 0x00000020 */ -#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, bit 5 */ +#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, pin 5 */ #define GPIO_IDT_IDT6_Pos (6U) #define GPIO_IDT_IDT6_Msk (0x1U << GPIO_IDT_IDT6_Pos) /*!< 0x00000040 */ -#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, bit 6 */ +#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, pin 6 */ #define GPIO_IDT_IDT7_Pos (7U) #define GPIO_IDT_IDT7_Msk (0x1U << GPIO_IDT_IDT7_Pos) /*!< 0x00000080 */ -#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, bit 7 */ +#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, pin 7 */ #define GPIO_IDT_IDT8_Pos (8U) #define GPIO_IDT_IDT8_Msk (0x1U << GPIO_IDT_IDT8_Pos) /*!< 0x00000100 */ -#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, bit 8 */ +#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, pin 8 */ #define GPIO_IDT_IDT9_Pos (9U) #define GPIO_IDT_IDT9_Msk (0x1U << GPIO_IDT_IDT9_Pos) /*!< 0x00000200 */ -#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, bit 9 */ +#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, pin 9 */ #define GPIO_IDT_IDT10_Pos (10U) #define GPIO_IDT_IDT10_Msk (0x1U << GPIO_IDT_IDT10_Pos) /*!< 0x00000400 */ -#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, bit 10 */ +#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, pin 10 */ #define GPIO_IDT_IDT11_Pos (11U) #define GPIO_IDT_IDT11_Msk (0x1U << GPIO_IDT_IDT11_Pos) /*!< 0x00000800 */ -#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, bit 11 */ +#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, pin 11 */ #define GPIO_IDT_IDT12_Pos (12U) #define GPIO_IDT_IDT12_Msk (0x1U << GPIO_IDT_IDT12_Pos) /*!< 0x00001000 */ -#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, bit 12 */ +#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, pin 12 */ #define GPIO_IDT_IDT13_Pos (13U) #define GPIO_IDT_IDT13_Msk (0x1U << GPIO_IDT_IDT13_Pos) /*!< 0x00002000 */ -#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, bit 13 */ +#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, pin 13 */ #define GPIO_IDT_IDT14_Pos (14U) #define GPIO_IDT_IDT14_Msk (0x1U << GPIO_IDT_IDT14_Pos) /*!< 0x00004000 */ -#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, bit 14 */ +#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, pin 14 */ #define GPIO_IDT_IDT15_Pos (15U) #define GPIO_IDT_IDT15_Msk (0x1U << GPIO_IDT_IDT15_Pos) /*!< 0x00008000 */ -#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, bit 15 */ +#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, pin 15 */ /******************* Bit definition for GPIO_ODT register *******************/ #define GPIO_ODT_ODT0_Pos (0U) #define GPIO_ODT_ODT0_Msk (0x1U << GPIO_ODT_ODT0_Pos) /*!< 0x00000001 */ -#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, bit 0 */ +#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, pin 0 */ #define GPIO_ODT_ODT1_Pos (1U) #define GPIO_ODT_ODT1_Msk (0x1U << GPIO_ODT_ODT1_Pos) /*!< 0x00000002 */ -#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, bit 1 */ +#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, pin 1 */ #define GPIO_ODT_ODT2_Pos (2U) #define GPIO_ODT_ODT2_Msk (0x1U << GPIO_ODT_ODT2_Pos) /*!< 0x00000004 */ -#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, bit 2 */ +#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, pin 2 */ #define GPIO_ODT_ODT3_Pos (3U) #define GPIO_ODT_ODT3_Msk (0x1U << GPIO_ODT_ODT3_Pos) /*!< 0x00000008 */ -#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, bit 3 */ +#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, pin 3 */ #define GPIO_ODT_ODT4_Pos (4U) #define GPIO_ODT_ODT4_Msk (0x1U << GPIO_ODT_ODT4_Pos) /*!< 0x00000010 */ -#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, bit 4 */ +#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, pin 4 */ #define GPIO_ODT_ODT5_Pos (5U) #define GPIO_ODT_ODT5_Msk (0x1U << GPIO_ODT_ODT5_Pos) /*!< 0x00000020 */ -#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, bit 5 */ +#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, pin 5 */ #define GPIO_ODT_ODT6_Pos (6U) #define GPIO_ODT_ODT6_Msk (0x1U << GPIO_ODT_ODT6_Pos) /*!< 0x00000040 */ -#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, bit 6 */ +#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, pin 6 */ #define GPIO_ODT_ODT7_Pos (7U) #define GPIO_ODT_ODT7_Msk (0x1U << GPIO_ODT_ODT7_Pos) /*!< 0x00000080 */ -#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, bit 7 */ +#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, pin 7 */ #define GPIO_ODT_ODT8_Pos (8U) #define GPIO_ODT_ODT8_Msk (0x1U << GPIO_ODT_ODT8_Pos) /*!< 0x00000100 */ -#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, bit 8 */ +#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, pin 8 */ #define GPIO_ODT_ODT9_Pos (9U) #define GPIO_ODT_ODT9_Msk (0x1U << GPIO_ODT_ODT9_Pos) /*!< 0x00000200 */ -#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, bit 9 */ +#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, pin 9 */ #define GPIO_ODT_ODT10_Pos (10U) #define GPIO_ODT_ODT10_Msk (0x1U << GPIO_ODT_ODT10_Pos) /*!< 0x00000400 */ -#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, bit 10 */ +#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, pin 10 */ #define GPIO_ODT_ODT11_Pos (11U) #define GPIO_ODT_ODT11_Msk (0x1U << GPIO_ODT_ODT11_Pos) /*!< 0x00000800 */ -#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, bit 11 */ +#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, pin 11 */ #define GPIO_ODT_ODT12_Pos (12U) #define GPIO_ODT_ODT12_Msk (0x1U << GPIO_ODT_ODT12_Pos) /*!< 0x00001000 */ -#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, bit 12 */ +#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, pin 12 */ #define GPIO_ODT_ODT13_Pos (13U) #define GPIO_ODT_ODT13_Msk (0x1U << GPIO_ODT_ODT13_Pos) /*!< 0x00002000 */ -#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, bit 13 */ +#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, pin 13 */ #define GPIO_ODT_ODT14_Pos (14U) #define GPIO_ODT_ODT14_Msk (0x1U << GPIO_ODT_ODT14_Pos) /*!< 0x00004000 */ -#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, bit 14 */ +#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, pin 14 */ #define GPIO_ODT_ODT15_Pos (15U) #define GPIO_ODT_ODT15_Msk (0x1U << GPIO_ODT_ODT15_Pos) /*!< 0x00008000 */ -#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, bit 15 */ +#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, pin 15 */ /******************* Bit definition for GPIO_SCR register *******************/ #define GPIO_SCR_IOSB0_Pos (0U) #define GPIO_SCR_IOSB0_Msk (0x1U << GPIO_SCR_IOSB0_Pos) /*!< 0x00000001 */ -#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit 0 */ +#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit, pin 0 */ #define GPIO_SCR_IOSB1_Pos (1U) #define GPIO_SCR_IOSB1_Msk (0x1U << GPIO_SCR_IOSB1_Pos) /*!< 0x00000002 */ -#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit 1 */ +#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit, pin 1 */ #define GPIO_SCR_IOSB2_Pos (2U) #define GPIO_SCR_IOSB2_Msk (0x1U << GPIO_SCR_IOSB2_Pos) /*!< 0x00000004 */ -#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit 2 */ +#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit, pin 2 */ #define GPIO_SCR_IOSB3_Pos (3U) #define GPIO_SCR_IOSB3_Msk (0x1U << GPIO_SCR_IOSB3_Pos) /*!< 0x00000008 */ -#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit 3 */ +#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit, pin 3 */ #define GPIO_SCR_IOSB4_Pos (4U) #define GPIO_SCR_IOSB4_Msk (0x1U << GPIO_SCR_IOSB4_Pos) /*!< 0x00000010 */ -#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit 4 */ +#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit, pin 4 */ #define GPIO_SCR_IOSB5_Pos (5U) #define GPIO_SCR_IOSB5_Msk (0x1U << GPIO_SCR_IOSB5_Pos) /*!< 0x00000020 */ -#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit 5 */ +#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit, pin 5 */ #define GPIO_SCR_IOSB6_Pos (6U) #define GPIO_SCR_IOSB6_Msk (0x1U << GPIO_SCR_IOSB6_Pos) /*!< 0x00000040 */ -#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit 6 */ +#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit, pin 6 */ #define GPIO_SCR_IOSB7_Pos (7U) #define GPIO_SCR_IOSB7_Msk (0x1U << GPIO_SCR_IOSB7_Pos) /*!< 0x00000080 */ -#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit 7 */ +#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit, pin 7 */ #define GPIO_SCR_IOSB8_Pos (8U) #define GPIO_SCR_IOSB8_Msk (0x1U << GPIO_SCR_IOSB8_Pos) /*!< 0x00000100 */ -#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit 8 */ +#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit, pin 8 */ #define GPIO_SCR_IOSB9_Pos (9U) #define GPIO_SCR_IOSB9_Msk (0x1U << GPIO_SCR_IOSB9_Pos) /*!< 0x00000200 */ -#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit 9 */ +#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit, pin 9 */ #define GPIO_SCR_IOSB10_Pos (10U) #define GPIO_SCR_IOSB10_Msk (0x1U << GPIO_SCR_IOSB10_Pos) /*!< 0x00000400 */ -#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit 10 */ +#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit, pin 10 */ #define GPIO_SCR_IOSB11_Pos (11U) #define GPIO_SCR_IOSB11_Msk (0x1U << GPIO_SCR_IOSB11_Pos) /*!< 0x00000800 */ -#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit 11 */ +#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit, pin 11 */ #define GPIO_SCR_IOSB12_Pos (12U) #define GPIO_SCR_IOSB12_Msk (0x1U << GPIO_SCR_IOSB12_Pos) /*!< 0x00001000 */ -#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit 12 */ +#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit, pin 12 */ #define GPIO_SCR_IOSB13_Pos (13U) #define GPIO_SCR_IOSB13_Msk (0x1U << GPIO_SCR_IOSB13_Pos) /*!< 0x00002000 */ -#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit 13 */ +#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit, pin 13 */ #define GPIO_SCR_IOSB14_Pos (14U) #define GPIO_SCR_IOSB14_Msk (0x1U << GPIO_SCR_IOSB14_Pos) /*!< 0x00004000 */ -#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit 14 */ +#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit, pin 14 */ #define GPIO_SCR_IOSB15_Pos (15U) #define GPIO_SCR_IOSB15_Msk (0x1U << GPIO_SCR_IOSB15_Pos) /*!< 0x00008000 */ -#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit 15 */ +#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit, pin 15 */ #define GPIO_SCR_IOCB0_Pos (16U) #define GPIO_SCR_IOCB0_Msk (0x1U << GPIO_SCR_IOCB0_Pos) /*!< 0x00010000 */ -#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ #define GPIO_SCR_IOCB1_Pos (17U) #define GPIO_SCR_IOCB1_Msk (0x1U << GPIO_SCR_IOCB1_Pos) /*!< 0x00020000 */ -#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ #define GPIO_SCR_IOCB2_Pos (18U) #define GPIO_SCR_IOCB2_Msk (0x1U << GPIO_SCR_IOCB2_Pos) /*!< 0x00040000 */ -#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ #define GPIO_SCR_IOCB3_Pos (19U) #define GPIO_SCR_IOCB3_Msk (0x1U << GPIO_SCR_IOCB3_Pos) /*!< 0x00080000 */ -#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ #define GPIO_SCR_IOCB4_Pos (20U) #define GPIO_SCR_IOCB4_Msk (0x1U << GPIO_SCR_IOCB4_Pos) /*!< 0x00100000 */ -#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ #define GPIO_SCR_IOCB5_Pos (21U) #define GPIO_SCR_IOCB5_Msk (0x1U << GPIO_SCR_IOCB5_Pos) /*!< 0x00200000 */ -#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ #define GPIO_SCR_IOCB6_Pos (22U) #define GPIO_SCR_IOCB6_Msk (0x1U << GPIO_SCR_IOCB6_Pos) /*!< 0x00400000 */ -#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ #define GPIO_SCR_IOCB7_Pos (23U) #define GPIO_SCR_IOCB7_Msk (0x1U << GPIO_SCR_IOCB7_Pos) /*!< 0x00800000 */ -#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ #define GPIO_SCR_IOCB8_Pos (24U) #define GPIO_SCR_IOCB8_Msk (0x1U << GPIO_SCR_IOCB8_Pos) /*!< 0x01000000 */ -#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ #define GPIO_SCR_IOCB9_Pos (25U) #define GPIO_SCR_IOCB9_Msk (0x1U << GPIO_SCR_IOCB9_Pos) /*!< 0x02000000 */ -#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ #define GPIO_SCR_IOCB10_Pos (26U) #define GPIO_SCR_IOCB10_Msk (0x1U << GPIO_SCR_IOCB10_Pos) /*!< 0x04000000 */ -#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ #define GPIO_SCR_IOCB11_Pos (27U) #define GPIO_SCR_IOCB11_Msk (0x1U << GPIO_SCR_IOCB11_Pos) /*!< 0x08000000 */ -#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ #define GPIO_SCR_IOCB12_Pos (28U) #define GPIO_SCR_IOCB12_Msk (0x1U << GPIO_SCR_IOCB12_Pos) /*!< 0x10000000 */ -#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ #define GPIO_SCR_IOCB13_Pos (29U) #define GPIO_SCR_IOCB13_Msk (0x1U << GPIO_SCR_IOCB13_Pos) /*!< 0x20000000 */ -#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ #define GPIO_SCR_IOCB14_Pos (30U) #define GPIO_SCR_IOCB14_Msk (0x1U << GPIO_SCR_IOCB14_Pos) /*!< 0x40000000 */ -#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ #define GPIO_SCR_IOCB15_Pos (31U) #define GPIO_SCR_IOCB15_Msk (0x1U << GPIO_SCR_IOCB15_Pos) /*!< 0x80000000 */ -#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit 15 */ +#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ /******************* Bit definition for GPIO_CLR register *******************/ #define GPIO_CLR_IOCB0_Pos (0U) #define GPIO_CLR_IOCB0_Msk (0x1U << GPIO_CLR_IOCB0_Pos) /*!< 0x00000001 */ -#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ #define GPIO_CLR_IOCB1_Pos (1U) #define GPIO_CLR_IOCB1_Msk (0x1U << GPIO_CLR_IOCB1_Pos) /*!< 0x00000002 */ -#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ #define GPIO_CLR_IOCB2_Pos (2U) #define GPIO_CLR_IOCB2_Msk (0x1U << GPIO_CLR_IOCB2_Pos) /*!< 0x00000004 */ -#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ #define GPIO_CLR_IOCB3_Pos (3U) #define GPIO_CLR_IOCB3_Msk (0x1U << GPIO_CLR_IOCB3_Pos) /*!< 0x00000008 */ -#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ #define GPIO_CLR_IOCB4_Pos (4U) #define GPIO_CLR_IOCB4_Msk (0x1U << GPIO_CLR_IOCB4_Pos) /*!< 0x00000010 */ -#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ #define GPIO_CLR_IOCB5_Pos (5U) #define GPIO_CLR_IOCB5_Msk (0x1U << GPIO_CLR_IOCB5_Pos) /*!< 0x00000020 */ -#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ #define GPIO_CLR_IOCB6_Pos (6U) #define GPIO_CLR_IOCB6_Msk (0x1U << GPIO_CLR_IOCB6_Pos) /*!< 0x00000040 */ -#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ #define GPIO_CLR_IOCB7_Pos (7U) #define GPIO_CLR_IOCB7_Msk (0x1U << GPIO_CLR_IOCB7_Pos) /*!< 0x00000080 */ -#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ #define GPIO_CLR_IOCB8_Pos (8U) #define GPIO_CLR_IOCB8_Msk (0x1U << GPIO_CLR_IOCB8_Pos) /*!< 0x00000100 */ -#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ #define GPIO_CLR_IOCB9_Pos (9U) #define GPIO_CLR_IOCB9_Msk (0x1U << GPIO_CLR_IOCB9_Pos) /*!< 0x00000200 */ -#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ #define GPIO_CLR_IOCB10_Pos (10U) #define GPIO_CLR_IOCB10_Msk (0x1U << GPIO_CLR_IOCB10_Pos) /*!< 0x00000400 */ -#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ #define GPIO_CLR_IOCB11_Pos (11U) #define GPIO_CLR_IOCB11_Msk (0x1U << GPIO_CLR_IOCB11_Pos) /*!< 0x00000800 */ -#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ #define GPIO_CLR_IOCB12_Pos (12U) #define GPIO_CLR_IOCB12_Msk (0x1U << GPIO_CLR_IOCB12_Pos) /*!< 0x00001000 */ -#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ #define GPIO_CLR_IOCB13_Pos (13U) #define GPIO_CLR_IOCB13_Msk (0x1U << GPIO_CLR_IOCB13_Pos) /*!< 0x00002000 */ -#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ #define GPIO_CLR_IOCB14_Pos (14U) #define GPIO_CLR_IOCB14_Msk (0x1U << GPIO_CLR_IOCB14_Pos) /*!< 0x00004000 */ -#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ #define GPIO_CLR_IOCB15_Pos (15U) #define GPIO_CLR_IOCB15_Msk (0x1U << GPIO_CLR_IOCB15_Pos) /*!< 0x00008000 */ -#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit 15 */ +#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ /******************* Bit definition for GPIO_WPR register *******************/ #define GPIO_WPR_WPEN0_Pos (0U) #define GPIO_WPR_WPEN0_Msk (0x1U << GPIO_WPR_WPEN0_Pos) /*!< 0x00000001 */ -#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable bit 0 */ +#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable, pin 0 */ #define GPIO_WPR_WPEN1_Pos (1U) #define GPIO_WPR_WPEN1_Msk (0x1U << GPIO_WPR_WPEN1_Pos) /*!< 0x00000002 */ -#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable bit 1 */ +#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable, pin 1 */ #define GPIO_WPR_WPEN2_Pos (2U) #define GPIO_WPR_WPEN2_Msk (0x1U << GPIO_WPR_WPEN2_Pos) /*!< 0x00000004 */ -#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable bit 2 */ +#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable, pin 2 */ #define GPIO_WPR_WPEN3_Pos (3U) #define GPIO_WPR_WPEN3_Msk (0x1U << GPIO_WPR_WPEN3_Pos) /*!< 0x00000008 */ -#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable bit 3 */ +#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable, pin 3 */ #define GPIO_WPR_WPEN4_Pos (4U) #define GPIO_WPR_WPEN4_Msk (0x1U << GPIO_WPR_WPEN4_Pos) /*!< 0x00000010 */ -#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable bit 4 */ +#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable, pin 4 */ #define GPIO_WPR_WPEN5_Pos (5U) #define GPIO_WPR_WPEN5_Msk (0x1U << GPIO_WPR_WPEN5_Pos) /*!< 0x00000020 */ -#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable bit 5 */ +#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable, pin 5 */ #define GPIO_WPR_WPEN6_Pos (6U) #define GPIO_WPR_WPEN6_Msk (0x1U << GPIO_WPR_WPEN6_Pos) /*!< 0x00000040 */ -#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable bit 6 */ +#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable, pin 6 */ #define GPIO_WPR_WPEN7_Pos (7U) #define GPIO_WPR_WPEN7_Msk (0x1U << GPIO_WPR_WPEN7_Pos) /*!< 0x00000080 */ -#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable bit 7 */ +#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable, pin 7 */ #define GPIO_WPR_WPEN8_Pos (8U) #define GPIO_WPR_WPEN8_Msk (0x1U << GPIO_WPR_WPEN8_Pos) /*!< 0x00000100 */ -#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable bit 8 */ +#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable, pin 8 */ #define GPIO_WPR_WPEN9_Pos (9U) #define GPIO_WPR_WPEN9_Msk (0x1U << GPIO_WPR_WPEN9_Pos) /*!< 0x00000200 */ -#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable bit 9 */ +#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable, pin 9 */ #define GPIO_WPR_WPEN10_Pos (10U) #define GPIO_WPR_WPEN10_Msk (0x1U << GPIO_WPR_WPEN10_Pos) /*!< 0x00000400 */ -#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable bit 10 */ +#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable, pin 10 */ #define GPIO_WPR_WPEN11_Pos (11U) #define GPIO_WPR_WPEN11_Msk (0x1U << GPIO_WPR_WPEN11_Pos) /*!< 0x00000800 */ -#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable bit 11 */ +#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable, pin 11 */ #define GPIO_WPR_WPEN12_Pos (12U) #define GPIO_WPR_WPEN12_Msk (0x1U << GPIO_WPR_WPEN12_Pos) /*!< 0x00001000 */ -#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable bit 12 */ +#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable, pin 12 */ #define GPIO_WPR_WPEN13_Pos (13U) #define GPIO_WPR_WPEN13_Msk (0x1U << GPIO_WPR_WPEN13_Pos) /*!< 0x00002000 */ -#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable bit 13 */ +#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable, pin 13 */ #define GPIO_WPR_WPEN14_Pos (14U) #define GPIO_WPR_WPEN14_Msk (0x1U << GPIO_WPR_WPEN14_Pos) /*!< 0x00004000 */ -#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable bit 14 */ +#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable, pin 14 */ #define GPIO_WPR_WPEN15_Pos (15U) #define GPIO_WPR_WPEN15_Msk (0x1U << GPIO_WPR_WPEN15_Pos) /*!< 0x00008000 */ -#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable bit 15 */ +#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable, pin 15 */ #define GPIO_WPR_WPSEQ_Pos (16U) #define GPIO_WPR_WPSEQ_Msk (0x1U << GPIO_WPR_WPSEQ_Pos) /*!< 0x00010000 */ #define GPIO_WPR_WPSEQ GPIO_WPR_WPSEQ_Msk /*!< Write protect sequence */ @@ -2509,7 +2532,6 @@ typedef struct #define IOMUX_EVTOUT_EVOEN IOMUX_EVTOUT_EVOEN_Msk /*!< Event output enable */ /***************** Bit definition for IOMUX_REMAP register ******************/ -/*!< SPI1_MUX configuration */ #define IOMUX_REMAP_SPI1_MUX_Pos (0U) #define IOMUX_REMAP_SPI1_MUX_Msk (0x1U << IOMUX_REMAP_SPI1_MUX_Pos) /*!< 0x00000001 */ #define IOMUX_REMAP_SPI1_MUX IOMUX_REMAP_SPI1_MUX_Msk /*!< SPI1 IO multiplexing */ @@ -4053,18 +4075,21 @@ typedef struct #define DMA_CCTRL_MINCM_Msk (0x1U << DMA_CCTRL_MINCM_Pos) /*!< 0x00000080 */ #define DMA_CCTRL_MINCM DMA_CCTRL_MINCM_Msk /*!< Memory address increment mode */ +/*!< PWIDTH configuration */ #define DMA_CCTRL_PWIDTH_Pos (8U) #define DMA_CCTRL_PWIDTH_Msk (0x3U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000300 */ #define DMA_CCTRL_PWIDTH DMA_CCTRL_PWIDTH_Msk /*!< PWIDTH[1:0] bits (Peripheral data bit width) */ #define DMA_CCTRL_PWIDTH_0 (0x1U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000100 */ #define DMA_CCTRL_PWIDTH_1 (0x2U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000200 */ +/*!< MWIDTH configuration */ #define DMA_CCTRL_MWIDTH_Pos (10U) #define DMA_CCTRL_MWIDTH_Msk (0x3U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000C00 */ #define DMA_CCTRL_MWIDTH DMA_CCTRL_MWIDTH_Msk /*!< MWIDTH[1:0] bits (Memory data bit width) */ #define DMA_CCTRL_MWIDTH_0 (0x1U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000400 */ #define DMA_CCTRL_MWIDTH_1 (0x2U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000800 */ +/*!< CHPL configuration */ #define DMA_CCTRL_CHPL_Pos (12U) #define DMA_CCTRL_CHPL_Msk (0x3U << DMA_CCTRL_CHPL_Pos) /*!< 0x00003000 */ #define DMA_CCTRL_CHPL DMA_CCTRL_CHPL_Msk /*!< CHPL[1:0] bits(Channel priority level) */ @@ -4251,34 +4276,34 @@ typedef struct #define I2C_OADDR1_ADDR1_1_7 0x000000FEU /*!< Interface Address */ #define I2C_OADDR1_ADDR1_8_9 0x00000300U /*!< Interface Address */ -#define I2C_OADDR1_ADDR1_0_Pos (0U) +#define I2C_OADDR1_ADDR1_0_Pos (0U) #define I2C_OADDR1_ADDR1_0_Msk (0x1U << I2C_OADDR1_ADDR1_0_Pos) /*!< 0x00000001 */ #define I2C_OADDR1_ADDR1_0 I2C_OADDR1_ADDR1_0_Msk /*!< Bit 0 */ -#define I2C_OADDR1_ADDR1_1_Pos (1U) +#define I2C_OADDR1_ADDR1_1_Pos (1U) #define I2C_OADDR1_ADDR1_1_Msk (0x1U << I2C_OADDR1_ADDR1_1_Pos) /*!< 0x00000002 */ #define I2C_OADDR1_ADDR1_1 I2C_OADDR1_ADDR1_1_Msk /*!< Bit 1 */ -#define I2C_OADDR1_ADDR1_2_Pos (2U) +#define I2C_OADDR1_ADDR1_2_Pos (2U) #define I2C_OADDR1_ADDR1_2_Msk (0x1U << I2C_OADDR1_ADDR1_2_Pos) /*!< 0x00000004 */ #define I2C_OADDR1_ADDR1_2 I2C_OADDR1_ADDR1_2_Msk /*!< Bit 2 */ -#define I2C_OADDR1_ADDR1_3_Pos (3U) +#define I2C_OADDR1_ADDR1_3_Pos (3U) #define I2C_OADDR1_ADDR1_3_Msk (0x1U << I2C_OADDR1_ADDR1_3_Pos) /*!< 0x00000008 */ #define I2C_OADDR1_ADDR1_3 I2C_OADDR1_ADDR1_3_Msk /*!< Bit 3 */ -#define I2C_OADDR1_ADDR1_4_Pos (4U) +#define I2C_OADDR1_ADDR1_4_Pos (4U) #define I2C_OADDR1_ADDR1_4_Msk (0x1U << I2C_OADDR1_ADDR1_4_Pos) /*!< 0x00000010 */ #define I2C_OADDR1_ADDR1_4 I2C_OADDR1_ADDR1_4_Msk /*!< Bit 4 */ -#define I2C_OADDR1_ADDR1_5_Pos (5U) +#define I2C_OADDR1_ADDR1_5_Pos (5U) #define I2C_OADDR1_ADDR1_5_Msk (0x1U << I2C_OADDR1_ADDR1_5_Pos) /*!< 0x00000020 */ #define I2C_OADDR1_ADDR1_5 I2C_OADDR1_ADDR1_5_Msk /*!< Bit 5 */ -#define I2C_OADDR1_ADDR1_6_Pos (6U) +#define I2C_OADDR1_ADDR1_6_Pos (6U) #define I2C_OADDR1_ADDR1_6_Msk (0x1U << I2C_OADDR1_ADDR1_6_Pos) /*!< 0x00000040 */ #define I2C_OADDR1_ADDR1_6 I2C_OADDR1_ADDR1_6_Msk /*!< Bit 6 */ -#define I2C_OADDR1_ADDR1_7_Pos (7U) +#define I2C_OADDR1_ADDR1_7_Pos (7U) #define I2C_OADDR1_ADDR1_7_Msk (0x1U << I2C_OADDR1_ADDR1_7_Pos) /*!< 0x00000080 */ #define I2C_OADDR1_ADDR1_7 I2C_OADDR1_ADDR1_7_Msk /*!< Bit 7 */ -#define I2C_OADDR1_ADDR1_8_Pos (8U) +#define I2C_OADDR1_ADDR1_8_Pos (8U) #define I2C_OADDR1_ADDR1_8_Msk (0x1U << I2C_OADDR1_ADDR1_8_Pos) /*!< 0x00000100 */ #define I2C_OADDR1_ADDR1_8 I2C_OADDR1_ADDR1_8_Msk /*!< Bit 8 */ -#define I2C_OADDR1_ADDR1_9_Pos (9U) +#define I2C_OADDR1_ADDR1_9_Pos (9U) #define I2C_OADDR1_ADDR1_9_Msk (0x1U << I2C_OADDR1_ADDR1_9_Pos) /*!< 0x00000200 */ #define I2C_OADDR1_ADDR1_9 I2C_OADDR1_ADDR1_9_Msk /*!< Bit 9 */ @@ -4500,6 +4525,7 @@ typedef struct #define USART_CTRL2_CLKEN_Msk (0x1U << USART_CTRL2_CLKEN_Pos) /*!< 0x00000800 */ #define USART_CTRL2_CLKEN USART_CTRL2_CLKEN_Msk /*!< Clock enable */ +/*!< STOPBN configuration */ #define USART_CTRL2_STOPBN_Pos (12U) #define USART_CTRL2_STOPBN_Msk (0x3U << USART_CTRL2_STOPBN_Pos) /*!< 0x00003000 */ #define USART_CTRL2_STOPBN USART_CTRL2_STOPBN_Msk /*!< STOPBN[1:0] bits (STOP bit num) */ @@ -4546,6 +4572,7 @@ typedef struct #define USART_CTRL3_CTSCFIEN USART_CTRL3_CTSCFIEN_Msk /*!< CTSCF interrupt enable */ /****************** Bit definition for USART_GDIV register ******************/ +/*!< ISDIV configuration */ #define USART_GDIV_ISDIV_Pos (0U) #define USART_GDIV_ISDIV_Msk (0xFFU << USART_GDIV_ISDIV_Pos) /*!< 0x000000FF */ #define USART_GDIV_ISDIV USART_GDIV_ISDIV_Msk /*!< ISDIV[7:0] bits (IrDA/Smart Card division) */ @@ -4692,6 +4719,7 @@ typedef struct #define SPI_I2SCTRL_I2SCBN_Msk (0x1U << SPI_I2SCTRL_I2SCBN_Pos) /*!< 0x00000001 */ #define SPI_I2SCTRL_I2SCBN SPI_I2SCTRL_I2SCBN_Msk /*!< Channel length (I2S channel bit num) */ +/*!< I2SDBN configuration */ #define SPI_I2SCTRL_I2SDBN_Pos (1U) #define SPI_I2SCTRL_I2SDBN_Msk (0x3U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000006 */ #define SPI_I2SCTRL_I2SDBN SPI_I2SCTRL_I2SDBN_Msk /*!< I2SDBN[1:0] bits (I2S data bit num) */ @@ -4702,6 +4730,7 @@ typedef struct #define SPI_I2SCTRL_I2SCLKPOL_Msk (0x1U << SPI_I2SCTRL_I2SCLKPOL_Pos) /*!< 0x00000008 */ #define SPI_I2SCTRL_I2SCLKPOL SPI_I2SCTRL_I2SCLKPOL_Msk /*!< I2S clock polarity */ +/*!< STDSEL configuration */ #define SPI_I2SCTRL_STDSEL_Pos (4U) #define SPI_I2SCTRL_STDSEL_Msk (0x3U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000030 */ #define SPI_I2SCTRL_STDSEL SPI_I2SCTRL_STDSEL_Msk /*!< STDSEL[1:0] bits (I2S standard select) */ @@ -4712,6 +4741,7 @@ typedef struct #define SPI_I2SCTRL_PCMFSSEL_Msk (0x1U << SPI_I2SCTRL_PCMFSSEL_Pos) /*!< 0x00000080 */ #define SPI_I2SCTRL_PCMFSSEL SPI_I2SCTRL_PCMFSSEL_Msk /*!< PCM frame synchronization */ +/*!< OPERSEL configuration */ #define SPI_I2SCTRL_OPERSEL_Pos (8U) #define SPI_I2SCTRL_OPERSEL_Msk (0x3U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000300 */ #define SPI_I2SCTRL_OPERSEL SPI_I2SCTRL_OPERSEL_Msk /*!< OPERSEL[1:0] bits (I2S operation mode select) */ @@ -4742,6 +4772,7 @@ typedef struct /******************************************************************************/ /****************** Bit definition for WWDT_CTRL register *******************/ +/*!< CNT configuration */ #define WWDT_CTRL_CNT_Pos (0U) #define WWDT_CTRL_CNT_Msk (0x7FU << WWDT_CTRL_CNT_Pos) /*!< 0x0000007F */ #define WWDT_CTRL_CNT WWDT_CTRL_CNT_Msk /*!< CNT[6:0] bits (Down counter) */ @@ -4767,6 +4798,7 @@ typedef struct #define WWDT_CTRL_WWDTEN WWDT_CTRL_WWDTEN_Msk /*!< Window watchdog enable */ /******************* Bit definition for WWDT_CFG register *******************/ +/*!< WIN configuration */ #define WWDT_CFG_WIN_Pos (0U) #define WWDT_CFG_WIN_Msk (0x7FU << WWDT_CFG_WIN_Pos) /*!< 0x0000007F */ #define WWDT_CFG_WIN WWDT_CFG_WIN_Msk /*!< WIN[6:0] bits (Window value) */ @@ -4787,6 +4819,7 @@ typedef struct #define WWDT_CFG_WIN5 WWDT_CFG_WIN_5 #define WWDT_CFG_WIN6 WWDT_CFG_WIN_6 +/*!< DIV configuration */ #define WWDT_CFG_DIV_Pos (7U) #define WWDT_CFG_DIV_Msk (0x3U << WWDT_CFG_DIV_Pos) /*!< 0x00000180 */ #define WWDT_CFG_DIV WWDT_CFG_DIV_Msk /*!< DIV[1:0] bits (Clock division value) */ @@ -4818,6 +4851,7 @@ typedef struct #define WDT_CMD_CMD WDT_CMD_CMD_Msk /*!< Command register */ /******************* Bit definition for WDT_DIV register ********************/ +/*!< DIV configuration */ #define WDT_DIV_DIV_Pos (0U) #define WDT_DIV_DIV_Msk (0x7U << WDT_DIV_DIV_Pos) /*!< 0x00000007 */ #define WDT_DIV_DIV WDT_DIV_DIV_Msk /*!< DIV[2:0] (Clock division value) */ @@ -4845,6 +4879,7 @@ typedef struct /******************************************************************************/ /****************** Bit definition for ERTC_TIME register *******************/ +/*!< SU configuration */ #define ERTC_TIME_SU_Pos (0U) #define ERTC_TIME_SU_Msk (0xFU << ERTC_TIME_SU_Pos) /*!< 0x0000000F */ #define ERTC_TIME_SU ERTC_TIME_SU_Msk /*!< SU[3:0] (Second units) */ @@ -4853,6 +4888,7 @@ typedef struct #define ERTC_TIME_SU_2 (0x4U << ERTC_TIME_SU_Pos) /*!< 0x00000004 */ #define ERTC_TIME_SU_3 (0x8U << ERTC_TIME_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_TIME_ST_Pos (4U) #define ERTC_TIME_ST_Msk (0x7U << ERTC_TIME_ST_Pos) /*!< 0x00000070 */ #define ERTC_TIME_ST ERTC_TIME_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -4860,6 +4896,7 @@ typedef struct #define ERTC_TIME_ST_1 (0x2U << ERTC_TIME_ST_Pos) /*!< 0x00000020 */ #define ERTC_TIME_ST_2 (0x4U << ERTC_TIME_ST_Pos) /*!< 0x00000040 */ +/*!< MU configuration */ #define ERTC_TIME_MU_Pos (8U) #define ERTC_TIME_MU_Msk (0xFU << ERTC_TIME_MU_Pos) /*!< 0x00000F00 */ #define ERTC_TIME_MU ERTC_TIME_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -4868,6 +4905,7 @@ typedef struct #define ERTC_TIME_MU_2 (0x4U << ERTC_TIME_MU_Pos) /*!< 0x00000400 */ #define ERTC_TIME_MU_3 (0x8U << ERTC_TIME_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_TIME_MT_Pos (12U) #define ERTC_TIME_MT_Msk (0x7U << ERTC_TIME_MT_Pos) /*!< 0x00007000 */ #define ERTC_TIME_MT ERTC_TIME_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -4875,6 +4913,7 @@ typedef struct #define ERTC_TIME_MT_1 (0x2U << ERTC_TIME_MT_Pos) /*!< 0x00002000 */ #define ERTC_TIME_MT_2 (0x4U << ERTC_TIME_MT_Pos) /*!< 0x00004000 */ +/*!< HU configuration */ #define ERTC_TIME_HU_Pos (16U) #define ERTC_TIME_HU_Msk (0xFU << ERTC_TIME_HU_Pos) /*!< 0x000F0000 */ #define ERTC_TIME_HU ERTC_TIME_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -4883,6 +4922,7 @@ typedef struct #define ERTC_TIME_HU_2 (0x4U << ERTC_TIME_HU_Pos) /*!< 0x00040000 */ #define ERTC_TIME_HU_3 (0x8U << ERTC_TIME_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_TIME_HT_Pos (20U) #define ERTC_TIME_HT_Msk (0x3U << ERTC_TIME_HT_Pos) /*!< 0x00300000 */ #define ERTC_TIME_HT ERTC_TIME_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -4894,6 +4934,7 @@ typedef struct #define ERTC_TIME_AMPM ERTC_TIME_AMPM_Msk /*!< AM/PM */ /****************** Bit definition for ERTC_DATE register *******************/ +/*!< DU configuration */ #define ERTC_DATE_DU_Pos (0U) #define ERTC_DATE_DU_Msk (0xFU << ERTC_DATE_DU_Pos) /*!< 0x0000000F */ #define ERTC_DATE_DU ERTC_DATE_DU_Msk /*!< DU[3:0] (Date units) */ @@ -4902,12 +4943,14 @@ typedef struct #define ERTC_DATE_DU_2 (0x4U << ERTC_DATE_DU_Pos) /*!< 0x00000004 */ #define ERTC_DATE_DU_3 (0x8U << ERTC_DATE_DU_Pos) /*!< 0x00000008 */ +/*!< DT configuration */ #define ERTC_DATE_DT_Pos (4U) #define ERTC_DATE_DT_Msk (0x3U << ERTC_DATE_DT_Pos) /*!< 0x00300000 */ #define ERTC_DATE_DT ERTC_DATE_DT_Msk /*!< DT[1:0] (Date tens) */ #define ERTC_DATE_DT_0 (0x1U << ERTC_DATE_DT_Pos) /*!< 0x00000010 */ #define ERTC_DATE_DT_1 (0x2U << ERTC_DATE_DT_Pos) /*!< 0x00000020 */ +/*!< MU configuration */ #define ERTC_DATE_MU_Pos (8U) #define ERTC_DATE_MU_Msk (0xFU << ERTC_DATE_MU_Pos) /*!< 0x00000F00 */ #define ERTC_DATE_MU ERTC_DATE_MU_Msk /*!< MU[3:0] (Month units) */ @@ -4920,6 +4963,7 @@ typedef struct #define ERTC_DATE_MT_Msk (0x1U << ERTC_DATE_MT_Pos) /*!< 0x00001000 */ #define ERTC_DATE_MT ERTC_DATE_MT_Msk /*!< Month tens */ +/*!< WK configuration */ #define ERTC_DATE_WK_Pos (13U) #define ERTC_DATE_WK_Msk (0x7U << ERTC_DATE_WK_Pos) /*!< 0x0000E000 */ #define ERTC_DATE_WK ERTC_DATE_WK_Msk /*!< WK[2:0] (Week day) */ @@ -4927,6 +4971,7 @@ typedef struct #define ERTC_DATE_WK_1 (0x2U << ERTC_DATE_WK_Pos) /*!< 0x00004000 */ #define ERTC_DATE_WK_2 (0x4U << ERTC_DATE_WK_Pos) /*!< 0x00008000 */ +/*!< YU configuration */ #define ERTC_DATE_YU_Pos (16U) #define ERTC_DATE_YU_Msk (0xFU << ERTC_DATE_YU_Pos) /*!< 0x000F0000 */ #define ERTC_DATE_YU ERTC_DATE_YU_Msk /*!< YU[3:0] (Year units) */ @@ -4935,6 +4980,7 @@ typedef struct #define ERTC_DATE_YU_2 (0x4U << ERTC_DATE_YU_Pos) /*!< 0x00040000 */ #define ERTC_DATE_YU_3 (0x8U << ERTC_DATE_YU_Pos) /*!< 0x00080000 */ +/*!< YT configuration */ #define ERTC_DATE_YT_Pos (20U) #define ERTC_DATE_YT_Msk (0xFU << ERTC_DATE_YT_Pos) /*!< 0x00F00000 */ #define ERTC_DATE_YT ERTC_DATE_YT_Msk /*!< YT[3:0] (Year tens) */ @@ -4944,6 +4990,7 @@ typedef struct #define ERTC_DATE_YT_3 (0x8U << ERTC_DATE_YT_Pos) /*!< 0x00800000 */ /****************** Bit definition for ERTC_CTRL register *******************/ +/*!< WATCLK configuration */ #define ERTC_CTRL_WATCLK_Pos (0U) #define ERTC_CTRL_WATCLK_Msk (0x7U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000007 */ #define ERTC_CTRL_WATCLK ERTC_CTRL_WATCLK_Msk /*!< WATCLK[2:0] (Wakeup timer clock selection) */ @@ -5006,9 +5053,10 @@ typedef struct #define ERTC_CTRL_OUTP_Msk (0x1U << ERTC_CTRL_OUTP_Pos) /*!< 0x00100000 */ #define ERTC_CTRL_OUTP ERTC_CTRL_OUTP_Msk /*!< Output polarity */ +/*!< OUTSEL configuration */ #define ERTC_CTRL_OUTSEL_Pos (21U) #define ERTC_CTRL_OUTSEL_Msk (0x3U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00600000 */ -#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< WATCLK[1:0] (Output source selection) */ +#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< OUTSEL[1:0] (Output source selection) */ #define ERTC_CTRL_OUTSEL_0 (0x1U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00200000 */ #define ERTC_CTRL_OUTSEL_1 (0x2U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00400000 */ @@ -5077,6 +5125,7 @@ typedef struct #define ERTC_WAT_VAL ERTC_WAT_VAL_Msk /*!< Wakeup timer reload value */ /****************** Bit definition for ERTC_CCAL register *******************/ +/*!< CALVAL configuration */ #define ERTC_CCAL_CALVAL_Pos (0U) #define ERTC_CCAL_CALVAL_Msk (0x1FU << ERTC_CCAL_CALVAL_Pos) /*!< 0x0000001F */ #define ERTC_CCAL_CALVAL ERTC_CCAL_CALVAL_Msk /*!< CALVAL[4:0] (Calibration value) */ @@ -5091,6 +5140,7 @@ typedef struct #define ERTC_CCAL_CALDIR ERTC_CCAL_CALDIR_Msk /*!< Calibration direction */ /******************* Bit definition for ERTC_ALA register *******************/ +/*!< SU configuration */ #define ERTC_ALA_SU_Pos (0U) #define ERTC_ALA_SU_Msk (0xFU << ERTC_ALA_SU_Pos) /*!< 0x0000000F */ #define ERTC_ALA_SU ERTC_ALA_SU_Msk /*!< SU[3:0] (Second units) */ @@ -5099,6 +5149,7 @@ typedef struct #define ERTC_ALA_SU_2 (0x4U << ERTC_ALA_SU_Pos) /*!< 0x00000004 */ #define ERTC_ALA_SU_3 (0x8U << ERTC_ALA_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_ALA_ST_Pos (4U) #define ERTC_ALA_ST_Msk (0x7U << ERTC_ALA_ST_Pos) /*!< 0x00000070 */ #define ERTC_ALA_ST ERTC_ALA_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -5110,6 +5161,7 @@ typedef struct #define ERTC_ALA_MASK1_Msk (0x1U << ERTC_ALA_MASK1_Pos) /*!< 0x00000080 */ #define ERTC_ALA_MASK1 ERTC_ALA_MASK1_Msk /*!< Second mask */ +/*!< MU configuration */ #define ERTC_ALA_MU_Pos (8U) #define ERTC_ALA_MU_Msk (0xFU << ERTC_ALA_MU_Pos) /*!< 0x00000F00 */ #define ERTC_ALA_MU ERTC_ALA_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -5118,6 +5170,7 @@ typedef struct #define ERTC_ALA_MU_2 (0x4U << ERTC_ALA_MU_Pos) /*!< 0x00000400 */ #define ERTC_ALA_MU_3 (0x8U << ERTC_ALA_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_ALA_MT_Pos (12U) #define ERTC_ALA_MT_Msk (0x7U << ERTC_ALA_MT_Pos) /*!< 0x00007000 */ #define ERTC_ALA_MT ERTC_ALA_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -5129,6 +5182,7 @@ typedef struct #define ERTC_ALA_MASK2_Msk (0x1U << ERTC_ALA_MASK2_Pos) /*!< 0x00008000 */ #define ERTC_ALA_MASK2 ERTC_ALA_MASK2_Msk /*!< Minute mask */ +/*!< HU configuration */ #define ERTC_ALA_HU_Pos (16U) #define ERTC_ALA_HU_Msk (0xFU << ERTC_ALA_HU_Pos) /*!< 0x000F0000 */ #define ERTC_ALA_HU ERTC_ALA_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -5137,6 +5191,7 @@ typedef struct #define ERTC_ALA_HU_2 (0x4U << ERTC_ALA_HU_Pos) /*!< 0x00040000 */ #define ERTC_ALA_HU_3 (0x8U << ERTC_ALA_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_ALA_HT_Pos (20U) #define ERTC_ALA_HT_Msk (0x3U << ERTC_ALA_HT_Pos) /*!< 0x00300000 */ #define ERTC_ALA_HT ERTC_ALA_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -5150,6 +5205,7 @@ typedef struct #define ERTC_ALA_MASK3_Msk (0x1U << ERTC_ALA_MASK3_Pos) /*!< 0x00800000 */ #define ERTC_ALA_MASK3 ERTC_ALA_MASK3_Msk /*!< Hour mask */ +/*!< DU configuration */ #define ERTC_ALA_DU_Pos (24U) #define ERTC_ALA_DU_Msk (0xFU << ERTC_ALA_DU_Pos) /*!< 0x0F000000 */ #define ERTC_ALA_DU ERTC_ALA_DU_Msk /*!< DU[3:0] (Date/week day units) */ @@ -5158,6 +5214,7 @@ typedef struct #define ERTC_ALA_DU_2 (0x4U << ERTC_ALA_DU_Pos) /*!< 0x04000000 */ #define ERTC_ALA_DU_3 (0x8U << ERTC_ALA_DU_Pos) /*!< 0x08000000 */ +/*!< DT configuration */ #define ERTC_ALA_DT_Pos (28U) #define ERTC_ALA_DT_Msk (0x3U << ERTC_ALA_DT_Pos) /*!< 0x30000000 */ #define ERTC_ALA_DT ERTC_ALA_DT_Msk /*!< DT[1:0] (Date/week day tens) */ @@ -5172,6 +5229,7 @@ typedef struct #define ERTC_ALA_MASK4 ERTC_ALA_MASK4_Msk /*!< Date/week day mask */ /******************* Bit definition for ERTC_ALB register *******************/ +/*!< SU configuration */ #define ERTC_ALB_SU_Pos (0U) #define ERTC_ALB_SU_Msk (0xFU << ERTC_ALB_SU_Pos) /*!< 0x0000000F */ #define ERTC_ALB_SU ERTC_ALB_SU_Msk /*!< SU[3:0] (Second units) */ @@ -5180,6 +5238,7 @@ typedef struct #define ERTC_ALB_SU_2 (0x4U << ERTC_ALB_SU_Pos) /*!< 0x00000004 */ #define ERTC_ALB_SU_3 (0x8U << ERTC_ALB_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_ALB_ST_Pos (4U) #define ERTC_ALB_ST_Msk (0x7U << ERTC_ALB_ST_Pos) /*!< 0x00000070 */ #define ERTC_ALB_ST ERTC_ALB_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -5191,6 +5250,7 @@ typedef struct #define ERTC_ALB_MASK1_Msk (0x1U << ERTC_ALB_MASK1_Pos) /*!< 0x00000080 */ #define ERTC_ALB_MASK1 ERTC_ALB_MASK1_Msk /*!< Second mask */ +/*!< MU configuration */ #define ERTC_ALB_MU_Pos (8U) #define ERTC_ALB_MU_Msk (0xFU << ERTC_ALB_MU_Pos) /*!< 0x00000F00 */ #define ERTC_ALB_MU ERTC_ALB_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -5199,6 +5259,7 @@ typedef struct #define ERTC_ALB_MU_2 (0x4U << ERTC_ALB_MU_Pos) /*!< 0x00000400 */ #define ERTC_ALB_MU_3 (0x8U << ERTC_ALB_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_ALB_MT_Pos (12U) #define ERTC_ALB_MT_Msk (0x7U << ERTC_ALB_MT_Pos) /*!< 0x00007000 */ #define ERTC_ALB_MT ERTC_ALB_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -5210,6 +5271,7 @@ typedef struct #define ERTC_ALB_MASK2_Msk (0x1U << ERTC_ALB_MASK2_Pos) /*!< 0x00008000 */ #define ERTC_ALB_MASK2 ERTC_ALB_MASK2_Msk /*!< Minute mask */ +/*!< HU configuration */ #define ERTC_ALB_HU_Pos (16U) #define ERTC_ALB_HU_Msk (0xFU << ERTC_ALB_HU_Pos) /*!< 0x000F0000 */ #define ERTC_ALB_HU ERTC_ALB_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -5218,6 +5280,7 @@ typedef struct #define ERTC_ALB_HU_2 (0x4U << ERTC_ALB_HU_Pos) /*!< 0x00040000 */ #define ERTC_ALB_HU_3 (0x8U << ERTC_ALB_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_ALB_HT_Pos (20U) #define ERTC_ALB_HT_Msk (0x3U << ERTC_ALB_HT_Pos) /*!< 0x00300000 */ #define ERTC_ALB_HT ERTC_ALB_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -5231,6 +5294,7 @@ typedef struct #define ERTC_ALB_MASK3_Msk (0x1U << ERTC_ALB_MASK3_Pos) /*!< 0x00800000 */ #define ERTC_ALB_MASK3 ERTC_ALB_MASK3_Msk /*!< Hour mask */ +/*!< DU configuration */ #define ERTC_ALB_DU_Pos (24U) #define ERTC_ALB_DU_Msk (0xFU << ERTC_ALB_DU_Pos) /*!< 0x0F000000 */ #define ERTC_ALB_DU ERTC_ALB_DU_Msk /*!< DU[3:0] (Date/week day units) */ @@ -5239,6 +5303,7 @@ typedef struct #define ERTC_ALB_DU_2 (0x4U << ERTC_ALB_DU_Pos) /*!< 0x04000000 */ #define ERTC_ALB_DU_3 (0x8U << ERTC_ALB_DU_Pos) /*!< 0x08000000 */ +/*!< DT configuration */ #define ERTC_ALB_DT_Pos (28U) #define ERTC_ALB_DT_Msk (0x3U << ERTC_ALB_DT_Pos) /*!< 0x30000000 */ #define ERTC_ALB_DT ERTC_ALB_DT_Msk /*!< DT[1:0] (Date/week day tens) */ @@ -5271,6 +5336,7 @@ typedef struct #define ERTC_TADJ_ADD1S ERTC_TADJ_ADD1S_Msk /*!< Add 1 second */ /****************** Bit definition for ERTC_TSTM register *******************/ +/*!< SU configuration */ #define ERTC_TSTM_SU_Pos (0U) #define ERTC_TSTM_SU_Msk (0xFU << ERTC_TSTM_SU_Pos) /*!< 0x0000000F */ #define ERTC_TSTM_SU ERTC_TSTM_SU_Msk /*!< SU[3:0] (Second units) */ @@ -5279,6 +5345,7 @@ typedef struct #define ERTC_TSTM_SU_2 (0x4U << ERTC_TSTM_SU_Pos) /*!< 0x00000004 */ #define ERTC_TSTM_SU_3 (0x8U << ERTC_TSTM_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_TSTM_ST_Pos (4U) #define ERTC_TSTM_ST_Msk (0x7U << ERTC_TSTM_ST_Pos) /*!< 0x00000070 */ #define ERTC_TSTM_ST ERTC_TSTM_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -5286,6 +5353,7 @@ typedef struct #define ERTC_TSTM_ST_1 (0x2U << ERTC_TSTM_ST_Pos) /*!< 0x00000020 */ #define ERTC_TSTM_ST_2 (0x4U << ERTC_TSTM_ST_Pos) /*!< 0x00000040 */ +/*!< MU configuration */ #define ERTC_TSTM_MU_Pos (8U) #define ERTC_TSTM_MU_Msk (0xFU << ERTC_TSTM_MU_Pos) /*!< 0x00000F00 */ #define ERTC_TSTM_MU ERTC_TSTM_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -5294,6 +5362,7 @@ typedef struct #define ERTC_TSTM_MU_2 (0x4U << ERTC_TSTM_MU_Pos) /*!< 0x00000400 */ #define ERTC_TSTM_MU_3 (0x8U << ERTC_TSTM_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_TSTM_MT_Pos (12U) #define ERTC_TSTM_MT_Msk (0x7U << ERTC_TSTM_MT_Pos) /*!< 0x00007000 */ #define ERTC_TSTM_MT ERTC_TSTM_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -5301,6 +5370,7 @@ typedef struct #define ERTC_TSTM_MT_1 (0x2U << ERTC_TSTM_MT_Pos) /*!< 0x00002000 */ #define ERTC_TSTM_MT_2 (0x4U << ERTC_TSTM_MT_Pos) /*!< 0x00004000 */ +/*!< HU configuration */ #define ERTC_TSTM_HU_Pos (16U) #define ERTC_TSTM_HU_Msk (0xFU << ERTC_TSTM_HU_Pos) /*!< 0x000F0000 */ #define ERTC_TSTM_HU ERTC_TSTM_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -5309,6 +5379,7 @@ typedef struct #define ERTC_TSTM_HU_2 (0x4U << ERTC_TSTM_HU_Pos) /*!< 0x00040000 */ #define ERTC_TSTM_HU_3 (0x8U << ERTC_TSTM_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_TSTM_HT_Pos (20U) #define ERTC_TSTM_HT_Msk (0x3U << ERTC_TSTM_HT_Pos) /*!< 0x00300000 */ #define ERTC_TSTM_HT ERTC_TSTM_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -5320,6 +5391,7 @@ typedef struct #define ERTC_TSTM_AMPM ERTC_TSTM_AMPM_Msk /*!< AM/PM */ /****************** Bit definition for ERTC_TSDT register *******************/ +/*!< DU configuration */ #define ERTC_TSDT_DU_Pos (0U) #define ERTC_TSDT_DU_Msk (0xFU << ERTC_TSDT_DU_Pos) /*!< 0x0000000F */ #define ERTC_TSDT_DU ERTC_TSDT_DU_Msk /*!< DU[3:0] (Date units) */ @@ -5328,12 +5400,14 @@ typedef struct #define ERTC_TSDT_DU_2 (0x4U << ERTC_TSDT_DU_Pos) /*!< 0x00000004 */ #define ERTC_TSDT_DU_3 (0x8U << ERTC_TSDT_DU_Pos) /*!< 0x00000008 */ +/*!< DT configuration */ #define ERTC_TSDT_DT_Pos (4U) #define ERTC_TSDT_DT_Msk (0x3U << ERTC_TSDT_DT_Pos) /*!< 0x00000030 */ #define ERTC_TSDT_DT ERTC_TSDT_DT_Msk /*!< DT[1:0] (Date tens) */ #define ERTC_TSDT_DT_0 (0x1U << ERTC_TSDT_DT_Pos) /*!< 0x00000010 */ #define ERTC_TSDT_DT_1 (0x2U << ERTC_TSDT_DT_Pos) /*!< 0x00000020 */ +/*!< MU configuration */ #define ERTC_TSDT_MU_Pos (8U) #define ERTC_TSDT_MU_Msk (0xFU << ERTC_TSDT_MU_Pos) /*!< 0x00000F00 */ #define ERTC_TSDT_MU ERTC_TSDT_MU_Msk /*!< MU[3:0] (Month units) */ @@ -5346,6 +5420,7 @@ typedef struct #define ERTC_TSDT_MT_Msk (0x1U << ERTC_TSDT_MT_Pos) /*!< 0x00001000 */ #define ERTC_TSDT_MT ERTC_TSDT_MT_Msk /*!< Month tens */ +/*!< WK configuration */ #define ERTC_TSDT_WK_Pos (13U) #define ERTC_TSDT_WK_Msk (0x7U << ERTC_TSDT_WK_Pos) /*!< 0x0000E000 */ #define ERTC_TSDT_WK ERTC_TSDT_WK_Msk /*!< WK[2:0] (Week day) */ @@ -5386,6 +5461,7 @@ typedef struct #define ERTC_TAMP_TPTSEN_Msk (0x1U << ERTC_TAMP_TPTSEN_Pos) /*!< 0x00000080 */ #define ERTC_TAMP_TPTSEN ERTC_TAMP_TPTSEN_Msk /*!< Tamper detection timestamp enable */ +/*!< TPFREQ configuration */ #define ERTC_TAMP_TPFREQ_Pos (8U) #define ERTC_TAMP_TPFREQ_Msk (0x7U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000700 */ #define ERTC_TAMP_TPFREQ ERTC_TAMP_TPFREQ_Msk /*!< TPFREQ[2:0] (Tamper detection frequency) */ @@ -5393,12 +5469,14 @@ typedef struct #define ERTC_TAMP_TPFREQ_1 (0x2U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000200 */ #define ERTC_TAMP_TPFREQ_2 (0x4U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000400 */ +/*!< TPFLT configuration */ #define ERTC_TAMP_TPFLT_Pos (11U) #define ERTC_TAMP_TPFLT_Msk (0x3U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001800 */ #define ERTC_TAMP_TPFLT ERTC_TAMP_TPFLT_Msk /*!< TPFLT[1:0] (Tamper detection filter time) */ #define ERTC_TAMP_TPFLT_0 (0x1U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00000800 */ #define ERTC_TAMP_TPFLT_1 (0x2U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001000 */ +/*!< TPPR configuration */ #define ERTC_TAMP_TPPR_Pos (13U) #define ERTC_TAMP_TPPR_Msk (0x3U << ERTC_TAMP_TPPR_Pos) /*!< 0x00006000 */ #define ERTC_TAMP_TPPR ERTC_TAMP_TPPR_Msk /*!< TPPR[1:0] (Tamper detection pre-charge time) */ @@ -5417,9 +5495,10 @@ typedef struct #define ERTC_ALASBS_SBS_Msk (0x7FFFU << ERTC_ALASBS_SBS_Pos) /*!< 0x00007FFF */ #define ERTC_ALASBS_SBS ERTC_ALASBS_SBS_Msk /*!< Sub-second value */ +/*!< SBSMSK configuration */ #define ERTC_ALASBS_SBSMSK_Pos (24U) #define ERTC_ALASBS_SBSMSK_Msk (0xFU << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x0F000000 */ -#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ #define ERTC_ALASBS_SBSMSK_0 (0x1U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x01000000 */ #define ERTC_ALASBS_SBSMSK_1 (0x2U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x02000000 */ #define ERTC_ALASBS_SBSMSK_2 (0x4U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x04000000 */ @@ -5430,9 +5509,10 @@ typedef struct #define ERTC_ALBSBS_SBS_Msk (0x7FFFU << ERTC_ALBSBS_SBS_Pos) /*!< 0x00007FFF */ #define ERTC_ALBSBS_SBS ERTC_ALBSBS_SBS_Msk /*!< Sub-second value */ +/*!< SBSMSK configuration */ #define ERTC_ALBSBS_SBSMSK_Pos (24U) #define ERTC_ALBSBS_SBSMSK_Msk (0xFU << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x0F000000 */ -#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ #define ERTC_ALBSBS_SBSMSK_0 (0x1U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x01000000 */ #define ERTC_ALBSBS_SBSMSK_1 (0x2U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x02000000 */ #define ERTC_ALBSBS_SBSMSK_2 (0x4U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x04000000 */ @@ -5569,6 +5649,7 @@ typedef struct #define ADC_STS_PCCE (ADC_STS_PCCC) /****************** Bit definition for ADC_CTRL1 register *******************/ +/*!< VMCSEL configuration */ #define ADC_CTRL1_VMCSEL_Pos (0U) #define ADC_CTRL1_VMCSEL_Msk (0x1FU << ADC_CTRL1_VMCSEL_Pos) /*!< 0x0000001F */ #define ADC_CTRL1_VMCSEL ADC_CTRL1_VMCSEL_Msk /*!< VMCSEL[4:0] bits (Voltage monitoring channel select) */ @@ -5603,6 +5684,7 @@ typedef struct #define ADC_CTRL1_PCPEN_Msk (0x1U << ADC_CTRL1_PCPEN_Pos) /*!< 0x00001000 */ #define ADC_CTRL1_PCPEN ADC_CTRL1_PCPEN_Msk /*!< Partitioned mode enable on preempted channels */ +/*!< OCPCNT configuration */ #define ADC_CTRL1_OCPCNT_Pos (13U) #define ADC_CTRL1_OCPCNT_Msk (0x7U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x0000E000 */ #define ADC_CTRL1_OCPCNT ADC_CTRL1_OCPCNT_Msk /*!< OCPCNT[2:0] bits (Partitioned mode conversion count of ordinary channels) */ @@ -5627,7 +5709,7 @@ typedef struct #define ADC_CTRL2_ADCEN ADC_CTRL2_ADCEN_Msk /*!< A/D converter enable */ #define ADC_CTRL2_RPEN_Pos (1U) #define ADC_CTRL2_RPEN_Msk (0x1U << ADC_CTRL2_RPEN_Pos) /*!< 0x00000002 */ -#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repition mode enable */ +#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repetition mode enable */ #define ADC_CTRL2_ADCAL_Pos (2U) #define ADC_CTRL2_ADCAL_Msk (0x1U << ADC_CTRL2_ADCAL_Pos) /*!< 0x00000004 */ #define ADC_CTRL2_ADCAL ADC_CTRL2_ADCAL_Msk /*!< A/D calibration */ @@ -5675,6 +5757,7 @@ typedef struct #define ADC_CTRL2_ITSRVEN ADC_CTRL2_ITSRVEN_Msk /*!< Internal temperature sensor and VINTRV enable */ /******************* Bit definition for ADC_SPT1 register *******************/ +/*!< CSPT10 configuration */ #define ADC_SPT1_CSPT10_Pos (0U) #define ADC_SPT1_CSPT10_Msk (0x7U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000007 */ #define ADC_SPT1_CSPT10 ADC_SPT1_CSPT10_Msk /*!< CSPT10[2:0] bits (Sample time selection of channel ADC_IN10) */ @@ -5682,6 +5765,7 @@ typedef struct #define ADC_SPT1_CSPT10_1 (0x2U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000002 */ #define ADC_SPT1_CSPT10_2 (0x4U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000004 */ +/*!< CSPT11 configuration */ #define ADC_SPT1_CSPT11_Pos (3U) #define ADC_SPT1_CSPT11_Msk (0x7U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000038 */ #define ADC_SPT1_CSPT11 ADC_SPT1_CSPT11_Msk /*!< CSPT11[2:0] bits (Sample time selection of channel ADC_IN11) */ @@ -5689,6 +5773,7 @@ typedef struct #define ADC_SPT1_CSPT11_1 (0x2U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000010 */ #define ADC_SPT1_CSPT11_2 (0x4U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000020 */ +/*!< CSPT12 configuration */ #define ADC_SPT1_CSPT12_Pos (6U) #define ADC_SPT1_CSPT12_Msk (0x7U << ADC_SPT1_CSPT12_Pos) /*!< 0x000001C0 */ #define ADC_SPT1_CSPT12 ADC_SPT1_CSPT12_Msk /*!< CSPT12[2:0] bits (Sample time selection of channel ADC_IN12) */ @@ -5696,6 +5781,7 @@ typedef struct #define ADC_SPT1_CSPT12_1 (0x2U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000080 */ #define ADC_SPT1_CSPT12_2 (0x4U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000100 */ +/*!< CSPT13 configuration */ #define ADC_SPT1_CSPT13_Pos (9U) #define ADC_SPT1_CSPT13_Msk (0x7U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000E00 */ #define ADC_SPT1_CSPT13 ADC_SPT1_CSPT13_Msk /*!< CSPT13[2:0] bits (Sample time selection of channel ADC_IN13) */ @@ -5703,6 +5789,7 @@ typedef struct #define ADC_SPT1_CSPT13_1 (0x2U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000400 */ #define ADC_SPT1_CSPT13_2 (0x4U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000800 */ +/*!< CSPT14 configuration */ #define ADC_SPT1_CSPT14_Pos (12U) #define ADC_SPT1_CSPT14_Msk (0x7U << ADC_SPT1_CSPT14_Pos) /*!< 0x00007000 */ #define ADC_SPT1_CSPT14 ADC_SPT1_CSPT14_Msk /*!< CSPT14[2:0] bits (Sample time selection of channel ADC_IN14) */ @@ -5710,6 +5797,7 @@ typedef struct #define ADC_SPT1_CSPT14_1 (0x2U << ADC_SPT1_CSPT14_Pos) /*!< 0x00002000 */ #define ADC_SPT1_CSPT14_2 (0x4U << ADC_SPT1_CSPT14_Pos) /*!< 0x00004000 */ +/*!< CSPT15 configuration */ #define ADC_SPT1_CSPT15_Pos (15U) #define ADC_SPT1_CSPT15_Msk (0x7U << ADC_SPT1_CSPT15_Pos) /*!< 0x00038000 */ #define ADC_SPT1_CSPT15 ADC_SPT1_CSPT15_Msk /*!< CSPT15[2:0] bits (Sample time selection of channel ADC_IN15) */ @@ -5717,6 +5805,7 @@ typedef struct #define ADC_SPT1_CSPT15_1 (0x2U << ADC_SPT1_CSPT15_Pos) /*!< 0x00010000 */ #define ADC_SPT1_CSPT15_2 (0x4U << ADC_SPT1_CSPT15_Pos) /*!< 0x00020000 */ +/*!< CSPT16 configuration */ #define ADC_SPT1_CSPT16_Pos (18U) #define ADC_SPT1_CSPT16_Msk (0x7U << ADC_SPT1_CSPT16_Pos) /*!< 0x001C0000 */ #define ADC_SPT1_CSPT16 ADC_SPT1_CSPT16_Msk /*!< CSPT16[2:0] bits (Sample time selection of channel ADC_IN16) */ @@ -5724,6 +5813,7 @@ typedef struct #define ADC_SPT1_CSPT16_1 (0x2U << ADC_SPT1_CSPT16_Pos) /*!< 0x00080000 */ #define ADC_SPT1_CSPT16_2 (0x4U << ADC_SPT1_CSPT16_Pos) /*!< 0x00100000 */ +/*!< CSPT17 configuration */ #define ADC_SPT1_CSPT17_Pos (21U) #define ADC_SPT1_CSPT17_Msk (0x7U << ADC_SPT1_CSPT17_Pos) /*!< 0x00E00000 */ #define ADC_SPT1_CSPT17 ADC_SPT1_CSPT17_Msk /*!< CSPT17[2:0] bits (Sample time selection of channel ADC_IN17) */ @@ -5732,6 +5822,7 @@ typedef struct #define ADC_SPT1_CSPT17_2 (0x4U << ADC_SPT1_CSPT17_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_SPT2 register *******************/ +/*!< CSPT0 configuration */ #define ADC_SPT2_CSPT0_Pos (0U) #define ADC_SPT2_CSPT0_Msk (0x7U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000007 */ #define ADC_SPT2_CSPT0 ADC_SPT2_CSPT0_Msk /*!< CSPT0[2:0] bits (Sample time selection of channel ADC_IN0) */ @@ -5739,6 +5830,7 @@ typedef struct #define ADC_SPT2_CSPT0_1 (0x2U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000002 */ #define ADC_SPT2_CSPT0_2 (0x4U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000004 */ +/*!< CSPT1 configuration */ #define ADC_SPT2_CSPT1_Pos (3U) #define ADC_SPT2_CSPT1_Msk (0x7U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000038 */ #define ADC_SPT2_CSPT1 ADC_SPT2_CSPT1_Msk /*!< CSPT1[2:0] bits (Sample time selection of channel ADC_IN1) */ @@ -5746,6 +5838,7 @@ typedef struct #define ADC_SPT2_CSPT1_1 (0x2U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000010 */ #define ADC_SPT2_CSPT1_2 (0x4U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000020 */ +/*!< CSPT2 configuration */ #define ADC_SPT2_CSPT2_Pos (6U) #define ADC_SPT2_CSPT2_Msk (0x7U << ADC_SPT2_CSPT2_Pos) /*!< 0x000001C0 */ #define ADC_SPT2_CSPT2 ADC_SPT2_CSPT2_Msk /*!< CSPT2[2:0] bits (Sample time selection of channel ADC_IN2) */ @@ -5753,6 +5846,7 @@ typedef struct #define ADC_SPT2_CSPT2_1 (0x2U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000080 */ #define ADC_SPT2_CSPT2_2 (0x4U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000100 */ +/*!< CSPT3 configuration */ #define ADC_SPT2_CSPT3_Pos (9U) #define ADC_SPT2_CSPT3_Msk (0x7U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000E00 */ #define ADC_SPT2_CSPT3 ADC_SPT2_CSPT3_Msk /*!< CSPT3[2:0] bits (Sample time selection of channel ADC_IN3) */ @@ -5760,6 +5854,7 @@ typedef struct #define ADC_SPT2_CSPT3_1 (0x2U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000400 */ #define ADC_SPT2_CSPT3_2 (0x4U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000800 */ +/*!< CSPT4 configuration */ #define ADC_SPT2_CSPT4_Pos (12U) #define ADC_SPT2_CSPT4_Msk (0x7U << ADC_SPT2_CSPT4_Pos) /*!< 0x00007000 */ #define ADC_SPT2_CSPT4 ADC_SPT2_CSPT4_Msk /*!< CSPT4[2:0] bits (Sample time selection of channel ADC_IN4) */ @@ -5767,6 +5862,7 @@ typedef struct #define ADC_SPT2_CSPT4_1 (0x2U << ADC_SPT2_CSPT4_Pos) /*!< 0x00002000 */ #define ADC_SPT2_CSPT4_2 (0x4U << ADC_SPT2_CSPT4_Pos) /*!< 0x00004000 */ +/*!< CSPT5 configuration */ #define ADC_SPT2_CSPT5_Pos (15U) #define ADC_SPT2_CSPT5_Msk (0x7U << ADC_SPT2_CSPT5_Pos) /*!< 0x00038000 */ #define ADC_SPT2_CSPT5 ADC_SPT2_CSPT5_Msk /*!< CSPT5[2:0] bits (Sample time selection of channel ADC_IN5) */ @@ -5774,6 +5870,7 @@ typedef struct #define ADC_SPT2_CSPT5_1 (0x2U << ADC_SPT2_CSPT5_Pos) /*!< 0x00010000 */ #define ADC_SPT2_CSPT5_2 (0x4U << ADC_SPT2_CSPT5_Pos) /*!< 0x00020000 */ +/*!< CSPT6 configuration */ #define ADC_SPT2_CSPT6_Pos (18U) #define ADC_SPT2_CSPT6_Msk (0x7U << ADC_SPT2_CSPT6_Pos) /*!< 0x001C0000 */ #define ADC_SPT2_CSPT6 ADC_SPT2_CSPT6_Msk /*!< CSPT6[2:0] bits (Sample time selection of channel ADC_IN6) */ @@ -5781,6 +5878,7 @@ typedef struct #define ADC_SPT2_CSPT6_1 (0x2U << ADC_SPT2_CSPT6_Pos) /*!< 0x00080000 */ #define ADC_SPT2_CSPT6_2 (0x4U << ADC_SPT2_CSPT6_Pos) /*!< 0x00100000 */ +/*!< CSPT7 configuration */ #define ADC_SPT2_CSPT7_Pos (21U) #define ADC_SPT2_CSPT7_Msk (0x7U << ADC_SPT2_CSPT7_Pos) /*!< 0x00E00000 */ #define ADC_SPT2_CSPT7 ADC_SPT2_CSPT7_Msk /*!< CSPT7[2:0] bits (Sample time selection of channel ADC_IN7) */ @@ -5788,6 +5886,7 @@ typedef struct #define ADC_SPT2_CSPT7_1 (0x2U << ADC_SPT2_CSPT7_Pos) /*!< 0x00400000 */ #define ADC_SPT2_CSPT7_2 (0x4U << ADC_SPT2_CSPT7_Pos) /*!< 0x00800000 */ +/*!< CSPT8 configuration */ #define ADC_SPT2_CSPT8_Pos (24U) #define ADC_SPT2_CSPT8_Msk (0x7U << ADC_SPT2_CSPT8_Pos) /*!< 0x07000000 */ #define ADC_SPT2_CSPT8 ADC_SPT2_CSPT8_Msk /*!< CSPT8[2:0] bits (Sample time selection of channel ADC_IN8) */ @@ -5795,6 +5894,7 @@ typedef struct #define ADC_SPT2_CSPT8_1 (0x2U << ADC_SPT2_CSPT8_Pos) /*!< 0x02000000 */ #define ADC_SPT2_CSPT8_2 (0x4U << ADC_SPT2_CSPT8_Pos) /*!< 0x04000000 */ +/*!< CSPT9 configuration */ #define ADC_SPT2_CSPT9_Pos (27U) #define ADC_SPT2_CSPT9_Msk (0x7U << ADC_SPT2_CSPT9_Pos) /*!< 0x38000000 */ #define ADC_SPT2_CSPT9 ADC_SPT2_CSPT9_Msk /*!< CSPT9[2:0] bits (Sample time selection of channel ADC_IN9) */ @@ -5833,6 +5933,7 @@ typedef struct #define ADC_VMLB_VMLB ADC_VMLB_VMLB_Msk /*!< Voltage monitoring low boundary */ /******************* Bit definition for ADC_OSQ1 register *******************/ +/*!< OSN13 configuration */ #define ADC_OSQ1_OSN13_Pos (0U) #define ADC_OSQ1_OSN13_Msk (0x1FU << ADC_OSQ1_OSN13_Pos) /*!< 0x0000001F */ #define ADC_OSQ1_OSN13 ADC_OSQ1_OSN13_Msk /*!< OSN13[4:0] bits (Number of 13th conversion in ordinary sequence) */ @@ -5842,6 +5943,7 @@ typedef struct #define ADC_OSQ1_OSN13_3 (0x08U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000008 */ #define ADC_OSQ1_OSN13_4 (0x10U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000010 */ +/*!< OSN14 configuration */ #define ADC_OSQ1_OSN14_Pos (5U) #define ADC_OSQ1_OSN14_Msk (0x1FU << ADC_OSQ1_OSN14_Pos) /*!< 0x000003E0 */ #define ADC_OSQ1_OSN14 ADC_OSQ1_OSN14_Msk /*!< OSN14[4:0] bits (Number of 14th conversion in ordinary sequence) */ @@ -5851,6 +5953,7 @@ typedef struct #define ADC_OSQ1_OSN14_3 (0x08U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000100 */ #define ADC_OSQ1_OSN14_4 (0x10U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000200 */ +/*!< OSN15 configuration */ #define ADC_OSQ1_OSN15_Pos (10U) #define ADC_OSQ1_OSN15_Msk (0x1FU << ADC_OSQ1_OSN15_Pos) /*!< 0x00007C00 */ #define ADC_OSQ1_OSN15 ADC_OSQ1_OSN15_Msk /*!< OSN15[4:0] bits (Number of 15th conversion in ordinary sequence) */ @@ -5860,6 +5963,7 @@ typedef struct #define ADC_OSQ1_OSN15_3 (0x08U << ADC_OSQ1_OSN15_Pos) /*!< 0x00002000 */ #define ADC_OSQ1_OSN15_4 (0x10U << ADC_OSQ1_OSN15_Pos) /*!< 0x00004000 */ +/*!< OSN16 configuration */ #define ADC_OSQ1_OSN16_Pos (15U) #define ADC_OSQ1_OSN16_Msk (0x1FU << ADC_OSQ1_OSN16_Pos) /*!< 0x000F8000 */ #define ADC_OSQ1_OSN16 ADC_OSQ1_OSN16_Msk /*!< OSN16[4:0] bits (Number of 16th conversion in ordinary sequence) */ @@ -5869,6 +5973,7 @@ typedef struct #define ADC_OSQ1_OSN16_3 (0x08U << ADC_OSQ1_OSN16_Pos) /*!< 0x00040000 */ #define ADC_OSQ1_OSN16_4 (0x10U << ADC_OSQ1_OSN16_Pos) /*!< 0x00080000 */ +/*!< OCLEN configuration */ #define ADC_OSQ1_OCLEN_Pos (20U) #define ADC_OSQ1_OCLEN_Msk (0xFU << ADC_OSQ1_OCLEN_Pos) /*!< 0x00F00000 */ #define ADC_OSQ1_OCLEN ADC_OSQ1_OCLEN_Msk /*!< OCLEN[3:0] bits (Ordinary conversion sequence length) */ @@ -5878,6 +5983,7 @@ typedef struct #define ADC_OSQ1_OCLEN_3 (0x8U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_OSQ2 register *******************/ +/*!< OSN7 configuration */ #define ADC_OSQ2_OSN7_Pos (0U) #define ADC_OSQ2_OSN7_Msk (0x1FU << ADC_OSQ2_OSN7_Pos) /*!< 0x0000001F */ #define ADC_OSQ2_OSN7 ADC_OSQ2_OSN7_Msk /*!< OSN7[4:0] bits (Number of 7th conversion in ordinary sequence) */ @@ -5887,6 +5993,7 @@ typedef struct #define ADC_OSQ2_OSN7_3 (0x08U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000008 */ #define ADC_OSQ2_OSN7_4 (0x10U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000010 */ +/*!< OSN8 configuration */ #define ADC_OSQ2_OSN8_Pos (5U) #define ADC_OSQ2_OSN8_Msk (0x1FU << ADC_OSQ2_OSN8_Pos) /*!< 0x000003E0 */ #define ADC_OSQ2_OSN8 ADC_OSQ2_OSN8_Msk /*!< OSN8[4:0] bits (Number of 8th conversion in ordinary sequence) */ @@ -5896,6 +6003,7 @@ typedef struct #define ADC_OSQ2_OSN8_3 (0x08U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000100 */ #define ADC_OSQ2_OSN8_4 (0x10U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000200 */ +/*!< OSN9 configuration */ #define ADC_OSQ2_OSN9_Pos (10U) #define ADC_OSQ2_OSN9_Msk (0x1FU << ADC_OSQ2_OSN9_Pos) /*!< 0x00007C00 */ #define ADC_OSQ2_OSN9 ADC_OSQ2_OSN9_Msk /*!< OSN9[4:0] bits (Number of 9th conversion in ordinary sequence) */ @@ -5905,6 +6013,7 @@ typedef struct #define ADC_OSQ2_OSN9_3 (0x08U << ADC_OSQ2_OSN9_Pos) /*!< 0x00002000 */ #define ADC_OSQ2_OSN9_4 (0x10U << ADC_OSQ2_OSN9_Pos) /*!< 0x00004000 */ +/*!< OSN10 configuration */ #define ADC_OSQ2_OSN10_Pos (15U) #define ADC_OSQ2_OSN10_Msk (0x1FU << ADC_OSQ2_OSN10_Pos) /*!< 0x000F8000 */ #define ADC_OSQ2_OSN10 ADC_OSQ2_OSN10_Msk /*!< OSN10[4:0] bits (Number of 10th conversion in ordinary sequence) */ @@ -5914,6 +6023,7 @@ typedef struct #define ADC_OSQ2_OSN10_3 (0x08U << ADC_OSQ2_OSN10_Pos) /*!< 0x00040000 */ #define ADC_OSQ2_OSN10_4 (0x10U << ADC_OSQ2_OSN10_Pos) /*!< 0x00080000 */ +/*!< OSN11 configuration */ #define ADC_OSQ2_OSN11_Pos (20U) #define ADC_OSQ2_OSN11_Msk (0x1FU << ADC_OSQ2_OSN11_Pos) /*!< 0x01F00000 */ #define ADC_OSQ2_OSN11 ADC_OSQ2_OSN11_Msk /*!< OSN11[4:0] bits (Number of 11th conversion in ordinary sequence) */ @@ -5923,6 +6033,7 @@ typedef struct #define ADC_OSQ2_OSN11_3 (0x08U << ADC_OSQ2_OSN11_Pos) /*!< 0x00800000 */ #define ADC_OSQ2_OSN11_4 (0x10U << ADC_OSQ2_OSN11_Pos) /*!< 0x01000000 */ +/*!< OSN12 configuration */ #define ADC_OSQ2_OSN12_Pos (25U) #define ADC_OSQ2_OSN12_Msk (0x1FU << ADC_OSQ2_OSN12_Pos) /*!< 0x3E000000 */ #define ADC_OSQ2_OSN12 ADC_OSQ2_OSN12_Msk /*!< OSN12[4:0] bits (Number of 12th conversion in ordinary sequence) */ @@ -5933,6 +6044,7 @@ typedef struct #define ADC_OSQ2_OSN12_4 (0x10U << ADC_OSQ2_OSN12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_OSQ3 register *******************/ +/*!< OSN1 configuration */ #define ADC_OSQ3_OSN1_Pos (0U) #define ADC_OSQ3_OSN1_Msk (0x1FU << ADC_OSQ3_OSN1_Pos) /*!< 0x0000001F */ #define ADC_OSQ3_OSN1 ADC_OSQ3_OSN1_Msk /*!< OSN1[4:0] bits (Number of 1st conversion in ordinary sequence) */ @@ -5942,6 +6054,7 @@ typedef struct #define ADC_OSQ3_OSN1_3 (0x08U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000008 */ #define ADC_OSQ3_OSN1_4 (0x10U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000010 */ +/*!< OSN2 configuration */ #define ADC_OSQ3_OSN2_Pos (5U) #define ADC_OSQ3_OSN2_Msk (0x1FU << ADC_OSQ3_OSN2_Pos) /*!< 0x000003E0 */ #define ADC_OSQ3_OSN2 ADC_OSQ3_OSN2_Msk /*!< OSN2[4:0] bits (Number of 2nd conversion in ordinary sequence) */ @@ -5951,6 +6064,7 @@ typedef struct #define ADC_OSQ3_OSN2_3 (0x08U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000100 */ #define ADC_OSQ3_OSN2_4 (0x10U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000200 */ +/*!< OSN3 configuration */ #define ADC_OSQ3_OSN3_Pos (10U) #define ADC_OSQ3_OSN3_Msk (0x1FU << ADC_OSQ3_OSN3_Pos) /*!< 0x00007C00 */ #define ADC_OSQ3_OSN3 ADC_OSQ3_OSN3_Msk /*!< OSN3[4:0] bits (Number of 3rd conversion in ordinary sequence) */ @@ -5960,6 +6074,7 @@ typedef struct #define ADC_OSQ3_OSN3_3 (0x08U << ADC_OSQ3_OSN3_Pos) /*!< 0x00002000 */ #define ADC_OSQ3_OSN3_4 (0x10U << ADC_OSQ3_OSN3_Pos) /*!< 0x00004000 */ +/*!< OSN4 configuration */ #define ADC_OSQ3_OSN4_Pos (15U) #define ADC_OSQ3_OSN4_Msk (0x1FU << ADC_OSQ3_OSN4_Pos) /*!< 0x000F8000 */ #define ADC_OSQ3_OSN4 ADC_OSQ3_OSN4_Msk /*!< OSN4[4:0] bits (Number of 4th conversion in ordinary sequence) */ @@ -5969,6 +6084,7 @@ typedef struct #define ADC_OSQ3_OSN4_3 (0x08U << ADC_OSQ3_OSN4_Pos) /*!< 0x00040000 */ #define ADC_OSQ3_OSN4_4 (0x10U << ADC_OSQ3_OSN4_Pos) /*!< 0x00080000 */ +/*!< OSN5 configuration */ #define ADC_OSQ3_OSN5_Pos (20U) #define ADC_OSQ3_OSN5_Msk (0x1FU << ADC_OSQ3_OSN5_Pos) /*!< 0x01F00000 */ #define ADC_OSQ3_OSN5 ADC_OSQ3_OSN5_Msk /*!< OSN5[4:0] bits (Number of 5th conversion in ordinary sequence) */ @@ -5978,6 +6094,7 @@ typedef struct #define ADC_OSQ3_OSN5_3 (0x08U << ADC_OSQ3_OSN5_Pos) /*!< 0x00800000 */ #define ADC_OSQ3_OSN5_4 (0x10U << ADC_OSQ3_OSN5_Pos) /*!< 0x01000000 */ +/*!< OSN6 configuration */ #define ADC_OSQ3_OSN6_Pos (25U) #define ADC_OSQ3_OSN6_Msk (0x1FU << ADC_OSQ3_OSN6_Pos) /*!< 0x3E000000 */ #define ADC_OSQ3_OSN6 ADC_OSQ3_OSN6_Msk /*!< OSN6[4:0] bits (Number of 6th conversion in ordinary sequence) */ @@ -5988,6 +6105,7 @@ typedef struct #define ADC_OSQ3_OSN6_4 (0x10U << ADC_OSQ3_OSN6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_PSQ register ********************/ +/*!< PSN1 configuration */ #define ADC_PSQ_PSN1_Pos (0U) #define ADC_PSQ_PSN1_Msk (0x1FU << ADC_PSQ_PSN1_Pos) /*!< 0x0000001F */ #define ADC_PSQ_PSN1 ADC_PSQ_PSN1_Msk /*!< PSN1[4:0] bits (Number of 1st conversion in preempted sequence) */ @@ -5997,6 +6115,7 @@ typedef struct #define ADC_PSQ_PSN1_3 (0x08U << ADC_PSQ_PSN1_Pos) /*!< 0x00000008 */ #define ADC_PSQ_PSN1_4 (0x10U << ADC_PSQ_PSN1_Pos) /*!< 0x00000010 */ +/*!< PSN2 configuration */ #define ADC_PSQ_PSN2_Pos (5U) #define ADC_PSQ_PSN2_Msk (0x1FU << ADC_PSQ_PSN2_Pos) /*!< 0x000003E0 */ #define ADC_PSQ_PSN2 ADC_PSQ_PSN2_Msk /*!< PSN2[4:0] bits (Number of 2nd conversion in preempted sequence) */ @@ -6006,6 +6125,7 @@ typedef struct #define ADC_PSQ_PSN2_3 (0x08U << ADC_PSQ_PSN2_Pos) /*!< 0x00000100 */ #define ADC_PSQ_PSN2_4 (0x10U << ADC_PSQ_PSN2_Pos) /*!< 0x00000200 */ +/*!< PSN3 configuration */ #define ADC_PSQ_PSN3_Pos (10U) #define ADC_PSQ_PSN3_Msk (0x1FU << ADC_PSQ_PSN3_Pos) /*!< 0x00007C00 */ #define ADC_PSQ_PSN3 ADC_PSQ_PSN3_Msk /*!< PSN3[4:0] bits (Number of 3rd conversion in preempted sequence) */ @@ -6015,6 +6135,7 @@ typedef struct #define ADC_PSQ_PSN3_3 (0x08U << ADC_PSQ_PSN3_Pos) /*!< 0x00002000 */ #define ADC_PSQ_PSN3_4 (0x10U << ADC_PSQ_PSN3_Pos) /*!< 0x00004000 */ +/*!< PSN4 configuration */ #define ADC_PSQ_PSN4_Pos (15U) #define ADC_PSQ_PSN4_Msk (0x1FU << ADC_PSQ_PSN4_Pos) /*!< 0x000F8000 */ #define ADC_PSQ_PSN4 ADC_PSQ_PSN4_Msk /*!< PSN4[4:0] bits (Number of 4th conversion in preempted sequence) */ @@ -6024,6 +6145,7 @@ typedef struct #define ADC_PSQ_PSN4_3 (0x08U << ADC_PSQ_PSN4_Pos) /*!< 0x00040000 */ #define ADC_PSQ_PSN4_4 (0x10U << ADC_PSQ_PSN4_Pos) /*!< 0x00080000 */ +/*!< PCLEN configuration */ #define ADC_PSQ_PCLEN_Pos (20U) #define ADC_PSQ_PCLEN_Msk (0x3U << ADC_PSQ_PCLEN_Pos) /*!< 0x00300000 */ #define ADC_PSQ_PCLEN ADC_PSQ_PCLEN_Msk /*!< PCLEN[1:0] bits (Preempted conversion sequence length) */ @@ -6054,9 +6176,6 @@ typedef struct #define ADC_ODT_ODT_Pos (0U) #define ADC_ODT_ODT_Msk (0xFFFFU << ADC_ODT_ODT_Pos) /*!< 0x0000FFFF */ #define ADC_ODT_ODT ADC_ODT_ODT_Msk /*!< Conversion data of ordinary channel */ -#define ADC_ODT_ADC2ODT_Pos (16U) -#define ADC_ODT_ADC2ODT_Msk (0xFFFFU << ADC_ODT_ADC2ODT_Pos) /*!< 0xFFFF0000 */ -#define ADC_ODT_ADC2ODT ADC_ODT_ADC2ODT_Msk /*!< ADC2 conversion data of ordinary channel */ /******************************************************************************/ /* */ @@ -6176,6 +6295,7 @@ typedef struct #define CAN_TSTS_TMNR_Msk (0x3U << CAN_TSTS_TMNR_Pos) /*!< 0x03000000 */ #define CAN_TSTS_TMNR CAN_TSTS_TMNR_Msk /*!< TMNR[1:0] bits (Transmit mailbox number record) */ +/*!< TMEF congiguration */ #define CAN_TSTS_TMEF_Pos (26U) #define CAN_TSTS_TMEF_Msk (0x7U << CAN_TSTS_TMEF_Pos) /*!< 0x1C000000 */ #define CAN_TSTS_TMEF CAN_TSTS_TMEF_Msk /*!< TMEF[2:0] bits (Transmit mailbox empty flag) */ @@ -6189,6 +6309,7 @@ typedef struct #define CAN_TSTS_TM2EF_Msk (0x1U << CAN_TSTS_TM2EF_Pos) /*!< 0x10000000 */ #define CAN_TSTS_TM2EF CAN_TSTS_TM2EF_Msk /*!< Transmit mailbox 2 empty flag */ +/*!< TMLPF congiguration */ #define CAN_TSTS_TMLPF_Pos (29U) #define CAN_TSTS_TMLPF_Msk (0x7U << CAN_TSTS_TMLPF_Pos) /*!< 0xE0000000 */ #define CAN_TSTS_TMLPF CAN_TSTS_TMLPF_Msk /*!< TMLPF[2:0] bits (Transmit mailbox lowest priority flag) */ @@ -6285,6 +6406,7 @@ typedef struct #define CAN_ESTS_BOF_Msk (0x1U << CAN_ESTS_BOF_Pos) /*!< 0x00000004 */ #define CAN_ESTS_BOF CAN_ESTS_BOF_Msk /*!< Bus-off flag */ +/*!< ETR congiguration */ #define CAN_ESTS_ETR_Pos (4U) #define CAN_ESTS_ETR_Msk (0x7U << CAN_ESTS_ETR_Pos) /*!< 0x00000070 */ #define CAN_ESTS_ETR CAN_ESTS_ETR_Msk /*!< ETR[2:0] bits (Error type record) */ @@ -6304,6 +6426,7 @@ typedef struct #define CAN_BTMG_BRDIV_Msk (0xFFFU << CAN_BTMG_BRDIV_Pos) /*!< 0x00000FFF */ #define CAN_BTMG_BRDIV CAN_BTMG_BRDIV_Msk /*!< Baud rate division */ +/*!< BTS1 congiguration */ #define CAN_BTMG_BTS1_Pos (16U) #define CAN_BTMG_BTS1_Msk (0xFU << CAN_BTMG_BTS1_Pos) /*!< 0x000F0000 */ #define CAN_BTMG_BTS1 CAN_BTMG_BTS1_Msk /*!< BTS1[3:0] bits (Bit time segment 1) */ @@ -6312,6 +6435,7 @@ typedef struct #define CAN_BTMG_BTS1_2 (0x4U << CAN_BTMG_BTS1_Pos) /*!< 0x00040000 */ #define CAN_BTMG_BTS1_3 (0x8U << CAN_BTMG_BTS1_Pos) /*!< 0x00080000 */ +/*!< BTS2 congiguration */ #define CAN_BTMG_BTS2_Pos (20U) #define CAN_BTMG_BTS2_Msk (0x7U << CAN_BTMG_BTS2_Pos) /*!< 0x00700000 */ #define CAN_BTMG_BTS2 CAN_BTMG_BTS2_Msk /*!< BTS2[2:0] bits (Bit time segment 2) */ @@ -6319,6 +6443,7 @@ typedef struct #define CAN_BTMG_BTS2_1 (0x2U << CAN_BTMG_BTS2_Pos) /*!< 0x00200000 */ #define CAN_BTMG_BTS2_2 (0x4U << CAN_BTMG_BTS2_Pos) /*!< 0x00400000 */ +/*!< RSAW congiguration */ #define CAN_BTMG_RSAW_Pos (24U) #define CAN_BTMG_RSAW_Msk (0x3U << CAN_BTMG_RSAW_Pos) /*!< 0x03000000 */ #define CAN_BTMG_RSAW CAN_BTMG_RSAW_Msk /*!< RSAW[1:0] bits (Resynchronization width) */ @@ -9552,6 +9677,7 @@ typedef struct /******************************************************************************/ /***************** Bit definition for SDIO_PWRCTRL register *****************/ +/*!< PS congiguration */ #define SDIO_PWRCTRL_PS_Pos (0U) #define SDIO_PWRCTRL_PS_Msk (0x3U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000003 */ #define SDIO_PWRCTRL_PS SDIO_PWRCTRL_PS_Msk /*!< PS[1:0] bits (Power switch) */ @@ -9571,6 +9697,7 @@ typedef struct #define SDIO_CLKCTRL_BYPSEN_Msk (0x1U << SDIO_CLKCTRL_BYPSEN_Pos) /*!< 0x00000400 */ #define SDIO_CLKCTRL_BYPSEN SDIO_CLKCTRL_BYPSEN_Msk /*!< Clock divider bypass enable bit */ +/*!< BUSWS congiguration */ #define SDIO_CLKCTRL_BUSWS_Pos (11U) #define SDIO_CLKCTRL_BUSWS_Msk (0x3U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00001800 */ #define SDIO_CLKCTRL_BUSWS SDIO_CLKCTRL_BUSWS_Msk /*!< BUSWS[1:0] bits (Bus width selection) */ @@ -9594,6 +9721,7 @@ typedef struct #define SDIO_CMD_CMDIDX_Msk (0x3FU << SDIO_CMD_CMDIDX_Pos) /*!< 0x0000003F */ #define SDIO_CMD_CMDIDX SDIO_CMD_CMDIDX_Msk /*!< Command index */ +/*!< RSPWT congiguration */ #define SDIO_CMD_RSPWT_Pos (6U) #define SDIO_CMD_RSPWT_Msk (0x3U << SDIO_CMD_RSPWT_Pos) /*!< 0x000000C0 */ #define SDIO_CMD_RSPWT SDIO_CMD_RSPWT_Msk /*!< RSPWT[1:0] bits (Wait for response bits) */ @@ -9644,7 +9772,7 @@ typedef struct #define SDIO_DTTMR_TIMEOUT SDIO_DTTMR_TIMEOUT_Msk /*!< Data timeout period */ /****************** Bit definition for SDIO_DTLEN register ******************/ -#define SDIO_DTLEN_DTLEN_Pos (0U) +#define SDIO_DTLEN_DTLEN_Pos (0U) #define SDIO_DTLEN_DTLEN_Msk (0x1FFFFFFU << SDIO_DTLEN_DTLEN_Pos) /*!< 0x01FFFFFF */ #define SDIO_DTLEN_DTLEN SDIO_DTLEN_DTLEN_Msk /*!< Data length value */ @@ -9662,6 +9790,7 @@ typedef struct #define SDIO_DTCTRL_DMAEN_Msk (0x1U << SDIO_DTCTRL_DMAEN_Pos) /*!< 0x00000008 */ #define SDIO_DTCTRL_DMAEN SDIO_DTCTRL_DMAEN_Msk /*!< DMA enable bit */ +/*!< BLKSIZE congiguration */ #define SDIO_DTCTRL_BLKSIZE_Pos (4U) #define SDIO_DTCTRL_BLKSIZE_Msk (0xFU << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x000000F0 */ #define SDIO_DTCTRL_BLKSIZE SDIO_DTCTRL_BLKSIZE_Msk /*!< BLKSIZE[3:0] bits (Data block size) */ @@ -9895,6 +10024,7 @@ typedef struct #define CMP_CTRLSTS1_CMP1SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP1SSEL_Pos) /*!< 0x00000004 */ #define CMP_CTRLSTS1_CMP1SSEL CMP_CTRLSTS1_CMP1SSEL_Msk /*!< Comparator 1 speed selection */ +/*!< CMP1INVSEL congiguration */ #define CMP_CTRLSTS1_CMP1INVSEL_Pos (4U) #define CMP_CTRLSTS1_CMP1INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000070 */ #define CMP_CTRLSTS1_CMP1INVSEL CMP_CTRLSTS1_CMP1INVSEL_Msk /*!< CMP1INVSEL[2:0] bits (Comparator 1 inverting selection) */ @@ -9902,6 +10032,7 @@ typedef struct #define CMP_CTRLSTS1_CMP1INVSEL_1 (0x2U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000020 */ #define CMP_CTRLSTS1_CMP1INVSEL_2 (0x4U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000040 */ +/*!< CMP1TAG congiguration */ #define CMP_CTRLSTS1_CMP1TAG_Pos (8U) #define CMP_CTRLSTS1_CMP1TAG_Msk (0x7U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000700 */ #define CMP_CTRLSTS1_CMP1TAG CMP_CTRLSTS1_CMP1TAG_Msk /*!< CMP1TAG[2:0] bits (Comparator 1 output target) */ @@ -9913,6 +10044,7 @@ typedef struct #define CMP_CTRLSTS1_CMP1P_Msk (0x1U << CMP_CTRLSTS1_CMP1P_Pos) /*!< 0x00000800 */ #define CMP_CTRLSTS1_CMP1P CMP_CTRLSTS1_CMP1P_Msk /*!< Comparator 1 polarity */ +/*!< CMP1HYST congiguration */ #define CMP_CTRLSTS1_CMP1HYST_Pos (12U) #define CMP_CTRLSTS1_CMP1HYST_Msk (0x3U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00003000 */ #define CMP_CTRLSTS1_CMP1HYST CMP_CTRLSTS1_CMP1HYST_Msk /*!< CMP1HYST[1:0] bits (Comparator 1 hysteresis) */ @@ -9932,6 +10064,7 @@ typedef struct #define CMP_CTRLSTS1_CMP2SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP2SSEL_Pos) /*!< 0x00040000 */ #define CMP_CTRLSTS1_CMP2SSEL CMP_CTRLSTS1_CMP2SSEL_Msk /*!< Comparator 2 speed selection */ +/*!< CMP2INVSEL congiguration */ #define CMP_CTRLSTS1_CMP2INVSEL_Pos (20U) #define CMP_CTRLSTS1_CMP2INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00700000 */ #define CMP_CTRLSTS1_CMP2INVSEL CMP_CTRLSTS1_CMP2INVSEL_Msk /*!< CMP2INVSEL[2:0] bits (Comparator 2 inverting selection) */ @@ -9943,6 +10076,7 @@ typedef struct #define CMP_CTRLSTS1_DCMPEN_Msk (0x1U << CMP_CTRLSTS1_DCMPEN_Pos) /*!< 0x00800000 */ #define CMP_CTRLSTS1_DCMPEN CMP_CTRLSTS1_DCMPEN_Msk /*!< Double comparator mode enable */ +/*!< CMP2TAG congiguration */ #define CMP_CTRLSTS1_CMP2TAG_Pos (24U) #define CMP_CTRLSTS1_CMP2TAG_Msk (0x7U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x07000000 */ #define CMP_CTRLSTS1_CMP2TAG CMP_CTRLSTS1_CMP2TAG_Msk /*!< CMP2TAG[2:0] bits (Comparator 2 output target) */ @@ -9954,6 +10088,7 @@ typedef struct #define CMP_CTRLSTS1_CMP2P_Msk (0x1U << CMP_CTRLSTS1_CMP2P_Pos) /*!< 0x08000000 */ #define CMP_CTRLSTS1_CMP2P CMP_CTRLSTS1_CMP2P_Msk /*!< Comparator 2 polarity */ +/*!< CMP2HYST congiguration */ #define CMP_CTRLSTS1_CMP2HYST_Pos (28U) #define CMP_CTRLSTS1_CMP2HYST_Msk (0x3U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x30000000 */ #define CMP_CTRLSTS1_CMP2HYST CMP_CTRLSTS1_CMP2HYST_Msk /*!< CMP2HYST[1:0] bits (Comparator 2 hysteresis) */ @@ -9968,15 +10103,17 @@ typedef struct #define CMP_CTRLSTS1_CMP2WP CMP_CTRLSTS1_CMP2WP_Msk /*!< Comparator 2 write protect */ /***************** Bit definition for CMP_CTRLSTS2 register *****************/ +/*!< CMP1NINVSEL congiguration */ #define CMP_CTRLSTS2_CMP1NINVSEL_Pos (0U) #define CMP_CTRLSTS2_CMP1NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000003 */ -#define CMP_CTRLSTS2_CMP1NINVSEL CMP_CTRLSTS2_CMP1NINVSEL_Msk /*!< Comparator 1 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP1NINVSEL CMP_CTRLSTS2_CMP1NINVSEL_Msk /*!< CMP1NINVSEL[1:0] bits (Comparator 1 non-inverting input selection) */ #define CMP_CTRLSTS2_CMP1NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000001 */ #define CMP_CTRLSTS2_CMP1NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000002 */ +/*!< CMP2NINVSEL congiguration */ #define CMP_CTRLSTS2_CMP2NINVSEL_Pos (16U) #define CMP_CTRLSTS2_CMP2NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00030000 */ -#define CMP_CTRLSTS2_CMP2NINVSEL CMP_CTRLSTS2_CMP2NINVSEL_Msk /*!< Comparator 2 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP2NINVSEL CMP_CTRLSTS2_CMP2NINVSEL_Msk /*!< CMP2NINVSEL[1:0] bits (Comparator 2 non-inverting input selection) */ #define CMP_CTRLSTS2_CMP2NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00010000 */ #define CMP_CTRLSTS2_CMP2NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00020000 */ @@ -9987,6 +10124,7 @@ typedef struct /******************************************************************************/ /***************** Bit definition for DEBUG_IDCODE register *****************/ +/*!< PID congiguration */ #define DEBUG_IDCODE_PID_Pos (0U) #define DEBUG_IDCODE_PID_Msk (0xFFFFFFFFU << DEBUG_IDCODE_PID_Pos) /*!< 0xFFFFFFFF */ #define DEBUG_IDCODE_PID DEBUG_IDCODE_PID_Msk /*!< PID[31:0] bits (PID information) */ @@ -10037,6 +10175,7 @@ typedef struct #define DEBUG_CTRL_TRACE_IOEN_Msk (0x1U << DEBUG_CTRL_TRACE_IOEN_Pos) /*!< 0x00000020 */ #define DEBUG_CTRL_TRACE_IOEN DEBUG_CTRL_TRACE_IOEN_Msk /*!< Trace pin assignment enable */ +/*!< TRACE_MODE congiguration */ #define DEBUG_CTRL_TRACE_MODE_Pos (6U) #define DEBUG_CTRL_TRACE_MODE_Msk (0x3U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x000000C0 */ #define DEBUG_CTRL_TRACE_MODE DEBUG_CTRL_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace pin assignment control) */ @@ -10095,335 +10234,6 @@ typedef struct * @{ */ -/******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) - -#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) - -#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) - -/******************************* CAN Instances ********************************/ -#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) - -/******************************* CRC Instances ********************************/ -#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) - -/******************************* DMA Instances ********************************/ -#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ - ((INSTANCE) == DMA1_Channel2) || \ - ((INSTANCE) == DMA1_Channel3) || \ - ((INSTANCE) == DMA1_Channel4) || \ - ((INSTANCE) == DMA1_Channel5) || \ - ((INSTANCE) == DMA1_Channel6) || \ - ((INSTANCE) == DMA1_Channel7) || \ - ((INSTANCE) == DMA2_Channel1) || \ - ((INSTANCE) == DMA2_Channel2) || \ - ((INSTANCE) == DMA2_Channel3) || \ - ((INSTANCE) == DMA2_Channel4) || \ - ((INSTANCE) == DMA2_Channel5) || \ - ((INSTANCE) == DMA2_Channel6) || \ - ((INSTANCE) == DMA2_Channel7)) - -/******************************* GPIO Instances *******************************/ -#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ - ((INSTANCE) == GPIOB) || \ - ((INSTANCE) == GPIOC) || \ - ((INSTANCE) == GPIOD) || \ - ((INSTANCE) == GPIOF)) - -/********************* IOMUX Multiplex Function Instances *********************/ -#define IS_IOMUX_ALL_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) - -/**************************** GPIO Lock Instances *****************************/ -#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) - -/******************************* I2C Instances ********************************/ -#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ - ((INSTANCE) == I2C2)) - -/****************************** SMBUS Instances *******************************/ -#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE - -/******************************* I2S Instances ********************************/ -#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ - ((INSTANCE) == SPI2)) - -/******************************* WDT Instances ********************************/ -#define IS_WDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WDT) - -/******************************* SDIO Instances *******************************/ -#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) - -/******************************* SPI Instances ********************************/ -#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ - ((INSTANCE) == SPI2)) - -/**************************** START TMR Instances *****************************/ -/******************************* TMR Instances ********************************/ -#define IS_TMR_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9) || \ - ((INSTANCE) == TMR10) || \ - ((INSTANCE) == TMR11)) - -#define IS_TMR_ADVANCED_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1) - -#define IS_TMR_C1_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9) || \ - ((INSTANCE) == TMR10) || \ - ((INSTANCE) == TMR11)) - -#define IS_TMR_C2_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_C3_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_C4_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_CLOCKSOURCE_EXTMODE1_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_CLOCKSOURCE_EXTMODE2_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_CLOCKSOURCE_TRGIN_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_CLOCKSOURCE_ISX_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_OCXREF_CLEAR_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_XOR_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_MASTER_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_SLAVE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_DMABURST_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_BREAK_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1) - -#define IS_TMR_CX_INSTANCE(INSTANCE, CHANNEL) \ - ((((INSTANCE) == TMR1) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR2) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR3) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR4) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR5) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR9) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2))) \ - || \ - (((INSTANCE) == TMR10) && \ - (((CHANNEL) == TMR_CHANNEL_1))) \ - || \ - (((INSTANCE) == TMR11) && \ - (((CHANNEL) == TMR_CHANNEL_1)))) - -#define IS_TMR_CXN_INSTANCE(INSTANCE, CHANNEL) \ - (((INSTANCE) == TMR1) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3))) - -#define IS_TMR_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_REPETITION_COUNTER_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1) - -#define IS_TMR_CLOCK_DIVISION_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9) || \ - ((INSTANCE) == TMR10) || \ - ((INSTANCE) == TMR11)) - -#define IS_TMR_DMA_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_DMA_CC_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1)) - -#define IS_TMR_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_32B_COUNTER_INSTANCE(INSTANCE) 0U - -/***************************** END TMR Instances ******************************/ - -/********************* USART Instances : Synchronous mode *********************/ -#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2)) - -/********************* UART Instances : Asynchronous mode *********************/ -#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2)) - -/********************* UART Instances : Half-Duplex mode **********************/ -#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2)) - -/************************* UART Instances : LIN mode **************************/ -#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2)) - -/******************* UART Instances : Hardware Flow control *******************/ -#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2)) - -/********************* UART Instances : Smard card mode ***********************/ -#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2)) - -/************************* UART Instances : IRDA mode *************************/ -#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2)) - -/******************* UART Instances : Multi-Processor mode ********************/ -#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2)) - -/******************** UART Instances : DMA mode available *********************/ -#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2)) - -/******************************* ERTC Instances *******************************/ -#define IS_ERTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ERTC) - -/******************************* WWDT Instances *******************************/ -#define IS_WWDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDT) - #define CRM_HEXT_MIN 4000000U #define CRM_HEXT_MAX 25000000U diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h index 708df9bc40..fdd170d7af 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file at32f415rx.h * @author Artery Technology & HorrorTroll & Zhaqian - * @version v2.1.1 - * @date 26-October-2023 + * @version v2.1.2 + * @date 05-January-2024 * @brief AT32F415Rx header file. * ****************************************************************************** @@ -42,11 +42,11 @@ #endif /** - * @brief CMSIS Device version number V2.1.1 + * @brief CMSIS Device version number V2.1.2 */ #define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ #define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ -#define __AT32F415_LIBRARY_VERSION_MINOR (0x01) /*!< [15:8] minor version */ +#define __AT32F415_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */ #define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\ |(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\ @@ -102,7 +102,7 @@ typedef enum WWDT_IRQn = 0, /*!< Window WatchDog Timer Interrupt */ PVM_IRQn = 1, /*!< PVM Interrupt linked to EXINT16 */ TAMPER_IRQn = 2, /*!< Tamper Interrupt linked to EXINT21 */ - ERTC_IRQn = 3, /*!< ERTC Interrupt linked to EXINT22 */ + ERTC_WKUP_IRQn = 3, /*!< ERTC Wake Up Interrupt linked to EXINT22 */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ CRM_IRQn = 5, /*!< CRM global Interrupt */ EXINT0_IRQn = 6, /*!< EXINT Line 0 Interrupt */ @@ -181,8 +181,8 @@ typedef struct __IO uint32_t SPT2; /*!< ADC sampling time register 2, Address offset: 0x10 */ __IO uint32_t PCDTO1; /*!< ADC preempted channel data offset reg 1, Address offset: 0x14 */ __IO uint32_t PCDTO2; /*!< ADC preempted channel data offset reg 2, Address offset: 0x18 */ - __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3 Address offset: 0x1C */ - __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4 Address offset: 0x20 */ + __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3, Address offset: 0x1C */ + __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4, Address offset: 0x20 */ __IO uint32_t VMHB; /*!< ADC voltage monitor high threshold register, Address offset: 0x24 */ __IO uint32_t VMLB; /*!< ADC voltage monitor low threshold register, Address offset: 0x28 */ __IO uint32_t OSQ1; /*!< ADC ordinary sequence register 1, Address offset: 0x2C */ @@ -244,10 +244,10 @@ typedef struct __IO uint32_t INTEN; /*!< CAN interrupt enable register, Address offset: 0x014 */ __IO uint32_t ESTS; /*!< CAN error status register, Address offset: 0x018 */ __IO uint32_t BTMG; /*!< CAN bit timing register, Address offset: 0x01C */ - uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17F */ + uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17C */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN TX Mailbox registers, Address offset: 0x180 ~ 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO Mailbox registers, Address offset: 0x1B0 ~ 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FF */ + uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FC */ __IO uint32_t FCTRL; /*!< CAN filter control register, Address offset: 0x200 */ __IO uint32_t FMCFG; /*!< CAN filter mode configuration register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x208 */ @@ -256,7 +256,7 @@ typedef struct __IO uint32_t FRF; /*!< CAN filter FIFO association register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x218 */ __IO uint32_t FACFG; /*!< CAN filter activation control register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23F */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23C */ CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN filter registers, Address offset: 0x240 ~ 0x2AC */ } CAN_TypeDef; @@ -271,7 +271,7 @@ typedef struct } CMP_TypeDef; /** - * @brief CRC calculation unit + * @brief CRC Calculation Unit */ typedef struct @@ -324,10 +324,10 @@ typedef struct typedef struct { - __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x08 + 20 * (x - 1) x = 1 ... 7 */ - __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x0C + 20 * (x - 1) x = 1 ... 7 */ - __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + 20 * (x - 1) x = 1 ... 7 */ - __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x14 + 20 * (x - 1) x = 1 ... 7 */ + __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x08 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x0C + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x14 + 20 * (x - 1) (x = 1 ... 7) */ } DMA_Channel_TypeDef; typedef struct @@ -408,7 +408,7 @@ typedef struct typedef struct { __IO uint32_t PSR; /*!< FLASH performance select register, Address offset: 0x00 */ - __IO uint32_t UNLOCK; /*!< FLASH unlock register 1, Address offset: 0x04 */ + __IO uint32_t UNLOCK; /*!< FLASH unlock register, Address offset: 0x04 */ __IO uint32_t USD_UNLOCK; /*!< FLASH user system data unlock register, Address offset: 0x08 */ __IO uint32_t STS; /*!< FLASH status register, Address offset: 0x0C */ __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x10 */ @@ -428,7 +428,7 @@ typedef struct __IO uint32_t SLIB_SET_PWD; /*!< FLASH security library password setting reg, Address offset: 0x160 */ __IO uint32_t SLIB_SET_RANGE; /*!< FLASH security library address setting reg, Address offset: 0x164 */ __IO uint32_t EM_SLIB_SET; /*!< FLASH extension mem security lib set reg, Address offset: 0x168 */ - __IO uint32_t BTM_MODE_SET; /*!< FLASH boot mode setting register, Address offset: 0x16C */ + __IO uint32_t BTM_MODE_SET; /*!< FLASH boot memory mode setting register, Address offset: 0x16C */ __IO uint32_t SLIB_UNLOCK; /*!< FLASH security library unlock register, Address offset: 0x170 */ } FLASH_TypeDef; @@ -438,15 +438,15 @@ typedef struct typedef struct { - __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ - __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ - __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ - __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ - __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ - __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ - __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ - __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ - __IO uint16_t DATA[504]; /*!< USD User data 2 ~ 505, Address offset: 0x1FFF_F810 ~ 0x1FFF_FBFC */ + __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ + __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ + __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ + __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ + __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ + __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ + __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ + __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ + __IO uint16_t DATA[504]; /*!< USD User data 2 ~ 505, Address offset: 0x1FFF_F810 ~ 0x1FFF_FBFC */ } USD_TypeDef; /** @@ -455,13 +455,13 @@ typedef struct typedef struct { - __IO uint32_t CFGLR; /*!< GPIO configuration register low, Address offset: 0x00 */ - __IO uint32_t CFGHR; /*!< GPIO configuration register high, Address offset: 0x04 */ - __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x08 */ - __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x0C */ - __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x10 */ - __IO uint32_t CLR; /*!< GPIO clear register, Address offset: 0x14 */ - __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x18 */ + __IO uint32_t CFGLR; /*!< GPIO configuration register low, Address offset: 0x00 */ + __IO uint32_t CFGHR; /*!< GPIO configuration register high, Address offset: 0x04 */ + __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x08 */ + __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x0C */ + __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x10 */ + __IO uint32_t CLR; /*!< GPIO clear register, Address offset: 0x14 */ + __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x18 */ } GPIO_TypeDef; /** @@ -470,17 +470,17 @@ typedef struct typedef struct { - __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ - __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ - __IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ - __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ - __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ - __IO uint32_t REMAP4; /*!< IOMUX remap register 4, Address offset: 0x24 */ - __IO uint32_t REMAP5; /*!< IOMUX remap register 5, Address offset: 0x28 */ - __IO uint32_t REMAP6; /*!< IOMUX remap register 6, Address offset: 0x2C */ - __IO uint32_t REMAP7; /*!< IOMUX remap register 7, Address offset: 0x30 */ - __IO uint32_t REMAP8; /*!< IOMUX remap register 8, Address offset: 0x34 */ + __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ + __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ + __IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register x, Address offset: 0x08 ~ 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ + __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ + __IO uint32_t REMAP4; /*!< IOMUX remap register 4, Address offset: 0x24 */ + __IO uint32_t REMAP5; /*!< IOMUX remap register 5, Address offset: 0x28 */ + __IO uint32_t REMAP6; /*!< IOMUX remap register 6, Address offset: 0x2C */ + __IO uint32_t REMAP7; /*!< IOMUX remap register 7, Address offset: 0x30 */ + __IO uint32_t REMAP8; /*!< IOMUX remap register 8, Address offset: 0x34 */ } IOMUX_TypeDef; /** @@ -549,9 +549,9 @@ typedef struct __IO uint32_t STS; /*!< SPI status register, Address offset: 0x08 */ __IO uint32_t DT; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CPOLY; /*!< SPI CRC register, Address offset: 0x10 */ - __IO uint32_t RCRC; /*!< SPI RX CRC register, Address offset: 0x14 */ - __IO uint32_t TCRC; /*!< SPI TX CRC register, Address offset: 0x18 */ - __IO uint32_t I2SCTRL; /*!< SPI_I2S register, Address offset: 0x1C */ + __IO uint32_t RCRC; /*!< SPI receive CRC register, Address offset: 0x14 */ + __IO uint32_t TCRC; /*!< SPI transmit CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCTRL; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SCLKP; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; @@ -569,9 +569,9 @@ typedef struct __IO uint32_t SWEVT; /*!< TMR software event register, Address offset: 0x14 */ __IO uint32_t CM1; /*!< TMR channel mode register 1, Address offset: 0x18 */ __IO uint32_t CM2; /*!< TMR channel mode register 2, Address offset: 0x1C */ - __IO uint32_t CCTRL; /*!< TMR Channel control register, Address offset: 0x20 */ - __IO uint32_t CVAL; /*!< TMR counter value, Address offset: 0x24 */ - __IO uint32_t DIV; /*!< TMR division value, Address offset: 0x28 */ + __IO uint32_t CCTRL; /*!< TMR channel control register, Address offset: 0x20 */ + __IO uint32_t CVAL; /*!< TMR counter value register, Address offset: 0x24 */ + __IO uint32_t DIV; /*!< TMR division value register, Address offset: 0x28 */ __IO uint32_t PR; /*!< TMR period register, Address offset: 0x2C */ __IO uint32_t RPR; /*!< TMR repetition period register, Address offset: 0x30 */ __IO uint32_t C1DT; /*!< TMR channel 1 data register, Address offset: 0x34 */ @@ -659,6 +659,7 @@ typedef struct #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /*!< I2C2 base address */ #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) /*!< CAN1 base address */ #define PWC_BASE (APB1PERIPH_BASE + 0x00007000U) /*!< PWC base address */ + #define IOMUX_BASE (APB2PERIPH_BASE + 0x00000000U) /*!< IOMUX base address */ #define EXINT_BASE (APB2PERIPH_BASE + 0x00000400U) /*!< EXINT base address */ #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) /*!< GPIOA base address */ @@ -702,8 +703,8 @@ typedef struct #define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ -/* USB OTG device FS */ -#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG Peripheral Registers base address */ +/* USB OTG FS */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG FS Peripheral Registers base address */ #define USB_OTG_GLOBAL_BASE 0x00000000U /*!< USB OTG Global Registers base address */ #define USB_OTG_DEVICE_BASE 0x00000800U /*!< USB OTG Device ModeRegisters base address */ @@ -714,9 +715,7 @@ typedef struct #define USB_OTG_HOST_PORT_BASE 0x00000440U /*!< USB OTG Host Port Registers base address */ #define USB_OTG_HOST_CHANNEL_BASE 0x00000500U /*!< USB OTG Host Channel Registers base address */ #define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U /*!< USB OTG Host Channel Registers size address */ -#define USB_OTG_DEP3RMPEN_BASE 0x00000D0CU /*!< USB OTG DEP3RMPEN Registers base address */ #define USB_OTG_PCGCCTL_BASE 0x00000E00U /*!< USB OTG Power and Ctrl Registers base address */ -#define USB_OTG_USBDIVRST_BASE 0x00000E10U /*!< USB OTG USBDIVRST Registers base address */ #define USB_OTG_FIFO_BASE 0x00001000U /*!< USB OTG FIFO Registers base address */ #define USB_OTG_FIFO_SIZE 0x00001000U /*!< USB OTG FIFO Registers size address */ @@ -728,59 +727,59 @@ typedef struct * @{ */ -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -#define CAN1 ((CAN_TypeDef *)CAN1_BASE) -#define CMP ((CMP_TypeDef *)CMP_BASE) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define CRM ((CRM_TypeDef *)CRM_BASE) -#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) -#define DMA1 ((DMA_TypeDef *)DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) -#define DMA2 ((DMA_TypeDef *)DMA2_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) -#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) -#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) -#define ERTC ((ERTC_TypeDef *)ERTC_BASE) -#define EXINT ((EXINT_TypeDef *)EXINT_BASE) -#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) -#define USD ((USD_TypeDef *)USD_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) -#define IOMUX ((IOMUX_TypeDef *)IOMUX_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define I2C2 ((I2C_TypeDef *)I2C2_BASE) -#define PWC ((PWC_TypeDef *)PWC_BASE) -#define SDIO ((SDIO_TypeDef *)SDIO_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) -#define TMR1 ((TMR_TypeDef *)TMR1_BASE) -#define TMR2 ((TMR_TypeDef *)TMR2_BASE) -#define TMR3 ((TMR_TypeDef *)TMR3_BASE) -#define TMR4 ((TMR_TypeDef *)TMR4_BASE) -#define TMR5 ((TMR_TypeDef *)TMR5_BASE) -#define TMR9 ((TMR_TypeDef *)TMR9_BASE) -#define TMR10 ((TMR_TypeDef *)TMR10_BASE) -#define TMR11 ((TMR_TypeDef *)TMR11_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define USART2 ((USART_TypeDef *)USART2_BASE) -#define USART3 ((USART_TypeDef *)USART3_BASE) -#define UART4 ((USART_TypeDef *)UART4_BASE) -#define UART5 ((USART_TypeDef *)UART5_BASE) -#define WDT ((WDT_TypeDef *)WDT_BASE) -#define WWDT ((WWDT_TypeDef *)WWDT_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CMP ((CMP_TypeDef *)CMP_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CRM ((CRM_TypeDef *)CRM_BASE) +#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) +#define ERTC ((ERTC_TypeDef *)ERTC_BASE) +#define EXINT ((EXINT_TypeDef *)EXINT_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USD ((USD_TypeDef *)USD_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define IOMUX ((IOMUX_TypeDef *)IOMUX_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define PWC ((PWC_TypeDef *)PWC_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define TMR1 ((TMR_TypeDef *)TMR1_BASE) +#define TMR2 ((TMR_TypeDef *)TMR2_BASE) +#define TMR3 ((TMR_TypeDef *)TMR3_BASE) +#define TMR4 ((TMR_TypeDef *)TMR4_BASE) +#define TMR5 ((TMR_TypeDef *)TMR5_BASE) +#define TMR9 ((TMR_TypeDef *)TMR9_BASE) +#define TMR10 ((TMR_TypeDef *)TMR10_BASE) +#define TMR11 ((TMR_TypeDef *)TMR11_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define UART5 ((USART_TypeDef *)UART5_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) /** * @} @@ -810,7 +809,7 @@ typedef struct #define PWC_CTRL_VRSEL PWC_CTRL_VRSEL_Msk /*!< LDO state select in deep sleep mode */ #define PWC_CTRL_LPSEL_Pos (1U) #define PWC_CTRL_LPSEL_Msk (0x1U << PWC_CTRL_LPSEL_Pos) /*!< 0x00000002 */ -#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep */ +#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep mode */ #define PWC_CTRL_CLSWEF_Pos (2U) #define PWC_CTRL_CLSWEF_Msk (0x1U << PWC_CTRL_CLSWEF_Pos) /*!< 0x00000004 */ #define PWC_CTRL_CLSWEF PWC_CTRL_CLSWEF_Msk /*!< Clear SWEF flag */ @@ -1164,7 +1163,7 @@ typedef struct #define CRM_CLKINT_PLLSTBLF CRM_CLKINT_PLLSTBLF_Msk /*!< PLL stable flag */ #define CRM_CLKINT_CFDF_Pos (7U) #define CRM_CLKINT_CFDF_Msk (0x1U << CRM_CLKINT_CFDF_Pos) /*!< 0x00000080 */ -#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock Failure Detection flag */ +#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock failure detection flag */ #define CRM_CLKINT_LICKSTBLIEN_Pos (8U) #define CRM_CLKINT_LICKSTBLIEN_Msk (0x1U << CRM_CLKINT_LICKSTBLIEN_Pos) /*!< 0x00000100 */ #define CRM_CLKINT_LICKSTBLIEN CRM_CLKINT_LICKSTBLIEN_Msk /*!< LICK stable interrupt enable */ @@ -1407,10 +1406,10 @@ typedef struct #define CRM_BPDC_LEXTEN CRM_BPDC_LEXTEN_Msk /*!< External low-speed oscillator enable */ #define CRM_BPDC_LEXTSTBL_Pos (1U) #define CRM_BPDC_LEXTSTBL_Msk (0x1U << CRM_BPDC_LEXTSTBL_Pos) /*!< 0x00000002 */ -#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< Low speed external oscillator stable */ +#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< External low-speed oscillator stable */ #define CRM_BPDC_LEXTBYPS_Pos (2U) #define CRM_BPDC_LEXTBYPS_Msk (0x1U << CRM_BPDC_LEXTBYPS_Pos) /*!< 0x00000004 */ -#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< Low speed external crystal bypass */ +#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< External low-speed crystal bypass */ /*!< ERTCSEL congiguration */ #define CRM_BPDC_ERTCSEL_Pos (8U) @@ -1521,7 +1520,7 @@ typedef struct #define CRM_MISC1_HICKCAL_KEY_Msk (0xFFU << CRM_MISC1_HICKCAL_KEY_Pos) /*!< 0x000000FF */ #define CRM_MISC1_HICKCAL_KEY CRM_MISC1_HICKCAL_KEY_Msk /*!< HICK calibration key */ #define CRM_MISC1_CLKOUT_SEL_Pos (16U) -#define CRM_MISC1_CLKOUT_SEL_Msk (0x1U << CRN_MISC1_CLKOUT_SEL_Pos) /*!< 0x00010000 */ +#define CRM_MISC1_CLKOUT_SEL_Msk (0x1U << CRM_MISC1_CLKOUT_SEL_Pos) /*!< 0x00010000 */ #define CRM_MISC1_CLKOUT_SEL CRM_MISC1_CLKOUT_SEL_Msk /*!< Clock output selection */ #define CRM_MISC1_CLKFMC_SRC_Pos (20U) #define CRM_MISC1_CLKFMC_SRC_Msk (0x1U << CRM_MISC1_CLKFMC_SRC_Pos) /*!< 0x00100000 */ @@ -1533,7 +1532,7 @@ typedef struct /*!< CLKOUTDIV congiguration */ #define CRM_MISC1_CLKOUTDIV_Pos (28U) #define CRM_MISC1_CLKOUTDIV_Msk (0xFU << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0xF0000000 */ -#define CRM_MISC1_CLKOUTDIV CRM_MISC1_CLKOUTDIV_Msk /*!< CLKOUTDIV[3:0] bits (Clock output division */ +#define CRM_MISC1_CLKOUTDIV CRM_MISC1_CLKOUTDIV_Msk /*!< CLKOUTDIV[3:0] bits (Clock output division) */ #define CRM_MISC1_CLKOUTDIV_0 (0x1U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x10000000 */ #define CRM_MISC1_CLKOUTDIV_1 (0x2U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x20000000 */ #define CRM_MISC1_CLKOUTDIV_2 (0x4U << CRM_MISC1_CLKOUTDIV_Pos) /*!< 0x40000000 */ @@ -1561,7 +1560,7 @@ typedef struct /*!< AUTO_STEP_EN congiguration */ #define CRM_MISC2_AUTO_STEP_EN_Pos (4U) #define CRM_MISC2_AUTO_STEP_EN_Msk (0x3U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000030 */ -#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] Auto step-by-step SCLK switch enable */ +#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] bits (Auto step-by-step SCLK switch enable) */ #define CRM_MISC2_AUTO_STEP_EN_0 (0x1U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000010 */ #define CRM_MISC2_AUTO_STEP_EN_1 (0x2U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000020 */ @@ -1579,7 +1578,7 @@ typedef struct /*!< WTCYC congiguration */ #define FLASH_PSR_WTCYC_Pos (0U) #define FLASH_PSR_WTCYC_Msk (0x7U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000007 */ -#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] Wait states */ +#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] bits (Wait cycle) */ #define FLASH_PSR_WTCYC_0 (0x1U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000001 */ #define FLASH_PSR_WTCYC_1 (0x2U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000002 */ #define FLASH_PSR_WTCYC_2 (0x4U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000004 */ @@ -1620,7 +1619,7 @@ typedef struct /****************** Bit definition for FLASH_STS register *******************/ #define FLASH_STS_OBF_Pos (0U) #define FLASH_STS_OBF_Msk (0x1U << FLASH_STS_OBF_Pos) /*!< 0x00000001 */ -#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation done flag */ +#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation busy flag */ #define FLASH_STS_PRGMERR_Pos (2U) #define FLASH_STS_PRGMERR_Msk (0x1U << FLASH_STS_PRGMERR_Pos) /*!< 0x00000004 */ #define FLASH_STS_PRGMERR FLASH_STS_PRGMERR_Msk /*!< Programming error */ @@ -1727,10 +1726,10 @@ typedef struct #define SLIB_STS1_SLIB_SS_Msk (0x7FFU << SLIB_STS1_SLIB_SS_Pos) /*!< 0x000007FF */ #define SLIB_STS1_SLIB_SS SLIB_STS1_SLIB_SS_Msk /*!< Security library start page */ #define SLIB_STS1_SLIB_DAT_SS_Pos (11U) -#define SLIB_STS1_SLIB_DAT_SS_Msk (0x3FF8U << SLIB_STS1_SLIB_DAT_SS_Pos) /*!< 0x003FF800 */ +#define SLIB_STS1_SLIB_DAT_SS_Msk (0x7FFU << SLIB_STS1_SLIB_DAT_SS_Pos) /*!< 0x003FF800 */ #define SLIB_STS1_SLIB_DAT_SS SLIB_STS1_SLIB_DAT_SS_Msk /*!< Security library data start page */ #define SLIB_STS1_SLIB_ES_Pos (22U) -#define SLIB_STS1_SLIB_ES_Msk (0xFFCU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ +#define SLIB_STS1_SLIB_ES_Msk (0x3FFU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ #define SLIB_STS1_SLIB_ES SLIB_STS1_SLIB_ES_Msk /*!< Security library end page */ /***************** Bit definition for SLIB_PWD_CLR register ******************/ @@ -1749,10 +1748,10 @@ typedef struct #define SLIB_MISC_STS_SLIB_ULKF_Msk (0x1U << SLIB_MISC_STS_SLIB_ULKF_Pos) /*!< 0x00000004 */ #define SLIB_MISC_STS_SLIB_ULKF SLIB_MISC_STS_SLIB_ULKF_Msk /*!< Security library unlock flag */ -/***************** Bit definition for FLASH_CRC_ARR register *****************/ -#define FLASH_CRC_ARR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ -#define FLASH_CRC_ARR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ARR_CRC_ADDR_Pos) -#define FLASH_CRC_ARR_CRC_ADDR FLASH_CRC_ARR_CRC_ADDR_Msk /*!< CRC address */ +/**************** Bit definition for FLASH_CRC_ADDR register *****************/ +#define FLASH_CRC_ADDR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_ADDR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ADDR_CRC_ADDR_Pos) +#define FLASH_CRC_ADDR_CRC_ADDR FLASH_CRC_ADDR_CRC_ADDR_Msk /*!< CRC address */ /**************** Bit definition for FLASH_CRC_CTRL register *****************/ #define FLASH_CRC_CTRL_CRC_SN_Pos (0U) @@ -1770,7 +1769,7 @@ typedef struct /***************** Bit definition for SLIB_SET_PWD register ******************/ #define SLIB_SET_PWD_SLIB_PSET_VAL_Pos (0U) /*!< 0xFFFFFFFF */ #define SLIB_SET_PWD_SLIB_PSET_VAL_Msk (0xFFFFFFFFU << SLIB_SET_PWD_SLIB_PSET_VAL_Pos) -#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< sLib password setting value */ +#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< Security library password setting value */ /**************** Bit definition for SLIB_SET_RANGE register *****************/ #define SLIB_SET_RANGE_SLIB_SS_SET_Pos (0U) /*!< 0x000007FF */ @@ -1789,7 +1788,7 @@ typedef struct #define EM_SLIB_SET_EM_SLIB_SET EM_SLIB_SET_EM_SLIB_SET_Msk /*!< Extension memory sLib setting */ #define EM_SLIB_SET_EM_SLIB_ISS_SET_Pos (16U) /*!< 0x00FF0000 */ #define EM_SLIB_SET_EM_SLIB_ISS_SET_Msk (0xFFU << EM_SLIB_SET_EM_SLIB_ISS_SET_Pos) -#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page setting */ /***************** Bit definition for BTM_MODE_SET register ******************/ #define BTM_MODE_SET_BTM_MODE_SET_Pos (0U) /*!< 0x000000FF */ @@ -1801,9 +1800,9 @@ typedef struct #define SLIB_UNLOCK_SLIB_UKVAL_Msk (0xFFFFFFFFU << SLIB_UNLOCK_SLIB_UKVAL_Pos) #define SLIB_UNLOCK_SLIB_UKVAL SLIB_UNLOCK_SLIB_UKVAL_Msk /*!< Security library unlock key value */ -#define SLIB_KEY_Pos (0U) +#define SLIB_KEY_Pos (0U) #define SLIB_KEY_Msk (0xA35F6D24U << SLIB_KEY_Pos) /*!< 0xA35F6D24 */ -#define SLIB_KEY SLIB_KEY_Msk +#define SLIB_KEY SLIB_KEY_Msk /*!< Security library key */ /*----------------------------------------------------------------------------*/ @@ -1823,7 +1822,7 @@ typedef struct #define FLASH_SSB_nSSB_Msk (0xFFU << FLASH_SSB_nSSB_Pos) /*!< 0xFF000000 */ #define FLASH_SSB_nSSB FLASH_SSB_nSSB_Msk /*!< Inverse code of system configuration byte */ -/****************** Bit definition for FLASH_DATA0 register *****************/ +/***************** Bit definition for FLASH_DATA0 register ******************/ #define FLASH_DATA0_DATA0_Pos (0U) #define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data 0 */ @@ -1831,7 +1830,7 @@ typedef struct #define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< Inverse code of user data 0 */ -/****************** Bit definition for FLASH_DATA1 register *****************/ +/***************** Bit definition for FLASH_DATA1 register ******************/ #define FLASH_DATA1_DATA1_Pos (16U) #define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data 1 */ @@ -1871,15 +1870,7 @@ typedef struct #define FLASH_EPP3_nEPP3_Msk (0xFFU << FLASH_EPP3_nEPP3_Pos) /*!< 0xFF000000 */ #define FLASH_EPP3_nEPP3 FLASH_EPP3_nEPP3_Msk /*!< Inverse code of flash erase/write protection byte 3 */ -/***************** Bit definition for FLASH_EOPB0 register ******************/ -#define FLASH_EOPB0_EOPB0_Pos (0U) -#define FLASH_EOPB0_EOPB0_Msk (0xFFU << FLASH_EOPB0_EOPB0_Pos) /*!< 0x000000FF */ -#define FLASH_EOPB0_EOPB0 FLASH_EOPB0_EOPB0_Msk /*!< Extended system options */ -#define FLASH_EOPB0_nEOPB0_Pos (8U) -#define FLASH_EOPB0_nEOPB0_Msk (0xFFU << FLASH_EOPB0_nEOPB0_Pos) /*!< 0x0000FF00 */ -#define FLASH_EOPB0_nEOPB0 FLASH_EOPB0_nEOPB0_Msk /*!< Inverse code of extended system options */ - -/****************** Bit definition for FLASH_DATA2 register *****************/ +/***************** Bit definition for FLASH_DATA2 register ******************/ #define FLASH_DATA2_DATA2_Pos (0U) #define FLASH_DATA2_DATA2_Msk (0xFFU << FLASH_DATA2_DATA2_Pos) /*!< 0x000000FF */ #define FLASH_DATA2_DATA2 FLASH_DATA2_DATA2_Msk /*!< User data 2 */ @@ -1887,7 +1878,7 @@ typedef struct #define FLASH_DATA2_nDATA2_Msk (0xFFU << FLASH_DATA2_nDATA2_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA2_nDATA2 FLASH_DATA2_nDATA2_Msk /*!< Inverse code of user data 2 */ -/****************** Bit definition for FLASH_DATA3 register *****************/ +/***************** Bit definition for FLASH_DATA3 register ******************/ #define FLASH_DATA3_DATA3_Pos (16U) #define FLASH_DATA3_DATA3_Msk (0xFFU << FLASH_DATA3_DATA3_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA3_DATA3 FLASH_DATA3_DATA3_Msk /*!< User data 3 */ @@ -1895,7 +1886,7 @@ typedef struct #define FLASH_DATA3_nDATA3_Msk (0xFFU << FLASH_DATA3_nDATA3_Pos) /*!< 0xFF000000 */ #define FLASH_DATA3_nDATA3 FLASH_DATA3_nDATA3_Msk /*!< Inverse code of user data 3 */ -/****************** Bit definition for FLASH_DATA4 register *****************/ +/***************** Bit definition for FLASH_DATA4 register ******************/ #define FLASH_DATA4_DATA4_Pos (0U) #define FLASH_DATA4_DATA4_Msk (0xFFU << FLASH_DATA4_DATA4_Pos) /*!< 0x000000FF */ #define FLASH_DATA4_DATA4 FLASH_DATA4_DATA4_Msk /*!< User data 4 */ @@ -1903,7 +1894,7 @@ typedef struct #define FLASH_DATA4_nDATA4_Msk (0xFFU << FLASH_DATA4_nDATA4_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA4_nDATA4 FLASH_DATA4_nDATA4_Msk /*!< Inverse code of user data 4 */ -/****************** Bit definition for FLASH_DATA5 register *****************/ +/***************** Bit definition for FLASH_DATA5 register ******************/ #define FLASH_DATA5_DATA5_Pos (16U) #define FLASH_DATA5_DATA5_Msk (0xFFU << FLASH_DATA5_DATA5_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA5_DATA5 FLASH_DATA5_DATA5_Msk /*!< User data 5 */ @@ -1911,7 +1902,7 @@ typedef struct #define FLASH_DATA5_nDATA5_Msk (0xFFU << FLASH_DATA5_nDATA5_Pos) /*!< 0xFF000000 */ #define FLASH_DATA5_nDATA5 FLASH_DATA5_nDATA5_Msk /*!< Inverse code of user data 5 */ -/****************** Bit definition for FLASH_DATA6 register *****************/ +/***************** Bit definition for FLASH_DATA6 register ******************/ #define FLASH_DATA6_DATA6_Pos (0U) #define FLASH_DATA6_DATA6_Msk (0xFFU << FLASH_DATA6_DATA6_Pos) /*!< 0x000000FF */ #define FLASH_DATA6_DATA6 FLASH_DATA6_DATA6_Msk /*!< User data 6 */ @@ -1919,7 +1910,7 @@ typedef struct #define FLASH_DATA6_nDATA6_Msk (0xFFU << FLASH_DATA6_nDATA6_Pos) /*!< 0x0000FF00 */ #define FLASH_DATA6_nDATA6 FLASH_DATA6_nDATA6_Msk /*!< Inverse code of user data 6 */ -/****************** Bit definition for FLASH_DATA7 register *****************/ +/***************** Bit definition for FLASH_DATA7 register ******************/ #define FLASH_DATA7_DATA7_Pos (16U) #define FLASH_DATA7_DATA7_Msk (0xFFU << FLASH_DATA7_DATA7_Pos) /*!< 0x00FF0000 */ #define FLASH_DATA7_DATA7 FLASH_DATA7_DATA7_Msk /*!< User data 7 */ @@ -1940,48 +1931,56 @@ typedef struct #define GPIO_CFGLR_IOMC_Msk (0x33333333U << GPIO_CFGLR_IOMC_Pos) /*!< 0x33333333 */ #define GPIO_CFGLR_IOMC GPIO_CFGLR_IOMC_Msk /*!< GPIO x mode configuration */ +/*!< IOMC0 configuration */ #define GPIO_CFGLR_IOMC0_Pos (0U) #define GPIO_CFGLR_IOMC0_Msk (0x3U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000003 */ #define GPIO_CFGLR_IOMC0 GPIO_CFGLR_IOMC0_Msk /*!< IOMC0[1:0] bits (GPIO x mode configuration, pin 0) */ #define GPIO_CFGLR_IOMC0_0 (0x1U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000001 */ #define GPIO_CFGLR_IOMC0_1 (0x2U << GPIO_CFGLR_IOMC0_Pos) /*!< 0x00000002 */ +/*!< IOMC1 configuration */ #define GPIO_CFGLR_IOMC1_Pos (4U) #define GPIO_CFGLR_IOMC1_Msk (0x3U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000030 */ #define GPIO_CFGLR_IOMC1 GPIO_CFGLR_IOMC1_Msk /*!< IOMC1[1:0] bits (GPIO x mode configuration, pin 1) */ #define GPIO_CFGLR_IOMC1_0 (0x1U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000010 */ #define GPIO_CFGLR_IOMC1_1 (0x2U << GPIO_CFGLR_IOMC1_Pos) /*!< 0x00000020 */ +/*!< IOMC2 configuration */ #define GPIO_CFGLR_IOMC2_Pos (8U) #define GPIO_CFGLR_IOMC2_Msk (0x3U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000300 */ #define GPIO_CFGLR_IOMC2 GPIO_CFGLR_IOMC2_Msk /*!< IOMC2[1:0] bits (GPIO x mode configuration, pin 2) */ #define GPIO_CFGLR_IOMC2_0 (0x1U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000100 */ #define GPIO_CFGLR_IOMC2_1 (0x2U << GPIO_CFGLR_IOMC2_Pos) /*!< 0x00000200 */ +/*!< IOMC3 configuration */ #define GPIO_CFGLR_IOMC3_Pos (12U) #define GPIO_CFGLR_IOMC3_Msk (0x3U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00003000 */ #define GPIO_CFGLR_IOMC3 GPIO_CFGLR_IOMC3_Msk /*!< IOMC3[1:0] bits (GPIO x mode configuration, pin 3) */ #define GPIO_CFGLR_IOMC3_0 (0x1U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00001000 */ #define GPIO_CFGLR_IOMC3_1 (0x2U << GPIO_CFGLR_IOMC3_Pos) /*!< 0x00002000 */ +/*!< IOMC4 configuration */ #define GPIO_CFGLR_IOMC4_Pos (16U) #define GPIO_CFGLR_IOMC4_Msk (0x3U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00030000 */ #define GPIO_CFGLR_IOMC4 GPIO_CFGLR_IOMC4_Msk /*!< IOMC4[1:0] bits (GPIO x mode configuration, pin 4) */ #define GPIO_CFGLR_IOMC4_0 (0x1U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00010000 */ #define GPIO_CFGLR_IOMC4_1 (0x2U << GPIO_CFGLR_IOMC4_Pos) /*!< 0x00020000 */ +/*!< IOMC5 configuration */ #define GPIO_CFGLR_IOMC5_Pos (20U) #define GPIO_CFGLR_IOMC5_Msk (0x3U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00300000 */ #define GPIO_CFGLR_IOMC5 GPIO_CFGLR_IOMC5_Msk /*!< IOMC5[1:0] bits (GPIO x mode configuration, pin 5) */ #define GPIO_CFGLR_IOMC5_0 (0x1U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00100000 */ #define GPIO_CFGLR_IOMC5_1 (0x2U << GPIO_CFGLR_IOMC5_Pos) /*!< 0x00200000 */ +/*!< IOMC6 configuration */ #define GPIO_CFGLR_IOMC6_Pos (24U) #define GPIO_CFGLR_IOMC6_Msk (0x3U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x03000000 */ #define GPIO_CFGLR_IOMC6 GPIO_CFGLR_IOMC6_Msk /*!< IOMC6[1:0] bits (GPIO x mode configuration, pin 6) */ #define GPIO_CFGLR_IOMC6_0 (0x1U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x01000000 */ #define GPIO_CFGLR_IOMC6_1 (0x2U << GPIO_CFGLR_IOMC6_Pos) /*!< 0x02000000 */ +/*!< IOMC7 configuration */ #define GPIO_CFGLR_IOMC7_Pos (28U) #define GPIO_CFGLR_IOMC7_Msk (0x3U << GPIO_CFGLR_IOMC7_Pos) /*!< 0x30000000 */ #define GPIO_CFGLR_IOMC7 GPIO_CFGLR_IOMC7_Msk /*!< IOMC7[1:0] bits (GPIO x mode configuration, pin 7) */ @@ -1992,48 +1991,56 @@ typedef struct #define GPIO_CFGLR_IOFC_Msk (0x33333333U << GPIO_CFGLR_IOFC_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CFGLR_IOFC GPIO_CFGLR_IOFC_Msk /*!< GPIO x function configuration */ +/*!< IOFC0 configuration */ #define GPIO_CFGLR_IOFC0_Pos (2U) #define GPIO_CFGLR_IOFC0_Msk (0x3U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x0000000C */ #define GPIO_CFGLR_IOFC0 GPIO_CFGLR_IOFC0_Msk /*!< IOFC0[1:0] bits (GPIO x function configuration, pin 0) */ #define GPIO_CFGLR_IOFC0_0 (0x1U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000004 */ #define GPIO_CFGLR_IOFC0_1 (0x2U << GPIO_CFGLR_IOFC0_Pos) /*!< 0x00000008 */ +/*!< IOFC1 configuration */ #define GPIO_CFGLR_IOFC1_Pos (6U) #define GPIO_CFGLR_IOFC1_Msk (0x3U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x000000C0 */ #define GPIO_CFGLR_IOFC1 GPIO_CFGLR_IOFC1_Msk /*!< IOFC1[1:0] bits (GPIO x function configuration, pin 1) */ #define GPIO_CFGLR_IOFC1_0 (0x1U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000040 */ #define GPIO_CFGLR_IOFC1_1 (0x2U << GPIO_CFGLR_IOFC1_Pos) /*!< 0x00000080 */ +/*!< IOFC2 configuration */ #define GPIO_CFGLR_IOFC2_Pos (10U) #define GPIO_CFGLR_IOFC2_Msk (0x3U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000C00 */ #define GPIO_CFGLR_IOFC2 GPIO_CFGLR_IOFC2_Msk /*!< IOFC2[1:0] bits (GPIO x function configuration, pin 2) */ #define GPIO_CFGLR_IOFC2_0 (0x1U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000400 */ #define GPIO_CFGLR_IOFC2_1 (0x2U << GPIO_CFGLR_IOFC2_Pos) /*!< 0x00000800 */ +/*!< IOFC3 configuration */ #define GPIO_CFGLR_IOFC3_Pos (14U) #define GPIO_CFGLR_IOFC3_Msk (0x3U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x0000C000 */ #define GPIO_CFGLR_IOFC3 GPIO_CFGLR_IOFC3_Msk /*!< IOFC3[1:0] bits (GPIO x function configuration, pin 3) */ #define GPIO_CFGLR_IOFC3_0 (0x1U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00004000 */ #define GPIO_CFGLR_IOFC3_1 (0x2U << GPIO_CFGLR_IOFC3_Pos) /*!< 0x00008000 */ +/*!< IOFC4 configuration */ #define GPIO_CFGLR_IOFC4_Pos (18U) #define GPIO_CFGLR_IOFC4_Msk (0x3U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x000C0000 */ #define GPIO_CFGLR_IOFC4 GPIO_CFGLR_IOFC4_Msk /*!< IOFC4[1:0] bits (GPIO x function configuration, pin 4) */ #define GPIO_CFGLR_IOFC4_0 (0x1U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00040000 */ #define GPIO_CFGLR_IOFC4_1 (0x2U << GPIO_CFGLR_IOFC4_Pos) /*!< 0x00080000 */ +/*!< IOFC5 configuration */ #define GPIO_CFGLR_IOFC5_Pos (22U) #define GPIO_CFGLR_IOFC5_Msk (0x3U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00C00000 */ #define GPIO_CFGLR_IOFC5 GPIO_CFGLR_IOFC5_Msk /*!< IOFC5[1:0] bits (GPIO x function configuration, pin 5) */ #define GPIO_CFGLR_IOFC5_0 (0x1U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00400000 */ #define GPIO_CFGLR_IOFC5_1 (0x2U << GPIO_CFGLR_IOFC5_Pos) /*!< 0x00800000 */ +/*!< IOFC6 configuration */ #define GPIO_CFGLR_IOFC6_Pos (26U) #define GPIO_CFGLR_IOFC6_Msk (0x3U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x0C000000 */ #define GPIO_CFGLR_IOFC6 GPIO_CFGLR_IOFC6_Msk /*!< IOFC6[1:0] bits (GPIO x function configuration, pin 6) */ #define GPIO_CFGLR_IOFC6_0 (0x1U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x04000000 */ #define GPIO_CFGLR_IOFC6_1 (0x2U << GPIO_CFGLR_IOFC6_Pos) /*!< 0x08000000 */ +/*!< IOFC7 configuration */ #define GPIO_CFGLR_IOFC7_Pos (30U) #define GPIO_CFGLR_IOFC7_Msk (0x3U << GPIO_CFGLR_IOFC7_Pos) /*!< 0xC0000000 */ #define GPIO_CFGLR_IOFC7 GPIO_CFGLR_IOFC7_Msk /*!< IOFC7[1:0] bits (GPIO x function configuration, pin 7) */ @@ -2045,48 +2052,56 @@ typedef struct #define GPIO_CFGHR_IOMC_Msk (0x33333333U << GPIO_CFGHR_IOMC_Pos) /*!< 0x33333333 */ #define GPIO_CFGHR_IOMC GPIO_CFGHR_IOMC_Msk /*!< GPIO x mode configuration */ +/*!< IOMC8 configuration */ #define GPIO_CFGHR_IOMC8_Pos (0U) #define GPIO_CFGHR_IOMC8_Msk (0x3U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000003 */ #define GPIO_CFGHR_IOMC8 GPIO_CFGHR_IOMC8_Msk /*!< IOMC8[1:0] bits (GPIO x mode configuration, pin 8) */ #define GPIO_CFGHR_IOMC8_0 (0x1U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000001 */ #define GPIO_CFGHR_IOMC8_1 (0x2U << GPIO_CFGHR_IOMC8_Pos) /*!< 0x00000002 */ +/*!< IOMC9 configuration */ #define GPIO_CFGHR_IOMC9_Pos (4U) #define GPIO_CFGHR_IOMC9_Msk (0x3U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000030 */ #define GPIO_CFGHR_IOMC9 GPIO_CFGHR_IOMC9_Msk /*!< IOMC9[1:0] bits (GPIO x mode configuration, pin 9) */ #define GPIO_CFGHR_IOMC9_0 (0x1U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000010 */ #define GPIO_CFGHR_IOMC9_1 (0x2U << GPIO_CFGHR_IOMC9_Pos) /*!< 0x00000020 */ +/*!< IOMC10 configuration */ #define GPIO_CFGHR_IOMC10_Pos (8U) #define GPIO_CFGHR_IOMC10_Msk (0x3U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000300 */ #define GPIO_CFGHR_IOMC10 GPIO_CFGHR_IOMC10_Msk /*!< IOMC10[1:0] bits (GPIO x mode configuration, pin 10) */ #define GPIO_CFGHR_IOMC10_0 (0x1U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000100 */ #define GPIO_CFGHR_IOMC10_1 (0x2U << GPIO_CFGHR_IOMC10_Pos) /*!< 0x00000200 */ +/*!< IOMC11 configuration */ #define GPIO_CFGHR_IOMC11_Pos (12U) #define GPIO_CFGHR_IOMC11_Msk (0x3U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00003000 */ #define GPIO_CFGHR_IOMC11 GPIO_CFGHR_IOMC11_Msk /*!< IOMC11[1:0] bits (GPIO x mode configuration, pin 11) */ #define GPIO_CFGHR_IOMC11_0 (0x1U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00001000 */ #define GPIO_CFGHR_IOMC11_1 (0x2U << GPIO_CFGHR_IOMC11_Pos) /*!< 0x00002000 */ +/*!< IOMC12 configuration */ #define GPIO_CFGHR_IOMC12_Pos (16U) #define GPIO_CFGHR_IOMC12_Msk (0x3U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00030000 */ #define GPIO_CFGHR_IOMC12 GPIO_CFGHR_IOMC12_Msk /*!< IOMC12[1:0] bits (GPIO x mode configuration, pin 12) */ #define GPIO_CFGHR_IOMC12_0 (0x1U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00010000 */ #define GPIO_CFGHR_IOMC12_1 (0x2U << GPIO_CFGHR_IOMC12_Pos) /*!< 0x00020000 */ +/*!< IOMC13 configuration */ #define GPIO_CFGHR_IOMC13_Pos (20U) #define GPIO_CFGHR_IOMC13_Msk (0x3U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00300000 */ #define GPIO_CFGHR_IOMC13 GPIO_CFGHR_IOMC13_Msk /*!< IOMC13[1:0] bits (GPIO x mode configuration, pin 13) */ #define GPIO_CFGHR_IOMC13_0 (0x1U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00100000 */ #define GPIO_CFGHR_IOMC13_1 (0x2U << GPIO_CFGHR_IOMC13_Pos) /*!< 0x00200000 */ +/*!< IOMC14 configuration */ #define GPIO_CFGHR_IOMC14_Pos (24U) #define GPIO_CFGHR_IOMC14_Msk (0x3U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x03000000 */ #define GPIO_CFGHR_IOMC14 GPIO_CFGHR_IOMC14_Msk /*!< IOMC14[1:0] bits (GPIO x mode configuration, pin 14) */ #define GPIO_CFGHR_IOMC14_0 (0x1U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x01000000 */ #define GPIO_CFGHR_IOMC14_1 (0x2U << GPIO_CFGHR_IOMC14_Pos) /*!< 0x02000000 */ +/*!< IOMC15 configuration */ #define GPIO_CFGHR_IOMC15_Pos (28U) #define GPIO_CFGHR_IOMC15_Msk (0x3U << GPIO_CFGHR_IOMC15_Pos) /*!< 0x30000000 */ #define GPIO_CFGHR_IOMC15 GPIO_CFGHR_IOMC15_Msk /*!< IOMC15[1:0] bits (GPIO x mode configuration, pin 15) */ @@ -2097,48 +2112,56 @@ typedef struct #define GPIO_CFGHR_IOFC_Msk (0x33333333U << GPIO_CFGHR_IOFC_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CFGHR_IOFC GPIO_CFGHR_IOFC_Msk /*!< GPIO x function configuration */ +/*!< IOFC8 configuration */ #define GPIO_CFGHR_IOFC8_Pos (2U) #define GPIO_CFGHR_IOFC8_Msk (0x3U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x0000000C */ #define GPIO_CFGHR_IOFC8 GPIO_CFGHR_IOFC8_Msk /*!< IOFC8[1:0] bits (GPIO x function configuration, pin 8) */ #define GPIO_CFGHR_IOFC8_0 (0x1U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000004 */ #define GPIO_CFGHR_IOFC8_1 (0x2U << GPIO_CFGHR_IOFC8_Pos) /*!< 0x00000008 */ +/*!< IOFC9 configuration */ #define GPIO_CFGHR_IOFC9_Pos (6U) #define GPIO_CFGHR_IOFC9_Msk (0x3U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x000000C0 */ #define GPIO_CFGHR_IOFC9 GPIO_CFGHR_IOFC9_Msk /*!< IOFC9[1:0] bits (GPIO x function configuration, pin 9) */ #define GPIO_CFGHR_IOFC9_0 (0x1U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000040 */ #define GPIO_CFGHR_IOFC9_1 (0x2U << GPIO_CFGHR_IOFC9_Pos) /*!< 0x00000080 */ +/*!< IOFC10 configuration */ #define GPIO_CFGHR_IOFC10_Pos (10U) #define GPIO_CFGHR_IOFC10_Msk (0x3U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000C00 */ #define GPIO_CFGHR_IOFC10 GPIO_CFGHR_IOFC10_Msk /*!< IOFC10[1:0] bits (GPIO x function configuration, pin 10) */ #define GPIO_CFGHR_IOFC10_0 (0x1U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000400 */ #define GPIO_CFGHR_IOFC10_1 (0x2U << GPIO_CFGHR_IOFC10_Pos) /*!< 0x00000800 */ +/*!< IOFC11 configuration */ #define GPIO_CFGHR_IOFC11_Pos (14U) #define GPIO_CFGHR_IOFC11_Msk (0x3U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x0000C000 */ #define GPIO_CFGHR_IOFC11 GPIO_CFGHR_IOFC11_Msk /*!< IOFC11[1:0] bits (GPIO x function configuration, pin 11) */ #define GPIO_CFGHR_IOFC11_0 (0x1U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00004000 */ #define GPIO_CFGHR_IOFC11_1 (0x2U << GPIO_CFGHR_IOFC11_Pos) /*!< 0x00008000 */ +/*!< IOFC12 configuration */ #define GPIO_CFGHR_IOFC12_Pos (18U) #define GPIO_CFGHR_IOFC12_Msk (0x3U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x000C0000 */ #define GPIO_CFGHR_IOFC12 GPIO_CFGHR_IOFC12_Msk /*!< IOFC12[1:0] bits (GPIO x function configuration, pin 12) */ #define GPIO_CFGHR_IOFC12_0 (0x1U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00040000 */ #define GPIO_CFGHR_IOFC12_1 (0x2U << GPIO_CFGHR_IOFC12_Pos) /*!< 0x00080000 */ +/*!< IOFC13 configuration */ #define GPIO_CFGHR_IOFC13_Pos (22U) #define GPIO_CFGHR_IOFC13_Msk (0x3U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00C00000 */ #define GPIO_CFGHR_IOFC13 GPIO_CFGHR_IOFC13_Msk /*!< IOFC13[1:0] bits (GPIO x function configuration, pin 13) */ #define GPIO_CFGHR_IOFC13_0 (0x1U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00400000 */ #define GPIO_CFGHR_IOFC13_1 (0x2U << GPIO_CFGHR_IOFC13_Pos) /*!< 0x00800000 */ +/*!< IOFC14 configuration */ #define GPIO_CFGHR_IOFC14_Pos (26U) #define GPIO_CFGHR_IOFC14_Msk (0x3U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x0C000000 */ #define GPIO_CFGHR_IOFC14 GPIO_CFGHR_IOFC14_Msk /*!< IOFC14[1:0] bits (GPIO x function configuration, pin 14) */ #define GPIO_CFGHR_IOFC14_0 (0x1U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x04000000 */ #define GPIO_CFGHR_IOFC14_1 (0x2U << GPIO_CFGHR_IOFC14_Pos) /*!< 0x08000000 */ +/*!< IOFC15 configuration */ #define GPIO_CFGHR_IOFC15_Pos (30U) #define GPIO_CFGHR_IOFC15_Msk (0x3U << GPIO_CFGHR_IOFC15_Pos) /*!< 0xC0000000 */ #define GPIO_CFGHR_IOFC15 GPIO_CFGHR_IOFC15_Msk /*!< IOFC15[1:0] bits (GPIO x function configuration, pin 15) */ @@ -2148,300 +2171,300 @@ typedef struct /*!<**************** Bit definition for GPIO_IDT register *******************/ #define GPIO_IDT_IDT0_Pos (0U) #define GPIO_IDT_IDT0_Msk (0x1U << GPIO_IDT_IDT0_Pos) /*!< 0x00000001 */ -#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, bit 0 */ +#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, pin 0 */ #define GPIO_IDT_IDT1_Pos (1U) #define GPIO_IDT_IDT1_Msk (0x1U << GPIO_IDT_IDT1_Pos) /*!< 0x00000002 */ -#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, bit 1 */ +#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, pin 1 */ #define GPIO_IDT_IDT2_Pos (2U) #define GPIO_IDT_IDT2_Msk (0x1U << GPIO_IDT_IDT2_Pos) /*!< 0x00000004 */ -#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, bit 2 */ +#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, pin 2 */ #define GPIO_IDT_IDT3_Pos (3U) #define GPIO_IDT_IDT3_Msk (0x1U << GPIO_IDT_IDT3_Pos) /*!< 0x00000008 */ -#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, bit 3 */ +#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, pin 3 */ #define GPIO_IDT_IDT4_Pos (4U) #define GPIO_IDT_IDT4_Msk (0x1U << GPIO_IDT_IDT4_Pos) /*!< 0x00000010 */ -#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, bit 4 */ +#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, pin 4 */ #define GPIO_IDT_IDT5_Pos (5U) #define GPIO_IDT_IDT5_Msk (0x1U << GPIO_IDT_IDT5_Pos) /*!< 0x00000020 */ -#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, bit 5 */ +#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, pin 5 */ #define GPIO_IDT_IDT6_Pos (6U) #define GPIO_IDT_IDT6_Msk (0x1U << GPIO_IDT_IDT6_Pos) /*!< 0x00000040 */ -#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, bit 6 */ +#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, pin 6 */ #define GPIO_IDT_IDT7_Pos (7U) #define GPIO_IDT_IDT7_Msk (0x1U << GPIO_IDT_IDT7_Pos) /*!< 0x00000080 */ -#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, bit 7 */ +#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, pin 7 */ #define GPIO_IDT_IDT8_Pos (8U) #define GPIO_IDT_IDT8_Msk (0x1U << GPIO_IDT_IDT8_Pos) /*!< 0x00000100 */ -#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, bit 8 */ +#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, pin 8 */ #define GPIO_IDT_IDT9_Pos (9U) #define GPIO_IDT_IDT9_Msk (0x1U << GPIO_IDT_IDT9_Pos) /*!< 0x00000200 */ -#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, bit 9 */ +#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, pin 9 */ #define GPIO_IDT_IDT10_Pos (10U) #define GPIO_IDT_IDT10_Msk (0x1U << GPIO_IDT_IDT10_Pos) /*!< 0x00000400 */ -#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, bit 10 */ +#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, pin 10 */ #define GPIO_IDT_IDT11_Pos (11U) #define GPIO_IDT_IDT11_Msk (0x1U << GPIO_IDT_IDT11_Pos) /*!< 0x00000800 */ -#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, bit 11 */ +#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, pin 11 */ #define GPIO_IDT_IDT12_Pos (12U) #define GPIO_IDT_IDT12_Msk (0x1U << GPIO_IDT_IDT12_Pos) /*!< 0x00001000 */ -#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, bit 12 */ +#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, pin 12 */ #define GPIO_IDT_IDT13_Pos (13U) #define GPIO_IDT_IDT13_Msk (0x1U << GPIO_IDT_IDT13_Pos) /*!< 0x00002000 */ -#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, bit 13 */ +#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, pin 13 */ #define GPIO_IDT_IDT14_Pos (14U) #define GPIO_IDT_IDT14_Msk (0x1U << GPIO_IDT_IDT14_Pos) /*!< 0x00004000 */ -#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, bit 14 */ +#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, pin 14 */ #define GPIO_IDT_IDT15_Pos (15U) #define GPIO_IDT_IDT15_Msk (0x1U << GPIO_IDT_IDT15_Pos) /*!< 0x00008000 */ -#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, bit 15 */ +#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, pin 15 */ /******************* Bit definition for GPIO_ODT register *******************/ #define GPIO_ODT_ODT0_Pos (0U) #define GPIO_ODT_ODT0_Msk (0x1U << GPIO_ODT_ODT0_Pos) /*!< 0x00000001 */ -#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, bit 0 */ +#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, pin 0 */ #define GPIO_ODT_ODT1_Pos (1U) #define GPIO_ODT_ODT1_Msk (0x1U << GPIO_ODT_ODT1_Pos) /*!< 0x00000002 */ -#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, bit 1 */ +#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, pin 1 */ #define GPIO_ODT_ODT2_Pos (2U) #define GPIO_ODT_ODT2_Msk (0x1U << GPIO_ODT_ODT2_Pos) /*!< 0x00000004 */ -#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, bit 2 */ +#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, pin 2 */ #define GPIO_ODT_ODT3_Pos (3U) #define GPIO_ODT_ODT3_Msk (0x1U << GPIO_ODT_ODT3_Pos) /*!< 0x00000008 */ -#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, bit 3 */ +#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, pin 3 */ #define GPIO_ODT_ODT4_Pos (4U) #define GPIO_ODT_ODT4_Msk (0x1U << GPIO_ODT_ODT4_Pos) /*!< 0x00000010 */ -#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, bit 4 */ +#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, pin 4 */ #define GPIO_ODT_ODT5_Pos (5U) #define GPIO_ODT_ODT5_Msk (0x1U << GPIO_ODT_ODT5_Pos) /*!< 0x00000020 */ -#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, bit 5 */ +#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, pin 5 */ #define GPIO_ODT_ODT6_Pos (6U) #define GPIO_ODT_ODT6_Msk (0x1U << GPIO_ODT_ODT6_Pos) /*!< 0x00000040 */ -#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, bit 6 */ +#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, pin 6 */ #define GPIO_ODT_ODT7_Pos (7U) #define GPIO_ODT_ODT7_Msk (0x1U << GPIO_ODT_ODT7_Pos) /*!< 0x00000080 */ -#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, bit 7 */ +#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, pin 7 */ #define GPIO_ODT_ODT8_Pos (8U) #define GPIO_ODT_ODT8_Msk (0x1U << GPIO_ODT_ODT8_Pos) /*!< 0x00000100 */ -#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, bit 8 */ +#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, pin 8 */ #define GPIO_ODT_ODT9_Pos (9U) #define GPIO_ODT_ODT9_Msk (0x1U << GPIO_ODT_ODT9_Pos) /*!< 0x00000200 */ -#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, bit 9 */ +#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, pin 9 */ #define GPIO_ODT_ODT10_Pos (10U) #define GPIO_ODT_ODT10_Msk (0x1U << GPIO_ODT_ODT10_Pos) /*!< 0x00000400 */ -#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, bit 10 */ +#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, pin 10 */ #define GPIO_ODT_ODT11_Pos (11U) #define GPIO_ODT_ODT11_Msk (0x1U << GPIO_ODT_ODT11_Pos) /*!< 0x00000800 */ -#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, bit 11 */ +#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, pin 11 */ #define GPIO_ODT_ODT12_Pos (12U) #define GPIO_ODT_ODT12_Msk (0x1U << GPIO_ODT_ODT12_Pos) /*!< 0x00001000 */ -#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, bit 12 */ +#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, pin 12 */ #define GPIO_ODT_ODT13_Pos (13U) #define GPIO_ODT_ODT13_Msk (0x1U << GPIO_ODT_ODT13_Pos) /*!< 0x00002000 */ -#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, bit 13 */ +#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, pin 13 */ #define GPIO_ODT_ODT14_Pos (14U) #define GPIO_ODT_ODT14_Msk (0x1U << GPIO_ODT_ODT14_Pos) /*!< 0x00004000 */ -#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, bit 14 */ +#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, pin 14 */ #define GPIO_ODT_ODT15_Pos (15U) #define GPIO_ODT_ODT15_Msk (0x1U << GPIO_ODT_ODT15_Pos) /*!< 0x00008000 */ -#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, bit 15 */ +#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, pin 15 */ /******************* Bit definition for GPIO_SCR register *******************/ #define GPIO_SCR_IOSB0_Pos (0U) #define GPIO_SCR_IOSB0_Msk (0x1U << GPIO_SCR_IOSB0_Pos) /*!< 0x00000001 */ -#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit 0 */ +#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit, pin 0 */ #define GPIO_SCR_IOSB1_Pos (1U) #define GPIO_SCR_IOSB1_Msk (0x1U << GPIO_SCR_IOSB1_Pos) /*!< 0x00000002 */ -#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit 1 */ +#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit, pin 1 */ #define GPIO_SCR_IOSB2_Pos (2U) #define GPIO_SCR_IOSB2_Msk (0x1U << GPIO_SCR_IOSB2_Pos) /*!< 0x00000004 */ -#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit 2 */ +#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit, pin 2 */ #define GPIO_SCR_IOSB3_Pos (3U) #define GPIO_SCR_IOSB3_Msk (0x1U << GPIO_SCR_IOSB3_Pos) /*!< 0x00000008 */ -#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit 3 */ +#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit, pin 3 */ #define GPIO_SCR_IOSB4_Pos (4U) #define GPIO_SCR_IOSB4_Msk (0x1U << GPIO_SCR_IOSB4_Pos) /*!< 0x00000010 */ -#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit 4 */ +#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit, pin 4 */ #define GPIO_SCR_IOSB5_Pos (5U) #define GPIO_SCR_IOSB5_Msk (0x1U << GPIO_SCR_IOSB5_Pos) /*!< 0x00000020 */ -#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit 5 */ +#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit, pin 5 */ #define GPIO_SCR_IOSB6_Pos (6U) #define GPIO_SCR_IOSB6_Msk (0x1U << GPIO_SCR_IOSB6_Pos) /*!< 0x00000040 */ -#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit 6 */ +#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit, pin 6 */ #define GPIO_SCR_IOSB7_Pos (7U) #define GPIO_SCR_IOSB7_Msk (0x1U << GPIO_SCR_IOSB7_Pos) /*!< 0x00000080 */ -#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit 7 */ +#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit, pin 7 */ #define GPIO_SCR_IOSB8_Pos (8U) #define GPIO_SCR_IOSB8_Msk (0x1U << GPIO_SCR_IOSB8_Pos) /*!< 0x00000100 */ -#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit 8 */ +#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit, pin 8 */ #define GPIO_SCR_IOSB9_Pos (9U) #define GPIO_SCR_IOSB9_Msk (0x1U << GPIO_SCR_IOSB9_Pos) /*!< 0x00000200 */ -#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit 9 */ +#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit, pin 9 */ #define GPIO_SCR_IOSB10_Pos (10U) #define GPIO_SCR_IOSB10_Msk (0x1U << GPIO_SCR_IOSB10_Pos) /*!< 0x00000400 */ -#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit 10 */ +#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit, pin 10 */ #define GPIO_SCR_IOSB11_Pos (11U) #define GPIO_SCR_IOSB11_Msk (0x1U << GPIO_SCR_IOSB11_Pos) /*!< 0x00000800 */ -#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit 11 */ +#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit, pin 11 */ #define GPIO_SCR_IOSB12_Pos (12U) #define GPIO_SCR_IOSB12_Msk (0x1U << GPIO_SCR_IOSB12_Pos) /*!< 0x00001000 */ -#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit 12 */ +#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit, pin 12 */ #define GPIO_SCR_IOSB13_Pos (13U) #define GPIO_SCR_IOSB13_Msk (0x1U << GPIO_SCR_IOSB13_Pos) /*!< 0x00002000 */ -#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit 13 */ +#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit, pin 13 */ #define GPIO_SCR_IOSB14_Pos (14U) #define GPIO_SCR_IOSB14_Msk (0x1U << GPIO_SCR_IOSB14_Pos) /*!< 0x00004000 */ -#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit 14 */ +#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit, pin 14 */ #define GPIO_SCR_IOSB15_Pos (15U) #define GPIO_SCR_IOSB15_Msk (0x1U << GPIO_SCR_IOSB15_Pos) /*!< 0x00008000 */ -#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit 15 */ +#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit, pin 15 */ #define GPIO_SCR_IOCB0_Pos (16U) #define GPIO_SCR_IOCB0_Msk (0x1U << GPIO_SCR_IOCB0_Pos) /*!< 0x00010000 */ -#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ #define GPIO_SCR_IOCB1_Pos (17U) #define GPIO_SCR_IOCB1_Msk (0x1U << GPIO_SCR_IOCB1_Pos) /*!< 0x00020000 */ -#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ #define GPIO_SCR_IOCB2_Pos (18U) #define GPIO_SCR_IOCB2_Msk (0x1U << GPIO_SCR_IOCB2_Pos) /*!< 0x00040000 */ -#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ #define GPIO_SCR_IOCB3_Pos (19U) #define GPIO_SCR_IOCB3_Msk (0x1U << GPIO_SCR_IOCB3_Pos) /*!< 0x00080000 */ -#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ #define GPIO_SCR_IOCB4_Pos (20U) #define GPIO_SCR_IOCB4_Msk (0x1U << GPIO_SCR_IOCB4_Pos) /*!< 0x00100000 */ -#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ #define GPIO_SCR_IOCB5_Pos (21U) #define GPIO_SCR_IOCB5_Msk (0x1U << GPIO_SCR_IOCB5_Pos) /*!< 0x00200000 */ -#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ #define GPIO_SCR_IOCB6_Pos (22U) #define GPIO_SCR_IOCB6_Msk (0x1U << GPIO_SCR_IOCB6_Pos) /*!< 0x00400000 */ -#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ #define GPIO_SCR_IOCB7_Pos (23U) #define GPIO_SCR_IOCB7_Msk (0x1U << GPIO_SCR_IOCB7_Pos) /*!< 0x00800000 */ -#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ #define GPIO_SCR_IOCB8_Pos (24U) #define GPIO_SCR_IOCB8_Msk (0x1U << GPIO_SCR_IOCB8_Pos) /*!< 0x01000000 */ -#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ #define GPIO_SCR_IOCB9_Pos (25U) #define GPIO_SCR_IOCB9_Msk (0x1U << GPIO_SCR_IOCB9_Pos) /*!< 0x02000000 */ -#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ #define GPIO_SCR_IOCB10_Pos (26U) #define GPIO_SCR_IOCB10_Msk (0x1U << GPIO_SCR_IOCB10_Pos) /*!< 0x04000000 */ -#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ #define GPIO_SCR_IOCB11_Pos (27U) #define GPIO_SCR_IOCB11_Msk (0x1U << GPIO_SCR_IOCB11_Pos) /*!< 0x08000000 */ -#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ #define GPIO_SCR_IOCB12_Pos (28U) #define GPIO_SCR_IOCB12_Msk (0x1U << GPIO_SCR_IOCB12_Pos) /*!< 0x10000000 */ -#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ #define GPIO_SCR_IOCB13_Pos (29U) #define GPIO_SCR_IOCB13_Msk (0x1U << GPIO_SCR_IOCB13_Pos) /*!< 0x20000000 */ -#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ #define GPIO_SCR_IOCB14_Pos (30U) #define GPIO_SCR_IOCB14_Msk (0x1U << GPIO_SCR_IOCB14_Pos) /*!< 0x40000000 */ -#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ #define GPIO_SCR_IOCB15_Pos (31U) #define GPIO_SCR_IOCB15_Msk (0x1U << GPIO_SCR_IOCB15_Pos) /*!< 0x80000000 */ -#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit 15 */ +#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ /******************* Bit definition for GPIO_CLR register *******************/ #define GPIO_CLR_IOCB0_Pos (0U) #define GPIO_CLR_IOCB0_Msk (0x1U << GPIO_CLR_IOCB0_Pos) /*!< 0x00000001 */ -#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit 0 */ +#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ #define GPIO_CLR_IOCB1_Pos (1U) #define GPIO_CLR_IOCB1_Msk (0x1U << GPIO_CLR_IOCB1_Pos) /*!< 0x00000002 */ -#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit 1 */ +#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ #define GPIO_CLR_IOCB2_Pos (2U) #define GPIO_CLR_IOCB2_Msk (0x1U << GPIO_CLR_IOCB2_Pos) /*!< 0x00000004 */ -#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit 2 */ +#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ #define GPIO_CLR_IOCB3_Pos (3U) #define GPIO_CLR_IOCB3_Msk (0x1U << GPIO_CLR_IOCB3_Pos) /*!< 0x00000008 */ -#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit 3 */ +#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ #define GPIO_CLR_IOCB4_Pos (4U) #define GPIO_CLR_IOCB4_Msk (0x1U << GPIO_CLR_IOCB4_Pos) /*!< 0x00000010 */ -#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit 4 */ +#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ #define GPIO_CLR_IOCB5_Pos (5U) #define GPIO_CLR_IOCB5_Msk (0x1U << GPIO_CLR_IOCB5_Pos) /*!< 0x00000020 */ -#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit 5 */ +#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ #define GPIO_CLR_IOCB6_Pos (6U) #define GPIO_CLR_IOCB6_Msk (0x1U << GPIO_CLR_IOCB6_Pos) /*!< 0x00000040 */ -#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit 6 */ +#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ #define GPIO_CLR_IOCB7_Pos (7U) #define GPIO_CLR_IOCB7_Msk (0x1U << GPIO_CLR_IOCB7_Pos) /*!< 0x00000080 */ -#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit 7 */ +#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ #define GPIO_CLR_IOCB8_Pos (8U) #define GPIO_CLR_IOCB8_Msk (0x1U << GPIO_CLR_IOCB8_Pos) /*!< 0x00000100 */ -#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit 8 */ +#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ #define GPIO_CLR_IOCB9_Pos (9U) #define GPIO_CLR_IOCB9_Msk (0x1U << GPIO_CLR_IOCB9_Pos) /*!< 0x00000200 */ -#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit 9 */ +#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ #define GPIO_CLR_IOCB10_Pos (10U) #define GPIO_CLR_IOCB10_Msk (0x1U << GPIO_CLR_IOCB10_Pos) /*!< 0x00000400 */ -#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit 10 */ +#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ #define GPIO_CLR_IOCB11_Pos (11U) #define GPIO_CLR_IOCB11_Msk (0x1U << GPIO_CLR_IOCB11_Pos) /*!< 0x00000800 */ -#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit 11 */ +#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ #define GPIO_CLR_IOCB12_Pos (12U) #define GPIO_CLR_IOCB12_Msk (0x1U << GPIO_CLR_IOCB12_Pos) /*!< 0x00001000 */ -#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit 12 */ +#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ #define GPIO_CLR_IOCB13_Pos (13U) #define GPIO_CLR_IOCB13_Msk (0x1U << GPIO_CLR_IOCB13_Pos) /*!< 0x00002000 */ -#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit 13 */ +#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ #define GPIO_CLR_IOCB14_Pos (14U) #define GPIO_CLR_IOCB14_Msk (0x1U << GPIO_CLR_IOCB14_Pos) /*!< 0x00004000 */ -#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit 14 */ +#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ #define GPIO_CLR_IOCB15_Pos (15U) #define GPIO_CLR_IOCB15_Msk (0x1U << GPIO_CLR_IOCB15_Pos) /*!< 0x00008000 */ -#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit 15 */ +#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ /******************* Bit definition for GPIO_WPR register *******************/ #define GPIO_WPR_WPEN0_Pos (0U) #define GPIO_WPR_WPEN0_Msk (0x1U << GPIO_WPR_WPEN0_Pos) /*!< 0x00000001 */ -#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable bit 0 */ +#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable, pin 0 */ #define GPIO_WPR_WPEN1_Pos (1U) #define GPIO_WPR_WPEN1_Msk (0x1U << GPIO_WPR_WPEN1_Pos) /*!< 0x00000002 */ -#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable bit 1 */ +#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable, pin 1 */ #define GPIO_WPR_WPEN2_Pos (2U) #define GPIO_WPR_WPEN2_Msk (0x1U << GPIO_WPR_WPEN2_Pos) /*!< 0x00000004 */ -#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable bit 2 */ +#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable, pin 2 */ #define GPIO_WPR_WPEN3_Pos (3U) #define GPIO_WPR_WPEN3_Msk (0x1U << GPIO_WPR_WPEN3_Pos) /*!< 0x00000008 */ -#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable bit 3 */ +#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable, pin 3 */ #define GPIO_WPR_WPEN4_Pos (4U) #define GPIO_WPR_WPEN4_Msk (0x1U << GPIO_WPR_WPEN4_Pos) /*!< 0x00000010 */ -#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable bit 4 */ +#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable, pin 4 */ #define GPIO_WPR_WPEN5_Pos (5U) #define GPIO_WPR_WPEN5_Msk (0x1U << GPIO_WPR_WPEN5_Pos) /*!< 0x00000020 */ -#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable bit 5 */ +#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable, pin 5 */ #define GPIO_WPR_WPEN6_Pos (6U) #define GPIO_WPR_WPEN6_Msk (0x1U << GPIO_WPR_WPEN6_Pos) /*!< 0x00000040 */ -#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable bit 6 */ +#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable, pin 6 */ #define GPIO_WPR_WPEN7_Pos (7U) #define GPIO_WPR_WPEN7_Msk (0x1U << GPIO_WPR_WPEN7_Pos) /*!< 0x00000080 */ -#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable bit 7 */ +#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable, pin 7 */ #define GPIO_WPR_WPEN8_Pos (8U) #define GPIO_WPR_WPEN8_Msk (0x1U << GPIO_WPR_WPEN8_Pos) /*!< 0x00000100 */ -#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable bit 8 */ +#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable, pin 8 */ #define GPIO_WPR_WPEN9_Pos (9U) #define GPIO_WPR_WPEN9_Msk (0x1U << GPIO_WPR_WPEN9_Pos) /*!< 0x00000200 */ -#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable bit 9 */ +#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable, pin 9 */ #define GPIO_WPR_WPEN10_Pos (10U) #define GPIO_WPR_WPEN10_Msk (0x1U << GPIO_WPR_WPEN10_Pos) /*!< 0x00000400 */ -#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable bit 10 */ +#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable, pin 10 */ #define GPIO_WPR_WPEN11_Pos (11U) #define GPIO_WPR_WPEN11_Msk (0x1U << GPIO_WPR_WPEN11_Pos) /*!< 0x00000800 */ -#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable bit 11 */ +#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable, pin 11 */ #define GPIO_WPR_WPEN12_Pos (12U) #define GPIO_WPR_WPEN12_Msk (0x1U << GPIO_WPR_WPEN12_Pos) /*!< 0x00001000 */ -#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable bit 12 */ +#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable, pin 12 */ #define GPIO_WPR_WPEN13_Pos (13U) #define GPIO_WPR_WPEN13_Msk (0x1U << GPIO_WPR_WPEN13_Pos) /*!< 0x00002000 */ -#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable bit 13 */ +#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable, pin 13 */ #define GPIO_WPR_WPEN14_Pos (14U) #define GPIO_WPR_WPEN14_Msk (0x1U << GPIO_WPR_WPEN14_Pos) /*!< 0x00004000 */ -#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable bit 14 */ +#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable, pin 14 */ #define GPIO_WPR_WPEN15_Pos (15U) #define GPIO_WPR_WPEN15_Msk (0x1U << GPIO_WPR_WPEN15_Pos) /*!< 0x00008000 */ -#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable bit 15 */ +#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable, pin 15 */ #define GPIO_WPR_WPSEQ_Pos (16U) #define GPIO_WPR_WPSEQ_Msk (0x1U << GPIO_WPR_WPSEQ_Pos) /*!< 0x00010000 */ #define GPIO_WPR_WPSEQ GPIO_WPR_WPSEQ_Msk /*!< Write protect sequence */ @@ -2536,7 +2559,6 @@ typedef struct #define IOMUX_EVTOUT_EVOEN IOMUX_EVTOUT_EVOEN_Msk /*!< Event output enable */ /***************** Bit definition for IOMUX_REMAP register ******************/ -/*!< SPI1_MUX configuration */ #define IOMUX_REMAP_SPI1_MUX_Pos (0U) #define IOMUX_REMAP_SPI1_MUX_Msk (0x1U << IOMUX_REMAP_SPI1_MUX_Pos) /*!< 0x00000001 */ #define IOMUX_REMAP_SPI1_MUX IOMUX_REMAP_SPI1_MUX_Msk /*!< SPI1 IO multiplexing */ @@ -4126,18 +4148,21 @@ typedef struct #define DMA_CCTRL_MINCM_Msk (0x1U << DMA_CCTRL_MINCM_Pos) /*!< 0x00000080 */ #define DMA_CCTRL_MINCM DMA_CCTRL_MINCM_Msk /*!< Memory address increment mode */ +/*!< PWIDTH configuration */ #define DMA_CCTRL_PWIDTH_Pos (8U) #define DMA_CCTRL_PWIDTH_Msk (0x3U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000300 */ #define DMA_CCTRL_PWIDTH DMA_CCTRL_PWIDTH_Msk /*!< PWIDTH[1:0] bits (Peripheral data bit width) */ #define DMA_CCTRL_PWIDTH_0 (0x1U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000100 */ #define DMA_CCTRL_PWIDTH_1 (0x2U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000200 */ +/*!< MWIDTH configuration */ #define DMA_CCTRL_MWIDTH_Pos (10U) #define DMA_CCTRL_MWIDTH_Msk (0x3U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000C00 */ #define DMA_CCTRL_MWIDTH DMA_CCTRL_MWIDTH_Msk /*!< MWIDTH[1:0] bits (Memory data bit width) */ #define DMA_CCTRL_MWIDTH_0 (0x1U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000400 */ #define DMA_CCTRL_MWIDTH_1 (0x2U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000800 */ +/*!< CHPL configuration */ #define DMA_CCTRL_CHPL_Pos (12U) #define DMA_CCTRL_CHPL_Msk (0x3U << DMA_CCTRL_CHPL_Pos) /*!< 0x00003000 */ #define DMA_CCTRL_CHPL DMA_CCTRL_CHPL_Msk /*!< CHPL[1:0] bits(Channel priority level) */ @@ -4324,34 +4349,34 @@ typedef struct #define I2C_OADDR1_ADDR1_1_7 0x000000FEU /*!< Interface Address */ #define I2C_OADDR1_ADDR1_8_9 0x00000300U /*!< Interface Address */ -#define I2C_OADDR1_ADDR1_0_Pos (0U) +#define I2C_OADDR1_ADDR1_0_Pos (0U) #define I2C_OADDR1_ADDR1_0_Msk (0x1U << I2C_OADDR1_ADDR1_0_Pos) /*!< 0x00000001 */ #define I2C_OADDR1_ADDR1_0 I2C_OADDR1_ADDR1_0_Msk /*!< Bit 0 */ -#define I2C_OADDR1_ADDR1_1_Pos (1U) +#define I2C_OADDR1_ADDR1_1_Pos (1U) #define I2C_OADDR1_ADDR1_1_Msk (0x1U << I2C_OADDR1_ADDR1_1_Pos) /*!< 0x00000002 */ #define I2C_OADDR1_ADDR1_1 I2C_OADDR1_ADDR1_1_Msk /*!< Bit 1 */ -#define I2C_OADDR1_ADDR1_2_Pos (2U) +#define I2C_OADDR1_ADDR1_2_Pos (2U) #define I2C_OADDR1_ADDR1_2_Msk (0x1U << I2C_OADDR1_ADDR1_2_Pos) /*!< 0x00000004 */ #define I2C_OADDR1_ADDR1_2 I2C_OADDR1_ADDR1_2_Msk /*!< Bit 2 */ -#define I2C_OADDR1_ADDR1_3_Pos (3U) +#define I2C_OADDR1_ADDR1_3_Pos (3U) #define I2C_OADDR1_ADDR1_3_Msk (0x1U << I2C_OADDR1_ADDR1_3_Pos) /*!< 0x00000008 */ #define I2C_OADDR1_ADDR1_3 I2C_OADDR1_ADDR1_3_Msk /*!< Bit 3 */ -#define I2C_OADDR1_ADDR1_4_Pos (4U) +#define I2C_OADDR1_ADDR1_4_Pos (4U) #define I2C_OADDR1_ADDR1_4_Msk (0x1U << I2C_OADDR1_ADDR1_4_Pos) /*!< 0x00000010 */ #define I2C_OADDR1_ADDR1_4 I2C_OADDR1_ADDR1_4_Msk /*!< Bit 4 */ -#define I2C_OADDR1_ADDR1_5_Pos (5U) +#define I2C_OADDR1_ADDR1_5_Pos (5U) #define I2C_OADDR1_ADDR1_5_Msk (0x1U << I2C_OADDR1_ADDR1_5_Pos) /*!< 0x00000020 */ #define I2C_OADDR1_ADDR1_5 I2C_OADDR1_ADDR1_5_Msk /*!< Bit 5 */ -#define I2C_OADDR1_ADDR1_6_Pos (6U) +#define I2C_OADDR1_ADDR1_6_Pos (6U) #define I2C_OADDR1_ADDR1_6_Msk (0x1U << I2C_OADDR1_ADDR1_6_Pos) /*!< 0x00000040 */ #define I2C_OADDR1_ADDR1_6 I2C_OADDR1_ADDR1_6_Msk /*!< Bit 6 */ -#define I2C_OADDR1_ADDR1_7_Pos (7U) +#define I2C_OADDR1_ADDR1_7_Pos (7U) #define I2C_OADDR1_ADDR1_7_Msk (0x1U << I2C_OADDR1_ADDR1_7_Pos) /*!< 0x00000080 */ #define I2C_OADDR1_ADDR1_7 I2C_OADDR1_ADDR1_7_Msk /*!< Bit 7 */ -#define I2C_OADDR1_ADDR1_8_Pos (8U) +#define I2C_OADDR1_ADDR1_8_Pos (8U) #define I2C_OADDR1_ADDR1_8_Msk (0x1U << I2C_OADDR1_ADDR1_8_Pos) /*!< 0x00000100 */ #define I2C_OADDR1_ADDR1_8 I2C_OADDR1_ADDR1_8_Msk /*!< Bit 8 */ -#define I2C_OADDR1_ADDR1_9_Pos (9U) +#define I2C_OADDR1_ADDR1_9_Pos (9U) #define I2C_OADDR1_ADDR1_9_Msk (0x1U << I2C_OADDR1_ADDR1_9_Pos) /*!< 0x00000200 */ #define I2C_OADDR1_ADDR1_9 I2C_OADDR1_ADDR1_9_Msk /*!< Bit 9 */ @@ -4573,6 +4598,7 @@ typedef struct #define USART_CTRL2_CLKEN_Msk (0x1U << USART_CTRL2_CLKEN_Pos) /*!< 0x00000800 */ #define USART_CTRL2_CLKEN USART_CTRL2_CLKEN_Msk /*!< Clock enable */ +/*!< STOPBN configuration */ #define USART_CTRL2_STOPBN_Pos (12U) #define USART_CTRL2_STOPBN_Msk (0x3U << USART_CTRL2_STOPBN_Pos) /*!< 0x00003000 */ #define USART_CTRL2_STOPBN USART_CTRL2_STOPBN_Msk /*!< STOPBN[1:0] bits (STOP bit num) */ @@ -4619,6 +4645,7 @@ typedef struct #define USART_CTRL3_CTSCFIEN USART_CTRL3_CTSCFIEN_Msk /*!< CTSCF interrupt enable */ /****************** Bit definition for USART_GDIV register ******************/ +/*!< ISDIV configuration */ #define USART_GDIV_ISDIV_Pos (0U) #define USART_GDIV_ISDIV_Msk (0xFFU << USART_GDIV_ISDIV_Pos) /*!< 0x000000FF */ #define USART_GDIV_ISDIV USART_GDIV_ISDIV_Msk /*!< ISDIV[7:0] bits (IrDA/Smart Card division) */ @@ -4765,6 +4792,7 @@ typedef struct #define SPI_I2SCTRL_I2SCBN_Msk (0x1U << SPI_I2SCTRL_I2SCBN_Pos) /*!< 0x00000001 */ #define SPI_I2SCTRL_I2SCBN SPI_I2SCTRL_I2SCBN_Msk /*!< Channel length (I2S channel bit num) */ +/*!< I2SDBN configuration */ #define SPI_I2SCTRL_I2SDBN_Pos (1U) #define SPI_I2SCTRL_I2SDBN_Msk (0x3U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000006 */ #define SPI_I2SCTRL_I2SDBN SPI_I2SCTRL_I2SDBN_Msk /*!< I2SDBN[1:0] bits (I2S data bit num) */ @@ -4775,6 +4803,7 @@ typedef struct #define SPI_I2SCTRL_I2SCLKPOL_Msk (0x1U << SPI_I2SCTRL_I2SCLKPOL_Pos) /*!< 0x00000008 */ #define SPI_I2SCTRL_I2SCLKPOL SPI_I2SCTRL_I2SCLKPOL_Msk /*!< I2S clock polarity */ +/*!< STDSEL configuration */ #define SPI_I2SCTRL_STDSEL_Pos (4U) #define SPI_I2SCTRL_STDSEL_Msk (0x3U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000030 */ #define SPI_I2SCTRL_STDSEL SPI_I2SCTRL_STDSEL_Msk /*!< STDSEL[1:0] bits (I2S standard select) */ @@ -4785,6 +4814,7 @@ typedef struct #define SPI_I2SCTRL_PCMFSSEL_Msk (0x1U << SPI_I2SCTRL_PCMFSSEL_Pos) /*!< 0x00000080 */ #define SPI_I2SCTRL_PCMFSSEL SPI_I2SCTRL_PCMFSSEL_Msk /*!< PCM frame synchronization */ +/*!< OPERSEL configuration */ #define SPI_I2SCTRL_OPERSEL_Pos (8U) #define SPI_I2SCTRL_OPERSEL_Msk (0x3U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000300 */ #define SPI_I2SCTRL_OPERSEL SPI_I2SCTRL_OPERSEL_Msk /*!< OPERSEL[1:0] bits (I2S operation mode select) */ @@ -4815,6 +4845,7 @@ typedef struct /******************************************************************************/ /****************** Bit definition for WWDT_CTRL register *******************/ +/*!< CNT configuration */ #define WWDT_CTRL_CNT_Pos (0U) #define WWDT_CTRL_CNT_Msk (0x7FU << WWDT_CTRL_CNT_Pos) /*!< 0x0000007F */ #define WWDT_CTRL_CNT WWDT_CTRL_CNT_Msk /*!< CNT[6:0] bits (Down counter) */ @@ -4840,6 +4871,7 @@ typedef struct #define WWDT_CTRL_WWDTEN WWDT_CTRL_WWDTEN_Msk /*!< Window watchdog enable */ /******************* Bit definition for WWDT_CFG register *******************/ +/*!< WIN configuration */ #define WWDT_CFG_WIN_Pos (0U) #define WWDT_CFG_WIN_Msk (0x7FU << WWDT_CFG_WIN_Pos) /*!< 0x0000007F */ #define WWDT_CFG_WIN WWDT_CFG_WIN_Msk /*!< WIN[6:0] bits (Window value) */ @@ -4860,6 +4892,7 @@ typedef struct #define WWDT_CFG_WIN5 WWDT_CFG_WIN_5 #define WWDT_CFG_WIN6 WWDT_CFG_WIN_6 +/*!< DIV configuration */ #define WWDT_CFG_DIV_Pos (7U) #define WWDT_CFG_DIV_Msk (0x3U << WWDT_CFG_DIV_Pos) /*!< 0x00000180 */ #define WWDT_CFG_DIV WWDT_CFG_DIV_Msk /*!< DIV[1:0] bits (Clock division value) */ @@ -4891,6 +4924,7 @@ typedef struct #define WDT_CMD_CMD WDT_CMD_CMD_Msk /*!< Command register */ /******************* Bit definition for WDT_DIV register ********************/ +/*!< DIV configuration */ #define WDT_DIV_DIV_Pos (0U) #define WDT_DIV_DIV_Msk (0x7U << WDT_DIV_DIV_Pos) /*!< 0x00000007 */ #define WDT_DIV_DIV WDT_DIV_DIV_Msk /*!< DIV[2:0] (Clock division value) */ @@ -4918,6 +4952,7 @@ typedef struct /******************************************************************************/ /****************** Bit definition for ERTC_TIME register *******************/ +/*!< SU configuration */ #define ERTC_TIME_SU_Pos (0U) #define ERTC_TIME_SU_Msk (0xFU << ERTC_TIME_SU_Pos) /*!< 0x0000000F */ #define ERTC_TIME_SU ERTC_TIME_SU_Msk /*!< SU[3:0] (Second units) */ @@ -4926,6 +4961,7 @@ typedef struct #define ERTC_TIME_SU_2 (0x4U << ERTC_TIME_SU_Pos) /*!< 0x00000004 */ #define ERTC_TIME_SU_3 (0x8U << ERTC_TIME_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_TIME_ST_Pos (4U) #define ERTC_TIME_ST_Msk (0x7U << ERTC_TIME_ST_Pos) /*!< 0x00000070 */ #define ERTC_TIME_ST ERTC_TIME_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -4933,6 +4969,7 @@ typedef struct #define ERTC_TIME_ST_1 (0x2U << ERTC_TIME_ST_Pos) /*!< 0x00000020 */ #define ERTC_TIME_ST_2 (0x4U << ERTC_TIME_ST_Pos) /*!< 0x00000040 */ +/*!< MU configuration */ #define ERTC_TIME_MU_Pos (8U) #define ERTC_TIME_MU_Msk (0xFU << ERTC_TIME_MU_Pos) /*!< 0x00000F00 */ #define ERTC_TIME_MU ERTC_TIME_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -4941,6 +4978,7 @@ typedef struct #define ERTC_TIME_MU_2 (0x4U << ERTC_TIME_MU_Pos) /*!< 0x00000400 */ #define ERTC_TIME_MU_3 (0x8U << ERTC_TIME_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_TIME_MT_Pos (12U) #define ERTC_TIME_MT_Msk (0x7U << ERTC_TIME_MT_Pos) /*!< 0x00007000 */ #define ERTC_TIME_MT ERTC_TIME_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -4948,6 +4986,7 @@ typedef struct #define ERTC_TIME_MT_1 (0x2U << ERTC_TIME_MT_Pos) /*!< 0x00002000 */ #define ERTC_TIME_MT_2 (0x4U << ERTC_TIME_MT_Pos) /*!< 0x00004000 */ +/*!< HU configuration */ #define ERTC_TIME_HU_Pos (16U) #define ERTC_TIME_HU_Msk (0xFU << ERTC_TIME_HU_Pos) /*!< 0x000F0000 */ #define ERTC_TIME_HU ERTC_TIME_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -4956,6 +4995,7 @@ typedef struct #define ERTC_TIME_HU_2 (0x4U << ERTC_TIME_HU_Pos) /*!< 0x00040000 */ #define ERTC_TIME_HU_3 (0x8U << ERTC_TIME_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_TIME_HT_Pos (20U) #define ERTC_TIME_HT_Msk (0x3U << ERTC_TIME_HT_Pos) /*!< 0x00300000 */ #define ERTC_TIME_HT ERTC_TIME_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -4967,6 +5007,7 @@ typedef struct #define ERTC_TIME_AMPM ERTC_TIME_AMPM_Msk /*!< AM/PM */ /****************** Bit definition for ERTC_DATE register *******************/ +/*!< DU configuration */ #define ERTC_DATE_DU_Pos (0U) #define ERTC_DATE_DU_Msk (0xFU << ERTC_DATE_DU_Pos) /*!< 0x0000000F */ #define ERTC_DATE_DU ERTC_DATE_DU_Msk /*!< DU[3:0] (Date units) */ @@ -4975,12 +5016,14 @@ typedef struct #define ERTC_DATE_DU_2 (0x4U << ERTC_DATE_DU_Pos) /*!< 0x00000004 */ #define ERTC_DATE_DU_3 (0x8U << ERTC_DATE_DU_Pos) /*!< 0x00000008 */ +/*!< DT configuration */ #define ERTC_DATE_DT_Pos (4U) #define ERTC_DATE_DT_Msk (0x3U << ERTC_DATE_DT_Pos) /*!< 0x00300000 */ #define ERTC_DATE_DT ERTC_DATE_DT_Msk /*!< DT[1:0] (Date tens) */ #define ERTC_DATE_DT_0 (0x1U << ERTC_DATE_DT_Pos) /*!< 0x00000010 */ #define ERTC_DATE_DT_1 (0x2U << ERTC_DATE_DT_Pos) /*!< 0x00000020 */ +/*!< MU configuration */ #define ERTC_DATE_MU_Pos (8U) #define ERTC_DATE_MU_Msk (0xFU << ERTC_DATE_MU_Pos) /*!< 0x00000F00 */ #define ERTC_DATE_MU ERTC_DATE_MU_Msk /*!< MU[3:0] (Month units) */ @@ -4993,6 +5036,7 @@ typedef struct #define ERTC_DATE_MT_Msk (0x1U << ERTC_DATE_MT_Pos) /*!< 0x00001000 */ #define ERTC_DATE_MT ERTC_DATE_MT_Msk /*!< Month tens */ +/*!< WK configuration */ #define ERTC_DATE_WK_Pos (13U) #define ERTC_DATE_WK_Msk (0x7U << ERTC_DATE_WK_Pos) /*!< 0x0000E000 */ #define ERTC_DATE_WK ERTC_DATE_WK_Msk /*!< WK[2:0] (Week day) */ @@ -5000,6 +5044,7 @@ typedef struct #define ERTC_DATE_WK_1 (0x2U << ERTC_DATE_WK_Pos) /*!< 0x00004000 */ #define ERTC_DATE_WK_2 (0x4U << ERTC_DATE_WK_Pos) /*!< 0x00008000 */ +/*!< YU configuration */ #define ERTC_DATE_YU_Pos (16U) #define ERTC_DATE_YU_Msk (0xFU << ERTC_DATE_YU_Pos) /*!< 0x000F0000 */ #define ERTC_DATE_YU ERTC_DATE_YU_Msk /*!< YU[3:0] (Year units) */ @@ -5008,6 +5053,7 @@ typedef struct #define ERTC_DATE_YU_2 (0x4U << ERTC_DATE_YU_Pos) /*!< 0x00040000 */ #define ERTC_DATE_YU_3 (0x8U << ERTC_DATE_YU_Pos) /*!< 0x00080000 */ +/*!< YT configuration */ #define ERTC_DATE_YT_Pos (20U) #define ERTC_DATE_YT_Msk (0xFU << ERTC_DATE_YT_Pos) /*!< 0x00F00000 */ #define ERTC_DATE_YT ERTC_DATE_YT_Msk /*!< YT[3:0] (Year tens) */ @@ -5017,6 +5063,7 @@ typedef struct #define ERTC_DATE_YT_3 (0x8U << ERTC_DATE_YT_Pos) /*!< 0x00800000 */ /****************** Bit definition for ERTC_CTRL register *******************/ +/*!< WATCLK configuration */ #define ERTC_CTRL_WATCLK_Pos (0U) #define ERTC_CTRL_WATCLK_Msk (0x7U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000007 */ #define ERTC_CTRL_WATCLK ERTC_CTRL_WATCLK_Msk /*!< WATCLK[2:0] (Wakeup timer clock selection) */ @@ -5079,9 +5126,10 @@ typedef struct #define ERTC_CTRL_OUTP_Msk (0x1U << ERTC_CTRL_OUTP_Pos) /*!< 0x00100000 */ #define ERTC_CTRL_OUTP ERTC_CTRL_OUTP_Msk /*!< Output polarity */ +/*!< OUTSEL configuration */ #define ERTC_CTRL_OUTSEL_Pos (21U) #define ERTC_CTRL_OUTSEL_Msk (0x3U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00600000 */ -#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< WATCLK[1:0] (Output source selection) */ +#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< OUTSEL[1:0] (Output source selection) */ #define ERTC_CTRL_OUTSEL_0 (0x1U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00200000 */ #define ERTC_CTRL_OUTSEL_1 (0x2U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00400000 */ @@ -5150,6 +5198,7 @@ typedef struct #define ERTC_WAT_VAL ERTC_WAT_VAL_Msk /*!< Wakeup timer reload value */ /****************** Bit definition for ERTC_CCAL register *******************/ +/*!< CALVAL configuration */ #define ERTC_CCAL_CALVAL_Pos (0U) #define ERTC_CCAL_CALVAL_Msk (0x1FU << ERTC_CCAL_CALVAL_Pos) /*!< 0x0000001F */ #define ERTC_CCAL_CALVAL ERTC_CCAL_CALVAL_Msk /*!< CALVAL[4:0] (Calibration value) */ @@ -5164,6 +5213,7 @@ typedef struct #define ERTC_CCAL_CALDIR ERTC_CCAL_CALDIR_Msk /*!< Calibration direction */ /******************* Bit definition for ERTC_ALA register *******************/ +/*!< SU configuration */ #define ERTC_ALA_SU_Pos (0U) #define ERTC_ALA_SU_Msk (0xFU << ERTC_ALA_SU_Pos) /*!< 0x0000000F */ #define ERTC_ALA_SU ERTC_ALA_SU_Msk /*!< SU[3:0] (Second units) */ @@ -5172,6 +5222,7 @@ typedef struct #define ERTC_ALA_SU_2 (0x4U << ERTC_ALA_SU_Pos) /*!< 0x00000004 */ #define ERTC_ALA_SU_3 (0x8U << ERTC_ALA_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_ALA_ST_Pos (4U) #define ERTC_ALA_ST_Msk (0x7U << ERTC_ALA_ST_Pos) /*!< 0x00000070 */ #define ERTC_ALA_ST ERTC_ALA_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -5183,6 +5234,7 @@ typedef struct #define ERTC_ALA_MASK1_Msk (0x1U << ERTC_ALA_MASK1_Pos) /*!< 0x00000080 */ #define ERTC_ALA_MASK1 ERTC_ALA_MASK1_Msk /*!< Second mask */ +/*!< MU configuration */ #define ERTC_ALA_MU_Pos (8U) #define ERTC_ALA_MU_Msk (0xFU << ERTC_ALA_MU_Pos) /*!< 0x00000F00 */ #define ERTC_ALA_MU ERTC_ALA_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -5191,6 +5243,7 @@ typedef struct #define ERTC_ALA_MU_2 (0x4U << ERTC_ALA_MU_Pos) /*!< 0x00000400 */ #define ERTC_ALA_MU_3 (0x8U << ERTC_ALA_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_ALA_MT_Pos (12U) #define ERTC_ALA_MT_Msk (0x7U << ERTC_ALA_MT_Pos) /*!< 0x00007000 */ #define ERTC_ALA_MT ERTC_ALA_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -5202,6 +5255,7 @@ typedef struct #define ERTC_ALA_MASK2_Msk (0x1U << ERTC_ALA_MASK2_Pos) /*!< 0x00008000 */ #define ERTC_ALA_MASK2 ERTC_ALA_MASK2_Msk /*!< Minute mask */ +/*!< HU configuration */ #define ERTC_ALA_HU_Pos (16U) #define ERTC_ALA_HU_Msk (0xFU << ERTC_ALA_HU_Pos) /*!< 0x000F0000 */ #define ERTC_ALA_HU ERTC_ALA_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -5210,6 +5264,7 @@ typedef struct #define ERTC_ALA_HU_2 (0x4U << ERTC_ALA_HU_Pos) /*!< 0x00040000 */ #define ERTC_ALA_HU_3 (0x8U << ERTC_ALA_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_ALA_HT_Pos (20U) #define ERTC_ALA_HT_Msk (0x3U << ERTC_ALA_HT_Pos) /*!< 0x00300000 */ #define ERTC_ALA_HT ERTC_ALA_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -5223,6 +5278,7 @@ typedef struct #define ERTC_ALA_MASK3_Msk (0x1U << ERTC_ALA_MASK3_Pos) /*!< 0x00800000 */ #define ERTC_ALA_MASK3 ERTC_ALA_MASK3_Msk /*!< Hour mask */ +/*!< DU configuration */ #define ERTC_ALA_DU_Pos (24U) #define ERTC_ALA_DU_Msk (0xFU << ERTC_ALA_DU_Pos) /*!< 0x0F000000 */ #define ERTC_ALA_DU ERTC_ALA_DU_Msk /*!< DU[3:0] (Date/week day units) */ @@ -5231,6 +5287,7 @@ typedef struct #define ERTC_ALA_DU_2 (0x4U << ERTC_ALA_DU_Pos) /*!< 0x04000000 */ #define ERTC_ALA_DU_3 (0x8U << ERTC_ALA_DU_Pos) /*!< 0x08000000 */ +/*!< DT configuration */ #define ERTC_ALA_DT_Pos (28U) #define ERTC_ALA_DT_Msk (0x3U << ERTC_ALA_DT_Pos) /*!< 0x30000000 */ #define ERTC_ALA_DT ERTC_ALA_DT_Msk /*!< DT[1:0] (Date/week day tens) */ @@ -5245,6 +5302,7 @@ typedef struct #define ERTC_ALA_MASK4 ERTC_ALA_MASK4_Msk /*!< Date/week day mask */ /******************* Bit definition for ERTC_ALB register *******************/ +/*!< SU configuration */ #define ERTC_ALB_SU_Pos (0U) #define ERTC_ALB_SU_Msk (0xFU << ERTC_ALB_SU_Pos) /*!< 0x0000000F */ #define ERTC_ALB_SU ERTC_ALB_SU_Msk /*!< SU[3:0] (Second units) */ @@ -5253,6 +5311,7 @@ typedef struct #define ERTC_ALB_SU_2 (0x4U << ERTC_ALB_SU_Pos) /*!< 0x00000004 */ #define ERTC_ALB_SU_3 (0x8U << ERTC_ALB_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_ALB_ST_Pos (4U) #define ERTC_ALB_ST_Msk (0x7U << ERTC_ALB_ST_Pos) /*!< 0x00000070 */ #define ERTC_ALB_ST ERTC_ALB_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -5264,6 +5323,7 @@ typedef struct #define ERTC_ALB_MASK1_Msk (0x1U << ERTC_ALB_MASK1_Pos) /*!< 0x00000080 */ #define ERTC_ALB_MASK1 ERTC_ALB_MASK1_Msk /*!< Second mask */ +/*!< MU configuration */ #define ERTC_ALB_MU_Pos (8U) #define ERTC_ALB_MU_Msk (0xFU << ERTC_ALB_MU_Pos) /*!< 0x00000F00 */ #define ERTC_ALB_MU ERTC_ALB_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -5272,6 +5332,7 @@ typedef struct #define ERTC_ALB_MU_2 (0x4U << ERTC_ALB_MU_Pos) /*!< 0x00000400 */ #define ERTC_ALB_MU_3 (0x8U << ERTC_ALB_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_ALB_MT_Pos (12U) #define ERTC_ALB_MT_Msk (0x7U << ERTC_ALB_MT_Pos) /*!< 0x00007000 */ #define ERTC_ALB_MT ERTC_ALB_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -5283,6 +5344,7 @@ typedef struct #define ERTC_ALB_MASK2_Msk (0x1U << ERTC_ALB_MASK2_Pos) /*!< 0x00008000 */ #define ERTC_ALB_MASK2 ERTC_ALB_MASK2_Msk /*!< Minute mask */ +/*!< HU configuration */ #define ERTC_ALB_HU_Pos (16U) #define ERTC_ALB_HU_Msk (0xFU << ERTC_ALB_HU_Pos) /*!< 0x000F0000 */ #define ERTC_ALB_HU ERTC_ALB_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -5291,6 +5353,7 @@ typedef struct #define ERTC_ALB_HU_2 (0x4U << ERTC_ALB_HU_Pos) /*!< 0x00040000 */ #define ERTC_ALB_HU_3 (0x8U << ERTC_ALB_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_ALB_HT_Pos (20U) #define ERTC_ALB_HT_Msk (0x3U << ERTC_ALB_HT_Pos) /*!< 0x00300000 */ #define ERTC_ALB_HT ERTC_ALB_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -5304,6 +5367,7 @@ typedef struct #define ERTC_ALB_MASK3_Msk (0x1U << ERTC_ALB_MASK3_Pos) /*!< 0x00800000 */ #define ERTC_ALB_MASK3 ERTC_ALB_MASK3_Msk /*!< Hour mask */ +/*!< DU configuration */ #define ERTC_ALB_DU_Pos (24U) #define ERTC_ALB_DU_Msk (0xFU << ERTC_ALB_DU_Pos) /*!< 0x0F000000 */ #define ERTC_ALB_DU ERTC_ALB_DU_Msk /*!< DU[3:0] (Date/week day units) */ @@ -5312,6 +5376,7 @@ typedef struct #define ERTC_ALB_DU_2 (0x4U << ERTC_ALB_DU_Pos) /*!< 0x04000000 */ #define ERTC_ALB_DU_3 (0x8U << ERTC_ALB_DU_Pos) /*!< 0x08000000 */ +/*!< DT configuration */ #define ERTC_ALB_DT_Pos (28U) #define ERTC_ALB_DT_Msk (0x3U << ERTC_ALB_DT_Pos) /*!< 0x30000000 */ #define ERTC_ALB_DT ERTC_ALB_DT_Msk /*!< DT[1:0] (Date/week day tens) */ @@ -5344,6 +5409,7 @@ typedef struct #define ERTC_TADJ_ADD1S ERTC_TADJ_ADD1S_Msk /*!< Add 1 second */ /****************** Bit definition for ERTC_TSTM register *******************/ +/*!< SU configuration */ #define ERTC_TSTM_SU_Pos (0U) #define ERTC_TSTM_SU_Msk (0xFU << ERTC_TSTM_SU_Pos) /*!< 0x0000000F */ #define ERTC_TSTM_SU ERTC_TSTM_SU_Msk /*!< SU[3:0] (Second units) */ @@ -5352,6 +5418,7 @@ typedef struct #define ERTC_TSTM_SU_2 (0x4U << ERTC_TSTM_SU_Pos) /*!< 0x00000004 */ #define ERTC_TSTM_SU_3 (0x8U << ERTC_TSTM_SU_Pos) /*!< 0x00000008 */ +/*!< ST configuration */ #define ERTC_TSTM_ST_Pos (4U) #define ERTC_TSTM_ST_Msk (0x7U << ERTC_TSTM_ST_Pos) /*!< 0x00000070 */ #define ERTC_TSTM_ST ERTC_TSTM_ST_Msk /*!< ST[2:0] (Second tens) */ @@ -5359,6 +5426,7 @@ typedef struct #define ERTC_TSTM_ST_1 (0x2U << ERTC_TSTM_ST_Pos) /*!< 0x00000020 */ #define ERTC_TSTM_ST_2 (0x4U << ERTC_TSTM_ST_Pos) /*!< 0x00000040 */ +/*!< MU configuration */ #define ERTC_TSTM_MU_Pos (8U) #define ERTC_TSTM_MU_Msk (0xFU << ERTC_TSTM_MU_Pos) /*!< 0x00000F00 */ #define ERTC_TSTM_MU ERTC_TSTM_MU_Msk /*!< MU[3:0] (Minute units) */ @@ -5367,6 +5435,7 @@ typedef struct #define ERTC_TSTM_MU_2 (0x4U << ERTC_TSTM_MU_Pos) /*!< 0x00000400 */ #define ERTC_TSTM_MU_3 (0x8U << ERTC_TSTM_MU_Pos) /*!< 0x00000800 */ +/*!< MT configuration */ #define ERTC_TSTM_MT_Pos (12U) #define ERTC_TSTM_MT_Msk (0x7U << ERTC_TSTM_MT_Pos) /*!< 0x00007000 */ #define ERTC_TSTM_MT ERTC_TSTM_MT_Msk /*!< MT[2:0] (Minute tens) */ @@ -5374,6 +5443,7 @@ typedef struct #define ERTC_TSTM_MT_1 (0x2U << ERTC_TSTM_MT_Pos) /*!< 0x00002000 */ #define ERTC_TSTM_MT_2 (0x4U << ERTC_TSTM_MT_Pos) /*!< 0x00004000 */ +/*!< HU configuration */ #define ERTC_TSTM_HU_Pos (16U) #define ERTC_TSTM_HU_Msk (0xFU << ERTC_TSTM_HU_Pos) /*!< 0x000F0000 */ #define ERTC_TSTM_HU ERTC_TSTM_HU_Msk /*!< HU[3:0] (Hour units) */ @@ -5382,6 +5452,7 @@ typedef struct #define ERTC_TSTM_HU_2 (0x4U << ERTC_TSTM_HU_Pos) /*!< 0x00040000 */ #define ERTC_TSTM_HU_3 (0x8U << ERTC_TSTM_HU_Pos) /*!< 0x00080000 */ +/*!< HT configuration */ #define ERTC_TSTM_HT_Pos (20U) #define ERTC_TSTM_HT_Msk (0x3U << ERTC_TSTM_HT_Pos) /*!< 0x00300000 */ #define ERTC_TSTM_HT ERTC_TSTM_HT_Msk /*!< HT[1:0] (Hour tens) */ @@ -5393,6 +5464,7 @@ typedef struct #define ERTC_TSTM_AMPM ERTC_TSTM_AMPM_Msk /*!< AM/PM */ /****************** Bit definition for ERTC_TSDT register *******************/ +/*!< DU configuration */ #define ERTC_TSDT_DU_Pos (0U) #define ERTC_TSDT_DU_Msk (0xFU << ERTC_TSDT_DU_Pos) /*!< 0x0000000F */ #define ERTC_TSDT_DU ERTC_TSDT_DU_Msk /*!< DU[3:0] (Date units) */ @@ -5401,12 +5473,14 @@ typedef struct #define ERTC_TSDT_DU_2 (0x4U << ERTC_TSDT_DU_Pos) /*!< 0x00000004 */ #define ERTC_TSDT_DU_3 (0x8U << ERTC_TSDT_DU_Pos) /*!< 0x00000008 */ +/*!< DT configuration */ #define ERTC_TSDT_DT_Pos (4U) #define ERTC_TSDT_DT_Msk (0x3U << ERTC_TSDT_DT_Pos) /*!< 0x00000030 */ #define ERTC_TSDT_DT ERTC_TSDT_DT_Msk /*!< DT[1:0] (Date tens) */ #define ERTC_TSDT_DT_0 (0x1U << ERTC_TSDT_DT_Pos) /*!< 0x00000010 */ #define ERTC_TSDT_DT_1 (0x2U << ERTC_TSDT_DT_Pos) /*!< 0x00000020 */ +/*!< MU configuration */ #define ERTC_TSDT_MU_Pos (8U) #define ERTC_TSDT_MU_Msk (0xFU << ERTC_TSDT_MU_Pos) /*!< 0x00000F00 */ #define ERTC_TSDT_MU ERTC_TSDT_MU_Msk /*!< MU[3:0] (Month units) */ @@ -5419,6 +5493,7 @@ typedef struct #define ERTC_TSDT_MT_Msk (0x1U << ERTC_TSDT_MT_Pos) /*!< 0x00001000 */ #define ERTC_TSDT_MT ERTC_TSDT_MT_Msk /*!< Month tens */ +/*!< WK configuration */ #define ERTC_TSDT_WK_Pos (13U) #define ERTC_TSDT_WK_Msk (0x7U << ERTC_TSDT_WK_Pos) /*!< 0x0000E000 */ #define ERTC_TSDT_WK ERTC_TSDT_WK_Msk /*!< WK[2:0] (Week day) */ @@ -5459,6 +5534,7 @@ typedef struct #define ERTC_TAMP_TPTSEN_Msk (0x1U << ERTC_TAMP_TPTSEN_Pos) /*!< 0x00000080 */ #define ERTC_TAMP_TPTSEN ERTC_TAMP_TPTSEN_Msk /*!< Tamper detection timestamp enable */ +/*!< TPFREQ configuration */ #define ERTC_TAMP_TPFREQ_Pos (8U) #define ERTC_TAMP_TPFREQ_Msk (0x7U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000700 */ #define ERTC_TAMP_TPFREQ ERTC_TAMP_TPFREQ_Msk /*!< TPFREQ[2:0] (Tamper detection frequency) */ @@ -5466,12 +5542,14 @@ typedef struct #define ERTC_TAMP_TPFREQ_1 (0x2U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000200 */ #define ERTC_TAMP_TPFREQ_2 (0x4U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000400 */ +/*!< TPFLT configuration */ #define ERTC_TAMP_TPFLT_Pos (11U) #define ERTC_TAMP_TPFLT_Msk (0x3U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001800 */ #define ERTC_TAMP_TPFLT ERTC_TAMP_TPFLT_Msk /*!< TPFLT[1:0] (Tamper detection filter time) */ #define ERTC_TAMP_TPFLT_0 (0x1U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00000800 */ #define ERTC_TAMP_TPFLT_1 (0x2U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001000 */ +/*!< TPPR configuration */ #define ERTC_TAMP_TPPR_Pos (13U) #define ERTC_TAMP_TPPR_Msk (0x3U << ERTC_TAMP_TPPR_Pos) /*!< 0x00006000 */ #define ERTC_TAMP_TPPR ERTC_TAMP_TPPR_Msk /*!< TPPR[1:0] (Tamper detection pre-charge time) */ @@ -5490,9 +5568,10 @@ typedef struct #define ERTC_ALASBS_SBS_Msk (0x7FFFU << ERTC_ALASBS_SBS_Pos) /*!< 0x00007FFF */ #define ERTC_ALASBS_SBS ERTC_ALASBS_SBS_Msk /*!< Sub-second value */ +/*!< SBSMSK configuration */ #define ERTC_ALASBS_SBSMSK_Pos (24U) #define ERTC_ALASBS_SBSMSK_Msk (0xFU << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x0F000000 */ -#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ #define ERTC_ALASBS_SBSMSK_0 (0x1U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x01000000 */ #define ERTC_ALASBS_SBSMSK_1 (0x2U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x02000000 */ #define ERTC_ALASBS_SBSMSK_2 (0x4U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x04000000 */ @@ -5503,9 +5582,10 @@ typedef struct #define ERTC_ALBSBS_SBS_Msk (0x7FFFU << ERTC_ALBSBS_SBS_Pos) /*!< 0x00007FFF */ #define ERTC_ALBSBS_SBS ERTC_ALBSBS_SBS_Msk /*!< Sub-second value */ +/*!< SBSMSK configuration */ #define ERTC_ALBSBS_SBSMSK_Pos (24U) #define ERTC_ALBSBS_SBSMSK_Msk (0xFU << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x0F000000 */ -#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< Sub-second mask */ +#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ #define ERTC_ALBSBS_SBSMSK_0 (0x1U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x01000000 */ #define ERTC_ALBSBS_SBSMSK_1 (0x2U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x02000000 */ #define ERTC_ALBSBS_SBSMSK_2 (0x4U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x04000000 */ @@ -5642,6 +5722,7 @@ typedef struct #define ADC_STS_PCCE (ADC_STS_PCCC) /****************** Bit definition for ADC_CTRL1 register *******************/ +/*!< VMCSEL configuration */ #define ADC_CTRL1_VMCSEL_Pos (0U) #define ADC_CTRL1_VMCSEL_Msk (0x1FU << ADC_CTRL1_VMCSEL_Pos) /*!< 0x0000001F */ #define ADC_CTRL1_VMCSEL ADC_CTRL1_VMCSEL_Msk /*!< VMCSEL[4:0] bits (Voltage monitoring channel select) */ @@ -5676,6 +5757,7 @@ typedef struct #define ADC_CTRL1_PCPEN_Msk (0x1U << ADC_CTRL1_PCPEN_Pos) /*!< 0x00001000 */ #define ADC_CTRL1_PCPEN ADC_CTRL1_PCPEN_Msk /*!< Partitioned mode enable on preempted channels */ +/*!< OCPCNT configuration */ #define ADC_CTRL1_OCPCNT_Pos (13U) #define ADC_CTRL1_OCPCNT_Msk (0x7U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x0000E000 */ #define ADC_CTRL1_OCPCNT ADC_CTRL1_OCPCNT_Msk /*!< OCPCNT[2:0] bits (Partitioned mode conversion count of ordinary channels) */ @@ -5700,7 +5782,7 @@ typedef struct #define ADC_CTRL2_ADCEN ADC_CTRL2_ADCEN_Msk /*!< A/D converter enable */ #define ADC_CTRL2_RPEN_Pos (1U) #define ADC_CTRL2_RPEN_Msk (0x1U << ADC_CTRL2_RPEN_Pos) /*!< 0x00000002 */ -#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repition mode enable */ +#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repetition mode enable */ #define ADC_CTRL2_ADCAL_Pos (2U) #define ADC_CTRL2_ADCAL_Msk (0x1U << ADC_CTRL2_ADCAL_Pos) /*!< 0x00000004 */ #define ADC_CTRL2_ADCAL ADC_CTRL2_ADCAL_Msk /*!< A/D calibration */ @@ -5748,6 +5830,7 @@ typedef struct #define ADC_CTRL2_ITSRVEN ADC_CTRL2_ITSRVEN_Msk /*!< Internal temperature sensor and VINTRV enable */ /******************* Bit definition for ADC_SPT1 register *******************/ +/*!< CSPT10 configuration */ #define ADC_SPT1_CSPT10_Pos (0U) #define ADC_SPT1_CSPT10_Msk (0x7U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000007 */ #define ADC_SPT1_CSPT10 ADC_SPT1_CSPT10_Msk /*!< CSPT10[2:0] bits (Sample time selection of channel ADC_IN10) */ @@ -5755,6 +5838,7 @@ typedef struct #define ADC_SPT1_CSPT10_1 (0x2U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000002 */ #define ADC_SPT1_CSPT10_2 (0x4U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000004 */ +/*!< CSPT11 configuration */ #define ADC_SPT1_CSPT11_Pos (3U) #define ADC_SPT1_CSPT11_Msk (0x7U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000038 */ #define ADC_SPT1_CSPT11 ADC_SPT1_CSPT11_Msk /*!< CSPT11[2:0] bits (Sample time selection of channel ADC_IN11) */ @@ -5762,6 +5846,7 @@ typedef struct #define ADC_SPT1_CSPT11_1 (0x2U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000010 */ #define ADC_SPT1_CSPT11_2 (0x4U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000020 */ +/*!< CSPT12 configuration */ #define ADC_SPT1_CSPT12_Pos (6U) #define ADC_SPT1_CSPT12_Msk (0x7U << ADC_SPT1_CSPT12_Pos) /*!< 0x000001C0 */ #define ADC_SPT1_CSPT12 ADC_SPT1_CSPT12_Msk /*!< CSPT12[2:0] bits (Sample time selection of channel ADC_IN12) */ @@ -5769,6 +5854,7 @@ typedef struct #define ADC_SPT1_CSPT12_1 (0x2U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000080 */ #define ADC_SPT1_CSPT12_2 (0x4U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000100 */ +/*!< CSPT13 configuration */ #define ADC_SPT1_CSPT13_Pos (9U) #define ADC_SPT1_CSPT13_Msk (0x7U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000E00 */ #define ADC_SPT1_CSPT13 ADC_SPT1_CSPT13_Msk /*!< CSPT13[2:0] bits (Sample time selection of channel ADC_IN13) */ @@ -5776,6 +5862,7 @@ typedef struct #define ADC_SPT1_CSPT13_1 (0x2U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000400 */ #define ADC_SPT1_CSPT13_2 (0x4U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000800 */ +/*!< CSPT14 configuration */ #define ADC_SPT1_CSPT14_Pos (12U) #define ADC_SPT1_CSPT14_Msk (0x7U << ADC_SPT1_CSPT14_Pos) /*!< 0x00007000 */ #define ADC_SPT1_CSPT14 ADC_SPT1_CSPT14_Msk /*!< CSPT14[2:0] bits (Sample time selection of channel ADC_IN14) */ @@ -5783,6 +5870,7 @@ typedef struct #define ADC_SPT1_CSPT14_1 (0x2U << ADC_SPT1_CSPT14_Pos) /*!< 0x00002000 */ #define ADC_SPT1_CSPT14_2 (0x4U << ADC_SPT1_CSPT14_Pos) /*!< 0x00004000 */ +/*!< CSPT15 configuration */ #define ADC_SPT1_CSPT15_Pos (15U) #define ADC_SPT1_CSPT15_Msk (0x7U << ADC_SPT1_CSPT15_Pos) /*!< 0x00038000 */ #define ADC_SPT1_CSPT15 ADC_SPT1_CSPT15_Msk /*!< CSPT15[2:0] bits (Sample time selection of channel ADC_IN15) */ @@ -5790,6 +5878,7 @@ typedef struct #define ADC_SPT1_CSPT15_1 (0x2U << ADC_SPT1_CSPT15_Pos) /*!< 0x00010000 */ #define ADC_SPT1_CSPT15_2 (0x4U << ADC_SPT1_CSPT15_Pos) /*!< 0x00020000 */ +/*!< CSPT16 configuration */ #define ADC_SPT1_CSPT16_Pos (18U) #define ADC_SPT1_CSPT16_Msk (0x7U << ADC_SPT1_CSPT16_Pos) /*!< 0x001C0000 */ #define ADC_SPT1_CSPT16 ADC_SPT1_CSPT16_Msk /*!< CSPT16[2:0] bits (Sample time selection of channel ADC_IN16) */ @@ -5797,6 +5886,7 @@ typedef struct #define ADC_SPT1_CSPT16_1 (0x2U << ADC_SPT1_CSPT16_Pos) /*!< 0x00080000 */ #define ADC_SPT1_CSPT16_2 (0x4U << ADC_SPT1_CSPT16_Pos) /*!< 0x00100000 */ +/*!< CSPT17 configuration */ #define ADC_SPT1_CSPT17_Pos (21U) #define ADC_SPT1_CSPT17_Msk (0x7U << ADC_SPT1_CSPT17_Pos) /*!< 0x00E00000 */ #define ADC_SPT1_CSPT17 ADC_SPT1_CSPT17_Msk /*!< CSPT17[2:0] bits (Sample time selection of channel ADC_IN17) */ @@ -5805,6 +5895,7 @@ typedef struct #define ADC_SPT1_CSPT17_2 (0x4U << ADC_SPT1_CSPT17_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_SPT2 register *******************/ +/*!< CSPT0 configuration */ #define ADC_SPT2_CSPT0_Pos (0U) #define ADC_SPT2_CSPT0_Msk (0x7U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000007 */ #define ADC_SPT2_CSPT0 ADC_SPT2_CSPT0_Msk /*!< CSPT0[2:0] bits (Sample time selection of channel ADC_IN0) */ @@ -5812,6 +5903,7 @@ typedef struct #define ADC_SPT2_CSPT0_1 (0x2U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000002 */ #define ADC_SPT2_CSPT0_2 (0x4U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000004 */ +/*!< CSPT1 configuration */ #define ADC_SPT2_CSPT1_Pos (3U) #define ADC_SPT2_CSPT1_Msk (0x7U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000038 */ #define ADC_SPT2_CSPT1 ADC_SPT2_CSPT1_Msk /*!< CSPT1[2:0] bits (Sample time selection of channel ADC_IN1) */ @@ -5819,6 +5911,7 @@ typedef struct #define ADC_SPT2_CSPT1_1 (0x2U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000010 */ #define ADC_SPT2_CSPT1_2 (0x4U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000020 */ +/*!< CSPT2 configuration */ #define ADC_SPT2_CSPT2_Pos (6U) #define ADC_SPT2_CSPT2_Msk (0x7U << ADC_SPT2_CSPT2_Pos) /*!< 0x000001C0 */ #define ADC_SPT2_CSPT2 ADC_SPT2_CSPT2_Msk /*!< CSPT2[2:0] bits (Sample time selection of channel ADC_IN2) */ @@ -5826,6 +5919,7 @@ typedef struct #define ADC_SPT2_CSPT2_1 (0x2U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000080 */ #define ADC_SPT2_CSPT2_2 (0x4U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000100 */ +/*!< CSPT3 configuration */ #define ADC_SPT2_CSPT3_Pos (9U) #define ADC_SPT2_CSPT3_Msk (0x7U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000E00 */ #define ADC_SPT2_CSPT3 ADC_SPT2_CSPT3_Msk /*!< CSPT3[2:0] bits (Sample time selection of channel ADC_IN3) */ @@ -5833,6 +5927,7 @@ typedef struct #define ADC_SPT2_CSPT3_1 (0x2U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000400 */ #define ADC_SPT2_CSPT3_2 (0x4U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000800 */ +/*!< CSPT4 configuration */ #define ADC_SPT2_CSPT4_Pos (12U) #define ADC_SPT2_CSPT4_Msk (0x7U << ADC_SPT2_CSPT4_Pos) /*!< 0x00007000 */ #define ADC_SPT2_CSPT4 ADC_SPT2_CSPT4_Msk /*!< CSPT4[2:0] bits (Sample time selection of channel ADC_IN4) */ @@ -5840,6 +5935,7 @@ typedef struct #define ADC_SPT2_CSPT4_1 (0x2U << ADC_SPT2_CSPT4_Pos) /*!< 0x00002000 */ #define ADC_SPT2_CSPT4_2 (0x4U << ADC_SPT2_CSPT4_Pos) /*!< 0x00004000 */ +/*!< CSPT5 configuration */ #define ADC_SPT2_CSPT5_Pos (15U) #define ADC_SPT2_CSPT5_Msk (0x7U << ADC_SPT2_CSPT5_Pos) /*!< 0x00038000 */ #define ADC_SPT2_CSPT5 ADC_SPT2_CSPT5_Msk /*!< CSPT5[2:0] bits (Sample time selection of channel ADC_IN5) */ @@ -5847,6 +5943,7 @@ typedef struct #define ADC_SPT2_CSPT5_1 (0x2U << ADC_SPT2_CSPT5_Pos) /*!< 0x00010000 */ #define ADC_SPT2_CSPT5_2 (0x4U << ADC_SPT2_CSPT5_Pos) /*!< 0x00020000 */ +/*!< CSPT6 configuration */ #define ADC_SPT2_CSPT6_Pos (18U) #define ADC_SPT2_CSPT6_Msk (0x7U << ADC_SPT2_CSPT6_Pos) /*!< 0x001C0000 */ #define ADC_SPT2_CSPT6 ADC_SPT2_CSPT6_Msk /*!< CSPT6[2:0] bits (Sample time selection of channel ADC_IN6) */ @@ -5854,6 +5951,7 @@ typedef struct #define ADC_SPT2_CSPT6_1 (0x2U << ADC_SPT2_CSPT6_Pos) /*!< 0x00080000 */ #define ADC_SPT2_CSPT6_2 (0x4U << ADC_SPT2_CSPT6_Pos) /*!< 0x00100000 */ +/*!< CSPT7 configuration */ #define ADC_SPT2_CSPT7_Pos (21U) #define ADC_SPT2_CSPT7_Msk (0x7U << ADC_SPT2_CSPT7_Pos) /*!< 0x00E00000 */ #define ADC_SPT2_CSPT7 ADC_SPT2_CSPT7_Msk /*!< CSPT7[2:0] bits (Sample time selection of channel ADC_IN7) */ @@ -5861,6 +5959,7 @@ typedef struct #define ADC_SPT2_CSPT7_1 (0x2U << ADC_SPT2_CSPT7_Pos) /*!< 0x00400000 */ #define ADC_SPT2_CSPT7_2 (0x4U << ADC_SPT2_CSPT7_Pos) /*!< 0x00800000 */ +/*!< CSPT8 configuration */ #define ADC_SPT2_CSPT8_Pos (24U) #define ADC_SPT2_CSPT8_Msk (0x7U << ADC_SPT2_CSPT8_Pos) /*!< 0x07000000 */ #define ADC_SPT2_CSPT8 ADC_SPT2_CSPT8_Msk /*!< CSPT8[2:0] bits (Sample time selection of channel ADC_IN8) */ @@ -5868,6 +5967,7 @@ typedef struct #define ADC_SPT2_CSPT8_1 (0x2U << ADC_SPT2_CSPT8_Pos) /*!< 0x02000000 */ #define ADC_SPT2_CSPT8_2 (0x4U << ADC_SPT2_CSPT8_Pos) /*!< 0x04000000 */ +/*!< CSPT9 configuration */ #define ADC_SPT2_CSPT9_Pos (27U) #define ADC_SPT2_CSPT9_Msk (0x7U << ADC_SPT2_CSPT9_Pos) /*!< 0x38000000 */ #define ADC_SPT2_CSPT9 ADC_SPT2_CSPT9_Msk /*!< CSPT9[2:0] bits (Sample time selection of channel ADC_IN9) */ @@ -5906,6 +6006,7 @@ typedef struct #define ADC_VMLB_VMLB ADC_VMLB_VMLB_Msk /*!< Voltage monitoring low boundary */ /******************* Bit definition for ADC_OSQ1 register *******************/ +/*!< OSN13 configuration */ #define ADC_OSQ1_OSN13_Pos (0U) #define ADC_OSQ1_OSN13_Msk (0x1FU << ADC_OSQ1_OSN13_Pos) /*!< 0x0000001F */ #define ADC_OSQ1_OSN13 ADC_OSQ1_OSN13_Msk /*!< OSN13[4:0] bits (Number of 13th conversion in ordinary sequence) */ @@ -5915,6 +6016,7 @@ typedef struct #define ADC_OSQ1_OSN13_3 (0x08U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000008 */ #define ADC_OSQ1_OSN13_4 (0x10U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000010 */ +/*!< OSN14 configuration */ #define ADC_OSQ1_OSN14_Pos (5U) #define ADC_OSQ1_OSN14_Msk (0x1FU << ADC_OSQ1_OSN14_Pos) /*!< 0x000003E0 */ #define ADC_OSQ1_OSN14 ADC_OSQ1_OSN14_Msk /*!< OSN14[4:0] bits (Number of 14th conversion in ordinary sequence) */ @@ -5924,6 +6026,7 @@ typedef struct #define ADC_OSQ1_OSN14_3 (0x08U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000100 */ #define ADC_OSQ1_OSN14_4 (0x10U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000200 */ +/*!< OSN15 configuration */ #define ADC_OSQ1_OSN15_Pos (10U) #define ADC_OSQ1_OSN15_Msk (0x1FU << ADC_OSQ1_OSN15_Pos) /*!< 0x00007C00 */ #define ADC_OSQ1_OSN15 ADC_OSQ1_OSN15_Msk /*!< OSN15[4:0] bits (Number of 15th conversion in ordinary sequence) */ @@ -5933,6 +6036,7 @@ typedef struct #define ADC_OSQ1_OSN15_3 (0x08U << ADC_OSQ1_OSN15_Pos) /*!< 0x00002000 */ #define ADC_OSQ1_OSN15_4 (0x10U << ADC_OSQ1_OSN15_Pos) /*!< 0x00004000 */ +/*!< OSN16 configuration */ #define ADC_OSQ1_OSN16_Pos (15U) #define ADC_OSQ1_OSN16_Msk (0x1FU << ADC_OSQ1_OSN16_Pos) /*!< 0x000F8000 */ #define ADC_OSQ1_OSN16 ADC_OSQ1_OSN16_Msk /*!< OSN16[4:0] bits (Number of 16th conversion in ordinary sequence) */ @@ -5942,6 +6046,7 @@ typedef struct #define ADC_OSQ1_OSN16_3 (0x08U << ADC_OSQ1_OSN16_Pos) /*!< 0x00040000 */ #define ADC_OSQ1_OSN16_4 (0x10U << ADC_OSQ1_OSN16_Pos) /*!< 0x00080000 */ +/*!< OCLEN configuration */ #define ADC_OSQ1_OCLEN_Pos (20U) #define ADC_OSQ1_OCLEN_Msk (0xFU << ADC_OSQ1_OCLEN_Pos) /*!< 0x00F00000 */ #define ADC_OSQ1_OCLEN ADC_OSQ1_OCLEN_Msk /*!< OCLEN[3:0] bits (Ordinary conversion sequence length) */ @@ -5951,6 +6056,7 @@ typedef struct #define ADC_OSQ1_OCLEN_3 (0x8U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_OSQ2 register *******************/ +/*!< OSN7 configuration */ #define ADC_OSQ2_OSN7_Pos (0U) #define ADC_OSQ2_OSN7_Msk (0x1FU << ADC_OSQ2_OSN7_Pos) /*!< 0x0000001F */ #define ADC_OSQ2_OSN7 ADC_OSQ2_OSN7_Msk /*!< OSN7[4:0] bits (Number of 7th conversion in ordinary sequence) */ @@ -5960,6 +6066,7 @@ typedef struct #define ADC_OSQ2_OSN7_3 (0x08U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000008 */ #define ADC_OSQ2_OSN7_4 (0x10U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000010 */ +/*!< OSN8 configuration */ #define ADC_OSQ2_OSN8_Pos (5U) #define ADC_OSQ2_OSN8_Msk (0x1FU << ADC_OSQ2_OSN8_Pos) /*!< 0x000003E0 */ #define ADC_OSQ2_OSN8 ADC_OSQ2_OSN8_Msk /*!< OSN8[4:0] bits (Number of 8th conversion in ordinary sequence) */ @@ -5969,6 +6076,7 @@ typedef struct #define ADC_OSQ2_OSN8_3 (0x08U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000100 */ #define ADC_OSQ2_OSN8_4 (0x10U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000200 */ +/*!< OSN9 configuration */ #define ADC_OSQ2_OSN9_Pos (10U) #define ADC_OSQ2_OSN9_Msk (0x1FU << ADC_OSQ2_OSN9_Pos) /*!< 0x00007C00 */ #define ADC_OSQ2_OSN9 ADC_OSQ2_OSN9_Msk /*!< OSN9[4:0] bits (Number of 9th conversion in ordinary sequence) */ @@ -5978,6 +6086,7 @@ typedef struct #define ADC_OSQ2_OSN9_3 (0x08U << ADC_OSQ2_OSN9_Pos) /*!< 0x00002000 */ #define ADC_OSQ2_OSN9_4 (0x10U << ADC_OSQ2_OSN9_Pos) /*!< 0x00004000 */ +/*!< OSN10 configuration */ #define ADC_OSQ2_OSN10_Pos (15U) #define ADC_OSQ2_OSN10_Msk (0x1FU << ADC_OSQ2_OSN10_Pos) /*!< 0x000F8000 */ #define ADC_OSQ2_OSN10 ADC_OSQ2_OSN10_Msk /*!< OSN10[4:0] bits (Number of 10th conversion in ordinary sequence) */ @@ -5987,6 +6096,7 @@ typedef struct #define ADC_OSQ2_OSN10_3 (0x08U << ADC_OSQ2_OSN10_Pos) /*!< 0x00040000 */ #define ADC_OSQ2_OSN10_4 (0x10U << ADC_OSQ2_OSN10_Pos) /*!< 0x00080000 */ +/*!< OSN11 configuration */ #define ADC_OSQ2_OSN11_Pos (20U) #define ADC_OSQ2_OSN11_Msk (0x1FU << ADC_OSQ2_OSN11_Pos) /*!< 0x01F00000 */ #define ADC_OSQ2_OSN11 ADC_OSQ2_OSN11_Msk /*!< OSN11[4:0] bits (Number of 11th conversion in ordinary sequence) */ @@ -5996,6 +6106,7 @@ typedef struct #define ADC_OSQ2_OSN11_3 (0x08U << ADC_OSQ2_OSN11_Pos) /*!< 0x00800000 */ #define ADC_OSQ2_OSN11_4 (0x10U << ADC_OSQ2_OSN11_Pos) /*!< 0x01000000 */ +/*!< OSN12 configuration */ #define ADC_OSQ2_OSN12_Pos (25U) #define ADC_OSQ2_OSN12_Msk (0x1FU << ADC_OSQ2_OSN12_Pos) /*!< 0x3E000000 */ #define ADC_OSQ2_OSN12 ADC_OSQ2_OSN12_Msk /*!< OSN12[4:0] bits (Number of 12th conversion in ordinary sequence) */ @@ -6006,6 +6117,7 @@ typedef struct #define ADC_OSQ2_OSN12_4 (0x10U << ADC_OSQ2_OSN12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_OSQ3 register *******************/ +/*!< OSN1 configuration */ #define ADC_OSQ3_OSN1_Pos (0U) #define ADC_OSQ3_OSN1_Msk (0x1FU << ADC_OSQ3_OSN1_Pos) /*!< 0x0000001F */ #define ADC_OSQ3_OSN1 ADC_OSQ3_OSN1_Msk /*!< OSN1[4:0] bits (Number of 1st conversion in ordinary sequence) */ @@ -6015,6 +6127,7 @@ typedef struct #define ADC_OSQ3_OSN1_3 (0x08U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000008 */ #define ADC_OSQ3_OSN1_4 (0x10U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000010 */ +/*!< OSN2 configuration */ #define ADC_OSQ3_OSN2_Pos (5U) #define ADC_OSQ3_OSN2_Msk (0x1FU << ADC_OSQ3_OSN2_Pos) /*!< 0x000003E0 */ #define ADC_OSQ3_OSN2 ADC_OSQ3_OSN2_Msk /*!< OSN2[4:0] bits (Number of 2nd conversion in ordinary sequence) */ @@ -6024,6 +6137,7 @@ typedef struct #define ADC_OSQ3_OSN2_3 (0x08U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000100 */ #define ADC_OSQ3_OSN2_4 (0x10U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000200 */ +/*!< OSN3 configuration */ #define ADC_OSQ3_OSN3_Pos (10U) #define ADC_OSQ3_OSN3_Msk (0x1FU << ADC_OSQ3_OSN3_Pos) /*!< 0x00007C00 */ #define ADC_OSQ3_OSN3 ADC_OSQ3_OSN3_Msk /*!< OSN3[4:0] bits (Number of 3rd conversion in ordinary sequence) */ @@ -6033,6 +6147,7 @@ typedef struct #define ADC_OSQ3_OSN3_3 (0x08U << ADC_OSQ3_OSN3_Pos) /*!< 0x00002000 */ #define ADC_OSQ3_OSN3_4 (0x10U << ADC_OSQ3_OSN3_Pos) /*!< 0x00004000 */ +/*!< OSN4 configuration */ #define ADC_OSQ3_OSN4_Pos (15U) #define ADC_OSQ3_OSN4_Msk (0x1FU << ADC_OSQ3_OSN4_Pos) /*!< 0x000F8000 */ #define ADC_OSQ3_OSN4 ADC_OSQ3_OSN4_Msk /*!< OSN4[4:0] bits (Number of 4th conversion in ordinary sequence) */ @@ -6042,6 +6157,7 @@ typedef struct #define ADC_OSQ3_OSN4_3 (0x08U << ADC_OSQ3_OSN4_Pos) /*!< 0x00040000 */ #define ADC_OSQ3_OSN4_4 (0x10U << ADC_OSQ3_OSN4_Pos) /*!< 0x00080000 */ +/*!< OSN5 configuration */ #define ADC_OSQ3_OSN5_Pos (20U) #define ADC_OSQ3_OSN5_Msk (0x1FU << ADC_OSQ3_OSN5_Pos) /*!< 0x01F00000 */ #define ADC_OSQ3_OSN5 ADC_OSQ3_OSN5_Msk /*!< OSN5[4:0] bits (Number of 5th conversion in ordinary sequence) */ @@ -6051,6 +6167,7 @@ typedef struct #define ADC_OSQ3_OSN5_3 (0x08U << ADC_OSQ3_OSN5_Pos) /*!< 0x00800000 */ #define ADC_OSQ3_OSN5_4 (0x10U << ADC_OSQ3_OSN5_Pos) /*!< 0x01000000 */ +/*!< OSN6 configuration */ #define ADC_OSQ3_OSN6_Pos (25U) #define ADC_OSQ3_OSN6_Msk (0x1FU << ADC_OSQ3_OSN6_Pos) /*!< 0x3E000000 */ #define ADC_OSQ3_OSN6 ADC_OSQ3_OSN6_Msk /*!< OSN6[4:0] bits (Number of 6th conversion in ordinary sequence) */ @@ -6061,6 +6178,7 @@ typedef struct #define ADC_OSQ3_OSN6_4 (0x10U << ADC_OSQ3_OSN6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_PSQ register ********************/ +/*!< PSN1 configuration */ #define ADC_PSQ_PSN1_Pos (0U) #define ADC_PSQ_PSN1_Msk (0x1FU << ADC_PSQ_PSN1_Pos) /*!< 0x0000001F */ #define ADC_PSQ_PSN1 ADC_PSQ_PSN1_Msk /*!< PSN1[4:0] bits (Number of 1st conversion in preempted sequence) */ @@ -6070,6 +6188,7 @@ typedef struct #define ADC_PSQ_PSN1_3 (0x08U << ADC_PSQ_PSN1_Pos) /*!< 0x00000008 */ #define ADC_PSQ_PSN1_4 (0x10U << ADC_PSQ_PSN1_Pos) /*!< 0x00000010 */ +/*!< PSN2 configuration */ #define ADC_PSQ_PSN2_Pos (5U) #define ADC_PSQ_PSN2_Msk (0x1FU << ADC_PSQ_PSN2_Pos) /*!< 0x000003E0 */ #define ADC_PSQ_PSN2 ADC_PSQ_PSN2_Msk /*!< PSN2[4:0] bits (Number of 2nd conversion in preempted sequence) */ @@ -6079,6 +6198,7 @@ typedef struct #define ADC_PSQ_PSN2_3 (0x08U << ADC_PSQ_PSN2_Pos) /*!< 0x00000100 */ #define ADC_PSQ_PSN2_4 (0x10U << ADC_PSQ_PSN2_Pos) /*!< 0x00000200 */ +/*!< PSN3 configuration */ #define ADC_PSQ_PSN3_Pos (10U) #define ADC_PSQ_PSN3_Msk (0x1FU << ADC_PSQ_PSN3_Pos) /*!< 0x00007C00 */ #define ADC_PSQ_PSN3 ADC_PSQ_PSN3_Msk /*!< PSN3[4:0] bits (Number of 3rd conversion in preempted sequence) */ @@ -6088,6 +6208,7 @@ typedef struct #define ADC_PSQ_PSN3_3 (0x08U << ADC_PSQ_PSN3_Pos) /*!< 0x00002000 */ #define ADC_PSQ_PSN3_4 (0x10U << ADC_PSQ_PSN3_Pos) /*!< 0x00004000 */ +/*!< PSN4 configuration */ #define ADC_PSQ_PSN4_Pos (15U) #define ADC_PSQ_PSN4_Msk (0x1FU << ADC_PSQ_PSN4_Pos) /*!< 0x000F8000 */ #define ADC_PSQ_PSN4 ADC_PSQ_PSN4_Msk /*!< PSN4[4:0] bits (Number of 4th conversion in preempted sequence) */ @@ -6097,6 +6218,7 @@ typedef struct #define ADC_PSQ_PSN4_3 (0x08U << ADC_PSQ_PSN4_Pos) /*!< 0x00040000 */ #define ADC_PSQ_PSN4_4 (0x10U << ADC_PSQ_PSN4_Pos) /*!< 0x00080000 */ +/*!< PCLEN configuration */ #define ADC_PSQ_PCLEN_Pos (20U) #define ADC_PSQ_PCLEN_Msk (0x3U << ADC_PSQ_PCLEN_Pos) /*!< 0x00300000 */ #define ADC_PSQ_PCLEN ADC_PSQ_PCLEN_Msk /*!< PCLEN[1:0] bits (Preempted conversion sequence length) */ @@ -6127,9 +6249,6 @@ typedef struct #define ADC_ODT_ODT_Pos (0U) #define ADC_ODT_ODT_Msk (0xFFFFU << ADC_ODT_ODT_Pos) /*!< 0x0000FFFF */ #define ADC_ODT_ODT ADC_ODT_ODT_Msk /*!< Conversion data of ordinary channel */ -#define ADC_ODT_ADC2ODT_Pos (16U) -#define ADC_ODT_ADC2ODT_Msk (0xFFFFU << ADC_ODT_ADC2ODT_Pos) /*!< 0xFFFF0000 */ -#define ADC_ODT_ADC2ODT ADC_ODT_ADC2ODT_Msk /*!< ADC2 conversion data of ordinary channel */ /******************************************************************************/ /* */ @@ -6249,6 +6368,7 @@ typedef struct #define CAN_TSTS_TMNR_Msk (0x3U << CAN_TSTS_TMNR_Pos) /*!< 0x03000000 */ #define CAN_TSTS_TMNR CAN_TSTS_TMNR_Msk /*!< TMNR[1:0] bits (Transmit mailbox number record) */ +/*!< TMEF congiguration */ #define CAN_TSTS_TMEF_Pos (26U) #define CAN_TSTS_TMEF_Msk (0x7U << CAN_TSTS_TMEF_Pos) /*!< 0x1C000000 */ #define CAN_TSTS_TMEF CAN_TSTS_TMEF_Msk /*!< TMEF[2:0] bits (Transmit mailbox empty flag) */ @@ -6262,6 +6382,7 @@ typedef struct #define CAN_TSTS_TM2EF_Msk (0x1U << CAN_TSTS_TM2EF_Pos) /*!< 0x10000000 */ #define CAN_TSTS_TM2EF CAN_TSTS_TM2EF_Msk /*!< Transmit mailbox 2 empty flag */ +/*!< TMLPF congiguration */ #define CAN_TSTS_TMLPF_Pos (29U) #define CAN_TSTS_TMLPF_Msk (0x7U << CAN_TSTS_TMLPF_Pos) /*!< 0xE0000000 */ #define CAN_TSTS_TMLPF CAN_TSTS_TMLPF_Msk /*!< TMLPF[2:0] bits (Transmit mailbox lowest priority flag) */ @@ -6358,6 +6479,7 @@ typedef struct #define CAN_ESTS_BOF_Msk (0x1U << CAN_ESTS_BOF_Pos) /*!< 0x00000004 */ #define CAN_ESTS_BOF CAN_ESTS_BOF_Msk /*!< Bus-off flag */ +/*!< ETR congiguration */ #define CAN_ESTS_ETR_Pos (4U) #define CAN_ESTS_ETR_Msk (0x7U << CAN_ESTS_ETR_Pos) /*!< 0x00000070 */ #define CAN_ESTS_ETR CAN_ESTS_ETR_Msk /*!< ETR[2:0] bits (Error type record) */ @@ -6377,6 +6499,7 @@ typedef struct #define CAN_BTMG_BRDIV_Msk (0xFFFU << CAN_BTMG_BRDIV_Pos) /*!< 0x00000FFF */ #define CAN_BTMG_BRDIV CAN_BTMG_BRDIV_Msk /*!< Baud rate division */ +/*!< BTS1 congiguration */ #define CAN_BTMG_BTS1_Pos (16U) #define CAN_BTMG_BTS1_Msk (0xFU << CAN_BTMG_BTS1_Pos) /*!< 0x000F0000 */ #define CAN_BTMG_BTS1 CAN_BTMG_BTS1_Msk /*!< BTS1[3:0] bits (Bit time segment 1) */ @@ -6385,6 +6508,7 @@ typedef struct #define CAN_BTMG_BTS1_2 (0x4U << CAN_BTMG_BTS1_Pos) /*!< 0x00040000 */ #define CAN_BTMG_BTS1_3 (0x8U << CAN_BTMG_BTS1_Pos) /*!< 0x00080000 */ +/*!< BTS2 congiguration */ #define CAN_BTMG_BTS2_Pos (20U) #define CAN_BTMG_BTS2_Msk (0x7U << CAN_BTMG_BTS2_Pos) /*!< 0x00700000 */ #define CAN_BTMG_BTS2 CAN_BTMG_BTS2_Msk /*!< BTS2[2:0] bits (Bit time segment 2) */ @@ -6392,6 +6516,7 @@ typedef struct #define CAN_BTMG_BTS2_1 (0x2U << CAN_BTMG_BTS2_Pos) /*!< 0x00200000 */ #define CAN_BTMG_BTS2_2 (0x4U << CAN_BTMG_BTS2_Pos) /*!< 0x00400000 */ +/*!< RSAW congiguration */ #define CAN_BTMG_RSAW_Pos (24U) #define CAN_BTMG_RSAW_Msk (0x3U << CAN_BTMG_RSAW_Pos) /*!< 0x03000000 */ #define CAN_BTMG_RSAW CAN_BTMG_RSAW_Msk /*!< RSAW[1:0] bits (Resynchronization width) */ @@ -9625,6 +9750,7 @@ typedef struct /******************************************************************************/ /***************** Bit definition for SDIO_PWRCTRL register *****************/ +/*!< PS congiguration */ #define SDIO_PWRCTRL_PS_Pos (0U) #define SDIO_PWRCTRL_PS_Msk (0x3U << SDIO_PWRCTRL_PS_Pos) /*!< 0x00000003 */ #define SDIO_PWRCTRL_PS SDIO_PWRCTRL_PS_Msk /*!< PS[1:0] bits (Power switch) */ @@ -9644,6 +9770,7 @@ typedef struct #define SDIO_CLKCTRL_BYPSEN_Msk (0x1U << SDIO_CLKCTRL_BYPSEN_Pos) /*!< 0x00000400 */ #define SDIO_CLKCTRL_BYPSEN SDIO_CLKCTRL_BYPSEN_Msk /*!< Clock divider bypass enable bit */ +/*!< BUSWS congiguration */ #define SDIO_CLKCTRL_BUSWS_Pos (11U) #define SDIO_CLKCTRL_BUSWS_Msk (0x3U << SDIO_CLKCTRL_BUSWS_Pos) /*!< 0x00001800 */ #define SDIO_CLKCTRL_BUSWS SDIO_CLKCTRL_BUSWS_Msk /*!< BUSWS[1:0] bits (Bus width selection) */ @@ -9667,6 +9794,7 @@ typedef struct #define SDIO_CMD_CMDIDX_Msk (0x3FU << SDIO_CMD_CMDIDX_Pos) /*!< 0x0000003F */ #define SDIO_CMD_CMDIDX SDIO_CMD_CMDIDX_Msk /*!< Command index */ +/*!< RSPWT congiguration */ #define SDIO_CMD_RSPWT_Pos (6U) #define SDIO_CMD_RSPWT_Msk (0x3U << SDIO_CMD_RSPWT_Pos) /*!< 0x000000C0 */ #define SDIO_CMD_RSPWT SDIO_CMD_RSPWT_Msk /*!< RSPWT[1:0] bits (Wait for response bits) */ @@ -9717,7 +9845,7 @@ typedef struct #define SDIO_DTTMR_TIMEOUT SDIO_DTTMR_TIMEOUT_Msk /*!< Data timeout period */ /****************** Bit definition for SDIO_DTLEN register ******************/ -#define SDIO_DTLEN_DTLEN_Pos (0U) +#define SDIO_DTLEN_DTLEN_Pos (0U) #define SDIO_DTLEN_DTLEN_Msk (0x1FFFFFFU << SDIO_DTLEN_DTLEN_Pos) /*!< 0x01FFFFFF */ #define SDIO_DTLEN_DTLEN SDIO_DTLEN_DTLEN_Msk /*!< Data length value */ @@ -9735,6 +9863,7 @@ typedef struct #define SDIO_DTCTRL_DMAEN_Msk (0x1U << SDIO_DTCTRL_DMAEN_Pos) /*!< 0x00000008 */ #define SDIO_DTCTRL_DMAEN SDIO_DTCTRL_DMAEN_Msk /*!< DMA enable bit */ +/*!< BLKSIZE congiguration */ #define SDIO_DTCTRL_BLKSIZE_Pos (4U) #define SDIO_DTCTRL_BLKSIZE_Msk (0xFU << SDIO_DTCTRL_BLKSIZE_Pos) /*!< 0x000000F0 */ #define SDIO_DTCTRL_BLKSIZE SDIO_DTCTRL_BLKSIZE_Msk /*!< BLKSIZE[3:0] bits (Data block size) */ @@ -9968,6 +10097,7 @@ typedef struct #define CMP_CTRLSTS1_CMP1SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP1SSEL_Pos) /*!< 0x00000004 */ #define CMP_CTRLSTS1_CMP1SSEL CMP_CTRLSTS1_CMP1SSEL_Msk /*!< Comparator 1 speed selection */ +/*!< CMP1INVSEL congiguration */ #define CMP_CTRLSTS1_CMP1INVSEL_Pos (4U) #define CMP_CTRLSTS1_CMP1INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000070 */ #define CMP_CTRLSTS1_CMP1INVSEL CMP_CTRLSTS1_CMP1INVSEL_Msk /*!< CMP1INVSEL[2:0] bits (Comparator 1 inverting selection) */ @@ -9975,6 +10105,7 @@ typedef struct #define CMP_CTRLSTS1_CMP1INVSEL_1 (0x2U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000020 */ #define CMP_CTRLSTS1_CMP1INVSEL_2 (0x4U << CMP_CTRLSTS1_CMP1INVSEL_Pos) /*!< 0x00000040 */ +/*!< CMP1TAG congiguration */ #define CMP_CTRLSTS1_CMP1TAG_Pos (8U) #define CMP_CTRLSTS1_CMP1TAG_Msk (0x7U << CMP_CTRLSTS1_CMP1TAG_Pos) /*!< 0x00000700 */ #define CMP_CTRLSTS1_CMP1TAG CMP_CTRLSTS1_CMP1TAG_Msk /*!< CMP1TAG[2:0] bits (Comparator 1 output target) */ @@ -9986,6 +10117,7 @@ typedef struct #define CMP_CTRLSTS1_CMP1P_Msk (0x1U << CMP_CTRLSTS1_CMP1P_Pos) /*!< 0x00000800 */ #define CMP_CTRLSTS1_CMP1P CMP_CTRLSTS1_CMP1P_Msk /*!< Comparator 1 polarity */ +/*!< CMP1HYST congiguration */ #define CMP_CTRLSTS1_CMP1HYST_Pos (12U) #define CMP_CTRLSTS1_CMP1HYST_Msk (0x3U << CMP_CTRLSTS1_CMP1HYST_Pos) /*!< 0x00003000 */ #define CMP_CTRLSTS1_CMP1HYST CMP_CTRLSTS1_CMP1HYST_Msk /*!< CMP1HYST[1:0] bits (Comparator 1 hysteresis) */ @@ -10005,6 +10137,7 @@ typedef struct #define CMP_CTRLSTS1_CMP2SSEL_Msk (0x1U << CMP_CTRLSTS1_CMP2SSEL_Pos) /*!< 0x00040000 */ #define CMP_CTRLSTS1_CMP2SSEL CMP_CTRLSTS1_CMP2SSEL_Msk /*!< Comparator 2 speed selection */ +/*!< CMP2INVSEL congiguration */ #define CMP_CTRLSTS1_CMP2INVSEL_Pos (20U) #define CMP_CTRLSTS1_CMP2INVSEL_Msk (0x7U << CMP_CTRLSTS1_CMP2INVSEL_Pos) /*!< 0x00700000 */ #define CMP_CTRLSTS1_CMP2INVSEL CMP_CTRLSTS1_CMP2INVSEL_Msk /*!< CMP2INVSEL[2:0] bits (Comparator 2 inverting selection) */ @@ -10016,6 +10149,7 @@ typedef struct #define CMP_CTRLSTS1_DCMPEN_Msk (0x1U << CMP_CTRLSTS1_DCMPEN_Pos) /*!< 0x00800000 */ #define CMP_CTRLSTS1_DCMPEN CMP_CTRLSTS1_DCMPEN_Msk /*!< Double comparator mode enable */ +/*!< CMP2TAG congiguration */ #define CMP_CTRLSTS1_CMP2TAG_Pos (24U) #define CMP_CTRLSTS1_CMP2TAG_Msk (0x7U << CMP_CTRLSTS1_CMP2TAG_Pos) /*!< 0x07000000 */ #define CMP_CTRLSTS1_CMP2TAG CMP_CTRLSTS1_CMP2TAG_Msk /*!< CMP2TAG[2:0] bits (Comparator 2 output target) */ @@ -10027,6 +10161,7 @@ typedef struct #define CMP_CTRLSTS1_CMP2P_Msk (0x1U << CMP_CTRLSTS1_CMP2P_Pos) /*!< 0x08000000 */ #define CMP_CTRLSTS1_CMP2P CMP_CTRLSTS1_CMP2P_Msk /*!< Comparator 2 polarity */ +/*!< CMP2HYST congiguration */ #define CMP_CTRLSTS1_CMP2HYST_Pos (28U) #define CMP_CTRLSTS1_CMP2HYST_Msk (0x3U << CMP_CTRLSTS1_CMP2HYST_Pos) /*!< 0x30000000 */ #define CMP_CTRLSTS1_CMP2HYST CMP_CTRLSTS1_CMP2HYST_Msk /*!< CMP2HYST[1:0] bits (Comparator 2 hysteresis) */ @@ -10041,15 +10176,17 @@ typedef struct #define CMP_CTRLSTS1_CMP2WP CMP_CTRLSTS1_CMP2WP_Msk /*!< Comparator 2 write protect */ /***************** Bit definition for CMP_CTRLSTS2 register *****************/ +/*!< CMP1NINVSEL congiguration */ #define CMP_CTRLSTS2_CMP1NINVSEL_Pos (0U) #define CMP_CTRLSTS2_CMP1NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000003 */ -#define CMP_CTRLSTS2_CMP1NINVSEL CMP_CTRLSTS2_CMP1NINVSEL_Msk /*!< Comparator 1 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP1NINVSEL CMP_CTRLSTS2_CMP1NINVSEL_Msk /*!< CMP1NINVSEL[1:0] bits (Comparator 1 non-inverting input selection) */ #define CMP_CTRLSTS2_CMP1NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000001 */ #define CMP_CTRLSTS2_CMP1NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP1NINVSEL_Pos) /*!< 0x00000002 */ +/*!< CMP2NINVSEL congiguration */ #define CMP_CTRLSTS2_CMP2NINVSEL_Pos (16U) #define CMP_CTRLSTS2_CMP2NINVSEL_Msk (0x3U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00030000 */ -#define CMP_CTRLSTS2_CMP2NINVSEL CMP_CTRLSTS2_CMP2NINVSEL_Msk /*!< Comparator 2 non-inverting input selection */ +#define CMP_CTRLSTS2_CMP2NINVSEL CMP_CTRLSTS2_CMP2NINVSEL_Msk /*!< CMP2NINVSEL[1:0] bits (Comparator 2 non-inverting input selection) */ #define CMP_CTRLSTS2_CMP2NINVSEL_0 (0x1U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00010000 */ #define CMP_CTRLSTS2_CMP2NINVSEL_1 (0x2U << CMP_CTRLSTS2_CMP2NINVSEL_Pos) /*!< 0x00020000 */ @@ -10060,6 +10197,7 @@ typedef struct /******************************************************************************/ /***************** Bit definition for DEBUG_IDCODE register *****************/ +/*!< PID congiguration */ #define DEBUG_IDCODE_PID_Pos (0U) #define DEBUG_IDCODE_PID_Msk (0xFFFFFFFFU << DEBUG_IDCODE_PID_Pos) /*!< 0xFFFFFFFF */ #define DEBUG_IDCODE_PID DEBUG_IDCODE_PID_Msk /*!< PID[31:0] bits (PID information) */ @@ -10110,6 +10248,7 @@ typedef struct #define DEBUG_CTRL_TRACE_IOEN_Msk (0x1U << DEBUG_CTRL_TRACE_IOEN_Pos) /*!< 0x00000020 */ #define DEBUG_CTRL_TRACE_IOEN DEBUG_CTRL_TRACE_IOEN_Msk /*!< Trace pin assignment enable */ +/*!< TRACE_MODE congiguration */ #define DEBUG_CTRL_TRACE_MODE_Pos (6U) #define DEBUG_CTRL_TRACE_MODE_Msk (0x3U << DEBUG_CTRL_TRACE_MODE_Pos) /*!< 0x000000C0 */ #define DEBUG_CTRL_TRACE_MODE DEBUG_CTRL_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace pin assignment control) */ @@ -10168,355 +10307,6 @@ typedef struct * @{ */ -/******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) - -#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) - -#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) - -/******************************* CAN Instances ********************************/ -#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) - -/******************************* CRC Instances ********************************/ -#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) - -/******************************* DMA Instances ********************************/ -#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ - ((INSTANCE) == DMA1_Channel2) || \ - ((INSTANCE) == DMA1_Channel3) || \ - ((INSTANCE) == DMA1_Channel4) || \ - ((INSTANCE) == DMA1_Channel5) || \ - ((INSTANCE) == DMA1_Channel6) || \ - ((INSTANCE) == DMA1_Channel7) || \ - ((INSTANCE) == DMA2_Channel1) || \ - ((INSTANCE) == DMA2_Channel2) || \ - ((INSTANCE) == DMA2_Channel3) || \ - ((INSTANCE) == DMA2_Channel4) || \ - ((INSTANCE) == DMA2_Channel5) || \ - ((INSTANCE) == DMA2_Channel6) || \ - ((INSTANCE) == DMA2_Channel7)) - -/******************************* GPIO Instances *******************************/ -#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ - ((INSTANCE) == GPIOB) || \ - ((INSTANCE) == GPIOC) || \ - ((INSTANCE) == GPIOD) || \ - ((INSTANCE) == GPIOF)) - -/********************* IOMUX Multiplex Function Instances *********************/ -#define IS_IOMUX_ALL_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) - -/**************************** GPIO Lock Instances *****************************/ -#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) - -/******************************* I2C Instances ********************************/ -#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ - ((INSTANCE) == I2C2)) - -/****************************** SMBUS Instances *******************************/ -#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE - -/******************************* I2S Instances ********************************/ -#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ - ((INSTANCE) == SPI2)) - -/******************************* WDT Instances ********************************/ -#define IS_WDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WDT) - -/******************************* SDIO Instances *******************************/ -#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) - -/******************************* SPI Instances ********************************/ -#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ - ((INSTANCE) == SPI2)) - -/**************************** START TMR Instances *****************************/ -/******************************* TMR Instances ********************************/ -#define IS_TMR_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9) || \ - ((INSTANCE) == TMR10) || \ - ((INSTANCE) == TMR11)) - -#define IS_TMR_ADVANCED_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1) - -#define IS_TMR_C1_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9) || \ - ((INSTANCE) == TMR10) || \ - ((INSTANCE) == TMR11)) - -#define IS_TMR_C2_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_C3_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_C4_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_CLOCKSOURCE_EXTMODE1_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_CLOCKSOURCE_EXTMODE2_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_CLOCKSOURCE_TRGIN_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_CLOCKSOURCE_ISX_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_OCXREF_CLEAR_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_XOR_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_MASTER_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_SLAVE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9)) - -#define IS_TMR_DMABURST_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_BREAK_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1) - -#define IS_TMR_CX_INSTANCE(INSTANCE, CHANNEL) \ - ((((INSTANCE) == TMR1) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR2) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR3) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR4) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR5) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3) || \ - ((CHANNEL) == TMR_CHANNEL_4))) \ - || \ - (((INSTANCE) == TMR9) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2))) \ - || \ - (((INSTANCE) == TMR10) && \ - (((CHANNEL) == TMR_CHANNEL_1))) \ - || \ - (((INSTANCE) == TMR11) && \ - (((CHANNEL) == TMR_CHANNEL_1)))) - -#define IS_TMR_CXN_INSTANCE(INSTANCE, CHANNEL) \ - (((INSTANCE) == TMR1) && \ - (((CHANNEL) == TMR_CHANNEL_1) || \ - ((CHANNEL) == TMR_CHANNEL_2) || \ - ((CHANNEL) == TMR_CHANNEL_3))) - -#define IS_TMR_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_REPETITION_COUNTER_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1) - -#define IS_TMR_CLOCK_DIVISION_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5) || \ - ((INSTANCE) == TMR9) || \ - ((INSTANCE) == TMR10) || \ - ((INSTANCE) == TMR11)) - -#define IS_TMR_DMA_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_DMA_CC_INSTANCE(INSTANCE)\ - (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ - ((INSTANCE) == TMR1)) - -#define IS_TMR_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \ - ((INSTANCE) == TMR2) || \ - ((INSTANCE) == TMR3) || \ - ((INSTANCE) == TMR4) || \ - ((INSTANCE) == TMR5)) - -#define IS_TMR_32B_COUNTER_INSTANCE(INSTANCE) 0U - -/***************************** END TMR Instances ******************************/ - -/********************* USART Instances : Synchronous mode *********************/ -#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/********************* UART Instances : Asynchronous mode *********************/ -#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3) || \ - ((INSTANCE) == UART4) || \ - ((INSTANCE) == UART5)) - -/********************* UART Instances : Half-Duplex mode **********************/ -#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3) || \ - ((INSTANCE) == UART4) || \ - ((INSTANCE) == UART5)) - -/************************* UART Instances : LIN mode **************************/ -#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3) || \ - ((INSTANCE) == UART4) || \ - ((INSTANCE) == UART5)) - -/******************* UART Instances : Hardware Flow control *******************/ -#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/********************* UART Instances : Smard card mode ***********************/ -#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3)) - -/************************* UART Instances : IRDA mode *************************/ -#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3) || \ - ((INSTANCE) == UART4) || \ - ((INSTANCE) == UART5)) - -/******************* UART Instances : Multi-Processor mode ********************/ -#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3) || \ - ((INSTANCE) == UART4) || \ - ((INSTANCE) == UART5)) - -/******************** UART Instances : DMA mode available *********************/ -#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART3) || \ - ((INSTANCE) == UART4)) - -/******************************* ERTC Instances *******************************/ -#define IS_ERTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ERTC) - -/******************************* WWDT Instances *******************************/ -#define IS_WWDT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDT) - #define CRM_HEXT_MIN 4000000U #define CRM_HEXT_MAX 25000000U diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h index 9be1d33002..84677e5f7d 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h @@ -47,6 +47,10 @@ extern "C" { * @{ */ +/** + * @} + */ + /** @defgroup AT32F415_System_Clock_Stable_Definition * @{ */ diff --git a/os/hal/ports/AT32/AT32F415/at32_isr.h b/os/hal/ports/AT32/AT32F415/at32_isr.h index 239867cc1a..7599293edb 100644 --- a/os/hal/ports/AT32/AT32F415/at32_isr.h +++ b/os/hal/ports/AT32/AT32F415/at32_isr.h @@ -145,7 +145,7 @@ #define AT32_EXINT19_HANDLER Vector158 /* Note: same as CMP1_IRQn */ #define AT32_EXINT20_HANDLER Vector15C /* Note: same as CMP2_IRQn */ #define AT32_EXINT21_HANDLER Vector48 /* Note: same as TAMPER_IRQn */ -#define AT32_EXINT22_HANDLER Vector4C /* Note: same as ERTC_IRQn */ +#define AT32_EXINT22_HANDLER Vector4C /* Note: same as ERTC_WKUP_IRQn */ #define AT32_EXINT0_NUMBER 6 #define AT32_EXINT1_NUMBER 7 @@ -160,7 +160,7 @@ #define AT32_EXINT19_NUMBER 70 /* Note: same as CMP1_IRQn */ #define AT32_EXINT20_NUMBER 71 /* Note: same as CMP2_IRQn */ #define AT32_EXINT21_NUMBER 2 /* Note: same as TAMPER_IRQn */ -#define AT32_EXINT22_NUMBER 3 /* Note: same as ERTC_IRQn */ +#define AT32_EXINT22_NUMBER 3 /* Note: same as ERTC_WKUP_IRQn */ /* * I2C units. From ceb0454fcd77ebedc0c0e54b08a1ddb03b0ec87e Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Tue, 25 Jun 2024 13:42:33 +0700 Subject: [PATCH 02/18] Another patch update and cleanup AT32F415 files --- .../ARMCMx/devices/AT32F415/cmparams.h | 4 +- os/hal/boards/AT_START_F415/board.c | 36 ++- os/hal/boards/AT_START_F415/board.h | 89 +++-- os/hal/ports/AT32/AT32F415/at32_crm.h | 11 +- os/hal/ports/AT32/AT32F415/at32_isr.h | 10 +- os/hal/ports/AT32/AT32F415/at32_registry.h | 228 +++++++------ os/hal/ports/AT32/AT32F415/hal_efl_lld.c | 2 +- os/hal/ports/AT32/AT32F415/hal_lld.c | 70 ++-- os/hal/ports/AT32/AT32F415/hal_lld.h | 304 ++++++++++-------- 9 files changed, 415 insertions(+), 339 deletions(-) diff --git a/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h b/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h index 0e45ffc616..5a37704e76 100644 --- a/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h +++ b/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h @@ -13,11 +13,11 @@ ChibiOS/RT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License - along with this program. If not, see . + along with this program. If not, see . */ /** diff --git a/os/hal/boards/AT_START_F415/board.c b/os/hal/boards/AT_START_F415/board.c index ef92f8d769..fe4e2ddc2c 100644 --- a/os/hal/boards/AT_START_F415/board.c +++ b/os/hal/boards/AT_START_F415/board.c @@ -18,6 +18,18 @@ #include "hal.h" +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + /** * @brief PAL setup. * @details Digital I/O ports static configuration as defined in @p board.h. @@ -38,17 +50,29 @@ const PALConfig pal_default_config = }; #endif -/* - * Early initialization code. - * This initialization must be performed just after stack setup and before - * any other initialization. +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details System clocks are initialized before everything else. */ void __early_init(void) { at32_clock_init(); } -/* - * Board-specific initialization code. +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. */ void boardInit(void) { diff --git a/os/hal/boards/AT_START_F415/board.h b/os/hal/boards/AT_START_F415/board.h index 23f945bb5e..61b0c75a3f 100644 --- a/os/hal/boards/AT_START_F415/board.h +++ b/os/hal/boards/AT_START_F415/board.h @@ -19,6 +19,10 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + /* * Setup for a AT-START-F415 board. */ @@ -30,10 +34,15 @@ #define BOARD_NAME "Artery AT-START-F415" /* - * Board frequencies. + * Board oscillators-related settings. */ +#if !defined(AT32_LEXTCLK) #define AT32_LEXTCLK 32768 +#endif + +#if !defined(AT32_HEXTCLK) #define AT32_HEXTCLK 8000000 +#endif /* * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. @@ -43,17 +52,11 @@ /* * IO pins assignments. */ -#define GPIOA_ARD_A0 0U -#define GPIOA_ADC1_IN0 0U #define GPIOA_BUTTON 0U #define GPIOA_ARD_A1 1U -#define GPIOA_ADC1_IN1 1U #define GPIOA_ARD_D1 2U -#define GPIOA_USART2_TX 2U #define GPIOA_ARD_D0 3U -#define GPIOA_USART2_RX 3U #define GPIOA_ARD_A2 4U -#define GPIOA_ADC1_IN4 4U #define GPIOA_ARD_D13 5U #define GPIOA_ARD_D12 6U #define GPIOA_ARD_D11 7U @@ -67,10 +70,8 @@ #define GPIOA_ARD_D10 15U #define GPIOB_ARD_A3 0U -#define GPIOB_ADC1_IN8 0U #define GPIOB_PIN1 1U #define GPIOB_PIN2 2U -#define GPIOB_ARD_D3 3U #define GPIOB_SWO 3U #define GPIOB_ARD_D5 4U #define GPIOB_ARD_D4 5U @@ -79,19 +80,14 @@ #define GPIOB_ARD_SCL 8U #define GPIOB_ARD_SDA 9U #define GPIOB_ARD_D6 10U -#define GPIOB_PIN10 10U #define GPIOB_ARD_PB11 11U -#define GPIOB_PIN11 11U #define GPIOB_ARD_NSS 12U -#define GPIOB_PIN12 12U #define GPIOB_ARD_SCK 13U #define GPIOB_ARD_MISO 14U #define GPIOB_ARD_MOSI 15U #define GPIOC_ARD_A5 0U -#define GPIOC_ADC1_IN10 0U #define GPIOC_ARD_A4 1U -#define GPIOC_ADC1_IN11 1U #define GPIOC_LED_RED 2U #define GPIOC_LED_YELLOW 3U #define GPIOC_PIN4 4U @@ -104,44 +100,33 @@ #define GPIOC_PIN11 11U #define GPIOC_PIN12 12U #define GPIOC_BUTTON 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U +#define GPIOC_LEXT_IN 14U +#define GPIOC_LEXT_OUT 15U -#define GPIOD_OSC_IN 0U -#define GPIOD_PIN0 0U -#define GPIOD_OSC_OUT 1U -#define GPIOD_PIN1 1U +#define GPIOD_HEXT_IN 0U +#define GPIOD_HEXT_OUT 1U #define GPIOD_PIN2 2U -#define GPIOD_PIN3 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_PIN6 6U -#define GPIOD_PIN7 7U -#define GPIOD_PIN8 8U -#define GPIOD_PIN9 9U -#define GPIOD_PIN10 10U -#define GPIOD_PIN11 11U -#define GPIOD_PIN12 12U -#define GPIOD_PIN13 13U -#define GPIOD_PIN14 14U -#define GPIOD_PIN15 15U - -#define GPIOF_PIN0 0U -#define GPIOF_PIN1 1U -#define GPIOF_PIN2 2U -#define GPIOF_PIN3 3U + #define GPIOF_PIN4 4U #define GPIOF_PIN5 5U #define GPIOF_PIN6 6U #define GPIOF_PIN7 7U -#define GPIOF_PIN8 8U -#define GPIOF_PIN9 9U -#define GPIOF_PIN10 10U -#define GPIOF_PIN11 11U -#define GPIOF_PIN12 12U -#define GPIOF_PIN13 13U -#define GPIOF_PIN14 14U -#define GPIOF_PIN15 15U + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ /* * I/O ports initial setup, this configuration is established soon after reset @@ -171,8 +156,8 @@ * Port A setup. * Everything input with pull-up except: * PA0 - Normal input (GPIOA_BUTTON) - * PA2 - Alternate output (GPIOA_ARD_D1, GPIOA_USART2_TX) - * PA3 - Normal input (GPIOA_ARD_D0, GPIOA_USART2_RX) + * PA2 - Alternate output (GPIOA_ARD_D1) + * PA3 - Normal input (GPIOA_ARD_D0) * PA14 - Pull-down input (GPIOA_SWCLK) */ #define VAL_GPIOACFGLR 0x88884B84 /* PA7...PA0 */ @@ -201,8 +186,8 @@ /* * Port D setup. * Everything input with pull-up except: - * PD0 - Normal input (GPIOD_OSC_IN). - * PD1 - Normal input (GPIOD_OSC_OUT). + * PD0 - Normal input (GPIOD_HEXT_IN). + * PD1 - Normal input (GPIOD_HEXT_OUT). */ #define VAL_GPIODCFGLR 0x88888844 /* PD7...PD0 */ #define VAL_GPIODCFGHR 0x88888888 /* PD15...PD8 */ @@ -215,6 +200,10 @@ #define VAL_GPIOFCFGHR 0x88888888 /* PF15...PF8 */ #define VAL_GPIOFODT 0xFFFFFFFF +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + #if !defined(_FROM_ASM_) #ifdef __cplusplus extern "C" { diff --git a/os/hal/ports/AT32/AT32F415/at32_crm.h b/os/hal/ports/AT32/AT32F415/at32_crm.h index 0c42907f63..60f7ddaeb0 100644 --- a/os/hal/ports/AT32/AT32F415/at32_crm.h +++ b/os/hal/ports/AT32/AT32F415/at32_crm.h @@ -69,7 +69,6 @@ /** * @brief Disables the clock of one or more peripheral on the APB1 bus. - * @note The @p lp parameter is ignored in this family. * * @param[in] mask APB1 peripherals mask * @@ -109,7 +108,6 @@ /** * @brief Disables the clock of one or more peripheral on the APB2 bus. - * @note The @p lp parameter is ignored in this family. * * @param[in] mask APB2 peripherals mask * @@ -149,7 +147,6 @@ /** * @brief Disables the clock of one or more peripheral on the AHB bus. - * @note The @p lp parameter is ignored in this family. * * @param[in] mask AHB peripherals mask * @@ -259,6 +256,7 @@ * @api */ #define crmResetCAN1() crmResetAPB1(CRM_APB1RST_CAN1RST) +/** @} */ /** * @name DMA peripherals specific CRM operations @@ -307,7 +305,7 @@ #define crmDisableDMA2() crmDisableAHB(CRM_AHBEN_DMA2EN) /** - * @brief Resets the DMA1 peripheral. + * @brief Resets the DMA2 peripheral. * @note Not supported in this family, does nothing. * * @api @@ -374,6 +372,7 @@ */ /** * @brief Enables the OTG_FS peripheral clock. + * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -397,7 +396,7 @@ /** @} */ /** - * @name SDIO peripheral specific CRM operations + * @name SDIO peripherals specific CRM operations * @{ */ /** @@ -477,6 +476,7 @@ * @api */ #define crmResetSPI2() crmResetAPB1(CRM_APB1RST_SPI2RST) +/** @} */ /** * @name TMR peripherals specific CRM operations @@ -673,6 +673,7 @@ * @api */ #define crmResetTMR11() crmResetAPB2(CRM_APB2RST_TMR11RST) +/** @} */ /** * @name USART/UART peripherals specific CRM operations diff --git a/os/hal/ports/AT32/AT32F415/at32_isr.h b/os/hal/ports/AT32/AT32F415/at32_isr.h index 7599293edb..277b402f45 100644 --- a/os/hal/ports/AT32/AT32F415/at32_isr.h +++ b/os/hal/ports/AT32/AT32F415/at32_isr.h @@ -56,7 +56,7 @@ * @{ */ /* - * CAN units. + * CAN unit. */ #define AT32_CAN1_TX_HANDLER Vector8C #define AT32_CAN1_RX0_HANDLER Vector90 @@ -69,7 +69,7 @@ #define AT32_CAN1_SE_NUMBER 22 /* - * DMA unit + * DMA units. */ #define AT32_DMA1_CH1_HANDLER Vector6C #define AT32_DMA1_CH2_HANDLER Vector70 @@ -110,7 +110,7 @@ #define AT32_DMA2_CH7_CMASK 0x00003000U /* - * ERTC unit + * ERTC unit. */ #define AT32_ERTC_TAMP_STAMP_HANDLER Vector48 #define AT32_ERTC_WKUP_HANDLER Vector4C @@ -130,7 +130,7 @@ } while (false) /* - * EXINT unit. + * EXINT units. */ #define AT32_EXINT0_HANDLER Vector58 #define AT32_EXINT1_HANDLER Vector5C @@ -176,7 +176,7 @@ #define AT32_I2C2_ERROR_NUMBER 34 /* - * OTGFS units. + * OTG unit. */ #define AT32_OTG1_HANDLER Vector14C diff --git a/os/hal/ports/AT32/AT32F415/at32_registry.h b/os/hal/ports/AT32/AT32F415/at32_registry.h index 93463f5fc4..4213e294eb 100644 --- a/os/hal/ports/AT32/AT32F415/at32_registry.h +++ b/os/hal/ports/AT32/AT32F415/at32_registry.h @@ -73,6 +73,8 @@ #define AT32_CAN_MAX_FILTERS 14 /* DMA attributes.*/ +#define AT32_ADVANCED_DMA FALSE + #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) #define AT32_DMA_SUPPORTS_DMAMUX TRUE #else @@ -97,8 +99,9 @@ /* GPIO attributes.*/ #define AT32_HAS_GPIOA TRUE #define AT32_HAS_GPIOB TRUE -#define AT32_HAS_GPIOC FALSE #define AT32_HAS_GPIOD TRUE + +#define AT32_HAS_GPIOC FALSE #define AT32_HAS_GPIOF FALSE /* I2C attributes.*/ @@ -126,6 +129,8 @@ #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #endif +#define AT32_HAS_I2C3 FALSE + /* ERTC attributes.*/ #define AT32_HAS_ERTC TRUE #define AT32_ERTC_HAS_SUBSECONDS TRUE @@ -133,6 +138,9 @@ #define AT32_ERTC_NUM_ALARMS 2 #define AT32_ERTC_STORAGE_SIZE 80 +/* QUADSPI attributes.*/ +#define AT32_HAS_QUADSPI1 FALSE + /* SDIO attributes.*/ #define AT32_HAS_SDIO1 TRUE @@ -172,6 +180,8 @@ #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #endif +#define AT32_HAS_SPI3 FALSE + /* TMR attributes.*/ #define AT32_TMR_MAX_CHANNELS 4 @@ -207,6 +217,11 @@ #define AT32_TMR11_IS_32BITS FALSE #define AT32_TMR11_CHANNELS 1 +#define AT32_HAS_TMR6 FALSE +#define AT32_HAS_TMR7 FALSE +#define AT32_HAS_TMR13 FALSE +#define AT32_HAS_TMR14 FALSE + /* USART attributes.*/ #define AT32_HAS_USART1 TRUE @@ -233,45 +248,23 @@ #endif #define AT32_HAS_USART3 FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#endif - #define AT32_HAS_UART4 FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) -#endif - #define AT32_HAS_UART5 FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 -#endif +#define AT32_HAS_USART6 FALSE +#define AT32_HAS_UART7 FALSE +#define AT32_HAS_UART8 FALSE /* USB attributes.*/ #define AT32_OTG_STEPPING 1 + #define AT32_HAS_OTG1 TRUE #define AT32_OTG1_ENDPOINTS 3 +#define AT32_HAS_OTG2 FALSE + /* WDT attributes.*/ #define AT32_HAS_WDT TRUE +#define AT32_WDT_IS_WINDOWED FALSE /* CRC attributes.*/ #define AT32_HAS_CRC TRUE @@ -298,6 +291,8 @@ #define AT32_CAN_MAX_FILTERS 14 /* DMA attributes.*/ +#define AT32_ADVANCED_DMA FALSE + #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) #define AT32_DMA_SUPPORTS_DMAMUX TRUE #else @@ -322,8 +317,9 @@ /* GPIO attributes.*/ #define AT32_HAS_GPIOA TRUE #define AT32_HAS_GPIOB TRUE -#define AT32_HAS_GPIOC FALSE #define AT32_HAS_GPIOD TRUE + +#define AT32_HAS_GPIOC FALSE #define AT32_HAS_GPIOF FALSE /* I2C attributes.*/ @@ -351,6 +347,8 @@ #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #endif +#define AT32_HAS_I2C3 FALSE + /* ERTC attributes.*/ #define AT32_HAS_ERTC TRUE #define AT32_ERTC_HAS_SUBSECONDS TRUE @@ -358,6 +356,9 @@ #define AT32_ERTC_NUM_ALARMS 2 #define AT32_ERTC_STORAGE_SIZE 80 +/* QUADSPI attributes.*/ +#define AT32_HAS_QUADSPI1 FALSE + /* SDIO attributes.*/ #define AT32_HAS_SDIO1 TRUE @@ -397,6 +398,8 @@ #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #endif +#define AT32_HAS_SPI3 FALSE + /* TMR attributes.*/ #define AT32_TMR_MAX_CHANNELS 4 @@ -432,6 +435,11 @@ #define AT32_TMR11_IS_32BITS FALSE #define AT32_TMR11_CHANNELS 1 +#define AT32_HAS_TMR6 FALSE +#define AT32_HAS_TMR7 FALSE +#define AT32_HAS_TMR13 FALSE +#define AT32_HAS_TMR14 FALSE + /* USART attributes.*/ #define AT32_HAS_USART1 TRUE @@ -458,45 +466,23 @@ #endif #define AT32_HAS_USART3 FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#endif - #define AT32_HAS_UART4 FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) -#endif - #define AT32_HAS_UART5 FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 -#endif +#define AT32_HAS_USART6 FALSE +#define AT32_HAS_UART7 FALSE +#define AT32_HAS_UART8 FALSE /* USB attributes.*/ #define AT32_OTG_STEPPING 1 + #define AT32_HAS_OTG1 TRUE #define AT32_OTG1_ENDPOINTS 3 +#define AT32_HAS_OTG2 FALSE + /* WDT attributes.*/ #define AT32_HAS_WDT TRUE +#define AT32_WDT_IS_WINDOWED FALSE /* CRC attributes.*/ #define AT32_HAS_CRC TRUE @@ -523,6 +509,8 @@ #define AT32_CAN_MAX_FILTERS 14 /* DMA attributes.*/ +#define AT32_ADVANCED_DMA FALSE + #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) #define AT32_DMA_SUPPORTS_DMAMUX TRUE #else @@ -576,6 +564,8 @@ #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #endif +#define AT32_HAS_I2C3 FALSE + /* ERTC attributes.*/ #define AT32_HAS_ERTC TRUE #define AT32_ERTC_HAS_SUBSECONDS TRUE @@ -583,6 +573,9 @@ #define AT32_ERTC_NUM_ALARMS 2 #define AT32_ERTC_STORAGE_SIZE 80 +/* QUADSPI attributes.*/ +#define AT32_HAS_QUADSPI1 FALSE + /* SDIO attributes.*/ #define AT32_HAS_SDIO1 TRUE @@ -622,6 +615,8 @@ #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #endif +#define AT32_HAS_SPI3 FALSE + /* TMR attributes.*/ #define AT32_TMR_MAX_CHANNELS 4 @@ -657,6 +652,11 @@ #define AT32_TMR11_IS_32BITS FALSE #define AT32_TMR11_CHANNELS 1 +#define AT32_HAS_TMR6 FALSE +#define AT32_HAS_TMR7 FALSE +#define AT32_HAS_TMR13 FALSE +#define AT32_HAS_TMR14 FALSE + /* USART attributes.*/ #define AT32_HAS_USART1 TRUE @@ -695,33 +695,22 @@ #endif #define AT32_HAS_UART4 FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) -#endif - #define AT32_HAS_UART5 FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 -#endif +#define AT32_HAS_USART6 FALSE +#define AT32_HAS_UART7 FALSE +#define AT32_HAS_UART8 FALSE /* USB attributes.*/ #define AT32_OTG_STEPPING 1 + #define AT32_HAS_OTG1 TRUE #define AT32_OTG1_ENDPOINTS 3 +#define AT32_HAS_OTG2 FALSE + /* WDT attributes.*/ #define AT32_HAS_WDT TRUE +#define AT32_WDT_IS_WINDOWED FALSE /* CRC attributes.*/ #define AT32_HAS_CRC TRUE @@ -748,6 +737,8 @@ #define AT32_CAN_MAX_FILTERS 14 /* DMA attributes.*/ +#define AT32_ADVANCED_DMA FALSE + #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) #define AT32_DMA_SUPPORTS_DMAMUX TRUE #else @@ -801,6 +792,8 @@ #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #endif +#define AT32_HAS_I2C3 FALSE + /* ERTC attributes.*/ #define AT32_HAS_ERTC TRUE #define AT32_ERTC_HAS_SUBSECONDS TRUE @@ -808,6 +801,9 @@ #define AT32_ERTC_NUM_ALARMS 2 #define AT32_ERTC_STORAGE_SIZE 80 +/* QUADSPI attributes.*/ +#define AT32_HAS_QUADSPI1 FALSE + /* SDIO attributes.*/ #define AT32_HAS_SDIO1 TRUE @@ -847,6 +843,8 @@ #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #endif +#define AT32_HAS_SPI3 FALSE + /* TMR attributes.*/ #define AT32_TMR_MAX_CHANNELS 4 @@ -882,6 +880,11 @@ #define AT32_TMR11_IS_32BITS FALSE #define AT32_TMR11_CHANNELS 1 +#define AT32_HAS_TMR6 FALSE +#define AT32_HAS_TMR7 FALSE +#define AT32_HAS_TMR13 FALSE +#define AT32_HAS_TMR14 FALSE + /* USART attributes.*/ #define AT32_HAS_USART1 TRUE @@ -920,33 +923,22 @@ #endif #define AT32_HAS_UART4 FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) -#endif - #define AT32_HAS_UART5 FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 -#endif +#define AT32_HAS_USART6 FALSE +#define AT32_HAS_UART7 FALSE +#define AT32_HAS_UART8 FALSE /* USB attributes.*/ #define AT32_OTG_STEPPING 1 + #define AT32_HAS_OTG1 TRUE #define AT32_OTG1_ENDPOINTS 3 +#define AT32_HAS_OTG2 FALSE + /* WDT attributes.*/ #define AT32_HAS_WDT TRUE +#define AT32_WDT_IS_WINDOWED FALSE /* CRC attributes.*/ #define AT32_HAS_CRC TRUE @@ -973,6 +965,8 @@ #define AT32_CAN_MAX_FILTERS 14 /* DMA attributes.*/ +#define AT32_ADVANCED_DMA FALSE + #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) #define AT32_DMA_SUPPORTS_DMAMUX TRUE #else @@ -1026,6 +1020,8 @@ #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #endif +#define AT32_HAS_I2C3 FALSE + /* ERTC attributes.*/ #define AT32_HAS_ERTC TRUE #define AT32_ERTC_HAS_SUBSECONDS TRUE @@ -1033,6 +1029,9 @@ #define AT32_ERTC_NUM_ALARMS 2 #define AT32_ERTC_STORAGE_SIZE 80 +/* QUADSPI attributes.*/ +#define AT32_HAS_QUADSPI1 FALSE + /* SDIO attributes.*/ #define AT32_HAS_SDIO1 TRUE @@ -1072,6 +1071,8 @@ #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #endif +#define AT32_HAS_SPI3 FALSE + /* TMR attributes.*/ #define AT32_TMR_MAX_CHANNELS 4 @@ -1107,6 +1108,11 @@ #define AT32_TMR11_IS_32BITS FALSE #define AT32_TMR11_CHANNELS 1 +#define AT32_HAS_TMR6 FALSE +#define AT32_HAS_TMR7 FALSE +#define AT32_HAS_TMR13 FALSE +#define AT32_HAS_TMR14 FALSE + /* USART attributes.*/ #define AT32_HAS_USART1 TRUE @@ -1165,13 +1171,21 @@ #define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 #endif +#define AT32_HAS_USART6 FALSE +#define AT32_HAS_UART7 FALSE +#define AT32_HAS_UART8 FALSE + /* USB attributes.*/ #define AT32_OTG_STEPPING 1 + #define AT32_HAS_OTG1 TRUE #define AT32_OTG1_ENDPOINTS 3 +#define AT32_HAS_OTG2 FALSE + /* WDT attributes.*/ #define AT32_HAS_WDT TRUE +#define AT32_WDT_IS_WINDOWED FALSE /* CRC attributes.*/ #define AT32_HAS_CRC TRUE @@ -1198,6 +1212,8 @@ #define AT32_CAN_MAX_FILTERS 14 /* DMA attributes.*/ +#define AT32_ADVANCED_DMA FALSE + #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) #define AT32_DMA_SUPPORTS_DMAMUX TRUE #else @@ -1251,6 +1267,8 @@ #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #endif +#define AT32_HAS_I2C3 FALSE + /* ERTC attributes.*/ #define AT32_HAS_ERTC TRUE #define AT32_ERTC_HAS_SUBSECONDS TRUE @@ -1258,6 +1276,9 @@ #define AT32_ERTC_NUM_ALARMS 2 #define AT32_ERTC_STORAGE_SIZE 80 +/* QUADSPI attributes.*/ +#define AT32_HAS_QUADSPI1 FALSE + /* SDIO attributes.*/ #define AT32_HAS_SDIO1 TRUE @@ -1297,6 +1318,8 @@ #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #endif +#define AT32_HAS_SPI3 FALSE + /* TMR attributes.*/ #define AT32_TMR_MAX_CHANNELS 4 @@ -1332,6 +1355,11 @@ #define AT32_TMR11_IS_32BITS FALSE #define AT32_TMR11_CHANNELS 1 +#define AT32_HAS_TMR6 FALSE +#define AT32_HAS_TMR7 FALSE +#define AT32_HAS_TMR13 FALSE +#define AT32_HAS_TMR14 FALSE + /* USART attributes.*/ #define AT32_HAS_USART1 TRUE @@ -1390,13 +1418,21 @@ #define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 #endif +#define AT32_HAS_USART6 FALSE +#define AT32_HAS_UART7 FALSE +#define AT32_HAS_UART8 FALSE + /* USB attributes.*/ #define AT32_OTG_STEPPING 1 + #define AT32_HAS_OTG1 TRUE #define AT32_OTG1_ENDPOINTS 3 +#define AT32_HAS_OTG2 FALSE + /* WDT attributes.*/ #define AT32_HAS_WDT TRUE +#define AT32_WDT_IS_WINDOWED FALSE /* CRC attributes.*/ #define AT32_HAS_CRC TRUE diff --git a/os/hal/ports/AT32/AT32F415/hal_efl_lld.c b/os/hal/ports/AT32/AT32F415/hal_efl_lld.c index f14e0b1ca3..86471681dc 100644 --- a/os/hal/ports/AT32/AT32F415/hal_efl_lld.c +++ b/os/hal/ports/AT32/AT32F415/hal_efl_lld.c @@ -411,7 +411,7 @@ flash_error_t efl_lld_query_erase(void *instance, uint32_t *wait_time) { if (at32_flash_is_busy(devp) == 0U) { /* Disabling the various erase control bits.*/ - devp->flash->CTRL &= ~(FLASH_CTRL_USDERS | FLASH_CTRL_USDPRGM | + devp->flash->CTRL &= ~(FLASH_CTRL_USDERS | FLASH_CTRL_USDPRGM | FLASH_CTRL_BANKERS | FLASH_CTRL_SECERS); /* Back to ready state.*/ diff --git a/os/hal/ports/AT32/AT32F415/hal_lld.c b/os/hal/ports/AT32/AT32F415/hal_lld.c index 40bacd1d27..fbeb6bb9dd 100644 --- a/os/hal/ports/AT32/AT32F415/hal_lld.c +++ b/os/hal/ports/AT32/AT32F415/hal_lld.c @@ -55,22 +55,22 @@ uint32_t SystemCoreClock = AT32_HCLK; */ static void hal_lld_battery_powered_domain_init(void) { - /* Battery powered domain access enabled and left open. */ + /* Battery powered domain access enabled and left open.*/ PWC->CTRL |= PWC_CTRL_BPWEN; - /* Reset BPR domain if different clock source selected. */ + /* Reset BPR domain if different clock source selected.*/ if ((CRM->BPDC & AT32_ERTCSEL_MASK) != AT32_ERTCSEL) { - /* Battery powered domain reset. */ + /* Battery powered domain reset.*/ CRM->BPDC = CRM_BPDC_BPDRST; CRM->BPDC = 0; } #if AT32_LEXT_ENABLED #if defined(AT32_LEXT_BYPASS) - /* LEXT Bypass. */ + /* LEXT Bypass.*/ CRM->BPDC |= CRM_BPDC_LEXTEN | CRM_BPDC_LEXTBYPS; #else - /* No LEXT Bypass. */ + /* No LEXT Bypass.*/ CRM->BPDC |= CRM_BPDC_LEXTEN; #endif while ((CRM->BPDC & CRM_BPDC_LEXTSTBL) == 0) @@ -79,12 +79,12 @@ static void hal_lld_battery_powered_domain_init(void) { #if HAL_USE_RTC /* If the battery powered domain hasn't been initialized yet then proceed - with initialization. */ + with initialization.*/ if ((CRM->BPDC & CRM_BPDC_ERTCEN) == 0) { - /* Selects clock source. */ + /* Selects clock source.*/ CRM->BPDC |= AT32_ERTCSEL; - /* ERTC clock enabled. */ + /* ERTC clock enabled.*/ CRM->BPDC |= CRM_BPDC_ERTCEN; } #endif /* HAL_USE_RTC */ @@ -154,18 +154,18 @@ void hal_lld_init(void) { /* PWC clocks enabled. */ crmEnablePWCInterface(true); - /* Initializes the backup domain. */ + /* Initializes the backup domain.*/ hal_lld_battery_powered_domain_init(); - /* DMA subsystems initialization. */ + /* DMA subsystems initialization.*/ #if defined(AT32_DMA_REQUIRED) dmaInit(); #endif - /* IRQ subsystem initialization. */ + /* IRQ subsystem initialization.*/ irqInit(); - /* Power voltage monitoring enable. */ + /* Power voltage monitoring enable.*/ #if AT32_PVM_ENABLE PWC->CTRL |= PWC_CTRL_PVMEN | (AT32_PVMSEL & AT32_PVMSEL_MASK); #endif /* AT32_PVM_ENABLE */ @@ -186,7 +186,7 @@ void at32_clock_init(void) { #if !AT32_NO_INIT /* HICK setup, it enforces the reset situation in order to handle possible - problems with JTAG probes and re-initializations. */ + problems with JTAG probes and re-initializations.*/ CRM->CTRL |= CRM_CTRL_HICKEN; /* Make sure HICK is ON. */ while (!(CRM->CTRL & CRM_CTRL_HICKSTBL)) ; /* Wait until HICK is stable. */ @@ -199,22 +199,22 @@ void at32_clock_init(void) { ; /* Waits until HICK is selected. */ /* Registers finally cleared to reset values. */ - CRM->CTRL &= ~(0x010D0000U); /* CTRL reset value. */ - CRM->CFG = 0x00000000; /* CFG reset value. */ - CRM->PLL = 0x00001F10U; /* PLL reset value. */ - CRM->MISC1 = 0x00100000; /* MISC1 reset value. */ - CRM->MISC2 = 0x0000000D; /* MISC2 reset value. */ - CRM->CLKINT = 0x009F0000; /* CLKINT reset value. */ - - /* Flash setup and final clock selection. */ - FLASH->PSR = AT32_FLASHBITS; /* Flash wait states depending on clock. */ + CRM->CTRL &= ~(0x010D0000); /* CTRL reset value. */ + CRM->CFG = 0x00000000; /* CFG reset value. */ + CRM->PLL = 0x00001F10; /* PLL reset value. */ + CRM->MISC1 = 0x00100000; /* MISC1 reset value. */ + CRM->MISC2 = 0x0000000D; /* MISC2 reset value. */ + CRM->CLKINT = 0x009F0000; /* CLKINT reset value. */ + + /* Flash setup and final clock selection.*/ + FLASH->PSR = AT32_FLASHBITS; /* Flash wait states depending on clock.*/ while ((FLASH->PSR & FLASH_PSR_WTCYC_Msk) != (AT32_FLASHBITS & FLASH_PSR_WTCYC_Msk)) { } #if AT32_HEXT_ENABLED #if defined(AT32_HEXT_BYPASS) - /* HEXT Bypass. */ + /* HEXT Bypass.*/ CRM->CTRL |= CRM_CTRL_HEXTEN | CRM_CTRL_HEXTBYPS; #endif /* HEXT activation. */ @@ -224,14 +224,14 @@ void at32_clock_init(void) { #endif #if AT32_LICK_ENABLED - /* LICK activation. */ + /* LICK activation.*/ CRM->CTRLSTS |= CRM_CTRLSTS_LICKEN; while ((CRM->CTRLSTS & CRM_CTRLSTS_LICKSTBL) == 0) ; /* Waits until LICK is stable. */ #endif #if AT32_ACTIVATE_PLL - /* PLL activation. */ + /* PLL activation.*/ #if (AT32_PLLCFGEN == AT32_PLLCFGEN_SOLID) /* Solid PLL config. */ CRM->CFG |= AT32_PLLMULT | AT32_PLLHEXTDIV | AT32_PLLRCS; @@ -251,26 +251,26 @@ void at32_clock_init(void) { /* Clock settings.*/ #if AT32_HAS_OTG1 - CRM->CFG |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_CFG_MSK) | AT32_USBDIV | AT32_ADCDIV | - AT32_APB2DIV | AT32_APB1DIV | AT32_AHBDIV; + CRM->CFG |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_CFG_MASK) | AT32_USBDIV | AT32_ADCDIV | + AT32_APB2DIV | AT32_APB1DIV | AT32_AHBDIV; #else - CRM->CFG |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_CFG_MSK) | AT32_ADCDIV | - AT32_APB2DIV | AT32_APB1DIV | AT32_AHBDIV; + CRM->CFG |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_CFG_MASK) | AT32_ADCDIV | + AT32_APB2DIV | AT32_APB1DIV | AT32_AHBDIV; #endif - CRM->MISC1 |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_MISC_MSK) >> 11; + CRM->MISC1 |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_MISC1_MASK) >> 11 | AT32_CLKOUTDIV; - /* PLL Auto Step activation. */ + /* PLL auto step activation.*/ CRM->MISC2 |= CRM_MISC2_AUTO_STEP_EN; - /* Switching to the configured clock source if it is different from HICK. */ -#if (AT32_SCLKSEL != AT32_SCLKSEL_HICK) - /* Switches clock source. */ + /* Switching to the configured clock source if it is different from HICK.*/ +#if AT32_SCLKSEL != AT32_SCLKSEL_HICK + /* Switches clock source.*/ CRM->CFG |= AT32_SCLKSEL; while ((CRM->CFG & CRM_CFG_SCLKSTS) != (AT32_SCLKSEL << 2)) ; /* Waits selection complete. */ #endif - /* PLL Auto Step inactivation. */ + /* PLL auto step inactivation.*/ CRM->MISC2 &= ~CRM_MISC2_AUTO_STEP_EN; #if !AT32_HICK_ENABLED diff --git a/os/hal/ports/AT32/AT32F415/hal_lld.h b/os/hal/ports/AT32/AT32F415/hal_lld.h index d1c8375fb2..3b6b7cc15d 100644 --- a/os/hal/ports/AT32/AT32F415/hal_lld.h +++ b/os/hal/ports/AT32/AT32F415/hal_lld.h @@ -51,32 +51,32 @@ /** * @brief Requires use of SPIv2 driver model. */ -#define HAL_LLD_SELECT_SPI_V2 TRUE +#define HAL_LLD_SELECT_SPI_V2 TRUE /** * @name Platform identification * @{ */ #if defined(__DOXYGEN__) -#define PLATFORM_NAME "AT32F415" +#define PLATFORM_NAME "AT32F415" #elif defined(AT32F415K_MD) -#define PLATFORM_NAME "AT32F415K Value Line Medium Density" +#define PLATFORM_NAME "AT32F415K Value Line Medium Density" #elif defined(AT32F415K_HD) -#define PLATFORM_NAME "AT32F415K Value Line High Density" +#define PLATFORM_NAME "AT32F415K Value Line High Density" #elif defined(AT32F415C_MD) -#define PLATFORM_NAME "AT32F415C Value Line Medium Density" +#define PLATFORM_NAME "AT32F415C Value Line Medium Density" #elif defined(AT32F415C_HD) -#define PLATFORM_NAME "AT32F415C Value Line High Density" +#define PLATFORM_NAME "AT32F415C Value Line High Density" #elif defined(AT32F415R_MD) -#define PLATFORM_NAME "AT32F415R Value Line Medium Density" +#define PLATFORM_NAME "AT32F415R Value Line Medium Density" #elif defined(AT32F415R_HD) -#define PLATFORM_NAME "AT32F415R Value Line High Density" +#define PLATFORM_NAME "AT32F415R Value Line High Density" #else #error "unsupported or unrecognized AT32F415 member" @@ -98,170 +98,174 @@ /** * @brief Maximum system clock frequency. */ -#define AT32_SYSCLK_MAX 150000000 +#define AT32_SYSCLK_MAX 150000000 /** * @brief Maximum HEXT clock frequency. */ -#define AT32_HEXTCLK_MAX 25000000 +#define AT32_HEXTCLK_MAX 25000000 /** * @brief Minimum HEXT clock frequency. */ -#define AT32_HEXTCLK_MIN 4000000 +#define AT32_HEXTCLK_MIN 4000000 /** * @brief Maximum LEXT clock frequency. */ -#define AT32_LEXTCLK_MAX 1000000 +#define AT32_LEXTCLK_MAX 32768 /** * @brief Minimum LEXT clock frequency. */ -#define AT32_LEXTCLK_MIN 32768 +#define AT32_LEXTCLK_MIN 32768 /** * @brief Maximum PLLs input clock frequency. */ -#define AT32_PLLIN_MAX 16000000 +#define AT32_PLLIN_MAX 16000000 /** * @brief Minimum PLLs input clock frequency. */ -#define AT32_PLLIN_MIN 2000000 +#define AT32_PLLIN_MIN 2000000 /** * @brief Maximum PLL output clock frequency. */ -#define AT32_PLLOUT_MAX 150000000 +#define AT32_PLLOUT_MAX 150000000 /** * @brief Minimum PLL output clock frequency. */ -#define AT32_PLLOUT_MIN 4000000 +#define AT32_PLLOUT_MIN 4000000 /** * @brief Maximum PLL FR clock frequency. */ -#define AT32_PLLFR_MAX 1000000000 +#define AT32_PLLFR_MAX 1000000000 /** * @brief Minimum PLL FR clock frequency. */ -#define AT32_PLLFR_MIN 500000000 +#define AT32_PLLFR_MIN 500000000 /** * @brief Maximum APB1 clock frequency. */ -#define AT32_PCLK1_MAX 75000000 +#define AT32_PCLK1_MAX 75000000 /** * @brief Maximum APB2 clock frequency. */ -#define AT32_PCLK2_MAX 75000000 +#define AT32_PCLK2_MAX 75000000 /** * @brief Maximum ADC clock frequency. */ -#define AT32_ADCCLK_MAX 28000000 +#define AT32_ADCCLK_MAX 28000000 /** @} */ /** * @name Internal clock sources * @{ */ -#define AT32_HICKCLK 48000000 /**< High speed internal clock. */ -#define AT32_LICKCLK 40000 /**< Low speed internal clock. */ +#define AT32_HICKCLK 48000000 /**< High speed internal clock. */ +#define AT32_LICKCLK 40000 /**< Low speed internal clock. */ /** @} */ /** * @name PWC_CTRL register bits definitions * @{ */ -#define AT32_PVMSEL_MASK (7 << 5) /**< PVMSEL bits mask. */ -#define AT32_PVMSEL_LEV1 (1 << 5) /**< PVM level 1. */ -#define AT32_PVMSEL_LEV2 (2 << 5) /**< PVM level 2. */ -#define AT32_PVMSEL_LEV3 (3 << 5) /**< PVM level 3. */ -#define AT32_PVMSEL_LEV4 (4 << 5) /**< PVM level 4. */ -#define AT32_PVMSEL_LEV5 (5 << 5) /**< PVM level 5. */ -#define AT32_PVMSEL_LEV6 (6 << 5) /**< PVM level 6. */ -#define AT32_PVMSEL_LEV7 (7 << 5) /**< PVM level 7. */ +#define AT32_PVMSEL_MASK (7 << 5) /**< PVMSEL bits mask. */ +#define AT32_PVMSEL_LEV1 (1 << 5) /**< PVM level 1. */ +#define AT32_PVMSEL_LEV2 (2 << 5) /**< PVM level 2. */ +#define AT32_PVMSEL_LEV3 (3 << 5) /**< PVM level 3. */ +#define AT32_PVMSEL_LEV4 (4 << 5) /**< PVM level 4. */ +#define AT32_PVMSEL_LEV5 (5 << 5) /**< PVM level 5. */ +#define AT32_PVMSEL_LEV6 (6 << 5) /**< PVM level 6. */ +#define AT32_PVMSEL_LEV7 (7 << 5) /**< PVM level 7. */ /** @} */ /** * @name CRM_CFG register bits definitions * @{ */ -#define AT32_SCLKSEL_HICK (0 << 0) /**< SCLK source is HICK. */ -#define AT32_SCLKSEL_HEXT (1 << 0) /**< SCLK source is HEXT. */ -#define AT32_SCLKSEL_PLL (2 << 0) /**< SCLK source is PLL. */ - -#define AT32_SCLKSTS_HICK (0 << 2) /**< SCLK use HICK. */ -#define AT32_SCLKSTS_HEXT (1 << 2) /**< SCLK use HEXT. */ -#define AT32_SCLKSTS_PLL (2 << 2) /**< SCLK use PLL. */ - -#define AT32_AHBDIV_DIV1 (0 << 4) /**< SCLK divided by 1. */ -#define AT32_AHBDIV_DIV2 (8 << 4) /**< SCLK divided by 2. */ -#define AT32_AHBDIV_DIV4 (9 << 4) /**< SCLK divided by 4. */ -#define AT32_AHBDIV_DIV8 (10 << 4) /**< SCLK divided by 8. */ -#define AT32_AHBDIV_DIV16 (11 << 4) /**< SCLK divided by 16. */ -#define AT32_AHBDIV_DIV64 (12 << 4) /**< SCLK divided by 64. */ -#define AT32_AHBDIV_DIV128 (13 << 4) /**< SCLK divided by 128. */ -#define AT32_AHBDIV_DIV256 (14 << 4) /**< SCLK divided by 256. */ -#define AT32_AHBDIV_DIV512 (15 << 4) /**< SCLK divided by 512. */ - -#define AT32_APB1DIV_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define AT32_APB1DIV_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define AT32_APB1DIV_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define AT32_APB1DIV_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define AT32_APB1DIV_DIV16 (7 << 8) /**< HCLK divided by 16. */ - -#define AT32_APB2DIV_DIV1 (0 << 11) /**< HCLK divided by 1. */ -#define AT32_APB2DIV_DIV2 (4 << 11) /**< HCLK divided by 2. */ -#define AT32_APB2DIV_DIV4 (5 << 11) /**< HCLK divided by 4. */ -#define AT32_APB2DIV_DIV8 (6 << 11) /**< HCLK divided by 8. */ -#define AT32_APB2DIV_DIV16 (7 << 11) /**< HCLK divided by 16. */ - -#define AT32_ADCDIV_DIV2 (0 << 14) /**< APB2DIV divided by 2. */ -#define AT32_ADCDIV_DIV4 (1 << 14) /**< APB2DIV divided by 4. */ -#define AT32_ADCDIV_DIV6 (2 << 14) /**< APB2DIV divided by 6. */ -#define AT32_ADCDIV_DIV8 (3 << 14) /**< APB2DIV divided by 8. */ -#define AT32_ADCDIV_DIV12 ((1 << 28) | (1 << 14)) /**< APB2DIV divided by 12. */ -#define AT32_ADCDIV_DIV16 ((1 << 28) | (3 << 14)) /**< APB2DIV divided by 16. */ - -#define AT32_PLLRCS_HICK (0 << 16) /**< PLL clock source is HICK. */ -#define AT32_PLLRCS_HEXT (1 << 16) /**< PLL clock source is HEXT. */ - -#define AT32_PLLHEXTDIV_DIV1 (0 << 17) /**< HEXT divided by 1. */ -#define AT32_PLLHEXTDIV_DIV2 (1 << 17) /**< HEXT divided by 2. */ - -#define AT32_USBDIV_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */ -#define AT32_USBDIV_DIV1 (1 << 22) /**< PLLOUT divided by 1. */ -#define AT32_USBDIV_DIV2P5 (2 << 22) /**< PLLOUT divided by 2.5. */ -#define AT32_USBDIV_DIV2 (3 << 22) /**< PLLOUT divided by 2. */ -#define AT32_USBDIV_DIV3P5 (1 << 27) /**< PLLOUT divided by 3.5. */ -#define AT32_USBDIV_DIV3 ((1 << 27) | (1 << 22)) /**< PLLOUT divided by 3. */ -#define AT32_USBDIV_DIV4 ((1 << 27) | (2 << 22)) /**< PLLOUT divided by 4. */ - -#define AT32_CLKOUT_SEL_CFG_MSK (7 << 24) /**< CLKOUT_SEL pin on CRM_CFG mask. */ -#define AT32_CLKOUT_SEL_NOCLOCK (0 << 24) /**< No clock on CLKOUT_SEL pin. */ -#define AT32_CLKOUT_SEL_LICK (2 << 24) /**< LICK clockon CLKOUT_SEL pin. */ -#define AT32_CLKOUT_SEL_LEXT (3 << 24) /**< LEXT clock on CLKOUT_SEL pin. */ -#define AT32_CLKOUT_SEL_SCLK (4 << 24) /**< SCLK on CLKOUT_SEL pin. */ -#define AT32_CLKOUT_SEL_HICK (5 << 24) /**< HICK clock on CLKOUT_SEL pin. */ -#define AT32_CLKOUT_SEL_HEXT (6 << 24) /**< HEXT clock on CLKOUT_SEL pin. */ -#define AT32_CLKOUT_SEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on CLKOUT_SEL pin. */ +#define AT32_SCLKSEL_HICK (0 << 0) /**< SCLK source is HICK. */ +#define AT32_SCLKSEL_HEXT (1 << 0) /**< SCLK source is HEXT. */ +#define AT32_SCLKSEL_PLL (2 << 0) /**< SCLK source is PLL. */ + +#define AT32_SCLKSTS_HICK (0 << 2) /**< SCLK use HICK. */ +#define AT32_SCLKSTS_HEXT (1 << 2) /**< SCLK use HEXT. */ +#define AT32_SCLKSTS_PLL (2 << 2) /**< SCLK use PLL. */ + +#define AT32_AHBDIV_DIV1 (0 << 4) /**< SCLK divided by 1. */ +#define AT32_AHBDIV_DIV2 (8 << 4) /**< SCLK divided by 2. */ +#define AT32_AHBDIV_DIV4 (9 << 4) /**< SCLK divided by 4. */ +#define AT32_AHBDIV_DIV8 (10 << 4) /**< SCLK divided by 8. */ +#define AT32_AHBDIV_DIV16 (11 << 4) /**< SCLK divided by 16. */ +#define AT32_AHBDIV_DIV64 (12 << 4) /**< SCLK divided by 64. */ +#define AT32_AHBDIV_DIV128 (13 << 4) /**< SCLK divided by 128. */ +#define AT32_AHBDIV_DIV256 (14 << 4) /**< SCLK divided by 256. */ +#define AT32_AHBDIV_DIV512 (15 << 4) /**< SCLK divided by 512. */ + +#define AT32_APB1DIV_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define AT32_APB1DIV_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define AT32_APB1DIV_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define AT32_APB1DIV_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define AT32_APB1DIV_DIV16 (7 << 8) /**< HCLK divided by 16. */ + +#define AT32_APB2DIV_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define AT32_APB2DIV_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define AT32_APB2DIV_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define AT32_APB2DIV_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define AT32_APB2DIV_DIV16 (7 << 11) /**< HCLK divided by 16. */ + +#define AT32_ADCDIV_DIV2 (0 << 14) /**< APB2DIV divided by 2. */ +#define AT32_ADCDIV_DIV4 (1 << 14) /**< APB2DIV divided by 4. */ +#define AT32_ADCDIV_DIV6 (2 << 14) /**< APB2DIV divided by 6. */ +#define AT32_ADCDIV_DIV8 (3 << 14) /**< APB2DIV divided by 8. */ +#define AT32_ADCDIV_DIV12 ((1 << 28) | (1 << 14)) + /**< APB2DIV divided by 12. */ +#define AT32_ADCDIV_DIV16 ((1 << 28) | (3 << 14)) + /**< APB2DIV divided by 16. */ + +#define AT32_PLLRCS_HICK (0 << 16) /**< PLL clock source is HICK. */ +#define AT32_PLLRCS_HEXT (1 << 16) /**< PLL clock source is HEXT. */ + +#define AT32_PLLHEXTDIV_DIV1 (0 << 17) /**< HEXT divided by 1. */ +#define AT32_PLLHEXTDIV_DIV2 (1 << 17) /**< HEXT divided by 2. */ + +#define AT32_USBDIV_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */ +#define AT32_USBDIV_DIV1 (1 << 22) /**< PLLOUT divided by 1. */ +#define AT32_USBDIV_DIV2P5 (2 << 22) /**< PLLOUT divided by 2.5. */ +#define AT32_USBDIV_DIV2 (3 << 22) /**< PLLOUT divided by 2. */ +#define AT32_USBDIV_DIV3P5 (1 << 27) /**< PLLOUT divided by 3.5. */ +#define AT32_USBDIV_DIV3 ((1 << 27) | (1 << 22)) + /**< PLLOUT divided by 3. */ +#define AT32_USBDIV_DIV4 ((1 << 27) | (2 << 22)) + /**< PLLOUT divided by 4. */ + +#define AT32_CLKOUT_SEL_CFG_MASK (7 << 24) /**< CLKOUT_SEL pin on CRM_CFG mask. */ +#define AT32_CLKOUT_SEL_NOCLOCK (0 << 24) /**< No clock on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_LICK (2 << 24) /**< LICK clockon CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_LEXT (3 << 24) /**< LEXT clock on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_SCLK (4 << 24) /**< SCLK on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_HICK (5 << 24) /**< HICK clock on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_HEXT (6 << 24) /**< HEXT clock on CLKOUT_SEL pin. */ +#define AT32_CLKOUT_SEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on CLKOUT_SEL pin. */ /** @} */ /** * @name CRM_BPDC register bits definitions * @{ */ -#define AT32_ERTCSEL_MASK (3 << 8) /**< ERTC clock source mask. */ -#define AT32_ERTCSEL_NOCLOCK (0 << 8) /**< No clock. */ -#define AT32_ERTCSEL_LEXT (1 << 8) /**< LEXT used as ERTC clock. */ -#define AT32_ERTCSEL_LICK (2 << 8) /**< LICK used as ERTC clock. */ -#define AT32_ERTCSEL_HEXTDIV (3 << 8) /**< HEXT divided by 128 used as +#define AT32_ERTCSEL_MASK (3 << 8) /**< ERTC clock source mask. */ +#define AT32_ERTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define AT32_ERTCSEL_LEXT (1 << 8) /**< LEXT used as ERTC clock. */ +#define AT32_ERTCSEL_LICK (2 << 8) /**< LICK used as ERTC clock. */ +#define AT32_ERTCSEL_HEXTDIV (3 << 8) /**< HEXT divided by 128 used as ERTC clock. */ /** @} */ @@ -269,33 +273,38 @@ * @name CRM_PLL register bits definitions * @{ */ -#define AT32_PLL_FR_MASK (7 << 0) /**< PLL FR mask. */ -#define AT32_PLL_FR_DIV1 (0 << 0) /**< PLL divided by 1. */ -#define AT32_PLL_FR_DIV2 (1 << 0) /**< PLL divided by 2. */ -#define AT32_PLL_FR_DIV4 (2 << 0) /**< PLL divided by 4. */ -#define AT32_PLL_FR_DIV8 (3 << 0) /**< PLL divided by 8. */ -#define AT32_PLL_FR_DIV16 (4 << 0) /**< PLL divided by 16. */ -#define AT32_PLL_FR_DIV32 (5 << 0) /**< PLL divided by 32. */ +#define AT32_PLL_FR_DIV1 (0 << 0) /**< PLL divided by 1. */ +#define AT32_PLL_FR_DIV2 (1 << 0) /**< PLL divided by 2. */ +#define AT32_PLL_FR_DIV4 (2 << 0) /**< PLL divided by 4. */ +#define AT32_PLL_FR_DIV8 (3 << 0) /**< PLL divided by 8. */ +#define AT32_PLL_FR_DIV16 (4 << 0) /**< PLL divided by 16. */ +#define AT32_PLL_FR_DIV32 (5 << 0) /**< PLL divided by 32. */ -#define AT32_PLLCFGEN_SOLID (0 << 31) /**< PLL use solid config. */ -#define AT32_PLLCFGEN_FLEX (1 << 31) /**< PLL use flexible config. */ +#define AT32_PLLCFGEN_SOLID (0 << 31) /**< PLL use solid config. */ +#define AT32_PLLCFGEN_FLEX (1 << 31) /**< PLL use flexible config. */ /** * @name CRM_MISC1 Additional Register * @{ */ -#define AT32_CLKOUT_SEL_MISC_MSK (1 << 27) /**< CLKOUT_SEL pin on CRM_MISC1 mask. */ -#define AT32_CLKOUT_SEL_PLLDIV4 ((1 << 16) | (AT32_CLKOUT_SEL_SCLK)) +#define AT32_CLKOUT_SEL_MISC1_MASK (1 << 27) /**< CLKOUT_SEL pin on CRM_MISC1 mask. */ +#define AT32_CLKOUT_SEL_PLLDIV4 ((1 << 16) | (AT32_CLKOUT_SEL_SCLK)) /**< PLL/4 clock on CLKOUT_SEL pin. */ -#define AT32_CLKOUT_SEL_USB ((1 << 16) | (AT32_CLKOUT_SEL_HICK)) +#define AT32_CLKOUT_SEL_USB ((1 << 16) | (AT32_CLKOUT_SEL_HICK)) /**< USB clock on CLKOUT_SEL pin. */ -#define AT32_CLKOUT_SEL_ADC ((1 << 16) | (AT32_CLKOUT_SEL_HEXT)) +#define AT32_CLKOUT_SEL_ADC ((1 << 16) | (AT32_CLKOUT_SEL_HEXT)) /**< ADC clock on CLKOUT_SEL pin. */ -/** @} */ -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ +#define AT32_CLKOUTDIV_DIV1 (0 << 28) /**< CLKOUT divided by 1. */ +#define AT32_CLKOUTDIV_DIV2 (8 << 28) /**< CLKOUT divided by 2. */ +#define AT32_CLKOUTDIV_DIV4 (9 << 28) /**< CLKOUT divided by 4. */ +#define AT32_CLKOUTDIV_DIV8 (10 << 28) /**< CLKOUT divided by 8. */ +#define AT32_CLKOUTDIV_DIV16 (11 << 28) /**< CLKOUT divided by 16. */ +#define AT32_CLKOUTDIV_DIV64 (12 << 28) /**< CLKOUT divided by 64. */ +#define AT32_CLKOUTDIV_DIV128 (13 << 28) /**< CLKOUT divided by 128. */ +#define AT32_CLKOUTDIV_DIV256 (14 << 28) /**< CLKOUT divided by 256. */ +#define AT32_CLKOUTDIV_DIV512 (15 << 28) /**< CLKOUT divided by 512. */ +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -408,7 +417,7 @@ * @brief PLL FR divider value. * @note The allowed values are 1, 2, 4, 8, 16, 32. * @note The default value is calculated for a 144MHz system clock from - * an external 8MHz HEXT clock. + * a 8MHz crystal using the PLL. */ #if !defined(AT32_PLL_FR_VALUE) || defined(__DOXYGEN__) #define AT32_PLL_FR_VALUE 4 @@ -418,7 +427,7 @@ * @brief PLL MS divider value. * @note The allowed values are 1..15. * @note The default value is calculated for a 144MHz system clock from - * an external 8MHz HEXT clock. + * a 8MHz crystal using the PLL. */ #if !defined(AT32_PLL_MS_VALUE) || defined(__DOXYGEN__) #define AT32_PLL_MS_VALUE 1 @@ -428,7 +437,7 @@ * @brief PLL NS multiplier value. * @note The allowed values are 31..500. * @note The default value is calculated for a 144MHz system clock from - * an external 8MHz HEXT clock. + * a 8MHz crystal using the PLL. */ #if !defined(AT32_PLL_NS_VALUE) || defined(__DOXYGEN__) #define AT32_PLL_NS_VALUE 72 @@ -480,11 +489,19 @@ /** * @brief CLKOUT_SEL pin setting. + * @note The default value outputs no clock on CLKOUT_SEL pin. */ #if !defined(AT32_CLKOUT_SEL) || defined(__DOXYGEN__) #define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK #endif +/** + * @brief CLKOUT_SEL prescaler value. + */ +#if !defined(AT32_CLKOUTDIV) || defined(__DOXYGEN__) +#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 +#endif + /** * @brief ERTC clock source. */ @@ -504,6 +521,17 @@ #error "Using a wrong mcuconf.h file, AT32F415_MCUCONF not defined" #endif +/* + * Board files sanity checks. + */ +#if !defined(AT32_LEXTCLK) +#error "AT32_LEXTCLK not defined in board.h" +#endif + +#if !defined(AT32_HEXTCLK) +#error "AT32_HEXTCLK not defined in board.h" +#endif + /* * HICK related checks. */ @@ -514,7 +542,7 @@ #error "HICK not enabled, required by AT32_SCLKSEL" #endif -#if (AT32_SCLKSEL == AT32_SCLKSEL_PLL) && (AT32_PLLRCS == AT32_PLLRCS_HICK) +#if ((AT32_SCLKSEL == AT32_SCLKSEL_PLL) && (AT32_PLLRCS == AT32_PLLRCS_HICK)) #error "HICK not enabled, required by AT32_SCLKSEL and AT32_PLLRCS" #endif @@ -544,7 +572,7 @@ #error "HEXT not enabled, required by AT32_SCLKSEL" #endif -#if (AT32_SCLKSEL == AT32_SCLKSEL_PLL) && (AT32_PLLRCS == AT32_PLLRCS_HEXT) +#if ((AT32_SCLKSEL == AT32_SCLKSEL_PLL) && (AT32_PLLRCS == AT32_PLLRCS_HEXT)) #error "HEXT not enabled, required by AT32_SCLKSEL and AT32_PLLRCS" #endif @@ -555,7 +583,7 @@ #error "HEXT not enabled, required by AT32_CLKOUT_SEL" #endif -#if (AT32_ERTCSEL == AT32_ERTCSEL_HEXTDIV) +#if AT32_ERTCSEL == AT32_ERTCSEL_HEXTDIV #error "HEXT not enabled, required by AT32_ERTCSEL" #endif #endif /* !AT32_HEXT_ENABLED */ @@ -566,7 +594,7 @@ #if AT32_LICK_ENABLED #else /* !AT32_LICK_ENABLED */ -#if (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_LICK) +#if AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_LICK #error "LICK not enabled, required by AT32_CLKOUT_SEL" #endif @@ -582,15 +610,13 @@ #if (AT32_LEXTCLK == 0) #error "LEXT frequency not defined" -#endif - -#if (AT32_LEXTCLK < AT32_LEXTCLK_MIN) || (AT32_LEXTCLK > AT32_LEXTCLK_MAX) +#elif (AT32_LEXTCLK < AT32_LEXTCLK_MIN) || (AT32_LEXTCLK > AT32_LEXTCLK_MAX) #error "AT32_LEXTCLK outside acceptable range (AT32_LEXTCLK_MIN...AT32_LEXTCLK_MAX)" #endif #else /* !AT32_LEXT_ENABLED */ -#if (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_LEXT) +#if AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_LEXT #error "LEXT not enabled, required by AT32_CLKOUT_SEL" #endif @@ -641,7 +667,7 @@ * @brief PLL input clock frequency. */ #if (AT32_PLLRCS == AT32_PLLRCS_HEXT) || defined(__DOXYGEN__) -#if AT32_PLLHEXTDIV == AT32_PLLHEXTDIV_DIV1 || defined(__DOXYGEN__) +#if (AT32_PLLHEXTDIV == AT32_PLLHEXTDIV_DIV1) || defined(__DOXYGEN__) #define AT32_PLLRCSCLK (AT32_HEXTCLK / 1) #else #define AT32_PLLRCSCLK (AT32_HEXTCLK / 2) @@ -697,7 +723,7 @@ #if (AT32_PLLCFGEN == AT32_PLLCFGEN_SOLID) || defined(__DOXYGEN__) #define AT32_PLLCLKIN AT32_PLLRCSCLK #define AT32_PLLCLKOUT (AT32_PLLCLKIN * AT32_PLLMULT_VALUE) -#elif (AT32_PLLCFGEN == AT32_PLLCFGEN_FLEX) +#elif AT32_PLLCFGEN == AT32_PLLCFGEN_FLEX #define AT32_PLLCLKIN (AT32_PLLRCSCLK / AT32_PLL_MS_VALUE) #define AT32_PLLFRCLK (AT32_PLLCLKIN * AT32_PLL_NS_VALUE) #define AT32_PLLCLKOUT (AT32_PLLFRCLK / AT32_PLL_FR_VALUE) @@ -742,9 +768,9 @@ */ #if (AT32_SCLKSEL == AT32_SCLKSEL_PLL) || defined(__DOXYGEN__) #define AT32_SYSCLK AT32_PLLCLKOUT -#elif (AT32_SCLKSEL == AT32_SCLKSEL_HICK) +#elif AT32_SCLKSEL == AT32_SCLKSEL_HICK #define AT32_SYSCLK AT32_HICKCLK -#elif (AT32_SCLKSEL == AT32_SCLKSEL_HEXT) +#elif AT32_SCLKSEL == AT32_SCLKSEL_HEXT #define AT32_SYSCLK AT32_HEXTCLK #else #error "invalid AT32_SCLKSEL value specified" @@ -873,17 +899,17 @@ */ #if (AT32_USBDIV == AT32_USBDIV_DIV1P5) || defined(__DOXYGEN__) #define AT32_USBCLK ((AT32_PLLCLKOUT * 2) / 3) -#elif (AT32_USBDIV == AT32_USBDIV_DIV1) +#elif AT32_USBDIV == AT32_USBDIV_DIV1 #define AT32_USBCLK AT32_PLLCLKOUT -#elif (AT32_USBDIV == AT32_USBDIV_DIV2P5) +#elif AT32_USBDIV == AT32_USBDIV_DIV2P5 #define AT32_USBCLK ((AT32_PLLCLKOUT * 2) / 5) -#elif (AT32_USBDIV == AT32_USBDIV_DIV2) +#elif AT32_USBDIV == AT32_USBDIV_DIV2 #define AT32_USBCLK (AT32_PLLCLKOUT / 2) -#elif (AT32_USBDIV == AT32_USBDIV_DIV3P5) +#elif AT32_USBDIV == AT32_USBDIV_DIV3P5 #define AT32_USBCLK ((AT32_PLLCLKOUT * 2) / 7) -#elif (AT32_USBDIV == AT32_USBDIV_DIV3) +#elif AT32_USBDIV == AT32_USBDIV_DIV3 #define AT32_USBCLK (AT32_PLLCLKOUT / 3) -#elif (AT32_USBDIV == AT32_USBDIV_DIV4) +#elif AT32_USBDIV == AT32_USBDIV_DIV4 #define AT32_USBCLK (AT32_PLLCLKOUT / 4) #else #error "invalid AT32_USBDIV value specified" @@ -911,15 +937,15 @@ * @brief Flash settings. */ #if (AT32_HCLK <= 32000000) || defined(__DOXYGEN__) -#define AT32_FLASHBITS 0x00000010 +#define AT32_FLASHBITS 0x00000010 #elif (AT32_HCLK <= 64000000) -#define AT32_FLASHBITS 0x00000011 +#define AT32_FLASHBITS 0x00000011 #elif (AT32_HCLK <= 96000000) -#define AT32_FLASHBITS 0x00000012 +#define AT32_FLASHBITS 0x00000012 #elif (AT32_HCLK <= 128000000) -#define AT32_FLASHBITS 0x00000013 +#define AT32_FLASHBITS 0x00000013 #elif (AT32_HCLK <= 150000000) -#define AT32_FLASHBITS 0x00000014 +#define AT32_FLASHBITS 0x00000014 #endif /*===========================================================================*/ From e234b6981848c1d69dfbfaaea76b74120216525c Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Wed, 3 Jul 2024 10:52:05 +0700 Subject: [PATCH 03/18] Update board file, added new demo and HAL test --- demos/AT32/.keep | 0 .../AT32/RT-AT-START-F415}/.cproject | 34 ++-- demos/AT32/RT-AT-START-F415/.project | 78 ++++++++++ .../AT32/RT-AT-START-F415}/Makefile | 82 +++------- .../AT32/RT-AT-START-F415}/cfg/chconf.h | 35 ++++- .../AT32/RT-AT-START-F415}/cfg/halconf.h | 6 +- .../AT32/RT-AT-START-F415}/cfg/mcuconf.h | 14 +- demos/AT32/RT-AT-START-F415/main.c | 85 ++++++++++ os/hal/boards/AT_START_F415/board.h | 60 ++++++-- testhal/AT32/AT32F415/PWM-ICU/.project | 33 ---- testhal/AT32/AT32F415/PWM-ICU/main.c | 145 ------------------ testhal/AT32/AT32F415/PWM-ICU/readme.txt | 28 ---- testhal/AT32/AT32F415/USB_CDC/.project | 49 ------ testhal/AT32/AT32F415/USB_CDC/readme.txt | 26 ---- .../PWM-ICU => multi/USB_CDC}/.cproject | 39 +++-- testhal/AT32/multi/USB_CDC/.project | 78 ++++++++++ testhal/AT32/multi/USB_CDC/Makefile | 18 +++ .../USB_CDC/cfg/at-start-f415}/chconf.h | 35 ++++- .../USB_CDC/cfg/at-start-f415}/halconf.h | 0 .../USB_CDC/cfg/at-start-f415}/mcuconf.h | 8 +- .../multi/USB_CDC/cfg/at-start-f415/portab.c | 59 +++++++ .../multi/USB_CDC/cfg/at-start-f415/portab.h | 78 ++++++++++ .../AT32/{AT32F415 => multi}/USB_CDC/main.c | 43 ++++-- .../USB_CDC/make/at-start-f415.make} | 93 +++-------- .../USB_CDC => multi/USB_CDC/source}/usbcfg.c | 37 ++--- .../USB_CDC => multi/USB_CDC/source}/usbcfg.h | 2 +- 26 files changed, 650 insertions(+), 515 deletions(-) delete mode 100644 demos/AT32/.keep rename {testhal/AT32/AT32F415/USB_CDC => demos/AT32/RT-AT-START-F415}/.cproject (62%) create mode 100644 demos/AT32/RT-AT-START-F415/.project rename {testhal/AT32/AT32F415/USB_CDC => demos/AT32/RT-AT-START-F415}/Makefile (69%) rename {testhal/AT32/AT32F415/PWM-ICU => demos/AT32/RT-AT-START-F415}/cfg/chconf.h (96%) rename {testhal/AT32/AT32F415/PWM-ICU => demos/AT32/RT-AT-START-F415}/cfg/halconf.h (99%) rename {testhal/AT32/AT32F415/PWM-ICU => demos/AT32/RT-AT-START-F415}/cfg/mcuconf.h (96%) create mode 100644 demos/AT32/RT-AT-START-F415/main.c delete mode 100644 testhal/AT32/AT32F415/PWM-ICU/.project delete mode 100644 testhal/AT32/AT32F415/PWM-ICU/main.c delete mode 100644 testhal/AT32/AT32F415/PWM-ICU/readme.txt delete mode 100644 testhal/AT32/AT32F415/USB_CDC/.project delete mode 100644 testhal/AT32/AT32F415/USB_CDC/readme.txt rename testhal/AT32/{AT32F415/PWM-ICU => multi/USB_CDC}/.cproject (56%) create mode 100644 testhal/AT32/multi/USB_CDC/.project create mode 100644 testhal/AT32/multi/USB_CDC/Makefile rename testhal/AT32/{AT32F415/USB_CDC/cfg => multi/USB_CDC/cfg/at-start-f415}/chconf.h (96%) rename testhal/AT32/{AT32F415/USB_CDC/cfg => multi/USB_CDC/cfg/at-start-f415}/halconf.h (100%) rename testhal/AT32/{AT32F415/USB_CDC/cfg => multi/USB_CDC/cfg/at-start-f415}/mcuconf.h (98%) create mode 100644 testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.c create mode 100644 testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.h rename testhal/AT32/{AT32F415 => multi}/USB_CDC/main.c (82%) rename testhal/AT32/{AT32F415/PWM-ICU/Makefile => multi/USB_CDC/make/at-start-f415.make} (67%) rename testhal/AT32/{AT32F415/USB_CDC => multi/USB_CDC/source}/usbcfg.c (93%) rename testhal/AT32/{AT32F415/USB_CDC => multi/USB_CDC/source}/usbcfg.h (95%) diff --git a/demos/AT32/.keep b/demos/AT32/.keep deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/testhal/AT32/AT32F415/USB_CDC/.cproject b/demos/AT32/RT-AT-START-F415/.cproject similarity index 62% rename from testhal/AT32/AT32F415/USB_CDC/.cproject rename to demos/AT32/RT-AT-START-F415/.cproject index 7e9524dabe..74701160a0 100644 --- a/testhal/AT32/AT32F415/USB_CDC/.cproject +++ b/demos/AT32/RT-AT-START-F415/.cproject @@ -1,8 +1,8 @@ - - + + @@ -14,20 +14,20 @@ - - - - - - - - + + + + + + + + - - + + - - + + @@ -37,18 +37,18 @@ - + - + - + diff --git a/demos/AT32/RT-AT-START-F415/.project b/demos/AT32/RT-AT-START-F415/.project new file mode 100644 index 0000000000..6229eed12e --- /dev/null +++ b/demos/AT32/RT-AT-START-F415/.project @@ -0,0 +1,78 @@ + + + RT-AT-START-F415 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/testhal/AT32/AT32F415/USB_CDC/Makefile b/demos/AT32/RT-AT-START-F415/Makefile similarity index 69% rename from testhal/AT32/AT32F415/USB_CDC/Makefile rename to demos/AT32/RT-AT-START-F415/Makefile index cd0e85a6dd..9ca5d645d7 100644 --- a/testhal/AT32/AT32F415/USB_CDC/Makefile +++ b/demos/AT32/RT-AT-START-F415/Makefile @@ -33,11 +33,6 @@ ifeq ($(USE_LTO),) USE_LTO = yes endif -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - # Enable this if you want to see the full log while compiling. ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no @@ -74,6 +69,11 @@ ifeq ($(USE_FPU),) USE_FPU = no endif +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + # # Architecture or project specific options ############################################################################## @@ -85,9 +85,12 @@ endif # Define project name here PROJECT = ch +# Target settings. +MCU = cortex-m4 + # Imported source files and paths. -CHIBIOS := ../../../../../ChibiOS -CHIBIOS_CONTRIB := ../../../../ +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB := ../../.. CONFDIR := ./cfg BUILDDIR := ./build DEPDIR := ./.dep @@ -104,6 +107,8 @@ include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk # Other files (optional). include $(CHIBIOS)/os/test/test.mk include $(CHIBIOS)/test/rt/rt_test.mk @@ -111,80 +116,28 @@ include $(CHIBIOS)/test/oslib/oslib_test.mk include $(CHIBIOS)/os/hal/lib/streams/streams.mk include $(CHIBIOS)/os/various/shell/shell.mk -# Define linker script file here +# Define linker script file here. LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = $(ALLCSRC) \ $(TESTSRC) \ - usbcfg.c main.c + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. CPPSRC = $(ALLCPPSRC) -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - # List ASM source files here. ASMSRC = $(ALLASMSRC) + # List ASM with preprocessor source files here. ASMXSRC = $(ALLXASMSRC) # Inclusion directories. INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - # Define C warning options here. CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes @@ -192,7 +145,7 @@ CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes CPPWARN = -Wall -Wextra -Wundef # -# Compiler settings +# Project, target, sources and paths ############################################################################## ############################################################################## @@ -215,7 +168,7 @@ ULIBDIR = ULIBS = # -# End of user defines +# End of user section ############################################################################## ############################################################################## @@ -223,6 +176,7 @@ ULIBS = # RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk include $(RULESPATH)/rules.mk # diff --git a/testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h b/demos/AT32/RT-AT-START-F415/cfg/chconf.h similarity index 96% rename from testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h rename to demos/AT32/RT-AT-START-F415/cfg/chconf.h index 6ae2a5be1b..42828da814 100644 --- a/testhal/AT32/AT32F415/PWM-ICU/cfg/chconf.h +++ b/demos/AT32/RT-AT-START-F415/cfg/chconf.h @@ -141,6 +141,19 @@ #define CH_CFG_NO_IDLE_THREAD FALSE #endif +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + /** @} */ /*===========================================================================*/ @@ -362,6 +375,16 @@ #define CH_CFG_USE_MAILBOXES TRUE #endif +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + /** * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included @@ -565,7 +588,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#define CH_DBG_SYSTEM_STATE_CHECK FALSE #endif /** @@ -576,7 +599,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE +#define CH_DBG_ENABLE_CHECKS FALSE #endif /** @@ -588,7 +611,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** @@ -598,7 +621,7 @@ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. */ #if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED #endif /** @@ -621,7 +644,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE +#define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** @@ -633,7 +656,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h b/demos/AT32/RT-AT-START-F415/cfg/halconf.h similarity index 99% rename from testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h rename to demos/AT32/RT-AT-START-F415/cfg/halconf.h index 099dca49da..379afbbea6 100644 --- a/testhal/AT32/AT32F415/PWM-ICU/cfg/halconf.h +++ b/demos/AT32/RT-AT-START-F415/cfg/halconf.h @@ -102,7 +102,7 @@ * @brief Enables the ICU subsystem. */ #if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU TRUE +#define HAL_USE_ICU FALSE #endif /** @@ -123,7 +123,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM TRUE +#define HAL_USE_PWM FALSE #endif /** @@ -144,7 +144,7 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL FALSE +#define HAL_USE_SERIAL TRUE #endif /** diff --git a/testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h b/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h similarity index 96% rename from testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h rename to demos/AT32/RT-AT-START-F415/cfg/mcuconf.h index a8222ec634..8b6899806d 100644 --- a/testhal/AT32/AT32F415/PWM-ICU/cfg/mcuconf.h +++ b/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio ChibiOS - Copyright (C) 2023..2024 HorrorTroll ChibiOS - Copyright (C) 2023..2024 Zhaqian @@ -19,8 +19,6 @@ #ifndef MCUCONF_H #define MCUCONF_H -#define AT32F415_MCUCONF - /* * AT32F415 drivers configuration. * The following settings override the default settings present in @@ -35,6 +33,8 @@ * 0...3 Lowest...Highest. */ +#define AT32F415_MCUCONF + /* * HAL driver system settings. */ @@ -58,6 +58,7 @@ #define AT32_USB_CLOCK_REQUIRED TRUE #define AT32_USBDIV AT32_USBDIV_DIV3 #define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 #define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV #define AT32_PVM_ENABLE FALSE #define AT32_PVMSEL AT32_PVMSEL_LEV1 @@ -143,7 +144,7 @@ #define AT32_ICU_USE_TMR1 FALSE #define AT32_ICU_USE_TMR2 FALSE #define AT32_ICU_USE_TMR3 FALSE -#define AT32_ICU_USE_TMR4 TRUE +#define AT32_ICU_USE_TMR4 FALSE #define AT32_ICU_USE_TMR5 FALSE #define AT32_ICU_USE_TMR9 FALSE #define AT32_ICU_USE_TMR10 FALSE @@ -152,7 +153,7 @@ /* * PWM driver system settings. */ -#define AT32_PWM_USE_TMR1 TRUE +#define AT32_PWM_USE_TMR1 FALSE #define AT32_PWM_USE_TMR2 FALSE #define AT32_PWM_USE_TMR3 FALSE #define AT32_PWM_USE_TMR4 FALSE @@ -172,7 +173,7 @@ /* * SERIAL driver system settings. */ -#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART1 TRUE #define AT32_SERIAL_USE_USART2 FALSE #define AT32_SERIAL_USE_USART3 FALSE #define AT32_SERIAL_USE_UART4 FALSE @@ -212,7 +213,6 @@ #define AT32_USB_USE_OTG1 FALSE #define AT32_USB_OTG1_IRQ_PRIORITY 14 #define AT32_USB_OTG1_RX_FIFO_SIZE 512 -#define AT32_USB_HOST_WAKEUP_DURATION 2 /* * WDG driver system settings. diff --git a/demos/AT32/RT-AT-START-F415/main.c b/demos/AT32/RT-AT-START-F415/main.c new file mode 100644 index 0000000000..fc991eb7a8 --- /dev/null +++ b/demos/AT32/RT-AT-START-F415/main.c @@ -0,0 +1,85 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "rt_test_root.h" +#include "oslib_test_root.h" + +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + palSetLine(LINE_LED_RED); + chThdSleepMilliseconds(250); + palSetLine(LINE_LED_YELLOW); + chThdSleepMilliseconds(250); + palSetLine(LINE_LED_GREEN); + chThdSleepMilliseconds(250); + palClearLine(LINE_LED_RED); + chThdSleepMilliseconds(250); + palClearLine(LINE_LED_YELLOW); + chThdSleepMilliseconds(250); + palClearLine(LINE_LED_GREEN); + chThdSleepMilliseconds(250); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + if (palReadLine(LINE_BUTTON)) { + test_execute((BaseSequentialStream *)&SD1, &rt_test_suite); + test_execute((BaseSequentialStream *)&SD1, &oslib_test_suite); + } + chThdSleepMilliseconds(500); + } +} diff --git a/os/hal/boards/AT_START_F415/board.h b/os/hal/boards/AT_START_F415/board.h index 61b0c75a3f..7eecf54707 100644 --- a/os/hal/boards/AT_START_F415/board.h +++ b/os/hal/boards/AT_START_F415/board.h @@ -112,6 +112,47 @@ #define GPIOF_PIN6 6U #define GPIOF_PIN7 7U +/* + * IO lines assignments. + */ +#define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) +#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U) +#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U) +#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U) +#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_ARD_D10 PAL_LINE(GPIOA, 15U) +#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) +#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) +#define LINE_ARD_SCL PAL_LINE(GPIOB, 8U) +#define LINE_ARD_SDA PAL_LINE(GPIOB, 9U) +#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) +#define LINE_ARD_PB11 PAL_LINE(GPIOB, 11U) +#define LINE_ARD_NSS PAL_LINE(GPIOB, 12U) +#define LINE_ARD_SCK PAL_LINE(GPIOB, 13U) +#define LINE_ARD_MISO PAL_LINE(GPIOB, 14U) +#define LINE_ARD_MOSI PAL_LINE(GPIOB, 15U) +#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) +#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) +#define LINE_LED_RED PAL_LINE(GPIOC, 2U) +#define LINE_LED_YELLOW PAL_LINE(GPIOC, 3U) +#define LINE_LED_GREEN PAL_LINE(GPIOC, 5U) +#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) +#define LINE_BUTTON_ALT PAL_LINE(GPIOC, 13U) +#define LINE_LEXT_IN PAL_LINE(GPIOC, 14U) +#define LINE_LEXT_OUT PAL_LINE(GPIOC, 15U) +#define LINE_HEXT_IN PAL_LINE(GPIOD, 0U) +#define LINE_HEXT_OUT PAL_LINE(GPIOD, 1U) + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -155,13 +196,12 @@ /* * Port A setup. * Everything input with pull-up except: - * PA0 - Normal input (GPIOA_BUTTON) - * PA2 - Alternate output (GPIOA_ARD_D1) - * PA3 - Normal input (GPIOA_ARD_D0) - * PA14 - Pull-down input (GPIOA_SWCLK) + * PA0 - Normal input (GPIOA_BUTTON). + * PA9 - Alternate output (GPIOA_ARD_D8). + * PA10 - Normal input (GPIOA_ARD_D2). */ -#define VAL_GPIOACFGLR 0x88884B84 /* PA7...PA0 */ -#define VAL_GPIOACFGHR 0x88888888 /* PA15...PA8 */ +#define VAL_GPIOACFGLR 0x88888884 /* PA7...PA0 */ +#define VAL_GPIOACFGHR 0x888884B8 /* PA15...PA8 */ #define VAL_GPIOAODT 0xFFFFFFFF /* @@ -174,10 +214,10 @@ /* * Port C setup. * Everything input with pull-up except: - * PC2 - Push Pull output (GPIOC_LED_RED) - * PC3 - Push Pull output (GPIOC_LED_YELLOW) - * PC5 - Push Pull output (GPIOC_LED_GREEN) - * PC13 - Normal input (GPIOC_BUTTON) + * PC2 - Push Pull output (GPIOC_LED_RED). + * PC3 - Push Pull output (GPIOC_LED_YELLOW). + * PC5 - Push Pull output (GPIOC_LED_GREEN). + * PC13 - Normal input (GPIOC_BUTTON). */ #define VAL_GPIOCCFGLR 0x88383388 /* PC7...PC0 */ #define VAL_GPIOCCFGHR 0x88488888 /* PC15...PC8 */ diff --git a/testhal/AT32/AT32F415/PWM-ICU/.project b/testhal/AT32/AT32F415/PWM-ICU/.project deleted file mode 100644 index a94f918b02..0000000000 --- a/testhal/AT32/AT32F415/PWM-ICU/.project +++ /dev/null @@ -1,33 +0,0 @@ - - - AT32F415-PWM-ICU - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - os - 2 - CHIBIOS/os - - - diff --git a/testhal/AT32/AT32F415/PWM-ICU/main.c b/testhal/AT32/AT32F415/PWM-ICU/main.c deleted file mode 100644 index 4f22f79cec..0000000000 --- a/testhal/AT32/AT32F415/PWM-ICU/main.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "ch.h" -#include "hal.h" - -static void pwmpcb(PWMDriver *pwmp) { - - (void)pwmp; - palSetPad(IOPORT3, GPIOC_LED_GREEN); -} - -static void pwmc1cb(PWMDriver *pwmp) { - - (void)pwmp; - palClearPad(IOPORT3, GPIOC_LED_GREEN); -} - -static PWMConfig pwmcfg = { - 10000, /* 10kHz PWM clock frequency. */ - 10000, /* Initial PWM period 1S. */ - pwmpcb, - { - {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL} - }, - 0, - 0, - 0 -}; - -icucnt_t last_width, last_period; - -static void icuwidthcb(ICUDriver *icup) { - - last_width = icuGetWidthX(icup); -} - -static void icuperiodcb(ICUDriver *icup) { - - last_period = icuGetPeriodX(icup); -} - -static ICUConfig icucfg = { - ICU_INPUT_ACTIVE_HIGH, - 10000, /* 10kHz ICU clock frequency. */ - icuwidthcb, - icuperiodcb, - NULL, - ICU_CHANNEL_1, - 0U, - 0xFFFFFFFFU -}; - -/* - * Application entry point. - */ -int main(void) { - - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - - /* - * LED initially off. - */ - palSetPad(IOPORT3, GPIOC_LED_GREEN); - - /* - * Initializes the PWM driver 1 and ICU driver 4. - */ - pwmStart(&PWMD1, &pwmcfg); - pwmEnablePeriodicNotification(&PWMD1); - palSetPadMode(IOPORT1, 8, PAL_MODE_AT32_ALTERNATE_PUSHPULL); - icuStart(&ICUD4, &icucfg); - icuStartCapture(&ICUD4); - icuEnableNotifications(&ICUD4); - chThdSleepMilliseconds(2000); - - /* - * Starts the PWM channel 0 using 75% duty cycle. - */ - pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500)); - pwmEnableChannelNotification(&PWMD1, 0); - chThdSleepMilliseconds(5000); - - /* - * Changes the PWM channel 0 to 50% duty cycle. - */ - pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); - chThdSleepMilliseconds(5000); - - /* - * Changes the PWM channel 0 to 25% duty cycle. - */ - pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500)); - chThdSleepMilliseconds(5000); - - /* - * Changes PWM period to half second the duty cycle becomes 50% - * implicitly. - */ - pwmChangePeriod(&PWMD1, 5000); - chThdSleepMilliseconds(5000); - - /* - * Disables channel 0 and stops the drivers. - */ - pwmDisableChannel(&PWMD1, 0); - pwmStop(&PWMD1); - icuStopCapture(&ICUD4); - icuStop(&ICUD4); - palSetPad(IOPORT3, GPIOC_LED_GREEN); - - /* - * Normal main() thread activity, in this demo it does nothing. - */ - while (true) { - chThdSleepMilliseconds(500); - } - return 0; -} diff --git a/testhal/AT32/AT32F415/PWM-ICU/readme.txt b/testhal/AT32/AT32F415/PWM-ICU/readme.txt deleted file mode 100644 index 831073bf7d..0000000000 --- a/testhal/AT32/AT32F415/PWM-ICU/readme.txt +++ /dev/null @@ -1,28 +0,0 @@ -***************************************************************************** -** ChibiOS/HAL - PWM/ICU driver demo for AT32. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an AT-START-F415 board. - -** The Demo ** - -The application demonstrates the use of the AT32 PWM and ICU drivers. Pins -PA8 and PB6 must be connected in order to trigger the ICU input with the -PWM output. The ICU unit will measure the generated PWM. - -** Build Procedure ** - -The demo has been tested using the free Codesourcery GCC-based toolchain -and YAGARTO. -Just modify the TRGT line in the makefile in order to use different GCC ports. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are copyright of -Artery Technology and are licensed under a different license. -Also note that not all the files present in the AT library are distributed -with ChibiOS/RT, you can find the whole library on the AT web site: - - https://www.arterychip.com/en diff --git a/testhal/AT32/AT32F415/USB_CDC/.project b/testhal/AT32/AT32F415/USB_CDC/.project deleted file mode 100644 index d38abd8218..0000000000 --- a/testhal/AT32/AT32F415/USB_CDC/.project +++ /dev/null @@ -1,49 +0,0 @@ - - - AT32F415-USB_CDC - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - board - 2 - CHIBIOS_CONTRIB/os/hal/boards/AT_START_F415 - - - os - 2 - CHIBIOS/os - - - test - 2 - CHIBIOS/test - - - - - CHIBIOS_CONTRIB - file:/E:/Duc/Secrets/QMK_custom_mcu/at32_test_qmk/lib/chibios-contrib - - - diff --git a/testhal/AT32/AT32F415/USB_CDC/readme.txt b/testhal/AT32/AT32F415/USB_CDC/readme.txt deleted file mode 100644 index a016a1945e..0000000000 --- a/testhal/AT32/AT32F415/USB_CDC/readme.txt +++ /dev/null @@ -1,26 +0,0 @@ -***************************************************************************** -** ChibiOS/HAL - USB-CDC driver demo for AT32. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an AT-START-F415 board. - -** The Demo ** - -The application demonstrates the use of the AT32 USB (OTG) driver. - -** Build Procedure ** - -The demo has been tested using the free Codesourcery GCC-based toolchain -and YAGARTO. -Just modify the TRGT line in the makefile in order to use different GCC ports. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are copyright of -Artery Technology and are licensed under a different license. -Also note that not all the files present in the AT library are distributed -with ChibiOS/RT, you can find the whole library on the AT web site: - - https://www.arterychip.com/en diff --git a/testhal/AT32/AT32F415/PWM-ICU/.cproject b/testhal/AT32/multi/USB_CDC/.cproject similarity index 56% rename from testhal/AT32/AT32F415/PWM-ICU/.cproject rename to testhal/AT32/multi/USB_CDC/.cproject index 6caf490fe7..74701160a0 100644 --- a/testhal/AT32/AT32F415/PWM-ICU/.cproject +++ b/testhal/AT32/multi/USB_CDC/.cproject @@ -1,8 +1,8 @@ - - + + @@ -14,20 +14,20 @@ - - - - - - - - + + + + + + + + - - + + - - + + @@ -37,13 +37,20 @@ - + - + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/multi/USB_CDC/.project b/testhal/AT32/multi/USB_CDC/.project new file mode 100644 index 0000000000..619fe276fe --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/.project @@ -0,0 +1,78 @@ + + + AT32-USB_CDC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/testhal/AT32/multi/USB_CDC/Makefile b/testhal/AT32/multi/USB_CDC/Makefile new file mode 100644 index 0000000000..c8606df05e --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/Makefile @@ -0,0 +1,18 @@ +############################################################################## +# Multi-project makefile rules +# + +all: + @echo + @echo === Building for AT-START-F415 ===================================== + +@make --no-print-directory -f ./make/at-start-f415.make all + @echo ==================================================================== + @echo + +clean: + @echo + +@make --no-print-directory -f ./make/at-start-f415.make clean + @echo + +# +############################################################################## diff --git a/testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h similarity index 96% rename from testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h rename to testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h index 6ae2a5be1b..42828da814 100644 --- a/testhal/AT32/AT32F415/USB_CDC/cfg/chconf.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h @@ -141,6 +141,19 @@ #define CH_CFG_NO_IDLE_THREAD FALSE #endif +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + /** @} */ /*===========================================================================*/ @@ -362,6 +375,16 @@ #define CH_CFG_USE_MAILBOXES TRUE #endif +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + /** * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included @@ -565,7 +588,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#define CH_DBG_SYSTEM_STATE_CHECK FALSE #endif /** @@ -576,7 +599,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS TRUE +#define CH_DBG_ENABLE_CHECKS FALSE #endif /** @@ -588,7 +611,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS TRUE +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** @@ -598,7 +621,7 @@ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. */ #if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED #endif /** @@ -621,7 +644,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK TRUE +#define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** @@ -633,7 +656,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS TRUE +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/testhal/AT32/AT32F415/USB_CDC/cfg/halconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/halconf.h similarity index 100% rename from testhal/AT32/AT32F415/USB_CDC/cfg/halconf.h rename to testhal/AT32/multi/USB_CDC/cfg/at-start-f415/halconf.h diff --git a/testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h similarity index 98% rename from testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h rename to testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h index cdc11f27bf..3b0e65f93f 100644 --- a/testhal/AT32/AT32F415/USB_CDC/cfg/mcuconf.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio ChibiOS - Copyright (C) 2023..2024 HorrorTroll ChibiOS - Copyright (C) 2023..2024 Zhaqian @@ -19,8 +19,6 @@ #ifndef MCUCONF_H #define MCUCONF_H -#define AT32F415_MCUCONF - /* * AT32F415 drivers configuration. * The following settings override the default settings present in @@ -35,6 +33,8 @@ * 0...3 Lowest...Highest. */ +#define AT32F415_MCUCONF + /* * HAL driver system settings. */ @@ -58,6 +58,7 @@ #define AT32_USB_CLOCK_REQUIRED TRUE #define AT32_USBDIV AT32_USBDIV_DIV3 #define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 #define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV #define AT32_PVM_ENABLE FALSE #define AT32_PVMSEL AT32_PVMSEL_LEV1 @@ -212,7 +213,6 @@ #define AT32_USB_USE_OTG1 TRUE #define AT32_USB_OTG1_IRQ_PRIORITY 14 #define AT32_USB_OTG1_RX_FIFO_SIZE 512 -#define AT32_USB_HOST_WAKEUP_DURATION 2 /* * WDG driver system settings. diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.c b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.c new file mode 100644 index 0000000000..25e871321a --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.c @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.h new file mode 100644 index 0000000000..586eb17f65 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_USB1 USBD1 + +#define PORTAB_SDU1 SDU1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/AT32F415/USB_CDC/main.c b/testhal/AT32/multi/USB_CDC/main.c similarity index 82% rename from testhal/AT32/AT32F415/USB_CDC/main.c rename to testhal/AT32/multi/USB_CDC/main.c index 6bf5791d5a..a18e70123e 100644 --- a/testhal/AT32/AT32F415/USB_CDC/main.c +++ b/testhal/AT32/multi/USB_CDC/main.c @@ -16,12 +16,12 @@ limitations under the License. */ +#include #include #include #include "ch.h" #include "hal.h" - #include "shell.h" #include "chprintf.h" @@ -62,12 +62,12 @@ static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) { #if 1 /* Writing in channel mode.*/ - chnWrite(&SDU1, buf, sizeof buf - 1); + chnWrite(&PORTAB_SDU1, buf, sizeof buf - 1); #else /* Writing in buffer mode.*/ - (void) obqGetEmptyBufferTimeout(&SDU1.obqueue, TIME_INFINITE); - memcpy(SDU1.obqueue.ptr, buf, SERIAL_USB_BUFFERS_SIZE); - obqPostFullBuffer(&SDU1.obqueue, SERIAL_USB_BUFFERS_SIZE); + (void) obqGetEmptyBufferTimeout(&PORTAB_SDU1.obqueue, TIME_INFINITE); + memcpy(PORTAB_SDU1.obqueue.ptr, buf, SERIAL_USB_BUFFERS_SIZE); + obqPostFullBuffer(&PORTAB_SDU1.obqueue, SERIAL_USB_BUFFERS_SIZE); #endif } chprintf(chp, "\r\n\nstopped\r\n"); @@ -79,7 +79,7 @@ static const ShellCommand commands[] = { }; static const ShellConfig shell_cfg1 = { - (BaseSequentialStream *)&SDU1, + (BaseSequentialStream *)&PORTAB_SDU1, commands }; @@ -88,7 +88,7 @@ static const ShellConfig shell_cfg1 = { /*===========================================================================*/ /* - * Green LED blinker thread, times are in milliseconds. + * LED blinker thread, times are in milliseconds. */ static THD_WORKING_AREA(waThread1, 128); static THD_FUNCTION(Thread1, arg) { @@ -96,10 +96,20 @@ static THD_FUNCTION(Thread1, arg) { (void)arg; chRegSetThreadName("blinker"); while (true) { - systime_t time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500; - palClearPad(IOPORT3, GPIOC_LED_GREEN); + systime_t time; + + time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500; + palSetLine(PORTAB_BLINK_LED1); + chThdSleepMilliseconds(time); + palSetLine(PORTAB_BLINK_LED2); + chThdSleepMilliseconds(time); + palSetLine(PORTAB_BLINK_LED3); + chThdSleepMilliseconds(time); + palClearLine(PORTAB_BLINK_LED1); chThdSleepMilliseconds(time); - palSetPad(IOPORT3, GPIOC_LED_GREEN); + palClearLine(PORTAB_BLINK_LED2); + chThdSleepMilliseconds(time); + palClearLine(PORTAB_BLINK_LED3); chThdSleepMilliseconds(time); } } @@ -119,11 +129,16 @@ int main(void) { halInit(); chSysInit(); + /* + * Board-dependent initialization. + */ + portab_setup(); + /* * Initializes a serial-over-USB CDC driver. */ - sduObjectInit(&SDU1); - sduStart(&SDU1, &serusbcfg); + sduObjectInit(&PORTAB_SDU1); + sduStart(&PORTAB_SDU1, &serusbcfg); /* * Activates the USB driver and then the USB bus pull-up on D+. @@ -131,7 +146,7 @@ int main(void) { * after a reset. */ usbDisconnectBus(serusbcfg.usbp); - chThdSleepMilliseconds(1000); + chThdSleepMilliseconds(1500); usbStart(serusbcfg.usbp, &usbcfg); usbConnectBus(serusbcfg.usbp); @@ -149,7 +164,7 @@ int main(void) { * Normal main() thread activity, spawning shells. */ while (true) { - if (SDU1.config->usbp->state == USB_ACTIVE) { + if (PORTAB_SDU1.config->usbp->state == USB_ACTIVE) { thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, "shell", NORMALPRIO + 1, shellThread, (void *)&shell_cfg1); diff --git a/testhal/AT32/AT32F415/PWM-ICU/Makefile b/testhal/AT32/multi/USB_CDC/make/at-start-f415.make similarity index 67% rename from testhal/AT32/AT32F415/PWM-ICU/Makefile rename to testhal/AT32/multi/USB_CDC/make/at-start-f415.make index a00e20a67f..60300dbfcd 100644 --- a/testhal/AT32/AT32F415/PWM-ICU/Makefile +++ b/testhal/AT32/multi/USB_CDC/make/at-start-f415.make @@ -33,11 +33,6 @@ ifeq ($(USE_LTO),) USE_LTO = yes endif -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - # Enable this if you want to see the full log while compiling. ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no @@ -74,6 +69,11 @@ ifeq ($(USE_FPU),) USE_FPU = no endif +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + # # Architecture or project specific options ############################################################################## @@ -85,12 +85,15 @@ endif # Define project name here PROJECT = ch +# Target settings. +MCU = cortex-m4 + # Imported source files and paths. CHIBIOS := ../../../../../ChibiOS -CHIBIOS_CONTRIB := ../../../../ -CONFDIR := ./cfg -BUILDDIR := ./build -DEPDIR := ./.dep +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f415 +BUILDDIR := ./build/at-start-f415 +DEPDIR := ./.dep/at-start-f415 # Licensing files. include $(CHIBIOS)/os/license/license.mk @@ -104,85 +107,38 @@ include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk # Other files (optional). -#include $(CHIBIOS)/os/test/test.mk -#include $(CHIBIOS)/test/rt/rt_test.mk -#include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk -# Define linker script file here +# Define linker script file here. LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = $(ALLCSRC) \ $(TESTSRC) \ + $(CONFDIR)/portab.c \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. CPPSRC = $(ALLCPPSRC) -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - # List ASM source files here. ASMSRC = $(ALLASMSRC) + # List ASM with preprocessor source files here. ASMXSRC = $(ALLXASMSRC) # Inclusion directories. INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m4 - -#TRGT = arm-elf- -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -AR = $(TRGT)ar -OD = $(TRGT)objdump -SZ = $(TRGT)size -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - # Define C warning options here. CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes @@ -190,7 +146,7 @@ CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes CPPWARN = -Wall -Wextra -Wundef # -# Compiler settings +# Project, target, sources and paths ############################################################################## ############################################################################## @@ -213,7 +169,7 @@ ULIBDIR = ULIBS = # -# End of user defines +# End of user section ############################################################################## ############################################################################## @@ -221,6 +177,7 @@ ULIBS = # RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk include $(RULESPATH)/rules.mk # diff --git a/testhal/AT32/AT32F415/USB_CDC/usbcfg.c b/testhal/AT32/multi/USB_CDC/source/usbcfg.c similarity index 93% rename from testhal/AT32/AT32F415/USB_CDC/usbcfg.c rename to testhal/AT32/multi/USB_CDC/source/usbcfg.c index b1afb386b4..4ec94841aa 100644 --- a/testhal/AT32/AT32F415/USB_CDC/usbcfg.c +++ b/testhal/AT32/multi/USB_CDC/source/usbcfg.c @@ -17,16 +17,17 @@ */ #include "hal.h" +#include "portab.h" /* Virtual serial port over USB.*/ -SerialUSBDriver SDU1; +SerialUSBDriver PORTAB_SDU1; /* * Endpoints to be used for USBD1. */ -#define USBD1_DATA_REQUEST_EP 1 -#define USBD1_DATA_AVAILABLE_EP 1 -#define USBD1_INTERRUPT_REQUEST_EP 2 +#define USB1_DATA_REQUEST_EP 1 +#define USB1_DATA_AVAILABLE_EP 1 +#define USB1_INTERRUPT_REQUEST_EP 2 /* * USB Device Descriptor. @@ -104,7 +105,7 @@ static const uint8_t vcom_configuration_descriptor_data[67] = { USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class Interface). */ /* Endpoint 2 Descriptor.*/ - USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + USB_DESC_ENDPOINT (USB1_INTERRUPT_REQUEST_EP|0x80, 0x03, /* bmAttributes (Interrupt). */ 0x0008, /* wMaxPacketSize. */ 0xFF), /* bInterval. */ @@ -120,12 +121,12 @@ static const uint8_t vcom_configuration_descriptor_data[67] = { 4.7). */ 0x00), /* iInterface. */ /* Endpoint 3 Descriptor.*/ - USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + USB_DESC_ENDPOINT (USB1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ 0x02, /* bmAttributes (Bulk). */ 0x0040, /* wMaxPacketSize. */ 0x00), /* bInterval. */ /* Endpoint 1 Descriptor.*/ - USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + USB_DESC_ENDPOINT (USB1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ 0x02, /* bmAttributes (Bulk). */ 0x0040, /* wMaxPacketSize. */ 0x00) /* bInterval. */ @@ -266,7 +267,7 @@ static const USBEndpointConfig ep2config = { * Handles the USB driver global events. */ static void usb_event(USBDriver *usbp, usbevent_t event) { - extern SerialUSBDriver SDU1; + extern SerialUSBDriver PORTAB_SDU1; switch (event) { case USB_EVENT_ADDRESS: @@ -277,11 +278,11 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { /* Enables the endpoints specified into the configuration. Note, this callback is invoked from an ISR so I-Class functions must be used.*/ - usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); - usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + usbInitEndpointI(usbp, USB1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USB1_INTERRUPT_REQUEST_EP, &ep2config); /* Resetting the state of the CDC subsystem.*/ - sduConfigureHookI(&SDU1); + sduConfigureHookI(&PORTAB_SDU1); chSysUnlockFromISR(); return; @@ -293,7 +294,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { chSysLockFromISR(); /* Disconnection event on suspend.*/ - sduSuspendHookI(&SDU1); + sduSuspendHookI(&PORTAB_SDU1); chSysUnlockFromISR(); return; @@ -301,7 +302,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { chSysLockFromISR(); /* Connection event on wakeup.*/ - sduWakeupHookI(&SDU1); + sduWakeupHookI(&PORTAB_SDU1); chSysUnlockFromISR(); return; @@ -319,7 +320,7 @@ static void sof_handler(USBDriver *usbp) { (void)usbp; osalSysLockFromISR(); - sduSOFHookI(&SDU1); + sduSOFHookI(&PORTAB_SDU1); osalSysUnlockFromISR(); } @@ -337,8 +338,8 @@ const USBConfig usbcfg = { * Serial over USB driver configuration. */ const SerialUSBConfig serusbcfg = { - &USBD1, - USBD1_DATA_REQUEST_EP, - USBD1_DATA_AVAILABLE_EP, - USBD1_INTERRUPT_REQUEST_EP + &PORTAB_USB1, + USB1_DATA_REQUEST_EP, + USB1_DATA_AVAILABLE_EP, + USB1_INTERRUPT_REQUEST_EP }; diff --git a/testhal/AT32/AT32F415/USB_CDC/usbcfg.h b/testhal/AT32/multi/USB_CDC/source/usbcfg.h similarity index 95% rename from testhal/AT32/AT32F415/USB_CDC/usbcfg.h rename to testhal/AT32/multi/USB_CDC/source/usbcfg.h index 036a822f31..40a9a2d3ef 100644 --- a/testhal/AT32/AT32F415/USB_CDC/usbcfg.h +++ b/testhal/AT32/multi/USB_CDC/source/usbcfg.h @@ -21,7 +21,7 @@ extern const USBConfig usbcfg; extern SerialUSBConfig serusbcfg; -extern SerialUSBDriver SDU1; +extern SerialUSBDriver PORTAB_SDU1; #endif /* USBCFG_H */ From fbdaa46d1a98295616063ab4e32f439c3e8cc34a Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Wed, 3 Jul 2024 14:04:41 +0700 Subject: [PATCH 04/18] Update version of CMSIS files --- os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h | 4 ++-- os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h | 12 ++++++------ os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h | 12 ++++++------ os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h | 12 ++++++------ 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h index 07550788dd..ce0861468d 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h @@ -1,10 +1,10 @@ /** - ****************************************************************************** + ************************************************************************** * @file at32f415.h * @author Artery Technology & HorrorTroll & Zhaqian * @brief AT32F415 header file * - ****************************************************************************** + ************************************************************************** * Copyright notice & Disclaimer * * The software Board Support Package (BSP) that is made available to diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h index 1cd3e4e0f7..2507e3c7df 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h @@ -1,12 +1,12 @@ /** - ****************************************************************************** + ************************************************************************** * @file at32f415cx.h * @author Artery Technology & HorrorTroll & Zhaqian - * @version v2.1.2 - * @date 05-January-2024 + * @version v2.1.4 + * @date 01-February-2024 * @brief AT32F415Cx header file. * - ****************************************************************************** + ************************************************************************** * Copyright notice & Disclaimer * * The software Board Support Package (BSP) that is made available to @@ -42,11 +42,11 @@ #endif /** - * @brief CMSIS Device version number V2.1.2 + * @brief CMSIS Device version number V2.1.4 */ #define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ #define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ -#define __AT32F415_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */ +#define __AT32F415_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */ #define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\ |(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h index 2bc82557c5..994bd9891b 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h @@ -1,12 +1,12 @@ /** - ****************************************************************************** + ************************************************************************** * @file at32f415kx.h * @author Artery Technology & HorrorTroll & Zhaqian - * @version v2.1.2 - * @date 05-January-2024 + * @version v2.1.4 + * @date 01-February-2024 * @brief AT32F415Kx header file. * - ****************************************************************************** + ************************************************************************** * Copyright notice & Disclaimer * * The software Board Support Package (BSP) that is made available to @@ -42,11 +42,11 @@ #endif /** - * @brief CMSIS Device version number V2.1.2 + * @brief CMSIS Device version number V2.1.4 */ #define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ #define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ -#define __AT32F415_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */ +#define __AT32F415_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */ #define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\ |(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h index fdd170d7af..c3b77c5c92 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h @@ -1,12 +1,12 @@ /** - ****************************************************************************** + ************************************************************************** * @file at32f415rx.h * @author Artery Technology & HorrorTroll & Zhaqian - * @version v2.1.2 - * @date 05-January-2024 + * @version v2.1.4 + * @date 01-February-2024 * @brief AT32F415Rx header file. * - ****************************************************************************** + ************************************************************************** * Copyright notice & Disclaimer * * The software Board Support Package (BSP) that is made available to @@ -42,11 +42,11 @@ #endif /** - * @brief CMSIS Device version number V2.1.2 + * @brief CMSIS Device version number V2.1.4 */ #define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ #define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ -#define __AT32F415_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */ +#define __AT32F415_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */ #define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\ |(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\ From 7c973fe23b44e8f8f115c48da94568427e453ee6 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Sun, 28 Jul 2024 22:49:43 +0700 Subject: [PATCH 05/18] Update LLD driver for I2C, OTG and ERTC --- os/hal/ports/AT32/LLD/I2Cv1/driver.mk | 26 ++++++--- os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c | 22 ++++++++ os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h | 2 +- os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c | 34 +----------- os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h | 2 - os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c | 66 +++++++++++++++-------- 6 files changed, 88 insertions(+), 64 deletions(-) diff --git a/os/hal/ports/AT32/LLD/I2Cv1/driver.mk b/os/hal/ports/AT32/LLD/I2Cv1/driver.mk index 9a2fdb995c..e2adad39d7 100644 --- a/os/hal/ports/AT32/LLD/I2Cv1/driver.mk +++ b/os/hal/ports/AT32/LLD/I2Cv1/driver.mk @@ -1,9 +1,21 @@ -ifeq ($(USE_SMART_BUILD),yes) -ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c -endif +ifeq ($(USE_HAL_I2C_FALLBACK),yes) + # Fallback SW driver. + ifeq ($(USE_SMART_BUILD),yes) + ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) + PLATFORMSRC_CONTRIB += $(CHIBIOS)/os/hal/lib/fallback/I2C/hal_i2c_lld.c + endif + else + PLATFORMSRC_CONTRIB += $(CHIBIOS)/os/hal/lib/fallback/I2C/hal_i2c_lld.c + endif + PLATFORMINC_CONTRIB += $(CHIBIOS)/os/hal/lib/fallback/I2C else -PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c -endif + ifeq ($(USE_SMART_BUILD),yes) + ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) + PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c + endif + else + PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c + endif -PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1 + PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1 +endif diff --git a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c index 6e6482301a..e634185f52 100644 --- a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c +++ b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c @@ -280,6 +280,16 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { /* Clear ADDR7F flag. */ if (event & (I2C_STS1_ADDR7F | I2C_STS1_ADDRHF)) (void)dp->STS2; + /* BUSERR flag doesnt happen anymore in event handling */ +#if 0 + /* Errata 1.14.2 for AT32F415, I2C communication error when BUSERR is detected on bus.*/ + /* Errata 1.4.4 for AT32F403A/7, BUSERR is detected by I2C before start of communication.*/ + /* Errata 1.15.2 for AT32F413, BUSERR is detected by I2C before start of communication.*/ + /* Errata 1.2.2 for AT32A403A, BUSERR is detected by I2C before start of communication.*/ + if (event & I2C_STS1_BUSERR) { + dp->STS1 &= ~I2C_STS1_BUSERR; + } +#endif } /** @@ -354,6 +364,18 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sts) { if (sts & I2C_STS1_BUSERR) { /* Bus error. */ i2cp->errors |= I2C_BUS_ERROR; + /* No more needed */ +#if 0 + /* Errata 1.14.2 for AT32F415, I2C communication error when BUSERR is + detected on bus.*/ + /* Errata 1.4.4 for AT32F403A/7, BUSERR is detected by I2C before start + of communication.*/ + /* Errata 1.15.2 for AT32F413, BUSERR is detected by I2C before start + of communication.*/ + /* Errata 1.2.2 for AT32A403A, BUSERR is detected by I2C before start + of communication.*/ + i2cp->i2c->STS1 &= ~I2C_STS1_BUSERR; +#endif } if (sts & I2C_STS1_ARLOST) /* Arbitration lost. */ diff --git a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h index ca73059d07..154646cdb1 100644 --- a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h +++ b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h @@ -162,7 +162,7 @@ #endif /* Check clock range. */ -#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 72) +#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 75) #error "I2C peripheral clock frequency out of range." #endif diff --git a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c index fc114fb9a6..b43b3edb2e 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c +++ b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c @@ -49,13 +49,8 @@ #endif #elif AT32_OTG_STEPPING == 2 -#if defined(BOARD_OTG_VBUSIG_LPM) -#define GCCFG_INIT_VALUE (GCCFG_VBUSIG | GCCFG_LP_MODE | \ - GCCFG_PWRDOWN) -#elif defined(BOARD_OTG_VBUSIG) +#if defined(BOARD_OTG_VBUSIG) #define GCCFG_INIT_VALUE (GCCFG_VBUSIG | GCCFG_PWRDOWN) -#elif defined(BOARD_OTG_LPM) -#define GCCFG_INIT_VALUE (GCCFG_LP_MODE | GCCFG_PWRDOWN) #else #define GCCFG_INIT_VALUE GCCFG_PWRDOWN #endif @@ -792,16 +787,6 @@ void usb_lld_start(USBDriver *usbp) { crmEnableOTG_HS(true); crmResetOTG_HS(); - /* ULPI clock is managed depending on the presence of an external - PHY.*/ -#if defined(BOARD_OTG2_USES_ULPI) - crmEnableOTG_HSULPI(true); -#else - /* Workaround for the problem described here: - http://forum.chibios.org/phpbb/viewtopic.php?f=16&t=1798.*/ - crmDisableOTG_HSULPI(); -#endif - /* Enables IRQ vector.*/ nvicEnableVector(AT32_OTG2_NUMBER, AT32_USB_OTG2_IRQ_PRIORITY); @@ -833,21 +818,7 @@ void usb_lld_start(USBDriver *usbp) { /* PHY enabled.*/ otgp->PCGCCTL = 0; -#if defined(BOARD_OTG2_USES_ULPI) -#if AT32_USB_USE_OTG1 - if (&USBD1 == usbp) { - otgp->GCCFG = GCCFG_INIT_VALUE; - } -#endif - -#if AT32_USB_USE_OTG2 - if (&USBD2 == usbp) { - otgp->GCCFG = 0; - } -#endif -#else otgp->GCCFG = GCCFG_INIT_VALUE; -#endif /* Soft core reset.*/ otg_core_reset(usbp); @@ -913,9 +884,6 @@ void usb_lld_stop(USBDriver *usbp) { if (&USBD2 == usbp) { nvicDisableVector(AT32_OTG2_NUMBER); crmDisableOTG_HS(); -#if defined(BOARD_OTG2_USES_ULPI) - crmDisableOTG_HSULPI(); -#endif } #endif } diff --git a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h index 56cfc90b9d..f8c9fc8fee 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h +++ b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h @@ -150,11 +150,9 @@ #error "unsupported AT32_OTG_STEPPING" #endif -/* #if !defined(AT32_HAS_OTG1) || !defined(AT32_HAS_OTG2) #error "AT32_HAS_OTGx not defined in registry" #endif -*/ #if AT32_HAS_OTG1 && !defined(AT32_OTG1_ENDPOINTS) #error "AT32_OTG1_ENDPOINTS not defined in registry" diff --git a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c index e9e0c19358..b249f25620 100644 --- a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c +++ b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c @@ -282,6 +282,9 @@ OSAL_IRQ_HANDLER(AT32_ERTC_COMMON_HANDLER) { #if defined(ERTC_STS_TP1F) | ERTC_STS_TP1F #endif +#if defined(ERTC_STS_TP2F) + | ERTC_STS_TP2F +#endif #if defined(ERTC_STS_WATF) | ERTC_STS_WATF #endif @@ -337,6 +340,11 @@ OSAL_IRQ_HANDLER(AT32_ERTC_COMMON_HANDLER) { if ((sts & ERTC_STS_TP1F) != 0U) { RTCD1.callback(&RTCD1, RTC_EVENT_TAMP1); } +#endif +#if defined(ERTC_STS_TP2F) + if ((sts & ERTC_STS_TP2F) != 0U) { + RTCD1.callback(&RTCD1, RTC_EVENT_TAMP2); + } #endif } #endif /* !defined(ERTC_TAMP_TP1EN) */ @@ -364,6 +372,9 @@ OSAL_IRQ_HANDLER(AT32_ERTC_TAMP_STAMP_HANDLER) { | ERTC_STS_TSOF #if defined(ERTC_STS_TP1F) | ERTC_STS_TP1F +#endif +#if defined(ERTC_STS_TP2F) + | ERTC_STS_TP2F #endif ); @@ -392,6 +403,11 @@ OSAL_IRQ_HANDLER(AT32_ERTC_TAMP_STAMP_HANDLER) { if ((sts & ERTC_STS_TP1F) != 0U) { RTCD1.callback(&RTCD1, RTC_EVENT_TAMP1); } +#endif +#if defined(ERTC_STS_TP2F) + if ((sts & ERTC_STS_TP2F) != 0U) { + RTCD1.callback(&RTCD1, RTC_EVENT_TAMP2); + } #endif } #endif /* !defined(ERTC_TAMP_TP1EN) */ @@ -467,7 +483,7 @@ OSAL_IRQ_HANDLER(AT32_ERTC_ALARM_HANDLER) { } #else -#error "missing required RTC handlers definitions in IRQ" +#error "missing required RTC handlers definitions in registry" #endif /*===========================================================================*/ @@ -488,8 +504,8 @@ void rtc_lld_init(void) { RTCD1.rtc = ERTC; /* Disable write protection. */ - RTCD1.rtc->WP = 0xCA; - RTCD1.rtc->WP = 0x53; + RTCD1.rtc->WP = 0xCAU; + RTCD1.rtc->WP = 0x53U; /* If calendar has not been initialized yet then proceed with the initial setup.*/ @@ -497,12 +513,12 @@ void rtc_lld_init(void) { rtc_enter_init(); - RTCD1.rtc->CTRL = AT32_ERTC_CTRL_INIT; + RTCD1.rtc->CTRL = AT32_ERTC_CTRL_INIT | ERTC_CTRL_DREN; #if defined(ERTC_TAMP_TP1EN) RTCD1.rtc->TAMP = AT32_ERTC_TAMP_INIT; #endif RTCD1.rtc->STS = ERTC_STS_IMEN; /* Clearing all but ERTC_STS_IMEN. */ - RTCD1.rtc->DIV = AT32_ERTC_DIV_BITS; + RTCD1.rtc->DIV = AT32_ERTC_DIV_BITS & 0x7FFFU; RTCD1.rtc->DIV = AT32_ERTC_DIV_BITS; rtc_exit_init(); @@ -567,34 +583,42 @@ void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { * @notapi */ void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { - uint32_t date, time, ctrl; + uint32_t ctrl, date, time, prev_date, prev_time; uint32_t subs; #if AT32_ERTC_HAS_SUBSECONDS - uint32_t oldsbs, sbs; + uint32_t sbs, prev_sbs; #endif /* AT32_ERTC_HAS_SUBSECONDS */ syssts_t sts; /* Entering a reentrant critical zone.*/ sts = osalSysGetStatusAndLockX(); - /* Synchronization with the RTC and reading the registers, note - DATE must be read last.*/ - while ((rtcp->rtc->STS & ERTC_STS_UPDF) == 0) - ; + /* Repeated registers read until 2 matching sets are found.*/ #if AT32_ERTC_HAS_SUBSECONDS - do -#endif /* AT32_ERTC_HAS_SUBSECONDS */ - { - oldsbs = rtcp->rtc->SBS; + sbs = 0U; + time = 0U; + date = 0U; + do { + prev_sbs = sbs; + prev_time = time; + prev_date = date; + sbs = rtcp->rtc->SBS; time = rtcp->rtc->TIME; date = rtcp->rtc->DATE; - } -#if AT32_ERTC_HAS_SUBSECONDS - while (oldsbs != (sbs = rtcp->rtc->SBS)); - (void) rtcp->rtc->DATE; -#endif /* AT32_ERTC_HAS_SUBSECONDS */ + } while ((sbs != prev_sbs) || (time != prev_time) || (date != prev_date)); +#else /* !AT32_ERTC_HAS_SUBSECONDS */ + time = 0U; + date = 0U; + do { + prev_time = time; + prev_date = date; + time = rtcp->rtc->TIME; + date = rtcp->rtc->DATE; + } while ((time != prev_time) || (date != prev_date)); +#endif /* !AT32_ERTC_HAS_SUBSECONDS */ + + /* DST bit is in CTRL, no need to poll on this one.*/ ctrl = rtcp->rtc->CTRL; - rtcp->rtc->STS &= ~ERTC_STS_UPDF; /* Leaving a reentrant critical zone.*/ osalSysRestoreStatusX(sts); From dc3f512a5cb2f4a874b0bc254e2e3992a976eee3 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Tue, 30 Jul 2024 22:18:35 +0700 Subject: [PATCH 06/18] Update LLD driver for SYSTICK and GPT Timer --- os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk | 1 - os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c | 18 +++++++- os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h | 43 +++++++++++++++++-- os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c | 45 +++++++++++--------- 4 files changed, 81 insertions(+), 26 deletions(-) diff --git a/os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk b/os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk index 02016429dd..a77b92f0fc 100644 --- a/os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk +++ b/os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk @@ -1,4 +1,3 @@ PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SYSTICKv1 - diff --git a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c index fd23d1d6f6..0ec4ae3e3e 100644 --- a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c +++ b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c @@ -46,7 +46,23 @@ #define ST_CTRL1_INIT 0x00000000U #endif -#if AT32_ST_USE_TIMER == 2 +#if AT32_ST_USE_TIMER == 1 + +#if !AT32_HAS_TMR1 +#error "TMR1 not present in the selected device" +#endif + +#if (OSAL_ST_RESOLUTION == 32) && !AT32_TMR1_IS_32BITS +#error "TMR1 is not a 32bits timer" +#endif + +#define ST_HANDLER AT32_TMR1_CH_HANDLER +#define ST_NUMBER AT32_TMR1_CH_NUMBER +#define ST_CLOCK_SRC AT32_TMRCLK2 +#define ST_ENABLE_CLOCK() crmEnableTMR1(true) +#define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR1_PAUSE + +#elif AT32_ST_USE_TIMER == 2 #if !AT32_HAS_TMR2 #error "TMR2 not present in the selected device" diff --git a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h index d53329abc6..c821d52232 100644 --- a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h +++ b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h @@ -49,10 +49,10 @@ #endif /** - * @brief TIMx unit (by number) to be used for free running operations. + * @brief TMRx unit (by number) to be used for free running operations. * @note You must select a 32 bits timer if a 32 bits @p systick_t type * is required. - * @note Timers 2, 3, 4, 5, 9, 10 and 11 are supported. + * @note Timers 1, 2, 3, 4, 5, 9, 10 and 11 are supported. */ #if !defined(AT32_ST_USE_TIMER) || defined(__DOXYGEN__) #define AT32_ST_USE_TIMER 2 @@ -79,6 +79,10 @@ /* This has to go after transition to shared handlers is complete for all platforms.*/ +#if !defined(AT32_HAS_TMR1) +#define AT32_HAS_TMR1 FALSE +#endif + #if !defined(AT32_HAS_TMR2) #define AT32_HAS_TMR2 FALSE #endif @@ -110,7 +114,31 @@ #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING -#if AT32_ST_USE_TIMER == 2 +#if AT32_ST_USE_TIMER == 1 + +#if defined(AT32_TMR1_IS_USED) +#error "ST requires TMR1 but the timer is already used" +#else +#define AT32_TMR1_IS_USED +#endif + +#if defined(AT32_TMR1_SUPPRESS_ISR) +#define AT32_SYSTICK_SUPPRESS_ISR +#endif + +#define AT32_ST_TMR AT32_TMR1 +#define ST_LLD_NUM_ALARMS AT32_TMR1_CHANNELS +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 TRUE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 FALSE + +#elif AT32_ST_USE_TIMER == 2 #if defined(AT32_TMR2_IS_USED) #error "ST requires TMR2 but the timer is already used" @@ -125,6 +153,7 @@ #define AT32_ST_TMR AT32_TMR2 #define ST_LLD_NUM_ALARMS AT32_TMR2_CHANNELS #define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 FALSE #define AT32_ST_USE_TMR2 TRUE #define AT32_ST_USE_TMR3 FALSE #define AT32_ST_USE_TMR4 FALSE @@ -148,6 +177,7 @@ #define AT32_ST_TMR AT32_TMR3 #define ST_LLD_NUM_ALARMS AT32_TMR3_CHANNELS #define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 FALSE #define AT32_ST_USE_TMR2 FALSE #define AT32_ST_USE_TMR3 TRUE #define AT32_ST_USE_TMR4 FALSE @@ -171,6 +201,7 @@ #define AT32_ST_TMR AT32_TMR4 #define ST_LLD_NUM_ALARMS AT32_TMR4_CHANNELS #define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 FALSE #define AT32_ST_USE_TMR2 FALSE #define AT32_ST_USE_TMR3 FALSE #define AT32_ST_USE_TMR4 TRUE @@ -194,6 +225,7 @@ #define AT32_ST_TMR AT32_TMR5 #define ST_LLD_NUM_ALARMS AT32_TMR5_CHANNELS #define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 FALSE #define AT32_ST_USE_TMR2 FALSE #define AT32_ST_USE_TMR3 FALSE #define AT32_ST_USE_TMR4 FALSE @@ -217,6 +249,7 @@ #define AT32_ST_TMR AT32_TMR9 #define ST_LLD_NUM_ALARMS AT32_TMR9_CHANNELS #define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 FALSE #define AT32_ST_USE_TMR2 FALSE #define AT32_ST_USE_TMR3 FALSE #define AT32_ST_USE_TMR4 FALSE @@ -240,6 +273,7 @@ #define AT32_ST_TMR AT32_TMR10 #define ST_LLD_NUM_ALARMS AT32_TMR10_CHANNELS #define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 FALSE #define AT32_ST_USE_TMR2 FALSE #define AT32_ST_USE_TMR3 FALSE #define AT32_ST_USE_TMR4 FALSE @@ -263,6 +297,7 @@ #define AT32_ST_TMR AT32_TMR11 #define ST_LLD_NUM_ALARMS AT32_TMR11_CHANNELS #define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 FALSE #define AT32_ST_USE_TMR2 FALSE #define AT32_ST_USE_TMR3 FALSE #define AT32_ST_USE_TMR4 FALSE @@ -288,6 +323,7 @@ #elif OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC #define AT32_ST_USE_SYSTICK TRUE +#define AT32_ST_USE_TMR1 FALSE #define AT32_ST_USE_TMR2 FALSE #define AT32_ST_USE_TMR3 FALSE #define AT32_ST_USE_TMR4 FALSE @@ -299,6 +335,7 @@ #else #define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 FALSE #define AT32_ST_USE_TMR2 FALSE #define AT32_ST_USE_TMR3 FALSE #define AT32_ST_USE_TMR4 FALSE diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c index c10cc749e3..6c43aecdfb 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c @@ -248,58 +248,58 @@ void gpt_lld_init(void) { #if AT32_GPT_USE_TMR1 /* Driver initialization.*/ - gptObjectInit(&GPTD1); GPTD1.tmr = AT32_TMR1; GPTD1.has_plus_mode = (bool)AT32_TMR1_IS_32BITS; + gptObjectInit(&GPTD1); #endif #if AT32_GPT_USE_TMR2 /* Driver initialization.*/ - gptObjectInit(&GPTD2); GPTD2.tmr = AT32_TMR2; GPTD2.has_plus_mode = (bool)AT32_TMR2_IS_32BITS; + gptObjectInit(&GPTD2); #endif #if AT32_GPT_USE_TMR3 /* Driver initialization.*/ - gptObjectInit(&GPTD3); GPTD3.tmr = AT32_TMR3; GPTD3.has_plus_mode = (bool)AT32_TMR3_IS_32BITS; + gptObjectInit(&GPTD3); #endif #if AT32_GPT_USE_TMR4 /* Driver initialization.*/ - gptObjectInit(&GPTD4); GPTD4.tmr = AT32_TMR4; GPTD4.has_plus_mode = (bool)AT32_TMR4_IS_32BITS; + gptObjectInit(&GPTD4); #endif #if AT32_GPT_USE_TMR5 /* Driver initialization.*/ - gptObjectInit(&GPTD5); GPTD5.tmr = AT32_TMR5; GPTD5.has_plus_mode = (bool)AT32_TMR5_IS_32BITS; + gptObjectInit(&GPTD5); #endif #if AT32_GPT_USE_TMR9 /* Driver initialization.*/ - gptObjectInit(&GPTD9); GPTD9.tmr = AT32_TMR9; GPTD9.has_plus_mode = (bool)AT32_TMR9_IS_32BITS; + gptObjectInit(&GPTD9); #endif #if AT32_GPT_USE_TMR10 /* Driver initialization.*/ - gptObjectInit(&GPTD10); GPTD10.tmr = AT32_TMR10; GPTD10.has_plus_mode = (bool)AT32_TMR10_IS_32BITS; + gptObjectInit(&GPTD10); #endif #if AT32_GPT_USE_TMR11 /* Driver initialization.*/ - gptObjectInit(&GPTD11); GPTD11.tmr = AT32_TMR11; GPTD11.has_plus_mode = (bool)AT32_TMR11_IS_32BITS; + gptObjectInit(&GPTD11); #endif } @@ -409,15 +409,18 @@ void gpt_lld_start(GPTDriver *gptp) { osalDbgAssert(((uint32_t)(div + 1) * gptp->config->frequency) == gptp->clock, "invalid frequency"); + /* Timer configuration.*/ + /* If timer counter is 32bits.*/ if (gptp->has_plus_mode) { gptp->tmr->CTRL1 = AT32_TMR_CTRL1_PMEN; + } else { + gptp->tmr->CTRL1 = 0U; /* Initially stopped. */ } - /* Timer configuration.*/ gptp->tmr->CTRL2 = gptp->config->ctrl2; gptp->tmr->DIV = div; /* Prescaler value. */ - gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ + gptp->tmr->ISTS = 0U; /* Clear pending IRQs. */ gptp->tmr->IDEN = gptp->config->iden & /* DMA-related IDEN bits. */ ~AT32_TMR_IDEN_IRQ_MASK; } @@ -432,9 +435,9 @@ void gpt_lld_start(GPTDriver *gptp) { void gpt_lld_stop(GPTDriver *gptp) { if (gptp->state == GPT_READY) { - gptp->tmr->CTRL1 = 0; /* Timer disabled. */ - gptp->tmr->IDEN = 0; /* All IRQs disabled. */ - gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ + gptp->tmr->CTRL1 = 0U; /* Timer disabled. */ + gptp->tmr->IDEN = 0U; /* All IRQs disabled. */ + gptp->tmr->ISTS = 0U; /* Clear pending IRQs. */ #if AT32_GPT_USE_TMR1 if (&GPTD1 == gptp) { @@ -522,12 +525,12 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { gptp->tmr->PR = (uint32_t)(interval - 1U); /* Time constant. */ gptp->tmr->SWEVT = AT32_TMR_SWEVT_OVFSWTR; /* Update event. */ - gptp->tmr->CVAL = 0; /* Reset counter. */ + gptp->tmr->CVAL = 0U; /* Reset counter. */ /* NOTE: After generating the OVFSWTR event it takes several clock cycles before ISTS bit 0 goes to 1. This is why the clearing of CVAL has been inserted before the clearing of ISTS, to give it some time.*/ - gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ + gptp->tmr->ISTS = 0U; /* Clear pending IRQs. */ if (NULL != gptp->config->callback) gptp->tmr->IDEN |= AT32_TMR_IDEN_OVFIEN; /* Update Event IRQ enabled.*/ gptp->tmr->CTRL1 |= AT32_TMR_CTRL1_PRBEN | AT32_TMR_CTRL1_OVFS | AT32_TMR_CTRL1_TMREN; @@ -542,9 +545,8 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { */ void gpt_lld_stop_timer(GPTDriver *gptp) { - gptp->tmr->CTRL1 &= ~(AT32_TMR_CTRL1_PRBEN | AT32_TMR_CTRL1_OVFS | - AT32_TMR_CTRL1_TMREN); /* Initially stopped. */ - gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ + gptp->tmr->CTRL1 = 0U; /* Initially stopped. */ + gptp->tmr->ISTS = 0U; /* Clear pending IRQs. */ /* All interrupts disabled.*/ gptp->tmr->IDEN &= ~AT32_TMR_IDEN_IRQ_MASK; @@ -563,13 +565,14 @@ void gpt_lld_stop_timer(GPTDriver *gptp) { */ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + gptp->tmr->CTRL1 = AT32_TMR_CTRL1_OVFEN; /* Immediate update. */ gptp->tmr->PR = (uint32_t)(interval - 1U); /* Time constant. */ gptp->tmr->SWEVT = AT32_TMR_SWEVT_OVFSWTR; /* Update event. */ - gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ - gptp->tmr->CTRL1 |= AT32_TMR_CTRL1_OCMEN | AT32_TMR_CTRL1_OVFS | AT32_TMR_CTRL1_TMREN; + gptp->tmr->ISTS = 0U; /* Clear pending IRQs. */ + gptp->tmr->CTRL1 = AT32_TMR_CTRL1_OCMEN | AT32_TMR_CTRL1_OVFS | AT32_TMR_CTRL1_TMREN; while (!(gptp->tmr->ISTS & AT32_TMR_ISTS_OVFIF)) ; - gptp->tmr->ISTS = 0; /* Clear pending IRQs. */ + gptp->tmr->ISTS = 0U; /* Clear pending IRQs. */ } /** From fad2fcbb02d1f79a33f264a3f96cc0fcb3e036ac Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Thu, 1 Aug 2024 20:14:34 +0700 Subject: [PATCH 07/18] Update LLD driver for USART, ICU and PWM timers --- os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc | 2 +- os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c | 4 ++-- os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c | 1 - .../ports/AT32/LLD/USARTv1/hal_serial_lld.c | 22 +++++++++---------- os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c | 13 ----------- os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h | 8 ++----- 6 files changed, 15 insertions(+), 35 deletions(-) diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc index 1f860cf007..36ad2208bf 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc @@ -2,7 +2,7 @@ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio ChibiOS - Copyright (C) 2023..2024 HorrorTroll ChibiOS - Copyright (C) 2023..2024 Zhaqian - + Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c index 06ad33b847..4637ae3c39 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c @@ -634,7 +634,7 @@ void icu_lld_start_capture(ICUDriver *icup) { icup->tmr->ISTS = 0; /* Timer is started.*/ - icup->tmr->CTRL1 |= AT32_TMR_CTRL1_OVFS | AT32_TMR_CTRL1_TMREN; + icup->tmr->CTRL1 = AT32_TMR_CTRL1_OVFS | AT32_TMR_CTRL1_TMREN; } /** @@ -671,7 +671,7 @@ bool icu_lld_wait_capture(ICUDriver *icup) { void icu_lld_stop_capture(ICUDriver *icup) { /* Timer stopped.*/ - icup->tmr->CTRL1 &= ~(AT32_TMR_CTRL1_OVFS | AT32_TMR_CTRL1_TMREN); + icup->tmr->CTRL1 = 0; /* All interrupts disabled.*/ icup->tmr->IDEN &= ~AT32_TMR_IDEN_IRQ_MASK; diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c index f894318dfd..1ccd7ee104 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c @@ -674,7 +674,6 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, * @notapi */ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - pwmp->tmr->CDT[channel] = 0; pwmp->tmr->IDEN &= ~(2 << channel); } diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c index bbb1d2dd6f..0c205de859 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c @@ -91,14 +91,6 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) { baudr = (uint32_t)((sdp->clock + config->speed/2) / config->speed); -#if defined(USART_CTRL1_OVER8) - /* Correcting BAUDR value when oversampling by 8 instead of 16. - Fraction is still 4 bits wide, but only lower 3 bits used. - Mantissa is doubled, but Fraction is left the same.*/ - if (config->ctrl1 & USART_CTRL1_OVER8) - baudr = ((baudr & ~7) * 2) | (baudr & 7); -#endif - osalDbgAssert(baudr < 0x10000, "invalid BAUDR value"); u->BAUDR = baudr; @@ -111,7 +103,7 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) { USART_CTRL1_REN; u->STS = 0; (void)u->STS; /* STS reset step 1.*/ - (void)u->DT; /* DT reset step 2.*/ + (void)u->DT; /* STS reset step 2.*/ /* Deciding mask to be applied on the data register on receive, this is required in order to mask out the parity bit.*/ @@ -460,7 +452,7 @@ void sd_lld_stop(SerialDriver *sdp) { */ void sd_lld_serve_interrupt(SerialDriver *sdp) { USART_TypeDef *u = sdp->usart; - uint16_t ctrl1 = u->CTRL1; + uint16_t ctrl1; uint16_t sts = u->STS; /* Special case, LIN break detection.*/ @@ -487,6 +479,9 @@ void sd_lld_serve_interrupt(SerialDriver *sdp) { } osalSysUnlockFromISR(); + /* Caching CTRL1.*/ + ctrl1 = u->CTRL1; + /* Transmission buffer empty.*/ if ((ctrl1 & USART_CTRL1_TDBEIEN) && (sts & USART_STS_TDBE)) { msg_t b; @@ -494,7 +489,7 @@ void sd_lld_serve_interrupt(SerialDriver *sdp) { b = oqGetI(&sdp->oqueue); if (b < MSG_OK) { chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - u->CTRL1 = ctrl1 & ~USART_CTRL1_TDBEIEN; + ctrl1 &= ~USART_CTRL1_TDBEIEN; } else u->DT = b; @@ -506,10 +501,13 @@ void sd_lld_serve_interrupt(SerialDriver *sdp) { osalSysLockFromISR(); if (oqIsEmptyI(&sdp->oqueue)) { chnAddFlagsI(sdp, CHN_TRANSMISSION_END); - u->CTRL1 = ctrl1 & ~USART_CTRL1_TDCIEN; + ctrl1 &= ~USART_CTRL1_TDCIEN; } osalSysUnlockFromISR(); } + + /* Writing CTRL1 once.*/ + u->CTRL1 = ctrl1; } #endif /* HAL_USE_SERIAL */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c index a64e692c25..d5d2b8260e 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c @@ -154,14 +154,6 @@ static void usart_start(UARTDriver *uartp) { /* Baud rate setting.*/ baudr = (uint32_t)((uartp->clock + uartp->config->speed/2) / uartp->config->speed); - - /* Correcting USARTDIV when oversampling by 8 instead of 16. - Fraction is still 4 bits wide, but only lower 3 bits used. - Mantissa is doubled, but Fraction is left the same.*/ -#if defined(USART_CTRL1_OVER8) - if (uartp->config->ctrl1 & USART_CTRL1_OVER8) - baudr = ((baudr & ~7) * 2) | (baudr & 7); -#endif u->BAUDR = baudr; /* Resetting eventual pending status flags.*/ @@ -438,7 +430,6 @@ void uart_lld_start(UARTDriver *uartp) { crmEnableUSART1(true); nvicEnableVector(AT32_USART1_NUMBER, AT32_UART_USART1_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART1_DMA_PRIORITY); uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART1_DMA_PRIORITY); } @@ -464,7 +455,6 @@ void uart_lld_start(UARTDriver *uartp) { crmEnableUSART2(true); nvicEnableVector(AT32_USART2_NUMBER, AT32_UART_USART2_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART2_DMA_PRIORITY); uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART2_DMA_PRIORITY); } @@ -490,7 +480,6 @@ void uart_lld_start(UARTDriver *uartp) { crmEnableUSART3(true); nvicEnableVector(AT32_USART3_NUMBER, AT32_UART_USART3_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART3_DMA_PRIORITY); uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART3_DMA_PRIORITY); } @@ -522,7 +511,6 @@ void uart_lld_start(UARTDriver *uartp) { crmEnableUART4(true); nvicEnableVector(AT32_UART4_NUMBER, AT32_UART_UART4_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART4_DMA_PRIORITY); uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART4_DMA_PRIORITY); } @@ -554,7 +542,6 @@ void uart_lld_start(UARTDriver *uartp) { crmEnableUART5(true); nvicEnableVector(AT32_UART5_NUMBER, AT32_UART_UART5_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART5_DMA_PRIORITY); uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART5_DMA_PRIORITY); } diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h index e47ae7c1c5..66a83b40b0 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h @@ -197,17 +197,13 @@ #error "USART3 not present in the selected device" #endif -#if AT32_UART_USE_UART4 -#if !AT32_HAS_UART4 +#if AT32_UART_USE_UART4 && !AT32_HAS_UART4 #error "UART4 not present in the selected device" #endif -#endif /* AT32_UART_USE_UART4 */ -#if AT32_UART_USE_UART5 -#if !AT32_HAS_UART5 +#if AT32_UART_USE_UART5 && !AT32_HAS_UART5 #error "UART5 not present in the selected device" #endif -#endif /* AT32_UART_USE_UART5 */ #if !AT32_UART_USE_USART1 && !AT32_UART_USE_USART2 && \ !AT32_UART_USE_USART3 && !AT32_UART_USE_UART4 && \ From ae019b7da37cd6b0f795026d3bd233124c1a9c8f Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Fri, 2 Aug 2024 16:43:24 +0700 Subject: [PATCH 08/18] Update LLD drivers for ERTC and WDT again --- os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c | 240 ++++++++++----------- os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h | 101 +++++---- os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c | 34 +-- os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h | 18 +- 4 files changed, 196 insertions(+), 197 deletions(-) diff --git a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c index b249f25620..2dff5520c1 100644 --- a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c +++ b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c @@ -23,7 +23,7 @@ /** * @file RTCv2/hal_rtc_lld.c - * @brief AT32 RTC low level driver. + * @brief AT32 ERTC low level driver. * * @addtogroup RTC * @{ @@ -60,7 +60,7 @@ /*===========================================================================*/ /** - * @brief RTC driver identifier. + * @brief ERTC driver identifier. */ RTCDriver RTCD1; @@ -77,10 +77,10 @@ RTCDriver RTCD1; * * @notapi */ -static void rtc_enter_init(void) { +static void ertc_enter_init(void) { - RTCD1.rtc->STS |= ERTC_STS_IMEN; - while ((RTCD1.rtc->STS & ERTC_STS_IMF) == 0) + RTCD1.ertc->STS |= ERTC_STS_IMEN; + while ((RTCD1.ertc->STS & ERTC_STS_IMF) == 0) ; } @@ -89,9 +89,9 @@ static void rtc_enter_init(void) { * * @notapi */ -static inline void rtc_exit_init(void) { +static inline void ertc_exit_init(void) { - RTCD1.rtc->STS &= ~ERTC_STS_IMEN; + RTCD1.ertc->STS &= ~ERTC_STS_IMEN; } /** @@ -102,7 +102,7 @@ static inline void rtc_exit_init(void) { * * @notapi */ -static void rtc_decode_time(uint32_t time, RTCDateTime *timespec) { +static void ertc_decode_time(uint32_t time, RTCDateTime *timespec) { uint32_t n; n = ((time >> ERTC_TIME_HT_OFFSET) & 3) * 36000000; @@ -122,7 +122,7 @@ static void rtc_decode_time(uint32_t time, RTCDateTime *timespec) { * * @notapi */ -static void rtc_decode_date(uint32_t date, RTCDateTime *timespec) { +static void ertc_decode_date(uint32_t date, RTCDateTime *timespec) { timespec->year = (((date >> ERTC_DATE_YT_OFFSET) & 15) * 10) + ((date >> ERTC_DATE_YU_OFFSET) & 15); @@ -141,7 +141,7 @@ static void rtc_decode_date(uint32_t date, RTCDateTime *timespec) { * * @notapi */ -static uint32_t rtc_encode_time(const RTCDateTime *timespec) { +static uint32_t ertc_encode_time(const RTCDateTime *timespec) { uint32_t n, time = 0; /* Subseconds cannot be set.*/ @@ -175,7 +175,7 @@ static uint32_t rtc_encode_time(const RTCDateTime *timespec) { * * @notapi */ -static uint32_t rtc_encode_date(const RTCDateTime *timespec) { +static uint32_t ertc_encode_date(const RTCDateTime *timespec) { uint32_t n, date = 0; /* Year conversion. Note, only years last two digits are considered.*/ @@ -212,7 +212,7 @@ static size_t _getsize(void *instance) { static ps_error_t _read(void *instance, ps_offset_t offset, size_t n, uint8_t *rp) { - volatile uint32_t *bpr = &((RTCDriver *)instance)->rtc->BPR1; + volatile uint32_t *bpr = &((RTCDriver *)instance)->ertc->BPR1; unsigned i; osalDbgCheck((instance != NULL) && (rp != NULL)); @@ -231,7 +231,7 @@ static ps_error_t _read(void *instance, ps_offset_t offset, static ps_error_t _write(void *instance, ps_offset_t offset, size_t n, const uint8_t *wp) { - volatile uint32_t *bpr = &((RTCDriver *)instance)->rtc->BPR1; + volatile uint32_t *bpr = &((RTCDriver *)instance)->ertc->BPR1; unsigned i; osalDbgCheck((instance != NULL) && (wp != NULL)); @@ -252,7 +252,7 @@ static ps_error_t _write(void *instance, ps_offset_t offset, } /** - * @brief VMT for the RTC storage file interface. + * @brief VMT for the ERTC storage file interface. */ struct RTCDriverVMT _rtc_lld_vmt = { (size_t)0, @@ -267,7 +267,7 @@ struct RTCDriverVMT _rtc_lld_vmt = { #if defined(AT32_ERTC_COMMON_HANDLER) #if !defined(AT32_ERTC_SUPPRESS_COMMON_ISR) /** - * @brief RTC common interrupt handler. + * @brief ERTC common interrupt handler. * * @isr */ @@ -296,54 +296,54 @@ OSAL_IRQ_HANDLER(AT32_ERTC_COMMON_HANDLER) { #endif ); - sts = RTCD1.rtc->STS; - RTCD1.rtc->STS = sts & ~clear; + sts = RTCD1.ertc->STS; + RTCD1.ertc->STS = sts & ~clear; exintClearGroup1(EXINT_MASK1(AT32_ERTC_ALARM_EXINT) | EXINT_MASK1(AT32_ERTC_TAMP_STAMP_EXINT) | EXINT_MASK1(AT32_ERTC_WKUP_EXINT)); if (RTCD1.callback != NULL) { - uint32_t ctrl = RTCD1.rtc->CTRL; + uint32_t ctrl = RTCD1.ertc->CTRL; uint32_t tamp; #if defined(ERTC_STS_WATF) if (((ctrl & ERTC_CTRL_WATIEN) != 0U) && ((sts & ERTC_STS_WATF) != 0U)) { - RTCD1.callback(&RTCD1, RTC_EVENT_WAKEUP); + RTCD1.callback(&RTCD1, ERTC_EVENT_WAKEUP); } #endif #if defined(ERTC_STS_ALAF) if (((ctrl & ERTC_CTRL_ALAIEN) != 0U) && ((sts & ERTC_STS_ALAF) != 0U)) { - RTCD1.callback(&RTCD1, RTC_EVENT_ALARM_A); + RTCD1.callback(&RTCD1, ERTC_EVENT_ALARM_A); } #endif #if defined(ERTC_STS_ALBF) if (((ctrl & ERTC_CTRL_ALBIEN) != 0U) && ((sts & ERTC_STS_ALBF) != 0U)) { - RTCD1.callback(&RTCD1, RTC_EVENT_ALARM_B); + RTCD1.callback(&RTCD1, ERTC_EVENT_ALARM_B); } #endif if ((ctrl & ERTC_CTRL_TSIEN) != 0U) { if ((sts & ERTC_STS_TSF) != 0U) { - RTCD1.callback(&RTCD1, RTC_EVENT_TS); + RTCD1.callback(&RTCD1, ERTC_EVENT_TS); } if ((sts & ERTC_STS_TSOF) != 0U) { - RTCD1.callback(&RTCD1, RTC_EVENT_TS_OVF); + RTCD1.callback(&RTCD1, ERTC_EVENT_TS_OVF); } } #if defined(ERTC_TAMP_TP1EN) - tamp = RTCD1.rtc->TAMP; + tamp = RTCD1.ertc->TAMP; if ((tamp & ERTC_TAMP_TPIEN) != 0U) { #if defined(ERTC_STS_TP1F) if ((sts & ERTC_STS_TP1F) != 0U) { - RTCD1.callback(&RTCD1, RTC_EVENT_TAMP1); + RTCD1.callback(&RTCD1, ERTC_EVENT_TAMP1); } #endif #if defined(ERTC_STS_TP2F) if ((sts & ERTC_STS_TP2F) != 0U) { - RTCD1.callback(&RTCD1, RTC_EVENT_TAMP2); + RTCD1.callback(&RTCD1, ERTC_EVENT_TAMP2); } #endif } @@ -358,7 +358,7 @@ OSAL_IRQ_HANDLER(AT32_ERTC_COMMON_HANDLER) { defined(AT32_ERTC_WKUP_HANDLER) && \ defined(AT32_ERTC_ALARM_HANDLER) /** - * @brief RTC TAMP/STAMP interrupt handler. + * @brief ERTC TAMP/STAMP interrupt handler. * * @isr */ @@ -378,35 +378,35 @@ OSAL_IRQ_HANDLER(AT32_ERTC_TAMP_STAMP_HANDLER) { #endif ); - sts = RTCD1.rtc->STS; - RTCD1.rtc->STS = sts & ~clear; + sts = RTCD1.ertc->STS; + RTCD1.ertc->STS = sts & ~clear; exintClearGroup1(EXINT_MASK1(AT32_ERTC_TAMP_STAMP_EXINT)); if (RTCD1.callback != NULL) { uint32_t ctrl, tamp; - ctrl = RTCD1.rtc->CTRL; + ctrl = RTCD1.ertc->CTRL; if ((ctrl & ERTC_CTRL_TSIEN) != 0U) { if ((sts & ERTC_STS_TSF) != 0U) { - RTCD1.callback(&RTCD1, RTC_EVENT_TS); + RTCD1.callback(&RTCD1, ERTC_EVENT_TS); } if ((sts & ERTC_STS_TSOF) != 0U) { - RTCD1.callback(&RTCD1, RTC_EVENT_TS_OVF); + RTCD1.callback(&RTCD1, ERTC_EVENT_TS_OVF); } } #if defined(ERTC_TAMP_TP1EN) - tamp = RTCD1.rtc->TAMP; + tamp = RTCD1.ertc->TAMP; if ((tamp & ERTC_TAMP_TPIEN) != 0U) { #if defined(ERTC_STS_TP1F) if ((sts & ERTC_STS_TP1F) != 0U) { - RTCD1.callback(&RTCD1, RTC_EVENT_TAMP1); + RTCD1.callback(&RTCD1, ERTC_EVENT_TAMP1); } #endif #if defined(ERTC_STS_TP2F) if ((sts & ERTC_STS_TP2F) != 0U) { - RTCD1.callback(&RTCD1, RTC_EVENT_TAMP2); + RTCD1.callback(&RTCD1, ERTC_EVENT_TAMP2); } #endif } @@ -416,7 +416,7 @@ OSAL_IRQ_HANDLER(AT32_ERTC_TAMP_STAMP_HANDLER) { OSAL_IRQ_EPILOGUE(); } /** - * @brief RTC wakeup interrupt handler. + * @brief ERTC wakeup interrupt handler. * * @isr */ @@ -425,16 +425,16 @@ OSAL_IRQ_HANDLER(AT32_ERTC_WKUP_HANDLER) { OSAL_IRQ_PROLOGUE(); - sts = RTCD1.rtc->STS; - RTCD1.rtc->STS = sts & ~ERTC_STS_WATF; + sts = RTCD1.ertc->STS; + RTCD1.ertc->STS = sts & ~ERTC_STS_WATF; exintClearGroup1(EXINT_MASK1(AT32_ERTC_WKUP_EXINT)); if (RTCD1.callback != NULL) { - uint32_t ctrl = RTCD1.rtc->CTRL; + uint32_t ctrl = RTCD1.ertc->CTRL; if (((ctrl & ERTC_CTRL_WATIEN) != 0U) && ((sts & ERTC_STS_WATF) != 0U)) { - RTCD1.callback(&RTCD1, RTC_EVENT_WAKEUP); + RTCD1.callback(&RTCD1, ERTC_EVENT_WAKEUP); } } @@ -442,7 +442,7 @@ OSAL_IRQ_HANDLER(AT32_ERTC_WKUP_HANDLER) { } /** - * @brief RTC alarm interrupt handler. + * @brief ERTC alarm interrupt handler. * * @isr */ @@ -460,21 +460,21 @@ OSAL_IRQ_HANDLER(AT32_ERTC_ALARM_HANDLER) { #endif ); - sts = RTCD1.rtc->STS; - RTCD1.rtc->STS = sts & ~clear; + sts = RTCD1.ertc->STS; + RTCD1.ertc->STS = sts & ~clear; exintClearGroup1(EXINT_MASK1(AT32_ERTC_ALARM_EXINT)); if (RTCD1.callback != NULL) { - uint32_t ctrl = RTCD1.rtc->CTRL; + uint32_t ctrl = RTCD1.ertc->CTRL; #if defined(ERTC_STS_ALAF) if (((ctrl & ERTC_CTRL_ALAIEN) != 0U) && ((sts & ERTC_STS_ALAF) != 0U)) { - RTCD1.callback(&RTCD1, RTC_EVENT_ALARM_A); + RTCD1.callback(&RTCD1, ERTC_EVENT_ALARM_A); } #endif #if defined(ERTC_STS_ALBF) if (((ctrl & ERTC_CTRL_ALBIEN) != 0U) && ((sts & ERTC_STS_ALBF) != 0U)) { - RTCD1.callback(&RTCD1, RTC_EVENT_ALARM_B); + RTCD1.callback(&RTCD1, ERTC_EVENT_ALARM_B); } #endif } @@ -483,7 +483,7 @@ OSAL_IRQ_HANDLER(AT32_ERTC_ALARM_HANDLER) { } #else -#error "missing required RTC handlers definitions in registry" +#error "missing required ERTC handlers definitions in registry" #endif /*===========================================================================*/ @@ -497,40 +497,40 @@ OSAL_IRQ_HANDLER(AT32_ERTC_ALARM_HANDLER) { */ void rtc_lld_init(void) { - /* RTC object initialization.*/ + /* ERTC object initialization.*/ rtcObjectInit(&RTCD1); - /* RTC pointer initialization.*/ - RTCD1.rtc = ERTC; + /* ERTC pointer initialization.*/ + RTCD1.ertc = ERTC; /* Disable write protection. */ - RTCD1.rtc->WP = 0xCAU; - RTCD1.rtc->WP = 0x53U; + RTCD1.ertc->WP = 0xCAU; + RTCD1.ertc->WP = 0x53U; /* If calendar has not been initialized yet then proceed with the initial setup.*/ - if (!(RTCD1.rtc->STS & ERTC_STS_INITF)) { + if (!(RTCD1.ertc->STS & ERTC_STS_INITF)) { - rtc_enter_init(); + ertc_enter_init(); - RTCD1.rtc->CTRL = AT32_ERTC_CTRL_INIT | ERTC_CTRL_DREN; + RTCD1.ertc->CTRL = AT32_ERTC_CTRL_INIT | ERTC_CTRL_DREN; #if defined(ERTC_TAMP_TP1EN) - RTCD1.rtc->TAMP = AT32_ERTC_TAMP_INIT; + RTCD1.ertc->TAMP = AT32_ERTC_TAMP_INIT; #endif - RTCD1.rtc->STS = ERTC_STS_IMEN; /* Clearing all but ERTC_STS_IMEN. */ - RTCD1.rtc->DIV = AT32_ERTC_DIV_BITS & 0x7FFFU; - RTCD1.rtc->DIV = AT32_ERTC_DIV_BITS; + RTCD1.ertc->STS = ERTC_STS_IMEN; /* Clearing all but ERTC_STS_IMEN. */ + RTCD1.ertc->DIV = AT32_ERTC_DIV_BITS & 0x7FFFU; + RTCD1.ertc->DIV = AT32_ERTC_DIV_BITS; - rtc_exit_init(); + ertc_exit_init(); } else { - RTCD1.rtc->STS &= ~ERTC_STS_UPDF; + RTCD1.ertc->STS &= ~ERTC_STS_UPDF; } /* Callback initially disabled.*/ RTCD1.callback = NULL; - /* Enabling RTC-related EXINT lines.*/ + /* Enabling ERTC-related EXINT lines.*/ exintEnableGroup1(EXINT_MASK1(AT32_ERTC_ALARM_EXINT) | EXINT_MASK1(AT32_ERTC_TAMP_STAMP_EXINT) | EXINT_MASK1(AT32_ERTC_WKUP_EXINT), @@ -546,7 +546,7 @@ void rtc_lld_init(void) { * to set it on AT32 platform. * @note The function can be called from any context. * - * @param[in] rtcp pointer to RTC driver structure + * @param[in] rtcp pointer to ERTC driver structure * @param[in] timespec pointer to a @p RTCDateTime structure * * @notapi @@ -555,19 +555,19 @@ void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { uint32_t date, time; syssts_t sts; - time = rtc_encode_time(timespec); - date = rtc_encode_date(timespec); + time = ertc_encode_time(timespec); + date = ertc_encode_date(timespec); /* Entering a reentrant critical zone.*/ sts = osalSysGetStatusAndLockX(); /* Writing the registers.*/ - rtc_enter_init(); - rtcp->rtc->TIME = time; - rtcp->rtc->DATE = date; - rtcp->rtc->CTRL = (rtcp->rtc->CTRL & ~(1U << ERTC_CTRL_BPR_OFFSET)) | - (timespec->dstflag << ERTC_CTRL_BPR_OFFSET); - rtc_exit_init(); + ertc_enter_init(); + rtcp->ertc->TIME = time; + rtcp->ertc->DATE = date; + rtcp->ertc->CTRL = (rtcp->ertc->CTRL & ~(1U << ERTC_CTRL_BPR_OFFSET)) | + (timespec->dstflag << ERTC_CTRL_BPR_OFFSET); + ertc_exit_init(); /* Leaving a reentrant critical zone.*/ osalSysRestoreStatusX(sts); @@ -577,7 +577,7 @@ void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { * @brief Get current time. * @note The function can be called from any context. * - * @param[in] rtcp pointer to RTC driver structure + * @param[in] rtcp pointer to ERTC driver structure * @param[out] timespec pointer to a @p RTCDateTime structure * * @notapi @@ -602,9 +602,9 @@ void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { prev_sbs = sbs; prev_time = time; prev_date = date; - sbs = rtcp->rtc->SBS; - time = rtcp->rtc->TIME; - date = rtcp->rtc->DATE; + sbs = rtcp->ertc->SBS; + time = rtcp->ertc->TIME; + date = rtcp->ertc->DATE; } while ((sbs != prev_sbs) || (time != prev_time) || (date != prev_date)); #else /* !AT32_ERTC_HAS_SUBSECONDS */ time = 0U; @@ -612,22 +612,22 @@ void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { do { prev_time = time; prev_date = date; - time = rtcp->rtc->TIME; - date = rtcp->rtc->DATE; + time = rtcp->ertc->TIME; + date = rtcp->ertc->DATE; } while ((time != prev_time) || (date != prev_date)); #endif /* !AT32_ERTC_HAS_SUBSECONDS */ /* DST bit is in CTRL, no need to poll on this one.*/ - ctrl = rtcp->rtc->CTRL; + ctrl = rtcp->ertc->CTRL; /* Leaving a reentrant critical zone.*/ osalSysRestoreStatusX(sts); /* Decoding day time, this starts the atomic read sequence, see "Reading - the calendar" in the RTC documentation.*/ - rtc_decode_time(time, timespec); + the calendar" in the ERTC documentation.*/ + ertc_decode_time(time, timespec); - /* If the RTC is capable of sub-second counting then the value is + /* If the ERTC is capable of sub-second counting then the value is normalized in milliseconds and added to the time.*/ #if AT32_ERTC_HAS_SUBSECONDS subs = (((AT32_ERTC_DIVB_VALUE - 1U) - sbs) * 1000U) / AT32_ERTC_DIVB_VALUE; @@ -637,7 +637,7 @@ void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { timespec->millisecond += subs; /* Decoding date, this concludes the atomic read sequence.*/ - rtc_decode_date(date, timespec); + ertc_decode_date(date, timespec); /* Retrieving the DST bit.*/ timespec->dstflag = (ctrl >> ERTC_CTRL_BPR_OFFSET) & 1; @@ -650,7 +650,7 @@ void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { * @note Function does not performs any checks of alarm time validity. * @note The function can be called from any context. * - * @param[in] rtcp pointer to RTC driver structure. + * @param[in] rtcp pointer to ERTC driver structure. * @param[in] alarm alarm identifier. Can be 0 or 1. * @param[in] alarmspec pointer to a @p RTCAlarm structure. * @@ -666,31 +666,31 @@ void rtc_lld_set_alarm(RTCDriver *rtcp, if (alarm == 0) { if (alarmspec != NULL) { - rtcp->rtc->CTRL &= ~ERTC_CTRL_ALAEN; - while (!(rtcp->rtc->STS & ERTC_STS_ALAWF)) + rtcp->ertc->CTRL &= ~ERTC_CTRL_ALAEN; + while (!(rtcp->ertc->STS & ERTC_STS_ALAWF)) ; - rtcp->rtc->ALA = alarmspec->alrmr; - rtcp->rtc->CTRL |= ERTC_CTRL_ALAEN; - rtcp->rtc->CTRL |= ERTC_CTRL_ALAIEN; + rtcp->ertc->ALA = alarmspec->alrmr; + rtcp->ertc->CTRL |= ERTC_CTRL_ALAEN; + rtcp->ertc->CTRL |= ERTC_CTRL_ALAIEN; } else { - rtcp->rtc->CTRL &= ~ERTC_CTRL_ALAIEN; - rtcp->rtc->CTRL &= ~ERTC_CTRL_ALAEN; + rtcp->ertc->CTRL &= ~ERTC_CTRL_ALAIEN; + rtcp->ertc->CTRL &= ~ERTC_CTRL_ALAEN; } } #if RTC_ALARMS > 1 else { if (alarmspec != NULL) { - rtcp->rtc->CTRL &= ~ERTC_CTRL_ALBEN; - while (!(rtcp->rtc->STS & ERTC_STS_ALBWF)) + rtcp->ertc->CTRL &= ~ERTC_CTRL_ALBEN; + while (!(rtcp->ertc->STS & ERTC_STS_ALBWF)) ; - rtcp->rtc->ALB = alarmspec->alrmr; - rtcp->rtc->CTRL |= ERTC_CTRL_ALBEN; - rtcp->rtc->CTRL |= ERTC_CTRL_ALBIEN; + rtcp->ertc->ALB = alarmspec->alrmr; + rtcp->ertc->CTRL |= ERTC_CTRL_ALBEN; + rtcp->ertc->CTRL |= ERTC_CTRL_ALBIEN; } else { - rtcp->rtc->CTRL &= ~ERTC_CTRL_ALBIEN; - rtcp->rtc->CTRL &= ~ERTC_CTRL_ALBEN; + rtcp->ertc->CTRL &= ~ERTC_CTRL_ALBIEN; + rtcp->ertc->CTRL &= ~ERTC_CTRL_ALBEN; } } #endif /* RTC_ALARMS > 1 */ @@ -703,7 +703,7 @@ void rtc_lld_set_alarm(RTCDriver *rtcp, * @brief Get alarm time. * @note The function can be called from any context. * - * @param[in] rtcp pointer to RTC driver structure + * @param[in] rtcp pointer to ERTC driver structure * @param[in] alarm alarm identifier. Can be 0 or 1. * @param[out] alarmspec pointer to a @p RTCAlarm structure * @@ -714,21 +714,21 @@ void rtc_lld_get_alarm(RTCDriver *rtcp, RTCAlarm *alarmspec) { if (alarm == 0) - alarmspec->alrmr = rtcp->rtc->ALA; + alarmspec->alrmr = rtcp->ertc->ALA; #if RTC_ALARMS > 1 else - alarmspec->alrmr = rtcp->rtc->ALB; + alarmspec->alrmr = rtcp->ertc->ALB; #endif /* RTC_ALARMS > 1 */ } #endif /* RTC_ALARMS > 0 */ /** - * @brief Enables or disables RTC callbacks. + * @brief Enables or disables ERTC callbacks. * @details This function enables or disables callbacks, use a @p NULL pointer * in order to disable a callback. * @note The function can be called from any context. * - * @param[in] rtcp pointer to RTC driver structure + * @param[in] rtcp pointer to ERTC driver structure * @param[in] callback callback function pointer or @p NULL * * @notapi @@ -744,12 +744,12 @@ void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { * @note Default value after BPR domain reset is 0x0000FFFF * @note The function can be called from any context. * - * @param[in] rtcp pointer to RTC driver structure - * @param[in] wakeupspec pointer to a @p RTCWakeup structure + * @param[in] rtcp pointer to ERTC driver structure + * @param[in] wakeupspec pointer to a @p ERTCWakeup structure * * @api */ -void ertcAT32SetPeriodicWakeup(RTCDriver *rtcp, const RTCWakeup *wakeupspec) { +void ertcAT32SetPeriodicWakeup(RTCDriver *rtcp, const ERTCWakeup *wakeupspec) { syssts_t sts; /* Entering a reentrant critical zone.*/ @@ -758,19 +758,19 @@ void ertcAT32SetPeriodicWakeup(RTCDriver *rtcp, const RTCWakeup *wakeupspec) { if (wakeupspec != NULL) { osalDbgCheck(wakeupspec->wat != 0x30000); - rtcp->rtc->CTRL &= ~ERTC_CTRL_WATEN; - rtcp->rtc->CTRL &= ~ERTC_CTRL_WATIEN; - while (!(rtcp->rtc->STS & ERTC_STS_WATWF)) + rtcp->ertc->CTRL &= ~ERTC_CTRL_WATEN; + rtcp->ertc->CTRL &= ~ERTC_CTRL_WATIEN; + while (!(rtcp->ertc->STS & ERTC_STS_WATWF)) ; - rtcp->rtc->WAT = wakeupspec->wat & 0xFFFF; - rtcp->rtc->CTRL &= ~ERTC_CTRL_WATCLK; - rtcp->rtc->CTRL |= (wakeupspec->wat >> 16) & ERTC_CTRL_WATCLK; - rtcp->rtc->CTRL |= ERTC_CTRL_WATIEN; - rtcp->rtc->CTRL |= ERTC_CTRL_WATEN; + rtcp->ertc->WAT = wakeupspec->wat & 0xFFFF; + rtcp->ertc->CTRL &= ~ERTC_CTRL_WATCLK; + rtcp->ertc->CTRL |= (wakeupspec->wat >> 16) & ERTC_CTRL_WATCLK; + rtcp->ertc->CTRL |= ERTC_CTRL_WATIEN; + rtcp->ertc->CTRL |= ERTC_CTRL_WATEN; } else { - rtcp->rtc->CTRL &= ~ERTC_CTRL_WATEN; - rtcp->rtc->CTRL &= ~ERTC_CTRL_WATIEN; + rtcp->ertc->CTRL &= ~ERTC_CTRL_WATEN; + rtcp->ertc->CTRL &= ~ERTC_CTRL_WATIEN; } /* Leaving a reentrant critical zone.*/ @@ -782,20 +782,20 @@ void ertcAT32SetPeriodicWakeup(RTCDriver *rtcp, const RTCWakeup *wakeupspec) { * @note Default value after BPR domain reset is 0x0000FFFF * @note The function can be called from any context. * - * @param[in] rtcp pointer to RTC driver structure - * @param[out] wakeupspec pointer to a @p RTCWakeup structure + * @param[in] rtcp pointer to ERTC driver structure + * @param[out] wakeupspec pointer to a @p ERTCWakeup structure * * @api */ -void ertcAT32GetPeriodicWakeup(RTCDriver *rtcp, RTCWakeup *wakeupspec) { +void ertcAT32GetPeriodicWakeup(RTCDriver *rtcp, ERTCWakeup *wakeupspec) { syssts_t sts; /* Entering a reentrant critical zone.*/ sts = osalSysGetStatusAndLockX(); wakeupspec->wat = 0; - wakeupspec->wat |= rtcp->rtc->WAT; - wakeupspec->wat |= (((uint32_t)rtcp->rtc->CTRL) & 0x7) << 16; + wakeupspec->wat |= rtcp->ertc->WAT; + wakeupspec->wat |= (((uint32_t)rtcp->ertc->CTRL) & 0x7) << 16; /* Leaving a reentrant critical zone.*/ osalSysRestoreStatusX(sts); diff --git a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h index f7bcdda1cd..59ed2c6d8b 100644 --- a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h +++ b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h @@ -23,7 +23,7 @@ /** * @file RTCv2/hal_rtc_lld.h - * @brief AT32 RTC low level driver header. + * @brief AT32 ERTC low level driver header. * * @addtogroup RTC * @{ @@ -59,27 +59,27 @@ /** @} */ /** - * @brief RTC DIV register initializer. + * @brief ERTC DIV register initializer. */ -#define RTC_DIV(a, s) ((((a) - 1) << 16) | ((s) - 1)) +#define ERTC_DIV(a, s) ((((a) - 1) << 16) | ((s) - 1)) /** * @name Alarm helper macros * @{ */ -#define RTC_ALRM_MASK4 (1U << 31) -#define RTC_ALRM_WKSEL (1U << 30) -#define RTC_ALRM_DT(n) ((n) << 28) -#define RTC_ALRM_DU(n) ((n) << 24) -#define RTC_ALRM_MASK3 (1U << 23) -#define RTC_ALRM_HT(n) ((n) << 20) -#define RTC_ALRM_HU(n) ((n) << 16) -#define RTC_ALRM_MASK2 (1U << 15) -#define RTC_ALRM_MT(n) ((n) << 12) -#define RTC_ALRM_MU(n) ((n) << 8) -#define RTC_ALRM_MASK1 (1U << 7) -#define RTC_ALRM_ST(n) ((n) << 4) -#define RTC_ALRM_SU(n) ((n) << 0) +#define ERTC_ALRM_MASK4 (1U << 31) +#define ERTC_ALRM_WKSEL (1U << 30) +#define ERTC_ALRM_DT(n) ((n) << 28) +#define ERTC_ALRM_DU(n) ((n) << 24) +#define ERTC_ALRM_MASK3 (1U << 23) +#define ERTC_ALRM_HT(n) ((n) << 20) +#define ERTC_ALRM_HU(n) ((n) << 16) +#define ERTC_ALRM_MASK2 (1U << 15) +#define ERTC_ALRM_MT(n) ((n) << 12) +#define ERTC_ALRM_MU(n) ((n) << 8) +#define ERTC_ALRM_MASK1 (1U << 7) +#define ERTC_ALRM_ST(n) ((n) << 4) +#define ERTC_ALRM_SU(n) ((n) << 0) /** @} */ /* Requires services from the EXINT driver.*/ @@ -96,7 +96,7 @@ * @{ */ /** - * @brief RTC DIVA register initialization. + * @brief ERTC DIVA register initialization. * @note The default is calculated for a 32768Hz clock. */ #if !defined(AT32_ERTC_DIVA_VALUE) || defined(__DOXYGEN__) @@ -104,7 +104,7 @@ #endif /** - * @brief RTC DIVB divider initialization. + * @brief ERTC DIVB divider initialization. * @note The default is calculated for a 32768Hz clock. */ #if !defined(AT32_ERTC_DIVB_VALUE) || defined(__DOXYGEN__) @@ -112,18 +112,18 @@ #endif /** - * @brief RTC CTRL register initialization value. + * @brief ERTC CTRL register initialization value. * @note Use this value to initialize features not directly handled by - * the RTC driver. + * the ERTC driver. */ #if !defined(AT32_ERTC_CTRL_INIT) || defined(__DOXYGEN__) #define AT32_ERTC_CTRL_INIT 0 #endif /** - * @brief RTC TAMP register initialization value. + * @brief ERTC TAMP register initialization value. * @note Use this value to initialize features not directly handled by - * the RTC driver. + * the ERTC driver. * @note On some devices this values goes in the similar TAMP register. */ #if !defined(AT32_ERTC_TAMP_INIT) || defined(__DOXYGEN__) @@ -136,11 +136,11 @@ /*===========================================================================*/ #if HAL_USE_RTC && !AT32_HAS_ERTC -#error "RTC not present in the selected device" +#error "ERTC not present in the selected device" #endif #if !defined(AT32_ERTCCLK) -#error "RTC clock not exported by HAL layer" +#error "ERTC clock not exported by HAL layer" #endif #if AT32_PCLK1 < (AT32_ERTCCLK * 7) @@ -148,66 +148,65 @@ #endif /** - * @brief Initialization for the RTC_DIV register. + * @brief Initialization for the ERTC_DIV register. */ -#define AT32_ERTC_DIV_BITS RTC_DIV(AT32_ERTC_DIVA_VALUE, \ - AT32_ERTC_DIVB_VALUE) +#define AT32_ERTC_DIV_BITS ERTC_DIV(AT32_ERTC_DIVA_VALUE, \ + AT32_ERTC_DIVB_VALUE) /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ /** - * @brief Type of an RTC event. + * @brief Type of an ERTC event. */ typedef enum { - RTC_EVENT_ALARM_A = 0, /** Alarm A. */ - RTC_EVENT_ALARM_B = 1, /** Alarm B. */ - RTC_EVENT_TS = 2, /** Time stamp. */ - RTC_EVENT_TS_OVF = 3, /** Time stamp overflow. */ - RTC_EVENT_TAMP1 = 4, /** Tamper 1. */ - RTC_EVENT_TAMP2 = 5, /** Tamper 2- */ - RTC_EVENT_TAMP3 = 6, /** Tamper 3. */ - RTC_EVENT_WAKEUP = 7 /** Wakeup. */ - } rtcevent_t; + ERTC_EVENT_ALARM_A = 0, /** Alarm A. */ + ERTC_EVENT_ALARM_B = 1, /** Alarm B. */ + ERTC_EVENT_TS = 2, /** Time stamp. */ + ERTC_EVENT_TS_OVF = 3, /** Time stamp overflow. */ + ERTC_EVENT_TAMP1 = 4, /** Tamper 1. */ + ERTC_EVENT_TAMP2 = 5, /** Tamper 2. */ + ERTC_EVENT_WAKEUP = 6 /** Wakeup. */ + } ertcevent_t; /** - * @brief Type of a generic RTC callback. + * @brief Type of a generic ERTC callback. */ -typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); +typedef void (*rtccb_t)(RTCDriver *rtcp, ertcevent_t event); /** - * @brief Type of a structure representing an RTC alarm time stamp. + * @brief Type of a structure representing an ERTC alarm time stamp. */ -typedef struct hal_rtc_alarm { +typedef struct hal_ertc_alarm { /** - * @brief Type of an alarm as encoded in RTC ALx registers. + * @brief Type of an alarm as encoded in ERTC ALx registers. */ uint32_t alrmr; } RTCAlarm; #if AT32_ERTC_HAS_PERIODIC_WAKEUPS /** - * @brief Type of a wakeup as encoded in RTC WAT register. + * @brief Type of a wakeup as encoded in ERTC WAT register. */ -typedef struct hal_rtc_wakeup { +typedef struct hal_ertc_wakeup { /** - * @brief Wakeup as encoded in RTC WAT register. + * @brief Wakeup as encoded in ERTC WAT register. * @note ((WAT == 0) || (WATCLK == 3)) are a forbidden combination. * @note Bits 16..18 are copied in the CTRL bits 0..2 (WATCLK). */ uint32_t wat; -} RTCWakeup; +} ERTCWakeup; #endif /** * @brief Implementation-specific @p RTCDriver fields. */ #define rtc_lld_driver_fields \ - /* Pointer to the RTC registers block.*/ \ - ERTC_TypeDef *rtc; \ + /* Pointer to the ERTC registers block.*/ \ + ERTC_TypeDef *ertc; \ /* Callback pointer.*/ \ - rtccb_t callback + rtccb_t callback /*===========================================================================*/ /* Driver macros. */ @@ -235,8 +234,8 @@ extern "C" { RTCAlarm *alarmspec); #endif #if AT32_ERTC_HAS_PERIODIC_WAKEUPS - void ertcAT32SetPeriodicWakeup(RTCDriver *rtcp, const RTCWakeup *wakeupspec); - void ertcAT32GetPeriodicWakeup(RTCDriver *rtcp, RTCWakeup *wakeupspec); + void ertcAT32SetPeriodicWakeup(RTCDriver *rtcp, const ERTCWakeup *wakeupspec); + void ertcAT32GetPeriodicWakeup(RTCDriver *rtcp, ERTCWakeup *wakeupspec); #endif /* AT32_ERTC_HAS_PERIODIC_WAKEUPS */ #ifdef __cplusplus } diff --git a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c index 79181e464d..3fe9c48e5e 100644 --- a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c +++ b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c @@ -18,7 +18,7 @@ /** * @file xWDGv1/hal_wdg_lld.c - * @brief WDG Driver subsystem low level driver source. + * @brief WDT Driver subsystem low level driver source. * * @addtogroup WDG * @{ @@ -37,8 +37,8 @@ #define CMD_CMD_WRITE 0x5555U #define CMD_CMD_PROTECT 0x0000U -#if !defined(WDG) && defined(WDG1) -#define WDG WDG1 +#if !defined(WDT) && defined(WDT1) +#define WDT WDT1 #endif /*===========================================================================*/ @@ -66,7 +66,7 @@ WDGDriver WDGD1; /*===========================================================================*/ /** - * @brief Low level WDG driver initialization. + * @brief Low level WDT driver initialization. * * @notapi */ @@ -74,12 +74,12 @@ void wdg_lld_init(void) { #if AT32_WDG_USE_WDT WDGD1.state = WDG_STOP; - WDGD1.wdg = WDT; + WDGD1.wdt = WDT; #endif } /** - * @brief Configures and activates the WDG peripheral. + * @brief Configures and activates the WDT peripheral. * * @param[in] wdgp pointer to the @p WDGDriver object * @@ -87,23 +87,23 @@ void wdg_lld_init(void) { */ void wdg_lld_start(WDGDriver *wdgp) { - /* Enable WDG and unlock for write.*/ - wdgp->wdg->CMD = CMD_CMD_ENABLE; - wdgp->wdg->CMD = CMD_CMD_WRITE; + /* Enable WDT and unlock for write.*/ + wdgp->wdt->CMD = CMD_CMD_ENABLE; + wdgp->wdt->CMD = CMD_CMD_WRITE; /* Write configuration.*/ - wdgp->wdg->DIV = wdgp->config->div; - wdgp->wdg->RLD = wdgp->config->rld; + wdgp->wdt->DIV = wdgp->config->div; + wdgp->wdt->RLD = wdgp->config->rld; /* Wait the registers to be updated.*/ - while (wdgp->wdg->STS != 0) + while (wdgp->wdt->STS != 0) ; - wdgp->wdg->CMD = CMD_CMD_RELOAD; + wdgp->wdt->CMD = CMD_CMD_RELOAD; } /** - * @brief Deactivates the WDG peripheral. + * @brief Deactivates the WDT peripheral. * * @param[in] wdgp pointer to the @p WDGDriver object * @@ -112,11 +112,11 @@ void wdg_lld_start(WDGDriver *wdgp) { void wdg_lld_stop(WDGDriver *wdgp) { osalDbgAssert(wdgp->state == WDG_STOP, - "WDG cannot be stopped once activated"); + "WDT cannot be stopped once activated"); } /** - * @brief Reloads WDG's counter. + * @brief Reloads WDT's counter. * * @param[in] wdgp pointer to the @p WDGDriver object * @@ -124,7 +124,7 @@ void wdg_lld_stop(WDGDriver *wdgp) { */ void wdg_lld_reset(WDGDriver * wdgp) { - wdgp->wdg->CMD = CMD_CMD_RELOAD; + wdgp->wdt->CMD = CMD_CMD_RELOAD; } #endif /* HAL_USE_WDG == TRUE */ diff --git a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h index ffd40da695..da2391c447 100644 --- a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h +++ b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h @@ -18,7 +18,7 @@ /** * @file xWDGv1/hal_wdg_lld.h - * @brief WDG Driver subsystem low level driver header. + * @brief WDT Driver subsystem low level driver header. * * @addtogroup WDG * @{ @@ -64,8 +64,8 @@ * @{ */ /** - * @brief WDG driver enable switch. - * @details If set to @p TRUE the support for WDG is included. + * @brief WDT driver enable switch. + * @details If set to @p TRUE the support for WDT is included. * @note The default is @p FALSE. */ #if !defined(AT32_WDG_USE_WDT) || defined(__DOXYGEN__) @@ -78,11 +78,11 @@ /*===========================================================================*/ #if AT32_WDG_USE_WDT && !AT32_HAS_WDT -#error "WDG not present in the selected device" +#error "WDT not present in the selected device" #endif #if !AT32_WDG_USE_WDT -#error "WDG driver activated but no xWDG peripheral assigned" +#error "WDT driver activated but no xWDG peripheral assigned" #endif #if !defined(AT32_LICK_ENABLED) @@ -90,7 +90,7 @@ #endif #if (AT32_WDG_USE_WDT == TRUE) && (AT32_LICK_ENABLED == FALSE) -#error "WDG requires LICK clock" +#error "WDT requires LICK clock" #endif /*===========================================================================*/ @@ -98,7 +98,7 @@ /*===========================================================================*/ /** - * @brief Type of a structure representing an WDG driver. + * @brief Type of a structure representing an WDT driver. */ typedef struct WDGDriver WDGDriver; @@ -133,9 +133,9 @@ struct WDGDriver { const WDGConfig *config; /* End of the mandatory fields.*/ /** - * @brief Pointer to the WDG registers block. + * @brief Pointer to the WDT registers block. */ - WDT_TypeDef *wdg; + WDT_TypeDef *wdt; }; /*===========================================================================*/ From 163d7cee01a68feeb9e347f394b685d34bfda9a2 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Sat, 3 Aug 2024 14:50:30 +0700 Subject: [PATCH 09/18] Update demo test --- demos/AT32/RT-AT-START-F415/Makefile | 9 +++++-- demos/AT32/RT-AT-START-F415/cfg/chconf.h | 12 ++++----- demos/AT32/RT-AT-START-F415/cfg/config.h | 30 +++++++++++++++++++++++ demos/AT32/RT-AT-START-F415/cfg/mcuconf.h | 8 +++++- 4 files changed, 50 insertions(+), 9 deletions(-) create mode 100644 demos/AT32/RT-AT-START-F415/cfg/config.h diff --git a/demos/AT32/RT-AT-START-F415/Makefile b/demos/AT32/RT-AT-START-F415/Makefile index 9ca5d645d7..289af6d294 100644 --- a/demos/AT32/RT-AT-START-F415/Makefile +++ b/demos/AT32/RT-AT-START-F415/Makefile @@ -10,7 +10,7 @@ endif # C specific options here (added to USE_OPT). ifeq ($(USE_COPT),) - USE_COPT = + USE_COPT = endif # C++ specific options here (added to USE_OPT). @@ -25,7 +25,7 @@ endif # Linker extra options here. ifeq ($(USE_LDOPT),) - USE_LDOPT = + USE_LDOPT = endif # Enable this if you want link time optimizations (LTO). @@ -44,6 +44,11 @@ ifeq ($(USE_SMART_BUILD),) USE_SMART_BUILD = yes endif +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + # # Build global options ############################################################################## diff --git a/demos/AT32/RT-AT-START-F415/cfg/chconf.h b/demos/AT32/RT-AT-START-F415/cfg/chconf.h index 42828da814..46b3f78b68 100644 --- a/demos/AT32/RT-AT-START-F415/cfg/chconf.h +++ b/demos/AT32/RT-AT-START-F415/cfg/chconf.h @@ -588,7 +588,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#define CH_DBG_SYSTEM_STATE_CHECK TRUE #endif /** @@ -599,7 +599,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS FALSE +#define CH_DBG_ENABLE_CHECKS TRUE #endif /** @@ -611,7 +611,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS FALSE +#define CH_DBG_ENABLE_ASSERTS TRUE #endif /** @@ -621,7 +621,7 @@ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. */ #if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL #endif /** @@ -644,7 +644,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK TRUE #endif /** @@ -656,7 +656,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS TRUE #endif /** diff --git a/demos/AT32/RT-AT-START-F415/cfg/config.h b/demos/AT32/RT-AT-START-F415/cfg/config.h new file mode 100644 index 0000000000..4fbd7cc3df --- /dev/null +++ b/demos/AT32/RT-AT-START-F415/cfg/config.h @@ -0,0 +1,30 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h b/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h index 8b6899806d..4941f5a669 100644 --- a/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h +++ b/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h @@ -35,10 +35,16 @@ #define AT32F415_MCUCONF +#include "config.h" + /* - * HAL driver system settings. + * General settings. */ #define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ #define AT32_HICK_ENABLED TRUE #define AT32_LICK_ENABLED FALSE #define AT32_HEXT_ENABLED TRUE From f0adeb58ba520baaf413289661cd528071b9a91f Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Sat, 3 Aug 2024 22:13:31 +0700 Subject: [PATCH 10/18] Added HAL driver test for ERTC, I2C bitbang and hardware --- testhal/AT32/multi/ERTC/.cproject | 56 ++ testhal/AT32/multi/ERTC/.project | 78 ++ testhal/AT32/multi/ERTC/Makefile | 18 + .../multi/ERTC/cfg/at-start-f415/chconf.h | 842 ++++++++++++++++++ .../multi/ERTC/cfg/at-start-f415/config.h | 30 + .../multi/ERTC/cfg/at-start-f415/halconf.h | 555 ++++++++++++ .../multi/ERTC/cfg/at-start-f415/mcuconf.h | 228 +++++ .../multi/ERTC/cfg/at-start-f415/portab.c | 59 ++ .../multi/ERTC/cfg/at-start-f415/portab.h | 78 ++ testhal/AT32/multi/ERTC/main.c | 187 ++++ .../AT32/multi/ERTC/make/at-start-f415.make | 198 ++++ testhal/AT32/multi/I2C_HW/.cproject | 56 ++ testhal/AT32/multi/I2C_HW/.project | 78 ++ testhal/AT32/multi/I2C_HW/Makefile | 18 + .../multi/I2C_HW/cfg/at-start-f415/chconf.h | 842 ++++++++++++++++++ .../multi/I2C_HW/cfg/at-start-f415/config.h | 30 + .../multi/I2C_HW/cfg/at-start-f415/halconf.h | 555 ++++++++++++ .../multi/I2C_HW/cfg/at-start-f415/mcuconf.h | 228 +++++ .../multi/I2C_HW/cfg/at-start-f415/portab.c | 69 ++ .../multi/I2C_HW/cfg/at-start-f415/portab.h | 78 ++ testhal/AT32/multi/I2C_HW/main.c | 93 ++ .../AT32/multi/I2C_HW/make/at-start-f415.make | 196 ++++ testhal/AT32/multi/I2C_SW/.cproject | 56 ++ testhal/AT32/multi/I2C_SW/.project | 78 ++ testhal/AT32/multi/I2C_SW/Makefile | 18 + .../multi/I2C_SW/cfg/at-start-f415/chconf.h | 842 ++++++++++++++++++ .../multi/I2C_SW/cfg/at-start-f415/config.h | 30 + .../multi/I2C_SW/cfg/at-start-f415/halconf.h | 555 ++++++++++++ .../multi/I2C_SW/cfg/at-start-f415/mcuconf.h | 228 +++++ .../multi/I2C_SW/cfg/at-start-f415/portab.c | 75 ++ .../multi/I2C_SW/cfg/at-start-f415/portab.h | 82 ++ testhal/AT32/multi/I2C_SW/main.c | 93 ++ .../AT32/multi/I2C_SW/make/at-start-f415.make | 196 ++++ 33 files changed, 6825 insertions(+) create mode 100644 testhal/AT32/multi/ERTC/.cproject create mode 100644 testhal/AT32/multi/ERTC/.project create mode 100644 testhal/AT32/multi/ERTC/Makefile create mode 100644 testhal/AT32/multi/ERTC/cfg/at-start-f415/chconf.h create mode 100644 testhal/AT32/multi/ERTC/cfg/at-start-f415/config.h create mode 100644 testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf.h create mode 100644 testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h create mode 100644 testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.c create mode 100644 testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.h create mode 100644 testhal/AT32/multi/ERTC/main.c create mode 100644 testhal/AT32/multi/ERTC/make/at-start-f415.make create mode 100644 testhal/AT32/multi/I2C_HW/.cproject create mode 100644 testhal/AT32/multi/I2C_HW/.project create mode 100644 testhal/AT32/multi/I2C_HW/Makefile create mode 100644 testhal/AT32/multi/I2C_HW/cfg/at-start-f415/chconf.h create mode 100644 testhal/AT32/multi/I2C_HW/cfg/at-start-f415/config.h create mode 100644 testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf.h create mode 100644 testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h create mode 100644 testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.c create mode 100644 testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.h create mode 100644 testhal/AT32/multi/I2C_HW/main.c create mode 100644 testhal/AT32/multi/I2C_HW/make/at-start-f415.make create mode 100644 testhal/AT32/multi/I2C_SW/.cproject create mode 100644 testhal/AT32/multi/I2C_SW/.project create mode 100644 testhal/AT32/multi/I2C_SW/Makefile create mode 100644 testhal/AT32/multi/I2C_SW/cfg/at-start-f415/chconf.h create mode 100644 testhal/AT32/multi/I2C_SW/cfg/at-start-f415/config.h create mode 100644 testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf.h create mode 100644 testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h create mode 100644 testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.c create mode 100644 testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.h create mode 100644 testhal/AT32/multi/I2C_SW/main.c create mode 100644 testhal/AT32/multi/I2C_SW/make/at-start-f415.make diff --git a/testhal/AT32/multi/ERTC/.cproject b/testhal/AT32/multi/ERTC/.cproject new file mode 100644 index 0000000000..74701160a0 --- /dev/null +++ b/testhal/AT32/multi/ERTC/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/multi/ERTC/.project b/testhal/AT32/multi/ERTC/.project new file mode 100644 index 0000000000..67fcfbb74b --- /dev/null +++ b/testhal/AT32/multi/ERTC/.project @@ -0,0 +1,78 @@ + + + AT32-ERTC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/testhal/AT32/multi/ERTC/Makefile b/testhal/AT32/multi/ERTC/Makefile new file mode 100644 index 0000000000..c8606df05e --- /dev/null +++ b/testhal/AT32/multi/ERTC/Makefile @@ -0,0 +1,18 @@ +############################################################################## +# Multi-project makefile rules +# + +all: + @echo + @echo === Building for AT-START-F415 ===================================== + +@make --no-print-directory -f ./make/at-start-f415.make all + @echo ==================================================================== + @echo + +clean: + @echo + +@make --no-print-directory -f ./make/at-start-f415.make clean + @echo + +# +############################################################################## diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/chconf.h new file mode 100644 index 0000000000..46b3f78b68 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/config.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/config.h new file mode 100644 index 0000000000..4fbd7cc3df --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/config.h @@ -0,0 +1,30 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf.h new file mode 100644 index 0000000000..ec123afa7b --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h new file mode 100644 index 0000000000..3c30d3621c --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h @@ -0,0 +1,228 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F415_MCUCONF + +#include "config.h" + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED TRUE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_LICK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 TRUE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.c b/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.c new file mode 100644 index 0000000000..25e871321a --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.c @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.h new file mode 100644 index 0000000000..022c388716 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_RTC1 RTCD1 + +#define PORTAB_SD1 SD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/main.c b/testhal/AT32/multi/ERTC/main.c new file mode 100644 index 0000000000..36a683a0a4 --- /dev/null +++ b/testhal/AT32/multi/ERTC/main.c @@ -0,0 +1,187 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#include "shell.h" +#include "chprintf.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) + +static void cmd_date(BaseSequentialStream *chp, int argc, char *argv[]) { + RTCDateTime timespec; + + (void)argv; + + if (argc > 0) { + chprintf(chp, "Usage: date\r\n"); + return; + } + + rtcGetTime(&PORTAB_RTC1, ×pec); + chprintf(chp, "%02d:%02d:%02d:%03d - %02d-%02d-%04d\r\n", + timespec.millisecond / 3600000U, + (timespec.millisecond % 3600000U) / 60000U, + (timespec.millisecond % 60000U) / 1000U, + timespec.millisecond % 1000U, + timespec.month, + timespec.day, + timespec.year + 1980U); +} + +#if RTC_HAS_STORAGE +static void cmd_storage(BaseSequentialStream *chp, int argc, char *argv[]) { + size_t storage_size = psGetStorageSize(&PORTAB_RTC1); + ps_offset_t i; + + (void)argv; + + if (argc > 0) { + chprintf(chp, "Usage: storage\r\n"); + return; + } + + for (i = 0U; i < (ps_offset_t)storage_size; i++) { + uint8_t val; + psRead(&PORTAB_RTC1, i, 1U, &val); + chprintf(chp, "%02x ", val); + if (((i + 1) & 15) == 0U) { + chprintf(chp, "\r\n"); + } + } +} +#endif + +static const ShellCommand commands[] = { + {"date", cmd_date}, +#if RTC_HAS_STORAGE + {"storage", cmd_storage}, +#endif + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&PORTAB_SD1, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +static sysinterval_t interval = TIME_MS2I(500); + +/* + * LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + palToggleLine(PORTAB_BLINK_LED1); + palToggleLine(PORTAB_BLINK_LED2); + palToggleLine(PORTAB_BLINK_LED3); + chThdSleep(interval); + palToggleLine(PORTAB_BLINK_LED1); + palToggleLine(PORTAB_BLINK_LED2); + palToggleLine(PORTAB_BLINK_LED3); + chThdSleep(interval); + } +} + +/* + * ERTC callback. + */ +static void alarmcb(RTCDriver *rtcp, ertcevent_t event) { + + (void)rtcp; + + if (event == ERTC_EVENT_ALARM_A) { + interval = TIME_MS2I(500); + } + else if (event == ERTC_EVENT_ALARM_B) { + interval = TIME_MS2I(50); + } +} + +/* + * Application entry point. + */ +int main(void) { + static const RTCAlarm alarm1 = { + ERTC_ALRM_MASK4 | /* No month/week day match. */ + ERTC_ALRM_MASK3 | /* No hour match. */ + ERTC_ALRM_MASK2 | /* No minutes match. */ + ERTC_ALRM_ST(0) | + ERTC_ALRM_SU(0) /* Match minute start. */ + }; + static const RTCAlarm alarm2 = { + ERTC_ALRM_MASK4 | /* No month/week day match. */ + ERTC_ALRM_MASK3 | /* No hour match. */ + ERTC_ALRM_MASK2 | /* No minutes match. */ + ERTC_ALRM_ST(3) | + ERTC_ALRM_SU(0) /* Match minute half. */ + }; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* Board-dependent GPIO setup code.*/ + portab_setup(); + + /* Starting a serial port for shell.*/ + sdStart(&PORTAB_SD1, NULL); + + /* Shell manager initialization.*/ + shellInit(); + + /* Creates the blinker thread.*/ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + rtcSetAlarm(&PORTAB_RTC1, 0, &alarm1); + rtcSetAlarm(&PORTAB_RTC1, 1, &alarm2); + rtcSetCallback(&PORTAB_RTC1, alarmcb); +#if RTC_HAS_STORAGE + psWrite(&PORTAB_RTC1, 0U, 12U, (const uint8_t *)"Hello World!"); +#endif + + /* Normal main() thread activity, spawning shells.*/ + while (true) { + thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, + "shell", NORMALPRIO + 1, + shellThread, (void *)&shell_cfg1); + chThdWait(shelltp); /* Waiting termination. */ + chThdSleepMilliseconds(1000); + } +} diff --git a/testhal/AT32/multi/ERTC/make/at-start-f415.make b/testhal/AT32/multi/ERTC/make/at-start-f415.make new file mode 100644 index 0000000000..8e280f39d9 --- /dev/null +++ b/testhal/AT32/multi/ERTC/make/at-start-f415.make @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f415 +BUILDDIR := ./build/at-start-f415 +DEPDIR := ./.dep/at-start-f415 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/I2C_HW/.cproject b/testhal/AT32/multi/I2C_HW/.cproject new file mode 100644 index 0000000000..74701160a0 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/multi/I2C_HW/.project b/testhal/AT32/multi/I2C_HW/.project new file mode 100644 index 0000000000..f7fbbf59d6 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/.project @@ -0,0 +1,78 @@ + + + AT32-I2C_HW + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/testhal/AT32/multi/I2C_HW/Makefile b/testhal/AT32/multi/I2C_HW/Makefile new file mode 100644 index 0000000000..c8606df05e --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/Makefile @@ -0,0 +1,18 @@ +############################################################################## +# Multi-project makefile rules +# + +all: + @echo + @echo === Building for AT-START-F415 ===================================== + +@make --no-print-directory -f ./make/at-start-f415.make all + @echo ==================================================================== + @echo + +clean: + @echo + +@make --no-print-directory -f ./make/at-start-f415.make clean + @echo + +# +############################################################################## diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/chconf.h new file mode 100644 index 0000000000..46b3f78b68 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/config.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/config.h new file mode 100644 index 0000000000..4fbd7cc3df --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/config.h @@ -0,0 +1,30 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf.h new file mode 100644 index 0000000000..28336f6196 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h new file mode 100644 index 0000000000..569c8a8b26 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h @@ -0,0 +1,228 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F415_MCUCONF + +#include "config.h" + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 TRUE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.c b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.c new file mode 100644 index 0000000000..ce6fb62e34 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.c @@ -0,0 +1,69 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/* + * I2C driver configuration structure. + */ +I2CConfig i2ccfg = { + OPMODE_I2C, + 100000, + STD_DUTY_CYCLE +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + palSetLineMode(PAL_LINE(GPIOB, 6U), PAL_MODE_AT32_ALTERNATE_OPENDRAIN); + palSetLineMode(PAL_LINE(GPIOB, 7U), PAL_MODE_AT32_ALTERNATE_OPENDRAIN); +} + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.h new file mode 100644 index 0000000000..d01a8c4c5c --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_I2C1 I2CD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern I2CConfig i2ccfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/main.c b/testhal/AT32/multi/I2C_HW/main.c new file mode 100644 index 0000000000..14755d2a35 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/main.c @@ -0,0 +1,93 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "portab.h" + +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + palSetLine(PORTAB_BLINK_LED3); + chThdSleepMilliseconds(500); + palClearLine(PORTAB_BLINK_LED3); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Board-dependent setup code. + */ + portab_setup(); + + /* + * Starting the I2C driver 1. + */ + i2cStart(&PORTAB_I2C1, &i2ccfg); + + /* + * Starting the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (true) { + unsigned i; + msg_t msg; + static const uint8_t cmd[] = {0, 0}; + uint8_t data[16]; + + msg = i2cMasterTransmitTimeout(&PORTAB_I2C1, 0x52, cmd, sizeof(cmd), + data, sizeof(data), TIME_INFINITE); + if (msg != MSG_OK) + palToggleLine(PORTAB_BLINK_LED1); + for (i = 0; i < 256; i++) { + msg = i2cMasterReceiveTimeout(&PORTAB_I2C1, 0x52, + data, sizeof(data), TIME_INFINITE); + if (msg != MSG_OK) + palToggleLine(PORTAB_BLINK_LED1); + } + + chThdSleepMilliseconds(500); + palToggleLine(PORTAB_BLINK_LED2); + } +} diff --git a/testhal/AT32/multi/I2C_HW/make/at-start-f415.make b/testhal/AT32/multi/I2C_HW/make/at-start-f415.make new file mode 100644 index 0000000000..c52af3650d --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/make/at-start-f415.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f415 +BUILDDIR := ./build/at-start-f415 +DEPDIR := ./.dep/at-start-f415 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/I2C_SW/.cproject b/testhal/AT32/multi/I2C_SW/.cproject new file mode 100644 index 0000000000..74701160a0 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/multi/I2C_SW/.project b/testhal/AT32/multi/I2C_SW/.project new file mode 100644 index 0000000000..39d0e67cf5 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/.project @@ -0,0 +1,78 @@ + + + AT32-I2C_SW + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/testhal/AT32/multi/I2C_SW/Makefile b/testhal/AT32/multi/I2C_SW/Makefile new file mode 100644 index 0000000000..c8606df05e --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/Makefile @@ -0,0 +1,18 @@ +############################################################################## +# Multi-project makefile rules +# + +all: + @echo + @echo === Building for AT-START-F415 ===================================== + +@make --no-print-directory -f ./make/at-start-f415.make all + @echo ==================================================================== + @echo + +clean: + @echo + +@make --no-print-directory -f ./make/at-start-f415.make clean + @echo + +# +############################################################################## diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/chconf.h new file mode 100644 index 0000000000..9baf444de4 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 100000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/config.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/config.h new file mode 100644 index 0000000000..5406a5a50d --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/config.h @@ -0,0 +1,30 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 TRUE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf.h new file mode 100644 index 0000000000..28336f6196 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h new file mode 100644 index 0000000000..08f41ad1dd --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h @@ -0,0 +1,228 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F415_MCUCONF + +#include "config.h" + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.c b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.c new file mode 100644 index 0000000000..798046ff8d --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.c @@ -0,0 +1,75 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +#include "math.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/* + * I2C fallback driver configuration structure. + */ +I2CConfig i2ccfg = { + FALSE, + PORTAB_SCL_PIN, + PORTAB_SDA_PIN, +#if (SW_I2C_USE_OSAL_DELAY) + ceil((CH_CFG_ST_FREQUENCY / 100000) / 2), +#else + &i2c_sw_delay +#endif +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.h new file mode 100644 index 0000000000..c3bd55be49 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.h @@ -0,0 +1,82 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_I2C1 I2CD1 + +#define PORTAB_SCL_PIN PAL_LINE(GPIOB, 6U) + +#define PORTAB_SDA_PIN PAL_LINE(GPIOB, 7U) + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern I2CConfig i2ccfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_SW/main.c b/testhal/AT32/multi/I2C_SW/main.c new file mode 100644 index 0000000000..14755d2a35 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/main.c @@ -0,0 +1,93 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "portab.h" + +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + palSetLine(PORTAB_BLINK_LED3); + chThdSleepMilliseconds(500); + palClearLine(PORTAB_BLINK_LED3); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Board-dependent setup code. + */ + portab_setup(); + + /* + * Starting the I2C driver 1. + */ + i2cStart(&PORTAB_I2C1, &i2ccfg); + + /* + * Starting the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (true) { + unsigned i; + msg_t msg; + static const uint8_t cmd[] = {0, 0}; + uint8_t data[16]; + + msg = i2cMasterTransmitTimeout(&PORTAB_I2C1, 0x52, cmd, sizeof(cmd), + data, sizeof(data), TIME_INFINITE); + if (msg != MSG_OK) + palToggleLine(PORTAB_BLINK_LED1); + for (i = 0; i < 256; i++) { + msg = i2cMasterReceiveTimeout(&PORTAB_I2C1, 0x52, + data, sizeof(data), TIME_INFINITE); + if (msg != MSG_OK) + palToggleLine(PORTAB_BLINK_LED1); + } + + chThdSleepMilliseconds(500); + palToggleLine(PORTAB_BLINK_LED2); + } +} diff --git a/testhal/AT32/multi/I2C_SW/make/at-start-f415.make b/testhal/AT32/multi/I2C_SW/make/at-start-f415.make new file mode 100644 index 0000000000..c2a77a92d6 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/make/at-start-f415.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f415 +BUILDDIR := ./build/at-start-f415 +DEPDIR := ./.dep/at-start-f415 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## From 0c718460209b68b979b3c0b02dd2e93a6e41ee05 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Sun, 4 Aug 2024 22:31:11 +0700 Subject: [PATCH 11/18] Added HAL driver test for ICU, PWM and UART --- testhal/AT32/multi/PWM_ICU/.cproject | 56 ++ testhal/AT32/multi/PWM_ICU/.project | 78 ++ testhal/AT32/multi/PWM_ICU/Makefile | 18 + .../multi/PWM_ICU/cfg/at-start-f415/chconf.h | 842 ++++++++++++++++++ .../multi/PWM_ICU/cfg/at-start-f415/config.h | 30 + .../multi/PWM_ICU/cfg/at-start-f415/halconf.h | 555 ++++++++++++ .../multi/PWM_ICU/cfg/at-start-f415/mcuconf.h | 228 +++++ .../multi/PWM_ICU/cfg/at-start-f415/portab.c | 98 ++ .../multi/PWM_ICU/cfg/at-start-f415/portab.h | 81 ++ testhal/AT32/multi/PWM_ICU/main.c | 152 ++++ .../multi/PWM_ICU/make/at-start-f415.make | 196 ++++ testhal/AT32/multi/UART/.cproject | 56 ++ testhal/AT32/multi/UART/.project | 78 ++ testhal/AT32/multi/UART/Makefile | 18 + .../multi/UART/cfg/at-start-f415/chconf.h | 842 ++++++++++++++++++ .../multi/UART/cfg/at-start-f415/config.h | 30 + .../multi/UART/cfg/at-start-f415/halconf.h | 555 ++++++++++++ .../multi/UART/cfg/at-start-f415/mcuconf.h | 228 +++++ .../multi/UART/cfg/at-start-f415/portab.c | 81 ++ .../multi/UART/cfg/at-start-f415/portab.h | 78 ++ testhal/AT32/multi/UART/main.c | 147 +++ .../AT32/multi/UART/make/at-start-f415.make | 196 ++++ 22 files changed, 4643 insertions(+) create mode 100644 testhal/AT32/multi/PWM_ICU/.cproject create mode 100644 testhal/AT32/multi/PWM_ICU/.project create mode 100644 testhal/AT32/multi/PWM_ICU/Makefile create mode 100644 testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/chconf.h create mode 100644 testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/config.h create mode 100644 testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf.h create mode 100644 testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h create mode 100644 testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.c create mode 100644 testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.h create mode 100644 testhal/AT32/multi/PWM_ICU/main.c create mode 100644 testhal/AT32/multi/PWM_ICU/make/at-start-f415.make create mode 100644 testhal/AT32/multi/UART/.cproject create mode 100644 testhal/AT32/multi/UART/.project create mode 100644 testhal/AT32/multi/UART/Makefile create mode 100644 testhal/AT32/multi/UART/cfg/at-start-f415/chconf.h create mode 100644 testhal/AT32/multi/UART/cfg/at-start-f415/config.h create mode 100644 testhal/AT32/multi/UART/cfg/at-start-f415/halconf.h create mode 100644 testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h create mode 100644 testhal/AT32/multi/UART/cfg/at-start-f415/portab.c create mode 100644 testhal/AT32/multi/UART/cfg/at-start-f415/portab.h create mode 100644 testhal/AT32/multi/UART/main.c create mode 100644 testhal/AT32/multi/UART/make/at-start-f415.make diff --git a/testhal/AT32/multi/PWM_ICU/.cproject b/testhal/AT32/multi/PWM_ICU/.cproject new file mode 100644 index 0000000000..74701160a0 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/multi/PWM_ICU/.project b/testhal/AT32/multi/PWM_ICU/.project new file mode 100644 index 0000000000..99d7344a17 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/.project @@ -0,0 +1,78 @@ + + + AT32-PWM_ICU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/testhal/AT32/multi/PWM_ICU/Makefile b/testhal/AT32/multi/PWM_ICU/Makefile new file mode 100644 index 0000000000..c8606df05e --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/Makefile @@ -0,0 +1,18 @@ +############################################################################## +# Multi-project makefile rules +# + +all: + @echo + @echo === Building for AT-START-F415 ===================================== + +@make --no-print-directory -f ./make/at-start-f415.make all + @echo ==================================================================== + @echo + +clean: + @echo + +@make --no-print-directory -f ./make/at-start-f415.make clean + @echo + +# +############################################################################## diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/chconf.h new file mode 100644 index 0000000000..46b3f78b68 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/config.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/config.h new file mode 100644 index 0000000000..4fbd7cc3df --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/config.h @@ -0,0 +1,30 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf.h new file mode 100644 index 0000000000..099dca49da --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h new file mode 100644 index 0000000000..fe5684806a --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h @@ -0,0 +1,228 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F415_MCUCONF + +#include "config.h" + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 TRUE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 TRUE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.c b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.c new file mode 100644 index 0000000000..f1a4b153f0 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.c @@ -0,0 +1,98 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +void pwmpcb(PWMDriver *pwmp); +void pwmc1cb(PWMDriver *pwmp); + +/* + * PWM driver configuration structure. + */ +PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, + 0, + 0 +}; + +void icuwidthcb(ICUDriver *icup); +void icuperiodcb(ICUDriver *icup); +void icuovfcb(ICUDriver *icup); + +/* + * ICU driver configuration structure. + */ +ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + NULL, + ICU_CHANNEL_1, + 0, + 0xFFFFFFFFU +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.h new file mode 100644 index 0000000000..45937f93e1 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.h @@ -0,0 +1,81 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_PWM1 PWMD1 + +#define PORTAB_ICU1 ICUD3 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern PWMConfig pwmcfg; +extern ICUConfig icucfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/main.c b/testhal/AT32/multi/PWM_ICU/main.c new file mode 100644 index 0000000000..f0bd7e9b2a --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/main.c @@ -0,0 +1,152 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "portab.h" + +/*===========================================================================*/ +/* PWM driver related. */ +/*===========================================================================*/ + +void pwmpcb(PWMDriver *pwmp) { + (void)pwmp; +} + +void pwmc1cb(PWMDriver *pwmp) { + (void)pwmp; +} + +/*===========================================================================*/ +/* ICU driver related. */ +/*===========================================================================*/ + +icucnt_t last_width, last_period; + +void icuwidthcb(ICUDriver *icup) { + palSetLine(PORTAB_BLINK_LED1); + palSetLine(PORTAB_BLINK_LED2); + palSetLine(PORTAB_BLINK_LED3); + last_width = icuGetWidthX(icup); +} + +void icuperiodcb(ICUDriver *icup) { + palClearLine(PORTAB_BLINK_LED1); + palClearLine(PORTAB_BLINK_LED2); + palClearLine(PORTAB_BLINK_LED3); + last_period = icuGetPeriodX(icup); +} + +void icuovfcb(ICUDriver *icup) { + (void)icup; +} + +/*===========================================================================*/ +/* Application code. */ +/*===========================================================================*/ + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Board-dependent setup code. + */ + portab_setup(); + + /* + * Starting PWM driver 1 and enabling the notifications. + * GPIOA8 is programmed as PWM output (channel 1 of TMR1). + */ + pwmStart(&PORTAB_PWM1, &pwmcfg); + pwmEnablePeriodicNotification(&PORTAB_PWM1); + palSetLineMode(LINE_ARD_D7, PAL_MODE_AT32_ALTERNATE_PUSHPULL); + + /* + * Starting ICU driver 3. + * GPIOA6 is programmed as ICU input (channel 1 of TMR3). + */ + icuStart(&PORTAB_ICU1, &icucfg); + palSetLine(LINE_ARD_D12); + + /* + * GPIOC2/C3/C5 is programmed as output (board LED). + */ + palClearLine(PORTAB_BLINK_LED1); + palClearLine(PORTAB_BLINK_LED2); + palClearLine(PORTAB_BLINK_LED3); + palSetLine(PORTAB_BLINK_LED1); + palSetLine(PORTAB_BLINK_LED2); + palSetLine(PORTAB_BLINK_LED3); + chThdSleepMilliseconds(1000); + + /* + * Starting ICU capture and enabling the notifications. + */ + icuStartCapture(&PORTAB_ICU1); + icuEnableNotifications(&PORTAB_ICU1); + + /* + * Normal main() thread activity, various PWM patterns are generated + * cyclically, if the ICU input is connected to the PWM output the + * board LED mirrors the PWM output. + */ + while (true) { + /* + * Starts the PWM channel 0 using 75% duty cycle. + */ + pwmEnableChannel(&PORTAB_PWM1, 0, PWM_PERCENTAGE_TO_WIDTH(&PORTAB_PWM1, 7500)); + pwmEnableChannelNotification(&PORTAB_PWM1, 0); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 50% duty cycle. + */ + pwmEnableChannel(&PORTAB_PWM1, 0, PWM_PERCENTAGE_TO_WIDTH(&PORTAB_PWM1, 5000)); + chThdSleepMilliseconds(5000); + + /* + * Changes the PWM channel 0 to 25% duty cycle. + */ + pwmEnableChannel(&PORTAB_PWM1, 0, PWM_PERCENTAGE_TO_WIDTH(&PORTAB_PWM1, 2500)); + chThdSleepMilliseconds(5000); + + /* + * Changes PWM period to half second the duty cycle becomes 50% + * implicitly. + */ + pwmChangePeriod(&PORTAB_PWM1, 5000); + chThdSleepMilliseconds(5000); + + /* + * Disables channel 0. + */ + pwmDisableChannel(&PORTAB_PWM1, 0); + } +} diff --git a/testhal/AT32/multi/PWM_ICU/make/at-start-f415.make b/testhal/AT32/multi/PWM_ICU/make/at-start-f415.make new file mode 100644 index 0000000000..c52af3650d --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/make/at-start-f415.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f415 +BUILDDIR := ./build/at-start-f415 +DEPDIR := ./.dep/at-start-f415 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/UART/.cproject b/testhal/AT32/multi/UART/.cproject new file mode 100644 index 0000000000..74701160a0 --- /dev/null +++ b/testhal/AT32/multi/UART/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/multi/UART/.project b/testhal/AT32/multi/UART/.project new file mode 100644 index 0000000000..5d390c1f55 --- /dev/null +++ b/testhal/AT32/multi/UART/.project @@ -0,0 +1,78 @@ + + + AT32-UART + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/testhal/AT32/multi/UART/Makefile b/testhal/AT32/multi/UART/Makefile new file mode 100644 index 0000000000..c8606df05e --- /dev/null +++ b/testhal/AT32/multi/UART/Makefile @@ -0,0 +1,18 @@ +############################################################################## +# Multi-project makefile rules +# + +all: + @echo + @echo === Building for AT-START-F415 ===================================== + +@make --no-print-directory -f ./make/at-start-f415.make all + @echo ==================================================================== + @echo + +clean: + @echo + +@make --no-print-directory -f ./make/at-start-f415.make clean + @echo + +# +############################################################################## diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/UART/cfg/at-start-f415/chconf.h new file mode 100644 index 0000000000..46b3f78b68 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/config.h b/testhal/AT32/multi/UART/cfg/at-start-f415/config.h new file mode 100644 index 0000000000..4fbd7cc3df --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/config.h @@ -0,0 +1,30 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/UART/cfg/at-start-f415/halconf.h new file mode 100644 index 0000000000..46b0bcae74 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h new file mode 100644 index 0000000000..11ce707ca3 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h @@ -0,0 +1,228 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F415_MCUCONF + +#include "config.h" + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 TRUE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/portab.c b/testhal/AT32/multi/UART/cfg/at-start-f415/portab.c new file mode 100644 index 0000000000..b2d669c604 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/portab.c @@ -0,0 +1,81 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +void txend1(UARTDriver *uartp); +void txend2(UARTDriver *uartp); +void rxend(UARTDriver *uartp); +void rxchar(UARTDriver *uartp, uint16_t c); +void rxerr(UARTDriver *uartp, uartflags_t e); + +/* + * UART driver configuration structure. + */ +UARTConfig uartcfg = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + NULL, + 38400, + 0, + USART_CTRL2_LINEN, + 0 +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/portab.h b/testhal/AT32/multi/UART/cfg/at-start-f415/portab.h new file mode 100644 index 0000000000..1d682cf18d --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_UART1 UARTD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern UARTConfig uartcfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/main.c b/testhal/AT32/multi/UART/main.c new file mode 100644 index 0000000000..b610d2f600 --- /dev/null +++ b/testhal/AT32/multi/UART/main.c @@ -0,0 +1,147 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "portab.h" + +static virtual_timer_t vt1, vt2; + +static void restart(virtual_timer_t *vtp, void *p) { + + (void)vtp; + (void)p; + + chSysLockFromISR(); + uartStartSendI(&PORTAB_UART1, 14, "Hello World!\r\n"); + chSysUnlockFromISR(); +} + +static void ledoff(virtual_timer_t *vtp, void *p) { + + (void)vtp; + (void)p; + + palSetLine(PORTAB_BLINK_LED1); + palSetLine(PORTAB_BLINK_LED2); + palSetLine(PORTAB_BLINK_LED3); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +void txend1(UARTDriver *uartp) { + + (void)uartp; + + palClearLine(PORTAB_BLINK_LED1); + palClearLine(PORTAB_BLINK_LED2); + palClearLine(PORTAB_BLINK_LED3); +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +void txend2(UARTDriver *uartp) { + + (void)uartp; + + palSetLine(PORTAB_BLINK_LED1); + palSetLine(PORTAB_BLINK_LED2); + palSetLine(PORTAB_BLINK_LED3); + + chSysLockFromISR(); + chVTSetI(&vt1, TIME_MS2I(5000), restart, NULL); + chSysUnlockFromISR(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + + /* Flashing the LED each time a character is received.*/ + palClearLine(PORTAB_BLINK_LED1); + palClearLine(PORTAB_BLINK_LED2); + palClearLine(PORTAB_BLINK_LED3); + + chSysLockFromISR(); + chVTSetI(&vt2, TIME_MS2I(200), ledoff, NULL); + chSysUnlockFromISR(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +void rxend(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Board-dependent setup code. + */ + portab_setup(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + uartStart(&PORTAB_UART1, &uartcfg); + + /* + * Starts the transmission, it will be handled entirely in background. + */ + uartStartSend(&PORTAB_UART1, 13, "Starting...\r\n"); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (true) { + chThdSleepMilliseconds(500); + } +} diff --git a/testhal/AT32/multi/UART/make/at-start-f415.make b/testhal/AT32/multi/UART/make/at-start-f415.make new file mode 100644 index 0000000000..c52af3650d --- /dev/null +++ b/testhal/AT32/multi/UART/make/at-start-f415.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f415 +BUILDDIR := ./build/at-start-f415 +DEPDIR := ./.dep/at-start-f415 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## From 6404f2f566228b9176cba44c90e60f22a4843ba6 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Mon, 5 Aug 2024 17:13:13 +0700 Subject: [PATCH 12/18] Fixed missing CRC register on CMSIS --- .../ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h | 24 +++++++++++++++++++ .../ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h | 24 +++++++++++++++++++ .../ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h | 24 +++++++++++++++++++ 3 files changed, 72 insertions(+) diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h index 2507e3c7df..3cfb8d24ed 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h @@ -279,6 +279,7 @@ typedef struct __IO uint32_t CTRL; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x0C */ __IO uint32_t IDT; /*!< CRC Initialization register, Address offset: 0x10 */ + __IO uint32_t POLY; /*!< CRC Polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** @@ -4205,6 +4206,24 @@ typedef struct #define CRC_CTRL_RST_Msk (0x1U << CRC_CTRL_RST_Pos) /*!< 0x00000001 */ #define CRC_CTRL_RST CRC_CTRL_RST_Msk /*!< Reset CRC calculation unit */ +/*!< POLY_SIZE configuration */ +#define CRC_CTRL_POLY_SIZE_Pos (3U) +#define CRC_CTRL_POLY_SIZE_Msk (0x3U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE CRC_CTRL_POLY_SIZE_Msk /*!< POLY_SIZE[1:0] bits (Polynomial size) */ +#define CRC_CTRL_POLY_SIZE_0 (0x1U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_1 (0x2U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000010 */ + +#define CRC_CTRL_POLY_SIZE_32BITS 0x00000000U /*!< 32 bits */ +#define CRC_CTRL_POLY_SIZE_16BITS_Pos (3U) +#define CRC_CTRL_POLY_SIZE_16BITS_Msk (0x1U << CRC_CTRL_POLY_SIZE_16BITS_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_16BITS CRC_CTRL_POLY_SIZE_16BITS_Msk /*!< 16 bits */ +#define CRC_CTRL_POLY_SIZE_8BITS_Pos (4U) +#define CRC_CTRL_POLY_SIZE_8BITS_Msk (0x1U << CRC_CTRL_POLY_SIZE_8BITS_Pos) /*!< 0x00000010 */ +#define CRC_CTRL_POLY_SIZE_8BITS CRC_CTRL_POLY_SIZE_8BITS_Msk /*!< 8 bits */ +#define CRC_CTRL_POLY_SIZE_7BITS_Pos (3U) +#define CRC_CTRL_POLY_SIZE_7BITS_Msk (0x3U << CRC_CTRL_POLY_SIZE_7BITS_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE_7BITS CRC_CTRL_POLY_SIZE_7BITS_Msk /*!< 7 bits */ + /*!< REVID configuration */ #define CRC_CTRL_REVID_Pos (5U) #define CRC_CTRL_REVID_Msk (0x3U << CRC_CTRL_REVID_Pos) /*!< 0x00000060 */ @@ -4232,6 +4251,11 @@ typedef struct #define CRC_IDT_IDT_Msk (0xFFFFFFFFU << CRC_IDT_IDT_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDT_IDT CRC_IDT_IDT_Msk /*!< Initialization data register */ +/******************* Bit definition for CRC_POLY register *******************/ +#define CRC_POLY_POLY_Pos (0U) +#define CRC_POLY_POLY_Msk (0xFFFFFFFFU << CRC_POLY_POLY_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POLY_POLY CRC_POLY_POLY_Msk /*!< Polynomial coefficient */ + /******************************************************************************/ /* */ /* Inter-integrated circuit interface (I2C) */ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h index 994bd9891b..6b5fdf8059 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h @@ -278,6 +278,7 @@ typedef struct __IO uint32_t CTRL; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x0C */ __IO uint32_t IDT; /*!< CRC Initialization register, Address offset: 0x10 */ + __IO uint32_t POLY; /*!< CRC Polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** @@ -4164,6 +4165,24 @@ typedef struct #define CRC_CTRL_RST_Msk (0x1U << CRC_CTRL_RST_Pos) /*!< 0x00000001 */ #define CRC_CTRL_RST CRC_CTRL_RST_Msk /*!< Reset CRC calculation unit */ +/*!< POLY_SIZE configuration */ +#define CRC_CTRL_POLY_SIZE_Pos (3U) +#define CRC_CTRL_POLY_SIZE_Msk (0x3U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE CRC_CTRL_POLY_SIZE_Msk /*!< POLY_SIZE[1:0] bits (Polynomial size) */ +#define CRC_CTRL_POLY_SIZE_0 (0x1U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_1 (0x2U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000010 */ + +#define CRC_CTRL_POLY_SIZE_32BITS 0x00000000U /*!< 32 bits */ +#define CRC_CTRL_POLY_SIZE_16BITS_Pos (3U) +#define CRC_CTRL_POLY_SIZE_16BITS_Msk (0x1U << CRC_CTRL_POLY_SIZE_16BITS_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_16BITS CRC_CTRL_POLY_SIZE_16BITS_Msk /*!< 16 bits */ +#define CRC_CTRL_POLY_SIZE_8BITS_Pos (4U) +#define CRC_CTRL_POLY_SIZE_8BITS_Msk (0x1U << CRC_CTRL_POLY_SIZE_8BITS_Pos) /*!< 0x00000010 */ +#define CRC_CTRL_POLY_SIZE_8BITS CRC_CTRL_POLY_SIZE_8BITS_Msk /*!< 8 bits */ +#define CRC_CTRL_POLY_SIZE_7BITS_Pos (3U) +#define CRC_CTRL_POLY_SIZE_7BITS_Msk (0x3U << CRC_CTRL_POLY_SIZE_7BITS_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE_7BITS CRC_CTRL_POLY_SIZE_7BITS_Msk /*!< 7 bits */ + /*!< REVID configuration */ #define CRC_CTRL_REVID_Pos (5U) #define CRC_CTRL_REVID_Msk (0x3U << CRC_CTRL_REVID_Pos) /*!< 0x00000060 */ @@ -4191,6 +4210,11 @@ typedef struct #define CRC_IDT_IDT_Msk (0xFFFFFFFFU << CRC_IDT_IDT_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDT_IDT CRC_IDT_IDT_Msk /*!< Initialization data register */ +/******************* Bit definition for CRC_POLY register *******************/ +#define CRC_POLY_POLY_Pos (0U) +#define CRC_POLY_POLY_Msk (0xFFFFFFFFU << CRC_POLY_POLY_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POLY_POLY CRC_POLY_POLY_Msk /*!< Polynomial coefficient */ + /******************************************************************************/ /* */ /* Inter-integrated circuit interface (I2C) */ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h index c3b77c5c92..7015a9ab07 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h @@ -281,6 +281,7 @@ typedef struct __IO uint32_t CTRL; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x0C */ __IO uint32_t IDT; /*!< CRC Initialization register, Address offset: 0x10 */ + __IO uint32_t POLY; /*!< CRC Polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** @@ -4237,6 +4238,24 @@ typedef struct #define CRC_CTRL_RST_Msk (0x1U << CRC_CTRL_RST_Pos) /*!< 0x00000001 */ #define CRC_CTRL_RST CRC_CTRL_RST_Msk /*!< Reset CRC calculation unit */ +/*!< POLY_SIZE configuration */ +#define CRC_CTRL_POLY_SIZE_Pos (3U) +#define CRC_CTRL_POLY_SIZE_Msk (0x3U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE CRC_CTRL_POLY_SIZE_Msk /*!< POLY_SIZE[1:0] bits (Polynomial size) */ +#define CRC_CTRL_POLY_SIZE_0 (0x1U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_1 (0x2U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000010 */ + +#define CRC_CTRL_POLY_SIZE_32BITS 0x00000000U /*!< 32 bits */ +#define CRC_CTRL_POLY_SIZE_16BITS_Pos (3U) +#define CRC_CTRL_POLY_SIZE_16BITS_Msk (0x1U << CRC_CTRL_POLY_SIZE_16BITS_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_16BITS CRC_CTRL_POLY_SIZE_16BITS_Msk /*!< 16 bits */ +#define CRC_CTRL_POLY_SIZE_8BITS_Pos (4U) +#define CRC_CTRL_POLY_SIZE_8BITS_Msk (0x1U << CRC_CTRL_POLY_SIZE_8BITS_Pos) /*!< 0x00000010 */ +#define CRC_CTRL_POLY_SIZE_8BITS CRC_CTRL_POLY_SIZE_8BITS_Msk /*!< 8 bits */ +#define CRC_CTRL_POLY_SIZE_7BITS_Pos (3U) +#define CRC_CTRL_POLY_SIZE_7BITS_Msk (0x3U << CRC_CTRL_POLY_SIZE_7BITS_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE_7BITS CRC_CTRL_POLY_SIZE_7BITS_Msk /*!< 7 bits */ + /*!< REVID configuration */ #define CRC_CTRL_REVID_Pos (5U) #define CRC_CTRL_REVID_Msk (0x3U << CRC_CTRL_REVID_Pos) /*!< 0x00000060 */ @@ -4264,6 +4283,11 @@ typedef struct #define CRC_IDT_IDT_Msk (0xFFFFFFFFU << CRC_IDT_IDT_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDT_IDT CRC_IDT_IDT_Msk /*!< Initialization data register */ +/******************* Bit definition for CRC_POLY register *******************/ +#define CRC_POLY_POLY_Pos (0U) +#define CRC_POLY_POLY_Msk (0xFFFFFFFFU << CRC_POLY_POLY_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POLY_POLY CRC_POLY_POLY_Msk /*!< Polynomial coefficient */ + /******************************************************************************/ /* */ /* Inter-integrated circuit interface (I2C) */ From 41b3477d01cd4673d4d62f6762b81c5824f26ed2 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Mon, 5 Aug 2024 17:15:06 +0700 Subject: [PATCH 13/18] Deleted unused CRC on registry and update HAL test files --- os/hal/ports/AT32/AT32F415/at32_registry.h | 18 ------------------ .../multi/ERTC/cfg/at-start-f415/mcuconf.h | 4 ++-- .../multi/I2C_HW/cfg/at-start-f415/mcuconf.h | 4 ++-- .../multi/I2C_SW/cfg/at-start-f415/mcuconf.h | 4 ++-- .../multi/PWM_ICU/cfg/at-start-f415/mcuconf.h | 4 ++-- .../multi/UART/cfg/at-start-f415/mcuconf.h | 4 ++-- 6 files changed, 10 insertions(+), 28 deletions(-) diff --git a/os/hal/ports/AT32/AT32F415/at32_registry.h b/os/hal/ports/AT32/AT32F415/at32_registry.h index 4213e294eb..0e0df2792d 100644 --- a/os/hal/ports/AT32/AT32F415/at32_registry.h +++ b/os/hal/ports/AT32/AT32F415/at32_registry.h @@ -265,9 +265,6 @@ /* WDT attributes.*/ #define AT32_HAS_WDT TRUE #define AT32_WDT_IS_WINDOWED FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE /** @} */ #endif /* defined(AT32F415K_MD) */ @@ -483,9 +480,6 @@ /* WDT attributes.*/ #define AT32_HAS_WDT TRUE #define AT32_WDT_IS_WINDOWED FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE /** @} */ #endif /* defined(AT32F415K_HD) */ @@ -711,9 +705,6 @@ /* WDT attributes.*/ #define AT32_HAS_WDT TRUE #define AT32_WDT_IS_WINDOWED FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE /** @} */ #endif /* defined(AT32F415C_MD) */ @@ -939,9 +930,6 @@ /* WDT attributes.*/ #define AT32_HAS_WDT TRUE #define AT32_WDT_IS_WINDOWED FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE /** @} */ #endif /* defined(AT32F415C_HD) */ @@ -1186,9 +1174,6 @@ /* WDT attributes.*/ #define AT32_HAS_WDT TRUE #define AT32_WDT_IS_WINDOWED FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE /** @} */ #endif /* defined(AT32F415R_MD) */ @@ -1433,9 +1418,6 @@ /* WDT attributes.*/ #define AT32_HAS_WDT TRUE #define AT32_WDT_IS_WINDOWED FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE /** @} */ #endif /* defined(AT32F415R_HD) */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h index 3c30d3621c..d3da1f31a6 100644 --- a/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h @@ -35,8 +35,6 @@ #define AT32F415_MCUCONF -#include "config.h" - /* * General settings. */ @@ -225,4 +223,6 @@ */ #define AT32_WDG_USE_WDT FALSE +#include "config.h" + #endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h index 569c8a8b26..b218c904c4 100644 --- a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h @@ -35,8 +35,6 @@ #define AT32F415_MCUCONF -#include "config.h" - /* * General settings. */ @@ -225,4 +223,6 @@ */ #define AT32_WDG_USE_WDT FALSE +#include "config.h" + #endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h index 08f41ad1dd..4a4ddf6445 100644 --- a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h @@ -35,8 +35,6 @@ #define AT32F415_MCUCONF -#include "config.h" - /* * General settings. */ @@ -225,4 +223,6 @@ */ #define AT32_WDG_USE_WDT FALSE +#include "config.h" + #endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h index fe5684806a..323cb23b98 100644 --- a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h @@ -35,8 +35,6 @@ #define AT32F415_MCUCONF -#include "config.h" - /* * General settings. */ @@ -225,4 +223,6 @@ */ #define AT32_WDG_USE_WDT FALSE +#include "config.h" + #endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h index 11ce707ca3..8c64a6aea4 100644 --- a/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h @@ -35,8 +35,6 @@ #define AT32F415_MCUCONF -#include "config.h" - /* * General settings. */ @@ -225,4 +223,6 @@ */ #define AT32_WDG_USE_WDT FALSE +#include "config.h" + #endif /* MCUCONF_H */ From 92bcbceaffa25b65a7c53f19d1865d64357e51e3 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Mon, 5 Aug 2024 20:58:01 +0700 Subject: [PATCH 14/18] Update LLD drivers for WDT again and small changes for HAL test --- os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c | 5 +++++ os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h | 17 +++++++++++++++++ testhal/AT32/multi/I2C_HW/main.c | 1 + testhal/AT32/multi/I2C_SW/main.c | 1 + testhal/AT32/multi/PWM_ICU/main.c | 1 + testhal/AT32/multi/UART/main.c | 1 + 6 files changed, 26 insertions(+) diff --git a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c index 3fe9c48e5e..acde648698 100644 --- a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c +++ b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c @@ -99,7 +99,12 @@ void wdg_lld_start(WDGDriver *wdgp) { while (wdgp->wdt->STS != 0) ; +#if AT32_WDT_IS_WINDOWED + /* This also triggers a refresh.*/ + wdgp->wdt->WIN = wdgp->config->win; +#else wdgp->wdt->CMD = CMD_CMD_RELOAD; +#endif } /** diff --git a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h index da2391c447..f2e47c9963 100644 --- a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h +++ b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h @@ -55,6 +55,15 @@ #define AT32_WDT_DIV_256 6U /** @} */ +/** + * @name WIN register definitions + * @{ + */ +#define AT32_WDT_WIN_MASK (0x00000FFF << 0) +#define AT32_WDT_WIN(n) ((n) << 0) +#define AT32_WDT_WIN_DISABLED AT32_WDT_WIN(0x00000FFF) +/** @} */ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -117,6 +126,14 @@ typedef struct { * @details See the AT32 reference manual for details. */ uint32_t rld; +#if AT32_WDT_IS_WINDOWED || defined(__DOXYGEN__) + /** + * @brief Configuration of the WDT_WIN register. + * @details See the AT32 reference manual for details. + * @note This field is not present in F415 sub-families. + */ + uint32_t win; +#endif } WDGConfig; /** diff --git a/testhal/AT32/multi/I2C_HW/main.c b/testhal/AT32/multi/I2C_HW/main.c index 14755d2a35..9d3047a9c1 100644 --- a/testhal/AT32/multi/I2C_HW/main.c +++ b/testhal/AT32/multi/I2C_HW/main.c @@ -18,6 +18,7 @@ #include "ch.h" #include "hal.h" + #include "portab.h" /* diff --git a/testhal/AT32/multi/I2C_SW/main.c b/testhal/AT32/multi/I2C_SW/main.c index 14755d2a35..9d3047a9c1 100644 --- a/testhal/AT32/multi/I2C_SW/main.c +++ b/testhal/AT32/multi/I2C_SW/main.c @@ -18,6 +18,7 @@ #include "ch.h" #include "hal.h" + #include "portab.h" /* diff --git a/testhal/AT32/multi/PWM_ICU/main.c b/testhal/AT32/multi/PWM_ICU/main.c index f0bd7e9b2a..a85b9e6d00 100644 --- a/testhal/AT32/multi/PWM_ICU/main.c +++ b/testhal/AT32/multi/PWM_ICU/main.c @@ -18,6 +18,7 @@ #include "ch.h" #include "hal.h" + #include "portab.h" /*===========================================================================*/ diff --git a/testhal/AT32/multi/UART/main.c b/testhal/AT32/multi/UART/main.c index b610d2f600..536b95a5c9 100644 --- a/testhal/AT32/multi/UART/main.c +++ b/testhal/AT32/multi/UART/main.c @@ -18,6 +18,7 @@ #include "ch.h" #include "hal.h" + #include "portab.h" static virtual_timer_t vt1, vt2; From b79c56873ad5164fc6ea32cee901b0e9227b333c Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Mon, 5 Aug 2024 22:24:52 +0700 Subject: [PATCH 15/18] Added HAL driver test for WDT and update for USB_CDC --- .../multi/USB_CDC/cfg/at-start-f415/chconf.h | 12 +- .../multi/USB_CDC/cfg/at-start-f415/config.h | 30 + .../multi/USB_CDC/cfg/at-start-f415/mcuconf.h | 8 +- testhal/AT32/multi/USB_CDC/main.c | 5 +- .../multi/USB_CDC/make/at-start-f415.make | 9 +- testhal/AT32/multi/WDT/.cproject | 56 ++ testhal/AT32/multi/WDT/.project | 78 ++ testhal/AT32/multi/WDT/Makefile | 18 + .../AT32/multi/WDT/cfg/at-start-f415/chconf.h | 842 ++++++++++++++++++ .../AT32/multi/WDT/cfg/at-start-f415/config.h | 30 + .../multi/WDT/cfg/at-start-f415/halconf.h | 555 ++++++++++++ .../multi/WDT/cfg/at-start-f415/mcuconf.h | 228 +++++ .../AT32/multi/WDT/cfg/at-start-f415/portab.c | 70 ++ .../AT32/multi/WDT/cfg/at-start-f415/portab.h | 78 ++ testhal/AT32/multi/WDT/main.c | 60 ++ .../AT32/multi/WDT/make/at-start-f415.make | 196 ++++ 16 files changed, 2264 insertions(+), 11 deletions(-) create mode 100644 testhal/AT32/multi/USB_CDC/cfg/at-start-f415/config.h create mode 100644 testhal/AT32/multi/WDT/.cproject create mode 100644 testhal/AT32/multi/WDT/.project create mode 100644 testhal/AT32/multi/WDT/Makefile create mode 100644 testhal/AT32/multi/WDT/cfg/at-start-f415/chconf.h create mode 100644 testhal/AT32/multi/WDT/cfg/at-start-f415/config.h create mode 100644 testhal/AT32/multi/WDT/cfg/at-start-f415/halconf.h create mode 100644 testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h create mode 100644 testhal/AT32/multi/WDT/cfg/at-start-f415/portab.c create mode 100644 testhal/AT32/multi/WDT/cfg/at-start-f415/portab.h create mode 100644 testhal/AT32/multi/WDT/main.c create mode 100644 testhal/AT32/multi/WDT/make/at-start-f415.make diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h index 42828da814..46b3f78b68 100644 --- a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h @@ -588,7 +588,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) -#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#define CH_DBG_SYSTEM_STATE_CHECK TRUE #endif /** @@ -599,7 +599,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) -#define CH_DBG_ENABLE_CHECKS FALSE +#define CH_DBG_ENABLE_CHECKS TRUE #endif /** @@ -611,7 +611,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) -#define CH_DBG_ENABLE_ASSERTS FALSE +#define CH_DBG_ENABLE_ASSERTS TRUE #endif /** @@ -621,7 +621,7 @@ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. */ #if !defined(CH_DBG_TRACE_MASK) -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL #endif /** @@ -644,7 +644,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK TRUE #endif /** @@ -656,7 +656,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS TRUE #endif /** diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/config.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/config.h new file mode 100644 index 0000000000..4fbd7cc3df --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/config.h @@ -0,0 +1,30 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h index 3b0e65f93f..5257a8ca60 100644 --- a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h @@ -36,9 +36,13 @@ #define AT32F415_MCUCONF /* - * HAL driver system settings. + * General settings. */ #define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ #define AT32_HICK_ENABLED TRUE #define AT32_LICK_ENABLED FALSE #define AT32_HEXT_ENABLED TRUE @@ -219,4 +223,6 @@ */ #define AT32_WDG_USE_WDT FALSE +#include "config.h" + #endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/USB_CDC/main.c b/testhal/AT32/multi/USB_CDC/main.c index a18e70123e..66a444c978 100644 --- a/testhal/AT32/multi/USB_CDC/main.c +++ b/testhal/AT32/multi/USB_CDC/main.c @@ -16,22 +16,23 @@ limitations under the License. */ -#include #include #include #include "ch.h" #include "hal.h" + #include "shell.h" #include "chprintf.h" +#include "portab.h" #include "usbcfg.h" /*===========================================================================*/ /* Command line related. */ /*===========================================================================*/ -#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) /* Can be measured using dd if=/dev/xxxx of=/dev/null bs=512 count=10000.*/ static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { diff --git a/testhal/AT32/multi/USB_CDC/make/at-start-f415.make b/testhal/AT32/multi/USB_CDC/make/at-start-f415.make index 60300dbfcd..8e280f39d9 100644 --- a/testhal/AT32/multi/USB_CDC/make/at-start-f415.make +++ b/testhal/AT32/multi/USB_CDC/make/at-start-f415.make @@ -10,7 +10,7 @@ endif # C specific options here (added to USE_OPT). ifeq ($(USE_COPT),) - USE_COPT = + USE_COPT = endif # C++ specific options here (added to USE_OPT). @@ -25,7 +25,7 @@ endif # Linker extra options here. ifeq ($(USE_LDOPT),) - USE_LDOPT = + USE_LDOPT = endif # Enable this if you want link time optimizations (LTO). @@ -44,6 +44,11 @@ ifeq ($(USE_SMART_BUILD),) USE_SMART_BUILD = yes endif +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + # # Build global options ############################################################################## diff --git a/testhal/AT32/multi/WDT/.cproject b/testhal/AT32/multi/WDT/.cproject new file mode 100644 index 0000000000..74701160a0 --- /dev/null +++ b/testhal/AT32/multi/WDT/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/multi/WDT/.project b/testhal/AT32/multi/WDT/.project new file mode 100644 index 0000000000..be0419fe21 --- /dev/null +++ b/testhal/AT32/multi/WDT/.project @@ -0,0 +1,78 @@ + + + AT32-WDT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/testhal/AT32/multi/WDT/Makefile b/testhal/AT32/multi/WDT/Makefile new file mode 100644 index 0000000000..c8606df05e --- /dev/null +++ b/testhal/AT32/multi/WDT/Makefile @@ -0,0 +1,18 @@ +############################################################################## +# Multi-project makefile rules +# + +all: + @echo + @echo === Building for AT-START-F415 ===================================== + +@make --no-print-directory -f ./make/at-start-f415.make all + @echo ==================================================================== + @echo + +clean: + @echo + +@make --no-print-directory -f ./make/at-start-f415.make clean + @echo + +# +############################################################################## diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/chconf.h new file mode 100644 index 0000000000..46b3f78b68 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/config.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/config.h new file mode 100644 index 0000000000..4fbd7cc3df --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/config.h @@ -0,0 +1,30 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf.h new file mode 100644 index 0000000000..bb02d4b607 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG TRUE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h new file mode 100644 index 0000000000..d1646fa57a --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h @@ -0,0 +1,228 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F415_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED TRUE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT TRUE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.c b/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.c new file mode 100644 index 0000000000..1221b387b3 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.c @@ -0,0 +1,70 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/* + * Watchdog deadline set to more than one second (LICK = 40000 / (64 * 1000)). + */ +WDGConfig wdgcfg = { + AT32_WDT_DIV_64, + AT32_WDT_RLD(1000), +#if AT32_WDT_IS_WINDOWED + AT32_WDT_WIN_DISABLED +#endif +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.h new file mode 100644 index 0000000000..4c14ffc774 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_WDT1 WDGD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern WDGConfig wdgcfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/main.c b/testhal/AT32/multi/WDT/main.c new file mode 100644 index 0000000000..45987c7ea4 --- /dev/null +++ b/testhal/AT32/multi/WDT/main.c @@ -0,0 +1,60 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#include "portab.h" + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Board-dependent setup code. + */ + portab_setup(); + + /* + * Starting the watchdog driver. + */ + wdgStart(&PORTAB_WDT1, &wdgcfg); + + /* + * Normal main() thread activity, it resets the watchdog. + */ + while (true) { + wdgReset(&PORTAB_WDT1); + palToggleLine(PORTAB_BLINK_LED1); + palToggleLine(PORTAB_BLINK_LED2); + palToggleLine(PORTAB_BLINK_LED3); + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/AT32/multi/WDT/make/at-start-f415.make b/testhal/AT32/multi/WDT/make/at-start-f415.make new file mode 100644 index 0000000000..c52af3650d --- /dev/null +++ b/testhal/AT32/multi/WDT/make/at-start-f415.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f415 +BUILDDIR := ./build/at-start-f415 +DEPDIR := ./.dep/at-start-f415 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## From a48b4868b2845c326ea0a569536b089f33712ba0 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Sun, 11 Aug 2024 13:56:59 +0700 Subject: [PATCH 16/18] Update SPI LLD driver --- os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c index 5a1398ef2d..8489f04186 100644 --- a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c +++ b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c @@ -32,18 +32,26 @@ /* Driver local definitions. */ /*===========================================================================*/ +#if !defined(SPI_SPID1_MEMORY) +#define SPI_SPID1_MEMORY +#endif + +#if !defined(SPI_SPID2_MEMORY) +#define SPI_SPID2_MEMORY +#endif + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ /** @brief SPI1 driver identifier.*/ #if AT32_SPI_USE_SPI1 || defined(__DOXYGEN__) -SPIDriver SPID1; +SPI_SPID1_MEMORY SPIDriver SPID1; #endif /** @brief SPI2 driver identifier.*/ #if AT32_SPI_USE_SPI2 || defined(__DOXYGEN__) -SPIDriver SPID2; +SPI_SPID2_MEMORY SPIDriver SPID2; #endif /*===========================================================================*/ From 635a296fa132deaa663c7943136b6cbf9755e583 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Sun, 11 Aug 2024 13:59:07 +0700 Subject: [PATCH 17/18] Added support for SDIO LLD driver --- os/hal/boards/AT_START_F415/board.c | 22 + os/hal/ports/AT32/AT32F415/at32_dmamux.h | 2 +- os/hal/ports/AT32/AT32F415/at32_registry.h | 48 +- os/hal/ports/AT32/AT32F415/platform.mk | 1 + os/hal/ports/AT32/LLD/SDIOv1/driver.mk | 9 + os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c | 942 +++++++++++++++++++++ os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.h | 274 ++++++ 7 files changed, 1273 insertions(+), 25 deletions(-) create mode 100644 os/hal/ports/AT32/LLD/SDIOv1/driver.mk create mode 100644 os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c create mode 100644 os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.h diff --git a/os/hal/boards/AT_START_F415/board.c b/os/hal/boards/AT_START_F415/board.c index fe4e2ddc2c..8ae1f6737e 100644 --- a/os/hal/boards/AT_START_F415/board.c +++ b/os/hal/boards/AT_START_F415/board.c @@ -70,6 +70,28 @@ void __early_init(void) { at32_clock_init(); } +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + static bool last_status = false; + + if (blkIsTransferring(sdcp)) + return last_status; + return last_status = (bool)palReadPad(GPIOA, GPIOA_ARD_A2); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + return false; +} +#endif /* HAL_USE_SDC */ + /** * @brief Board-specific initialization code. * @note You can add your board-specific code here. diff --git a/os/hal/ports/AT32/AT32F415/at32_dmamux.h b/os/hal/ports/AT32/AT32F415/at32_dmamux.h index a584394b20..e48c61ae2a 100644 --- a/os/hal/ports/AT32/AT32F415/at32_dmamux.h +++ b/os/hal/ports/AT32/AT32F415/at32_dmamux.h @@ -54,7 +54,7 @@ #define AT32_DMAMUX_I2C1_TX 42 #define AT32_DMAMUX_I2C2_RX 43 #define AT32_DMAMUX_I2C2_TX 44 -#define AT32_DMAMUX_SDIO1 49 +#define AT32_DMAMUX_SDIO 49 #define AT32_DMAMUX_TMR1_TRIG 53 #define AT32_DMAMUX_TMR1_HALL 54 #define AT32_DMAMUX_TMR1_OVERFLOW 55 diff --git a/os/hal/ports/AT32/AT32F415/at32_registry.h b/os/hal/ports/AT32/AT32F415/at32_registry.h index 0e0df2792d..2d717fc3ed 100644 --- a/os/hal/ports/AT32/AT32F415/at32_registry.h +++ b/os/hal/ports/AT32/AT32F415/at32_registry.h @@ -142,13 +142,13 @@ #define AT32_HAS_QUADSPI1 FALSE /* SDIO attributes.*/ -#define AT32_HAS_SDIO1 TRUE +#define AT32_HAS_SDIO TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO_DMAMUX_CHANNEL 5 #else -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif /* SPI attributes.*/ @@ -357,13 +357,13 @@ #define AT32_HAS_QUADSPI1 FALSE /* SDIO attributes.*/ -#define AT32_HAS_SDIO1 TRUE +#define AT32_HAS_SDIO TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO_DMAMUX_CHANNEL 5 #else -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif /* SPI attributes.*/ @@ -571,13 +571,13 @@ #define AT32_HAS_QUADSPI1 FALSE /* SDIO attributes.*/ -#define AT32_HAS_SDIO1 TRUE +#define AT32_HAS_SDIO TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO_DMAMUX_CHANNEL 5 #else -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif /* SPI attributes.*/ @@ -796,13 +796,13 @@ #define AT32_HAS_QUADSPI1 FALSE /* SDIO attributes.*/ -#define AT32_HAS_SDIO1 TRUE +#define AT32_HAS_SDIO TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO_DMAMUX_CHANNEL 5 #else -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif /* SPI attributes.*/ @@ -1021,13 +1021,13 @@ #define AT32_HAS_QUADSPI1 FALSE /* SDIO attributes.*/ -#define AT32_HAS_SDIO1 TRUE +#define AT32_HAS_SDIO TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO_DMAMUX_CHANNEL 5 #else -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif /* SPI attributes.*/ @@ -1265,13 +1265,13 @@ #define AT32_HAS_QUADSPI1 FALSE /* SDIO attributes.*/ -#define AT32_HAS_SDIO1 TRUE +#define AT32_HAS_SDIO TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO_DMAMUX_CHANNEL 5 #else -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) +#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif /* SPI attributes.*/ diff --git a/os/hal/ports/AT32/AT32F415/platform.mk b/os/hal/ports/AT32/AT32F415/platform.mk index bf897f7dd7..5605bea088 100644 --- a/os/hal/ports/AT32/AT32F415/platform.mk +++ b/os/hal/ports/AT32/AT32F415/platform.mk @@ -31,6 +31,7 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/GPIOv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/OTGv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/RTCv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SDIOv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SPIv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1/driver.mk diff --git a/os/hal/ports/AT32/LLD/SDIOv1/driver.mk b/os/hal/ports/AT32/LLD/SDIOv1/driver.mk new file mode 100644 index 0000000000..9831504e0d --- /dev/null +++ b/os/hal/ports/AT32/LLD/SDIOv1/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SDIOv1 diff --git a/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c b/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c new file mode 100644 index 0000000000..bb8e1e96b6 --- /dev/null +++ b/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c @@ -0,0 +1,942 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SDIOv1/hal_sdc_lld.c + * @brief AT32 SDC subsystem low level driver source. + * + * @addtogroup SDC + * @{ + */ + +#include + +#include "hal.h" + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/* + * The following definitions are missing from some implementations, fixing + * as zeroed masks. + */ +#if !defined(SDIO_STS_SBITERR) +#define SDIO_STS_SBITERR 0 +#endif + +#if !defined(SDIO_INTCLR_SBITERR) +#define SDIO_INTCLR_SBITERR 0 +#endif + +#if !defined(SDIO_INTEN_SBITERRIEN) +#define SDIO_INTEN_SBITERRIEN 0 +#endif + +#define SDIO_INTCLR_ALL_FLAGS 0xFFFFFFFFU + +#define SDIO_STS_ERROR_MASK \ + (SDIO_STS_CMDFAIL | SDIO_STS_DTFAIL | \ + SDIO_STS_CMDTIMEOUT | SDIO_STS_DTTIMEOUT | \ + SDIO_STS_TXERRU | SDIO_STS_RXERRO) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SDCD1 driver identifier.*/ +SDCDriver SDCD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief SDIO default configuration. + */ +static const SDCConfig sdc_default_cfg = { + SDC_MODE_4BIT, + 0U +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Calculates a clock divider for the specified frequency. + * @note The divider is calculated to not exceed the required frequency + * in case of non-integer division. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] f required frequency + * @return The CLKCTRL value. + */ +static uint32_t sdc_lld_clkdiv(SDCDriver *sdcp, uint32_t f) { + uint32_t div; + +#if defined(AT32_SDC_MAX_CLOCK) + /* Optional enforcement of an arbitrary frequency limit.*/ + if (f > AT32_SDC_MAX_CLOCK) { + f = AT32_SDC_MAX_CLOCK; + } +#endif + + div = sdcp->config->slowdown + ((48000000U + f - 1U) / f); + if (div == 1U) { + return SDIO_CLKCTRL_BYPSEN; + } + + return div - 2U; +} + +/** + * @brief Calculates the value to be put in DTTMR for timeout. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] ms timeout in milliseconds + * @return The DTTMR value. + */ +__STATIC_FORCEINLINE uint32_t sdc_lld_get_timeout(SDCDriver *sdcp, + uint32_t ms) { + uint32_t div, clkctrl; + + clkctrl = sdcp->sdio->CLKCTRL; + if ((clkctrl & SDIO_CLKCTRL_BYPSEN) != 0U) { + div = 1U; + } + else { + div = (clkctrl & SDIO_CLKCTRL_CLKDIV_Msk) + 2U; + } + return (((48000000U / (div * 2U)) / 1000U) * ms); +} + +/** + * @brief Prepares to handle read transaction. + * @details Designed for read special registers from card. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[out] buf pointer to the read buffer + * @param[in] bytes number of bytes to read + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +static bool sdc_lld_prepare_read_bytes(SDCDriver *sdcp, + uint8_t *buf, uint32_t bytes) { + osalDbgCheck(bytes < 0x1000000); + + sdcp->sdio->DTTMR = sdc_lld_get_timeout(sdcp, AT32_SDC_READ_TIMEOUT_MS); + + /* Checks for errors and waits for the card to be ready for reading.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return HAL_FAILED; + + /* Prepares the DMA channel for writing.*/ + dmaStreamSetMemory0(sdcp->dma, buf); + dmaStreamSetTransactionSize(sdcp->dma, bytes / sizeof (uint32_t)); + dmaStreamSetMode(sdcp->dma, sdcp->dmamode | AT32_DMA_CCTRL_DTD_P2M); + dmaStreamEnable(sdcp->dma); + + /* Setting up data transfer.*/ + sdcp->sdio->INTCLR = SDIO_INTCLR_ALL_FLAGS; + sdcp->sdio->INTEN = SDIO_INTEN_DTFAILIEN | + SDIO_INTEN_DTTIMEOUTIEN | + SDIO_INTEN_SBITERRIEN | + SDIO_INTEN_RXERROIEN | + SDIO_INTEN_DTCMPLIEN; + sdcp->sdio->DTLEN = bytes; + + /* Transaction starts just after TFREN bit setting.*/ + sdcp->sdio->DTCTRL = SDIO_DTCTRL_TFRDIR | + SDIO_DTCTRL_TFRMODE | /* Multibyte data transfer.*/ + SDIO_DTCTRL_DMAEN | + SDIO_DTCTRL_TFREN; + + return HAL_SUCCESS; +} + +/** + * @brief Prepares card to handle read transaction. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[in] n number of blocks to read + * @param[in] resp pointer to the response buffer + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +static bool sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk, + uint32_t n, uint32_t *resp) { + + /* Driver handles data in 512 bytes blocks (just like HC cards). But if we + have not HC card than we must convert address from blocks to bytes.*/ + if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) + startblk *= MMCSD_BLOCK_SIZE; + + if (n > 1U) { + /* Send read multiple blocks command to card.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_MULTIPLE_BLOCK, + startblk, resp) || MMCSD_R1_ERROR(resp[0])) { + return HAL_FAILED; + } + } + else { + /* Send read single block command.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_READ_SINGLE_BLOCK, + startblk, resp) || MMCSD_R1_ERROR(resp[0])) { + return HAL_FAILED; + } + } + + return HAL_SUCCESS; +} + +/** + * @brief Prepares card to handle write transaction. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[in] n number of blocks to write + * @param[in] resp pointer to the response buffer + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +static bool sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk, + uint32_t n, uint32_t *resp) { + + /* Driver handles data in 512 bytes blocks (just like HC cards). But if we + have not HC card than we must convert address from blocks to bytes.*/ + if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY)) + startblk *= MMCSD_BLOCK_SIZE; + + if (n > 1U) { + /* Write multiple blocks command.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_MULTIPLE_BLOCK, + startblk, resp) || MMCSD_R1_ERROR(resp[0])) { + return HAL_FAILED; + } + } + else { + /* Write single block command.*/ + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_WRITE_BLOCK, + startblk, resp) || MMCSD_R1_ERROR(resp[0])) { + return HAL_FAILED; + } + } + + return HAL_SUCCESS; +} + +/** + * @brief Wait end of data transaction and performs finalizations. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] n number of blocks in transaction + * @param[in] resp pointer to the response buffer + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + */ +static bool sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n, + uint32_t *resp) { + + /* Note the mask is checked before going to sleep because the interrupt + may have occurred before reaching the critical zone.*/ + osalSysLock(); + + if (sdcp->sdio->INTEN != 0U) { + osalThreadSuspendS(&sdcp->thread); + } + + /* Stopping operations, waiting for transfer completion at DMA level, then + the stream is disabled and cleared.*/ + dmaWaitCompletion(sdcp->dma); + sdcp->sdio->INTEN = 0U; + sdcp->sdio->DTCTRL = 0U; + + if ((sdcp->sdio->STS & SDIO_STS_DTCMPL) == 0) { + osalSysUnlock(); + return HAL_FAILED; + } + + /* Clearing status.*/ + sdcp->sdio->INTCLR = SDIO_INTCLR_ALL_FLAGS; + + osalSysUnlock(); + + /* Finalize transaction.*/ + if (n > 1U) + return sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp); + + return HAL_SUCCESS; +} + +/** + * @brief Gets SDC errors. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] sts value of the STS register + * + * @notapi + */ +static void sdc_lld_collect_errors(SDCDriver *sdcp, uint32_t sts) { + uint32_t errors = SDC_NO_ERROR; + + if (sts & SDIO_STS_CMDFAIL) + errors |= SDC_CMD_CRC_ERROR; + if (sts & SDIO_STS_DTFAIL) + errors |= SDC_DATA_CRC_ERROR; + if (sts & SDIO_STS_CMDTIMEOUT) + errors |= SDC_COMMAND_TIMEOUT; + if (sts & SDIO_STS_DTTIMEOUT) + errors |= SDC_DATA_TIMEOUT; + if (sts & SDIO_STS_TXERRU) + errors |= SDC_TX_UNDERRUN; + if (sts & SDIO_STS_RXERRO) + errors |= SDC_RX_OVERRUN; + if (sts & SDIO_STS_SBITERR) + errors |= SDC_STARTBIT_ERROR; + + sdcp->errors |= errors; +} + +/** + * @brief Performs clean transaction stopping in case of errors. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] n number of blocks in transaction + * @param[in] resp pointer to the response buffer + * + * @notapi + */ +static void sdc_lld_error_cleanup(SDCDriver *sdcp, + uint32_t n, + uint32_t *resp) { + uint32_t sts; + + dmaStreamDisable(sdcp->dma); + + /* Clearing status.*/ + sts = sdcp->sdio->STS; + sdcp->sdio->INTCLR = sts; + sdcp->sdio->DTCTRL = 0U; + sdc_lld_collect_errors(sdcp, sts); + + if (n > 1U) { + sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if !defined(AT32_SDIO_HANDLER) +#error "AT32_SDIO_HANDLER not defined" +#endif +/** + * @brief SDIO IRQ handler. + * @details It just wakes transaction thread, errors handling is performed in + * there. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_SDIO_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + osalSysLockFromISR(); + + /* Disables the source but the status flags are not reset because the + read/write functions needs to check them.*/ + SDIO->INTEN = 0U; + + osalThreadResumeI(&SDCD1.thread, MSG_OK); + + osalSysUnlockFromISR(); + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SDC driver initialization. + * + * @notapi + */ +void sdc_lld_init(void) { + + sdcObjectInit(&SDCD1); + SDCD1.thread = NULL; + SDCD1.dma = NULL; + SDCD1.sdio = SDIO; + nvicEnableVector(AT32_SDIO_NUMBER, AT32_SDC_SDIO_IRQ_PRIORITY); +} + +/** + * @brief Configures and activates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_start(SDCDriver *sdcp) { + + /* Checking configuration, using a default if NULL has been passed.*/ + if (sdcp->config == NULL) { + sdcp->config = &sdc_default_cfg; + } + + sdcp->dmamode = AT32_DMA_CCTRL_CHPL(AT32_SDC_SDIO_DMA_PRIORITY) | + AT32_DMA_CCTRL_PWIDTH_WORD | + AT32_DMA_CCTRL_MWIDTH_WORD | + AT32_DMA_CCTRL_MINCM; + + /* If in stopped state then clocks are enabled and DMA initialized.*/ + if (sdcp->state == BLK_STOP) { + sdcp->dma = dmaStreamAllocI(AT32_SDC_SDIO_DMA_STREAM, + AT32_SDC_SDIO_IRQ_PRIORITY, + NULL, + NULL); + osalDbgAssert(sdcp->dma != NULL, "unable to allocate stream"); + +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(sdcp->dma, AT32_SDC_SDIO_DMAMUX_CHANNEL, AT32_DMAMUX_SDIO); +#endif + + dmaStreamSetPeripheral(sdcp->dma, &sdcp->sdio->BUF); + crmEnableSDIO(true); + } + + /* Configuration, card clock is initially stopped.*/ + sdcp->sdio->PWRCTRL = 0U; + sdcp->sdio->CLKCTRL = 0U; + sdcp->sdio->DTCTRL = 0U; + sdcp->sdio->DTTMR = 0U; + sdcp->sdio->INTCLR = SDIO_INTCLR_ALL_FLAGS; +} + +/** + * @brief Deactivates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop(SDCDriver *sdcp) { + + if (sdcp->state != BLK_STOP) { + + /* SDIO deactivation.*/ + sdcp->sdio->PWRCTRL = 0U; + sdcp->sdio->CLKCTRL = 0U; + sdcp->sdio->DTCTRL = 0U; + sdcp->sdio->DTTMR = 0U; + + /* DMA stream released.*/ + dmaStreamFreeI(sdcp->dma); + sdcp->dma = NULL; + + /* Clock deactivation.*/ + crmDisableSDIO(); + } +} + +/** + * @brief Starts the SDIO clock and sets it to init mode (400kHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_start_clk(SDCDriver *sdcp) { + + /* Initial clock setting: 400kHz, 1bit mode.*/ + sdcp->sdio->CLKCTRL = sdc_lld_clkdiv(sdcp, 400000); + sdcp->sdio->PWRCTRL |= SDIO_PWRCTRL_PS_0 | SDIO_PWRCTRL_PS_1; + sdcp->sdio->CLKCTRL |= SDIO_CLKCTRL_CLKOEN; + + /* Clock activation delay.*/ + osalThreadSleep(OSAL_MS2I(AT32_SDC_CLOCK_ACTIVATION_DELAY)); +} + +/** + * @brief Sets the SDIO clock to data mode (25/50 MHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] clk the clock mode + * + * @notapi + */ +void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) { + + if (SDC_CLK_50MHz == clk) { + sdcp->sdio->CLKCTRL = (sdcp->sdio->CLKCTRL & ~(SDIO_CLKCTRL_BYPSEN_Msk | + SDIO_CLKCTRL_PWRSVEN_Msk | + SDIO_CLKCTRL_CLKDIV_Msk)) | +#if AT32_SDC_SDIO_PWRSVEN + sdc_lld_clkdiv(sdcp, 50000000) | SDIO_CLKCTRL_PWRSVEN; +#else + sdc_lld_clkdiv(sdcp, 50000000); +#endif + } + else { + sdcp->sdio->CLKCTRL = (sdcp->sdio->CLKCTRL & ~(SDIO_CLKCTRL_BYPSEN_Msk | + SDIO_CLKCTRL_PWRSVEN_Msk | + SDIO_CLKCTRL_CLKDIV_Msk)) | +#if AT32_SDC_SDIO_PWRSVEN + sdc_lld_clkdiv(sdcp, 25000000) | SDIO_CLKCTRL_PWRSVEN; +#else + sdc_lld_clkdiv(sdcp, 25000000); +#endif + } +} + +/** + * @brief Stops the SDIO clock. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop_clk(SDCDriver *sdcp) { + + sdcp->sdio->CLKCTRL = 0U; + sdcp->sdio->PWRCTRL = 0U; +} + +/** + * @brief Switches the bus to 1, 4 or 8 bits mode. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] mode bus mode + * + * @notapi + */ +void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { + uint32_t clk = sdcp->sdio->CLKCTRL & ~SDIO_CLKCTRL_BUSWS; + + switch (mode) { + case SDC_MODE_1BIT: + sdcp->sdio->CLKCTRL = clk; + break; + case SDC_MODE_4BIT: + sdcp->sdio->CLKCTRL = clk | SDIO_CLKCTRL_BUSWS_0; + break; + case SDC_MODE_8BIT: + sdcp->sdio->CLKCTRL = clk | SDIO_CLKCTRL_BUSWS_1; + break; + } +} + +/** + * @brief Sends an SDIO command with no response expected. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * + * @notapi + */ +void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { + + sdcp->sdio->ARG = arg; + sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_CCSMEN; + while ((sdcp->sdio->STS & SDIO_STS_CMDCMPL) == 0) + ; + sdcp->sdio->INTCLR = SDIO_INTCLR_CMDCMPL; +} + +/** + * @brief Sends an SDIO command with a short response expected. + * @note The CRC is not verified. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sts; + + sdcp->sdio->ARG = arg; + sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_RSPWT_0 | SDIO_CMD_CCSMEN; + while (((sts = sdcp->sdio->STS) & (SDIO_STS_CMDRSPCMPL | SDIO_STS_CMDTIMEOUT | + SDIO_STS_CMDFAIL)) == 0) + ; + sdcp->sdio->INTCLR = sts & (SDIO_STS_CMDRSPCMPL | SDIO_STS_CMDTIMEOUT | + SDIO_STS_CMDFAIL); + if ((sts & (SDIO_STS_CMDTIMEOUT)) != 0) { + sdc_lld_collect_errors(sdcp, sts); + return HAL_FAILED; + } + *resp = sdcp->sdio->RSP1; + return HAL_SUCCESS; +} + +/** + * @brief Sends an SDIO command with a short response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sts; + + sdcp->sdio->ARG = arg; + sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_RSPWT_0 | SDIO_CMD_CCSMEN; + while (((sts = sdcp->sdio->STS) & (SDIO_STS_CMDRSPCMPL | SDIO_STS_CMDTIMEOUT | + SDIO_STS_CMDFAIL)) == 0) + ; + sdcp->sdio->INTCLR = sts & (SDIO_STS_CMDRSPCMPL | SDIO_STS_CMDTIMEOUT | + SDIO_STS_CMDFAIL); + if ((sts & (SDIO_STS_CMDTIMEOUT | SDIO_STS_CMDFAIL)) != 0) { + sdc_lld_collect_errors(sdcp, sts); + return HAL_FAILED; + } + *resp = sdcp->sdio->RSP1; + return HAL_SUCCESS; +} + +/** + * @brief Sends an SDIO command with a long response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (four words) + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sts; + + (void)sdcp; + + sdcp->sdio->ARG = arg; + sdcp->sdio->CMD = (uint32_t)cmd | SDIO_CMD_RSPWT_0 | SDIO_CMD_RSPWT_1 | + SDIO_CMD_CCSMEN; + while (((sts = sdcp->sdio->STS) & (SDIO_STS_CMDRSPCMPL | SDIO_STS_CMDTIMEOUT | + SDIO_STS_CMDFAIL)) == 0) + ; + sdcp->sdio->INTCLR = sts & (SDIO_STS_CMDRSPCMPL | SDIO_STS_CMDTIMEOUT | + SDIO_STS_CMDFAIL); + if ((sts & (SDIO_STS_ERROR_MASK)) != 0) { + sdc_lld_collect_errors(sdcp, sts); + return HAL_FAILED; + } + /* Save bytes in reverse order because MSB in response comes first.*/ + *resp++ = sdcp->sdio->RSP4; + *resp++ = sdcp->sdio->RSP3; + *resp++ = sdcp->sdio->RSP2; + *resp = sdcp->sdio->RSP1; + return HAL_SUCCESS; +} + +/** + * @brief Reads special registers using data bus. + * @details Needs only during card detection procedure. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[out] buf pointer to the read buffer + * @param[in] bytes number of bytes to read + * @param[in] cmd card command + * @param[in] arg argument for command + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes, + uint8_t cmd, uint32_t arg) { + uint32_t resp[1]; + + if (sdc_lld_prepare_read_bytes(sdcp, buf, bytes)) + goto error; + + if (sdc_lld_send_cmd_short_crc(sdcp, cmd, arg, resp) + || MMCSD_R1_ERROR(resp[0])) + goto error; + + if (sdc_lld_wait_transaction_end(sdcp, 1, resp)) + goto error; + + return HAL_SUCCESS; + +error: + sdc_lld_error_cleanup(sdcp, 1, resp); + return HAL_FAILED; +} + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] blocks number of blocks to read + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +bool sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t blocks) { + uint32_t resp[1]; + + osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE); + + sdcp->sdio->DTTMR = sdc_lld_get_timeout(sdcp, AT32_SDC_READ_TIMEOUT_MS); + + /* Checks for errors and waits for the card to be ready for reading.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return HAL_FAILED; + + /* Prepares the DMA channel for reading.*/ + dmaStreamSetMemory0(sdcp->dma, buf); + dmaStreamSetTransactionSize(sdcp->dma, + (blocks * MMCSD_BLOCK_SIZE) / sizeof (uint32_t)); + dmaStreamSetMode(sdcp->dma, sdcp->dmamode | AT32_DMA_CCTRL_DTD_P2M); + dmaStreamEnable(sdcp->dma); + + /* Setting up data transfer.*/ + sdcp->sdio->INTCLR = SDIO_INTCLR_ALL_FLAGS; + sdcp->sdio->INTEN = SDIO_INTEN_DTFAILIEN | + SDIO_INTEN_DTTIMEOUTIEN | + SDIO_INTEN_SBITERRIEN | + SDIO_INTEN_RXERROIEN | + SDIO_INTEN_DTCMPLIEN; + sdcp->sdio->DTLEN = blocks * MMCSD_BLOCK_SIZE; + + /* Transaction starts just after TFREN bit setting.*/ + sdcp->sdio->DTCTRL = SDIO_DTCTRL_TFRDIR | + SDIO_DTCTRL_BLKSIZE_3 | + SDIO_DTCTRL_BLKSIZE_0 | + SDIO_DTCTRL_DMAEN | + SDIO_DTCTRL_TFREN; + + if (sdc_lld_prepare_read(sdcp, startblk, blocks, resp) == true) + goto error; + + if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == true) + goto error; + + return HAL_SUCCESS; + +error: + sdc_lld_error_cleanup(sdcp, blocks, resp); + return HAL_FAILED; +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] n number of blocks to write + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +bool sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t blocks) { + uint32_t resp[1]; + + osalDbgCheck(blocks < 0x1000000 / MMCSD_BLOCK_SIZE); + + sdcp->sdio->DTTMR = sdc_lld_get_timeout(sdcp, AT32_SDC_WRITE_TIMEOUT_MS); + + /* Checks for errors and waits for the card to be ready for writing.*/ + if (_sdc_wait_for_transfer_state(sdcp)) + return HAL_FAILED; + + /* Prepares the DMA channel for writing.*/ + dmaStreamSetMemory0(sdcp->dma, buf); + dmaStreamSetTransactionSize(sdcp->dma, + (blocks * MMCSD_BLOCK_SIZE) / sizeof (uint32_t)); + dmaStreamSetMode(sdcp->dma, sdcp->dmamode | AT32_DMA_CCTRL_DTD_M2P); + dmaStreamEnable(sdcp->dma); + + /* Setting up data transfer.*/ + sdcp->sdio->INTCLR = SDIO_INTCLR_ALL_FLAGS; + sdcp->sdio->INTEN = SDIO_INTEN_DTFAILIEN | + SDIO_INTEN_DTTIMEOUTIEN | + SDIO_INTEN_SBITERRIEN | + SDIO_INTEN_TXERRUIEN | + SDIO_INTEN_DTCMPLIEN; + sdcp->sdio->DTLEN = blocks * MMCSD_BLOCK_SIZE; + + /* Talk to card what we want from it.*/ + if (sdc_lld_prepare_write(sdcp, startblk, blocks, resp) == true) + goto error; + + /* Transaction starts just after TFREN bit setting.*/ + sdcp->sdio->DTCTRL = SDIO_DTCTRL_BLKSIZE_3 | + SDIO_DTCTRL_BLKSIZE_0 | + SDIO_DTCTRL_DMAEN | + SDIO_DTCTRL_TFREN; + + if (sdc_lld_wait_transaction_end(sdcp, blocks, resp) == true) + goto error; + + return HAL_SUCCESS; + +error: + sdc_lld_error_cleanup(sdcp, blocks, resp); + return HAL_FAILED; +} + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] blocks number of blocks to read + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t blocks) { + +#if AT32_SDC_SDIO_UNALIGNED_SUPPORT + if (((unsigned)buf & 3U) != 0U) { + uint32_t i; + for (i = 0U; i < blocks; i++) { + if (sdc_lld_read_aligned(sdcp, startblk, sdcp->buf, 1)) { + return HAL_FAILED; + } + memcpy(buf, sdcp->buf, MMCSD_BLOCK_SIZE); + buf += MMCSD_BLOCK_SIZE; + startblk++; + } + return HAL_SUCCESS; + } +#else /* !AT32_SDC_SDIO_UNALIGNED_SUPPORT */ + osalDbgAssert((((unsigned)buf & 3U) == 0U), "unaligned buffer"); +#endif /* !AT32_SDC_SDIO_UNALIGNED_SUPPORT */ + return sdc_lld_read_aligned(sdcp, startblk, buf, blocks); +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] blocks number of blocks to write + * + * @return The operation status. + * @retval HAL_SUCCESS operation succeeded. + * @retval HAL_FAILED operation failed. + * + * @notapi + */ +bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t blocks) { + +#if AT32_SDC_SDIO_UNALIGNED_SUPPORT + if (((unsigned)buf & 3U) != 0U) { + uint32_t i; + for (i = 0U; i < blocks; i++) { + memcpy(sdcp->buf, buf, MMCSD_BLOCK_SIZE); + buf += MMCSD_BLOCK_SIZE; + if (sdc_lld_write_aligned(sdcp, startblk, sdcp->buf, 1)) + return HAL_FAILED; + startblk++; + } + return HAL_SUCCESS; + } +#else /* !AT32_SDC_SDIO_UNALIGNED_SUPPORT */ + osalDbgAssert((((unsigned)buf & 3U) == 0U), "unaligned buffer"); +#endif /* !AT32_SDC_SDIO_UNALIGNED_SUPPORT */ + return sdc_lld_write_aligned(sdcp, startblk, buf, blocks); +} + +/** + * @brief Waits for card idle condition. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @return The operation status. + * @retval HAL_SUCCESS the operation succeeded. + * @retval HAL_FAILED the operation failed. + * + * @api + */ +bool sdc_lld_sync(SDCDriver *sdcp) { + + /* CHTODO: Implement.*/ + (void)sdcp; + return HAL_SUCCESS; +} + +#endif /* HAL_USE_SDC */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.h b/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.h new file mode 100644 index 0000000000..9fb52e2ec1 --- /dev/null +++ b/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.h @@ -0,0 +1,274 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SDIOv1/hal_sdc_lld.h + * @brief AT32 SDC subsystem low level driver header. + * + * @addtogroup SDC + * @{ + */ + +#ifndef HAL_SDC_LLD_H +#define HAL_SDC_LLD_H + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SDIO DMA priority (0..3|lowest..highest). + */ +#if !defined(AT32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SDC_SDIO_DMA_PRIORITY 3 +#endif + +/** + * @brief SDIO interrupt priority level setting. + */ +#if !defined(AT32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SDC_SDIO_IRQ_PRIORITY 9 +#endif + +/** + * @brief Write timeout in milliseconds. + */ +#if !defined(AT32_SDC_WRITE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define AT32_SDC_WRITE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Read timeout in milliseconds. + */ +#if !defined(AT32_SDC_READ_TIMEOUT_MS) || defined(__DOXYGEN__) +#define AT32_SDC_READ_TIMEOUT_MS 1000 +#endif + +/** + * @brief Card clock power saving enable. + */ +#if !defined(AT32_SDC_SDIO_PWRSVEN) || defined(__DOXYGEN__) +#define AT32_SDC_SDIO_PWRSVEN FALSE +#endif + +/** + * @brief Card clock activation delay in milliseconds. + */ +#if !defined(AT32_SDC_CLOCK_ACTIVATION_DELAY) || defined(__DOXYGEN__) +#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 +#endif + +/** + * @brief Support for unaligned transfers. + * @note Unaligned transfers are much slower. + */ +#if !defined(AT32_SDC_SDIO_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) +#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !AT32_HAS_SDIO +#error "SDIO not present in the selected device" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SDC_SDIO_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDIO" +#endif + +#if !AT32_DMA_IS_VALID_PRIORITY(AT32_SDC_SDIO_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SDIO" +#endif + +#if !defined(AT32_DMA_REQUIRED) +#define AT32_DMA_REQUIRED +#endif + +/* + * SDIO clock divider. + */ +#if AT32_HCLK > 48000000 +#define AT32_SDIO_DIV_HS 1 +#define AT32_SDIO_DIV_LS 178 +#else + +#define AT32_SDIO_DIV_HS 0 +#define AT32_SDIO_DIV_LS 118 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of card flags. + */ +typedef uint32_t sdcmode_t; + +/** + * @brief SDC Driver condition flags type. + */ +typedef uint32_t sdcflags_t; + +/** + * @brief Type of a structure representing an SDC driver. + */ +typedef struct SDCDriver SDCDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Bus width. + */ + sdcbusmode_t bus_width; + /* End of the mandatory fields.*/ + /** + * @brief Bus slowdown. + * @note This values is added to the prescaler register in order to + * arbitrarily reduce clock speed. + */ + uint32_t slowdown; +} SDCConfig; + +/** + * @brief @p SDCDriver specific methods. + */ +#define _sdc_driver_methods \ + _mmcsd_block_device_methods + +/** + * @extends MMCSDBlockDeviceVMT + * + * @brief @p SDCDriver virtual methods table. + */ +struct SDCDriverVMT { + _sdc_driver_methods +}; + +/** + * @brief Structure representing an SDC driver. + */ +struct SDCDriver { + /** + * @brief Virtual Methods Table. + */ + const struct SDCDriverVMT *vmt; + _mmcsd_block_device_data + /** + * @brief Current configuration data. + */ + const SDCConfig *config; + /** + * @brief Various flags regarding the mounted card. + */ + sdcmode_t cardmode; + /** + * @brief Errors flags. + */ + sdcflags_t errors; + /** + * @brief Card RCA. + */ + uint32_t rca; + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion IRQ. + */ + thread_reference_t thread; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief Transmit DMA channel. + */ + const at32_dma_stream_t *dma; + /** + * @brief Pointer to the SDIO registers block. + * @note Needed for debugging aid. + */ + SDIO_TypeDef *sdio; + /** + * @brief Buffer for internal operations. + */ + uint8_t buf[MMCSD_BLOCK_SIZE]; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern SDCDriver SDCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sdc_lld_init(void); + void sdc_lld_start(SDCDriver *sdcp); + void sdc_lld_stop(SDCDriver *sdcp); + void sdc_lld_start_clk(SDCDriver *sdcp); + void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk); + void sdc_lld_stop_clk(SDCDriver *sdcp); + void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); + void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); + bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes, + uint8_t cmd, uint32_t argument); + bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t blocks); + bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t blocks); + bool sdc_lld_sync(SDCDriver *sdcp); + bool sdc_lld_is_card_inserted(SDCDriver *sdcp); + bool sdc_lld_is_write_protected(SDCDriver *sdcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SDC */ + +#endif /* HAL_SDC_LLD_H */ + +/** @} */ From d839f5d16e5c6753502bf7d0af6133d9b1a05f10 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Sun, 11 Aug 2024 14:26:53 +0700 Subject: [PATCH 18/18] Update mcuconf for all the test and demo files. Added new test for SDIO LLD driver. --- demos/AT32/RT-AT-START-F415/cfg/mcuconf.h | 14 +- .../multi/ERTC/cfg/at-start-f415/mcuconf.h | 10 + .../multi/I2C_HW/cfg/at-start-f415/mcuconf.h | 10 + .../multi/I2C_SW/cfg/at-start-f415/mcuconf.h | 10 + .../multi/PWM_ICU/cfg/at-start-f415/mcuconf.h | 10 + testhal/AT32/multi/SDC/.cproject | 56 ++ testhal/AT32/multi/SDC/.project | 78 ++ testhal/AT32/multi/SDC/Makefile | 18 + .../AT32/multi/SDC/cfg/at-start-f415/chconf.h | 842 ++++++++++++++++++ .../AT32/multi/SDC/cfg/at-start-f415/config.h | 30 + .../multi/SDC/cfg/at-start-f415/halconf.h | 555 ++++++++++++ .../multi/SDC/cfg/at-start-f415/mcuconf.h | 238 +++++ .../AT32/multi/SDC/cfg/at-start-f415/portab.c | 67 ++ .../AT32/multi/SDC/cfg/at-start-f415/portab.h | 80 ++ testhal/AT32/multi/SDC/main.c | 344 +++++++ .../AT32/multi/SDC/make/at-start-f415.make | 198 ++++ .../multi/UART/cfg/at-start-f415/mcuconf.h | 10 + .../multi/USB_CDC/cfg/at-start-f415/mcuconf.h | 10 + .../multi/WDT/cfg/at-start-f415/mcuconf.h | 10 + 19 files changed, 2588 insertions(+), 2 deletions(-) create mode 100644 testhal/AT32/multi/SDC/.cproject create mode 100644 testhal/AT32/multi/SDC/.project create mode 100644 testhal/AT32/multi/SDC/Makefile create mode 100644 testhal/AT32/multi/SDC/cfg/at-start-f415/chconf.h create mode 100644 testhal/AT32/multi/SDC/cfg/at-start-f415/config.h create mode 100644 testhal/AT32/multi/SDC/cfg/at-start-f415/halconf.h create mode 100644 testhal/AT32/multi/SDC/cfg/at-start-f415/mcuconf.h create mode 100644 testhal/AT32/multi/SDC/cfg/at-start-f415/portab.c create mode 100644 testhal/AT32/multi/SDC/cfg/at-start-f415/portab.h create mode 100644 testhal/AT32/multi/SDC/main.c create mode 100644 testhal/AT32/multi/SDC/make/at-start-f415.make diff --git a/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h b/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h index 4941f5a669..5afedd79a1 100644 --- a/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h +++ b/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h @@ -35,8 +35,6 @@ #define AT32F415_MCUCONF -#include "config.h" - /* * General settings. */ @@ -176,6 +174,16 @@ #define AT32_ERTC_CTRL_INIT 0 #define AT32_ERTC_TAMP_INIT 0 +/* + * SDC driver system settings. + */ +#define AT32_SDC_SDIO_DMA_PRIORITY 3 +#define AT32_SDC_SDIO_IRQ_PRIORITY 9 +#define AT32_SDC_WRITE_TIMEOUT_MS 1000 +#define AT32_SDC_READ_TIMEOUT_MS 1000 +#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE + /* * SERIAL driver system settings. */ @@ -225,4 +233,6 @@ */ #define AT32_WDG_USE_WDT FALSE +#include "config.h" + #endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h index d3da1f31a6..940b0f6580 100644 --- a/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h @@ -174,6 +174,16 @@ #define AT32_ERTC_CTRL_INIT 0 #define AT32_ERTC_TAMP_INIT 0 +/* + * SDC driver system settings. + */ +#define AT32_SDC_SDIO_DMA_PRIORITY 3 +#define AT32_SDC_SDIO_IRQ_PRIORITY 9 +#define AT32_SDC_WRITE_TIMEOUT_MS 1000 +#define AT32_SDC_READ_TIMEOUT_MS 1000 +#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE + /* * SERIAL driver system settings. */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h index b218c904c4..43da949f1a 100644 --- a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h @@ -174,6 +174,16 @@ #define AT32_ERTC_CTRL_INIT 0 #define AT32_ERTC_TAMP_INIT 0 +/* + * SDC driver system settings. + */ +#define AT32_SDC_SDIO_DMA_PRIORITY 3 +#define AT32_SDC_SDIO_IRQ_PRIORITY 9 +#define AT32_SDC_WRITE_TIMEOUT_MS 1000 +#define AT32_SDC_READ_TIMEOUT_MS 1000 +#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE + /* * SERIAL driver system settings. */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h index 4a4ddf6445..f7b4fbfe68 100644 --- a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h @@ -174,6 +174,16 @@ #define AT32_ERTC_CTRL_INIT 0 #define AT32_ERTC_TAMP_INIT 0 +/* + * SDC driver system settings. + */ +#define AT32_SDC_SDIO_DMA_PRIORITY 3 +#define AT32_SDC_SDIO_IRQ_PRIORITY 9 +#define AT32_SDC_WRITE_TIMEOUT_MS 1000 +#define AT32_SDC_READ_TIMEOUT_MS 1000 +#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE + /* * SERIAL driver system settings. */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h index 323cb23b98..ae61f32b63 100644 --- a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h @@ -174,6 +174,16 @@ #define AT32_ERTC_CTRL_INIT 0 #define AT32_ERTC_TAMP_INIT 0 +/* + * SDC driver system settings. + */ +#define AT32_SDC_SDIO_DMA_PRIORITY 3 +#define AT32_SDC_SDIO_IRQ_PRIORITY 9 +#define AT32_SDC_WRITE_TIMEOUT_MS 1000 +#define AT32_SDC_READ_TIMEOUT_MS 1000 +#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE + /* * SERIAL driver system settings. */ diff --git a/testhal/AT32/multi/SDC/.cproject b/testhal/AT32/multi/SDC/.cproject new file mode 100644 index 0000000000..74701160a0 --- /dev/null +++ b/testhal/AT32/multi/SDC/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/multi/SDC/.project b/testhal/AT32/multi/SDC/.project new file mode 100644 index 0000000000..c6e985d99b --- /dev/null +++ b/testhal/AT32/multi/SDC/.project @@ -0,0 +1,78 @@ + + + AT32-SDC + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/testhal/AT32/multi/SDC/Makefile b/testhal/AT32/multi/SDC/Makefile new file mode 100644 index 0000000000..c8606df05e --- /dev/null +++ b/testhal/AT32/multi/SDC/Makefile @@ -0,0 +1,18 @@ +############################################################################## +# Multi-project makefile rules +# + +all: + @echo + @echo === Building for AT-START-F415 ===================================== + +@make --no-print-directory -f ./make/at-start-f415.make all + @echo ==================================================================== + @echo + +clean: + @echo + +@make --no-print-directory -f ./make/at-start-f415.make clean + @echo + +# +############################################################################## diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/chconf.h new file mode 100644 index 0000000000..46b3f78b68 --- /dev/null +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/config.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/config.h new file mode 100644 index 0000000000..4fbd7cc3df --- /dev/null +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/config.h @@ -0,0 +1,30 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf.h new file mode 100644 index 0000000000..73c9e36b48 --- /dev/null +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf.h @@ -0,0 +1,555 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/mcuconf.h new file mode 100644 index 0000000000..5afedd79a1 --- /dev/null +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/mcuconf.h @@ -0,0 +1,238 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F415 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F415_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 +#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID +#define AT32_PLLMULT_VALUE 18 +#define AT32_PLL_FR_VALUE 4 +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV2 +#define AT32_ADCDIV AT32_ADCDIV_DIV4 +#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_USBDIV AT32_USBDIV_DIV3 +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK +#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT19_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR5_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DMA driver system settings. + */ +#define AT32_DMA_USE_DMAMUX FALSE + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR5 FALSE +#define AT32_ICU_USE_TMR9 FALSE +#define AT32_ICU_USE_TMR10 FALSE +#define AT32_ICU_USE_TMR11 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR5 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SDC driver system settings. + */ +#define AT32_SDC_SDIO_DMA_PRIORITY 3 +#define AT32_SDC_SDIO_IRQ_PRIORITY 9 +#define AT32_SDC_WRITE_TIMEOUT_MS 1000 +#define AT32_SDC_READ_TIMEOUT_MS 1000 +#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 TRUE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.c b/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.c new file mode 100644 index 0000000000..0e6bc7d6a1 --- /dev/null +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.c @@ -0,0 +1,67 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/* + * SDIO configuration. + */ +SDCConfig sdccfg = { + .bus_width = SDC_MODE_1BIT, + .slowdown = 0U +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.h new file mode 100644 index 0000000000..0c5d89d14e --- /dev/null +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.h @@ -0,0 +1,80 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_SDC1 SDCD1 + +#define PORTAB_SD1 SD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern SDCConfig sdccfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SDC/main.c b/testhal/AT32/multi/SDC/main.c new file mode 100644 index 0000000000..c997f2fdc3 --- /dev/null +++ b/testhal/AT32/multi/SDC/main.c @@ -0,0 +1,344 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2024 HorrorTroll + ChibiOS - Copyright (C) 2023..2024 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include + +#include "ch.h" +#include "hal.h" + +#include "shell.h" +#include "chprintf.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) + +#define SDC_BURST_SIZE 16 + +/* Buffer for block read/write operations, note that extra bytes are + allocated in order to support unaligned operations.*/ +static uint8_t buf[MMCSD_BLOCK_SIZE * SDC_BURST_SIZE + 4]; + +/* Additional buffer for sdcErase() test */ +static uint8_t buf2[MMCSD_BLOCK_SIZE * SDC_BURST_SIZE ]; + +void cmd_sdc(BaseSequentialStream *chp, int argc, char *argv[]) { + static const char *mode[] = {"SDV11", "SDV20", "MMC", NULL}; + systime_t start, end; + uint32_t n, startblk; + + if (argc != 1) { + chprintf(chp, "Usage: sdc read|write|erase|all\r\n"); + return; + } + + /* Card presence check.*/ + if (!blkIsInserted(&PORTAB_SDC1)) { + chprintf(chp, "Card not inserted, aborting.\r\n"); + return; + } + + /* Connection to the card.*/ + chprintf(chp, "Connecting... "); + if (sdcConnect(&PORTAB_SDC1)) { + chprintf(chp, "failed\r\n"); + return; + } + + chprintf(chp, "OK\r\n\r\nCard Info\r\n"); + chprintf(chp, "CSD : %08X %8X %08X %08X \r\n", + PORTAB_SDC1.csd[3], PORTAB_SDC1.csd[2], PORTAB_SDC1.csd[1], PORTAB_SDC1.csd[0]); + chprintf(chp, "CID : %08X %8X %08X %08X \r\n", + PORTAB_SDC1.cid[3], PORTAB_SDC1.cid[2], PORTAB_SDC1.cid[1], PORTAB_SDC1.cid[0]); + chprintf(chp, "Mode : %s\r\n", mode[PORTAB_SDC1.cardmode & 3U]); + chprintf(chp, "Capacity : %DMB\r\n", PORTAB_SDC1.capacity / 2048); + + /* The test is performed in the middle of the flash area.*/ + startblk = (PORTAB_SDC1.capacity / MMCSD_BLOCK_SIZE) / 2; + + if ((strcmp(argv[0], "read") == 0) || + (strcmp(argv[0], "all") == 0)) { + + /* Single block read performance, aligned.*/ + chprintf(chp, "Single block aligned read performance: "); + start = chVTGetSystemTime(); + end = chTimeAddX(start, TIME_MS2I(1000)); + n = 0; + do { + if (blkRead(&PORTAB_SDC1, startblk, buf, 1)) { + chprintf(chp, "failed\r\n"); + goto exittest; + } + n++; + } while (chVTIsSystemTimeWithin(start, end)); + chprintf(chp, "%D blocks/S, %D bytes/S\r\n", n, n * MMCSD_BLOCK_SIZE); + + /* Multiple sequential blocks read performance, aligned.*/ + chprintf(chp, "16 sequential blocks aligned read performance: "); + start = chVTGetSystemTime(); + end = chTimeAddX(start, TIME_MS2I(1000)); + n = 0; + do { + if (blkRead(&PORTAB_SDC1, startblk, buf, SDC_BURST_SIZE)) { + chprintf(chp, "failed\r\n"); + goto exittest; + } + n += SDC_BURST_SIZE; + } while (chVTIsSystemTimeWithin(start, end)); + chprintf(chp, "%D blocks/S, %D bytes/S\r\n", n, n * MMCSD_BLOCK_SIZE); + +#if AT32_SDC_SDIO_UNALIGNED_SUPPORT + /* Single block read performance, unaligned.*/ + chprintf(chp, "Single block unaligned read performance: "); + start = chVTGetSystemTime(); + end = chTimeAddX(start, TIME_MS2I(1000)); + n = 0; + do { + if (blkRead(&PORTAB_SDC1, startblk, buf + 1, 1)) { + chprintf(chp, "failed\r\n"); + goto exittest; + } + n++; + } while (chVTIsSystemTimeWithin(start, end)); + chprintf(chp, "%D blocks/S, %D bytes/S\r\n", n, n * MMCSD_BLOCK_SIZE); + + /* Multiple sequential blocks read performance, unaligned.*/ + chprintf(chp, "16 sequential blocks unaligned read performance: "); + start = chVTGetSystemTime(); + end = chTimeAddX(start, TIME_MS2I(1000)); + n = 0; + do { + if (blkRead(&PORTAB_SDC1, startblk, buf + 1, SDC_BURST_SIZE)) { + chprintf(chp, "failed\r\n"); + goto exittest; + } + n += SDC_BURST_SIZE; + } while (chVTIsSystemTimeWithin(start, end)); + chprintf(chp, "%D blocks/S, %D bytes/S\r\n", n, n * MMCSD_BLOCK_SIZE); +#endif /* AT32_SDC_SDIO_UNALIGNED_SUPPORT */ + } + + if ((strcmp(argv[0], "write") == 0) || + (strcmp(argv[0], "all") == 0)) { + unsigned i; + + memset(buf, 0xAA, MMCSD_BLOCK_SIZE * 2); + chprintf(chp, "Writing..."); + if(sdcWrite(&PORTAB_SDC1, startblk, buf, 2)) { + chprintf(chp, "failed\r\n"); + goto exittest; + } + chprintf(chp, "OK\r\n"); + + memset(buf, 0x55, MMCSD_BLOCK_SIZE * 2); + chprintf(chp, "Reading..."); + if (blkRead(&PORTAB_SDC1, startblk, buf, 1)) { + chprintf(chp, "failed\r\n"); + goto exittest; + } + chprintf(chp, "OK\r\n"); + + for (i = 0; i < MMCSD_BLOCK_SIZE; i++) + buf[i] = i + 8; + chprintf(chp, "Writing..."); + if(sdcWrite(&PORTAB_SDC1, startblk, buf, 2)) { + chprintf(chp, "failed\r\n"); + goto exittest; + } + chprintf(chp, "OK\r\n"); + + memset(buf, 0, MMCSD_BLOCK_SIZE * 2); + chprintf(chp, "Reading..."); + if (blkRead(&PORTAB_SDC1, startblk, buf, 1)) { + chprintf(chp, "failed\r\n"); + goto exittest; + } + chprintf(chp, "OK\r\n"); + } + + if ((strcmp(argv[0], "erase") == 0) || + (strcmp(argv[0], "all") == 0)) { + /** + * Test sdcErase() + * Strategy: + * 1. Fill two blocks with non-constant data + * 2. Write two blocks starting at startblk + * 3. Erase the second of the two blocks + * 3.1. First block should be equal to the data written + * 3.2. Second block should NOT be equal too the data written (i.e. erased). + * 4. Erase both first and second block + * 4.1 Both blocks should not be equal to the data initially written + * Precondition: SDC_BURST_SIZE >= 2 + */ + memset(buf, 0, MMCSD_BLOCK_SIZE * 2); + memset(buf2, 0, MMCSD_BLOCK_SIZE * 2); + /* 1. */ + unsigned int i = 0; + for (; i < MMCSD_BLOCK_SIZE * 2; ++i) { + buf[i] = (i + 7) % 'T'; //Ensure block 1/2 are not equal + } + /* 2. */ + if(sdcWrite(&PORTAB_SDC1, startblk, buf, 2)) { + chprintf(chp, "sdcErase() test write failed\r\n"); + goto exittest; + } + /* 3. (erase) */ + if(sdcErase(&PORTAB_SDC1, startblk + 1, startblk + 2)) { + chprintf(chp, "sdcErase() failed\r\n"); + goto exittest; + } + sdcflags_t errflags = sdcGetAndClearErrors(&PORTAB_SDC1); + if(errflags) { + chprintf(chp, "sdcErase() yielded error flags: %d\r\n", errflags); + goto exittest; + } + if(sdcRead(&PORTAB_SDC1, startblk, buf2, 2)) { + chprintf(chp, "single-block sdcErase() failed\r\n"); + goto exittest; + } + /* 3.1. */ + if(memcmp(buf, buf2, MMCSD_BLOCK_SIZE) != 0) { + chprintf(chp, "sdcErase() non-erased block compare failed\r\n"); + goto exittest; + } + /* 3.2. */ + if(memcmp(buf + MMCSD_BLOCK_SIZE, + buf2 + MMCSD_BLOCK_SIZE, MMCSD_BLOCK_SIZE) == 0) { + chprintf(chp, "sdcErase() erased block compare failed\r\n"); + goto exittest; + } + /* 4. */ + if(sdcErase(&PORTAB_SDC1, startblk, startblk + 2)) { + chprintf(chp, "multi-block sdcErase() failed\r\n"); + goto exittest; + } + if(sdcRead(&PORTAB_SDC1, startblk, buf2, 2)) { + chprintf(chp, "single-block sdcErase() failed\r\n"); + goto exittest; + } + /* 4.1 */ + if(memcmp(buf, buf2, MMCSD_BLOCK_SIZE) == 0) { + chprintf(chp, "multi-block sdcErase() erased block compare failed\r\n"); + goto exittest; + } + if(memcmp(buf + MMCSD_BLOCK_SIZE, + buf2 + MMCSD_BLOCK_SIZE, MMCSD_BLOCK_SIZE) == 0) { + chprintf(chp, "multi-block sdcErase() erased block compare failed\r\n"); + goto exittest; + } + /* END of sdcErase() test */ + } + + /* Card disconnect and command end.*/ +exittest: + sdcDisconnect(&PORTAB_SDC1); +} + +static const ShellCommand commands[] = { + {"sdc", cmd_sdc}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&PORTAB_SD1, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + palSetLine(PORTAB_BLINK_LED1); + chThdSleepMilliseconds(500); + palSetLine(PORTAB_BLINK_LED2); + chThdSleepMilliseconds(500); + palSetLine(PORTAB_BLINK_LED3); + chThdSleepMilliseconds(500); + palClearLine(PORTAB_BLINK_LED1); + chThdSleepMilliseconds(500); + palClearLine(PORTAB_BLINK_LED2); + chThdSleepMilliseconds(500); + palClearLine(PORTAB_BLINK_LED3); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Board-dependent setup code. + */ + portab_setup(); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Activates the serial driver 6 using the driver default configuration. + */ + sdStart(&PORTAB_SD1, NULL); + + /* + * Initializes the SDIO drivers. + */ + sdcStart(&PORTAB_SDC1, &sdccfg); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, spawning shells. + */ + while (true) { + thread_t *shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, + "shell", NORMALPRIO + 1, + shellThread, (void *)&shell_cfg1); + chThdWait(shelltp); /* Waiting termination. */ + chThdSleepMilliseconds(1000); + } +} diff --git a/testhal/AT32/multi/SDC/make/at-start-f415.make b/testhal/AT32/multi/SDC/make/at-start-f415.make new file mode 100644 index 0000000000..8e280f39d9 --- /dev/null +++ b/testhal/AT32/multi/SDC/make/at-start-f415.make @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f415 +BUILDDIR := ./build/at-start-f415 +DEPDIR := ./.dep/at-start-f415 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f415.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F415/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F415/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F415xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h index 8c64a6aea4..9e311dd92f 100644 --- a/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h @@ -174,6 +174,16 @@ #define AT32_ERTC_CTRL_INIT 0 #define AT32_ERTC_TAMP_INIT 0 +/* + * SDC driver system settings. + */ +#define AT32_SDC_SDIO_DMA_PRIORITY 3 +#define AT32_SDC_SDIO_IRQ_PRIORITY 9 +#define AT32_SDC_WRITE_TIMEOUT_MS 1000 +#define AT32_SDC_READ_TIMEOUT_MS 1000 +#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE + /* * SERIAL driver system settings. */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h index 5257a8ca60..a827f2815f 100644 --- a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h @@ -174,6 +174,16 @@ #define AT32_ERTC_CTRL_INIT 0 #define AT32_ERTC_TAMP_INIT 0 +/* + * SDC driver system settings. + */ +#define AT32_SDC_SDIO_DMA_PRIORITY 3 +#define AT32_SDC_SDIO_IRQ_PRIORITY 9 +#define AT32_SDC_WRITE_TIMEOUT_MS 1000 +#define AT32_SDC_READ_TIMEOUT_MS 1000 +#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE + /* * SERIAL driver system settings. */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h index d1646fa57a..ce6f302b38 100644 --- a/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h @@ -174,6 +174,16 @@ #define AT32_ERTC_CTRL_INIT 0 #define AT32_ERTC_TAMP_INIT 0 +/* + * SDC driver system settings. + */ +#define AT32_SDC_SDIO_DMA_PRIORITY 3 +#define AT32_SDC_SDIO_IRQ_PRIORITY 9 +#define AT32_SDC_WRITE_TIMEOUT_MS 1000 +#define AT32_SDC_READ_TIMEOUT_MS 1000 +#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE + /* * SERIAL driver system settings. */